beta_test.uasm

// see if it's *really* a Beta or only just pretending...

// This code makes the following assumptions about the Beta design:
//   after reset, the Beta starts executing at location 0
//   illegal instructions cause a trap to location 4
//   interrupts cause a trap to location 8

// If this program completes successfully, it enters a two-instruction
// loop at locations 0x5EC and 0x5F0.  It reaches 0x3C4 for the first
// time on cycle 270.

// If this program detects an error, it enters a two-instruction loop at
// locations 0x00C and 0x010 with an error code in R0.  The instruction
// at 0x00C is ADDC(R0,0,R31) so it is usually possible to use the
// waveform browser in the simulator to display the error code.

// possible error codes in R0:
//  4: BEQ(R31,...) didn't branch
//  5: BNE(R31,...) did branch

//  6: CMPEQC(R31,0,R0) failed
//  7: CMPLEC(R31,0,R0) failed
//  8: CMPLTC(R31,1,R0) failed
//  9: CMPEQC(R31,-1,R0) failed
//  10: CMPLEC(R31,-1,R0) failed
//  11: CMPLTC(R31,-1,R0) failed
//  12: didn't generate 0x8000000 or 0x7FFFFFFF correctly (see code)
//  13: 0x8000000 <= 0x7FFFFFF failed
//  14: 0x7FFFFFF <= 0x80000000 failed

//  15 - 47: some op/opc instruction failed
//  48: ADDC(R31,31,R31) changed the value of R31!

//  50: JMP executed following instruction
//  51: JMP didn't fill LP correctly

//  52: LDR failed or 0xAAAAAAAA + 0x55555555 != 1
//  53: 0xAAAAAAAA + 0xAAAAAAAA != 0x55555554
//  54: 0x55555555 + 0x55555555 != 0xAAAAAAAA
//  55: 1 - 1 != 0 (carry propagation test)

//  56: 0x0F0F & 0x7F00 != 0x0F00
//  57: 0x0F0F // 0x7F00 != 0x7F0F
//  58: 0x0F0F ^ 0x7F00 != 0x700F
//  59: ~(0x0F0F ^ 0x7F00) != 0xFFFF8FF0

//  60: 1 << 32 != 1
//  61: (1 << 31) >>signed 17 != 0xFFFFC000
//  62: (1 << 31) >>unsigned 17 != 0x00004000

//  63: XP not filled correctly on illegal op trap
//  64: expected 7 illops: 08, 1A, 1E, 27, 2F, 37, 3F

//  65: load or store failure
//  66: load or store failure
//  67: load or store failure
//  68: load or store failure

//  69: alu-bypass failure
//  70: pc-bypass failure

//  71: interrupt didn't happen on correct cycle
//  72: XP not filled correctly on interrupt
//  73: ensure JMP can't go from user mode to supervisor mode
//  74: test Beta's Z logic

.include "beta.uasm"

.macro FAIL_T(RA,TEST) { BF(RA,.+12) ADDC(R31,TEST,R0) BR(Error) }
.macro FAIL_F(RA,TEST) { BT(RA,.+12) ADDC(R31,TEST,R0) BR(Error) }

. = 0

// here on reset

        BEQ(R31,Start,XP)               // should branch
error1 = .

// here on illegal instructions or if BEQ above didn't work

        BR(IllInst)

// here on interrupts

        JMP(XP)                 // return from interrupt (don't adjust XP!)

// here when we've found an error

Error:
        ADDC(R0,0,R31)                  // put error code on result bus
        BR(Error)                       // loop (or least try to!)

// handler for illegal instructions
IllInst:
        CMPEQC(XP,error1,R0)            // did the first instruction fail?
        BF(R0,Ill_1)                    // nope, do regular processing
        MOVE(XP,R0)                     // yup, branch to error handler
        BR(Error)

Ill_1:  ADDC(R1,1,R1)                   // update count
        JMP(XP)                         // return to user...

// okay, now for some real tests...
Start:
test5:
        FAIL_T(R31,5)                   // shouldn't branch

        // test simple comparisons
test6:
        CMPEQC(R31,0,R0)
        FAIL_F(R0,6)
test7:
        CMPLEC(R31,0,R0)
        FAIL_F(R0,7)
test8:
        CMPLTC(R31,1,R0)
        FAIL_F(R0,8)
test9:
        CMPEQC(R31,-1,R0)
        FAIL_T(R0,9)
test10:
        CMPLEC(R31,-1,R0)
        FAIL_T(R0,10)
test11:
        CMPLTC(R31,-1,R0)
        FAIL_T(R0,11)

        // test comparisons with overflow
test12:
        ADDC(R31,1,R1)                  // load 0x8000000 into r0
        SHLC(R1,31,R1)
        SUBC(R1,1,R2)                   // load 0x7FFFFFF into r1
        OR(R1,R2,R3)                    // make sure we have what we think we have
        CMPEQC(R3,-1,R3)
        FAIL_F(R3,12)
test13:
        CMPLE(R1,R2,R3)                 // subtraction should overflow
        FAIL_F(R3,13)
test14:
        CMPLE(R2,R1,R3)                 // test it the other way too
        FAIL_T(R3,14)

        // test the registers
test15:
        ADD(R31,R31,R0)                 // start by making sure ADD works
        FAIL_T(R0,15)
test16:
        ADDC(R31,0,R0)                  // and then ADDC
        FAIL_T(R0,16)

        // use the OP and OPC instructions to fill R1-R30 with their number
test18:
        CMPEQ(R0,R31,R1)
        CMPEQC(R1,1,R0)
        FAIL_F(R0,18)
        
test19:
        SHLC(R1,1,R2)
        CMPEQC(R2,2,R0)
        FAIL_F(R0,19)
        
test20:
        ADD(R1,R2,R3)
        CMPEQC(R3,3,R0)
        FAIL_F(R0,20)

test21:
        ADDC(R1,3,R4)
        CMPEQC(R4,4,R0)
        FAIL_F(R0,21)
        
test22:
        XORC(R31,-1,R5) XORC(R5,-6,R5)
        CMPEQC(R5,5,R0)
        FAIL_F(R0,22)
        
test23:
        OR(R4,R2,R6)
        CMPEQC(R6,6,R0)
        FAIL_F(R0,23)
        
test24:
        SUBC(R31,1,R7) SHRC(R7,29,R7)
        CMPEQC(R7,7,R0)
        FAIL_F(R0,24)
        
test25:
        SHL(R1,R3,R8)
        CMPEQC(R8,8,R0)
        FAIL_F(R0,25)

test26:
        CMPLE(R8,R8,R9) SUBC(R9,-8,R9)
        CMPEQC(R9,9,R0)
        FAIL_F(R0,26)

test27:
        XOR(R8,R2,R10)
        CMPEQC(R10,10,R0)
        FAIL_F(R0,27)

test28:
        ORC(R3,8,R11)
        CMPEQC(R11,11,R0)
        FAIL_F(R0,28)

test29:
        SUB(R31,1,R12) SHRC(R12,29,R12) ADD(R12,R5,R12)
        CMPEQC(R12,12,R0)
        FAIL_F(R0,24)

test30:
        OR(R8,R5,R13)
        CMPEQC(R13,13,R0)
        FAIL_F(R0,30)

test31:
        CMPLT(R12,R13,R14) ADD(R13,R14,R14)
        CMPEQC(R14,14,R0)
        FAIL_F(R0,31)
        
test32:
        SHLC(R1,4,R15) SUB(R15,1,R15)
        CMPEQC(R15,15,R0)
        FAIL_F(R0,32)

test33:
        SHR(R15,2,R16) ADD(R16,R13,R16)
        CMPEQC(R16,16,R0)
        FAIL_F(R0,33)

test34:
        XNORC(R16,-2,R17)
        CMPEQC(R17,17,R0)
        FAIL_F(R0,34)

test35:
        AND(R15,R2,R18) ORC(R18,16,R18)
        CMPEQC(R18,18,R0)
        FAIL_F(R0,35)

test36:
        SRA(R12,R2,R19) XNOR(R16,R19,R19) XNORC(R19,0,R19)
        CMPEQC(R19,19,R0)
        FAIL_F(R0,36)

test37:
        ADDC(R31,31,R20) ANDC(R20,20,R20)
        CMPEQC(R20,20,R0)
        FAIL_F(R0,37)

test38:
        ORC(R20,1,R21)
        CMPEQC(R21,21,R0)
        FAIL_F(R0,38)

test39:
        ADDC(R17,5,R22)
        CMPEQC(R22,22,R0)
        FAIL_F(R0,39)

test40:
        XOR(R22,R1,R23)
        CMPEQC(R23,23,R0)
        FAIL_F(R0,40)

test41:
        ANDC(R23,0xFC,R24) ADD(R24,R4,R24)
        CMPEQC(R24,24,R0)
        FAIL_F(R0,41)

test42:
        ADD(R23,R24,R25) ADDC(R25,-22,R25)
        CMPEQC(R25,25,R0)
        FAIL_F(R0,42)

test43:
        SHL(R3,R3,R26) OR(R2,R26,R26)
        CMPEQC(R26,26,R0)
        FAIL_F(R0,43)

test44:
        ADD(R14,R13,R27)
        CMPEQC(R27,27,R0)
        FAIL_F(R0,44)

test45:
        SUBC(R23,-5,R28)
        CMPEQC(R28,28,R0)
        FAIL_F(R0,45)

test46:
        SUBC(R31,-29,R29)
        CMPEQC(R29,29,R0)
        FAIL_F(R0,46)

test47:
        ADDC(R31,31,R30) SHRC(R30,1,R30) SHLC(R30,1,R30)
        CMPEQC(R30,30,R0)
        FAIL_F(R0,47)
        BF(R0,Error,R0)

test48:
        ADDC(30,17,R31)
    FAIL_T(R31,48)

// check out JMPs

test50:
        CMOVE(jmp2,R17)
        SHLC(R1,31,R1)
        OR(R1,R17,R17)
        JMP(R17,LP)
jmp1 = .
        FAIL_F(R31,50)          // shouldn't execute this!
jmp2 = .
test51:
        SHLC(LP,1,LP)           // get rid of kernel-mode bit
        SHRC(LP,1,LP)
        CMPEQC(LP,jmp1,R23)     // see if LP was filled correctly
        FAIL_F(R23,51)


// check out LDR/ADD/SUB
test52:
        LDR(CA,R24)
        LDR(C5,R25)
        ADD(R24,R25,R26)        // 0xAAAAAAAA + 0x55555555 = -1
        CMPEQC(R26,-1,R27)
        FAIL_F(R27,52)
test53:
        ADD(R24,R24,R26)        // 0xAAAAAAAA + 0xAAAAAAAA = 0x55555554
        SUB(R26,R25,R26)
        CMPEQC(R26,-1,R27)
        FAIL_F(R27,53)
test54:
        ADD(R25,R25,R26)        // 0x55555555 + 0x55555555 = 0xAAAAAAAA
        SUB(R26,R24,R26)
        FAIL_T(R26,54)
test55:
        CMOVE(1,R17)
        SUBC(R17,1,R18)         // test carry propagation
        FAIL_T(R18,55)


// test boolean operations
test56:
        CMOVE(0x0F0F,R11)
        CMOVE(0x7F00,R12)
        AND(R11,R12,R13)        // 0x0F0F & 0x7F00 = 0x0F00
        CMPEQC(R13,0x0F00,R14)
        FAIL_F(R14,56)
test57:
        OR(R11,R12,R13)         // 0x0F0F // 0x7F00 = 0x7F0F
        CMPEQC(R13,0x7F0F,R14)
        FAIL_F(R14,57)
test58:
        XOR(R11,R12,R13)        // 0x0F0F ^ 0x7F00 = 0x700F
        CMPEQC(R13,0x700F,R14)
        FAIL_F(R14,58)
test59:
        XNOR(R11,R12,R13)       // ~(0x0F0F ^ 0x7F00) = 0xFFFF8FF0
        CMPEQC(R13,0x8FF0,R14)
        FAIL_F(R14,59)


// test shifts
test60:
        CMOVE(1,R27)
        SHLC(R27,32,R28)        // should do nothing
        CMPEQC(R28,1,R29)
        FAIL_F(R29,60)
test61:
        SHLC(R27,31,R28)        // 1 << 31 = 0x80000000
        SRAC(R28,17,R26)        // 0x80000000 >>(signed) 17 = 0xFFFFC000
        CMPEQC(R26,0xC000,R25)
        FAIL_F(R25,61)
test62:
        SHRC(R28,17,R26)        // 0x80000000 >>(unsigned) 17 = 0x00004000
        CMPEQC(R26,0x4000,R25)
        FAIL_F(R25,62)


// test illegal operations
test63:
        CMOVE(0,XP)
        CMOVE(0,R1)
        LONG((0x00 << 26)+20)      // illegal operation // for circuit

        SHLC(XP,1,XP)           // get rid of kernel-mode bit
        SHRC(XP,1,XP)
        CMPEQC(XP,.-8,R0)
        FAIL_F(R0,63)
test64:                                 // test remaining illegal operations
        LONG(0x01 << 26)
        LONG(0x02 << 26)
        LONG(0x03 << 26)
        LONG(0x04 << 26)
        LONG(0x05 << 26)
        LONG(0x06 << 26)
        LONG(0x07 << 26)
        LONG(0x08 << 26)
        LONG(0x09 << 26)
        LONG(0x0A << 26)
        LONG(0x0B << 26)
        LONG(0x0C << 26)
        LONG(0x0D << 26)
        LONG(0x0E << 26)
        LONG(0x0F << 26)
        LONG(0x10 << 26)
        LONG(0x11 << 26)
        LONG(0x12 << 26)
        LONG(0x13 << 26)
        LONG(0x14 << 26)
        LONG(0x15 << 26)
        LONG(0x16 << 26)
        LONG(0x17 << 26)
        LONG(0x1A << 26)
        LONG(0x1E << 26)
        LONG(0x27 << 26)
        LONG(0x2F << 26)
        LONG(0x37 << 26)
        LONG(0x3F << 26)
        CMPEQC(R1,30,R0)
        FAIL_F(R0,64)

// test load and store
test65:
        CMOVE(LDST,R4)          // load base reg
        LDR(CA,R9)
        XORC(R9,-1,R0)          // R0 <- 0x55555555
        ST(R9,0,R4)             // try some stores
        ST(R0,LDST+4,R31)       // check out bypassing (if any!)
        ST(R9,8,R4)
        ST(R0,LDST+12,R31)
        LD(R4,0,R6)
        LDR(C5,R5)
        CMPEQ(R6,R9,R0)         // check 1-stage stall
        FAIL_F(R0,65)
test66:
        LD(R31,LDST+4,R7)
        CMPEQ(R7,R5,R0)         // check 2-stage stall
        FAIL_F(R0,66)
test67:
        LD(R4,8,R8)
        CMPEQ(R8,R9,R0)
        FAIL_F(R0,67)
test68:
        LD(R31,LDST+12,R9)
        CMPEQ(R9,R5,R0)
        FAIL_F(R0,68)

// finally, check out some bypass paths (just in case...)
test69:
        ADD(R31,R20,R0)         // R20 = 20
        ADD(R0,R0,R1)           // bypass from ALU stage
        ADD(R0,R0,R2)           // bypass from MEM stage
        ADD(R0,R0,R3)           // bypass from WB stage
        ADD(R0,R0,R4)           // read from register
        ADD(R1,R2,R5)
        ADD(R3,R5,R5)
        ADD(R4,R5,R5)
        CMPEQC(R5,160,R0)
        FAIL_F(R0,69)
test70:
        BNE(R31,.+4,R0)         // R0 = bypass
bypass: ADD(R0,R0,R1)   // bypass PC from ALU stage
        ADD(R0,R0,R2)           // bypass PC from MEM stage
        ADD(R0,R0,R3)           // bypass PC from WB stage
        ADD(R0,R0,R4)           // read from register
        ADD(R1,R2,R5)
        ADD(R3,R5,R5)
        ADD(R4,R5,R5)
        CMPEQC(R5,8*bypass,R0)
        FAIL_F(R0,70)

///////////////////////////////
// check interrupts  [Can't run this test in BSIM!]
/*
test71:
        CMOVE(.+8,R0)
// this won't work in BSIM
        JMP(R0)                 // leave supervisor mode

//// FOR CIRCUIT ONLY
        BR(ifail)               // this should be interrupted
ixp:
        BR(iokay)               // this should be executed on return
ifail:
        FAIL_F(R31,71)          // report error
iokay:
test72:
        CMPEQC(XP,ixp,R0)       // see if XP has correct value
        FAIL_F(R0,72)
/// end of for CIRCUIT
*/
///////////////////////////////
/// FOR BSIM only

// in BSIM, use this in place of test71
        CMOVE(xxx,R0)
        JMP(R0)                 // leave supervisor mode
        ADDC(R31,R31,R31)
        ADDC(R31,R31,R31)
xxx:    ADDC(R31,R31,R31)    // interrupt
        ADDC(R31,R31,R31)    // JMP(XP) interrupt return
        ADDC(R31,R31,R31)    // BR(iokay)
        ADDC(R31,R31,R31)    // CMPEQC
        ADDC(R31,R31,R31)    // branch in FAIL_F

/// end of for BSIM
///////////////////////////////
        
// make sure we can't jump from user mode to supervisor mode
test73:
        CMOVE(JTtest,R0)
        CMOVE(1,R1)
        SHLC(R1,31,R1)
        OR(R1,R0,R0)    // turn on supervisor bit in jump target
        JMP(R0,R1)                      // jumps to next instruction
JTtest:
        BR(.+4,R0)              // see what current PC is
        CMPEQC(R0,JTtest+4,R1)  // shouldn't have supervisor bit on
        FAIL_F(R1,73)
        
// test Beta's Z logic
test74:
        LD(CA,r0)
        BEQ(r0,test74_fail)
        LD(C5,r0)
        BEQ(r0,test74_fail)
        CMOVE(0,r0)
        BNE(r0,test74_fail)
        CMOVE(1,r1)
        CMOVE(32,r2)
t74_loop:
        BNE(r1,test74_okay)
test74_fail:
        CMOVE(74,r0)
        BR(Error)
test74_okay:
        SHLC(r1,1,r1)
        SUBC(r2,1,r2)
        BNE(r2,t74_loop)

// all done!

Done:   ADDC(R31,0,R31)
//        BR(Done)       // actual hardware test loops
        HALT()         // bsim version halts

CA:     LONG(0xAAAAAAAA)
C5:     LONG(0x55555555)
LDST:   LONG(0)
        LONG(0)
        LONG(0)
        LONG(0)