diff --git a/riscv_patches/0001-Initialise-misa-for-CHERI-MCU-E-not-I-not-U-not-S-no.patch b/riscv_patches/0001-Initialise-misa-for-CHERI-MCU-E-not-I-not-U-not-S-no.patch index 896131d..ab6dc6a 100644 --- a/riscv_patches/0001-Initialise-misa-for-CHERI-MCU-E-not-I-not-U-not-S-no.patch +++ b/riscv_patches/0001-Initialise-misa-for-CHERI-MCU-E-not-I-not-U-not-S-no.patch @@ -1,35 +1,35 @@ -From d5a0048e5274cb1ce81030cfccc68060ce1183a4 Mon Sep 17 00:00:00 2001 +From 47c0bc46ee6152b89addb9432945b140bfe7fe3d Mon Sep 17 00:00:00 2001 From: Robert Norton Date: Mon, 31 Oct 2022 14:19:28 +0000 -Subject: [PATCH 01/10] Initialise misa for CHERI-MCU: E not I, not U, not S, - not A. +Subject: [PATCH 1/9] Initialise misa for CHERI-MCU: E not I, not U, not S, not + A. --- model/riscv_sys_control.sail | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail -index 6204ae5..9e684d9 100644 +index 3830725..914caec 100644 --- a/model/riscv_sys_control.sail +++ b/model/riscv_sys_control.sail -@@ -552,12 +552,13 @@ function init_sys() -> unit = { - mhartid = EXTZ(0b0); +@@ -556,12 +556,13 @@ function init_sys() -> unit = { + mhartid = zero_extend(0b0); misa->MXL() = arch_to_bits(if sizeof(xlen) == 32 then RV32 else RV64); -- misa->A() = 0b1; /* atomics */ -+ // misa->A() = 0b1; /* atomics */ - misa->C() = bool_to_bits(sys_enable_rvc()); /* RVC */ -- misa->I() = 0b1; /* base integer ISA */ -+ // misa->I() = 0b1; /* base integer ISA */ +- misa->A() = 0b1; /* atomics */ ++ // misa->A() = 0b1; /* atomics */ + misa->C() = bool_to_bits(sys_enable_rvc()); /* RVC */ +- misa->I() = 0b1; /* base integer ISA */ ++ // misa->I() = 0b1; /* base integer ISA */ + misa->E() = 0b1; - misa->M() = 0b1; /* integer multiply/divide */ -- misa->U() = 0b1; /* user-mode */ -- misa->S() = 0b1; /* supervisor-mode */ -+ misa->U() = 0b0; /* user-mode */ -+ misa->S() = 0b0; /* supervisor-mode */ + misa->M() = 0b1; /* integer multiply/divide */ +- misa->U() = 0b1; /* user-mode */ +- misa->S() = 0b1; /* supervisor-mode */ ++ misa->U() = 0b0; /* user-mode */ ++ misa->S() = 0b0; /* supervisor-mode */ + misa->V() = bool_to_bits(sys_enable_vext()); /* vector extension */ if sys_enable_fdext() & sys_enable_zfinx() - then internal_error("F and Zfinx cannot both be enabled!"); -- 2.39.2 diff --git a/riscv_patches/0002-Fix-handling-of-msatus.MIE-in-M-mode-only-case.patch b/riscv_patches/0002-Fix-handling-of-msatus.MIE-in-M-mode-only-case.patch index 180a9d4..424b44d 100644 --- a/riscv_patches/0002-Fix-handling-of-msatus.MIE-in-M-mode-only-case.patch +++ b/riscv_patches/0002-Fix-handling-of-msatus.MIE-in-M-mode-only-case.patch @@ -1,7 +1,7 @@ -From 8f054703175f4f1421b4638cfca50ba1e4e283bd Mon Sep 17 00:00:00 2001 +From 848c46be16d338cca297ca1e19527406f75befb5 Mon Sep 17 00:00:00 2001 From: Robert Norton Date: Mon, 31 Oct 2022 14:21:17 +0000 -Subject: [PATCH 02/10] Fix handling of msatus.MIE in M-mode only case. +Subject: [PATCH 2/9] Fix handling of msatus.MIE in M-mode only case. Previously if neither user or supervisor mode are present dispatchInterrupt ignored mstatus.MIE leading to an infinite interrupt @@ -11,12 +11,12 @@ loop. 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail -index 9e684d9..54a8daf 100644 +index 914caec..6b2aa42 100644 --- a/model/riscv_sys_control.sail +++ b/model/riscv_sys_control.sail -@@ -341,10 +341,14 @@ function dispatchInterrupt(priv : Privilege) -> option((InterruptType, Privilege +@@ -345,10 +345,14 @@ function dispatchInterrupt(priv : Privilege) -> option((InterruptType, Privilege */ - if (~ (haveUsrMode())) | ((~ (haveSupMode())) & (~ (haveNExt()))) then { + if not(haveUsrMode()) | (not(haveSupMode()) & not(haveNExt())) then { assert(priv == Machine, "invalid current privilege"); - let enabled_pending = mip.bits() & mie.bits(); - match findPendingInterrupt(enabled_pending) { diff --git a/riscv_patches/0003-Crash-if-reading-or-writing-upper-16-registers-TODO-.patch b/riscv_patches/0003-Crash-if-reading-or-writing-upper-16-registers-TODO-.patch index a6e0a28..56f341b 100644 --- a/riscv_patches/0003-Crash-if-reading-or-writing-upper-16-registers-TODO-.patch +++ b/riscv_patches/0003-Crash-if-reading-or-writing-upper-16-registers-TODO-.patch @@ -1,18 +1,18 @@ -From 6970cd7d361b44f9ca52a5abd4a0e6c4ac550482 Mon Sep 17 00:00:00 2001 +From d2f3d2cefbe1257a6f7eb5d1aa82a8eccab066e8 Mon Sep 17 00:00:00 2001 From: Robert Norton Date: Mon, 31 Oct 2022 14:49:45 +0000 -Subject: [PATCH 03/10] Crash if reading or writing upper 16 registers: TODO - this should really be reserved instruction trap. +Subject: [PATCH 3/9] Crash if reading or writing upper 16 registers: TODO this + should really be reserved instruction trap. --- model/riscv_regs.sail | 32 -------------------------------- 1 file changed, 32 deletions(-) diff --git a/model/riscv_regs.sail b/model/riscv_regs.sail -index a65c6c5..d9ef101 100644 +index 15e7613..4ff7871 100644 --- a/model/riscv_regs.sail +++ b/model/riscv_regs.sail -@@ -128,22 +128,6 @@ function rX r = { +@@ -130,22 +130,6 @@ function rX r = { 13 => x13, 14 => x14, 15 => x15, @@ -35,7 +35,7 @@ index a65c6c5..d9ef101 100644 _ => {assert(false, "invalid register number"); zero_reg} }; regval_from_reg(v) -@@ -181,22 +165,6 @@ function wX (r, in_v) = { +@@ -183,22 +167,6 @@ function wX (r, in_v) = { 13 => x13 = v, 14 => x14 = v, 15 => x15 = v, diff --git a/riscv_patches/0004-Add-very-basic-output-only-MMIO-UART-for-terminal-ou.patch b/riscv_patches/0004-Add-very-basic-output-only-MMIO-UART-for-terminal-ou.patch index e42d4af..fea446d 100644 --- a/riscv_patches/0004-Add-very-basic-output-only-MMIO-UART-for-terminal-ou.patch +++ b/riscv_patches/0004-Add-very-basic-output-only-MMIO-UART-for-terminal-ou.patch @@ -1,8 +1,7 @@ -From 812e68c5745c8e220c3ba67374a6d889a6c9ec63 Mon Sep 17 00:00:00 2001 +From a64a1c55a35e95d8303156e52cca02d48a9e161e Mon Sep 17 00:00:00 2001 From: Robert Norton Date: Mon, 31 Oct 2022 14:59:58 +0000 -Subject: [PATCH 04/10] Add very basic output-only MMIO UART for terminal - output. +Subject: [PATCH 4/9] Add very basic output-only MMIO UART for terminal output. Mapped at 0x10000100 to match flute, with address hardcoded in a similar way to CLINT. Should make this configurable. @@ -15,12 +14,12 @@ similar way to CLINT. Should make this configurable. 5 files changed, 95 insertions(+), 4 deletions(-) diff --git a/c_emulator/riscv_platform.c b/c_emulator/riscv_platform.c -index 2572dbc..7a257fc 100644 +index fbd63fa..71600d2 100644 --- a/c_emulator/riscv_platform.c +++ b/c_emulator/riscv_platform.c -@@ -58,6 +58,13 @@ mach_bits plat_clint_base(unit u) - mach_bits plat_clint_size(unit u) - { return rv_clint_size; } +@@ -108,6 +108,13 @@ mach_bits plat_clint_size(unit u) + return rv_clint_size; + } +mach_bits plat_uart_base(unit u) +{ return rv_uart_base; } @@ -33,10 +32,10 @@ index 2572dbc..7a257fc 100644 { reservation = addr; diff --git a/c_emulator/riscv_platform.h b/c_emulator/riscv_platform.h -index 5335a90..a9b98bb 100644 +index 4b6541f..9a3f25a 100644 --- a/c_emulator/riscv_platform.h +++ b/c_emulator/riscv_platform.h -@@ -25,6 +25,9 @@ mach_bits plat_get_16_random_bits(); +@@ -27,6 +27,9 @@ mach_bits plat_get_16_random_bits(); mach_bits plat_clint_base(unit); mach_bits plat_clint_size(unit); @@ -47,10 +46,10 @@ index 5335a90..a9b98bb 100644 unit load_reservation(mach_bits); bool match_reservation(mach_bits); diff --git a/c_emulator/riscv_platform_impl.c b/c_emulator/riscv_platform_impl.c -index b1504a7..9aca0b7 100644 +index 15ff8ad..75f77e9 100644 --- a/c_emulator/riscv_platform_impl.c +++ b/c_emulator/riscv_platform_impl.c -@@ -37,6 +37,9 @@ uint64_t rv_16_random_bits(void) { +@@ -40,6 +40,9 @@ uint64_t rv_16_random_bits(void) uint64_t rv_clint_base = UINT64_C(0x2000000); uint64_t rv_clint_size = UINT64_C(0xc0000); @@ -61,10 +60,10 @@ index b1504a7..9aca0b7 100644 uint64_t rv_insns_per_tick = UINT64_C(100); diff --git a/c_emulator/riscv_platform_impl.h b/c_emulator/riscv_platform_impl.h -index 165fb94..34edd1e 100644 +index e5c562a..0a6329e 100644 --- a/c_emulator/riscv_platform_impl.h +++ b/c_emulator/riscv_platform_impl.h -@@ -29,6 +29,9 @@ extern uint64_t rv_16_random_bits(void); +@@ -32,6 +32,9 @@ extern uint64_t rv_16_random_bits(void); extern uint64_t rv_clint_base; extern uint64_t rv_clint_size; @@ -75,10 +74,10 @@ index 165fb94..34edd1e 100644 extern uint64_t rv_insns_per_tick; diff --git a/model/riscv_platform.sail b/model/riscv_platform.sail -index ea27f48..eb8946d 100644 +index 579a118..71960c2 100644 --- a/model/riscv_platform.sail +++ b/model/riscv_platform.sail -@@ -124,6 +124,10 @@ val plat_rom_size = {ocaml: "Platform.rom_size", interpreter: "Platform.rom_si +@@ -126,6 +126,10 @@ val plat_rom_size = {ocaml: "Platform.rom_size", interpreter: "Platform.rom_si val plat_clint_base = {ocaml: "Platform.clint_base", interpreter: "Platform.clint_base", c: "plat_clint_base", lem: "plat_clint_base"} : unit -> xlenbits val plat_clint_size = {ocaml: "Platform.clint_size", interpreter: "Platform.clint_size", c: "plat_clint_size", lem: "plat_clint_size"} : unit -> xlenbits @@ -89,7 +88,7 @@ index ea27f48..eb8946d 100644 /* Location of HTIF ports */ val plat_htif_tohost = {ocaml: "Platform.htif_tohost", c: "plat_htif_tohost", lem: "plat_htif_tohost"} : unit -> xlenbits function plat_htif_tohost () = to_bits(sizeof(xlen), elf_tohost ()) -@@ -183,6 +187,18 @@ function within_htif_writable forall 'n, 0 < 'n <= max_mem_access . (addr : xlen +@@ -185,6 +189,18 @@ function within_htif_writable forall 'n, 0 < 'n <= max_mem_access . (addr : xlen function within_htif_readable forall 'n, 0 < 'n <= max_mem_access . (addr : xlenbits, width : atom('n)) -> bool = plat_htif_tohost() == addr | (plat_htif_tohost() + 4 == addr & width == 4) @@ -108,7 +107,7 @@ index ea27f48..eb8946d 100644 /* CLINT (Core Local Interruptor), based on Spike. */ val plat_insns_per_tick = {ocaml: "Platform.insns_per_tick", interpreter: "Platform.insns_per_tick", c: "plat_insns_per_tick", lem: "plat_insns_per_tick"} : unit -> int -@@ -452,20 +468,77 @@ function htif_tick() = { +@@ -454,20 +470,77 @@ function htif_tick() = { /* Top-level MMIO dispatch */ $ifndef RVFI_DII function within_mmio_readable forall 'n, 0 < 'n <= max_mem_access . (addr : xlenbits, width : atom('n)) -> bool = @@ -143,7 +142,7 @@ index ea27f48..eb8946d 100644 +function uart_load(t, addr, width) = { + let offset = addr - plat_uart_base(); + /* We only support reading the status register, which always indicates ready to write output */ -+ if offset == UART_OFFSET_LINE_STATUS & ('n == 4) ++ if offset == zero_extend(UART_OFFSET_LINE_STATUS) & ('n == 4) + then { + let result = 0b100000; /* TXBufEmpty always */ + if get_config_print_platform() @@ -164,12 +163,12 @@ index ea27f48..eb8946d 100644 +function uart_store(addr, width, data) = { + let offset = addr - plat_uart_base(); + /* only support writing to the data register for output, ignore other writes */ -+ if offset == UART_OFFSET_DATA & ('n == 8 | 'n == 4) then { ++ if offset == zero_extend(UART_OFFSET_DATA) & ('n == 8 | 'n == 4) then { + if get_config_print_platform() + then print_platform("uart[" ^ BitStr(offset) ^ "] <- " ^ BitStr(data)); + if UART_DLAB == bitzero then plat_term_write(data[7..0]); + MemValue(true) -+ } else if offset == UART_OFFSET_LINE_CTL & ('n == 8 | 'n == 4) then { ++ } else if offset == zero_extend(UART_OFFSET_LINE_CTL) & ('n == 8 | 'n == 4) then { + if get_config_print_platform() + then print_platform("uart[" ^ BitStr(offset) ^ "] <- " ^ BitStr(data)); + UART_DLAB = data[7]; @@ -189,7 +188,7 @@ index ea27f48..eb8946d 100644 then clint_load(t, paddr, width) else if within_htif_readable(paddr, width) & (1 <= 'n) then htif_load(t, paddr, width) -@@ -476,7 +549,9 @@ function mmio_read forall 'n, 0 < 'n <= max_mem_access . (t : AccessType(ext_acc +@@ -478,7 +551,9 @@ function mmio_read forall 'n, 0 < 'n <= max_mem_access . (t : AccessType(ext_acc } function mmio_write forall 'n, 0 <'n <= max_mem_access . (paddr : xlenbits, width : atom('n), data: bits(8 * 'n)) -> MemoryOpResult(bool) = diff --git a/riscv_patches/0005-riscv_sim-Add-command-line-arguments-to-enable-or-di.patch b/riscv_patches/0005-riscv_sim-Add-command-line-arguments-to-enable-or-di.patch index 6417673..e675453 100644 --- a/riscv_patches/0005-riscv_sim-Add-command-line-arguments-to-enable-or-di.patch +++ b/riscv_patches/0005-riscv_sim-Add-command-line-arguments-to-enable-or-di.patch @@ -1,7 +1,7 @@ -From 41c00661efdc44da5f606941e833ba0395c51e5c Mon Sep 17 00:00:00 2001 +From a03f2b539f022bd64cdec1baba6bd0c8dba22846 Mon Sep 17 00:00:00 2001 From: Robert Norton Date: Mon, 31 Oct 2022 14:46:27 +0000 -Subject: [PATCH 05/10] riscv_sim: Add command line arguments to enable or +Subject: [PATCH 5/9] riscv_sim: Add command line arguments to enable or disable use of boot ROM. This adds command line arguments --boot-rom and --no-boot-rom to @@ -13,14 +13,14 @@ the simulator just sets the initial PC to the entry point. For backwards compatibility the default is to use the boot-rom unless NO_BOOT_ROM is defined during compilation. --- - c_emulator/riscv_sim.c | 20 ++++++++++++++++++-- - 1 file changed, 18 insertions(+), 2 deletions(-) + c_emulator/riscv_sim.c | 17 +++++++++++++++-- + 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/c_emulator/riscv_sim.c b/c_emulator/riscv_sim.c -index 5ad83e9..787714e 100644 +index 13d1653..08aa211 100644 --- a/c_emulator/riscv_sim.c +++ b/c_emulator/riscv_sim.c -@@ -76,6 +76,13 @@ bool config_print_reg = true; +@@ -83,6 +83,13 @@ bool config_print_reg = true; bool config_print_mem_access = true; bool config_print_platform = true; bool config_print_rvfi = false; @@ -32,42 +32,42 @@ index 5ad83e9..787714e 100644 +#endif +; - void set_config_print(char *var, bool val) { - if (var == NULL || strcmp("all", var) == 0) { -@@ -131,6 +138,8 @@ static struct option options[] = { - {"no-trace", optional_argument, 0, 'V'}, - {"inst-limit", required_argument, 0, 'l'}, - {"enable-zfinx", no_argument, 0, 'x'}, -+ {"boot-rom", no_argument, &config_use_boot_rom, true}, -+ {"no-boot-rom", no_argument, &config_use_boot_rom, false}, + void set_config_print(char *var, bool val) + { +@@ -142,6 +149,8 @@ static struct option options[] = { + {"inst-limit", required_argument, 0, 'l' }, + {"enable-zfinx", no_argument, 0, 'x' }, + {"enable-writable-fiom", no_argument, 0, OPT_ENABLE_WRITABLE_FIOM}, ++ {"boot-rom", no_argument, &config_use_boot_rom, true}, ++ {"no-boot-rom", no_argument, &config_use_boot_rom, false}, #ifdef SAILCOV - {"sailcov-file", required_argument, 0, 'c'}, + {"sailcov-file", required_argument, 0, 'c' }, #endif -@@ -146,7 +155,10 @@ static void print_usage(const char *argv0, int ec) +@@ -156,10 +165,10 @@ static void print_usage(const char *argv0, int ec) #endif struct option *opt = options; while (opt->name) { -- fprintf(stdout, "\t -%c\t --%s\n", (char)opt->val, opt->name); +- if (isprint(opt->val)) + if (opt->flag == NULL) -+ fprintf(stdout, "\t -%c\t --%s\n", (char)opt->val, opt->name); -+ else + fprintf(stdout, "\t -%c\t --%s\n", (char)opt->val, opt->name); + else +- fprintf(stdout, "\t \t --%s\n", opt->name); + fprintf(stdout, "\t\t --%s\n", opt->name); opt++; } exit(ec); -@@ -551,7 +563,11 @@ void init_sail(uint64_t elf_entry) +@@ -601,7 +610,11 @@ void init_sail(uint64_t elf_entry) zPC = elf_entry; } else #endif -- init_sail_reset_vector(elf_entry); + if (config_use_boot_rom) { -+ init_sail_reset_vector(elf_entry); + init_sail_reset_vector(elf_entry); + } else { + zPC = elf_entry; + } // this is probably unnecessary now; remove - if (!rv_enable_rvc) z_set_Misa_C(&zmisa, 0); + if (!rv_enable_rvc) -- 2.39.2 diff --git a/riscv_patches/0006-Add-a-new-exception-trace-option-that-prints-only-on.patch b/riscv_patches/0006-Add-a-new-exception-trace-option-that-prints-only-on.patch index 257b38a..37312f5 100644 --- a/riscv_patches/0006-Add-a-new-exception-trace-option-that-prints-only-on.patch +++ b/riscv_patches/0006-Add-a-new-exception-trace-option-that-prints-only-on.patch @@ -1,7 +1,7 @@ -From 951cbc162ecdef31361e2dddf5bd84bd77ce9b44 Mon Sep 17 00:00:00 2001 +From 7fdf336470e32419126b205908b8ec1cc34234d3 Mon Sep 17 00:00:00 2001 From: Robert Norton Date: Wed, 18 Jan 2023 11:03:36 +0000 -Subject: [PATCH 06/10] Add a new 'exception' trace option that prints only on +Subject: [PATCH 6/9] Add a new 'exception' trace option that prints only on interrupts and exceptions. --- @@ -23,10 +23,10 @@ index f8f3eb3..dcbb32d 100644 extern bool config_print_platform; +extern bool config_print_exception; diff --git a/c_emulator/riscv_prelude.c b/c_emulator/riscv_prelude.c -index 92f8415..ad5a831 100644 +index 143a152..f65c591 100644 --- a/c_emulator/riscv_prelude.c +++ b/c_emulator/riscv_prelude.c -@@ -50,3 +50,8 @@ bool get_config_print_platform(unit u) +@@ -55,3 +55,8 @@ bool get_config_print_platform(unit u) { return (config_print_platform) ? true : false; } @@ -53,10 +53,10 @@ index 9ac33aa..84a4090 100644 +bool get_config_print_exception(unit u); \ No newline at end of file diff --git a/c_emulator/riscv_sim.c b/c_emulator/riscv_sim.c -index 787714e..648c4c9 100644 +index 08aa211..b37103b 100644 --- a/c_emulator/riscv_sim.c +++ b/c_emulator/riscv_sim.c -@@ -76,6 +76,7 @@ bool config_print_reg = true; +@@ -83,6 +83,7 @@ bool config_print_reg = true; bool config_print_mem_access = true; bool config_print_platform = true; bool config_print_rvfi = false; @@ -64,7 +64,7 @@ index 787714e..648c4c9 100644 int config_use_boot_rom = #ifdef NO_BOOT_ROM false -@@ -91,6 +92,7 @@ void set_config_print(char *var, bool val) { +@@ -99,6 +100,7 @@ void set_config_print(char *var, bool val) config_print_reg = val; config_print_platform = val; config_print_rvfi = val; @@ -72,23 +72,24 @@ index 787714e..648c4c9 100644 } else if (strcmp("instr", var) == 0) { config_print_instr = val; } else if (strcmp("reg", var) == 0) { -@@ -101,8 +103,10 @@ void set_config_print(char *var, bool val) { +@@ -109,9 +111,11 @@ void set_config_print(char *var, bool val) config_print_rvfi = val; } else if (strcmp("platform", var) == 0) { config_print_platform = val; + } else if (strcmp("exception", var) == 0) { + config_print_exception = val; } else { -- fprintf(stderr, "Unknown trace category: '%s' (should be instr|reg|mem|platform|all)\n", var); -+ fprintf(stderr, "Unknown trace category: '%s' (should be instr|reg|mem|exception|platform|all)\n", var); + fprintf(stderr, "Unknown trace category: '%s' (should be %s)\n", +- "instr|reg|mem|platform|all", var); ++ "instr|reg|mem|exception|platform|all", var); exit(1); } } diff --git a/model/prelude.sail b/model/prelude.sail -index 6e6718b..29646e2 100644 +index 3e05a96..52947aa 100644 --- a/model/prelude.sail +++ b/model/prelude.sail -@@ -175,6 +175,7 @@ val print_platform = {ocaml: "Platform.print_platform", interpreter: "print_endl +@@ -164,6 +164,7 @@ val print_platform = {ocaml: "Platform.print_platform", interpreter: "print_endl val get_config_print_instr = {ocaml: "Platform.get_config_print_instr", c:"get_config_print_instr"} : unit -> bool val get_config_print_reg = {ocaml: "Platform.get_config_print_reg", c:"get_config_print_reg"} : unit -> bool val get_config_print_mem = {ocaml: "Platform.get_config_print_mem", c:"get_config_print_mem"} : unit -> bool @@ -96,19 +97,19 @@ index 6e6718b..29646e2 100644 val get_config_print_platform = {ocaml: "Platform.get_config_print_platform", c:"get_config_print_platform"} : unit -> bool // defaults for other backends -@@ -182,6 +183,7 @@ function get_config_print_instr () = false +@@ -171,6 +172,7 @@ function get_config_print_instr () = false function get_config_print_reg () = false function get_config_print_mem () = false function get_config_print_platform () = false +function get_config_print_exception () = false - val EXTS : forall 'n 'm, 'm >= 'n. (implicit('m), bits('n)) -> bits('m) - val EXTZ : forall 'n 'm, 'm >= 'n. (implicit('m), bits('n)) -> bits('m) + val sign_extend : forall 'n 'm, 'm >= 'n. (implicit('m), bits('n)) -> bits('m) + val zero_extend : forall 'n 'm, 'm >= 'n. (implicit('m), bits('n)) -> bits('m) diff --git a/model/riscv_step.sail b/model/riscv_step.sail -index 40c0c80..5ba0e72 100644 +index 550f11a..146a168 100644 --- a/model/riscv_step.sail +++ b/model/riscv_step.sail -@@ -77,8 +77,8 @@ function step(step_no : int) -> bool = { +@@ -88,8 +88,8 @@ function step(step_no : int) -> bool = { let (retired, stepped) : (Retired, bool) = match dispatchInterrupt(cur_privilege) { Some(intr, priv) => { diff --git a/riscv_patches/0007-riscv_sim-disable-tracing-by-default.patch b/riscv_patches/0007-riscv_sim-disable-tracing-by-default.patch index ba36822..3130626 100644 --- a/riscv_patches/0007-riscv_sim-disable-tracing-by-default.patch +++ b/riscv_patches/0007-riscv_sim-disable-tracing-by-default.patch @@ -1,7 +1,7 @@ -From 487fe4de8060b5856d048904cc3d4ea3646f620e Mon Sep 17 00:00:00 2001 +From 1607644330f02e9e79380a8255ed3f215d88ff97 Mon Sep 17 00:00:00 2001 From: Robert Norton Date: Mon, 23 Jan 2023 15:04:55 +0000 -Subject: [PATCH 07/10] riscv_sim: disable tracing by default. +Subject: [PATCH 7/9] riscv_sim: disable tracing by default. The current default is excessively verbose, meaning most invocations require -V to disable verbose tracing, sometimes followed by options @@ -11,10 +11,10 @@ to selectively re-enable tracing. 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/c_emulator/riscv_sim.c b/c_emulator/riscv_sim.c -index 648c4c9..8fde33f 100644 +index b37103b..55d04ce 100644 --- a/c_emulator/riscv_sim.c +++ b/c_emulator/riscv_sim.c -@@ -71,12 +71,12 @@ uint64_t mem_sig_start = 0; +@@ -78,12 +78,12 @@ uint64_t mem_sig_start = 0; uint64_t mem_sig_end = 0; int signature_granularity = 4; diff --git a/riscv_patches/0008-riscv_sim-Pass-htif-exit-code-through-to-exit-so-we-.patch b/riscv_patches/0008-riscv_sim-Pass-htif-exit-code-through-to-exit-so-we-.patch index 8533acd..d7e8f7f 100644 --- a/riscv_patches/0008-riscv_sim-Pass-htif-exit-code-through-to-exit-so-we-.patch +++ b/riscv_patches/0008-riscv_sim-Pass-htif-exit-code-through-to-exit-so-we-.patch @@ -1,25 +1,25 @@ -From 93f474ef62752f9695fc65ff8c1d3da2ae25c8de Mon Sep 17 00:00:00 2001 +From 4be78b16b219dbed06649feaf494ae115580fa7a Mon Sep 17 00:00:00 2001 From: Robert Norton Date: Thu, 26 Jan 2023 13:56:21 +0000 -Subject: [PATCH 08/10] riscv_sim: Pass htif exit code through to exit so we - can easily test it when running tests. +Subject: [PATCH 8/9] riscv_sim: Pass htif exit code through to exit so we can + easily test it when running tests. --- c_emulator/riscv_sim.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/c_emulator/riscv_sim.c b/c_emulator/riscv_sim.c -index 8fde33f..4bcff94 100644 +index 55d04ce..cdb1868 100644 --- a/c_emulator/riscv_sim.c +++ b/c_emulator/riscv_sim.c -@@ -964,7 +964,7 @@ void run_sail(void) +@@ -1034,7 +1034,7 @@ dump_state: if (diverged) { /* TODO */ } - finish(diverged); + finish(diverged | zhtif_exit_code); - step_exception: + step_exception: fprintf(stderr, "Sail exception!"); -- 2.39.2 diff --git a/riscv_patches/0009-Add-a-hacky-mechanism-to-track-new-lines-in-terminal.patch b/riscv_patches/0009-Add-a-hacky-mechanism-to-track-new-lines-in-terminal.patch index d6ec3f9..90d28f9 100644 --- a/riscv_patches/0009-Add-a-hacky-mechanism-to-track-new-lines-in-terminal.patch +++ b/riscv_patches/0009-Add-a-hacky-mechanism-to-track-new-lines-in-terminal.patch @@ -1,19 +1,19 @@ -From abca61fad742ce147f8877862f072a28df700e2b Mon Sep 17 00:00:00 2001 +From 4b555538e3fdf552799b5eae2f422c0aeb6a699f Mon Sep 17 00:00:00 2001 From: Robert Norton Date: Fri, 3 Feb 2023 13:13:17 +0000 -Subject: [PATCH 09/10] Add a hacky mechanism to track new lines in terminal - and trace output and insert extra new lines to keep them separate. +Subject: [PATCH 9/9] Add a hacky mechanism to track new lines in terminal and + trace output and insert extra new lines to keep them separate. --- c_emulator/riscv_platform_impl.c | 6 ++++++ - c_emulator/riscv_prelude.c | 20 ++++++++++++++++++++ - 2 files changed, 26 insertions(+) + c_emulator/riscv_prelude.c | 24 ++++++++++++++++++++++-- + 2 files changed, 28 insertions(+), 2 deletions(-) diff --git a/c_emulator/riscv_platform_impl.c b/c_emulator/riscv_platform_impl.c -index 9aca0b7..e554d09 100644 +index 75f77e9..c181bb4 100644 --- a/c_emulator/riscv_platform_impl.c +++ b/c_emulator/riscv_platform_impl.c -@@ -44,9 +44,15 @@ uint64_t rv_htif_tohost = UINT64_C(0x80001000); +@@ -47,9 +47,15 @@ uint64_t rv_htif_tohost = UINT64_C(0x80001000); uint64_t rv_insns_per_tick = UINT64_C(100); int term_fd = 1; // set during startup @@ -30,12 +30,12 @@ index 9aca0b7..e554d09 100644 + have_newline = c == '\n'; } diff --git a/c_emulator/riscv_prelude.c b/c_emulator/riscv_prelude.c -index ad5a831..2235ba0 100644 +index f65c591..2b8d3df 100644 --- a/c_emulator/riscv_prelude.c +++ b/c_emulator/riscv_prelude.c -@@ -1,33 +1,53 @@ - #include "riscv_prelude.h" +@@ -2,37 +2,57 @@ #include "riscv_config.h" + #include "riscv_platform_impl.h" +/* Attempt to keep track of whether output is at the start of a line so that we + * can produce nicer output if trace output interrupts terminal output. */ @@ -44,13 +44,14 @@ index ad5a831..2235ba0 100644 +void ensure_newline() +{ + if (!have_newline) -+ putchar('\n'); ++ fputc('\n', trace_log); +} + unit print_string(sail_string prefix, sail_string msg) { +- printf("%s%s\n", prefix, msg); + ensure_newline(); - printf("%s%s\n", prefix, msg); ++ fprintf(trace_log, "%s%s\n", prefix, msg); + have_newline = true; return UNIT; } @@ -58,7 +59,8 @@ index ad5a831..2235ba0 100644 unit print_instr(sail_string s) { + ensure_newline(); - if (config_print_instr) printf("%s\n", s); + if (config_print_instr) + fprintf(trace_log, "%s\n", s); + have_newline = true; return UNIT; } @@ -66,7 +68,8 @@ index ad5a831..2235ba0 100644 unit print_reg(sail_string s) { + ensure_newline(); - if (config_print_reg) printf("%s\n", s); + if (config_print_reg) + fprintf(trace_log, "%s\n", s); + have_newline = true; return UNIT; } @@ -74,7 +77,8 @@ index ad5a831..2235ba0 100644 unit print_mem_access(sail_string s) { + ensure_newline(); - if (config_print_mem_access) printf("%s\n", s); + if (config_print_mem_access) + fprintf(trace_log, "%s\n", s); + have_newline = true; return UNIT; } @@ -82,11 +86,19 @@ index ad5a831..2235ba0 100644 unit print_platform(sail_string s) { + ensure_newline(); - if (config_print_platform) printf("%s\n", s); + if (config_print_platform) + fprintf(trace_log, "%s\n", s); + have_newline = true; return UNIT; } +@@ -59,4 +79,4 @@ bool get_config_print_platform(unit u) + bool get_config_print_exception(unit u) + { + return (config_print_exception) ? true : false; +-} +\ No newline at end of file ++} -- 2.39.2