From e4edecadfc5491baf0453469072a88fab035c52f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= <michal.zygowski@3mdeb.com>
Date: Wed, 27 Nov 2024 00:13:07 +0100
Subject: [PATCH] nb/amd/pi/00730F01,dsdt_top: Add hook for _PIC method
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Per family 16h models 30h-3fh BKDG the IoapicSbFeatureEn must be
configured according to the interrupt routing mode selecte by OS.
If OS chose APIC mode, the IoapicSbFeatureEn must be cleared.
Otherwise, it must be set, meaning PIC mode is used.

Add a hook to _PIC method to call SoC/northbridge specific code to
set/clear the bit to configure GNB IOAPIC properly.

ACPI specification says that _PIC method is optional and can be
called by OSPM to provide the interrupt routing mode information to
the firmware. However, if the method is not called, the firmware
must assume PIC mode is used. AGESA sets the IoapicSbFeatureEn
already to be compliant with ACPI. Previously, coreboot cleared the
bit unconditionally and left a comment to move that part to DSDT.
The hook allows to clear the IoapicSbFeatureEn bit if OS chooses APIC
mode for interrupt routing.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
---
 src/acpi/dsdt_top.asl                         |  7 +++++
 .../amd/pi/00730F01/acpi/northbridge.asl      | 30 +++++++++++++++++++
 2 files changed, 37 insertions(+)

diff --git a/src/acpi/dsdt_top.asl b/src/acpi/dsdt_top.asl
index 7539f00e571..568dde94785 100644
--- a/src/acpi/dsdt_top.asl
+++ b/src/acpi/dsdt_top.asl
@@ -7,6 +7,8 @@
 #include <vendorcode/google/chromeos/acpi/chromeos.asl>
 #endif
 
+External (\_SB.PCI0.NAPE, MethodObj)
+
 /* Operating system enumeration. */
 Name (OSYS, 0)
 
@@ -28,6 +30,11 @@ Method (_PIC, 1)
 {
 	/* Remember the OS' IRQ routing choice. */
 	PICM = Arg0
+
+	If (CondRefOf (\_SB.PCI0.NAPE))
+	{
+		\_SB.PCI0.NAPE(Arg0 & 1)
+	}
 }
 
 #if CONFIG(ECAM_MMCONF_SUPPORT)
diff --git a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl
index df6aea063be..6ac0a53d9d4 100644
--- a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl
+++ b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl
@@ -6,6 +6,36 @@ External (TOM2)
 Name(_HID, EISAID("PNP0A08"))	/* PCI Express Root Bridge */
 Name(_CID, EISAID("PNP0A03"))	/* PCI Root Bridge */
 
+OperationRegion (NAPC, PCI_Config, 0xF8, 0x08)
+Field (NAPC, DWordAcc, NoLock, Preserve)
+{
+	NAPX,   32,	/* Northbridge IOAPIC Index */
+	NAPD,   32	/* Northbridge IOAPIC Data */
+}
+
+IndexField (NAPX, NAPD, DWordAcc, NoLock, Preserve)
+{
+	NAFC,   32	/* Northbridge IOAPIC Feature Control */
+}
+
+Mutex (NAPM, 0x00)
+Method (NAPE, 1, NotSerialized)
+{
+	Acquire (NAPM, 0xFFFF)
+
+	Local0 = NAFC
+	Local0 &= 0xFFFFFFEF /* Clear IoapicSbFeatureEn for APIC mode */
+
+	/* Set IoapicSbFeatureEn if OS chose to use PIC mode */
+	If (Arg0 == 0) {
+		Local0 |= (1 << 4)
+	}
+
+	NAFC = Local0
+
+	Release (NAPM)
+}
+
 /* Describe the Northbridge devices */
 
 Method(_BBN, 0, NotSerialized)	/* Bus number = 0 */