From a728825cd38ac78d7d661be8ff199283becdaa42 Mon Sep 17 00:00:00 2001
From: Akhil Velagapudi <4@4khil.com>
Date: Wed, 8 Jan 2025 16:23:05 -0800
Subject: [PATCH] Fix incorrect PLL1 VCO selection

Signed-off-by: Akhil Velagapudi <4@4khil.com>
---
 src/clocks/h.rs | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/clocks/h.rs b/src/clocks/h.rs
index 88a7392..717d534 100644
--- a/src/clocks/h.rs
+++ b/src/clocks/h.rs
@@ -742,8 +742,9 @@ impl Clocks {
             // 0: Wide VCO range: 192 to 836 MHz (default after reset)
             // 1: Medium VCO range: 150 to 420 MHz
             let pll1_vco = match self.pll_input_speed(self.pll_src, 1) {
-                0..=2_000_000 => 0,
-                _ => 1,
+                1_000_000..=2_000_000 => 1,
+                2_000_001..=16_000_000 => 0,
+                _ => panic!("PLL1 input source must be between 1Mhz and 16Mhz."),
             };
 
             // The user application can then configure the proper VCO: if the frequency of the reference