From 3b1cf51cdcd389f2ecdaf1d57c4967e6af8b240d Mon Sep 17 00:00:00 2001 From: Ana-Maria Balas Date: Wed, 10 Apr 2019 13:33:21 +0300 Subject: [PATCH] FIX:HW: PmodOled_RGB was missing sub ip xci --- ip/Pmods/pmodOLEDrgb_v1_0/component.xml | 21 +- .../.Xil/.PmodOLEDrgb_axi_gpio_0_1.xcix.lock | 0 .../.PmodOLEDrgb_axi_quad_spi_0_0.xcix.lock | 0 .../.PmodOLEDrgb_pmod_bridge_0_0.xcix.lock | 0 .../ip/PmodOLEDrgb_axi_gpio_0_1.xcix | Bin 14409 -> 0 bytes .../PmodOLEDrgb_axi_gpio_0_1.upgrade_log | 37 + .../PmodOLEDrgb_axi_gpio_0_1.xci | 105 + .../PmodOLEDrgb_axi_gpio_0_1.xml | 1708 +++++ .../ip/PmodOLEDrgb_axi_quad_spi_0_0.xcix | Bin 30002 -> 0 bytes .../PmodOLEDrgb_axi_quad_spi_0_0.upgrade_log | 37 + .../PmodOLEDrgb_axi_quad_spi_0_0.xci | 169 + .../PmodOLEDrgb_axi_quad_spi_0_0.xml | 6162 +++++++++++++++++ .../ip/PmodOLEDrgb_pmod_bridge_0_0.xcix | Bin 12098 -> 0 bytes .../PmodOLEDrgb_pmod_bridge_0_0.upgrade_log | 58 + .../PmodOLEDrgb_pmod_bridge_0_0.xci | 41 + .../PmodOLEDrgb_pmod_bridge_0_0.xml | 2236 ++++++ 16 files changed, 10564 insertions(+), 10 deletions(-) delete mode 100644 ip/Pmods/pmodOLEDrgb_v1_0/ip/.Xil/.PmodOLEDrgb_axi_gpio_0_1.xcix.lock delete mode 100644 ip/Pmods/pmodOLEDrgb_v1_0/ip/.Xil/.PmodOLEDrgb_axi_quad_spi_0_0.xcix.lock delete mode 100644 ip/Pmods/pmodOLEDrgb_v1_0/ip/.Xil/.PmodOLEDrgb_pmod_bridge_0_0.xcix.lock delete mode 100644 ip/Pmods/pmodOLEDrgb_v1_0/ip/PmodOLEDrgb_axi_gpio_0_1.xcix create mode 100644 ip/Pmods/pmodOLEDrgb_v1_0/ip/PmodOLEDrgb_axi_gpio_0_1/PmodOLEDrgb_axi_gpio_0_1.upgrade_log create mode 100644 ip/Pmods/pmodOLEDrgb_v1_0/ip/PmodOLEDrgb_axi_gpio_0_1/PmodOLEDrgb_axi_gpio_0_1.xci create mode 100644 ip/Pmods/pmodOLEDrgb_v1_0/ip/PmodOLEDrgb_axi_gpio_0_1/PmodOLEDrgb_axi_gpio_0_1.xml delete mode 100644 ip/Pmods/pmodOLEDrgb_v1_0/ip/PmodOLEDrgb_axi_quad_spi_0_0.xcix create mode 100644 ip/Pmods/pmodOLEDrgb_v1_0/ip/PmodOLEDrgb_axi_quad_spi_0_0/PmodOLEDrgb_axi_quad_spi_0_0.upgrade_log create mode 100644 ip/Pmods/pmodOLEDrgb_v1_0/ip/PmodOLEDrgb_axi_quad_spi_0_0/PmodOLEDrgb_axi_quad_spi_0_0.xci create mode 100644 ip/Pmods/pmodOLEDrgb_v1_0/ip/PmodOLEDrgb_axi_quad_spi_0_0/PmodOLEDrgb_axi_quad_spi_0_0.xml delete mode 100644 ip/Pmods/pmodOLEDrgb_v1_0/ip/PmodOLEDrgb_pmod_bridge_0_0.xcix create mode 100644 ip/Pmods/pmodOLEDrgb_v1_0/ip/PmodOLEDrgb_pmod_bridge_0_0/PmodOLEDrgb_pmod_bridge_0_0.upgrade_log create mode 100644 ip/Pmods/pmodOLEDrgb_v1_0/ip/PmodOLEDrgb_pmod_bridge_0_0/PmodOLEDrgb_pmod_bridge_0_0.xci create mode 100644 ip/Pmods/pmodOLEDrgb_v1_0/ip/PmodOLEDrgb_pmod_bridge_0_0/PmodOLEDrgb_pmod_bridge_0_0.xml diff --git a/ip/Pmods/pmodOLEDrgb_v1_0/component.xml b/ip/Pmods/pmodOLEDrgb_v1_0/component.xml index e4e94db1..737b06f0 100644 --- a/ip/Pmods/pmodOLEDrgb_v1_0/component.xml +++ b/ip/Pmods/pmodOLEDrgb_v1_0/component.xml @@ -752,7 +752,7 @@ viewChecksum - 54c40a05 + c59a0995 @@ -783,7 +783,7 @@ viewChecksum - 54c40a05 + c59a0995 @@ -1824,17 +1824,18 @@ xci - ip/PmodOLEDrgb_axi_gpio_0_1/PmodOLEDrgb_axi_gpio_0_1.xci + ip/PmodOLEDrgb_pmod_bridge_0_0/PmodOLEDrgb_pmod_bridge_0_0.xci xci - ip/PmodOLEDrgb_pmod_bridge_0_0/PmodOLEDrgb_pmod_bridge_0_0.xci + ip/PmodOLEDrgb_axi_gpio_0_1/PmodOLEDrgb_axi_gpio_0_1.xci xci hdl/PmodOLEDrgb_v1_0.v verilogSource CHECKSUM_54c40a05 + USED_IN_ipstatic @@ -1894,11 +1895,11 @@ xci - ip/PmodOLEDrgb_axi_gpio_0_1/PmodOLEDrgb_axi_gpio_0_1.xci + ip/PmodOLEDrgb_pmod_bridge_0_0/PmodOLEDrgb_pmod_bridge_0_0.xci xci - ip/PmodOLEDrgb_pmod_bridge_0_0/PmodOLEDrgb_pmod_bridge_0_0.xci + ip/PmodOLEDrgb_axi_gpio_0_1/PmodOLEDrgb_axi_gpio_0_1.xci xci @@ -2155,19 +2156,19 @@ AXI_Peripheral PmodOLEDrgb_v1.0 - 51 - 2018-07-26T23:06:50Z + 54 + 2019-04-10T10:23:38Z C:/Tommywork/PMODOLEDRGB/ip_repo/PmodOLEDrgb_1.0 C:/Tommywork/PMODOLEDRGB/ip_repo/PmodOLEDrgb_1.0 - d:/Github/Experimental/vivado-library/ip/Pmods/pmodOLEDrgb_v1_0 + f:/ANA-MARIA/GIT/vivado-library/ip/Pmods/PmodOLEDrgb_v1_0 2018.2 - + diff --git a/ip/Pmods/pmodOLEDrgb_v1_0/ip/.Xil/.PmodOLEDrgb_axi_gpio_0_1.xcix.lock b/ip/Pmods/pmodOLEDrgb_v1_0/ip/.Xil/.PmodOLEDrgb_axi_gpio_0_1.xcix.lock deleted file mode 100644 index e69de29b..00000000 diff --git a/ip/Pmods/pmodOLEDrgb_v1_0/ip/.Xil/.PmodOLEDrgb_axi_quad_spi_0_0.xcix.lock b/ip/Pmods/pmodOLEDrgb_v1_0/ip/.Xil/.PmodOLEDrgb_axi_quad_spi_0_0.xcix.lock deleted file mode 100644 index e69de29b..00000000 diff --git a/ip/Pmods/pmodOLEDrgb_v1_0/ip/.Xil/.PmodOLEDrgb_pmod_bridge_0_0.xcix.lock b/ip/Pmods/pmodOLEDrgb_v1_0/ip/.Xil/.PmodOLEDrgb_pmod_bridge_0_0.xcix.lock deleted file mode 100644 index e69de29b..00000000 diff --git a/ip/Pmods/pmodOLEDrgb_v1_0/ip/PmodOLEDrgb_axi_gpio_0_1.xcix b/ip/Pmods/pmodOLEDrgb_v1_0/ip/PmodOLEDrgb_axi_gpio_0_1.xcix deleted file mode 100644 index 54386d3b0c06aa6d56d9a13d8fc2841bc7179964..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 14409 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b/ip/Pmods/pmodOLEDrgb_v1_0/ip/PmodOLEDrgb_axi_gpio_0_1/PmodOLEDrgb_axi_gpio_0_1.upgrade_log new file mode 100644 index 00000000..fb4928dc --- /dev/null +++ b/ip/Pmods/pmodOLEDrgb_v1_0/ip/PmodOLEDrgb_axi_gpio_0_1/PmodOLEDrgb_axi_gpio_0_1.upgrade_log @@ -0,0 +1,37 @@ +Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015 +| Date : Tue Mar 08 16:00:25 2016 +| Host : WK116 running 64-bit major release (build 9200) +| Command : upgrade_ip +| Device : xc7z010clg400-1 +------------------------------------------------------------------------------------ + +Upgrade Log for IP 'PmodOLEDrgb_axi_gpio_0_1' + +1. Summary +---------- + +SUCCESS in the update of PmodOLEDrgb_axi_gpio_0_1 (xilinx.com:ip:axi_gpio:2.0 (Rev. 9)) to current project options. + + + + + + +Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------ +| Tool Version : Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015 +| Date : Mon Feb 29 17:10:51 2016 +| Host : WK116 running 64-bit major release (build 9200) +| Command : upgrade_ip +| Device : xc7k325tffg900-2 +------------------------------------------------------------------------------------ + +Upgrade Log for IP 'PmodOLEDrgb_axi_gpio_0_1' + +1. Summary +---------- + +SUCCESS in the update of PmodOLEDrgb_axi_gpio_0_1 (xilinx.com:ip:axi_gpio:2.0 (Rev. 9)) to current project options. + diff --git a/ip/Pmods/pmodOLEDrgb_v1_0/ip/PmodOLEDrgb_axi_gpio_0_1/PmodOLEDrgb_axi_gpio_0_1.xci b/ip/Pmods/pmodOLEDrgb_v1_0/ip/PmodOLEDrgb_axi_gpio_0_1/PmodOLEDrgb_axi_gpio_0_1.xci new file mode 100644 index 00000000..882a078e --- /dev/null +++ b/ip/Pmods/pmodOLEDrgb_v1_0/ip/PmodOLEDrgb_axi_gpio_0_1/PmodOLEDrgb_axi_gpio_0_1.xci @@ -0,0 +1,105 @@ + + + xilinx.com + xci + unknown + 1.0 + + + PmodOLEDrgb_axi_gpio_0_1 + + + 1 + 9 + 0 + 0 + 0 + + 32 + 100000000 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0.000 + 0 + 0 + 0 + 0 + 0x00000000 + 0x00000000 + artix7 + 32 + 4 + 0 + 0 + 0xFFFFFFFF + 0xFFFFFFFF + 0 + 0 + 0 + 0 + 0x00000000 + 0x00000000 + 32 + 4 + 0 + 0 + 0xFFFFFFFF + 0xFFFFFFFF + PmodOLEDrgb_axi_gpio_0_1 + Custom + Custom + false + artix7 + digilentinc.com:nexys-a7-100t:part0:1.0 + xc7a100t + csg324 + VERILOG + + MIXED + -1 + + TRUE + TRUE + IP_Integrator + 19 + TRUE + . + + . + 2018.2 + GLOBAL + + + + + + + + + + + + diff --git a/ip/Pmods/pmodOLEDrgb_v1_0/ip/PmodOLEDrgb_axi_gpio_0_1/PmodOLEDrgb_axi_gpio_0_1.xml b/ip/Pmods/pmodOLEDrgb_v1_0/ip/PmodOLEDrgb_axi_gpio_0_1/PmodOLEDrgb_axi_gpio_0_1.xml new file mode 100644 index 00000000..b57ff138 --- /dev/null +++ b/ip/Pmods/pmodOLEDrgb_v1_0/ip/PmodOLEDrgb_axi_gpio_0_1/PmodOLEDrgb_axi_gpio_0_1.xml @@ -0,0 +1,1708 @@ + + + xilinx.com + customized_ip + PmodOLEDrgb_axi_gpio_0_1 + 1.0 + + + S_AXI + S_AXI + + + + + + + + + ARADDR + + + s_axi_araddr + + + + + ARREADY + + + s_axi_arready + + + + + ARVALID + + + s_axi_arvalid + + + + + AWADDR + + + s_axi_awaddr + + + + + AWREADY + + + s_axi_awready + + + + + AWVALID + + + s_axi_awvalid + + + + + BREADY + + + s_axi_bready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + RDATA + + + s_axi_rdata + + + + + RREADY + + + s_axi_rready + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + WDATA + + + s_axi_wdata + + + + + WREADY + + + s_axi_wready + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + + DATA_WIDTH + 32 + + + none + + + + + PROTOCOL + AXI4LITE + + + none + + + + + FREQ_HZ + 100000000 + + + none + + + + + ID_WIDTH + 0 + + + none + + + + + ADDR_WIDTH + 9 + + + none + + + + + AWUSER_WIDTH + 0 + + + none + + + + + ARUSER_WIDTH + 0 + + + none + + + + + WUSER_WIDTH + 0 + + + none + + + + + RUSER_WIDTH + 0 + + + none + + + + + BUSER_WIDTH + 0 + + + none + + + + + READ_WRITE_MODE + READ_WRITE + + + none + + + + + HAS_BURST + 0 + + + none + + + + + HAS_LOCK + 0 + + + none + + + + + HAS_PROT + 0 + + + none + + + + + HAS_CACHE + 0 + + + none + + + + + HAS_QOS + 0 + + + none + + + + + HAS_REGION + 0 + + + none + + + + + HAS_WSTRB + 1 + + + none + + + + + HAS_BRESP + 1 + + + none + + + + + HAS_RRESP + 1 + + + none + + + + + SUPPORTS_NARROW_BURST + 0 + + + none + + + + + NUM_READ_OUTSTANDING + 1 + + + none + + + + + NUM_WRITE_OUTSTANDING + 1 + + + none + + + + + MAX_BURST_LENGTH + 1 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + NUM_READ_THREADS + 1 + + + none + + + + + NUM_WRITE_THREADS + 1 + + + none + + + + + RUSER_BITS_PER_BYTE + 0 + + + none + + + + + WUSER_BITS_PER_BYTE + 0 + + + none + + + + + + + S_AXI_ACLK + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + S_AXI + + + ASSOCIATED_RESET + s_axi_aresetn + + + FREQ_HZ + 100000000 + + + none + + + + + PHASE + 0.000 + + + none + + + + + CLK_DOMAIN + + + + none + + + + + + + S_AXI_ARESETN + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + IP2INTC_IRQ + IP2Intc_irq + + + + + + + INTERRUPT + + + ip2intc_irpt + + + + + + SENSITIVITY + LEVEL_HIGH + + + PortWidth + 1 + + + none + + + + + + + + false + + + + + + GPIO + GPIO + + + + + + + TRI_I + + + gpio_io_i + + + + + TRI_O + + + gpio_io_o + + + + + TRI_T + + + gpio_io_t + + + + + + BOARD.ASSOCIATED_PARAM + GPIO_BOARD_INTERFACE + + + + required + + + + + + + + + true + + + + + + GPIO2 + GPIO2 + + + + + + + TRI_I + + + gpio2_io_i + + + + + TRI_O + + + gpio2_io_o + + + + + TRI_T + + + gpio2_io_t + + + + + + BOARD.ASSOCIATED_PARAM + GPIO2_BOARD_INTERFACE + + + + required + + + + + + + + + false + + + + + + + + S_AXI + S_AXI_MEM + Memory Map for S_AXI + + Reg + Reg + Register Block + 0 + 4096 + 32 + register + read-write + + GPIO_DATA + Channel-1 GPIO DATA + Channel-1 AXI GPIO Data register + 0x0 + 4 + true + read-write + + 0x0 + + + Channel-1 GPIO DATA + Channel-1 GPIO DATA + AXI GPIO Data Register. +For each I/O bit programmed as input + R - Reads value on the input pin. + W - No effect. +For each I/O bit programmed as output + R - Reads value on GPIO_O pins + W - Writes value to the corresponding AXI GPIO + data register bit and output pin + + 0 + 4 + true + read-write + + 0 + 0 + + false + + + + GPIO_TRI + Channel-1 GPIO TRI + Channel-1 AXI GPIO 3-State Control register + 0x4 + 4 + true + read-write + + 0x0 + + + Channel-1 GPIO TRI + Channel-1 GPIO DATA + AXI GPIO 3-State Control Register +Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input + + 0 + 4 + true + read-write + + 0 + 0 + + false + + + + GPIO2_DATA + Channel-2 GPIO DATA + Channel-2 AXI GPIO Data register + 0x8 + 32 + true + read-write + + 0x0 + + + Channel-2 GPIO DATA + Channel-2 GPIO DATA + AXI GPIO Data Register. +For each I/O bit programmed as input + R - Reads value on the input pin. + W - No effect. +For each I/O bit programmed as output + R - Reads value on GPIO_O pins + W - Writes value to the corresponding AXI GPIO + data register bit and output pin + + 0 + 32 + true + read-write + + 0 + 0 + + false + + + + GPIO2_TRI + Channel-2 GPIO TRI + Channel-2 AXI GPIO 3-State Control register + 0xC + 32 + true + read-write + + 0x0 + + + Channel-2 GPIO TRI + Channel-2 GPIO DATA + AXI GPIO 3-State Control Register +Each I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input + + 0 + 32 + true + read-write + + 0 + 0 + + false + + + + GIER + Global Interrupt Enable register + Global Interrupt Enable register + 0x11C + 32 + true + read-write + + 0x0 + + + Global Interrupt Enable + Global Interrupt Enable + Master enable for the device interrupt output + 0 - Disabled + 1 - Enabled + + 31 + 1 + true + read-write + + 0 + 0 + + false + + + + IP_IER + IP Interrupt Enable register + IP Interrupt Enable register + 0x128 + 32 + true + read-write + + 0x0 + + + Channel-1 Interrupt Enable + Channel-1 Interrupt Enable + Enable Channel 1 Interrupt + 0 - Disabled (masked) + 1 - Enabled + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + Channel-2 Interrupt Enable + Channel-2 Interrupt Enable + Enable Channel 2 Interrupt + 0 - Disabled (masked) + 1 - Enabled + + 1 + 1 + true + read-write + + 0 + 0 + + false + + + + IP_ISR + IP Interrupt Status register + IP Interrupt Status register + 0x120 + 32 + true + read-write + + 0x0 + + + Channel-1 Interrupt Status + Channel-1 Interrupt Status + Channel 1 Interrupt Status + 0 - No Channel 1 input interrupt + 1 - Channel 1 input interrupt + + 0 + 1 + true + read-write + oneToToggle + + 0 + 0 + + false + + + Channel-2 Interrupt Status + Channel-2 Interrupt Status + Channel 2 Interrupt Status + 0 - No Channel 2 input interrupt + 1 - Channel 2 input interrupt + + 1 + 1 + true + read-write + oneToToggle + + 0 + 0 + + false + + + + + + + + + xilinx_veriloginstantiationtemplate + Verilog Instantiation Template + verilogSource:vivado.xilinx.com:synthesis.template + verilog + + xilinx_veriloginstantiationtemplate_view_fileset + + + + GENtimestamp + Tue Apr 09 08:25:22 UTC 2019 + + + outputProductCRC + 8:9e0e8e79 + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_veriloginstantiationtemplate + + + + 0 + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_veriloginstantiationtemplate + + + + 1 + + + + + s_axi_awaddr + + in + + 8 + 0 + + + + std_logic_vector + xilinx_veriloginstantiationtemplate + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_veriloginstantiationtemplate + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_veriloginstantiationtemplate + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_veriloginstantiationtemplate + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_veriloginstantiationtemplate + + + + 0 + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_veriloginstantiationtemplate + + + + 0 + + + + + s_axi_wready + + out + + + std_logic + xilinx_veriloginstantiationtemplate + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_veriloginstantiationtemplate + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_veriloginstantiationtemplate + + + + + + s_axi_bready + + in + + + std_logic + xilinx_veriloginstantiationtemplate + + + + 0 + + + + + s_axi_araddr + + in + + 8 + 0 + + + + std_logic_vector + xilinx_veriloginstantiationtemplate + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_veriloginstantiationtemplate + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_veriloginstantiationtemplate + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_veriloginstantiationtemplate + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_veriloginstantiationtemplate + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_veriloginstantiationtemplate + + + + + + s_axi_rready + + in + + + std_logic + xilinx_veriloginstantiationtemplate + + + + 0 + + + + + ip2intc_irpt + + out + + + std_logic + xilinx_veriloginstantiationtemplate + + + + + + + false + + + + + + gpio_io_i + + in + + 3 + 0 + + + + std_logic_vector + xilinx_veriloginstantiationtemplate + + + + 0 + + + + + + true + + + + + + gpio_io_o + + out + + 3 + 0 + + + + std_logic_vector + xilinx_veriloginstantiationtemplate + + + + + + + true + + + + + + gpio_io_t + + out + + 3 + 0 + + + + std_logic_vector + xilinx_veriloginstantiationtemplate + + + + + + + true + + + + + + gpio2_io_i + + in + + 31 + 0 + + + + std_logic_vector + xilinx_veriloginstantiationtemplate + + + + 0 + + + + + + false + + + + + + gpio2_io_o + + out + + 31 + 0 + + + + std_logic_vector + xilinx_veriloginstantiationtemplate + + + + + + + false + + + + + + gpio2_io_t + + out + + 31 + 0 + + + + std_logic_vector + xilinx_veriloginstantiationtemplate + + + + + + + false + + + + + + + + C_FAMILY + artix7 + + + C_S_AXI_ADDR_WIDTH + C S Axi Addr Width + 9 + + + C_S_AXI_DATA_WIDTH + C S Axi Data Width + 32 + + + C_GPIO_WIDTH + GPIO Width + 4 + + + C_GPIO2_WIDTH + GPIO2 Data Width + 32 + + + C_ALL_INPUTS + All Inputs + 0 + + + C_ALL_INPUTS_2 + All Inputs + 0 + + + C_ALL_OUTPUTS + All Outputs + 0 + + + C_ALL_OUTPUTS_2 + All Outputs + 0 + + + C_INTERRUPT_PRESENT + Enable Interrupt + 0 + + + C_DOUT_DEFAULT + Default DOUT value + 0x00000000 + + + C_TRI_DEFAULT + Default tri state value + 0xFFFFFFFF + + + C_IS_DUAL + Enable Dual channel + 0 + + + C_DOUT_DEFAULT_2 + Default DOUT value2 + 0x00000000 + + + C_TRI_DEFAULT_2 + Default tri state value2 + 0xFFFFFFFF + + + + + + choice_list_f624b681 + Custom + dip_switches_16bits + dual_seven_seg_led_disp + led_16bits + push_buttons_5bits + rgb_led + seven_seg_led_an + + + choice_pairs_4873554b + 0 + 1 + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + PmodOLEDrgb_axi_gpio_0_1.vho + vhdlTemplate + + + PmodOLEDrgb_axi_gpio_0_1.veo + verilogTemplate + + + + Advanced eXtensible Interface General Purpose Input/Output (AXI GPIO) core provides a general purpose input/output interface to the AXI interface. + + + C_TRI_DEFAULT + Default Tri State Value + 0xFFFFFFFF + + + + true + + + + + + C_GPIO_WIDTH + GPIO Width + 4 + + + + true + + + + + + C_GPIO2_WIDTH + GPIO Width + 32 + + + + false + + + + + + C_IS_DUAL + Enable Dual Channel + 0 + + + + true + + + + + + C_ALL_INPUTS + All Inputs + 0 + + + + true + + + + + + C_TRI_DEFAULT_2 + Default Tri State Value + 0xFFFFFFFF + + + + false + + + + + + C_DOUT_DEFAULT_2 + Default Output Value + 0x00000000 + + + + false + + + + + + C_DOUT_DEFAULT + Default Output Value + 0x00000000 + + + + true + + + + + + C_ALL_INPUTS_2 + All Inputs + 0 + + + + false + + + + + + C_INTERRUPT_PRESENT + Enable Interrupt + 0 + + + + true + + + + + + Component_Name + PmodOLEDrgb_axi_gpio_0_1 + + + + true + + + + + + USE_BOARD_FLOW + Generate Board based IO Constraints + false + + + + true + + + + + + GPIO_BOARD_INTERFACE + Custom + + + + true + + + + + + GPIO2_BOARD_INTERFACE + Custom + + + + true + + + + + + C_ALL_OUTPUTS + All Outputs + 0 + + + + true + + + + + + C_ALL_OUTPUTS_2 + All Outputs + 0 + + + + false + + + + + + + + AXI GPIO + 19 + + + + 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+ MEM0 + Register Block + 0 + 4096 + 32 + register + read-write + + + OFFSET_BASE_PARAM + C_S_AXI4_BASEADDR + + + OFFSET_HIGH_PARAM + C_S_AXI4_HIGHADDR + + + + SRR + Software Reset Register + Software Reset Register + 0x40 + 32 + true + write-only + + 0x0 + + + Reset + AXI Quad SPI Reset + The only allowed operation on this register is a write of 0x0000000a, which resets the AXI Quad SPI core. + + 0 + 32 + true + write-only + + 0 + 0 + + false + + + + + true + + + + + + SPICR + SPI Control Register + SPI Control Register + 0x60 + 32 + true + read-write + + 0x180 + + + LOOP + Loopback Mode + Local loopback mode +Enables local loopback operation and is functional only in standard SPI master mode. +When set to: 0 - Normal operation. 1 - Loopback mode. The transmitter output is internally connected to the receiver input. The receiver and transmitter operate normally, except that received data (from remote slave) is ignored. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + SPE + SPI System Enable + SPI system enable +When set to: + 0 - SPI system disabled. Both master and slave outputs are in 3-state and slave inputs are ignored. + 1 - SPI system enabled. Master outputs active (for example, IO0 (MOSI) and SCK in idle state) and slave outputs become active if SS becomes asserted. The master starts transferring when transmit data is available. + + 1 + 1 + true + read-write + + 0 + 0 + + false + + + Master + Master + Master (SPI master mode) +Setting this bit configures the SPI device as a master or a slave. +When set to: + 0 - Slave configuration. + 1 - Master configuration. +In dual/quad SPI mode only the master mode of the core is allowed. +Standard Slave mode is not supported for SCK ratio = 2 + + 2 + 1 + true + read-write + + 0 + 0 + + false + + + CPOL + Clock Polarity + Clock polarity +Setting this bit defines clock polarity. +When set to: + 0 - Active-High clock; SCK idles Low. + 1 - Active-Low clock; SCK idles High. + + 3 + 1 + true + read-write + + 0 + 0 + + false + + + CPHA + Clock Phase + Clock phase +Setting this bit selects one of two fundamentally different transfer formats. + + 4 + 1 + true + read-write + + 0 + 0 + + false + + + TX_FIFO_Reset + Transmit FIFO reset + Transmit FIFO reset +When written to 1, this bit forces a reset of the transmit FIFO to the empty condition. One AXI clock cycle after reset, this bit is again set to 0. +When set to: 0 - Transmit FIFO normal operation. 1 - Reset transmit FIFO pointer + + 5 + 1 + true + read-write + + 0 + 0 + + false + + + RX_FIFO_Reset + Receive FIFO reset + Receive FIFO reset +When written to 1, this bit forces a reset of the receive FIFO to the empty condition. One AXI clock cycle after reset, this bit is again set to 0. +When set to: 0 - Receive FIFO normal operation. 1 - Reset receive FIFO pointer. + + 6 + 1 + true + read-write + + 0 + 0 + + false + + + Manual_Slave_Select_Assertion_Enable + Manual Slave Select Assertion Enable + Manual slave select assertion enable +This bit forces the data in the slave select register to be asserted on the slave select output anytime the device is configured as a master and the device is enabled (SPE asserted). +This bit has no effect on slave operation. +When set to: 0 - Slave select output asserted by master core logic. 1 - Slave select output follows data in slave select register. The manual slave assertion mode is supported in standard SPI mode only. + + 7 + 1 + true + read-write + + 0 + 0 + + false + + + Master_Transaction_Inhibit + Master_Transaction_Inhibit + Master transaction inhibit +This bit inhibits master transactions. +This bit has no effect on slave operation. +When set to: 0 - Master transactions enabled. 1 - Master transactions disabled. This bit immediately inhibits the transaction. Setting this bit while transfer is in progress would result in unpredictable outcome + + 8 + 1 + true + read-write + + 0 + 0 + + false + + + LSB_First + LSB First + LSB first +This bit selects LSB first data transfer format. +The default transfer format is MSB first. +When set to: + 0 - MSB first transfer format. + 1 - LSB first transfer format. +In Dual/Quad SPI mode, only the MSB first mode of the core is allowed. + + 9 + 1 + true + read-write + + 0 + 0 + + false + + + + + true + + + + + + SPISR + SPI Status Register + SPI Status Register + 0x64 + 32 + true + read-only + + 0x0A5 + + + RX_Empty + Receive Empty + Receive Empty. +When a receive FIFO exists, this bit is set High when the receive FIFO is empty. The occupancy of the FIFO is decremented with each FIFO read operation. +Note: When FIFOs do not exist, this bit is set High when the receive register has been read (this option is available only in standard SPI mode). This bit is cleared at the end of a successful SPI transfer. For dual/quad SPI mode, the FIFO is always present in the core. + + 0 + 1 + true + read-only + + 0 + 0 + + false + + + RX_Full + Receive Full + Receive full. +When a receive FIFO exists, this bit is set High when the receive FIFO is full. The occupancy of the FIFO is incremented with the completion of each SPI transaction. +Note: When FIFOs do not exist, this bit is set High when an SPI transfer has completed (this option is available only in standard SPI mode). Rx_Empty and Rx_Full are complements in this case + + 1 + 1 + true + read-only + + 0 + 0 + + false + + + TX_Empty + Transmit Empty + Transmit empty. +When a transmit FIFO exists, this bit is set to High when the transmit FIFO is empty. This bit goes High as soon as the TX FIFO becomes empty. While this bit is High, the last byte of the data that is to be transmitted would still be in the pipeline. +The occupancy of the FIFO is decremented with the completion of each SPI transfer. +Note: When FIFOs do not exist, this bit is set with the completion of an SPI transfer (this option is available only in standard SPI mode). Either with or without FIFOs, this bit is cleared on an AXI write to the FIFO or transmit register. For Dual/Quad SPI mode, the FIFO is always present in the core. + + 2 + 1 + true + read-only + + 0 + 0 + + false + + + TX_Full + Transmit Full + Transmit full. +When a transmit FIFO exists, this bit is set High when the transmit FIFO is full. +Note: When FIFOs do not exist, this bit is set High when an AXI write to the transmit register has been made (this option is available only in standard SPI mode). This bit is cleared when the SPI transfer is completed + + 3 + 1 + true + read-only + + 0 + 0 + + false + + + MODF + Mode-fault error flag + Mode-fault error flag. +This flag is set if the SS signal goes active while the SPI device is configured as a master. MODF is automatically cleared by reading the SPISR. +A Low-to-High MODF transition generates a single-cycle strobe interrupt. 0 - No error. 1 - Error condition detected + + 4 + 1 + true + read-only + + 0 + 0 + + false + + + Slave_Mode_Select + Slave Mode Select + Slave_Mode_Select flag. +This flag is asserted when the core is configured in slave mode. Slave_Mode_Select is activated as soon as the master SPI core asserts the chip select pin for the core. +1 - Default in standard mode. +0 - Asserted when core configured in slave mode and selected by external SPI master. + + 5 + 1 + true + read-only + + 0 + 0 + + false + + + CPOL_CPHA_Error + CPOL_CPHA_Error + CPOL_CPHA_Error flag. +When set to: 0 - Default. 1 - The CPOL and CPHA are set to 01 or 10. When the SPI memory is chosen as either Winbond, Micron or Spansion, and CPOL and CPHA are configured as 01 or 10, this bit is set. +These memories support CPOL=CPHA mode in 00 or in 11 mode. CPOL_CPHA_Error flag is only applicable when the core is configured either in dual or quad mode in legacy or enhanced mode AXI4 interface + + 6 + 1 + true + read-only + + 0 + 0 + + false + + + Slave_mode_error + Slave mode error + Slave mode error flag. +When set to: 1 - This bit is set when the core is configured with dual or quad SPI mode and the master is set to 0 in the control register (SPICR). 0 - Master mode is set in the control register (SPICR). Note: Quad SPI mode, only the master mode of the core is allowed. Slave mode error flag is only applicable when the core is configured either in dual or qu ad mode in legacy or enhanced AXI4 mode interface + + 7 + 1 + true + read-only + + 0 + 0 + + false + + + MSB_Error + MSB Error + MSB error flag. +When set to: 0 - Default. 1 - This bit is set when the core is configured to transfer the SPI transactions in either dual or quad SPI mode and LSB first bit is set in the control register (SPICR). Note: In dual/quad SPI mode, only the MSB first mode of the core is allowed. MSB error flag is only applicable when the core is configured either in dual or quad mode in legacy or enhanced mode AXI4 interface + + 8 + 1 + true + read-only + + 0 + 0 + + false + + + Loopback_Error + Loopback Error + Loopback error flag. +When set to: 0 - Default. The loopback bit in the control register is at default state. 1 - When the SPI command, address, and data bits are set to be transferred in other than standard SPI protocol mode and this bit is set in control register (SPICR). Note: Loopback is only allowed when the core is configured in standard mode. Other modes setting of the bit causes an error and the interrupt bit is set in legacy or enhanced mode AXI4 interface + + 9 + 1 + true + read-only + + 0 + 0 + + false + + + Command_Error + Command Error + Command error flag. +When set to: 0 - Default. 1 - When the core is configured in dual/quad SPI mode and the first entry in the SPI DTR FIFO (after reset) do not match with the supported command list for the particular memory, this bit is set. Note: Command error is only applicable when the core is configured either in dual or quad mode in legacy or enhanced mode AXI4 interface. + + 10 + 1 + true + read-only + + 0 + 0 + + false + + + + + true + + + + + + SPI_DTR + SPI Data Transmit Register + SPI Data Transmit Register + 0x68 + 32 + true + write-only + + 0x0 + + + TX_Data + TX_Data + SPI Transmit Data. + + 0 + 8 + true + write-only + + 0 + 0 + + false + + + + + true + + + + + + SPI_DRR + SPI Data Receive Register + SPI Data Receive Register + 0x6C + 32 + true + read-only + + 0x0 + + + RX_Data + Receive Data + SPI Receive Data + + 0 + 8 + true + read-only + + 0 + 0 + + false + + + + + true + + + + + + SPI_SSR + SPI Slave Select Register + SPI Slave Select Register + 0x70 + 32 + true + read-write + + 0xFFFF + + + Selected_Slave + Selected Slave + Active-Low, one-hot encoded slave select +The slaves are numbered right to left starting at zero with the LSB. The slave numbers correspond to the indexes of signal SS + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + + + true + + + + + + SPI_TXFIFO_OR + Transmit FIFO Occupancy Register + SPI Transmit FIFO Occupancy Register + 0x74 + 32 + true + read-only + + 0x0 + + + Occupancy_Value + Occupancy Value + The binary value plus 1 yields the occupancy. +Bit width is log(FIFO Depth). + + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + + true + + + + + + SPI_RXFIFO_OR + Receive FIFO Occupancy Register + SPI Receive FIFO Occupancy Register + 0x78 + 32 + true + read-only + + 0x0 + + + Occupancy_Value + Occupancy Value + The binary value plus 1 yields the occupancy. +Bit width is log(FIFO Depth). + + 0 + 32 + true + read-only + + 0 + 0 + + false + + + + DGIER + Device Global Interrupt Enable Register + Device Global Interrupt Enable Register + 0x1C + 32 + true + read-write + + 0x0 + + + GIE + Global Interrupt Enable + Global Interrupt Enable. +Allows passing all individually enabled interrupts to the interrupt controller. +When set to: 0 - Disabled. 1 - Enabled. + + 31 + 1 + true + read-write + + 0 + 0 + + false + + + + + true + + + + + + IPISR + IP Interrupt Status Register + IP Interrupt Status Register + 0x20 + 32 + true + read-write + + 0x0 + + + MODF + Mode Fault Error + Mode-fault error. +This interrupt is generated if the SS signal goes active while the SPI device is configured as a master. This bit is set immediately on SS going active. + + 0 + 1 + true + read-write + oneToToggle + + 0 + 0 + + false + + + Slave_MODF + Slave Mode Fault Error + Slave mode-fault error. +This interrupt is generated if the SS signal goes active while the SPI device is configured as a slave, but is not enabled. +This bit is set immediately on SS going active and continually set if SS is active and the device is not enabled + + 1 + 1 + true + read-write + oneToToggle + + 0 + 0 + + false + + + DTR_Empty + Data transmit register/FIFO empty + Data transmit register/FIFO empty. +It is set when the last byte of data has been transferred out to the external flash memory. +In the context of the M68HC11 reference manual, when configured without FIFOs, this interrupt is equivalent in information content to the complement of the SPI transfer complete flag (SPIF ) interrupt bit. +In master mode if this bit is set to 1, no more SPI transfers are permitted + + 2 + 1 + true + read-write + oneToToggle + + 0 + 0 + + false + + + DTR_Underrun + Data transmit register/FIFO underrun + Data transmit register/FIFO underrun. +This bit is set at the end of a SPI element transfer by a one-clock period strobe to the interrupt register when data is requested from an empty transmit register/FIFO by the SPI core logic to perform a SPI transfer. +This can occur only when the SPI device is configured as a slave in standard SPI configuration and is enabled by the SPE bit as set. All zeros are loaded in the shift register and transmitted by the slave in an under-run condition + + 3 + 1 + true + read-write + oneToToggle + + 0 + 0 + + false + + + DRR_Full + Data receive register/FIFO full + Data receive register/FIFO full. +Without FIFOs, this bit is set at the end of a SPI element transfer by a one-clock period strobe to the interrupt register (An element can be a byte, half-word, or word depending on the value of Transfer Width). +With FIFOs, this bit is set at the end of the SPI element transfer, when the receive FIFO has been completely filled by a one-clock period strobe to the interrupt register. + + 4 + 1 + true + read-write + oneToToggle + + 0 + 0 + + false + + + DRR_Overrun + Data receive register/FIFO overrun + Data receive register/FIFO overrun. +This bit is set by a one-clock period strobe to the interrupt register when an attempt to write data to a full receive register or FIFO is made by the SPI core logic to complete a SPI transfer. +This can occur when the SPI device is in either master or slave mode (in standard SPI mode) or if the IP is configured in SPI master mode (dual or quad SPI mode). + + 5 + 1 + true + read-write + oneToToggle + + 0 + 0 + + false + + + TXFIFO_Half_Empty + Transmit FIFO half empty + Transmit FIFO half empty. +In standard SPI configuration, IPISR Bit[6] is the transmit FIFO half-empty interrupt. +In dual or quad SPI configuration, based on the FIFO depth, this bit is set at half-empty condition. +Note: This interrupt exists only if the AXI Quad SPI core is configured with FIFOs (In standard, dual or quad SPI mode). + + 6 + 1 + true + read-write + oneToToggle + + 0 + 0 + + false + + + Slave_Select_Mode + Slave Select Mode + Slave select mode. +The assertion of this bit is applicable only when the core is configured in slave mode in standard SPI configuration. +This bit is set when the other SPI master core selects the core by asserting the slave select line. This bit is set by a one-clock period strobe to the interrupt register. +Note: This bit is applicable only in standard SPI slave mode + + 7 + 1 + true + read-write + oneToToggle + + 0 + 0 + + false + + + DRR_Not_Empty + DRR Not Empty + DRR not empty. +The assertion of this bit is applicable only in the case where FIFO Depth is 16 or 256 and the core is configured in slave mode and standard SPI mode. This bit is set when the DRR FIFO receives the first data value during the SPI transaction. +This bit is set by a one-clock period strobe to the interrupt register when the core receives the first data beat. +Note: The assertion of this bit is applicable only when the FIFO Depth parameter is 16 or 256 and the core is configured in slave mode in standard SPI mode. When FIFO Depth is set to 0, this bit always returns 0. This bit has no significance in dual/quad mode + + 8 + 1 + true + read-write + oneToToggle + + 0 + 0 + + false + + + CPOL_CPHA_Error + CPOL_CPHA Error + CPOL_CPHA error. +This flag is asserted when: + The core is configured in either dual or quad SPI mode and + The CPOL - CPHA control register bits are set to 01 or 10. +In standard SPI mode, this bit is always in default state. + + 9 + 1 + true + read-write + oneToToggle + + 0 + 0 + + false + + + Slave_Mode_Error + I/O mode instruction Error + I/O mode instruction error. +This flag is asserted when: + The core is configured in either dual or quad SPI mode and + The core is configured in master = 0 in control register (SPICR(2)). +In standard SPI mode, this bit is always in default state. + + 10 + 1 + true + read-write + oneToToggle + + 0 + 0 + + false + + + MSB_Error + MSB Error + MSB error. +This flag is asserted when: + The core is configured in either dual or quad SPI mode and + The LSB First bit in the control register (SPICR) is set to 1. +In standard SPI mode, this bit is always in default state. + + 11 + 1 + true + read-write + oneToToggle + + 0 + 0 + + false + + + Loopback_Error + Loopback Error + Loopback error. +This flag is asserted when: + The core is configured in dual or quad SPI transfer mode and + The LOOP bit is set in control register (SPICR(0)). +In standard SPI mode, this bit is always in default state. + + 12 + 1 + true + read-write + oneToToggle + + 0 + 0 + + false + + + Command_Error + Command Error + Command error. +This flag is asserted when: The core is configured in dual/quad SPI mode and The first entry in the SPI DTR FIFO (after reset) does not match with the supported command list for particular memory. When the SPI command in DTR FIFO does not match with the internal supported command list, the core completes the SPI transactions in standard SPI format. This bit is set to show this behavior of the core. +In standard SPI mode this bit is always in default state. + + 13 + 1 + true + read-write + oneToToggle + + 0 + 0 + + false + + + + + true + + + + + + IPIER + IP Interrupt Enable Register + IP Interrupt Enable Register + 0x28 + 32 + true + read-write + + 0x0 + + + MODF + Mode-fault error flag + Mode-fault error flag. + 0 - Disabled. + 1 - Enabled. + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + Slave_MODF + Slave mode-fault error flag + Slave mode-fault error flag. + 0 - Disabled. + 1 - Enabled. + + 1 + 1 + true + read-write + + 0 + 0 + + false + + + DTR_Empty + Data transmit register/FIFO empty + Data transmit register/FIFO empty. + 0 - Disabled. + 1 - Enabled. + + 2 + 1 + true + read-write + + 0 + 0 + + false + + + DTR_Underrun + Data transmit FIFO underrun + Data transmit FIFO underrun. + 0 - Disabled. + 1 - Enabled. + + 3 + 1 + true + read-write + + 0 + 0 + + false + + + DRR_Full + Data receive register/FIFO full + Data receive register/FIFO full. + 0 - Disabled. + 1 - Enabled. + + 4 + 1 + true + read-write + + 0 + 0 + + false + + + DRR_Overrun + Receive FIFO overrun + Receive FIFO overrun. + 0 - Disabled. + 1 - Enabled. + + 5 + 1 + true + read-write + + 0 + 0 + + false + + + TX_FIFO_Half_Empty + Transmit FIFO half empty + Transmit FIFO half empty. 0 - Disabled. 1 - Enabled. Note: This bit is meaningful only if the AXI Quad SPI core is configured with FIFOs. + + 6 + 1 + true + read-write + + 0 + 0 + + false + + + Slave_Select_Mode + Slave_Select_Mode + Slave_Select_Mode. 0 - Disabled. 1 - Enabled. This bit is applicable only when the core is configured in slave mode by selecting the active-Low status on spisel. +In master mode, setting this bit has no effect. + + 7 + 1 + true + read-write + + 0 + 0 + + false + + + DRR_Not_Empty + DRR_Not_Empty + DRR_Not_Empty. 0 - Disabled. 1 - Enabled. Note: The setting of this bit is applicable only when FIFO Depth is set to 1 and the core is configured in slave mode of standard SPI mode. +If FIFO Depth is set to 0, the setting of this bit has no effect. This is allowed only in standard SPI configuration. It means this bit is not set in the IPIER register. Therefore, this bit should only be used when FIFO Depth is set to 1 and when the core is configured in slave mode. +This bit has no significance in dual or quad mode. + + 8 + 1 + true + read-write + + 0 + 0 + + false + + + CPOL_CPHA_Error + CPOL_CPHA error + CPOL_CPHA error. 0 - Disabled. 1 - Enabled. This bit is applicable only when the core is configured in dual or quad SPI mode. + + 9 + 1 + true + read-write + + 0 + 0 + + false + + + Slave_Mode_Error + Slave_Mode_Error + I/O mode instruction error. 0 - Disabled. 1 - Enabled. This bit is applicable only when the core is configured in dual or quad SPI mode. + + 10 + 1 + true + read-write + + 0 + 0 + + false + + + MSB_Error + MSB_Error + MSB_Error. 0 - Disabled. 1 - Enabled. This bit is applicable only when the core is configured in dual or quad SPI mode. + + 11 + 1 + true + read-write + + 0 + 0 + + false + + + Loopback_Error + Loopback Error + Loopback Error. 0 - Disabled. 1 - Enabled. This bit is applicable only when the core is configured in dual or quad SPI mode. + + 12 + 1 + true + read-write + + 0 + 0 + + false + + + Command_Error + Command_Error + Command_Error. 0 - Disabled. 1 - Enabled. This bit is applicable only when the core is configured in dual or quad SPI mode. + + 13 + 1 + true + read-write + + 0 + 0 + + false + + + + + true + + + + + + XIP_Config_Reg + XIP Configuration Register + XIP Configuration Register + 0x60 + 32 + true + read-write + + 0x0 + + + CPHA + CPHA + CPHA + + 0 + 1 + true + read-write + + 0 + 0 + + false + + + CPOL + CPOL + CPOL + + 1 + 1 + true + read-write + + 0 + 0 + + false + + + + + false + + + + + + XIP_Status_Reg + XIP Status Register + XIP Status Register + 0x64 + 32 + true + read-only + + 0x1 + + + RX_Empty + Receiver Empty + Receiver Empty. + + 0 + 1 + true + read-only + + 0 + 0 + + false + + + RX_Full + Receiver Full + Receiver Full. + + 1 + 1 + true + read-only + + 0 + 0 + + false + + + Master_MODF + Master Mode Fault + Master mode fault. This bit is set to 1 if the spisel line is deasserted. + + 2 + 1 + true + read-only + + 0 + 0 + + false + + + CPOL_CPHA_Error + CPOL CPHA Error + CPOL_CPHA Error. + + 3 + 1 + true + read-only + + 0 + 0 + + false + + + AXI_Transaction_Error + AXI Transaction Error + AXI Transaction Error. + + 0 + 1 + true + read-only + + 0 + 0 + + false + + + + + false + + + + + + + + false + + + + + + + + + + xilinx_veriloginstantiationtemplate + Verilog Instantiation Template + verilogSource:vivado.xilinx.com:synthesis.template + verilog + + xilinx_veriloginstantiationtemplate_view_fileset + + + + GENtimestamp + Tue Apr 09 08:35:28 UTC 2019 + + + outputProductCRC + 8:db378d8f + + + + + + + ext_spi_clk + + in + + + std_logic + xilinx_veriloginstantiationtemplate + + + + 0 + + + + + s_axi_aclk + + in + + + std_logic + xilinx_veriloginstantiationtemplate + + + + 0 + + + + + + true + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_veriloginstantiationtemplate + + + + 0 + + + + + + true + + + + + + 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Mode + 0 + + + C_NUM_SS_BITS + No. of Slave Select Bits + 1 + + + C_NUM_TRANSFER_BITS + Num Transfer Bits + 8 + + + C_SPI_MODE + SPI Mode + 0 + + + C_USE_STARTUP + Use STARTUP Primitive + 0 + + + C_USE_STARTUP_EXT + Use internal STARTUP Primitive + 0 + + + C_SPI_MEMORY + SPI Memory + 1 + + + C_S_AXI_ADDR_WIDTH + C S Axi Addr Width + 7 + + + C_S_AXI_DATA_WIDTH + C S Axi Data Width + 32 + + + C_S_AXI4_ADDR_WIDTH + C S Axi4 Addr Width + 24 + + + C_S_AXI4_DATA_WIDTH + C S Axi4 Data Width + 32 + + + C_S_AXI4_ID_WIDTH + C S Axi4 Id Width + 1 + + + C_SHARED_STARTUP + Share startup ports + 0 + + + C_S_AXI4_BASEADDR + AXI4 Full Interface Base Address + 0xFFFFFFFF + + + C_S_AXI4_HIGHADDR + AXI4 Full Interface High Address + 0x00000000 + + + C_LSB_STUP + FCSBO_STUP + 0 + + + + + + choice_list_0051c444 + 16 + 256 + + + choice_list_552a89ba + 2 + 4 + 8 + 16 + + + choice_list_6727dfa6 + 1 + 0 + + + choice_list_7389bf1d + Custom + acl_spi + qspi_flash + acl_spi + qspi_flash + acl_spi + qspi_flash + + + choice_list_8112d406 + 8 + 16 + 32 + + + choice_list_83cf9db9 + 24 + 32 + + + choice_list_8af5a703 + 0 + 1 + + + choice_pairs_4873554b + 0 + 1 + + + choice_pairs_6bca56a5 + 0 + 1 + 2 + 3 + + + choice_pairs_9f49441c + 0 + 1 + + + choice_pairs_c8de7e7d + 0 + 1 + 2 + + + + + xilinx_veriloginstantiationtemplate_view_fileset + + PmodOLEDrgb_axi_quad_spi_0_0.vho + vhdlTemplate + + + PmodOLEDrgb_axi_quad_spi_0_0.veo + verilogTemplate + + + + SPI Interface for SPI Based Slave + + + C_SPI_MEMORY + SPI Memory + This parameter should be set for tagetting the SPI flash memory. Please refer PG for more reference. Allowed values are 0= Mixed Flash, 1= Winbond SPI Flash, 2= Micron SPI Flash(Numonyx), 3= Spansion SPI Flash. + 1 + + + + true + + + + + + C_USE_STARTUP + Use STARTUPE2 Primitive + This parameter should be set when the targeted FPGA have STARTUPE2 primitive for routing the SPI clock. Please refer PG for more reference. Allowed values are 0= STARTUP is not included, 1= STARTUP is included. Example Design is not supported when STARTUPE2 primitive is chosen in the design. + 0 + + + + true + + + + + + C_USE_STARTUP_INT + STARTUP Primitive Usage + This parameter will determine if the STARTUP primitive is instantiated with-in IP or outside + 0 + + + + false + + + + + + C_SPI_MODE + SPI Mode + This parameter should be set while choosing the SPI mode of the core. Please refer PG for more reference. Allowed values are 0= Standard SPI mode, 1= Dual SPI mode, 2= Quad SPI mode. + 0 + + + + true + + + + + + C_NUM_TRANSFER_BITS + Num Transfer Bits + This parameter should be set while choosing the no. of bits in single SPI transaction. Please refer PG for more reference. Allowed values are 8 or 16 or 32. The Standard SPI mode supports all the three values while Dual and Quad SPI mode supports only the 8-bit transfer mode. + 8 + + + + true + + + + + + C_DUAL_QUAD_MODE + Dual Quad Mode + This parameter should be set to access two flash in a mux fashion. + 0 + + + + false + + + + + + C_NUM_SS_BITS + No. of Slave Select Bits + This parameter should be set to choose the no. SPI slave memories in design. This parameter decides the length of Slave Select port width of the core. + 1 + + + + true + + + + + + C_SCK_RATIO + SCK Ratio + This parameter should be set while choosing the division ratio for SPI clock. Please refer PG for more reference. Standard SPI mode has variable values for division ratio for SPI clock, while Dual and Quad mode allows only 2. XIP mode also allows division ratio of 2. + 16 + + + + true + + + + + + C_FIFO_DEPTH + FIFO Depth + This parameter should be set while choosing FIFO depth. Please refer PG for more reference. Standard SPI mode provides the choice 0 or 16 or 256 beat FIFO depth, while Dual and Quad mode provides options of 16 or 256 beat FIFO depth. + 16 + + + + true + + + + + + C_XIP_MODE + XIP Mode + This parameter should be set while choosing the core to operate in eXecute In Place (XIP) mode. Please refer PG for more reference. + 0 + + + + true + + + + + + C_SPI_MEM_ADDR_BITS + XIP Mode Memory Addressing Bits + 24 + + + + false + + + + + + C_FAMILY + Sub Mode + zynq + + + + true + + + + + + UC_FAMILY + Sub Mode + 0 + + + + true + + + + + + C_SHARED_STARTUP + Share the un-used startup ports + 0 + + + + false + + + + + + C_SUB_FAMILY + Sub Mode + zynq + + + + true + + + + + + C_TYPE_OF_AXI4_INTERFACE + Type Of AXI4 Interface + This parameter should be set while choosing the type of AXI bus interface.Please refer PG for more reference. Allowed values are 0= AXI4 Lite Interface, 1= AXI4 Memory Mapped Interface. + 0 + + + + true + + + + + + C_INSTANCE + C Instance + axi_quad_spi_inst + + + + true + + + + + + Component_Name + PmodOLEDrgb_axi_quad_spi_0_0 + + + + true + + + + + + Master_mode + Enable Master Mode + This parameter should be set while choosing the core in Standard SPI mode. Please refer PG for more reference. Standard SPI mode can operate in Master SPI or Slave SPI mode, while Dual and Quad mode operates only in Master SPI mode. + 1 + + + + true + + + + + + FIFO_INCLUDED + Enable FIFO + This parameter should be set while choosing to include the FIFO in the design or notPlease refer PG for more reference. This parameter can be set only in Standard SPI mode where choice of FIFO inclusion or exclusion is provided. In case of Dual and Quad SPI modes the FIFO inclusion is mandatory. + 1 + + + + true + + + + + + Multiples16 + Multiples16 + This parameter should be set while choosing the SPI clock in Standard SPI mode. Please refer PG for more reference. + 1 + + + + true + + + + + + C_SCK_RATIO1 + C Sck Ratio1 + 1 + + + + true + + + + + + Async_Clk + Enable Async Clock Mode + This parameter should be set while choosing the core to be used in Standalone mode and if clocks to core are different. + 1 + + + + true + + + + + + C_S_AXI4_BASEADDR + C S Axi4 Base Address + 0xFFFFFFFF + + + + true + + + + + + C_S_AXI4_HIGHADDR + C S Axi4 High Address + 0x00000000 + + + + true + + + + + + USE_BOARD_FLOW + Generate Board based IO Constraints + false + + + + true + + + + + + QSPI_BOARD_INTERFACE + QSPI Board Interface + Custom + + + + true + + + + + + C_S_AXI4_ID_WIDTH + C S Axi4 Id Width + 0 + + + + true + + + + + + C_SELECT_XPM + 0 + + + + + AXI Quad SPI + + XPM_FIFO + XPM_MEMORY + + 16 + + + + + + + + + + + 2018.2 + + + + + + + + + diff --git a/ip/Pmods/pmodOLEDrgb_v1_0/ip/PmodOLEDrgb_pmod_bridge_0_0.xcix b/ip/Pmods/pmodOLEDrgb_v1_0/ip/PmodOLEDrgb_pmod_bridge_0_0.xcix deleted file mode 100644 index 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digilentinc.com:nexys-a7-100t:part0:1.0 + xc7a100t + csg324 + VERILOG + + MIXED + -1 + + TRUE + TRUE + IP_Integrator + 12 + TRUE + . + + . + 2018.2 + GLOBAL + + + + diff --git a/ip/Pmods/pmodOLEDrgb_v1_0/ip/PmodOLEDrgb_pmod_bridge_0_0/PmodOLEDrgb_pmod_bridge_0_0.xml b/ip/Pmods/pmodOLEDrgb_v1_0/ip/PmodOLEDrgb_pmod_bridge_0_0/PmodOLEDrgb_pmod_bridge_0_0.xml new file mode 100644 index 00000000..5d6b332a --- /dev/null +++ b/ip/Pmods/pmodOLEDrgb_v1_0/ip/PmodOLEDrgb_pmod_bridge_0_0/PmodOLEDrgb_pmod_bridge_0_0.xml @@ -0,0 +1,2236 @@ + + + digilentinc.com + customized_ip + PmodOLEDrgb_pmod_bridge_0_0 + 1.0 + + + Pmod_out + Pmod Out + + + + + + + PIN1_O + + + out0_O + + + + + PIN7_I + + + out4_I + + + + + PIN2_O + + + out1_O + + + + + PIN8_I + + + out5_I + + + + + PIN3_O + + + out2_O + + + + + PIN9_I + + + out6_I + + + + + PIN10_O + + + out7_O + + + + + PIN4_O + + + out3_O + + + + + PIN3_I + + + out2_I + + + + + PIN4_I + + + out3_I + + + + + PIN1_I + + + out0_I + + + + + PIN2_I + + + out1_I + + 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