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BetaB.jsim
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// Design Project optimized beta - following ISA and architecture layout from class handouts.
.include "/PC.jsim"
.include "/CTL.jsim"
.include "/RegFile.jsim"
.include "/ALU.jsim"
.include "/CLA.jsim"
.include "/utils.jsim"
.include "/nominal.jsim"
.include "/stdcell.jsim"
.include "/projcheckoff.jsim"
// todo: maybe add branch prediction
* Improved Beta: BetaB
.subckt beta clk reset irq ia_IF[31:0] id_IF[31:0] ma[31:0] moe mrd_MEM[31:0] wr mwd[31:0]
* Stage Logic and Elements
// IF Stage
Xbeta_pc clk reset stall n_stall ia_IF[31:0] pcsel[2:0] is_ILLOP_RF n_is_ILLOP_RF JT[31:0] BSA[31:0] BOA[31:0] pc
Xbeta_regfile clk werf ra2sel id_RF[20:16] id_RF[15:11] id_RF[25:21] id_WB[25:21] wdata[31:0] r1d[31:0] r2d[31:0] regfile
Xbeta_ctl_IF except_IF ctl_IF
X_IF_id_select32 IRSrc_IF[1:0] id_IF[31:0] id_IF_store[31:0] id_select32
// RF Stage
Xbeta_ctl_RF reset id_RF[31:26] id_RF[15:0] BSA_RF[31] Z irq except_IF except_ALU except_MEM except_WB
+ ra2sel asel bsel sxtc[31:0] pcsel[2:0] branch_taken is_ILLOP_RF n_is_ILLOP_RF except_RF ctl_RF
// compute Z
Xbeta_zero32_1 bp1_out[31:0] Z zero32
// Compute stall (1 if ra or rb are reg address that is stored to current cycle, and is not r31)
Xpipe_ctl_hazard reset id_RF[20:16] id_RF[15:11] id_RF[25:21] id_ALU[25:21] id_MEM[25:21] id_WB[25:21] wdsel_ALU[1] wdsel_MEM[1] ra2sel
+ stall n_stall bp1sel[1:0] bp2sel[1:0] ctl_hazard
// Rename some wires
Xrename_JT bp1_out[31:2] JT[31:2] knex
X_JT_false JT[1:0] constant0 // force the 2 least significant bits of JT to 0
Xrename_mwd bp2_out[31:0] mwd_RF[31:0] knex
// compute BOA = [PC + 4]_RF + 4*[sign-extended constant]_RF = BSA_RF + [sign-extended id_RF[15:0]] << 2 (but discard bit 31)
// notes: id[15]#14 id[15:0] 0#2 is 4*sign-extended-constant; rewiring performs the left-shift; carry-in is 0, carry-out is co_discard
X_RF_BOA_CLA32 BSA_RF[31:0] id_RF[15]#14 id_RF[15:0] 0#2 0 out31_discard BOA[30:0] co_discard CLA32
X_RF_BOA_gnd_1 BOA[31] constant0 // set bit 31 of branch offset value to 0
X_RF_id_select IRSrc_RF[1:0] id_RF[31:0] id_RF_store[31:0] id_select32
// ALU Stage
Xbeta_ctl_ALU id_ALU[31:26] alufn[5:0] wdsel_ALU[1:0] except_ALU ctl_ALU
// setup ALU A and B inputs
Xbeta_mux2_1 b_bsel#32 bp2_out[31:0] id_RF[15]#16 id_RF[15:0] B_RF[31:0] mux2 // mux between bypass2data and sign extended literal
Xbeta_mux2_2 b_asel#32 bp1_out[31:0] BOA[31:0] A_RF[31:0] mux2
Xbeta_alu alufn[5:0] A[31:0] B[31:0] alu_out[31:0] alu_z alu_v alu_n alu
X_ALU_id_select IRSrc_ALU[1:0] id_ALU[31:0] id_ALU_store[31:0] id_select32
// MEM Stage
Xbeta_ctl_MEM reset id_MEM[31:26] BSA_MEM[31] moe wr except_MEM ctl_MEM
Xrename_ma alu_out_MEM[31:0] ma[31:0] knex
X_MEM_id_select IRSrc_MEM[1:0] id_MEM[31:0] id_MEM_store[31:0] id_select32
// WB Stage
Xbeta_ctl_WB reset id_WB[31:26] BSA_WB[31] werf except_WB ctl_WB
Xwdata_mux4 b_wdsel[0]#32 b_wdsel[1]#32 BSA_WB[31:0] alu_out_WB[31:0] mrd_WB[31:0] 0#32 wdata[31:0] mux4
* Pipelining Registers
// IF stage
X_IF_state_stalldreg_0 BSA[31:0] clk#32 b_stall#32 BSA_RF[31:0] stalldreg
X_IF_state_stalldreg_1 id_IF_store[31:0] clk#32 b_stall#32 id_RF[31:0] stalldreg
// RF stage
X_RF_state_dreg_0 BSA_RF[31:0] clk#32 BSA_ALU[31:0] dreg
X_RF_state_dreg_1 id_RF_store[31:0] clk#32 id_ALU[31:0] dreg
X_RF_state_dreg_2 A_RF[31:0] clk#32 A[31:0] dreg
X_RF_state_dreg_3 B_RF[31:0] clk#32 B[31:0] dreg
X_RF_state_dreg_4 mwd_RF[31:0] clk#32 mwd_ALU[31:0] dreg
// ALU stage
X_ALU_state_dreg_0 BSA_ALU[31:0] clk#32 BSA_MEM[31:0] dreg
X_ALU_state_dreg_1 id_ALU_store[31:0] clk#32 id_MEM[31:0] dreg
X_ALU_state_dreg_2 wdsel_ALU[1:0] clk#2 wdsel_MEM[1:0] dreg
X_ALU_state_dreg_3 alu_out[31:0] clk#32 alu_out_MEM[31:0] dreg
X_ALU_state_dreg_4 mwd_ALU[31:0] clk#32 mwd[31:0] dreg
// MEM stage
X_MEM_state_dreg_0 BSA_MEM[31:0] clk#32 BSA_WB[31:0] dreg
X_MEM_state_dreg_1 id_MEM_store[31:0] clk#32 id_WB[31:0] dreg
X_MEM_state_dreg_2 wdsel_MEM[1:0] clk#2 wdsel[1:0] dreg // wdsel is finalized
X_MEM_state_dreg_3 alu_out_MEM[31:0] clk#32 alu_out_WB[31:0] dreg
X_MEM_state_dreg_4 mrd_MEM[31:0] clk#32 mrd_WB[31:0] dreg
* Pipelining Bypass
Xbypass_alu_mux2 wdsel_ALU[0]#32 BSA_ALU[31:0] alu_out[31:0] bypass_alu[31:0] mux2
Xbypass_mem_mux2 wdsel_MEM[0]#32 BSA_MEM[31:0] alu_out_MEM[31:0] bypass_mem[31:0] mux2
Xrename_bypass_wb wdata[31:0] bypass_wb[31:0] knex
// mux bypass signals with register output
Xbp1_out_mux4 b_bp1sel[0]#32 b_bp1sel[1]#32 r1d[31:0] bypass_wb[31:0] bypass_mem[31:0] bypass_alu[31:0] bp1_out[31:0] mux4 //out of order
Xbp2_out_mux4 b_bp2sel[0]#32 b_bp2sel[1]#32 r2d[31:0] bypass_wb[31:0] bypass_mem[31:0] bypass_alu[31:0] bp2_out[31:0] mux4
* Exception handling
Xpipe_ctl_except reset branch_taken stall is_ILLOP_RF except_IF except_RF except_ALU except_MEM except_WB
+ IRSrc_IF[1:0] IRSrc_RF[1:0] IRSrc_ALU[1:0] IRSrc_MEM[1:0] ctl_EXCEPT
* Buffers for high load inputs
Xbeta_buff_0 bsel b_bsel buffer_8
Xbeta_buff_1 asel b_asel buffer_8
Xbeta_buff_2 wdsel[0] b_wdsel[0] buffer_8
Xbeta_buff_3 wdsel[1] b_wdsel[1] buffer_8
Xbuffer_stall stall b_stall buffer_8
Xbuffer_bp1sel bp1sel[1:0] b_bp1sel[1:0] buffer_8
Xbuffer_bp2sel bp2sel[1:0] b_bp2sel[1:0] buffer_8
Xbuffer_wdsel_alu wdsel_ALU[0] b_wdsel_ALU[0] buffer_8
Xbuffer_wdsel_mem wdsel_MEM[0] b_wdsel_MEM[0] buffer_8
.ends
****
* Benchmark test
****
Xbeta clk reset 0 ia_IF[31:0] id_IF[31:0] ma[31:0] moe mrd_MEM[31:0] wr mwd[31:0] beta
*
* Main Memory
*
Xmem
+ vdd 0 0 ia_IF[11:2] id_IF[31:0]
+ moe clk wr ma[11:2] md[31:0]
+ $memory width=32 nlocations=1024
+ contents=(0x77ff0008 0x77ffffff 0x77ffffff 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x0000040c 0xc01f0000 0x7fbf0007 0x779f0007 0x779f002a 0x779f0090 0x779f00a2 0x779f00b1 0x679f0408 0x77ffffff 0x0000040c 0xc3bd0004 0x679dfffc 0xc01f7ff9 0xc03f0005 0x779f000a 0x643f0318 0x641f031c 0xc01f7de3 0xc03f0025 0x779f0005 0x643f0320 0x641f0324 0x639dfffc 0xc3bdfffc 0x6ffc0000 0xc05f0010 0xc07f0000 0xb0811000 0xc0bf0001 0xb0a51000 0xd4c00000 0x7be60003 0x84002000 0x80632800 0x77ff0002 0x80002000 0x84632800 0xc4420001 0xd4c20000 0x77e6fff3 0xd4c00000 0x77e60002 0x80010000 0xc4630001 0x8023f800 0x6ffc0000 0xc3bd0004 0x679dfffc 0xc01f037c 0xc3bd0004 0x641dfffc 0x779f000c 0xc7bd0004 0xc3bd0004 0x641dfffc 0xc01f0220 0xc3bd0004 0x641dfffc 0x779f001f 0xc7bd0008 0x641f0328 0x639dfffc 0xc3bdfffc 0x6ffc0000 0xc3bd0004 0x679dfffc 0xc3bd0004 0x677dfffc 0x837df800 0xc3bd0004 0x643dfffc 0xc3bd0004 0x645dfffc 0xc01f0000 0x603bfff4 0x77e10005 0x60410004 0x64010004 0x8001f800 0x8022f800 0x7be1fffb 0x605dfffc 0xc3bdfffc 0x603dfffc 0xc3bdfffc 0x637dfffc 0xc3bdfffc 0x639dfffc 0xc3bdfffc 0x6ffc0000 0xc3bd0004 0x679dfffc 0xc3bd0004 0x677dfffc 0x837df800 0xc3bd0004 0x643dfffc 0xc3bd0004 0x645dfffc 0xc3bd0004 0x647dfffc 0x601bfff4 0x603bfff0 0x7be00001 0x77e1000a 0x77e10007 0x60400000 0x60610000 0x90421800 0x77e20003 0x60000004 0x60210004 0x77fffff6 0xc01f0000 0x77ff0001 0xc01f0001 0x607dfffc 0xc3bdfffc 0x605dfffc 0xc3bdfffc 0x603dfffc 0xc3bdfffc 0x637dfffc 0xc3bdfffc 0x639dfffc 0xc3bdfffc 0x6ffc0000 0x00000001 0x00000268 0x0000000a 0x00000270 0x00000003 0x00000258 0x00000009 0x00000228 0x00000005 0x00000250 0x00000007 0x00000260 0x00000006 0x00000248 0x00000004 0x00000240 0x00000008 0x00000238 0x00000002 0x00000230 0x0000000b 0x00000000 0xc3bd0004 0x679dfffc 0xc05f0002 0xc0ff0384 0x779f0000 0xc01f003c 0x80c7f800 0x603cfffc 0x64270000 0xc39c0004 0xc0e70004 0xc4000004 0x7be0fffa 0xc4420001 0x77e20001 0x6fe60000 0x639dfffc 0xc3bdfffc 0x6ffc0000 0xc01f0000 0xc03f0000 0xc05f0014 0xc0000001 0xc0210003 0x80000800 0x80200800 0xc4420001 0x7be2fffa 0x80010000 0x641f03fc 0x6ffc0000 0xc01ffb2e 0xc800eac8 0x641f0400 0x6ffc0000 0xc01f1000 0x6780fffc 0x6000fffc 0x641f0404 0x6ffc0000 0xedededed 0xedededed 0xedededed 0xedededed 0xedededed 0x00000001 0x00000000 0x0000000a 0x00000344 0x00000003 0x00000374 0x00000009 0x0000036c 0x00000005 0x00000364 0x00000007 0x0000035c 0x00000006 0x0000034c 0x00000004 0x0000033c 0x00000008 0x00000354 0x00000002 0x0000032c 0x0000000b 0x00000334 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0xedededed 0xdeadbeef 0x0badbabe 0xedededed 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 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//+ file="/projcheckoff.bin" // I was unable to load from file, so I just used the contents declaration
// buffer high load inputs
Xmem_buff_0 moe b_moe buffer_8
Xmem_buff_1 wr b_wr buffer_8
// Merge read and write on ma port (using memory data md instead of mrd and mwd)
Xmem_tristate_r_access b_moe#32 md[31:0] mrd_MEM[31:0] tristate // pipe md to mrd when we are reading
Xmem_tristate_w_access b_wr#32 mwd[31:0] md[31:0] tristate // pipe mwd to md when we are writing
*
* Running Benchmarks
*
Vclk clk 0 pulse(3.3,0,3.11ns,.01ns,.01ns,3.11ns) // 3.11ns is half-clk-period
Vreset reset 0 pwl(0ns 3.3v, 30ns 3.3v, 30.1ns 0v)
.tran 7560ns // down from 24100ns
.plot clk
.plot betaop(id_IF[31:26])
.plot mwd[31:0]
.plot ia_IF[31:0]