forked from Xiaoyang-Lu/ChampSim_CAMAT
-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathtext.txt
1083 lines (1017 loc) · 29.1 KB
/
text.txt
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
*************************************************
ChampSim Multicore Out-of-Order Simulator
Last compiled: Mar 20 2022 18:18:42
*************************************************
DRAM access latency: 170
Off-chip DRAM Size: 4096 MB Channels: 1 Width: 64-bit Data Rate: 2400 MT/s
DRAM_DBUS_RETURN_TIME: 13
trace_0 ./traces/403.gcc-17B.champsimtrace.xz
trace_1 ./traces/403.gcc-17B.champsimtrace.xz
trace_2 ./traces/403.gcc-17B.champsimtrace.xz
trace_3 ./traces/403.gcc-17B.champsimtrace.xz
warmup_instructions 1000
simulation_instructions 100000
champsim_seed 680
num_cpus 4
cpu_freq 4000
dram_io_freq 2400
page_size 4096
block_size 64
max_read_per_cycle 20
max_fill_per_cycle 20
dram_channels 1
dram_ranks 1
dram_banks 8
dram_rows 65536
dram_columns 128
dram_row_size 8
dram_size 4096
dram_pages 1048576
fetch_width 20
decode_width 20
exec_width 20
lq_width 20
sq_width 20
retire_width 20
scheduler_size 128
branch_mispredict_penalty 20
rob_size 256
lq_size 72
sq_size 56
num_instr_destinations_sparc 4
num_instr_destinations 2
num_instr_sources 4
itlb_set 16
itlb_way 8
itlb_rq_size 16
itlb_wq_size 16
itlb_pq_size 0
itlb_mshr_size 8
itlb_latency 1
dtlb_set 16
dtlb_way 4
dtlb_rq_size 16
dtlb_wq_size 16
dtlb_pq_size 0
dtlb_mshr_size 8
dtlb_latency 1
stlb_set 128
stlb_way 12
stlb_rq_size 32
stlb_wq_size 32
stlb_pq_size 0
stlb_mshr_size 16
stlb_latency 8
l1i_size 32
l1i_set 64
l1i_way 8
l1i_rq_size 64
l1i_wq_size 64
l1i_pq_size 8
l1i_mshr_size 8
l1i_latency 1
l1d_size 32
l1d_set 64
l1d_way 8
l1d_rq_size 64
l1d_wq_size 64
l1d_pq_size 32
l1d_mshr_size 16
l1d_latency 4
l2c_size 256
l2c_set 512
l2c_way 8
l2c_rq_size 32
l2c_wq_size 32
l2c_pq_size 16
l2c_mshr_size 32
l2c_latency 10
llc_size 8192
llc_set 8192
llc_way 16
llc_rq_size 128
llc_wq_size 128
llc_pq_size 128
llc_mshr_size 256
llc_latency 20
dram_channel_width 8
dram_wq_size 64
dram_rq_size 64
tRP 15
tRCD 15
tCAS 12.5
dram_dbus_turn_around_time 30
dram_write_high_wm 56
dram_write_low_wm 48
min_dram_writes_per_switch 16
dram_mtps 2400
dram_dbus_return_time 13
Warmup complete CPU 0 instructions: 1026 cycles: 2215 (Simulation time: 0 hr 0 min 0 sec)
Warmup complete CPU 1 instructions: 1026 cycles: 2215 (Simulation time: 0 hr 0 min 0 sec)
Warmup complete CPU 2 instructions: 1019 cycles: 2215 (Simulation time: 0 hr 0 min 0 sec)
Warmup complete CPU 3 instructions: 1001 cycles: 2215 (Simulation time: 0 hr 0 min 0 sec)
Finished CPU 2 instructions: 100001 cycles: 416751 cumulative IPC: 0.239954 (Simulation time: 0 hr 0 min 4 sec)
Finished CPU 3 instructions: 100000 cycles: 416781 cumulative IPC: 0.239934 (Simulation time: 0 hr 0 min 4 sec)
Finished CPU 0 instructions: 100006 cycles: 416796 cumulative IPC: 0.23994 (Simulation time: 0 hr 0 min 4 sec)
Finished CPU 1 instructions: 100006 cycles: 416847 cumulative IPC: 0.239911 (Simulation time: 0 hr 0 min 4 sec)
ChampSim completed all CPUs
Total Simulation Statistics (not including warmup)
CPU 0 cumulative IPC: 0.239925 instructions: 100012 cycles: 416847
Core_0_L1D_total_access 33589
Core_0_L1D_total_hit 32673
Core_0_L1D_total_miss 916
Core_0_L1D_loads 19918
Core_0_L1D_load_hit 19015
Core_0_L1D_load_miss 903
Core_0_L1D_RFOs 13671
Core_0_L1D_RFO_hit 13658
Core_0_L1D_RFO_miss 13
Core_0_L1D_prefetches 0
Core_0_L1D_prefetch_hit 0
Core_0_L1D_prefetch_miss 0
Core_0_L1D_writebacks 0
Core_0_L1D_writeback_hit 0
Core_0_L1D_writeback_miss 0
Core_0_L1I_total_access 18579
Core_0_L1I_total_hit 18389
Core_0_L1I_total_miss 190
Core_0_L1I_loads 18579
Core_0_L1I_load_hit 18389
Core_0_L1I_load_miss 190
Core_0_L1I_RFOs 0
Core_0_L1I_RFO_hit 0
Core_0_L1I_RFO_miss 0
Core_0_L1I_prefetches 0
Core_0_L1I_prefetch_hit 0
Core_0_L1I_prefetch_miss 0
Core_0_L1I_writebacks 0
Core_0_L1I_writeback_hit 0
Core_0_L1I_writeback_miss 0
Core_0_L2C_total_access 1124
Core_0_L2C_total_hit 35
Core_0_L2C_total_miss 1089
Core_0_L2C_loads 1093
Core_0_L2C_load_hit 16
Core_0_L2C_load_miss 1077
Core_0_L2C_RFOs 13
Core_0_L2C_RFO_hit 1
Core_0_L2C_RFO_miss 12
Core_0_L2C_prefetches 0
Core_0_L2C_prefetch_hit 0
Core_0_L2C_prefetch_miss 0
Core_0_L2C_writebacks 18
Core_0_L2C_writeback_hit 18
Core_0_L2C_writeback_miss 0
Core_0_LLC_total_access 1089
Core_0_LLC_total_hit 0
Core_0_LLC_total_miss 1089
Core_0_LLC_loads 1077
Core_0_LLC_load_hit 0
Core_0_LLC_load_miss 1077
Core_0_LLC_RFOs 12
Core_0_LLC_RFO_hit 0
Core_0_LLC_RFO_miss 12
Core_0_LLC_prefetches 0
Core_0_LLC_prefetch_hit 0
Core_0_LLC_prefetch_miss 0
Core_0_LLC_writebacks 0
Core_0_LLC_writeback_hit 0
Core_0_LLC_writeback_miss 0
CPU 1 cumulative IPC: 0.239911 instructions: 100006 cycles: 416847
Core_1_L1D_total_access 33573
Core_1_L1D_total_hit 32657
Core_1_L1D_total_miss 916
Core_1_L1D_loads 19911
Core_1_L1D_load_hit 19008
Core_1_L1D_load_miss 903
Core_1_L1D_RFOs 13662
Core_1_L1D_RFO_hit 13649
Core_1_L1D_RFO_miss 13
Core_1_L1D_prefetches 0
Core_1_L1D_prefetch_hit 0
Core_1_L1D_prefetch_miss 0
Core_1_L1D_writebacks 0
Core_1_L1D_writeback_hit 0
Core_1_L1D_writeback_miss 0
Core_1_L1I_total_access 18579
Core_1_L1I_total_hit 18389
Core_1_L1I_total_miss 190
Core_1_L1I_loads 18579
Core_1_L1I_load_hit 18389
Core_1_L1I_load_miss 190
Core_1_L1I_RFOs 0
Core_1_L1I_RFO_hit 0
Core_1_L1I_RFO_miss 0
Core_1_L1I_prefetches 0
Core_1_L1I_prefetch_hit 0
Core_1_L1I_prefetch_miss 0
Core_1_L1I_writebacks 0
Core_1_L1I_writeback_hit 0
Core_1_L1I_writeback_miss 0
Core_1_L2C_total_access 1124
Core_1_L2C_total_hit 35
Core_1_L2C_total_miss 1089
Core_1_L2C_loads 1093
Core_1_L2C_load_hit 16
Core_1_L2C_load_miss 1077
Core_1_L2C_RFOs 13
Core_1_L2C_RFO_hit 1
Core_1_L2C_RFO_miss 12
Core_1_L2C_prefetches 0
Core_1_L2C_prefetch_hit 0
Core_1_L2C_prefetch_miss 0
Core_1_L2C_writebacks 18
Core_1_L2C_writeback_hit 18
Core_1_L2C_writeback_miss 0
Core_1_LLC_total_access 1089
Core_1_LLC_total_hit 0
Core_1_LLC_total_miss 1089
Core_1_LLC_loads 1077
Core_1_LLC_load_hit 0
Core_1_LLC_load_miss 1077
Core_1_LLC_RFOs 12
Core_1_LLC_RFO_hit 0
Core_1_LLC_RFO_miss 12
Core_1_LLC_prefetches 0
Core_1_LLC_prefetch_hit 0
Core_1_LLC_prefetch_miss 0
Core_1_LLC_writebacks 0
Core_1_LLC_writeback_hit 0
Core_1_LLC_writeback_miss 0
CPU 2 cumulative IPC: 0.239999 instructions: 100043 cycles: 416847
Core_2_L1D_total_access 33603
Core_2_L1D_total_hit 32687
Core_2_L1D_total_miss 916
Core_2_L1D_loads 19918
Core_2_L1D_load_hit 19015
Core_2_L1D_load_miss 903
Core_2_L1D_RFOs 13685
Core_2_L1D_RFO_hit 13672
Core_2_L1D_RFO_miss 13
Core_2_L1D_prefetches 0
Core_2_L1D_prefetch_hit 0
Core_2_L1D_prefetch_miss 0
Core_2_L1D_writebacks 0
Core_2_L1D_writeback_hit 0
Core_2_L1D_writeback_miss 0
Core_2_L1I_total_access 18579
Core_2_L1I_total_hit 18389
Core_2_L1I_total_miss 190
Core_2_L1I_loads 18579
Core_2_L1I_load_hit 18389
Core_2_L1I_load_miss 190
Core_2_L1I_RFOs 0
Core_2_L1I_RFO_hit 0
Core_2_L1I_RFO_miss 0
Core_2_L1I_prefetches 0
Core_2_L1I_prefetch_hit 0
Core_2_L1I_prefetch_miss 0
Core_2_L1I_writebacks 0
Core_2_L1I_writeback_hit 0
Core_2_L1I_writeback_miss 0
Core_2_L2C_total_access 1124
Core_2_L2C_total_hit 35
Core_2_L2C_total_miss 1089
Core_2_L2C_loads 1093
Core_2_L2C_load_hit 16
Core_2_L2C_load_miss 1077
Core_2_L2C_RFOs 13
Core_2_L2C_RFO_hit 1
Core_2_L2C_RFO_miss 12
Core_2_L2C_prefetches 0
Core_2_L2C_prefetch_hit 0
Core_2_L2C_prefetch_miss 0
Core_2_L2C_writebacks 18
Core_2_L2C_writeback_hit 18
Core_2_L2C_writeback_miss 0
Core_2_LLC_total_access 1089
Core_2_LLC_total_hit 0
Core_2_LLC_total_miss 1089
Core_2_LLC_loads 1077
Core_2_LLC_load_hit 0
Core_2_LLC_load_miss 1077
Core_2_LLC_RFOs 12
Core_2_LLC_RFO_hit 0
Core_2_LLC_RFO_miss 12
Core_2_LLC_prefetches 0
Core_2_LLC_prefetch_hit 0
Core_2_LLC_prefetch_miss 0
Core_2_LLC_writebacks 0
Core_2_LLC_writeback_hit 0
Core_2_LLC_writeback_miss 0
CPU 3 cumulative IPC: 0.239983 instructions: 100036 cycles: 416847
Core_3_L1D_total_access 33594
Core_3_L1D_total_hit 32678
Core_3_L1D_total_miss 916
Core_3_L1D_loads 19920
Core_3_L1D_load_hit 19017
Core_3_L1D_load_miss 903
Core_3_L1D_RFOs 13674
Core_3_L1D_RFO_hit 13661
Core_3_L1D_RFO_miss 13
Core_3_L1D_prefetches 0
Core_3_L1D_prefetch_hit 0
Core_3_L1D_prefetch_miss 0
Core_3_L1D_writebacks 0
Core_3_L1D_writeback_hit 0
Core_3_L1D_writeback_miss 0
Core_3_L1I_total_access 18579
Core_3_L1I_total_hit 18389
Core_3_L1I_total_miss 190
Core_3_L1I_loads 18579
Core_3_L1I_load_hit 18389
Core_3_L1I_load_miss 190
Core_3_L1I_RFOs 0
Core_3_L1I_RFO_hit 0
Core_3_L1I_RFO_miss 0
Core_3_L1I_prefetches 0
Core_3_L1I_prefetch_hit 0
Core_3_L1I_prefetch_miss 0
Core_3_L1I_writebacks 0
Core_3_L1I_writeback_hit 0
Core_3_L1I_writeback_miss 0
Core_3_L2C_total_access 1124
Core_3_L2C_total_hit 35
Core_3_L2C_total_miss 1089
Core_3_L2C_loads 1093
Core_3_L2C_load_hit 16
Core_3_L2C_load_miss 1077
Core_3_L2C_RFOs 13
Core_3_L2C_RFO_hit 1
Core_3_L2C_RFO_miss 12
Core_3_L2C_prefetches 0
Core_3_L2C_prefetch_hit 0
Core_3_L2C_prefetch_miss 0
Core_3_L2C_writebacks 18
Core_3_L2C_writeback_hit 18
Core_3_L2C_writeback_miss 0
Core_3_LLC_total_access 1089
Core_3_LLC_total_hit 0
Core_3_LLC_total_miss 1089
Core_3_LLC_loads 1077
Core_3_LLC_load_hit 0
Core_3_LLC_load_miss 1077
Core_3_LLC_RFOs 12
Core_3_LLC_RFO_hit 0
Core_3_LLC_RFO_miss 12
Core_3_LLC_prefetches 0
Core_3_LLC_prefetch_hit 0
Core_3_LLC_prefetch_miss 0
Core_3_LLC_writebacks 0
Core_3_LLC_writeback_hit 0
Core_3_LLC_writeback_miss 0
[ROI Statistics]
Core_0_instructions 100006
Core_0_cycles 416796
Core_0_IPC 0.23994
Core_0_branch_prediction_accuracy 90.9586
Core_0_branch_MPKI 16.4338
Core_0_average_ROB_occupancy_at_mispredict 57.0998
Core_0_L1D_total_access 33579
Core_0_L1D_total_hit 32663
Core_0_L1D_total_miss 916
Core_0_L1D_total_overlap_miss 916
Core_0_L1D_loads 19914
Core_0_L1D_load_hit 19011
Core_0_L1D_load_miss 903
Core_0_L1D_RFOs 13665
Core_0_L1D_RFO_hit 13652
Core_0_L1D_RFO_miss 13
Core_0_L1D_prefetches 0
Core_0_L1D_prefetch_hit 0
Core_0_L1D_prefetch_miss 0
Core_0_L1D_writebacks 0
Core_0_L1D_writeback_hit 0
Core_0_L1D_writeback_miss 0
Core_0_L1D_miss_rate 0.027279
Core_0_L1D_MPKI 9.16
Core_0_L1D_demand_miss 916
Core_0_L1D_prefetch_requested 0
Core_0_L1D_prefetch_issued 0
Core_0_L1D_prefetch_useful 0
Core_0_L1D_prefetch_useless 0
Core_0_L1D_prefetch_late 0
Core_0_L1D_average_miss_latency 198.864
Core_0_L1D_active_cycles 272565
Core_0_L1D_active_hit_cycles 114580
Core_0_L1D_active_miss_cycles 173650
Core_0_L1D_active_pure_miss_cycles 157985
Core_0_L1D_active_hit_miss_overlap_cycles 15665
Core_0_L1D_total_pure_miss 916
Core_0_L1D_pure_miss_rate 0.027279
Core_0_L1D_active_cycles_per_core 272565
Core_0_L1D_active_hit_cycles_per_core 114580
Core_0_L1D_active_miss_cycles_per_core 173650
Core_0_L1D_active_pure_miss_cycles_per_core 157985
Core_0_L1D_hit_miss_overlap_cycles_per_core 15665
Core_0_L1D_camat_per_core 8.11713
Core_0_L1I_total_access 18579
Core_0_L1I_total_hit 18389
Core_0_L1I_total_miss 190
Core_0_L1I_total_overlap_miss 190
Core_0_L1I_loads 18579
Core_0_L1I_load_hit 18389
Core_0_L1I_load_miss 190
Core_0_L1I_RFOs 0
Core_0_L1I_RFO_hit 0
Core_0_L1I_RFO_miss 0
Core_0_L1I_prefetches 0
Core_0_L1I_prefetch_hit 0
Core_0_L1I_prefetch_miss 0
Core_0_L1I_writebacks 0
Core_0_L1I_writeback_hit 0
Core_0_L1I_writeback_miss 0
Core_0_L1I_miss_rate 0.0102266
Core_0_L1I_MPKI 1.9
Core_0_L1I_demand_miss 190
Core_0_L1I_prefetch_requested 0
Core_0_L1I_prefetch_issued 0
Core_0_L1I_prefetch_useful 0
Core_0_L1I_prefetch_useless 0
Core_0_L1I_prefetch_late 0
Core_0_L1I_average_miss_latency 227.247
Core_0_L1I_active_cycles 44782
Core_0_L1I_active_hit_cycles 18441
Core_0_L1I_active_miss_cycles 26550
Core_0_L1I_active_pure_miss_cycles 26341
Core_0_L1I_active_hit_miss_overlap_cycles 209
Core_0_L1I_total_pure_miss 190
Core_0_L1I_pure_miss_rate 0.0102266
Core_0_L1I_active_cycles_per_core 44782
Core_0_L1I_active_hit_cycles_per_core 18441
Core_0_L1I_active_miss_cycles_per_core 26550
Core_0_L1I_active_pure_miss_cycles_per_core 26341
Core_0_L1I_hit_miss_overlap_cycles_per_core 209
Core_0_L1I_camat_per_core 2.41036
Core_0_L2C_total_access 1124
Core_0_L2C_total_hit 35
Core_0_L2C_total_miss 1089
Core_0_L2C_total_overlap_miss 1089
Core_0_L2C_loads 1093
Core_0_L2C_load_hit 16
Core_0_L2C_load_miss 1077
Core_0_L2C_RFOs 13
Core_0_L2C_RFO_hit 1
Core_0_L2C_RFO_miss 12
Core_0_L2C_prefetches 0
Core_0_L2C_prefetch_hit 0
Core_0_L2C_prefetch_miss 0
Core_0_L2C_writebacks 18
Core_0_L2C_writeback_hit 18
Core_0_L2C_writeback_miss 0
Core_0_L2C_miss_rate 0.968861
Core_0_L2C_MPKI 10.89
Core_0_L2C_demand_miss 1089
Core_0_L2C_prefetch_requested 0
Core_0_L2C_prefetch_issued 0
Core_0_L2C_prefetch_useful 0
Core_0_L2C_prefetch_useless 0
Core_0_L2C_prefetch_late 0
Core_0_L2C_average_miss_latency 190.749
Core_0_L2C_active_cycles 192987
Core_0_L2C_active_hit_cycles 13201
Core_0_L2C_active_miss_cycles 181763
Core_0_L2C_active_pure_miss_cycles 179786
Core_0_L2C_active_hit_miss_overlap_cycles 1977
Core_0_L2C_total_pure_miss 1089
Core_0_L2C_pure_miss_rate 0.968861
Core_0_L2C_active_cycles_per_core 192987
Core_0_L2C_active_hit_cycles_per_core 13201
Core_0_L2C_active_miss_cycles_per_core 181763
Core_0_L2C_active_pure_miss_cycles_per_core 179786
Core_0_L2C_hit_miss_overlap_cycles_per_core 1977
Core_0_L2C_camat_per_core 171.697
Core_0_LLC_total_access 1089
Core_0_LLC_total_hit 0
Core_0_LLC_total_miss 1089
Core_0_LLC_total_overlap_miss 1089
Core_0_LLC_loads 1077
Core_0_LLC_load_hit 0
Core_0_LLC_load_miss 1077
Core_0_LLC_RFOs 12
Core_0_LLC_RFO_hit 0
Core_0_LLC_RFO_miss 12
Core_0_LLC_prefetches 0
Core_0_LLC_prefetch_hit 0
Core_0_LLC_prefetch_miss 0
Core_0_LLC_writebacks 0
Core_0_LLC_writeback_hit 0
Core_0_LLC_writeback_miss 0
Core_0_LLC_miss_rate 1
Core_0_LLC_MPKI 10.89
Core_0_LLC_demand_miss 1089
Core_0_LLC_prefetch_requested 0
Core_0_LLC_prefetch_issued 0
Core_0_LLC_prefetch_useful 0
Core_0_LLC_prefetch_useless 0
Core_0_LLC_prefetch_late 0
Core_0_LLC_average_miss_latency 644.858
Core_0_LLC_active_cycles 246090
Core_0_LLC_active_hit_cycles 73716
Core_0_LLC_active_miss_cycles 236922
Core_0_LLC_active_pure_miss_cycles 172374
Core_0_LLC_active_hit_miss_overlap_cycles 64548
Core_0_LLC_total_pure_miss 1089
Core_0_LLC_pure_miss_rate 1
Core_0_LLC_active_cycles_per_core 172453
Core_0_LLC_active_hit_cycles_per_core 20787
Core_0_LLC_active_miss_cycles_per_core 154014
Core_0_LLC_active_pure_miss_cycles_per_core 151666
Core_0_LLC_hit_miss_overlap_cycles_per_core 2348
Core_0_LLC_camat_per_core 158.359
Core_0_major_page_fault 0
Core_0_minor_page_fault 156
Core_1_instructions 100006
Core_1_cycles 416847
Core_1_IPC 0.239911
Core_1_branch_prediction_accuracy 90.9586
Core_1_branch_MPKI 16.4347
Core_1_average_ROB_occupancy_at_mispredict 57.1186
Core_1_L1D_total_access 33573
Core_1_L1D_total_hit 32657
Core_1_L1D_total_miss 916
Core_1_L1D_total_overlap_miss 916
Core_1_L1D_loads 19911
Core_1_L1D_load_hit 19008
Core_1_L1D_load_miss 903
Core_1_L1D_RFOs 13662
Core_1_L1D_RFO_hit 13649
Core_1_L1D_RFO_miss 13
Core_1_L1D_prefetches 0
Core_1_L1D_prefetch_hit 0
Core_1_L1D_prefetch_miss 0
Core_1_L1D_writebacks 0
Core_1_L1D_writeback_hit 0
Core_1_L1D_writeback_miss 0
Core_1_L1D_miss_rate 0.0272838
Core_1_L1D_MPKI 9.16
Core_1_L1D_demand_miss 916
Core_1_L1D_prefetch_requested 0
Core_1_L1D_prefetch_issued 0
Core_1_L1D_prefetch_useful 0
Core_1_L1D_prefetch_useless 0
Core_1_L1D_prefetch_late 0
Core_1_L1D_average_miss_latency 197.931
Core_1_L1D_active_cycles 271271
Core_1_L1D_active_hit_cycles 114408
Core_1_L1D_active_miss_cycles 172514
Core_1_L1D_active_pure_miss_cycles 156863
Core_1_L1D_active_hit_miss_overlap_cycles 15651
Core_1_L1D_total_pure_miss 916
Core_1_L1D_pure_miss_rate 0.0272838
Core_1_L1D_active_cycles_per_core 271271
Core_1_L1D_active_hit_cycles_per_core 114408
Core_1_L1D_active_miss_cycles_per_core 172514
Core_1_L1D_active_pure_miss_cycles_per_core 156863
Core_1_L1D_hit_miss_overlap_cycles_per_core 15651
Core_1_L1D_camat_per_core 8.08003
Core_1_L1I_total_access 18579
Core_1_L1I_total_hit 18389
Core_1_L1I_total_miss 190
Core_1_L1I_total_overlap_miss 190
Core_1_L1I_loads 18579
Core_1_L1I_load_hit 18389
Core_1_L1I_load_miss 190
Core_1_L1I_RFOs 0
Core_1_L1I_RFO_hit 0
Core_1_L1I_RFO_miss 0
Core_1_L1I_prefetches 0
Core_1_L1I_prefetch_hit 0
Core_1_L1I_prefetch_miss 0
Core_1_L1I_writebacks 0
Core_1_L1I_writeback_hit 0
Core_1_L1I_writeback_miss 0
Core_1_L1I_miss_rate 0.0102266
Core_1_L1I_MPKI 1.9
Core_1_L1I_demand_miss 190
Core_1_L1I_prefetch_requested 0
Core_1_L1I_prefetch_issued 0
Core_1_L1I_prefetch_useful 0
Core_1_L1I_prefetch_useless 0
Core_1_L1I_prefetch_late 0
Core_1_L1I_average_miss_latency 240.742
Core_1_L1I_active_cycles 45919
Core_1_L1I_active_hit_cycles 18441
Core_1_L1I_active_miss_cycles 27687
Core_1_L1I_active_pure_miss_cycles 27478
Core_1_L1I_active_hit_miss_overlap_cycles 209
Core_1_L1I_total_pure_miss 190
Core_1_L1I_pure_miss_rate 0.0102266
Core_1_L1I_active_cycles_per_core 45919
Core_1_L1I_active_hit_cycles_per_core 18441
Core_1_L1I_active_miss_cycles_per_core 27687
Core_1_L1I_active_pure_miss_cycles_per_core 27478
Core_1_L1I_hit_miss_overlap_cycles_per_core 209
Core_1_L1I_camat_per_core 2.47155
Core_1_L2C_total_access 1124
Core_1_L2C_total_hit 35
Core_1_L2C_total_miss 1089
Core_1_L2C_total_overlap_miss 1089
Core_1_L2C_loads 1093
Core_1_L2C_load_hit 16
Core_1_L2C_load_miss 1077
Core_1_L2C_RFOs 13
Core_1_L2C_RFO_hit 1
Core_1_L2C_RFO_miss 12
Core_1_L2C_prefetches 0
Core_1_L2C_prefetch_hit 0
Core_1_L2C_prefetch_miss 0
Core_1_L2C_writebacks 18
Core_1_L2C_writeback_hit 18
Core_1_L2C_writeback_miss 0
Core_1_L2C_miss_rate 0.968861
Core_1_L2C_MPKI 10.89
Core_1_L2C_demand_miss 1089
Core_1_L2C_prefetch_requested 0
Core_1_L2C_prefetch_issued 0
Core_1_L2C_prefetch_useful 0
Core_1_L2C_prefetch_useless 0
Core_1_L2C_prefetch_late 0
Core_1_L2C_average_miss_latency 192.32
Core_1_L2C_active_cycles 193079
Core_1_L2C_active_hit_cycles 13192
Core_1_L2C_active_miss_cycles 181845
Core_1_L2C_active_pure_miss_cycles 179887
Core_1_L2C_active_hit_miss_overlap_cycles 1958
Core_1_L2C_total_pure_miss 1089
Core_1_L2C_pure_miss_rate 0.968861
Core_1_L2C_active_cycles_per_core 193079
Core_1_L2C_active_hit_cycles_per_core 13192
Core_1_L2C_active_miss_cycles_per_core 181845
Core_1_L2C_active_pure_miss_cycles_per_core 179887
Core_1_L2C_hit_miss_overlap_cycles_per_core 1958
Core_1_L2C_camat_per_core 171.778
Core_1_LLC_total_access 1089
Core_1_LLC_total_hit 0
Core_1_LLC_total_miss 1089
Core_1_LLC_total_overlap_miss 1089
Core_1_LLC_loads 1077
Core_1_LLC_load_hit 0
Core_1_LLC_load_miss 1077
Core_1_LLC_RFOs 12
Core_1_LLC_RFO_hit 0
Core_1_LLC_RFO_miss 12
Core_1_LLC_prefetches 0
Core_1_LLC_prefetch_hit 0
Core_1_LLC_prefetch_miss 0
Core_1_LLC_writebacks 0
Core_1_LLC_writeback_hit 0
Core_1_LLC_writeback_miss 0
Core_1_LLC_miss_rate 1
Core_1_LLC_MPKI 10.89
Core_1_LLC_demand_miss 1089
Core_1_LLC_prefetch_requested 0
Core_1_LLC_prefetch_issued 0
Core_1_LLC_prefetch_useful 0
Core_1_LLC_prefetch_useless 0
Core_1_LLC_prefetch_late 0
Core_1_LLC_average_miss_latency 644.858
Core_1_LLC_active_cycles 246090
Core_1_LLC_active_hit_cycles 73716
Core_1_LLC_active_miss_cycles 236922
Core_1_LLC_active_pure_miss_cycles 172374
Core_1_LLC_active_hit_miss_overlap_cycles 64548
Core_1_LLC_total_pure_miss 1089
Core_1_LLC_pure_miss_rate 1
Core_1_LLC_active_cycles_per_core 172564
Core_1_LLC_active_hit_cycles_per_core 20768
Core_1_LLC_active_miss_cycles_per_core 154106
Core_1_LLC_active_pure_miss_cycles_per_core 151796
Core_1_LLC_hit_miss_overlap_cycles_per_core 2310
Core_1_LLC_camat_per_core 158.461
Core_1_major_page_fault 0
Core_1_minor_page_fault 156
Core_2_instructions 100001
Core_2_cycles 416751
Core_2_IPC 0.239954
Core_2_branch_prediction_accuracy 90.9586
Core_2_branch_MPKI 16.4298
Core_2_average_ROB_occupancy_at_mispredict 57.0998
Core_2_L1D_total_access 33580
Core_2_L1D_total_hit 32664
Core_2_L1D_total_miss 916
Core_2_L1D_total_overlap_miss 916
Core_2_L1D_loads 19913
Core_2_L1D_load_hit 19010
Core_2_L1D_load_miss 903
Core_2_L1D_RFOs 13667
Core_2_L1D_RFO_hit 13654
Core_2_L1D_RFO_miss 13
Core_2_L1D_prefetches 0
Core_2_L1D_prefetch_hit 0
Core_2_L1D_prefetch_miss 0
Core_2_L1D_writebacks 0
Core_2_L1D_writeback_hit 0
Core_2_L1D_writeback_miss 0
Core_2_L1D_miss_rate 0.0272781
Core_2_L1D_MPKI 9.16
Core_2_L1D_demand_miss 916
Core_2_L1D_prefetch_requested 0
Core_2_L1D_prefetch_issued 0
Core_2_L1D_prefetch_useful 0
Core_2_L1D_prefetch_useless 0
Core_2_L1D_prefetch_late 0
Core_2_L1D_average_miss_latency 198.837
Core_2_L1D_active_cycles 272646
Core_2_L1D_active_hit_cycles 114617
Core_2_L1D_active_miss_cycles 173689
Core_2_L1D_active_pure_miss_cycles 158029
Core_2_L1D_active_hit_miss_overlap_cycles 15660
Core_2_L1D_total_pure_miss 916
Core_2_L1D_pure_miss_rate 0.0272781
Core_2_L1D_active_cycles_per_core 272646
Core_2_L1D_active_hit_cycles_per_core 114617
Core_2_L1D_active_miss_cycles_per_core 173689
Core_2_L1D_active_pure_miss_cycles_per_core 158029
Core_2_L1D_hit_miss_overlap_cycles_per_core 15660
Core_2_L1D_camat_per_core 8.1193
Core_2_L1I_total_access 18579
Core_2_L1I_total_hit 18389
Core_2_L1I_total_miss 190
Core_2_L1I_total_overlap_miss 190
Core_2_L1I_loads 18579
Core_2_L1I_load_hit 18389
Core_2_L1I_load_miss 190
Core_2_L1I_RFOs 0
Core_2_L1I_RFO_hit 0
Core_2_L1I_RFO_miss 0
Core_2_L1I_prefetches 0
Core_2_L1I_prefetch_hit 0
Core_2_L1I_prefetch_miss 0
Core_2_L1I_writebacks 0
Core_2_L1I_writeback_hit 0
Core_2_L1I_writeback_miss 0
Core_2_L1I_miss_rate 0.0102266
Core_2_L1I_MPKI 1.9
Core_2_L1I_demand_miss 190
Core_2_L1I_prefetch_requested 0
Core_2_L1I_prefetch_issued 0
Core_2_L1I_prefetch_useful 0
Core_2_L1I_prefetch_useless 0
Core_2_L1I_prefetch_late 0
Core_2_L1I_average_miss_latency 224.4
Core_2_L1I_active_cycles 44572
Core_2_L1I_active_hit_cycles 18441
Core_2_L1I_active_miss_cycles 26340
Core_2_L1I_active_pure_miss_cycles 26131
Core_2_L1I_active_hit_miss_overlap_cycles 209
Core_2_L1I_total_pure_miss 190
Core_2_L1I_pure_miss_rate 0.0102266
Core_2_L1I_active_cycles_per_core 44572
Core_2_L1I_active_hit_cycles_per_core 18441
Core_2_L1I_active_miss_cycles_per_core 26340
Core_2_L1I_active_pure_miss_cycles_per_core 26131
Core_2_L1I_hit_miss_overlap_cycles_per_core 209
Core_2_L1I_camat_per_core 2.39905
Core_2_L2C_total_access 1124
Core_2_L2C_total_hit 35
Core_2_L2C_total_miss 1089
Core_2_L2C_total_overlap_miss 1089
Core_2_L2C_loads 1093
Core_2_L2C_load_hit 16
Core_2_L2C_load_miss 1077
Core_2_L2C_RFOs 13
Core_2_L2C_RFO_hit 1
Core_2_L2C_RFO_miss 12
Core_2_L2C_prefetches 0
Core_2_L2C_prefetch_hit 0
Core_2_L2C_prefetch_miss 0
Core_2_L2C_writebacks 18
Core_2_L2C_writeback_hit 18
Core_2_L2C_writeback_miss 0
Core_2_L2C_miss_rate 0.968861
Core_2_L2C_MPKI 10.89
Core_2_L2C_demand_miss 1089
Core_2_L2C_prefetch_requested 0
Core_2_L2C_prefetch_issued 0
Core_2_L2C_prefetch_useful 0
Core_2_L2C_prefetch_useless 0
Core_2_L2C_prefetch_late 0
Core_2_L2C_average_miss_latency 190.23
Core_2_L2C_active_cycles 192886
Core_2_L2C_active_hit_cycles 13201
Core_2_L2C_active_miss_cycles 181642
Core_2_L2C_active_pure_miss_cycles 179685
Core_2_L2C_active_hit_miss_overlap_cycles 1957
Core_2_L2C_total_pure_miss 1089
Core_2_L2C_pure_miss_rate 0.968861
Core_2_L2C_active_cycles_per_core 192886
Core_2_L2C_active_hit_cycles_per_core 13201
Core_2_L2C_active_miss_cycles_per_core 181642
Core_2_L2C_active_pure_miss_cycles_per_core 179685
Core_2_L2C_hit_miss_overlap_cycles_per_core 1957
Core_2_L2C_camat_per_core 171.607
Core_2_LLC_total_access 1089
Core_2_LLC_total_hit 0
Core_2_LLC_total_miss 1089
Core_2_LLC_total_overlap_miss 1089
Core_2_LLC_loads 1077
Core_2_LLC_load_hit 0
Core_2_LLC_load_miss 1077
Core_2_LLC_RFOs 12
Core_2_LLC_RFO_hit 0
Core_2_LLC_RFO_miss 12
Core_2_LLC_prefetches 0
Core_2_LLC_prefetch_hit 0
Core_2_LLC_prefetch_miss 0
Core_2_LLC_writebacks 0
Core_2_LLC_writeback_hit 0
Core_2_LLC_writeback_miss 0
Core_2_LLC_miss_rate 1
Core_2_LLC_MPKI 10.89
Core_2_LLC_demand_miss 1089
Core_2_LLC_prefetch_requested 0
Core_2_LLC_prefetch_issued 0
Core_2_LLC_prefetch_useful 0
Core_2_LLC_prefetch_useless 0
Core_2_LLC_prefetch_late 0
Core_2_LLC_average_miss_latency 644.858
Core_2_LLC_active_cycles 246090
Core_2_LLC_active_hit_cycles 73716
Core_2_LLC_active_miss_cycles 236922
Core_2_LLC_active_pure_miss_cycles 172374
Core_2_LLC_active_hit_miss_overlap_cycles 64548
Core_2_LLC_total_pure_miss 1089
Core_2_LLC_pure_miss_rate 1
Core_2_LLC_active_cycles_per_core 172283
Core_2_LLC_active_hit_cycles_per_core 20787
Core_2_LLC_active_miss_cycles_per_core 153804
Core_2_LLC_active_pure_miss_cycles_per_core 151496
Core_2_LLC_hit_miss_overlap_cycles_per_core 2308
Core_2_LLC_camat_per_core 158.203
Core_2_major_page_fault 0
Core_2_minor_page_fault 156
Core_3_instructions 100000
Core_3_cycles 416781
Core_3_IPC 0.239934
Core_3_branch_prediction_accuracy 90.9586
Core_3_branch_MPKI 16.4339
Core_3_average_ROB_occupancy_at_mispredict 57.0529
Core_3_L1D_total_access 33577
Core_3_L1D_total_hit 32661
Core_3_L1D_total_miss 916
Core_3_L1D_total_overlap_miss 916
Core_3_L1D_loads 19909
Core_3_L1D_load_hit 19006
Core_3_L1D_load_miss 903
Core_3_L1D_RFOs 13668
Core_3_L1D_RFO_hit 13655
Core_3_L1D_RFO_miss 13
Core_3_L1D_prefetches 0
Core_3_L1D_prefetch_hit 0
Core_3_L1D_prefetch_miss 0
Core_3_L1D_writebacks 0
Core_3_L1D_writeback_hit 0
Core_3_L1D_writeback_miss 0
Core_3_L1D_miss_rate 0.0272806
Core_3_L1D_MPKI 9.16
Core_3_L1D_demand_miss 916
Core_3_L1D_prefetch_requested 0
Core_3_L1D_prefetch_issued 0
Core_3_L1D_prefetch_useful 0
Core_3_L1D_prefetch_useless 0
Core_3_L1D_prefetch_late 0
Core_3_L1D_average_miss_latency 198.222
Core_3_L1D_active_cycles 271615
Core_3_L1D_active_hit_cycles 114504
Core_3_L1D_active_miss_cycles 172718
Core_3_L1D_active_pure_miss_cycles 157111
Core_3_L1D_active_hit_miss_overlap_cycles 15607
Core_3_L1D_total_pure_miss 916
Core_3_L1D_pure_miss_rate 0.0272806
Core_3_L1D_active_cycles_per_core 271615
Core_3_L1D_active_hit_cycles_per_core 114504
Core_3_L1D_active_miss_cycles_per_core 172718
Core_3_L1D_active_pure_miss_cycles_per_core 157111
Core_3_L1D_hit_miss_overlap_cycles_per_core 15607
Core_3_L1D_camat_per_core 8.08932
Core_3_L1I_total_access 18579
Core_3_L1I_total_hit 18389
Core_3_L1I_total_miss 190
Core_3_L1I_total_overlap_miss 190
Core_3_L1I_loads 18579
Core_3_L1I_load_hit 18389
Core_3_L1I_load_miss 190
Core_3_L1I_RFOs 0
Core_3_L1I_RFO_hit 0
Core_3_L1I_RFO_miss 0
Core_3_L1I_prefetches 0
Core_3_L1I_prefetch_hit 0
Core_3_L1I_prefetch_miss 0
Core_3_L1I_writebacks 0
Core_3_L1I_writeback_hit 0
Core_3_L1I_writeback_miss 0
Core_3_L1I_miss_rate 0.0102266
Core_3_L1I_MPKI 1.9
Core_3_L1I_demand_miss 190
Core_3_L1I_prefetch_requested 0
Core_3_L1I_prefetch_issued 0
Core_3_L1I_prefetch_useful 0
Core_3_L1I_prefetch_useless 0
Core_3_L1I_prefetch_late 0
Core_3_L1I_average_miss_latency 238.363
Core_3_L1I_active_cycles 45384
Core_3_L1I_active_hit_cycles 18441
Core_3_L1I_active_miss_cycles 27152
Core_3_L1I_active_pure_miss_cycles 26943
Core_3_L1I_active_hit_miss_overlap_cycles 209
Core_3_L1I_total_pure_miss 190
Core_3_L1I_pure_miss_rate 0.0102266
Core_3_L1I_active_cycles_per_core 45384
Core_3_L1I_active_hit_cycles_per_core 18441
Core_3_L1I_active_miss_cycles_per_core 27152
Core_3_L1I_active_pure_miss_cycles_per_core 26943
Core_3_L1I_hit_miss_overlap_cycles_per_core 209
Core_3_L1I_camat_per_core 2.44276
Core_3_L2C_total_access 1124
Core_3_L2C_total_hit 35
Core_3_L2C_total_miss 1089
Core_3_L2C_total_overlap_miss 1089
Core_3_L2C_loads 1093
Core_3_L2C_load_hit 16
Core_3_L2C_load_miss 1077
Core_3_L2C_RFOs 13
Core_3_L2C_RFO_hit 1
Core_3_L2C_RFO_miss 12
Core_3_L2C_prefetches 0
Core_3_L2C_prefetch_hit 0