From ac1633675f42c6758b428ec0e43e0685f9c6958c Mon Sep 17 00:00:00 2001 From: Scott Nellenbach Date: Sat, 15 Jun 2019 21:39:19 -0400 Subject: [PATCH] restructured reset handling in rtl output so signals w/o reset are moved out of else block (part of issue #62) --- src/ordt/output/FieldProperties.java | 1 - .../SystemVerilogDecodeModule.java | 35 +- .../common/SystemVerilogRegisters.java | 107 +++-- .../basic_tests/rdl_basic_01/golden/output.sv | 32 +- test/basic_tests/rdl_basic_01/golden/output.v | 32 +- .../rdl_fieldstruct/golden/output.sv | 36 +- .../rdl_fieldstruct/golden/output.v | 36 +- test/basic_tests/rdl_hello/golden/output.sv | 14 +- test/basic_tests/rdl_hello/golden/output.v | 14 +- test/basic_tests/rdl_hier_01/golden/output.sv | 178 ++++---- test/basic_tests/rdl_hier_01/golden/output.v | 178 ++++---- test/basic_tests/rdl_hier_02/golden/output.sv | 430 ++++++++---------- test/basic_tests/rdl_hier_02/golden/output.v | 430 ++++++++---------- test/basic_tests/rdl_intr_01/golden/output.sv | 14 +- test/basic_tests/rdl_intr_01/golden/output.v | 14 +- test/basic_tests/rdl_iwrap/golden/output.sv | 10 +- test/basic_tests/rdl_iwrap/golden/output.v | 10 +- test/basic_tests/rdl_sec_if/golden/output.sv | 420 +++++++++-------- test/basic_tests/rdl_sec_if/golden/output.v | 420 +++++++++-------- .../rdl_uvmmem_default/golden/output.sv | 10 +- .../rdl_uvmmem_default/golden/output.v | 10 +- .../rdl_uvmmem_lite/golden/output.sv | 10 +- .../rdl_uvmmem_lite/golden/output.v | 10 +- .../rdl_uvmmem_mimic/golden/output.sv | 10 +- .../rdl_uvmmem_mimic/golden/output.v | 10 +- .../rdl_uvmmem_nums/golden/output.sv | 10 +- .../rdl_uvmmem_nums/golden/output.v | 10 +- .../rdl_write_enable/golden/output.sv | 36 +- .../rdl_write_enable/golden/output.v | 36 +- 29 files changed, 1151 insertions(+), 1412 deletions(-) diff --git a/src/ordt/output/FieldProperties.java b/src/ordt/output/FieldProperties.java index b006aeb..94b7bb2 100644 --- a/src/ordt/output/FieldProperties.java +++ b/src/ordt/output/FieldProperties.java @@ -329,7 +329,6 @@ else if (pList.hasProperty("dontcompare")) { // set interrupt enable/mask reference if (pList.hasProperty("enable")) { - if (getInstancePath().contains("global")) System.out.println("FieldProperties extractProperties: setting enable on inst=" + getInstancePath() + ", enable=" + pList.getProperty("enable") ); setRef(RhsRefType.INTR_ENABLE, pList.getProperty("enable"), pList.getDepth("enable")); } else if (pList.hasProperty("mask")) { diff --git a/src/ordt/output/systemverilog/SystemVerilogDecodeModule.java b/src/ordt/output/systemverilog/SystemVerilogDecodeModule.java index 33f57d8..140410d 100644 --- a/src/ordt/output/systemverilog/SystemVerilogDecodeModule.java +++ b/src/ordt/output/systemverilog/SystemVerilogDecodeModule.java @@ -177,8 +177,6 @@ private String getGroupPrefix(boolean isPrimary) { /** generate common internal pio interface code */ private void generateCommonPio(AddressableInstanceProperties topRegProperties) { String grpName = "pio i/f"; - String rstGrpName = "pio i/f (reset signal = " + builder.getDefaultReset() + ")"; - String optGrpName = (ExtParameters.sysVerResetAllOutputs())? rstGrpName : grpName; // selectable block group // add internal registered input sigs this.addScalarReg("pio_write_active"); // write indication @@ -187,19 +185,19 @@ private void generateCommonPio(AddressableInstanceProperties topRegProperties) { this.addVectorReg("pio_dec_write_data_d1", 0, builder.getMaxRegWidth()); // input write data capture register // pio read/write actives - enabled by ext re/we and disabled when ack/nack - this.addResetAssign(rstGrpName, builder.getDefaultReset(), "pio_write_active <= " + ExtParameters.sysVerSequentialAssignDelayString() + " 1'b0;"); - this.addResetAssign(rstGrpName, builder.getDefaultReset(), "pio_read_active <= " + ExtParameters.sysVerSequentialAssignDelayString() + " 1'b0;"); - this.addRegAssign(rstGrpName, "pio_write_active <= " + ExtParameters.sysVerSequentialAssignDelayString() + " pio_write_active ? pio_no_acks : pio_activate_write;"); // active stays high until ack/nack - this.addRegAssign(rstGrpName, "pio_read_active <= " + ExtParameters.sysVerSequentialAssignDelayString() + " pio_read_active ? pio_no_acks : pio_activate_read;"); + this.addResetAssign(grpName, builder.getDefaultReset(), "pio_write_active <= " + ExtParameters.sysVerSequentialAssignDelayString() + " 1'b0;"); + this.addResetAssign(grpName, builder.getDefaultReset(), "pio_read_active <= " + ExtParameters.sysVerSequentialAssignDelayString() + " 1'b0;"); + this.addRegAssign(grpName, "pio_write_active <= " + ExtParameters.sysVerSequentialAssignDelayString() + " pio_write_active ? pio_no_acks : pio_activate_write;"); // active stays high until ack/nack + this.addRegAssign(grpName, "pio_read_active <= " + ExtParameters.sysVerSequentialAssignDelayString() + " pio_read_active ? pio_no_acks : pio_activate_read;"); if (mapHasMultipleAddresses()) { if (ExtParameters.sysVerResetAllOutputs()) - this.addResetAssign(rstGrpName, builder.getDefaultReset(), "pio_dec_address_d1 <= " + ExtParameters.sysVerSequentialAssignDelayString() + " " + builder.getMapAddressWidth() + "'b0;" ); - this.addRegAssign(optGrpName, "pio_dec_address_d1 <= " + ExtParameters.sysVerSequentialAssignDelayString() + " " + pioInterfaceAddressName + ";"); // capture address if new transaction + this.addResetAssign(grpName, builder.getDefaultReset(), "pio_dec_address_d1 <= " + ExtParameters.sysVerSequentialAssignDelayString() + " " + builder.getMapAddressWidth() + "'b0;" ); + this.addRegAssign(grpName, "pio_dec_address_d1 <= " + ExtParameters.sysVerSequentialAssignDelayString() + " " + pioInterfaceAddressName + ";"); // capture address if new transaction } if (ExtParameters.sysVerResetAllOutputs()) - this.addResetAssign(rstGrpName, builder.getDefaultReset(), "pio_dec_write_data_d1 <= " + ExtParameters.sysVerSequentialAssignDelayString() + " " + builder.getMaxRegWidth() + "'b0;" ); - this.addRegAssign(optGrpName, "pio_dec_write_data_d1 <= " + ExtParameters.sysVerSequentialAssignDelayString() + " " + pioInterfaceWriteDataName + ";"); // capture write data if new transaction + this.addResetAssign(grpName, builder.getDefaultReset(), "pio_dec_write_data_d1 <= " + ExtParameters.sysVerSequentialAssignDelayString() + " " + builder.getMaxRegWidth() + "'b0;" ); + this.addRegAssign(grpName, "pio_dec_write_data_d1 <= " + ExtParameters.sysVerSequentialAssignDelayString() + " " + pioInterfaceWriteDataName + ";"); // capture write data if new transaction // if write enables are specified, then capture if (hasWriteEnables()) { @@ -217,8 +215,8 @@ private void generateCommonPio(AddressableInstanceProperties topRegProperties) { this.addVectorReg("pio_dec_trans_size_d1", 0, builder.getMaxWordBitSize()); // input trans size capture register this.addRegAssign(grpName, "pio_dec_trans_size_d1 <= " + ExtParameters.sysVerSequentialAssignDelayString() + " " + pioInterfaceTransactionSizeName + ";"); // capture trans size if new transaction this.addVectorReg(pioInterfaceRetTransactionSizeName, 0, builder.getMaxWordBitSize()); // register the size - this.addResetAssign(rstGrpName, builder.getDefaultReset(), pioInterfaceRetTransactionSizeName + " <= " + ExtParameters.sysVerSequentialAssignDelayString() + "" + builder.getMaxWordBitSize() + "'b0;"); // reset for delayed block select - this.addRegAssign(rstGrpName, pioInterfaceRetTransactionSizeName + " <= " + ExtParameters.sysVerSequentialAssignDelayString() + "reg_width;"); // use pio_width from decode to set + this.addResetAssign(grpName, builder.getDefaultReset(), pioInterfaceRetTransactionSizeName + " <= " + ExtParameters.sysVerSequentialAssignDelayString() + "" + builder.getMaxWordBitSize() + "'b0;"); // reset for delayed block select + this.addRegAssign(grpName, pioInterfaceRetTransactionSizeName + " <= " + ExtParameters.sysVerSequentialAssignDelayString() + "reg_width;"); // use pio_width from decode to set this.addVectorReg("reg_width", 0, builder.getMaxWordBitSize()); // size of current register } @@ -2554,7 +2552,6 @@ private ExternalInterfaceInfo generateBaseExternalInterface(AddressableInstanceP String intHwToDecodeTransactionSizeName = addrInstProperties.getFullSignalName(DefSignalType.H2D_RETSIZE) + "_d1"; // size of return read transaction in words String grpName = "external i/f"; - String rstGrpName = "external i/f (reset signal = " + builder.getDefaultReset() + ")"; // register the outputs and assign output reg values this.addVectorReg(extIf.decodeToHwName, 0, addrInstProperties.getMaxRegWidth()); @@ -2568,14 +2565,14 @@ private ExternalInterfaceInfo generateBaseExternalInterface(AddressableInstanceP this.addScalarReg(intDecodeToHwWeName); this.addScalarReg(intDecodeToHwReName); // reset output signals - this.addResetAssign(rstGrpName, builder.getDefaultReset(), extIf.decodeToHwWeName + " <= " + ExtParameters.sysVerSequentialAssignDelayString() + " 1'b0;" ); - this.addResetAssign(rstGrpName, builder.getDefaultReset(), extIf.decodeToHwReName + " <= " + ExtParameters.sysVerSequentialAssignDelayString() + " 1'b0;" ); + this.addResetAssign(grpName, builder.getDefaultReset(), extIf.decodeToHwWeName + " <= " + ExtParameters.sysVerSequentialAssignDelayString() + " 1'b0;" ); + this.addResetAssign(grpName, builder.getDefaultReset(), extIf.decodeToHwReName + " <= " + ExtParameters.sysVerSequentialAssignDelayString() + " 1'b0;" ); String ackInhibitStr = "~" + extIf.hwToDecodeAckName + " & ~" + extIf.hwToDecodeNackName; this.addRegAssign(grpName, extIf.decodeToHwName + " <= " + ExtParameters.sysVerSequentialAssignDelayString() + " " + intDecodeToHwName + ";"); // assign next to flop if (hasWriteEnables()) this.addRegAssign(grpName, extIf.decodeToHwEnableName + " <= " + ExtParameters.sysVerSequentialAssignDelayString() + " " + intDecodeToHwEnableName + ";"); // assign next to flop - this.addRegAssign(rstGrpName, extIf.decodeToHwWeName + " <= " + ExtParameters.sysVerSequentialAssignDelayString() + " " + intDecodeToHwWeName + " & " + ackInhibitStr + ";"); // assign next to flop - this.addRegAssign(rstGrpName, extIf.decodeToHwReName + " <= " + ExtParameters.sysVerSequentialAssignDelayString() + " " + intDecodeToHwReName + " & " + ackInhibitStr + ";"); // assign next to flop + this.addRegAssign(grpName, extIf.decodeToHwWeName + " <= " + ExtParameters.sysVerSequentialAssignDelayString() + " " + intDecodeToHwWeName + " & " + ackInhibitStr + ";"); // assign next to flop + this.addRegAssign(grpName, extIf.decodeToHwReName + " <= " + ExtParameters.sysVerSequentialAssignDelayString() + " " + intDecodeToHwReName + " & " + ackInhibitStr + ";"); // assign next to flop // if size of external range is greater than one reg we'll need an external address if (addrInstProperties.hasExtAddress()) { @@ -2594,8 +2591,8 @@ private ExternalInterfaceInfo generateBaseExternalInterface(AddressableInstanceP this.addRegAssign(grpName, extIf.decodeToHwTransactionSizeName + " <= " + ExtParameters.sysVerSequentialAssignDelayString() + " " + intDecodeToHwTransactionSizeName + ";"); // assign next to flop this.addVectorReg(intHwToDecodeTransactionSizeName, 0, regWordBits); - this.addResetAssign(rstGrpName, builder.getDefaultReset(), intHwToDecodeTransactionSizeName + " <= " + ExtParameters.sysVerSequentialAssignDelayString() + " " + regWordBits +"'b0;"); // reset input size flop - this.addRegAssign(rstGrpName, intHwToDecodeTransactionSizeName + " <= " + ExtParameters.sysVerSequentialAssignDelayString() + " " + extIf.hwToDecodeTransactionSizeName + ";"); // assign input size to flop + this.addResetAssign(grpName, builder.getDefaultReset(), intHwToDecodeTransactionSizeName + " <= " + ExtParameters.sysVerSequentialAssignDelayString() + " " + regWordBits +"'b0;"); // reset input size flop + this.addRegAssign(grpName, intHwToDecodeTransactionSizeName + " <= " + ExtParameters.sysVerSequentialAssignDelayString() + " " + extIf.hwToDecodeTransactionSizeName + ";"); // assign input size to flop } return extIf; } diff --git a/src/ordt/output/systemverilog/common/SystemVerilogRegisters.java b/src/ordt/output/systemverilog/common/SystemVerilogRegisters.java index bc0bfae..3423755 100644 --- a/src/ordt/output/systemverilog/common/SystemVerilogRegisters.java +++ b/src/ordt/output/systemverilog/common/SystemVerilogRegisters.java @@ -5,8 +5,11 @@ import java.util.ArrayList; import java.util.HashMap; +import java.util.HashSet; import java.util.Iterator; import java.util.List; +import java.util.regex.Matcher; +import java.util.regex.Pattern; import ordt.output.common.MsgUtils; import ordt.output.common.OutputWriterIntf; @@ -61,6 +64,16 @@ public void addReset(String reset, boolean activeLow) { public HashMap getResets() { return resetActiveLow; } + + /** write out verilog for this set of regs + * @param resolveNames */ + public void writeVerilog(int indentLevel) { + for (String regName: registers.keySet()) { + registers.get(regName).writeVerilog(indentLevel); + } + } + + // ------------------------------ /** inner class to hold verilog info associated with a register group */ public class VerilogRegInfo { @@ -71,6 +84,8 @@ public class VerilogRegInfo { private List combinAssignList; // list of combinatorial assign statements private List hiPrecCombinAssignList; // list of high precedence combinatorial assign statements private List lowPrecCombinAssignList; // list of low precedence combinatorial assign statements + private HashSet signalsWithResetAssigns; // set of signals having a reset assign + private boolean hasSimpleRegAssigns = true; // allow refactoring is only simple assigns /** * @param name - name of this reg group @@ -83,10 +98,10 @@ public VerilogRegInfo(String name) { this.combinAssignList = new ArrayList(); // list of combinatorial assign statements this.hiPrecCombinAssignList = new ArrayList(); // list of high precedence combinatorial assign statements this.lowPrecCombinAssignList = new ArrayList(); // list of low precedence combinatorial assign statements + this.signalsWithResetAssigns= new HashSet(); // set of signals having a reset assign } - /** get name - * @return the name - */ + + /** get name of this group */ public String getName() { return name; } @@ -128,14 +143,34 @@ else if (!resetActiveLow.containsKey(reset)) { } // add the assign stmt resetAssignList.get(reset).add(stmt); + // save signals with reset assingment + String assignedSignal = extractAssignedSignalName(stmt); + if (assignedSignal != null) signalsWithResetAssigns.add(assignedSignal); } + /* extract assigned signal name from a sequential assignment string */ + private String extractAssignedSignalName(String stmt) { + Pattern p = Pattern.compile("^\\s*(\\S+)\\s*<=\\s*"); + Matcher m = p.matcher(stmt); + if (m.find()) { + String sigName = m.group(1); + return sigName; + } + return null; + } + /** add a sync register assignment * @param stmt - verilog assignment statement */ public void addRegAssign(String stmt) { // add the assign stmt regAssignList.add(stmt); + // check for non-simple forms that can not be refactored + String assignedSignal = extractAssignedSignalName(stmt); + if (assignedSignal == null) { + hasSimpleRegAssigns = false; + //System.out.println("VerilogRegInfo addRegAssign: non-simple stmt=" + stmt); + } } /** add a list of reg assigns */ public void addRegAssign(List stmts) { @@ -155,6 +190,11 @@ public void addCombinAssign(List stmts) { // add the assign stmt combinAssignList.addAll(stmts); } + + private boolean hasResetAssigns() { + return !resetAssignList.isEmpty(); + } + /** add a combinatorial assignment to one of the hi/low precedence lists * @param hiPrecedence - true if this statement will have high priority * @param stmt - verilog assignment statement @@ -166,8 +206,7 @@ public void addPrecCombinAssign(boolean hiPrecedence, String stmt) { else lowPrecCombinAssignList.add(stmt); } - /** write out high precedence verilog for this reg/group - * @param resolveNames */ + /** write out high precedence verilog for this reg/group */ private void writeHiPrecedenceStatements(int indentLevel) { if (!hiPrecCombinAssignList.isEmpty()) { Iterator it = hiPrecCombinAssignList.iterator(); @@ -177,8 +216,7 @@ private void writeHiPrecedenceStatements(int indentLevel) { } } - /** write out low precedence verilog for this reg/group - * @param resolveNames */ + /** write out low precedence verilog for this reg/group */ private void writeLowPrecedenceStatements(int indentLevel) { if (!lowPrecCombinAssignList.isEmpty()) { Iterator it = lowPrecCombinAssignList.iterator(); @@ -188,8 +226,7 @@ private void writeLowPrecedenceStatements(int indentLevel) { } } - /** write out verilog for this reg/group - * @param resolveNames */ + /** write out verilog for this reg/group */ public void writeVerilog(int indentLevel) { // write combinatorial assignment block @@ -211,12 +248,13 @@ public void writeVerilog(int indentLevel) { // write synchronous assignment block if (!regAssignList.isEmpty()) { + //System.out.println("VerilogRegInfo writeVerilog: assigned reset sigs=" + signalsWithResetAssigns); writer.writeStmt(indentLevel, "//------- reg assigns for " + name); String asyncStr = useAsyncResets? genAsyncString() : ""; if (SystemVerilogModule.isLegacyVerilog()) writer.writeStmt(indentLevel++, "always @ (posedge " + clkName + asyncStr + ") begin"); else writer.writeStmt(indentLevel++, "always_ff @ (posedge " + clkName + asyncStr + ") begin"); - boolean hasResets = writeRegResets(indentLevel, resetAssignList); - writeRegAssigns(indentLevel, hasResets, regAssignList); + writeRegResets(indentLevel, resetAssignList); + writeRegAssigns(indentLevel, regAssignList); writer.writeStmt(--indentLevel, "end"); writer.writeStmt(indentLevel, ""); } @@ -231,50 +269,51 @@ private String genAsyncString() { } return outStr; } - /** write always block reset stmts - * @param resolveNames */ - private boolean writeRegResets(int indentLevel, HashMap> regResetList) { + /** write always block reset stmts */ + private void writeRegResets(int indentLevel, HashMap> regResetList) { // write reset assigns for each reset signal String firstRst = ""; - boolean hasResets = false; for (String reset: regResetList.keySet()) { if (!regResetList.get(reset).isEmpty()) { String notStr = (resetActiveLow.get(reset)) ? "! " : ""; - hasResets = true; writer.writeStmt(indentLevel++, firstRst + "if (" + notStr + reset + ") begin"); firstRst = "else "; Iterator it = regResetList.get(reset).iterator(); while (it.hasNext()) { - String elem = it.next(); - writer.writeStmt(indentLevel, elem); + String stmt = it.next(); + writer.writeStmt(indentLevel, stmt); } writer.writeStmt(--indentLevel, "end"); } } - return hasResets; } - /** write always block assign stmts - * @param resolveNames */ - private void writeRegAssigns(int indentLevel, boolean hasResets, List regAssignList) { + /** write always block assign stmts */ + private void writeRegAssigns(int indentLevel, List regAssignList) { if (regAssignList.isEmpty()) return; + boolean hasResets = hasResetAssigns(); + List movedAssignList = new ArrayList(); if (hasResets) writer.writeStmt(indentLevel++, "else begin"); Iterator it = regAssignList.iterator(); while (it.hasNext()) { - String elem = it.next(); - writer.writeStmt(indentLevel, elem); + String stmt = it.next(); + // if simple form, move signals without reset assign out of else block + String assignedSignal = extractAssignedSignalName(stmt); + if (hasSimpleRegAssigns && hasResets && !signalsWithResetAssigns.contains(assignedSignal)) { + //System.out.println("VerilogRegInfo writeRegAssigns: signal=" + assignedSignal + " has no reset and will be moved out of else block"); + movedAssignList.add(stmt); + } + else writer.writeStmt(indentLevel, stmt); + } + if (hasResets) writer.writeStmt(--indentLevel, "end"); + // move non-reset assigns out of else block + it = movedAssignList.iterator(); + while (it.hasNext()) { + String stmt = it.next(); + writer.writeStmt(indentLevel, stmt); } - if (hasResets) writer.writeStmt(--indentLevel, "end"); } - } + } // end VerilogRegInfo - /** write out verilog for this set of regs - * @param resolveNames */ - public void writeVerilog(int indentLevel) { - for (String regName: registers.keySet()) { - registers.get(regName).writeVerilog(indentLevel); - } - } - } diff --git a/test/basic_tests/rdl_basic_01/golden/output.sv b/test/basic_tests/rdl_basic_01/golden/output.sv index 0c56b2f..559234e 100644 --- a/test/basic_tests/rdl_basic_01/golden/output.sv +++ b/test/basic_tests/rdl_basic_01/golden/output.sv @@ -1,7 +1,7 @@ -// Ordt 190606.01 autogenerated file +// Ordt 190615.01 autogenerated file // Input: ./rdl_basic_01/test.rdl // Parms: ./rdl_basic_01/test.parms -// Date: Thu Jun 06 13:30:54 EDT 2019 +// Date: Sat Jun 15 21:05:39 EDT 2019 // // @@ -755,8 +755,8 @@ module simple1_jrdl_logic end else begin rg_rdr_roll32_counter_reg_count <= #1 reg_rdr_roll32_counter_reg_count_next; - l2h_rdr_roll32_counter_reg_count_overflow_o <= #1 cntr_rdr_roll32_counter_reg_count_next[4] & ~l2h_rdr_roll32_counter_reg_count_overflow_o; end + l2h_rdr_roll32_counter_reg_count_overflow_o <= #1 cntr_rdr_roll32_counter_reg_count_next[4] & ~l2h_rdr_roll32_counter_reg_count_overflow_o; end //------- combinatorial assigns for rdr_sat32_counter_reg (pio read data) @@ -1103,19 +1103,7 @@ module simple1_jrdl_decode end end - //------- reg assigns for external i/f (reset signal = reset) - always_ff @ (posedge clk) begin - if (reset) begin - d2h_rdr_cp_fp_wr_we_ex <= #1 1'b0; - d2h_rdr_cp_fp_wr_re_ex <= #1 1'b0; - end - else begin - d2h_rdr_cp_fp_wr_we_ex <= #1 d2h_rdr_cp_fp_wr_we_next & ~h2d_rdr_cp_fp_wr_ack_ex & ~h2d_rdr_cp_fp_wr_nack_ex; - d2h_rdr_cp_fp_wr_re_ex <= #1 d2h_rdr_cp_fp_wr_re_next & ~h2d_rdr_cp_fp_wr_ack_ex & ~h2d_rdr_cp_fp_wr_nack_ex; - end - end - - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always_ff @ (posedge clk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -1127,10 +1115,6 @@ module simple1_jrdl_decode pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; dec_pio_trans_size <= #1 reg_width; end - end - - //------- reg assigns for pio i/f - always_ff @ (posedge clk) begin pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; pio_dec_trans_size_d1 <= #1 pio_dec_trans_size; @@ -1138,6 +1122,14 @@ module simple1_jrdl_decode //------- reg assigns for external i/f always_ff @ (posedge clk) begin + if (reset) begin + d2h_rdr_cp_fp_wr_we_ex <= #1 1'b0; + d2h_rdr_cp_fp_wr_re_ex <= #1 1'b0; + end + else begin + d2h_rdr_cp_fp_wr_we_ex <= #1 d2h_rdr_cp_fp_wr_we_next & ~h2d_rdr_cp_fp_wr_ack_ex & ~h2d_rdr_cp_fp_wr_nack_ex; + d2h_rdr_cp_fp_wr_re_ex <= #1 d2h_rdr_cp_fp_wr_re_next & ~h2d_rdr_cp_fp_wr_ack_ex & ~h2d_rdr_cp_fp_wr_nack_ex; + end d2h_rdr_cp_fp_wr_w_ex <= #1 d2h_rdr_cp_fp_wr_w_next; d2h_rdr_cp_fp_wr_addr_ex <= #1 d2h_rdr_cp_fp_wr_addr_next; end diff --git a/test/basic_tests/rdl_basic_01/golden/output.v b/test/basic_tests/rdl_basic_01/golden/output.v index 556b0b8..0bfcca2 100644 --- a/test/basic_tests/rdl_basic_01/golden/output.v +++ b/test/basic_tests/rdl_basic_01/golden/output.v @@ -1,7 +1,7 @@ -// Ordt 190606.01 autogenerated file +// Ordt 190615.01 autogenerated file // Input: ./rdl_basic_01/test.rdl // Parms: ./rdl_basic_01/test.parms -// Date: Thu Jun 06 13:30:54 EDT 2019 +// Date: Sat Jun 15 21:05:39 EDT 2019 // // @@ -755,8 +755,8 @@ module simple1_jrdl_logic end else begin rg_rdr_roll32_counter_reg_count <= #1 reg_rdr_roll32_counter_reg_count_next; - l2h_rdr_roll32_counter_reg_count_overflow_o <= #1 cntr_rdr_roll32_counter_reg_count_next[4] & ~l2h_rdr_roll32_counter_reg_count_overflow_o; end + l2h_rdr_roll32_counter_reg_count_overflow_o <= #1 cntr_rdr_roll32_counter_reg_count_next[4] & ~l2h_rdr_roll32_counter_reg_count_overflow_o; end //------- combinatorial assigns for rdr_sat32_counter_reg (pio read data) @@ -1103,19 +1103,7 @@ module simple1_jrdl_decode end end - //------- reg assigns for external i/f (reset signal = reset) - always @ (posedge clk) begin - if (reset) begin - d2h_rdr_cp_fp_wr_we_ex <= #1 1'b0; - d2h_rdr_cp_fp_wr_re_ex <= #1 1'b0; - end - else begin - d2h_rdr_cp_fp_wr_we_ex <= #1 d2h_rdr_cp_fp_wr_we_next & ~h2d_rdr_cp_fp_wr_ack_ex & ~h2d_rdr_cp_fp_wr_nack_ex; - d2h_rdr_cp_fp_wr_re_ex <= #1 d2h_rdr_cp_fp_wr_re_next & ~h2d_rdr_cp_fp_wr_ack_ex & ~h2d_rdr_cp_fp_wr_nack_ex; - end - end - - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always @ (posedge clk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -1127,10 +1115,6 @@ module simple1_jrdl_decode pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; dec_pio_trans_size <= #1 reg_width; end - end - - //------- reg assigns for pio i/f - always @ (posedge clk) begin pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; pio_dec_trans_size_d1 <= #1 pio_dec_trans_size; @@ -1138,6 +1122,14 @@ module simple1_jrdl_decode //------- reg assigns for external i/f always @ (posedge clk) begin + if (reset) begin + d2h_rdr_cp_fp_wr_we_ex <= #1 1'b0; + d2h_rdr_cp_fp_wr_re_ex <= #1 1'b0; + end + else begin + d2h_rdr_cp_fp_wr_we_ex <= #1 d2h_rdr_cp_fp_wr_we_next & ~h2d_rdr_cp_fp_wr_ack_ex & ~h2d_rdr_cp_fp_wr_nack_ex; + d2h_rdr_cp_fp_wr_re_ex <= #1 d2h_rdr_cp_fp_wr_re_next & ~h2d_rdr_cp_fp_wr_ack_ex & ~h2d_rdr_cp_fp_wr_nack_ex; + end d2h_rdr_cp_fp_wr_w_ex <= #1 d2h_rdr_cp_fp_wr_w_next; d2h_rdr_cp_fp_wr_addr_ex <= #1 d2h_rdr_cp_fp_wr_addr_next; end diff --git a/test/basic_tests/rdl_fieldstruct/golden/output.sv b/test/basic_tests/rdl_fieldstruct/golden/output.sv index 9caef27..f6bf946 100644 --- a/test/basic_tests/rdl_fieldstruct/golden/output.sv +++ b/test/basic_tests/rdl_fieldstruct/golden/output.sv @@ -1,7 +1,7 @@ -// Ordt 190606.01 autogenerated file +// Ordt 190615.01 autogenerated file // Input: ./rdl_fieldstruct/test.rdl // Parms: ./rdl_fieldstruct/test.parms -// Date: Thu Jun 06 13:30:55 EDT 2019 +// Date: Sat Jun 15 21:05:40 EDT 2019 // // @@ -278,13 +278,13 @@ module foo_jrdl_logic end else begin rg_areg_0_hier_fs_fs1_fld1 <= #1 reg_areg_0_hier_fs_fs1_fld1_next; - rg_areg_0_hier_fs_fs1_fld2 <= #1 reg_areg_0_hier_fs_fs1_fld2_next; - rg_areg_0_hier_fs_fld1 <= #1 reg_areg_0_hier_fs_fld1_next; rg_areg_0_hier_fs_fs2_fld1 <= #1 reg_areg_0_hier_fs_fs2_fld1_next; - rg_areg_0_hier_fs_fs2_fld2 <= #1 reg_areg_0_hier_fs_fs2_fld2_next; rg_areg_0_fs3_fld1 <= #1 reg_areg_0_fs3_fld1_next; - rg_areg_0_fs3_fld2 <= #1 reg_areg_0_fs3_fld2_next; end + rg_areg_0_hier_fs_fs1_fld2 <= #1 reg_areg_0_hier_fs_fs1_fld2_next; + rg_areg_0_hier_fs_fld1 <= #1 reg_areg_0_hier_fs_fld1_next; + rg_areg_0_hier_fs_fs2_fld2 <= #1 reg_areg_0_hier_fs_fs2_fld2_next; + rg_areg_0_fs3_fld2 <= #1 reg_areg_0_fs3_fld2_next; end //------- combinatorial assigns for areg_0 (pio read data) @@ -336,13 +336,13 @@ module foo_jrdl_logic end else begin rg_areg_1_hier_fs_fs1_fld1 <= #1 reg_areg_1_hier_fs_fs1_fld1_next; - rg_areg_1_hier_fs_fs1_fld2 <= #1 reg_areg_1_hier_fs_fs1_fld2_next; - rg_areg_1_hier_fs_fld1 <= #1 reg_areg_1_hier_fs_fld1_next; rg_areg_1_hier_fs_fs2_fld1 <= #1 reg_areg_1_hier_fs_fs2_fld1_next; - rg_areg_1_hier_fs_fs2_fld2 <= #1 reg_areg_1_hier_fs_fs2_fld2_next; rg_areg_1_fs3_fld1 <= #1 reg_areg_1_fs3_fld1_next; - rg_areg_1_fs3_fld2 <= #1 reg_areg_1_fs3_fld2_next; end + rg_areg_1_hier_fs_fs1_fld2 <= #1 reg_areg_1_hier_fs_fs1_fld2_next; + rg_areg_1_hier_fs_fld1 <= #1 reg_areg_1_hier_fs_fld1_next; + rg_areg_1_hier_fs_fs2_fld2 <= #1 reg_areg_1_hier_fs_fs2_fld2_next; + rg_areg_1_fs3_fld2 <= #1 reg_areg_1_fs3_fld2_next; end //------- combinatorial assigns for blabla @@ -395,16 +395,16 @@ module foo_jrdl_logic end else begin rg_blabla_fs1_0_fld1 <= #1 reg_blabla_fs1_0_fld1_next; - rg_blabla_fs1_0_fld2 <= #1 reg_blabla_fs1_0_fld2_next; rg_blabla_fs1_1_fld1 <= #1 reg_blabla_fs1_1_fld1_next; - rg_blabla_fs1_1_fld2 <= #1 reg_blabla_fs1_1_fld2_next; rg_blabla_fs1_2_fld1 <= #1 reg_blabla_fs1_2_fld1_next; - rg_blabla_fs1_2_fld2 <= #1 reg_blabla_fs1_2_fld2_next; rg_blabla_fs3_0_fld1 <= #1 reg_blabla_fs3_0_fld1_next; - rg_blabla_fs3_0_fld2 <= #1 reg_blabla_fs3_0_fld2_next; rg_blabla_fs3_1_fld1 <= #1 reg_blabla_fs3_1_fld1_next; - rg_blabla_fs3_1_fld2 <= #1 reg_blabla_fs3_1_fld2_next; end + rg_blabla_fs1_0_fld2 <= #1 reg_blabla_fs1_0_fld2_next; + rg_blabla_fs1_1_fld2 <= #1 reg_blabla_fs1_1_fld2_next; + rg_blabla_fs1_2_fld2 <= #1 reg_blabla_fs1_2_fld2_next; + rg_blabla_fs3_0_fld2 <= #1 reg_blabla_fs3_0_fld2_next; + rg_blabla_fs3_1_fld2 <= #1 reg_blabla_fs3_1_fld2_next; end endmodule @@ -556,7 +556,7 @@ module foo_jrdl_decode end end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always_ff @ (posedge clk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -566,10 +566,6 @@ module foo_jrdl_decode pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; end - end - - //------- reg assigns for pio i/f - always_ff @ (posedge clk) begin pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; end diff --git a/test/basic_tests/rdl_fieldstruct/golden/output.v b/test/basic_tests/rdl_fieldstruct/golden/output.v index b2c31d3..85d2d12 100644 --- a/test/basic_tests/rdl_fieldstruct/golden/output.v +++ b/test/basic_tests/rdl_fieldstruct/golden/output.v @@ -1,7 +1,7 @@ -// Ordt 190606.01 autogenerated file +// Ordt 190615.01 autogenerated file // Input: ./rdl_fieldstruct/test.rdl // Parms: ./rdl_fieldstruct/test.parms -// Date: Thu Jun 06 13:30:55 EDT 2019 +// Date: Sat Jun 15 21:05:40 EDT 2019 // // @@ -278,13 +278,13 @@ module foo_jrdl_logic end else begin rg_areg_0_hier_fs_fs1_fld1 <= #1 reg_areg_0_hier_fs_fs1_fld1_next; - rg_areg_0_hier_fs_fs1_fld2 <= #1 reg_areg_0_hier_fs_fs1_fld2_next; - rg_areg_0_hier_fs_fld1 <= #1 reg_areg_0_hier_fs_fld1_next; rg_areg_0_hier_fs_fs2_fld1 <= #1 reg_areg_0_hier_fs_fs2_fld1_next; - rg_areg_0_hier_fs_fs2_fld2 <= #1 reg_areg_0_hier_fs_fs2_fld2_next; rg_areg_0_fs3_fld1 <= #1 reg_areg_0_fs3_fld1_next; - rg_areg_0_fs3_fld2 <= #1 reg_areg_0_fs3_fld2_next; end + rg_areg_0_hier_fs_fs1_fld2 <= #1 reg_areg_0_hier_fs_fs1_fld2_next; + rg_areg_0_hier_fs_fld1 <= #1 reg_areg_0_hier_fs_fld1_next; + rg_areg_0_hier_fs_fs2_fld2 <= #1 reg_areg_0_hier_fs_fs2_fld2_next; + rg_areg_0_fs3_fld2 <= #1 reg_areg_0_fs3_fld2_next; end //------- combinatorial assigns for areg_0 (pio read data) @@ -336,13 +336,13 @@ module foo_jrdl_logic end else begin rg_areg_1_hier_fs_fs1_fld1 <= #1 reg_areg_1_hier_fs_fs1_fld1_next; - rg_areg_1_hier_fs_fs1_fld2 <= #1 reg_areg_1_hier_fs_fs1_fld2_next; - rg_areg_1_hier_fs_fld1 <= #1 reg_areg_1_hier_fs_fld1_next; rg_areg_1_hier_fs_fs2_fld1 <= #1 reg_areg_1_hier_fs_fs2_fld1_next; - rg_areg_1_hier_fs_fs2_fld2 <= #1 reg_areg_1_hier_fs_fs2_fld2_next; rg_areg_1_fs3_fld1 <= #1 reg_areg_1_fs3_fld1_next; - rg_areg_1_fs3_fld2 <= #1 reg_areg_1_fs3_fld2_next; end + rg_areg_1_hier_fs_fs1_fld2 <= #1 reg_areg_1_hier_fs_fs1_fld2_next; + rg_areg_1_hier_fs_fld1 <= #1 reg_areg_1_hier_fs_fld1_next; + rg_areg_1_hier_fs_fs2_fld2 <= #1 reg_areg_1_hier_fs_fs2_fld2_next; + rg_areg_1_fs3_fld2 <= #1 reg_areg_1_fs3_fld2_next; end //------- combinatorial assigns for blabla @@ -395,16 +395,16 @@ module foo_jrdl_logic end else begin rg_blabla_fs1_0_fld1 <= #1 reg_blabla_fs1_0_fld1_next; - rg_blabla_fs1_0_fld2 <= #1 reg_blabla_fs1_0_fld2_next; rg_blabla_fs1_1_fld1 <= #1 reg_blabla_fs1_1_fld1_next; - rg_blabla_fs1_1_fld2 <= #1 reg_blabla_fs1_1_fld2_next; rg_blabla_fs1_2_fld1 <= #1 reg_blabla_fs1_2_fld1_next; - rg_blabla_fs1_2_fld2 <= #1 reg_blabla_fs1_2_fld2_next; rg_blabla_fs3_0_fld1 <= #1 reg_blabla_fs3_0_fld1_next; - rg_blabla_fs3_0_fld2 <= #1 reg_blabla_fs3_0_fld2_next; rg_blabla_fs3_1_fld1 <= #1 reg_blabla_fs3_1_fld1_next; - rg_blabla_fs3_1_fld2 <= #1 reg_blabla_fs3_1_fld2_next; end + rg_blabla_fs1_0_fld2 <= #1 reg_blabla_fs1_0_fld2_next; + rg_blabla_fs1_1_fld2 <= #1 reg_blabla_fs1_1_fld2_next; + rg_blabla_fs1_2_fld2 <= #1 reg_blabla_fs1_2_fld2_next; + rg_blabla_fs3_0_fld2 <= #1 reg_blabla_fs3_0_fld2_next; + rg_blabla_fs3_1_fld2 <= #1 reg_blabla_fs3_1_fld2_next; end endmodule @@ -556,7 +556,7 @@ module foo_jrdl_decode end end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always @ (posedge clk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -566,10 +566,6 @@ module foo_jrdl_decode pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; end - end - - //------- reg assigns for pio i/f - always @ (posedge clk) begin pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; end diff --git a/test/basic_tests/rdl_hello/golden/output.sv b/test/basic_tests/rdl_hello/golden/output.sv index 8a35b80..2f0470d 100644 --- a/test/basic_tests/rdl_hello/golden/output.sv +++ b/test/basic_tests/rdl_hello/golden/output.sv @@ -1,7 +1,7 @@ -// Ordt 190606.01 autogenerated file +// Ordt 190615.01 autogenerated file // Input: ./rdl_hello/test.rdl // Parms: ./rdl_hello/test.parms -// Date: Thu Jun 06 13:30:55 EDT 2019 +// Date: Sat Jun 15 21:05:40 EDT 2019 // // @@ -109,9 +109,9 @@ module foo_jrdl_logic end else begin rg_bar_a_reg_0_fld1 <= #1 reg_bar_a_reg_0_fld1_next; - rg_bar_a_reg_0_fld2 <= #1 reg_bar_a_reg_0_fld2_next; rg_bar_a_reg_0_ERR25 <= #1 reg_bar_a_reg_0_ERR25_next; end + rg_bar_a_reg_0_fld2 <= #1 reg_bar_a_reg_0_fld2_next; end //------- combinatorial assigns for bar_a_reg_1 @@ -136,9 +136,9 @@ module foo_jrdl_logic end else begin rg_bar_a_reg_1_fld1 <= #1 reg_bar_a_reg_1_fld1_next; - rg_bar_a_reg_1_fld2 <= #1 reg_bar_a_reg_1_fld2_next; rg_bar_a_reg_1_ERR25 <= #1 reg_bar_a_reg_1_ERR25_next; end + rg_bar_a_reg_1_fld2 <= #1 reg_bar_a_reg_1_fld2_next; end //------- combinatorial assigns for bar_a_reg_0 (pio read data) @@ -287,7 +287,7 @@ module foo_jrdl_decode end end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always_ff @ (posedge clk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -297,10 +297,6 @@ module foo_jrdl_decode pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; end - end - - //------- reg assigns for pio i/f - always_ff @ (posedge clk) begin pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; end diff --git a/test/basic_tests/rdl_hello/golden/output.v b/test/basic_tests/rdl_hello/golden/output.v index 65cf6ed..cbacbb2 100644 --- a/test/basic_tests/rdl_hello/golden/output.v +++ b/test/basic_tests/rdl_hello/golden/output.v @@ -1,7 +1,7 @@ -// Ordt 190606.01 autogenerated file +// Ordt 190615.01 autogenerated file // Input: ./rdl_hello/test.rdl // Parms: ./rdl_hello/test.parms -// Date: Thu Jun 06 13:30:55 EDT 2019 +// Date: Sat Jun 15 21:05:40 EDT 2019 // // @@ -109,9 +109,9 @@ module foo_jrdl_logic end else begin rg_bar_a_reg_0_fld1 <= #1 reg_bar_a_reg_0_fld1_next; - rg_bar_a_reg_0_fld2 <= #1 reg_bar_a_reg_0_fld2_next; rg_bar_a_reg_0_ERR25 <= #1 reg_bar_a_reg_0_ERR25_next; end + rg_bar_a_reg_0_fld2 <= #1 reg_bar_a_reg_0_fld2_next; end //------- combinatorial assigns for bar_a_reg_1 @@ -136,9 +136,9 @@ module foo_jrdl_logic end else begin rg_bar_a_reg_1_fld1 <= #1 reg_bar_a_reg_1_fld1_next; - rg_bar_a_reg_1_fld2 <= #1 reg_bar_a_reg_1_fld2_next; rg_bar_a_reg_1_ERR25 <= #1 reg_bar_a_reg_1_ERR25_next; end + rg_bar_a_reg_1_fld2 <= #1 reg_bar_a_reg_1_fld2_next; end //------- combinatorial assigns for bar_a_reg_0 (pio read data) @@ -287,7 +287,7 @@ module foo_jrdl_decode end end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always @ (posedge clk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -297,10 +297,6 @@ module foo_jrdl_decode pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; end - end - - //------- reg assigns for pio i/f - always @ (posedge clk) begin pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; end diff --git a/test/basic_tests/rdl_hier_01/golden/output.sv b/test/basic_tests/rdl_hier_01/golden/output.sv index 5c9487a..f4cc60c 100644 --- a/test/basic_tests/rdl_hier_01/golden/output.sv +++ b/test/basic_tests/rdl_hier_01/golden/output.sv @@ -1,7 +1,7 @@ -// Ordt 190606.01 autogenerated file +// Ordt 190615.01 autogenerated file // Input: ./rdl_hier_01/test.rdl // Parms: ./rdl_hier_01/test.parms -// Date: Thu Jun 06 13:30:56 EDT 2019 +// Date: Sat Jun 15 21:05:41 EDT 2019 // // @@ -1053,7 +1053,23 @@ module base_map_jrdl_decode end end - //------- reg assigns for external i/f (reset signal = reset) + //------- reg assigns for pio i/f + always_ff @ (posedge clk) begin + if (reset) begin + pio_write_active <= #1 1'b0; + pio_read_active <= #1 1'b0; + pio_dec_address_d1 <= #1 17'b0; + pio_dec_write_data_d1 <= #1 32'b0; + end + else begin + pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; + pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; + pio_dec_address_d1 <= #1 pio_dec_address; + pio_dec_write_data_d1 <= #1 pio_dec_write_data; + end + end + + //------- reg assigns for external i/f always_ff @ (posedge clk) begin if (reset) begin d2h_ext_base_regs_we_ex <= #1 1'b0; @@ -1079,26 +1095,6 @@ module base_map_jrdl_decode d2h_opt_reg_we_ex <= #1 d2h_opt_reg_we_next & ~h2d_opt_reg_ack_ex & ~h2d_opt_reg_nack_ex; d2h_opt_reg_re_ex <= #1 d2h_opt_reg_re_next & ~h2d_opt_reg_ack_ex & ~h2d_opt_reg_nack_ex; end - end - - //------- reg assigns for pio i/f (reset signal = reset) - always_ff @ (posedge clk) begin - if (reset) begin - pio_write_active <= #1 1'b0; - pio_read_active <= #1 1'b0; - pio_dec_address_d1 <= #1 17'b0; - pio_dec_write_data_d1 <= #1 32'b0; - end - else begin - pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; - pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; - pio_dec_address_d1 <= #1 pio_dec_address; - pio_dec_write_data_d1 <= #1 pio_dec_write_data; - end - end - - //------- reg assigns for external i/f - always_ff @ (posedge clk) begin d2h_ext_base_regs_w_ex <= #1 d2h_ext_base_regs_w_next; d2h_ext_base_regs_addr_ex <= #1 d2h_ext_base_regs_addr_next; d2h_l2_r16_child_w_ex <= #1 d2h_l2_r16_child_w_next; @@ -1212,11 +1208,11 @@ module base_map_jrdl_decode s8_l2_s8_child_cmdData_dly1 <= #1 s8_l2_s8_child_cmdData_dly0; s8_l2_s8_child_resValid_dly1 <= #1 s8_l2_s8_child_resValid_dly0; s8_l2_s8_child_resData_dly1 <= #1 s8_l2_s8_child_resData_dly0; - s8_l2_s8_child_rdata_accum <= #1 s8_l2_s8_child_rdata_accum_next; h2d_l2_s8_child_nack_early <= #1 h2d_l2_s8_child_nack_early_next; s8_l2_s8_child_addr_cnt <= #1 s8_l2_s8_child_addr_cnt_next; s8_l2_s8_child_data_cnt <= #1 s8_l2_s8_child_data_cnt_next; end + s8_l2_s8_child_rdata_accum <= #1 s8_l2_s8_child_rdata_accum_next; end //------- combinatorial assigns for leaf i/f @@ -1329,9 +1325,9 @@ module base_map_jrdl_decode r16_l2_r16_child_resData_dly1 <= #1 r16_l2_r16_child_resData_dly0; r16_l2_r16_child_resValid_dly2 <= #1 r16_l2_r16_child_resValid_dly1; r16_l2_r16_child_resData_dly2 <= #1 r16_l2_r16_child_resData_dly1; - r16_l2_r16_child_rdata_accum <= #1 r16_l2_r16_child_rdata_accum_next; r16_l2_r16_child_data_cnt <= #1 r16_l2_r16_child_data_cnt_next; end + r16_l2_r16_child_rdata_accum <= #1 r16_l2_r16_child_rdata_accum_next; end //------- combinatorial assigns for pio ack/nack @@ -2838,23 +2834,7 @@ module base_map_l2_r16_child_jrdl_decode end end - //------- reg assigns for external i/f (reset signal = reset) - always_ff @ (posedge clk) begin - if (reset) begin - d2h_l2_r16_child_ext_base_regs_we_ex <= #1 1'b0; - d2h_l2_r16_child_ext_base_regs_re_ex <= #1 1'b0; - d2h_l2_r16_child_l3_child_we_ex <= #1 1'b0; - d2h_l2_r16_child_l3_child_re_ex <= #1 1'b0; - end - else begin - d2h_l2_r16_child_ext_base_regs_we_ex <= #1 d2h_l2_r16_child_ext_base_regs_we_next & ~h2d_l2_r16_child_ext_base_regs_ack_ex & ~h2d_l2_r16_child_ext_base_regs_nack_ex; - d2h_l2_r16_child_ext_base_regs_re_ex <= #1 d2h_l2_r16_child_ext_base_regs_re_next & ~h2d_l2_r16_child_ext_base_regs_ack_ex & ~h2d_l2_r16_child_ext_base_regs_nack_ex; - d2h_l2_r16_child_l3_child_we_ex <= #1 d2h_l2_r16_child_l3_child_we_next & ~h2d_l2_r16_child_l3_child_ack_ex & ~h2d_l2_r16_child_l3_child_nack_ex; - d2h_l2_r16_child_l3_child_re_ex <= #1 d2h_l2_r16_child_l3_child_re_next & ~h2d_l2_r16_child_l3_child_ack_ex & ~h2d_l2_r16_child_l3_child_nack_ex; - end - end - - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always_ff @ (posedge clk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -2872,6 +2852,18 @@ module base_map_l2_r16_child_jrdl_decode //------- reg assigns for external i/f always_ff @ (posedge clk) begin + if (reset) begin + d2h_l2_r16_child_ext_base_regs_we_ex <= #1 1'b0; + d2h_l2_r16_child_ext_base_regs_re_ex <= #1 1'b0; + d2h_l2_r16_child_l3_child_we_ex <= #1 1'b0; + d2h_l2_r16_child_l3_child_re_ex <= #1 1'b0; + end + else begin + d2h_l2_r16_child_ext_base_regs_we_ex <= #1 d2h_l2_r16_child_ext_base_regs_we_next & ~h2d_l2_r16_child_ext_base_regs_ack_ex & ~h2d_l2_r16_child_ext_base_regs_nack_ex; + d2h_l2_r16_child_ext_base_regs_re_ex <= #1 d2h_l2_r16_child_ext_base_regs_re_next & ~h2d_l2_r16_child_ext_base_regs_ack_ex & ~h2d_l2_r16_child_ext_base_regs_nack_ex; + d2h_l2_r16_child_l3_child_we_ex <= #1 d2h_l2_r16_child_l3_child_we_next & ~h2d_l2_r16_child_l3_child_ack_ex & ~h2d_l2_r16_child_l3_child_nack_ex; + d2h_l2_r16_child_l3_child_re_ex <= #1 d2h_l2_r16_child_l3_child_re_next & ~h2d_l2_r16_child_l3_child_ack_ex & ~h2d_l2_r16_child_l3_child_nack_ex; + end d2h_l2_r16_child_ext_base_regs_w_ex <= #1 d2h_l2_r16_child_ext_base_regs_w_next; d2h_l2_r16_child_ext_base_regs_addr_ex <= #1 d2h_l2_r16_child_ext_base_regs_addr_next; d2h_l2_r16_child_l3_child_w_ex <= #1 d2h_l2_r16_child_l3_child_w_next; @@ -3164,11 +3156,11 @@ module base_map_l2_r16_child_jrdl_decode s8_l2_r16_child_l3_child_cmdData_dly1 <= #1 s8_l2_r16_child_l3_child_cmdData_dly0; s8_l2_r16_child_l3_child_resValid_dly1 <= #1 s8_l2_r16_child_l3_child_resValid_dly0; s8_l2_r16_child_l3_child_resData_dly1 <= #1 s8_l2_r16_child_l3_child_resData_dly0; - s8_l2_r16_child_l3_child_rdata_accum <= #1 s8_l2_r16_child_l3_child_rdata_accum_next; h2d_l2_r16_child_l3_child_nack_early <= #1 h2d_l2_r16_child_l3_child_nack_early_next; s8_l2_r16_child_l3_child_addr_cnt <= #1 s8_l2_r16_child_l3_child_addr_cnt_next; s8_l2_r16_child_l3_child_data_cnt <= #1 s8_l2_r16_child_l3_child_data_cnt_next; end + s8_l2_r16_child_l3_child_rdata_accum <= #1 s8_l2_r16_child_l3_child_rdata_accum_next; end //------- combinatorial assigns for pio ack/nack @@ -4466,18 +4458,6 @@ module base_map_l2_r16_child_l3_child_jrdl_decode end end - //------- reg assigns for external i/f (reset signal = reset) - always_ff @ (posedge clk) begin - if (reset) begin - d2h_l2_r16_child_l3_child_ext_base_regs_we_ex <= #1 1'b0; - d2h_l2_r16_child_l3_child_ext_base_regs_re_ex <= #1 1'b0; - end - else begin - d2h_l2_r16_child_l3_child_ext_base_regs_we_ex <= #1 d2h_l2_r16_child_l3_child_ext_base_regs_we_next & ~h2d_l2_r16_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_r16_child_l3_child_ext_base_regs_nack_ex; - d2h_l2_r16_child_l3_child_ext_base_regs_re_ex <= #1 d2h_l2_r16_child_l3_child_ext_base_regs_re_next & ~h2d_l2_r16_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_r16_child_l3_child_ext_base_regs_nack_ex; - end - end - //------- combinatorial assigns for serial8 i/f always_comb begin s8_state_next = s8_state; @@ -4576,16 +4556,16 @@ module base_map_l2_r16_child_l3_child_jrdl_decode end else begin s8_state <= #1 s8_state_next; - s8_addr_accum <= #1 s8_addr_accum_next; - s8_wdata_accum <= #1 s8_wdata_accum_next; - s8_wr_state_capture <= #1 s8_wr_state_capture_next; - s8_rdata_capture <= #1 s8_rdata_capture_next; s8_addr_cnt <= #1 s8_addr_cnt_next; s8_data_cnt <= #1 s8_data_cnt_next; end + s8_addr_accum <= #1 s8_addr_accum_next; + s8_wdata_accum <= #1 s8_wdata_accum_next; + s8_wr_state_capture <= #1 s8_wr_state_capture_next; + s8_rdata_capture <= #1 s8_rdata_capture_next; end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always_ff @ (posedge clk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -4603,6 +4583,14 @@ module base_map_l2_r16_child_l3_child_jrdl_decode //------- reg assigns for external i/f always_ff @ (posedge clk) begin + if (reset) begin + d2h_l2_r16_child_l3_child_ext_base_regs_we_ex <= #1 1'b0; + d2h_l2_r16_child_l3_child_ext_base_regs_re_ex <= #1 1'b0; + end + else begin + d2h_l2_r16_child_l3_child_ext_base_regs_we_ex <= #1 d2h_l2_r16_child_l3_child_ext_base_regs_we_next & ~h2d_l2_r16_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_r16_child_l3_child_ext_base_regs_nack_ex; + d2h_l2_r16_child_l3_child_ext_base_regs_re_ex <= #1 d2h_l2_r16_child_l3_child_ext_base_regs_re_next & ~h2d_l2_r16_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_r16_child_l3_child_ext_base_regs_nack_ex; + end d2h_l2_r16_child_l3_child_ext_base_regs_w_ex <= #1 d2h_l2_r16_child_l3_child_ext_base_regs_w_next; d2h_l2_r16_child_l3_child_ext_base_regs_addr_ex <= #1 d2h_l2_r16_child_l3_child_ext_base_regs_addr_next; end @@ -5924,22 +5912,6 @@ module base_map_l2_s8_child_jrdl_decode end end - //------- reg assigns for external i/f (reset signal = reset) - always_ff @ (posedge clk) begin - if (reset) begin - d2h_l2_s8_child_ext_base_regs_we_ex <= #1 1'b0; - d2h_l2_s8_child_ext_base_regs_re_ex <= #1 1'b0; - d2h_l2_s8_child_l3_child_we_ex <= #1 1'b0; - d2h_l2_s8_child_l3_child_re_ex <= #1 1'b0; - end - else begin - d2h_l2_s8_child_ext_base_regs_we_ex <= #1 d2h_l2_s8_child_ext_base_regs_we_next & ~h2d_l2_s8_child_ext_base_regs_ack_ex & ~h2d_l2_s8_child_ext_base_regs_nack_ex; - d2h_l2_s8_child_ext_base_regs_re_ex <= #1 d2h_l2_s8_child_ext_base_regs_re_next & ~h2d_l2_s8_child_ext_base_regs_ack_ex & ~h2d_l2_s8_child_ext_base_regs_nack_ex; - d2h_l2_s8_child_l3_child_we_ex <= #1 d2h_l2_s8_child_l3_child_we_next & ~h2d_l2_s8_child_l3_child_ack_ex & ~h2d_l2_s8_child_l3_child_nack_ex; - d2h_l2_s8_child_l3_child_re_ex <= #1 d2h_l2_s8_child_l3_child_re_next & ~h2d_l2_s8_child_l3_child_ack_ex & ~h2d_l2_s8_child_l3_child_nack_ex; - end - end - //------- combinatorial assigns for serial8 i/f always_comb begin s8_state_next = s8_state; @@ -6038,16 +6010,16 @@ module base_map_l2_s8_child_jrdl_decode end else begin s8_state <= #1 s8_state_next; - s8_addr_accum <= #1 s8_addr_accum_next; - s8_wdata_accum <= #1 s8_wdata_accum_next; - s8_wr_state_capture <= #1 s8_wr_state_capture_next; - s8_rdata_capture <= #1 s8_rdata_capture_next; s8_addr_cnt <= #1 s8_addr_cnt_next; s8_data_cnt <= #1 s8_data_cnt_next; end + s8_addr_accum <= #1 s8_addr_accum_next; + s8_wdata_accum <= #1 s8_wdata_accum_next; + s8_wr_state_capture <= #1 s8_wr_state_capture_next; + s8_rdata_capture <= #1 s8_rdata_capture_next; end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always_ff @ (posedge clk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -6065,6 +6037,18 @@ module base_map_l2_s8_child_jrdl_decode //------- reg assigns for external i/f always_ff @ (posedge clk) begin + if (reset) begin + d2h_l2_s8_child_ext_base_regs_we_ex <= #1 1'b0; + d2h_l2_s8_child_ext_base_regs_re_ex <= #1 1'b0; + d2h_l2_s8_child_l3_child_we_ex <= #1 1'b0; + d2h_l2_s8_child_l3_child_re_ex <= #1 1'b0; + end + else begin + d2h_l2_s8_child_ext_base_regs_we_ex <= #1 d2h_l2_s8_child_ext_base_regs_we_next & ~h2d_l2_s8_child_ext_base_regs_ack_ex & ~h2d_l2_s8_child_ext_base_regs_nack_ex; + d2h_l2_s8_child_ext_base_regs_re_ex <= #1 d2h_l2_s8_child_ext_base_regs_re_next & ~h2d_l2_s8_child_ext_base_regs_ack_ex & ~h2d_l2_s8_child_ext_base_regs_nack_ex; + d2h_l2_s8_child_l3_child_we_ex <= #1 d2h_l2_s8_child_l3_child_we_next & ~h2d_l2_s8_child_l3_child_ack_ex & ~h2d_l2_s8_child_l3_child_nack_ex; + d2h_l2_s8_child_l3_child_re_ex <= #1 d2h_l2_s8_child_l3_child_re_next & ~h2d_l2_s8_child_l3_child_ack_ex & ~h2d_l2_s8_child_l3_child_nack_ex; + end d2h_l2_s8_child_ext_base_regs_w_ex <= #1 d2h_l2_s8_child_ext_base_regs_w_next; d2h_l2_s8_child_ext_base_regs_addr_ex <= #1 d2h_l2_s8_child_ext_base_regs_addr_next; d2h_l2_s8_child_l3_child_w_ex <= #1 d2h_l2_s8_child_l3_child_w_next; @@ -6174,11 +6158,11 @@ module base_map_l2_s8_child_jrdl_decode s8_l2_s8_child_l3_child_cmdData_dly1 <= #1 s8_l2_s8_child_l3_child_cmdData_dly0; s8_l2_s8_child_l3_child_resValid_dly1 <= #1 s8_l2_s8_child_l3_child_resValid_dly0; s8_l2_s8_child_l3_child_resData_dly1 <= #1 s8_l2_s8_child_l3_child_resData_dly0; - s8_l2_s8_child_l3_child_rdata_accum <= #1 s8_l2_s8_child_l3_child_rdata_accum_next; h2d_l2_s8_child_l3_child_nack_early <= #1 h2d_l2_s8_child_l3_child_nack_early_next; s8_l2_s8_child_l3_child_addr_cnt <= #1 s8_l2_s8_child_l3_child_addr_cnt_next; s8_l2_s8_child_l3_child_data_cnt <= #1 s8_l2_s8_child_l3_child_data_cnt_next; end + s8_l2_s8_child_l3_child_rdata_accum <= #1 s8_l2_s8_child_l3_child_rdata_accum_next; end //------- combinatorial assigns for pio ack/nack @@ -7476,18 +7460,6 @@ module base_map_l2_s8_child_l3_child_jrdl_decode end end - //------- reg assigns for external i/f (reset signal = reset) - always_ff @ (posedge clk) begin - if (reset) begin - d2h_l2_s8_child_l3_child_ext_base_regs_we_ex <= #1 1'b0; - d2h_l2_s8_child_l3_child_ext_base_regs_re_ex <= #1 1'b0; - end - else begin - d2h_l2_s8_child_l3_child_ext_base_regs_we_ex <= #1 d2h_l2_s8_child_l3_child_ext_base_regs_we_next & ~h2d_l2_s8_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_s8_child_l3_child_ext_base_regs_nack_ex; - d2h_l2_s8_child_l3_child_ext_base_regs_re_ex <= #1 d2h_l2_s8_child_l3_child_ext_base_regs_re_next & ~h2d_l2_s8_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_s8_child_l3_child_ext_base_regs_nack_ex; - end - end - //------- combinatorial assigns for serial8 i/f always_comb begin s8_state_next = s8_state; @@ -7586,16 +7558,16 @@ module base_map_l2_s8_child_l3_child_jrdl_decode end else begin s8_state <= #1 s8_state_next; - s8_addr_accum <= #1 s8_addr_accum_next; - s8_wdata_accum <= #1 s8_wdata_accum_next; - s8_wr_state_capture <= #1 s8_wr_state_capture_next; - s8_rdata_capture <= #1 s8_rdata_capture_next; s8_addr_cnt <= #1 s8_addr_cnt_next; s8_data_cnt <= #1 s8_data_cnt_next; end + s8_addr_accum <= #1 s8_addr_accum_next; + s8_wdata_accum <= #1 s8_wdata_accum_next; + s8_wr_state_capture <= #1 s8_wr_state_capture_next; + s8_rdata_capture <= #1 s8_rdata_capture_next; end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always_ff @ (posedge clk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -7613,6 +7585,14 @@ module base_map_l2_s8_child_l3_child_jrdl_decode //------- reg assigns for external i/f always_ff @ (posedge clk) begin + if (reset) begin + d2h_l2_s8_child_l3_child_ext_base_regs_we_ex <= #1 1'b0; + d2h_l2_s8_child_l3_child_ext_base_regs_re_ex <= #1 1'b0; + end + else begin + d2h_l2_s8_child_l3_child_ext_base_regs_we_ex <= #1 d2h_l2_s8_child_l3_child_ext_base_regs_we_next & ~h2d_l2_s8_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_s8_child_l3_child_ext_base_regs_nack_ex; + d2h_l2_s8_child_l3_child_ext_base_regs_re_ex <= #1 d2h_l2_s8_child_l3_child_ext_base_regs_re_next & ~h2d_l2_s8_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_s8_child_l3_child_ext_base_regs_nack_ex; + end d2h_l2_s8_child_l3_child_ext_base_regs_w_ex <= #1 d2h_l2_s8_child_l3_child_ext_base_regs_w_next; d2h_l2_s8_child_l3_child_ext_base_regs_addr_ex <= #1 d2h_l2_s8_child_l3_child_ext_base_regs_addr_next; end diff --git a/test/basic_tests/rdl_hier_01/golden/output.v b/test/basic_tests/rdl_hier_01/golden/output.v index 01c444f..23cefb6 100644 --- a/test/basic_tests/rdl_hier_01/golden/output.v +++ b/test/basic_tests/rdl_hier_01/golden/output.v @@ -1,7 +1,7 @@ -// Ordt 190606.01 autogenerated file +// Ordt 190615.01 autogenerated file // Input: ./rdl_hier_01/test.rdl // Parms: ./rdl_hier_01/test.parms -// Date: Thu Jun 06 13:30:56 EDT 2019 +// Date: Sat Jun 15 21:05:41 EDT 2019 // // @@ -1053,7 +1053,23 @@ module base_map_jrdl_decode end end - //------- reg assigns for external i/f (reset signal = reset) + //------- reg assigns for pio i/f + always @ (posedge clk) begin + if (reset) begin + pio_write_active <= #1 1'b0; + pio_read_active <= #1 1'b0; + pio_dec_address_d1 <= #1 17'b0; + pio_dec_write_data_d1 <= #1 32'b0; + end + else begin + pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; + pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; + pio_dec_address_d1 <= #1 pio_dec_address; + pio_dec_write_data_d1 <= #1 pio_dec_write_data; + end + end + + //------- reg assigns for external i/f always @ (posedge clk) begin if (reset) begin d2h_ext_base_regs_we_ex <= #1 1'b0; @@ -1079,26 +1095,6 @@ module base_map_jrdl_decode d2h_opt_reg_we_ex <= #1 d2h_opt_reg_we_next & ~h2d_opt_reg_ack_ex & ~h2d_opt_reg_nack_ex; d2h_opt_reg_re_ex <= #1 d2h_opt_reg_re_next & ~h2d_opt_reg_ack_ex & ~h2d_opt_reg_nack_ex; end - end - - //------- reg assigns for pio i/f (reset signal = reset) - always @ (posedge clk) begin - if (reset) begin - pio_write_active <= #1 1'b0; - pio_read_active <= #1 1'b0; - pio_dec_address_d1 <= #1 17'b0; - pio_dec_write_data_d1 <= #1 32'b0; - end - else begin - pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; - pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; - pio_dec_address_d1 <= #1 pio_dec_address; - pio_dec_write_data_d1 <= #1 pio_dec_write_data; - end - end - - //------- reg assigns for external i/f - always @ (posedge clk) begin d2h_ext_base_regs_w_ex <= #1 d2h_ext_base_regs_w_next; d2h_ext_base_regs_addr_ex <= #1 d2h_ext_base_regs_addr_next; d2h_l2_r16_child_w_ex <= #1 d2h_l2_r16_child_w_next; @@ -1212,11 +1208,11 @@ module base_map_jrdl_decode s8_l2_s8_child_cmdData_dly1 <= #1 s8_l2_s8_child_cmdData_dly0; s8_l2_s8_child_resValid_dly1 <= #1 s8_l2_s8_child_resValid_dly0; s8_l2_s8_child_resData_dly1 <= #1 s8_l2_s8_child_resData_dly0; - s8_l2_s8_child_rdata_accum <= #1 s8_l2_s8_child_rdata_accum_next; h2d_l2_s8_child_nack_early <= #1 h2d_l2_s8_child_nack_early_next; s8_l2_s8_child_addr_cnt <= #1 s8_l2_s8_child_addr_cnt_next; s8_l2_s8_child_data_cnt <= #1 s8_l2_s8_child_data_cnt_next; end + s8_l2_s8_child_rdata_accum <= #1 s8_l2_s8_child_rdata_accum_next; end //------- combinatorial assigns for leaf i/f @@ -1329,9 +1325,9 @@ module base_map_jrdl_decode r16_l2_r16_child_resData_dly1 <= #1 r16_l2_r16_child_resData_dly0; r16_l2_r16_child_resValid_dly2 <= #1 r16_l2_r16_child_resValid_dly1; r16_l2_r16_child_resData_dly2 <= #1 r16_l2_r16_child_resData_dly1; - r16_l2_r16_child_rdata_accum <= #1 r16_l2_r16_child_rdata_accum_next; r16_l2_r16_child_data_cnt <= #1 r16_l2_r16_child_data_cnt_next; end + r16_l2_r16_child_rdata_accum <= #1 r16_l2_r16_child_rdata_accum_next; end //------- combinatorial assigns for pio ack/nack @@ -3033,23 +3029,7 @@ module base_map_l2_r16_child_jrdl_decode end end - //------- reg assigns for external i/f (reset signal = reset) - always @ (posedge clk) begin - if (reset) begin - d2h_l2_r16_child_ext_base_regs_we_ex <= #1 1'b0; - d2h_l2_r16_child_ext_base_regs_re_ex <= #1 1'b0; - d2h_l2_r16_child_l3_child_we_ex <= #1 1'b0; - d2h_l2_r16_child_l3_child_re_ex <= #1 1'b0; - end - else begin - d2h_l2_r16_child_ext_base_regs_we_ex <= #1 d2h_l2_r16_child_ext_base_regs_we_next & ~h2d_l2_r16_child_ext_base_regs_ack_ex & ~h2d_l2_r16_child_ext_base_regs_nack_ex; - d2h_l2_r16_child_ext_base_regs_re_ex <= #1 d2h_l2_r16_child_ext_base_regs_re_next & ~h2d_l2_r16_child_ext_base_regs_ack_ex & ~h2d_l2_r16_child_ext_base_regs_nack_ex; - d2h_l2_r16_child_l3_child_we_ex <= #1 d2h_l2_r16_child_l3_child_we_next & ~h2d_l2_r16_child_l3_child_ack_ex & ~h2d_l2_r16_child_l3_child_nack_ex; - d2h_l2_r16_child_l3_child_re_ex <= #1 d2h_l2_r16_child_l3_child_re_next & ~h2d_l2_r16_child_l3_child_ack_ex & ~h2d_l2_r16_child_l3_child_nack_ex; - end - end - - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always @ (posedge clk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -3067,6 +3047,18 @@ module base_map_l2_r16_child_jrdl_decode //------- reg assigns for external i/f always @ (posedge clk) begin + if (reset) begin + d2h_l2_r16_child_ext_base_regs_we_ex <= #1 1'b0; + d2h_l2_r16_child_ext_base_regs_re_ex <= #1 1'b0; + d2h_l2_r16_child_l3_child_we_ex <= #1 1'b0; + d2h_l2_r16_child_l3_child_re_ex <= #1 1'b0; + end + else begin + d2h_l2_r16_child_ext_base_regs_we_ex <= #1 d2h_l2_r16_child_ext_base_regs_we_next & ~h2d_l2_r16_child_ext_base_regs_ack_ex & ~h2d_l2_r16_child_ext_base_regs_nack_ex; + d2h_l2_r16_child_ext_base_regs_re_ex <= #1 d2h_l2_r16_child_ext_base_regs_re_next & ~h2d_l2_r16_child_ext_base_regs_ack_ex & ~h2d_l2_r16_child_ext_base_regs_nack_ex; + d2h_l2_r16_child_l3_child_we_ex <= #1 d2h_l2_r16_child_l3_child_we_next & ~h2d_l2_r16_child_l3_child_ack_ex & ~h2d_l2_r16_child_l3_child_nack_ex; + d2h_l2_r16_child_l3_child_re_ex <= #1 d2h_l2_r16_child_l3_child_re_next & ~h2d_l2_r16_child_l3_child_ack_ex & ~h2d_l2_r16_child_l3_child_nack_ex; + end d2h_l2_r16_child_ext_base_regs_w_ex <= #1 d2h_l2_r16_child_ext_base_regs_w_next; d2h_l2_r16_child_ext_base_regs_addr_ex <= #1 d2h_l2_r16_child_ext_base_regs_addr_next; d2h_l2_r16_child_l3_child_w_ex <= #1 d2h_l2_r16_child_l3_child_w_next; @@ -3359,11 +3351,11 @@ module base_map_l2_r16_child_jrdl_decode s8_l2_r16_child_l3_child_cmdData_dly1 <= #1 s8_l2_r16_child_l3_child_cmdData_dly0; s8_l2_r16_child_l3_child_resValid_dly1 <= #1 s8_l2_r16_child_l3_child_resValid_dly0; s8_l2_r16_child_l3_child_resData_dly1 <= #1 s8_l2_r16_child_l3_child_resData_dly0; - s8_l2_r16_child_l3_child_rdata_accum <= #1 s8_l2_r16_child_l3_child_rdata_accum_next; h2d_l2_r16_child_l3_child_nack_early <= #1 h2d_l2_r16_child_l3_child_nack_early_next; s8_l2_r16_child_l3_child_addr_cnt <= #1 s8_l2_r16_child_l3_child_addr_cnt_next; s8_l2_r16_child_l3_child_data_cnt <= #1 s8_l2_r16_child_l3_child_data_cnt_next; end + s8_l2_r16_child_l3_child_rdata_accum <= #1 s8_l2_r16_child_l3_child_rdata_accum_next; end //------- combinatorial assigns for pio ack/nack @@ -4832,18 +4824,6 @@ module base_map_l2_r16_child_l3_child_jrdl_decode end end - //------- reg assigns for external i/f (reset signal = reset) - always @ (posedge clk) begin - if (reset) begin - d2h_l2_r16_child_l3_child_ext_base_regs_we_ex <= #1 1'b0; - d2h_l2_r16_child_l3_child_ext_base_regs_re_ex <= #1 1'b0; - end - else begin - d2h_l2_r16_child_l3_child_ext_base_regs_we_ex <= #1 d2h_l2_r16_child_l3_child_ext_base_regs_we_next & ~h2d_l2_r16_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_r16_child_l3_child_ext_base_regs_nack_ex; - d2h_l2_r16_child_l3_child_ext_base_regs_re_ex <= #1 d2h_l2_r16_child_l3_child_ext_base_regs_re_next & ~h2d_l2_r16_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_r16_child_l3_child_ext_base_regs_nack_ex; - end - end - //------- combinatorial assigns for serial8 i/f always @ (*) begin s8_state_next = s8_state; @@ -4942,16 +4922,16 @@ module base_map_l2_r16_child_l3_child_jrdl_decode end else begin s8_state <= #1 s8_state_next; - s8_addr_accum <= #1 s8_addr_accum_next; - s8_wdata_accum <= #1 s8_wdata_accum_next; - s8_wr_state_capture <= #1 s8_wr_state_capture_next; - s8_rdata_capture <= #1 s8_rdata_capture_next; s8_addr_cnt <= #1 s8_addr_cnt_next; s8_data_cnt <= #1 s8_data_cnt_next; end + s8_addr_accum <= #1 s8_addr_accum_next; + s8_wdata_accum <= #1 s8_wdata_accum_next; + s8_wr_state_capture <= #1 s8_wr_state_capture_next; + s8_rdata_capture <= #1 s8_rdata_capture_next; end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always @ (posedge clk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -4969,6 +4949,14 @@ module base_map_l2_r16_child_l3_child_jrdl_decode //------- reg assigns for external i/f always @ (posedge clk) begin + if (reset) begin + d2h_l2_r16_child_l3_child_ext_base_regs_we_ex <= #1 1'b0; + d2h_l2_r16_child_l3_child_ext_base_regs_re_ex <= #1 1'b0; + end + else begin + d2h_l2_r16_child_l3_child_ext_base_regs_we_ex <= #1 d2h_l2_r16_child_l3_child_ext_base_regs_we_next & ~h2d_l2_r16_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_r16_child_l3_child_ext_base_regs_nack_ex; + d2h_l2_r16_child_l3_child_ext_base_regs_re_ex <= #1 d2h_l2_r16_child_l3_child_ext_base_regs_re_next & ~h2d_l2_r16_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_r16_child_l3_child_ext_base_regs_nack_ex; + end d2h_l2_r16_child_l3_child_ext_base_regs_w_ex <= #1 d2h_l2_r16_child_l3_child_ext_base_regs_w_next; d2h_l2_r16_child_l3_child_ext_base_regs_addr_ex <= #1 d2h_l2_r16_child_l3_child_ext_base_regs_addr_next; end @@ -6457,22 +6445,6 @@ module base_map_l2_s8_child_jrdl_decode end end - //------- reg assigns for external i/f (reset signal = reset) - always @ (posedge clk) begin - if (reset) begin - d2h_l2_s8_child_ext_base_regs_we_ex <= #1 1'b0; - d2h_l2_s8_child_ext_base_regs_re_ex <= #1 1'b0; - d2h_l2_s8_child_l3_child_we_ex <= #1 1'b0; - d2h_l2_s8_child_l3_child_re_ex <= #1 1'b0; - end - else begin - d2h_l2_s8_child_ext_base_regs_we_ex <= #1 d2h_l2_s8_child_ext_base_regs_we_next & ~h2d_l2_s8_child_ext_base_regs_ack_ex & ~h2d_l2_s8_child_ext_base_regs_nack_ex; - d2h_l2_s8_child_ext_base_regs_re_ex <= #1 d2h_l2_s8_child_ext_base_regs_re_next & ~h2d_l2_s8_child_ext_base_regs_ack_ex & ~h2d_l2_s8_child_ext_base_regs_nack_ex; - d2h_l2_s8_child_l3_child_we_ex <= #1 d2h_l2_s8_child_l3_child_we_next & ~h2d_l2_s8_child_l3_child_ack_ex & ~h2d_l2_s8_child_l3_child_nack_ex; - d2h_l2_s8_child_l3_child_re_ex <= #1 d2h_l2_s8_child_l3_child_re_next & ~h2d_l2_s8_child_l3_child_ack_ex & ~h2d_l2_s8_child_l3_child_nack_ex; - end - end - //------- combinatorial assigns for serial8 i/f always @ (*) begin s8_state_next = s8_state; @@ -6571,16 +6543,16 @@ module base_map_l2_s8_child_jrdl_decode end else begin s8_state <= #1 s8_state_next; - s8_addr_accum <= #1 s8_addr_accum_next; - s8_wdata_accum <= #1 s8_wdata_accum_next; - s8_wr_state_capture <= #1 s8_wr_state_capture_next; - s8_rdata_capture <= #1 s8_rdata_capture_next; s8_addr_cnt <= #1 s8_addr_cnt_next; s8_data_cnt <= #1 s8_data_cnt_next; end + s8_addr_accum <= #1 s8_addr_accum_next; + s8_wdata_accum <= #1 s8_wdata_accum_next; + s8_wr_state_capture <= #1 s8_wr_state_capture_next; + s8_rdata_capture <= #1 s8_rdata_capture_next; end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always @ (posedge clk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -6598,6 +6570,18 @@ module base_map_l2_s8_child_jrdl_decode //------- reg assigns for external i/f always @ (posedge clk) begin + if (reset) begin + d2h_l2_s8_child_ext_base_regs_we_ex <= #1 1'b0; + d2h_l2_s8_child_ext_base_regs_re_ex <= #1 1'b0; + d2h_l2_s8_child_l3_child_we_ex <= #1 1'b0; + d2h_l2_s8_child_l3_child_re_ex <= #1 1'b0; + end + else begin + d2h_l2_s8_child_ext_base_regs_we_ex <= #1 d2h_l2_s8_child_ext_base_regs_we_next & ~h2d_l2_s8_child_ext_base_regs_ack_ex & ~h2d_l2_s8_child_ext_base_regs_nack_ex; + d2h_l2_s8_child_ext_base_regs_re_ex <= #1 d2h_l2_s8_child_ext_base_regs_re_next & ~h2d_l2_s8_child_ext_base_regs_ack_ex & ~h2d_l2_s8_child_ext_base_regs_nack_ex; + d2h_l2_s8_child_l3_child_we_ex <= #1 d2h_l2_s8_child_l3_child_we_next & ~h2d_l2_s8_child_l3_child_ack_ex & ~h2d_l2_s8_child_l3_child_nack_ex; + d2h_l2_s8_child_l3_child_re_ex <= #1 d2h_l2_s8_child_l3_child_re_next & ~h2d_l2_s8_child_l3_child_ack_ex & ~h2d_l2_s8_child_l3_child_nack_ex; + end d2h_l2_s8_child_ext_base_regs_w_ex <= #1 d2h_l2_s8_child_ext_base_regs_w_next; d2h_l2_s8_child_ext_base_regs_addr_ex <= #1 d2h_l2_s8_child_ext_base_regs_addr_next; d2h_l2_s8_child_l3_child_w_ex <= #1 d2h_l2_s8_child_l3_child_w_next; @@ -6707,11 +6691,11 @@ module base_map_l2_s8_child_jrdl_decode s8_l2_s8_child_l3_child_cmdData_dly1 <= #1 s8_l2_s8_child_l3_child_cmdData_dly0; s8_l2_s8_child_l3_child_resValid_dly1 <= #1 s8_l2_s8_child_l3_child_resValid_dly0; s8_l2_s8_child_l3_child_resData_dly1 <= #1 s8_l2_s8_child_l3_child_resData_dly0; - s8_l2_s8_child_l3_child_rdata_accum <= #1 s8_l2_s8_child_l3_child_rdata_accum_next; h2d_l2_s8_child_l3_child_nack_early <= #1 h2d_l2_s8_child_l3_child_nack_early_next; s8_l2_s8_child_l3_child_addr_cnt <= #1 s8_l2_s8_child_l3_child_addr_cnt_next; s8_l2_s8_child_l3_child_data_cnt <= #1 s8_l2_s8_child_l3_child_data_cnt_next; end + s8_l2_s8_child_l3_child_rdata_accum <= #1 s8_l2_s8_child_l3_child_rdata_accum_next; end //------- combinatorial assigns for pio ack/nack @@ -8180,18 +8164,6 @@ module base_map_l2_s8_child_l3_child_jrdl_decode end end - //------- reg assigns for external i/f (reset signal = reset) - always @ (posedge clk) begin - if (reset) begin - d2h_l2_s8_child_l3_child_ext_base_regs_we_ex <= #1 1'b0; - d2h_l2_s8_child_l3_child_ext_base_regs_re_ex <= #1 1'b0; - end - else begin - d2h_l2_s8_child_l3_child_ext_base_regs_we_ex <= #1 d2h_l2_s8_child_l3_child_ext_base_regs_we_next & ~h2d_l2_s8_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_s8_child_l3_child_ext_base_regs_nack_ex; - d2h_l2_s8_child_l3_child_ext_base_regs_re_ex <= #1 d2h_l2_s8_child_l3_child_ext_base_regs_re_next & ~h2d_l2_s8_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_s8_child_l3_child_ext_base_regs_nack_ex; - end - end - //------- combinatorial assigns for serial8 i/f always @ (*) begin s8_state_next = s8_state; @@ -8290,16 +8262,16 @@ module base_map_l2_s8_child_l3_child_jrdl_decode end else begin s8_state <= #1 s8_state_next; - s8_addr_accum <= #1 s8_addr_accum_next; - s8_wdata_accum <= #1 s8_wdata_accum_next; - s8_wr_state_capture <= #1 s8_wr_state_capture_next; - s8_rdata_capture <= #1 s8_rdata_capture_next; s8_addr_cnt <= #1 s8_addr_cnt_next; s8_data_cnt <= #1 s8_data_cnt_next; end + s8_addr_accum <= #1 s8_addr_accum_next; + s8_wdata_accum <= #1 s8_wdata_accum_next; + s8_wr_state_capture <= #1 s8_wr_state_capture_next; + s8_rdata_capture <= #1 s8_rdata_capture_next; end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always @ (posedge clk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -8317,6 +8289,14 @@ module base_map_l2_s8_child_l3_child_jrdl_decode //------- reg assigns for external i/f always @ (posedge clk) begin + if (reset) begin + d2h_l2_s8_child_l3_child_ext_base_regs_we_ex <= #1 1'b0; + d2h_l2_s8_child_l3_child_ext_base_regs_re_ex <= #1 1'b0; + end + else begin + d2h_l2_s8_child_l3_child_ext_base_regs_we_ex <= #1 d2h_l2_s8_child_l3_child_ext_base_regs_we_next & ~h2d_l2_s8_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_s8_child_l3_child_ext_base_regs_nack_ex; + d2h_l2_s8_child_l3_child_ext_base_regs_re_ex <= #1 d2h_l2_s8_child_l3_child_ext_base_regs_re_next & ~h2d_l2_s8_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_s8_child_l3_child_ext_base_regs_nack_ex; + end d2h_l2_s8_child_l3_child_ext_base_regs_w_ex <= #1 d2h_l2_s8_child_l3_child_ext_base_regs_w_next; d2h_l2_s8_child_l3_child_ext_base_regs_addr_ex <= #1 d2h_l2_s8_child_l3_child_ext_base_regs_addr_next; end diff --git a/test/basic_tests/rdl_hier_02/golden/output.sv b/test/basic_tests/rdl_hier_02/golden/output.sv index 19b9f41..d1c3b12 100644 --- a/test/basic_tests/rdl_hier_02/golden/output.sv +++ b/test/basic_tests/rdl_hier_02/golden/output.sv @@ -1,7 +1,7 @@ -// Ordt 190606.01 autogenerated file +// Ordt 190615.01 autogenerated file // Input: ./rdl_hier_02/test.rdl // Parms: ./rdl_hier_02/test.parms -// Date: Thu Jun 06 13:30:57 EDT 2019 +// Date: Sat Jun 15 21:05:42 EDT 2019 // // @@ -1549,12 +1549,96 @@ module base_map_jrdl_decode //------- reg assigns for pio i/f always_ff @ (posedge uclk) begin + if (reset) begin + pio_write_active <= #1 1'b0; + pio_read_active <= #1 1'b0; + end + else begin + pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; + pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; + end pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; end //------- reg assigns for external i/f always_ff @ (posedge uclk) begin + if (reset) begin + d2h_ext_base_regs_we_ex <= #1 1'b0; + d2h_ext_base_regs_re_ex <= #1 1'b0; + d2h_l2_r16_child_we_ex <= #1 1'b0; + d2h_l2_r16_child_re_ex <= #1 1'b0; + d2h_l2_s8_child_we_ex <= #1 1'b0; + d2h_l2_s8_child_re_ex <= #1 1'b0; + d2h_l2_dflt_child_we_ex <= #1 1'b0; + d2h_l2_dflt_child_re_ex <= #1 1'b0; + d2h_singleton_rf_s8_we_ex <= #1 1'b0; + d2h_singleton_rf_s8_re_ex <= #1 1'b0; + d2h_singleton_rf_r16_we_ex <= #1 1'b0; + d2h_singleton_rf_r16_re_ex <= #1 1'b0; + d2h_singleton_rf_dflt_we_ex <= #1 1'b0; + d2h_singleton_rf_dflt_re_ex <= #1 1'b0; + d2h_rf_lvl2_0_rf_lvl1_0_reg_dflt_we_ex <= #1 1'b0; + d2h_rf_lvl2_0_rf_lvl1_0_reg_dflt_re_ex <= #1 1'b0; + d2h_rf_lvl2_0_rf_lvl1_reg_l1_we_ex <= #1 1'b0; + d2h_rf_lvl2_0_rf_lvl1_reg_l1_re_ex <= #1 1'b0; + d2h_rf_lvl2_rf_lvl1_reg_l2_we_ex <= #1 1'b0; + d2h_rf_lvl2_rf_lvl1_reg_l2_re_ex <= #1 1'b0; + d2h_rf_lvl2_0_rf_lvl1_1_reg_dflt_we_ex <= #1 1'b0; + d2h_rf_lvl2_0_rf_lvl1_1_reg_dflt_re_ex <= #1 1'b0; + d2h_rf_lvl2_0_rf_lvl1_2_reg_dflt_we_ex <= #1 1'b0; + d2h_rf_lvl2_0_rf_lvl1_2_reg_dflt_re_ex <= #1 1'b0; + d2h_rf_lvl2_0_rf_lvl1_3_reg_dflt_we_ex <= #1 1'b0; + d2h_rf_lvl2_0_rf_lvl1_3_reg_dflt_re_ex <= #1 1'b0; + d2h_rf_lvl2_1_rf_lvl1_0_reg_dflt_we_ex <= #1 1'b0; + d2h_rf_lvl2_1_rf_lvl1_0_reg_dflt_re_ex <= #1 1'b0; + d2h_rf_lvl2_1_rf_lvl1_reg_l1_we_ex <= #1 1'b0; + d2h_rf_lvl2_1_rf_lvl1_reg_l1_re_ex <= #1 1'b0; + d2h_rf_lvl2_1_rf_lvl1_1_reg_dflt_we_ex <= #1 1'b0; + d2h_rf_lvl2_1_rf_lvl1_1_reg_dflt_re_ex <= #1 1'b0; + d2h_rf_lvl2_1_rf_lvl1_2_reg_dflt_we_ex <= #1 1'b0; + d2h_rf_lvl2_1_rf_lvl1_2_reg_dflt_re_ex <= #1 1'b0; + d2h_rf_lvl2_1_rf_lvl1_3_reg_dflt_we_ex <= #1 1'b0; + d2h_rf_lvl2_1_rf_lvl1_3_reg_dflt_re_ex <= #1 1'b0; + end + else begin + d2h_ext_base_regs_we_ex <= #1 d2h_ext_base_regs_we_next & ~h2d_ext_base_regs_ack_ex & ~h2d_ext_base_regs_nack_ex; + d2h_ext_base_regs_re_ex <= #1 d2h_ext_base_regs_re_next & ~h2d_ext_base_regs_ack_ex & ~h2d_ext_base_regs_nack_ex; + d2h_l2_r16_child_we_ex <= #1 d2h_l2_r16_child_we_next & ~h2d_l2_r16_child_ack_ex & ~h2d_l2_r16_child_nack_ex; + d2h_l2_r16_child_re_ex <= #1 d2h_l2_r16_child_re_next & ~h2d_l2_r16_child_ack_ex & ~h2d_l2_r16_child_nack_ex; + d2h_l2_s8_child_we_ex <= #1 d2h_l2_s8_child_we_next & ~h2d_l2_s8_child_ack_ex & ~h2d_l2_s8_child_nack_ex; + d2h_l2_s8_child_re_ex <= #1 d2h_l2_s8_child_re_next & ~h2d_l2_s8_child_ack_ex & ~h2d_l2_s8_child_nack_ex; + d2h_l2_dflt_child_we_ex <= #1 d2h_l2_dflt_child_we_next & ~h2d_l2_dflt_child_ack_ex & ~h2d_l2_dflt_child_nack_ex; + d2h_l2_dflt_child_re_ex <= #1 d2h_l2_dflt_child_re_next & ~h2d_l2_dflt_child_ack_ex & ~h2d_l2_dflt_child_nack_ex; + d2h_singleton_rf_s8_we_ex <= #1 d2h_singleton_rf_s8_we_next & ~h2d_singleton_rf_s8_ack_ex & ~h2d_singleton_rf_s8_nack_ex; + d2h_singleton_rf_s8_re_ex <= #1 d2h_singleton_rf_s8_re_next & ~h2d_singleton_rf_s8_ack_ex & ~h2d_singleton_rf_s8_nack_ex; + d2h_singleton_rf_r16_we_ex <= #1 d2h_singleton_rf_r16_we_next & ~h2d_singleton_rf_r16_ack_ex & ~h2d_singleton_rf_r16_nack_ex; + d2h_singleton_rf_r16_re_ex <= #1 d2h_singleton_rf_r16_re_next & ~h2d_singleton_rf_r16_ack_ex & ~h2d_singleton_rf_r16_nack_ex; + d2h_singleton_rf_dflt_we_ex <= #1 d2h_singleton_rf_dflt_we_next & ~h2d_singleton_rf_dflt_ack_ex & ~h2d_singleton_rf_dflt_nack_ex; + d2h_singleton_rf_dflt_re_ex <= #1 d2h_singleton_rf_dflt_re_next & ~h2d_singleton_rf_dflt_ack_ex & ~h2d_singleton_rf_dflt_nack_ex; + d2h_rf_lvl2_0_rf_lvl1_0_reg_dflt_we_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_0_reg_dflt_we_next & ~h2d_rf_lvl2_0_rf_lvl1_0_reg_dflt_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_0_reg_dflt_nack_ex; + d2h_rf_lvl2_0_rf_lvl1_0_reg_dflt_re_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_0_reg_dflt_re_next & ~h2d_rf_lvl2_0_rf_lvl1_0_reg_dflt_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_0_reg_dflt_nack_ex; + d2h_rf_lvl2_0_rf_lvl1_reg_l1_we_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_reg_l1_we_next & ~h2d_rf_lvl2_0_rf_lvl1_reg_l1_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_reg_l1_nack_ex; + d2h_rf_lvl2_0_rf_lvl1_reg_l1_re_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_reg_l1_re_next & ~h2d_rf_lvl2_0_rf_lvl1_reg_l1_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_reg_l1_nack_ex; + d2h_rf_lvl2_rf_lvl1_reg_l2_we_ex <= #1 d2h_rf_lvl2_rf_lvl1_reg_l2_we_next & ~h2d_rf_lvl2_rf_lvl1_reg_l2_ack_ex & ~h2d_rf_lvl2_rf_lvl1_reg_l2_nack_ex; + d2h_rf_lvl2_rf_lvl1_reg_l2_re_ex <= #1 d2h_rf_lvl2_rf_lvl1_reg_l2_re_next & ~h2d_rf_lvl2_rf_lvl1_reg_l2_ack_ex & ~h2d_rf_lvl2_rf_lvl1_reg_l2_nack_ex; + d2h_rf_lvl2_0_rf_lvl1_1_reg_dflt_we_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_1_reg_dflt_we_next & ~h2d_rf_lvl2_0_rf_lvl1_1_reg_dflt_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_1_reg_dflt_nack_ex; + d2h_rf_lvl2_0_rf_lvl1_1_reg_dflt_re_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_1_reg_dflt_re_next & ~h2d_rf_lvl2_0_rf_lvl1_1_reg_dflt_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_1_reg_dflt_nack_ex; + d2h_rf_lvl2_0_rf_lvl1_2_reg_dflt_we_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_2_reg_dflt_we_next & ~h2d_rf_lvl2_0_rf_lvl1_2_reg_dflt_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_2_reg_dflt_nack_ex; + d2h_rf_lvl2_0_rf_lvl1_2_reg_dflt_re_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_2_reg_dflt_re_next & ~h2d_rf_lvl2_0_rf_lvl1_2_reg_dflt_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_2_reg_dflt_nack_ex; + d2h_rf_lvl2_0_rf_lvl1_3_reg_dflt_we_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_3_reg_dflt_we_next & ~h2d_rf_lvl2_0_rf_lvl1_3_reg_dflt_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_3_reg_dflt_nack_ex; + d2h_rf_lvl2_0_rf_lvl1_3_reg_dflt_re_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_3_reg_dflt_re_next & ~h2d_rf_lvl2_0_rf_lvl1_3_reg_dflt_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_3_reg_dflt_nack_ex; + d2h_rf_lvl2_1_rf_lvl1_0_reg_dflt_we_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_0_reg_dflt_we_next & ~h2d_rf_lvl2_1_rf_lvl1_0_reg_dflt_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_0_reg_dflt_nack_ex; + d2h_rf_lvl2_1_rf_lvl1_0_reg_dflt_re_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_0_reg_dflt_re_next & ~h2d_rf_lvl2_1_rf_lvl1_0_reg_dflt_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_0_reg_dflt_nack_ex; + d2h_rf_lvl2_1_rf_lvl1_reg_l1_we_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_reg_l1_we_next & ~h2d_rf_lvl2_1_rf_lvl1_reg_l1_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_reg_l1_nack_ex; + d2h_rf_lvl2_1_rf_lvl1_reg_l1_re_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_reg_l1_re_next & ~h2d_rf_lvl2_1_rf_lvl1_reg_l1_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_reg_l1_nack_ex; + d2h_rf_lvl2_1_rf_lvl1_1_reg_dflt_we_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_1_reg_dflt_we_next & ~h2d_rf_lvl2_1_rf_lvl1_1_reg_dflt_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_1_reg_dflt_nack_ex; + d2h_rf_lvl2_1_rf_lvl1_1_reg_dflt_re_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_1_reg_dflt_re_next & ~h2d_rf_lvl2_1_rf_lvl1_1_reg_dflt_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_1_reg_dflt_nack_ex; + d2h_rf_lvl2_1_rf_lvl1_2_reg_dflt_we_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_2_reg_dflt_we_next & ~h2d_rf_lvl2_1_rf_lvl1_2_reg_dflt_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_2_reg_dflt_nack_ex; + d2h_rf_lvl2_1_rf_lvl1_2_reg_dflt_re_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_2_reg_dflt_re_next & ~h2d_rf_lvl2_1_rf_lvl1_2_reg_dflt_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_2_reg_dflt_nack_ex; + d2h_rf_lvl2_1_rf_lvl1_3_reg_dflt_we_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_3_reg_dflt_we_next & ~h2d_rf_lvl2_1_rf_lvl1_3_reg_dflt_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_3_reg_dflt_nack_ex; + d2h_rf_lvl2_1_rf_lvl1_3_reg_dflt_re_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_3_reg_dflt_re_next & ~h2d_rf_lvl2_1_rf_lvl1_3_reg_dflt_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_3_reg_dflt_nack_ex; + end d2h_ext_base_regs_w_ex <= #1 d2h_ext_base_regs_w_next; d2h_ext_base_regs_addr_ex <= #1 d2h_ext_base_regs_addr_next; d2h_l2_r16_child_w_ex <= #1 d2h_l2_r16_child_w_next; @@ -1691,9 +1775,9 @@ module base_map_jrdl_decode r16_singleton_rf_r16_cmdData_dly1 <= #1 r16_singleton_rf_r16_cmdData_dly0; r16_singleton_rf_r16_resValid_dly1 <= #1 r16_singleton_rf_r16_resValid_dly0; r16_singleton_rf_r16_resData_dly1 <= #1 r16_singleton_rf_r16_resData_dly0; - r16_singleton_rf_r16_rdata_accum <= #1 r16_singleton_rf_r16_rdata_accum_next; r16_singleton_rf_r16_data_cnt <= #1 r16_singleton_rf_r16_data_cnt_next; end + r16_singleton_rf_r16_rdata_accum <= #1 r16_singleton_rf_r16_rdata_accum_next; end //------- combinatorial assigns for pio ack/nack @@ -1722,98 +1806,6 @@ module base_map_jrdl_decode end end - //------- reg assigns for external i/f (reset signal = reset) - always_ff @ (posedge uclk) begin - if (reset) begin - d2h_ext_base_regs_we_ex <= #1 1'b0; - d2h_ext_base_regs_re_ex <= #1 1'b0; - d2h_l2_r16_child_we_ex <= #1 1'b0; - d2h_l2_r16_child_re_ex <= #1 1'b0; - d2h_l2_s8_child_we_ex <= #1 1'b0; - d2h_l2_s8_child_re_ex <= #1 1'b0; - d2h_l2_dflt_child_we_ex <= #1 1'b0; - d2h_l2_dflt_child_re_ex <= #1 1'b0; - d2h_singleton_rf_s8_we_ex <= #1 1'b0; - d2h_singleton_rf_s8_re_ex <= #1 1'b0; - d2h_singleton_rf_r16_we_ex <= #1 1'b0; - d2h_singleton_rf_r16_re_ex <= #1 1'b0; - d2h_singleton_rf_dflt_we_ex <= #1 1'b0; - d2h_singleton_rf_dflt_re_ex <= #1 1'b0; - d2h_rf_lvl2_0_rf_lvl1_0_reg_dflt_we_ex <= #1 1'b0; - d2h_rf_lvl2_0_rf_lvl1_0_reg_dflt_re_ex <= #1 1'b0; - d2h_rf_lvl2_0_rf_lvl1_reg_l1_we_ex <= #1 1'b0; - d2h_rf_lvl2_0_rf_lvl1_reg_l1_re_ex <= #1 1'b0; - d2h_rf_lvl2_rf_lvl1_reg_l2_we_ex <= #1 1'b0; - d2h_rf_lvl2_rf_lvl1_reg_l2_re_ex <= #1 1'b0; - d2h_rf_lvl2_0_rf_lvl1_1_reg_dflt_we_ex <= #1 1'b0; - d2h_rf_lvl2_0_rf_lvl1_1_reg_dflt_re_ex <= #1 1'b0; - d2h_rf_lvl2_0_rf_lvl1_2_reg_dflt_we_ex <= #1 1'b0; - d2h_rf_lvl2_0_rf_lvl1_2_reg_dflt_re_ex <= #1 1'b0; - d2h_rf_lvl2_0_rf_lvl1_3_reg_dflt_we_ex <= #1 1'b0; - d2h_rf_lvl2_0_rf_lvl1_3_reg_dflt_re_ex <= #1 1'b0; - d2h_rf_lvl2_1_rf_lvl1_0_reg_dflt_we_ex <= #1 1'b0; - d2h_rf_lvl2_1_rf_lvl1_0_reg_dflt_re_ex <= #1 1'b0; - d2h_rf_lvl2_1_rf_lvl1_reg_l1_we_ex <= #1 1'b0; - d2h_rf_lvl2_1_rf_lvl1_reg_l1_re_ex <= #1 1'b0; - d2h_rf_lvl2_1_rf_lvl1_1_reg_dflt_we_ex <= #1 1'b0; - d2h_rf_lvl2_1_rf_lvl1_1_reg_dflt_re_ex <= #1 1'b0; - d2h_rf_lvl2_1_rf_lvl1_2_reg_dflt_we_ex <= #1 1'b0; - d2h_rf_lvl2_1_rf_lvl1_2_reg_dflt_re_ex <= #1 1'b0; - d2h_rf_lvl2_1_rf_lvl1_3_reg_dflt_we_ex <= #1 1'b0; - d2h_rf_lvl2_1_rf_lvl1_3_reg_dflt_re_ex <= #1 1'b0; - end - else begin - d2h_ext_base_regs_we_ex <= #1 d2h_ext_base_regs_we_next & ~h2d_ext_base_regs_ack_ex & ~h2d_ext_base_regs_nack_ex; - d2h_ext_base_regs_re_ex <= #1 d2h_ext_base_regs_re_next & ~h2d_ext_base_regs_ack_ex & ~h2d_ext_base_regs_nack_ex; - d2h_l2_r16_child_we_ex <= #1 d2h_l2_r16_child_we_next & ~h2d_l2_r16_child_ack_ex & ~h2d_l2_r16_child_nack_ex; - d2h_l2_r16_child_re_ex <= #1 d2h_l2_r16_child_re_next & ~h2d_l2_r16_child_ack_ex & ~h2d_l2_r16_child_nack_ex; - d2h_l2_s8_child_we_ex <= #1 d2h_l2_s8_child_we_next & ~h2d_l2_s8_child_ack_ex & ~h2d_l2_s8_child_nack_ex; - d2h_l2_s8_child_re_ex <= #1 d2h_l2_s8_child_re_next & ~h2d_l2_s8_child_ack_ex & ~h2d_l2_s8_child_nack_ex; - d2h_l2_dflt_child_we_ex <= #1 d2h_l2_dflt_child_we_next & ~h2d_l2_dflt_child_ack_ex & ~h2d_l2_dflt_child_nack_ex; - d2h_l2_dflt_child_re_ex <= #1 d2h_l2_dflt_child_re_next & ~h2d_l2_dflt_child_ack_ex & ~h2d_l2_dflt_child_nack_ex; - d2h_singleton_rf_s8_we_ex <= #1 d2h_singleton_rf_s8_we_next & ~h2d_singleton_rf_s8_ack_ex & ~h2d_singleton_rf_s8_nack_ex; - d2h_singleton_rf_s8_re_ex <= #1 d2h_singleton_rf_s8_re_next & ~h2d_singleton_rf_s8_ack_ex & ~h2d_singleton_rf_s8_nack_ex; - d2h_singleton_rf_r16_we_ex <= #1 d2h_singleton_rf_r16_we_next & ~h2d_singleton_rf_r16_ack_ex & ~h2d_singleton_rf_r16_nack_ex; - d2h_singleton_rf_r16_re_ex <= #1 d2h_singleton_rf_r16_re_next & ~h2d_singleton_rf_r16_ack_ex & ~h2d_singleton_rf_r16_nack_ex; - d2h_singleton_rf_dflt_we_ex <= #1 d2h_singleton_rf_dflt_we_next & ~h2d_singleton_rf_dflt_ack_ex & ~h2d_singleton_rf_dflt_nack_ex; - d2h_singleton_rf_dflt_re_ex <= #1 d2h_singleton_rf_dflt_re_next & ~h2d_singleton_rf_dflt_ack_ex & ~h2d_singleton_rf_dflt_nack_ex; - d2h_rf_lvl2_0_rf_lvl1_0_reg_dflt_we_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_0_reg_dflt_we_next & ~h2d_rf_lvl2_0_rf_lvl1_0_reg_dflt_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_0_reg_dflt_nack_ex; - d2h_rf_lvl2_0_rf_lvl1_0_reg_dflt_re_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_0_reg_dflt_re_next & ~h2d_rf_lvl2_0_rf_lvl1_0_reg_dflt_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_0_reg_dflt_nack_ex; - d2h_rf_lvl2_0_rf_lvl1_reg_l1_we_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_reg_l1_we_next & ~h2d_rf_lvl2_0_rf_lvl1_reg_l1_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_reg_l1_nack_ex; - d2h_rf_lvl2_0_rf_lvl1_reg_l1_re_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_reg_l1_re_next & ~h2d_rf_lvl2_0_rf_lvl1_reg_l1_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_reg_l1_nack_ex; - d2h_rf_lvl2_rf_lvl1_reg_l2_we_ex <= #1 d2h_rf_lvl2_rf_lvl1_reg_l2_we_next & ~h2d_rf_lvl2_rf_lvl1_reg_l2_ack_ex & ~h2d_rf_lvl2_rf_lvl1_reg_l2_nack_ex; - d2h_rf_lvl2_rf_lvl1_reg_l2_re_ex <= #1 d2h_rf_lvl2_rf_lvl1_reg_l2_re_next & ~h2d_rf_lvl2_rf_lvl1_reg_l2_ack_ex & ~h2d_rf_lvl2_rf_lvl1_reg_l2_nack_ex; - d2h_rf_lvl2_0_rf_lvl1_1_reg_dflt_we_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_1_reg_dflt_we_next & ~h2d_rf_lvl2_0_rf_lvl1_1_reg_dflt_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_1_reg_dflt_nack_ex; - d2h_rf_lvl2_0_rf_lvl1_1_reg_dflt_re_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_1_reg_dflt_re_next & ~h2d_rf_lvl2_0_rf_lvl1_1_reg_dflt_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_1_reg_dflt_nack_ex; - d2h_rf_lvl2_0_rf_lvl1_2_reg_dflt_we_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_2_reg_dflt_we_next & ~h2d_rf_lvl2_0_rf_lvl1_2_reg_dflt_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_2_reg_dflt_nack_ex; - d2h_rf_lvl2_0_rf_lvl1_2_reg_dflt_re_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_2_reg_dflt_re_next & ~h2d_rf_lvl2_0_rf_lvl1_2_reg_dflt_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_2_reg_dflt_nack_ex; - d2h_rf_lvl2_0_rf_lvl1_3_reg_dflt_we_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_3_reg_dflt_we_next & ~h2d_rf_lvl2_0_rf_lvl1_3_reg_dflt_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_3_reg_dflt_nack_ex; - d2h_rf_lvl2_0_rf_lvl1_3_reg_dflt_re_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_3_reg_dflt_re_next & ~h2d_rf_lvl2_0_rf_lvl1_3_reg_dflt_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_3_reg_dflt_nack_ex; - d2h_rf_lvl2_1_rf_lvl1_0_reg_dflt_we_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_0_reg_dflt_we_next & ~h2d_rf_lvl2_1_rf_lvl1_0_reg_dflt_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_0_reg_dflt_nack_ex; - d2h_rf_lvl2_1_rf_lvl1_0_reg_dflt_re_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_0_reg_dflt_re_next & ~h2d_rf_lvl2_1_rf_lvl1_0_reg_dflt_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_0_reg_dflt_nack_ex; - d2h_rf_lvl2_1_rf_lvl1_reg_l1_we_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_reg_l1_we_next & ~h2d_rf_lvl2_1_rf_lvl1_reg_l1_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_reg_l1_nack_ex; - d2h_rf_lvl2_1_rf_lvl1_reg_l1_re_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_reg_l1_re_next & ~h2d_rf_lvl2_1_rf_lvl1_reg_l1_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_reg_l1_nack_ex; - d2h_rf_lvl2_1_rf_lvl1_1_reg_dflt_we_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_1_reg_dflt_we_next & ~h2d_rf_lvl2_1_rf_lvl1_1_reg_dflt_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_1_reg_dflt_nack_ex; - d2h_rf_lvl2_1_rf_lvl1_1_reg_dflt_re_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_1_reg_dflt_re_next & ~h2d_rf_lvl2_1_rf_lvl1_1_reg_dflt_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_1_reg_dflt_nack_ex; - d2h_rf_lvl2_1_rf_lvl1_2_reg_dflt_we_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_2_reg_dflt_we_next & ~h2d_rf_lvl2_1_rf_lvl1_2_reg_dflt_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_2_reg_dflt_nack_ex; - d2h_rf_lvl2_1_rf_lvl1_2_reg_dflt_re_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_2_reg_dflt_re_next & ~h2d_rf_lvl2_1_rf_lvl1_2_reg_dflt_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_2_reg_dflt_nack_ex; - d2h_rf_lvl2_1_rf_lvl1_3_reg_dflt_we_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_3_reg_dflt_we_next & ~h2d_rf_lvl2_1_rf_lvl1_3_reg_dflt_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_3_reg_dflt_nack_ex; - d2h_rf_lvl2_1_rf_lvl1_3_reg_dflt_re_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_3_reg_dflt_re_next & ~h2d_rf_lvl2_1_rf_lvl1_3_reg_dflt_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_3_reg_dflt_nack_ex; - end - end - - //------- reg assigns for pio i/f (reset signal = reset) - always_ff @ (posedge uclk) begin - if (reset) begin - pio_write_active <= #1 1'b0; - pio_read_active <= #1 1'b0; - end - else begin - pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; - pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; - end - end - //------- combinatorial assigns for l2_s8_child serial8 i/f always_comb begin s8_l2_s8_child_state_next = s8_l2_s8_child_state; @@ -1917,11 +1909,11 @@ module base_map_jrdl_decode s8_l2_s8_child_cmdData_dly1 <= #1 s8_l2_s8_child_cmdData_dly0; s8_l2_s8_child_resValid_dly1 <= #1 s8_l2_s8_child_resValid_dly0; s8_l2_s8_child_resData_dly1 <= #1 s8_l2_s8_child_resData_dly0; - s8_l2_s8_child_rdata_accum <= #1 s8_l2_s8_child_rdata_accum_next; h2d_l2_s8_child_nack_early <= #1 h2d_l2_s8_child_nack_early_next; s8_l2_s8_child_addr_cnt <= #1 s8_l2_s8_child_addr_cnt_next; s8_l2_s8_child_data_cnt <= #1 s8_l2_s8_child_data_cnt_next; end + s8_l2_s8_child_rdata_accum <= #1 s8_l2_s8_child_rdata_accum_next; end //------- combinatorial assigns for singleton_rf_s8 serial8 i/f @@ -2014,10 +2006,10 @@ module base_map_jrdl_decode s8_singleton_rf_s8_cmdData_dly1 <= #1 s8_singleton_rf_s8_cmdData_dly0; s8_singleton_rf_s8_resValid_dly1 <= #1 s8_singleton_rf_s8_resValid_dly0; s8_singleton_rf_s8_resData_dly1 <= #1 s8_singleton_rf_s8_resData_dly0; - s8_singleton_rf_s8_rdata_accum <= #1 s8_singleton_rf_s8_rdata_accum_next; h2d_singleton_rf_s8_nack_early <= #1 h2d_singleton_rf_s8_nack_early_next; s8_singleton_rf_s8_data_cnt <= #1 s8_singleton_rf_s8_data_cnt_next; end + s8_singleton_rf_s8_rdata_accum <= #1 s8_singleton_rf_s8_rdata_accum_next; end //------- combinatorial assigns for rf_lvl2_1_rf_lvl1_0_reg_dflt external field read data assigns @@ -2137,9 +2129,9 @@ module base_map_jrdl_decode r16_l2_r16_child_resData_dly1 <= #1 r16_l2_r16_child_resData_dly0; r16_l2_r16_child_resValid_dly2 <= #1 r16_l2_r16_child_resValid_dly1; r16_l2_r16_child_resData_dly2 <= #1 r16_l2_r16_child_resData_dly1; - r16_l2_r16_child_rdata_accum <= #1 r16_l2_r16_child_rdata_accum_next; r16_l2_r16_child_data_cnt <= #1 r16_l2_r16_child_data_cnt_next; end + r16_l2_r16_child_rdata_accum <= #1 r16_l2_r16_child_rdata_accum_next; end //------- combinatorial assigns for rf_lvl2_1_rf_lvl1_2_reg_dflt external field read data assigns @@ -4131,23 +4123,7 @@ module base_map_l2_r16_child_jrdl_decode end end - //------- reg assigns for external i/f (reset signal = reset) - always_ff @ (posedge uclk) begin - if (reset) begin - d2h_l2_r16_child_ext_base_regs_we_ex <= #1 1'b0; - d2h_l2_r16_child_ext_base_regs_re_ex <= #1 1'b0; - d2h_l2_r16_child_l3_child_we_ex <= #1 1'b0; - d2h_l2_r16_child_l3_child_re_ex <= #1 1'b0; - end - else begin - d2h_l2_r16_child_ext_base_regs_we_ex <= #1 d2h_l2_r16_child_ext_base_regs_we_next & ~h2d_l2_r16_child_ext_base_regs_ack_ex & ~h2d_l2_r16_child_ext_base_regs_nack_ex; - d2h_l2_r16_child_ext_base_regs_re_ex <= #1 d2h_l2_r16_child_ext_base_regs_re_next & ~h2d_l2_r16_child_ext_base_regs_ack_ex & ~h2d_l2_r16_child_ext_base_regs_nack_ex; - d2h_l2_r16_child_l3_child_we_ex <= #1 d2h_l2_r16_child_l3_child_we_next & ~h2d_l2_r16_child_l3_child_ack_ex & ~h2d_l2_r16_child_l3_child_nack_ex; - d2h_l2_r16_child_l3_child_re_ex <= #1 d2h_l2_r16_child_l3_child_re_next & ~h2d_l2_r16_child_l3_child_ack_ex & ~h2d_l2_r16_child_l3_child_nack_ex; - end - end - - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always_ff @ (posedge uclk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -4157,16 +4133,24 @@ module base_map_l2_r16_child_jrdl_decode pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; end - end - - //------- reg assigns for pio i/f - always_ff @ (posedge uclk) begin pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; end //------- reg assigns for external i/f always_ff @ (posedge uclk) begin + if (reset) begin + d2h_l2_r16_child_ext_base_regs_we_ex <= #1 1'b0; + d2h_l2_r16_child_ext_base_regs_re_ex <= #1 1'b0; + d2h_l2_r16_child_l3_child_we_ex <= #1 1'b0; + d2h_l2_r16_child_l3_child_re_ex <= #1 1'b0; + end + else begin + d2h_l2_r16_child_ext_base_regs_we_ex <= #1 d2h_l2_r16_child_ext_base_regs_we_next & ~h2d_l2_r16_child_ext_base_regs_ack_ex & ~h2d_l2_r16_child_ext_base_regs_nack_ex; + d2h_l2_r16_child_ext_base_regs_re_ex <= #1 d2h_l2_r16_child_ext_base_regs_re_next & ~h2d_l2_r16_child_ext_base_regs_ack_ex & ~h2d_l2_r16_child_ext_base_regs_nack_ex; + d2h_l2_r16_child_l3_child_we_ex <= #1 d2h_l2_r16_child_l3_child_we_next & ~h2d_l2_r16_child_l3_child_ack_ex & ~h2d_l2_r16_child_l3_child_nack_ex; + d2h_l2_r16_child_l3_child_re_ex <= #1 d2h_l2_r16_child_l3_child_re_next & ~h2d_l2_r16_child_l3_child_ack_ex & ~h2d_l2_r16_child_l3_child_nack_ex; + end d2h_l2_r16_child_ext_base_regs_w_ex <= #1 d2h_l2_r16_child_ext_base_regs_w_next; d2h_l2_r16_child_ext_base_regs_addr_ex <= #1 d2h_l2_r16_child_ext_base_regs_addr_next; d2h_l2_r16_child_l3_child_w_ex <= #1 d2h_l2_r16_child_l3_child_w_next; @@ -4491,11 +4475,11 @@ module base_map_l2_r16_child_jrdl_decode s8_l2_r16_child_l3_child_cmdData_dly1 <= #1 s8_l2_r16_child_l3_child_cmdData_dly0; s8_l2_r16_child_l3_child_resValid_dly1 <= #1 s8_l2_r16_child_l3_child_resValid_dly0; s8_l2_r16_child_l3_child_resData_dly1 <= #1 s8_l2_r16_child_l3_child_resData_dly0; - s8_l2_r16_child_l3_child_rdata_accum <= #1 s8_l2_r16_child_l3_child_rdata_accum_next; h2d_l2_r16_child_l3_child_nack_early <= #1 h2d_l2_r16_child_l3_child_nack_early_next; s8_l2_r16_child_l3_child_addr_cnt <= #1 s8_l2_r16_child_l3_child_addr_cnt_next; s8_l2_r16_child_l3_child_data_cnt <= #1 s8_l2_r16_child_l3_child_data_cnt_next; end + s8_l2_r16_child_l3_child_rdata_accum <= #1 s8_l2_r16_child_l3_child_rdata_accum_next; end //------- combinatorial assigns for pio ack/nack @@ -5812,18 +5796,6 @@ module base_map_l2_r16_child_l3_child_jrdl_decode end end - //------- reg assigns for external i/f (reset signal = reset) - always_ff @ (posedge uclk) begin - if (reset) begin - d2h_l2_r16_child_l3_child_ext_base_regs_we_ex <= #1 1'b0; - d2h_l2_r16_child_l3_child_ext_base_regs_re_ex <= #1 1'b0; - end - else begin - d2h_l2_r16_child_l3_child_ext_base_regs_we_ex <= #1 d2h_l2_r16_child_l3_child_ext_base_regs_we_next & ~h2d_l2_r16_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_r16_child_l3_child_ext_base_regs_nack_ex; - d2h_l2_r16_child_l3_child_ext_base_regs_re_ex <= #1 d2h_l2_r16_child_l3_child_ext_base_regs_re_next & ~h2d_l2_r16_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_r16_child_l3_child_ext_base_regs_nack_ex; - end - end - //------- combinatorial assigns for serial8 i/f always_comb begin s8_state_next = s8_state; @@ -5922,16 +5894,16 @@ module base_map_l2_r16_child_l3_child_jrdl_decode end else begin s8_state <= #1 s8_state_next; - s8_addr_accum <= #1 s8_addr_accum_next; - s8_wdata_accum <= #1 s8_wdata_accum_next; - s8_wr_state_capture <= #1 s8_wr_state_capture_next; - s8_rdata_capture <= #1 s8_rdata_capture_next; s8_addr_cnt <= #1 s8_addr_cnt_next; s8_data_cnt <= #1 s8_data_cnt_next; end + s8_addr_accum <= #1 s8_addr_accum_next; + s8_wdata_accum <= #1 s8_wdata_accum_next; + s8_wr_state_capture <= #1 s8_wr_state_capture_next; + s8_rdata_capture <= #1 s8_rdata_capture_next; end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always_ff @ (posedge uclk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -5941,16 +5913,20 @@ module base_map_l2_r16_child_l3_child_jrdl_decode pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; end - end - - //------- reg assigns for pio i/f - always_ff @ (posedge uclk) begin pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; end //------- reg assigns for external i/f always_ff @ (posedge uclk) begin + if (reset) begin + d2h_l2_r16_child_l3_child_ext_base_regs_we_ex <= #1 1'b0; + d2h_l2_r16_child_l3_child_ext_base_regs_re_ex <= #1 1'b0; + end + else begin + d2h_l2_r16_child_l3_child_ext_base_regs_we_ex <= #1 d2h_l2_r16_child_l3_child_ext_base_regs_we_next & ~h2d_l2_r16_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_r16_child_l3_child_ext_base_regs_nack_ex; + d2h_l2_r16_child_l3_child_ext_base_regs_re_ex <= #1 d2h_l2_r16_child_l3_child_ext_base_regs_re_next & ~h2d_l2_r16_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_r16_child_l3_child_ext_base_regs_nack_ex; + end d2h_l2_r16_child_l3_child_ext_base_regs_w_ex <= #1 d2h_l2_r16_child_l3_child_ext_base_regs_w_next; d2h_l2_r16_child_l3_child_ext_base_regs_addr_ex <= #1 d2h_l2_r16_child_l3_child_ext_base_regs_addr_next; end @@ -7323,22 +7299,6 @@ module base_map_l2_s8_child_jrdl_decode end end - //------- reg assigns for external i/f (reset signal = reset) - always_ff @ (posedge uclk) begin - if (reset) begin - d2h_l2_s8_child_ext_base_regs_we_ex <= #1 1'b0; - d2h_l2_s8_child_ext_base_regs_re_ex <= #1 1'b0; - d2h_l2_s8_child_l3_child_we_ex <= #1 1'b0; - d2h_l2_s8_child_l3_child_re_ex <= #1 1'b0; - end - else begin - d2h_l2_s8_child_ext_base_regs_we_ex <= #1 d2h_l2_s8_child_ext_base_regs_we_next & ~h2d_l2_s8_child_ext_base_regs_ack_ex & ~h2d_l2_s8_child_ext_base_regs_nack_ex; - d2h_l2_s8_child_ext_base_regs_re_ex <= #1 d2h_l2_s8_child_ext_base_regs_re_next & ~h2d_l2_s8_child_ext_base_regs_ack_ex & ~h2d_l2_s8_child_ext_base_regs_nack_ex; - d2h_l2_s8_child_l3_child_we_ex <= #1 d2h_l2_s8_child_l3_child_we_next & ~h2d_l2_s8_child_l3_child_ack_ex & ~h2d_l2_s8_child_l3_child_nack_ex; - d2h_l2_s8_child_l3_child_re_ex <= #1 d2h_l2_s8_child_l3_child_re_next & ~h2d_l2_s8_child_l3_child_ack_ex & ~h2d_l2_s8_child_l3_child_nack_ex; - end - end - //------- combinatorial assigns for serial8 i/f always_comb begin s8_state_next = s8_state; @@ -7437,16 +7397,16 @@ module base_map_l2_s8_child_jrdl_decode end else begin s8_state <= #1 s8_state_next; - s8_addr_accum <= #1 s8_addr_accum_next; - s8_wdata_accum <= #1 s8_wdata_accum_next; - s8_wr_state_capture <= #1 s8_wr_state_capture_next; - s8_rdata_capture <= #1 s8_rdata_capture_next; s8_addr_cnt <= #1 s8_addr_cnt_next; s8_data_cnt <= #1 s8_data_cnt_next; end + s8_addr_accum <= #1 s8_addr_accum_next; + s8_wdata_accum <= #1 s8_wdata_accum_next; + s8_wr_state_capture <= #1 s8_wr_state_capture_next; + s8_rdata_capture <= #1 s8_rdata_capture_next; end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always_ff @ (posedge uclk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -7456,16 +7416,24 @@ module base_map_l2_s8_child_jrdl_decode pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; end - end - - //------- reg assigns for pio i/f - always_ff @ (posedge uclk) begin pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; end //------- reg assigns for external i/f always_ff @ (posedge uclk) begin + if (reset) begin + d2h_l2_s8_child_ext_base_regs_we_ex <= #1 1'b0; + d2h_l2_s8_child_ext_base_regs_re_ex <= #1 1'b0; + d2h_l2_s8_child_l3_child_we_ex <= #1 1'b0; + d2h_l2_s8_child_l3_child_re_ex <= #1 1'b0; + end + else begin + d2h_l2_s8_child_ext_base_regs_we_ex <= #1 d2h_l2_s8_child_ext_base_regs_we_next & ~h2d_l2_s8_child_ext_base_regs_ack_ex & ~h2d_l2_s8_child_ext_base_regs_nack_ex; + d2h_l2_s8_child_ext_base_regs_re_ex <= #1 d2h_l2_s8_child_ext_base_regs_re_next & ~h2d_l2_s8_child_ext_base_regs_ack_ex & ~h2d_l2_s8_child_ext_base_regs_nack_ex; + d2h_l2_s8_child_l3_child_we_ex <= #1 d2h_l2_s8_child_l3_child_we_next & ~h2d_l2_s8_child_l3_child_ack_ex & ~h2d_l2_s8_child_l3_child_nack_ex; + d2h_l2_s8_child_l3_child_re_ex <= #1 d2h_l2_s8_child_l3_child_re_next & ~h2d_l2_s8_child_l3_child_ack_ex & ~h2d_l2_s8_child_l3_child_nack_ex; + end d2h_l2_s8_child_ext_base_regs_w_ex <= #1 d2h_l2_s8_child_ext_base_regs_w_next; d2h_l2_s8_child_ext_base_regs_addr_ex <= #1 d2h_l2_s8_child_ext_base_regs_addr_next; d2h_l2_s8_child_l3_child_w_ex <= #1 d2h_l2_s8_child_l3_child_w_next; @@ -7575,11 +7543,11 @@ module base_map_l2_s8_child_jrdl_decode s8_l2_s8_child_l3_child_cmdData_dly1 <= #1 s8_l2_s8_child_l3_child_cmdData_dly0; s8_l2_s8_child_l3_child_resValid_dly1 <= #1 s8_l2_s8_child_l3_child_resValid_dly0; s8_l2_s8_child_l3_child_resData_dly1 <= #1 s8_l2_s8_child_l3_child_resData_dly0; - s8_l2_s8_child_l3_child_rdata_accum <= #1 s8_l2_s8_child_l3_child_rdata_accum_next; h2d_l2_s8_child_l3_child_nack_early <= #1 h2d_l2_s8_child_l3_child_nack_early_next; s8_l2_s8_child_l3_child_addr_cnt <= #1 s8_l2_s8_child_l3_child_addr_cnt_next; s8_l2_s8_child_l3_child_data_cnt <= #1 s8_l2_s8_child_l3_child_data_cnt_next; end + s8_l2_s8_child_l3_child_rdata_accum <= #1 s8_l2_s8_child_l3_child_rdata_accum_next; end //------- reg assigns for clock gate delay @@ -8928,18 +8896,6 @@ module base_map_l2_s8_child_l3_child_jrdl_decode end end - //------- reg assigns for external i/f (reset signal = reset) - always_ff @ (posedge uclk) begin - if (reset) begin - d2h_l2_s8_child_l3_child_ext_base_regs_we_ex <= #1 1'b0; - d2h_l2_s8_child_l3_child_ext_base_regs_re_ex <= #1 1'b0; - end - else begin - d2h_l2_s8_child_l3_child_ext_base_regs_we_ex <= #1 d2h_l2_s8_child_l3_child_ext_base_regs_we_next & ~h2d_l2_s8_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_s8_child_l3_child_ext_base_regs_nack_ex; - d2h_l2_s8_child_l3_child_ext_base_regs_re_ex <= #1 d2h_l2_s8_child_l3_child_ext_base_regs_re_next & ~h2d_l2_s8_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_s8_child_l3_child_ext_base_regs_nack_ex; - end - end - //------- combinatorial assigns for serial8 i/f always_comb begin s8_state_next = s8_state; @@ -9038,16 +8994,16 @@ module base_map_l2_s8_child_l3_child_jrdl_decode end else begin s8_state <= #1 s8_state_next; - s8_addr_accum <= #1 s8_addr_accum_next; - s8_wdata_accum <= #1 s8_wdata_accum_next; - s8_wr_state_capture <= #1 s8_wr_state_capture_next; - s8_rdata_capture <= #1 s8_rdata_capture_next; s8_addr_cnt <= #1 s8_addr_cnt_next; s8_data_cnt <= #1 s8_data_cnt_next; end + s8_addr_accum <= #1 s8_addr_accum_next; + s8_wdata_accum <= #1 s8_wdata_accum_next; + s8_wr_state_capture <= #1 s8_wr_state_capture_next; + s8_rdata_capture <= #1 s8_rdata_capture_next; end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always_ff @ (posedge uclk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -9057,16 +9013,20 @@ module base_map_l2_s8_child_l3_child_jrdl_decode pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; end - end - - //------- reg assigns for pio i/f - always_ff @ (posedge uclk) begin pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; end //------- reg assigns for external i/f always_ff @ (posedge uclk) begin + if (reset) begin + d2h_l2_s8_child_l3_child_ext_base_regs_we_ex <= #1 1'b0; + d2h_l2_s8_child_l3_child_ext_base_regs_re_ex <= #1 1'b0; + end + else begin + d2h_l2_s8_child_l3_child_ext_base_regs_we_ex <= #1 d2h_l2_s8_child_l3_child_ext_base_regs_we_next & ~h2d_l2_s8_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_s8_child_l3_child_ext_base_regs_nack_ex; + d2h_l2_s8_child_l3_child_ext_base_regs_re_ex <= #1 d2h_l2_s8_child_l3_child_ext_base_regs_re_next & ~h2d_l2_s8_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_s8_child_l3_child_ext_base_regs_nack_ex; + end d2h_l2_s8_child_l3_child_ext_base_regs_w_ex <= #1 d2h_l2_s8_child_l3_child_ext_base_regs_w_next; d2h_l2_s8_child_l3_child_ext_base_regs_addr_ex <= #1 d2h_l2_s8_child_l3_child_ext_base_regs_addr_next; end @@ -10430,23 +10390,7 @@ module base_map_l2_dflt_child_jrdl_decode end end - //------- reg assigns for external i/f (reset signal = reset) - always_ff @ (posedge uclk) begin - if (reset) begin - d2h_l2_dflt_child_ext_base_regs_we_ex <= #1 1'b0; - d2h_l2_dflt_child_ext_base_regs_re_ex <= #1 1'b0; - d2h_l2_dflt_child_l3_child_we_ex <= #1 1'b0; - d2h_l2_dflt_child_l3_child_re_ex <= #1 1'b0; - end - else begin - d2h_l2_dflt_child_ext_base_regs_we_ex <= #1 d2h_l2_dflt_child_ext_base_regs_we_next & ~h2d_l2_dflt_child_ext_base_regs_ack_ex & ~h2d_l2_dflt_child_ext_base_regs_nack_ex; - d2h_l2_dflt_child_ext_base_regs_re_ex <= #1 d2h_l2_dflt_child_ext_base_regs_re_next & ~h2d_l2_dflt_child_ext_base_regs_ack_ex & ~h2d_l2_dflt_child_ext_base_regs_nack_ex; - d2h_l2_dflt_child_l3_child_we_ex <= #1 d2h_l2_dflt_child_l3_child_we_next & ~h2d_l2_dflt_child_l3_child_ack_ex & ~h2d_l2_dflt_child_l3_child_nack_ex; - d2h_l2_dflt_child_l3_child_re_ex <= #1 d2h_l2_dflt_child_l3_child_re_next & ~h2d_l2_dflt_child_l3_child_ack_ex & ~h2d_l2_dflt_child_l3_child_nack_ex; - end - end - - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always_ff @ (posedge uclk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -10456,16 +10400,24 @@ module base_map_l2_dflt_child_jrdl_decode pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; end - end - - //------- reg assigns for pio i/f - always_ff @ (posedge uclk) begin pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; end //------- reg assigns for external i/f always_ff @ (posedge uclk) begin + if (reset) begin + d2h_l2_dflt_child_ext_base_regs_we_ex <= #1 1'b0; + d2h_l2_dflt_child_ext_base_regs_re_ex <= #1 1'b0; + d2h_l2_dflt_child_l3_child_we_ex <= #1 1'b0; + d2h_l2_dflt_child_l3_child_re_ex <= #1 1'b0; + end + else begin + d2h_l2_dflt_child_ext_base_regs_we_ex <= #1 d2h_l2_dflt_child_ext_base_regs_we_next & ~h2d_l2_dflt_child_ext_base_regs_ack_ex & ~h2d_l2_dflt_child_ext_base_regs_nack_ex; + d2h_l2_dflt_child_ext_base_regs_re_ex <= #1 d2h_l2_dflt_child_ext_base_regs_re_next & ~h2d_l2_dflt_child_ext_base_regs_ack_ex & ~h2d_l2_dflt_child_ext_base_regs_nack_ex; + d2h_l2_dflt_child_l3_child_we_ex <= #1 d2h_l2_dflt_child_l3_child_we_next & ~h2d_l2_dflt_child_l3_child_ack_ex & ~h2d_l2_dflt_child_l3_child_nack_ex; + d2h_l2_dflt_child_l3_child_re_ex <= #1 d2h_l2_dflt_child_l3_child_re_next & ~h2d_l2_dflt_child_l3_child_ack_ex & ~h2d_l2_dflt_child_l3_child_nack_ex; + end d2h_l2_dflt_child_ext_base_regs_w_ex <= #1 d2h_l2_dflt_child_ext_base_regs_w_next; d2h_l2_dflt_child_ext_base_regs_addr_ex <= #1 d2h_l2_dflt_child_ext_base_regs_addr_next; d2h_l2_dflt_child_l3_child_w_ex <= #1 d2h_l2_dflt_child_l3_child_w_next; @@ -10575,11 +10527,11 @@ module base_map_l2_dflt_child_jrdl_decode s8_l2_dflt_child_l3_child_cmdData_dly1 <= #1 s8_l2_dflt_child_l3_child_cmdData_dly0; s8_l2_dflt_child_l3_child_resValid_dly1 <= #1 s8_l2_dflt_child_l3_child_resValid_dly0; s8_l2_dflt_child_l3_child_resData_dly1 <= #1 s8_l2_dflt_child_l3_child_resData_dly0; - s8_l2_dflt_child_l3_child_rdata_accum <= #1 s8_l2_dflt_child_l3_child_rdata_accum_next; h2d_l2_dflt_child_l3_child_nack_early <= #1 h2d_l2_dflt_child_l3_child_nack_early_next; s8_l2_dflt_child_l3_child_addr_cnt <= #1 s8_l2_dflt_child_l3_child_addr_cnt_next; s8_l2_dflt_child_l3_child_data_cnt <= #1 s8_l2_dflt_child_l3_child_data_cnt_next; end + s8_l2_dflt_child_l3_child_rdata_accum <= #1 s8_l2_dflt_child_l3_child_rdata_accum_next; end //------- reg assigns for clock gate delay @@ -11934,18 +11886,6 @@ module base_map_l2_dflt_child_l3_child_jrdl_decode end end - //------- reg assigns for external i/f (reset signal = reset) - always_ff @ (posedge uclk) begin - if (reset) begin - d2h_l2_dflt_child_l3_child_ext_base_regs_we_ex <= #1 1'b0; - d2h_l2_dflt_child_l3_child_ext_base_regs_re_ex <= #1 1'b0; - end - else begin - d2h_l2_dflt_child_l3_child_ext_base_regs_we_ex <= #1 d2h_l2_dflt_child_l3_child_ext_base_regs_we_next & ~h2d_l2_dflt_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_dflt_child_l3_child_ext_base_regs_nack_ex; - d2h_l2_dflt_child_l3_child_ext_base_regs_re_ex <= #1 d2h_l2_dflt_child_l3_child_ext_base_regs_re_next & ~h2d_l2_dflt_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_dflt_child_l3_child_ext_base_regs_nack_ex; - end - end - //------- combinatorial assigns for serial8 i/f always_comb begin s8_state_next = s8_state; @@ -12044,16 +11984,16 @@ module base_map_l2_dflt_child_l3_child_jrdl_decode end else begin s8_state <= #1 s8_state_next; - s8_addr_accum <= #1 s8_addr_accum_next; - s8_wdata_accum <= #1 s8_wdata_accum_next; - s8_wr_state_capture <= #1 s8_wr_state_capture_next; - s8_rdata_capture <= #1 s8_rdata_capture_next; s8_addr_cnt <= #1 s8_addr_cnt_next; s8_data_cnt <= #1 s8_data_cnt_next; end + s8_addr_accum <= #1 s8_addr_accum_next; + s8_wdata_accum <= #1 s8_wdata_accum_next; + s8_wr_state_capture <= #1 s8_wr_state_capture_next; + s8_rdata_capture <= #1 s8_rdata_capture_next; end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always_ff @ (posedge uclk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -12063,16 +12003,20 @@ module base_map_l2_dflt_child_l3_child_jrdl_decode pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; end - end - - //------- reg assigns for pio i/f - always_ff @ (posedge uclk) begin pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; end //------- reg assigns for external i/f always_ff @ (posedge uclk) begin + if (reset) begin + d2h_l2_dflt_child_l3_child_ext_base_regs_we_ex <= #1 1'b0; + d2h_l2_dflt_child_l3_child_ext_base_regs_re_ex <= #1 1'b0; + end + else begin + d2h_l2_dflt_child_l3_child_ext_base_regs_we_ex <= #1 d2h_l2_dflt_child_l3_child_ext_base_regs_we_next & ~h2d_l2_dflt_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_dflt_child_l3_child_ext_base_regs_nack_ex; + d2h_l2_dflt_child_l3_child_ext_base_regs_re_ex <= #1 d2h_l2_dflt_child_l3_child_ext_base_regs_re_next & ~h2d_l2_dflt_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_dflt_child_l3_child_ext_base_regs_nack_ex; + end d2h_l2_dflt_child_l3_child_ext_base_regs_w_ex <= #1 d2h_l2_dflt_child_l3_child_ext_base_regs_w_next; d2h_l2_dflt_child_l3_child_ext_base_regs_addr_ex <= #1 d2h_l2_dflt_child_l3_child_ext_base_regs_addr_next; end @@ -12765,14 +12709,14 @@ module base_map_singleton_rf_s8_jrdl_decode end else begin s8_state <= #1 s8_state_next; - s8_wdata_accum <= #1 s8_wdata_accum_next; - s8_wr_state_capture <= #1 s8_wr_state_capture_next; - s8_rdata_capture <= #1 s8_rdata_capture_next; s8_data_cnt <= #1 s8_data_cnt_next; end + s8_wdata_accum <= #1 s8_wdata_accum_next; + s8_wr_state_capture <= #1 s8_wr_state_capture_next; + s8_rdata_capture <= #1 s8_rdata_capture_next; end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always_ff @ (posedge uclk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -12782,10 +12726,6 @@ module base_map_singleton_rf_s8_jrdl_decode pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; end - end - - //------- reg assigns for pio i/f - always_ff @ (posedge uclk) begin pio_dec_write_data_d1 <= #1 pio_dec_write_data; end @@ -13122,7 +13062,7 @@ module base_map_singleton_rf_r16_jrdl_decode end end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always_ff @ (posedge uclk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -13132,10 +13072,6 @@ module base_map_singleton_rf_r16_jrdl_decode pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; end - end - - //------- reg assigns for pio i/f - always_ff @ (posedge uclk) begin pio_dec_write_data_d1 <= #1 pio_dec_write_data; end @@ -13618,7 +13554,7 @@ module base_map_singleton_rf_dflt_jrdl_decode end end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always_ff @ (posedge uclk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -13628,10 +13564,6 @@ module base_map_singleton_rf_dflt_jrdl_decode pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; end - end - - //------- reg assigns for pio i/f - always_ff @ (posedge uclk) begin pio_dec_write_data_d1 <= #1 pio_dec_write_data; end diff --git a/test/basic_tests/rdl_hier_02/golden/output.v b/test/basic_tests/rdl_hier_02/golden/output.v index 9c35c4e..27e085d 100644 --- a/test/basic_tests/rdl_hier_02/golden/output.v +++ b/test/basic_tests/rdl_hier_02/golden/output.v @@ -1,7 +1,7 @@ -// Ordt 190606.01 autogenerated file +// Ordt 190615.01 autogenerated file // Input: ./rdl_hier_02/test.rdl // Parms: ./rdl_hier_02/test.parms -// Date: Thu Jun 06 13:30:57 EDT 2019 +// Date: Sat Jun 15 21:05:42 EDT 2019 // // @@ -1549,12 +1549,96 @@ module base_map_jrdl_decode //------- reg assigns for pio i/f always @ (posedge uclk) begin + if (reset) begin + pio_write_active <= #1 1'b0; + pio_read_active <= #1 1'b0; + end + else begin + pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; + pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; + end pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; end //------- reg assigns for external i/f always @ (posedge uclk) begin + if (reset) begin + d2h_ext_base_regs_we_ex <= #1 1'b0; + d2h_ext_base_regs_re_ex <= #1 1'b0; + d2h_l2_r16_child_we_ex <= #1 1'b0; + d2h_l2_r16_child_re_ex <= #1 1'b0; + d2h_l2_s8_child_we_ex <= #1 1'b0; + d2h_l2_s8_child_re_ex <= #1 1'b0; + d2h_l2_dflt_child_we_ex <= #1 1'b0; + d2h_l2_dflt_child_re_ex <= #1 1'b0; + d2h_singleton_rf_s8_we_ex <= #1 1'b0; + d2h_singleton_rf_s8_re_ex <= #1 1'b0; + d2h_singleton_rf_r16_we_ex <= #1 1'b0; + d2h_singleton_rf_r16_re_ex <= #1 1'b0; + d2h_singleton_rf_dflt_we_ex <= #1 1'b0; + d2h_singleton_rf_dflt_re_ex <= #1 1'b0; + d2h_rf_lvl2_0_rf_lvl1_0_reg_dflt_we_ex <= #1 1'b0; + d2h_rf_lvl2_0_rf_lvl1_0_reg_dflt_re_ex <= #1 1'b0; + d2h_rf_lvl2_0_rf_lvl1_reg_l1_we_ex <= #1 1'b0; + d2h_rf_lvl2_0_rf_lvl1_reg_l1_re_ex <= #1 1'b0; + d2h_rf_lvl2_rf_lvl1_reg_l2_we_ex <= #1 1'b0; + d2h_rf_lvl2_rf_lvl1_reg_l2_re_ex <= #1 1'b0; + d2h_rf_lvl2_0_rf_lvl1_1_reg_dflt_we_ex <= #1 1'b0; + d2h_rf_lvl2_0_rf_lvl1_1_reg_dflt_re_ex <= #1 1'b0; + d2h_rf_lvl2_0_rf_lvl1_2_reg_dflt_we_ex <= #1 1'b0; + d2h_rf_lvl2_0_rf_lvl1_2_reg_dflt_re_ex <= #1 1'b0; + d2h_rf_lvl2_0_rf_lvl1_3_reg_dflt_we_ex <= #1 1'b0; + d2h_rf_lvl2_0_rf_lvl1_3_reg_dflt_re_ex <= #1 1'b0; + d2h_rf_lvl2_1_rf_lvl1_0_reg_dflt_we_ex <= #1 1'b0; + d2h_rf_lvl2_1_rf_lvl1_0_reg_dflt_re_ex <= #1 1'b0; + d2h_rf_lvl2_1_rf_lvl1_reg_l1_we_ex <= #1 1'b0; + d2h_rf_lvl2_1_rf_lvl1_reg_l1_re_ex <= #1 1'b0; + d2h_rf_lvl2_1_rf_lvl1_1_reg_dflt_we_ex <= #1 1'b0; + d2h_rf_lvl2_1_rf_lvl1_1_reg_dflt_re_ex <= #1 1'b0; + d2h_rf_lvl2_1_rf_lvl1_2_reg_dflt_we_ex <= #1 1'b0; + d2h_rf_lvl2_1_rf_lvl1_2_reg_dflt_re_ex <= #1 1'b0; + d2h_rf_lvl2_1_rf_lvl1_3_reg_dflt_we_ex <= #1 1'b0; + d2h_rf_lvl2_1_rf_lvl1_3_reg_dflt_re_ex <= #1 1'b0; + end + else begin + d2h_ext_base_regs_we_ex <= #1 d2h_ext_base_regs_we_next & ~h2d_ext_base_regs_ack_ex & ~h2d_ext_base_regs_nack_ex; + d2h_ext_base_regs_re_ex <= #1 d2h_ext_base_regs_re_next & ~h2d_ext_base_regs_ack_ex & ~h2d_ext_base_regs_nack_ex; + d2h_l2_r16_child_we_ex <= #1 d2h_l2_r16_child_we_next & ~h2d_l2_r16_child_ack_ex & ~h2d_l2_r16_child_nack_ex; + d2h_l2_r16_child_re_ex <= #1 d2h_l2_r16_child_re_next & ~h2d_l2_r16_child_ack_ex & ~h2d_l2_r16_child_nack_ex; + d2h_l2_s8_child_we_ex <= #1 d2h_l2_s8_child_we_next & ~h2d_l2_s8_child_ack_ex & ~h2d_l2_s8_child_nack_ex; + d2h_l2_s8_child_re_ex <= #1 d2h_l2_s8_child_re_next & ~h2d_l2_s8_child_ack_ex & ~h2d_l2_s8_child_nack_ex; + d2h_l2_dflt_child_we_ex <= #1 d2h_l2_dflt_child_we_next & ~h2d_l2_dflt_child_ack_ex & ~h2d_l2_dflt_child_nack_ex; + d2h_l2_dflt_child_re_ex <= #1 d2h_l2_dflt_child_re_next & ~h2d_l2_dflt_child_ack_ex & ~h2d_l2_dflt_child_nack_ex; + d2h_singleton_rf_s8_we_ex <= #1 d2h_singleton_rf_s8_we_next & ~h2d_singleton_rf_s8_ack_ex & ~h2d_singleton_rf_s8_nack_ex; + d2h_singleton_rf_s8_re_ex <= #1 d2h_singleton_rf_s8_re_next & ~h2d_singleton_rf_s8_ack_ex & ~h2d_singleton_rf_s8_nack_ex; + d2h_singleton_rf_r16_we_ex <= #1 d2h_singleton_rf_r16_we_next & ~h2d_singleton_rf_r16_ack_ex & ~h2d_singleton_rf_r16_nack_ex; + d2h_singleton_rf_r16_re_ex <= #1 d2h_singleton_rf_r16_re_next & ~h2d_singleton_rf_r16_ack_ex & ~h2d_singleton_rf_r16_nack_ex; + d2h_singleton_rf_dflt_we_ex <= #1 d2h_singleton_rf_dflt_we_next & ~h2d_singleton_rf_dflt_ack_ex & ~h2d_singleton_rf_dflt_nack_ex; + d2h_singleton_rf_dflt_re_ex <= #1 d2h_singleton_rf_dflt_re_next & ~h2d_singleton_rf_dflt_ack_ex & ~h2d_singleton_rf_dflt_nack_ex; + d2h_rf_lvl2_0_rf_lvl1_0_reg_dflt_we_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_0_reg_dflt_we_next & ~h2d_rf_lvl2_0_rf_lvl1_0_reg_dflt_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_0_reg_dflt_nack_ex; + d2h_rf_lvl2_0_rf_lvl1_0_reg_dflt_re_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_0_reg_dflt_re_next & ~h2d_rf_lvl2_0_rf_lvl1_0_reg_dflt_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_0_reg_dflt_nack_ex; + d2h_rf_lvl2_0_rf_lvl1_reg_l1_we_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_reg_l1_we_next & ~h2d_rf_lvl2_0_rf_lvl1_reg_l1_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_reg_l1_nack_ex; + d2h_rf_lvl2_0_rf_lvl1_reg_l1_re_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_reg_l1_re_next & ~h2d_rf_lvl2_0_rf_lvl1_reg_l1_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_reg_l1_nack_ex; + d2h_rf_lvl2_rf_lvl1_reg_l2_we_ex <= #1 d2h_rf_lvl2_rf_lvl1_reg_l2_we_next & ~h2d_rf_lvl2_rf_lvl1_reg_l2_ack_ex & ~h2d_rf_lvl2_rf_lvl1_reg_l2_nack_ex; + d2h_rf_lvl2_rf_lvl1_reg_l2_re_ex <= #1 d2h_rf_lvl2_rf_lvl1_reg_l2_re_next & ~h2d_rf_lvl2_rf_lvl1_reg_l2_ack_ex & ~h2d_rf_lvl2_rf_lvl1_reg_l2_nack_ex; + d2h_rf_lvl2_0_rf_lvl1_1_reg_dflt_we_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_1_reg_dflt_we_next & ~h2d_rf_lvl2_0_rf_lvl1_1_reg_dflt_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_1_reg_dflt_nack_ex; + d2h_rf_lvl2_0_rf_lvl1_1_reg_dflt_re_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_1_reg_dflt_re_next & ~h2d_rf_lvl2_0_rf_lvl1_1_reg_dflt_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_1_reg_dflt_nack_ex; + d2h_rf_lvl2_0_rf_lvl1_2_reg_dflt_we_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_2_reg_dflt_we_next & ~h2d_rf_lvl2_0_rf_lvl1_2_reg_dflt_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_2_reg_dflt_nack_ex; + d2h_rf_lvl2_0_rf_lvl1_2_reg_dflt_re_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_2_reg_dflt_re_next & ~h2d_rf_lvl2_0_rf_lvl1_2_reg_dflt_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_2_reg_dflt_nack_ex; + d2h_rf_lvl2_0_rf_lvl1_3_reg_dflt_we_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_3_reg_dflt_we_next & ~h2d_rf_lvl2_0_rf_lvl1_3_reg_dflt_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_3_reg_dflt_nack_ex; + d2h_rf_lvl2_0_rf_lvl1_3_reg_dflt_re_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_3_reg_dflt_re_next & ~h2d_rf_lvl2_0_rf_lvl1_3_reg_dflt_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_3_reg_dflt_nack_ex; + d2h_rf_lvl2_1_rf_lvl1_0_reg_dflt_we_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_0_reg_dflt_we_next & ~h2d_rf_lvl2_1_rf_lvl1_0_reg_dflt_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_0_reg_dflt_nack_ex; + d2h_rf_lvl2_1_rf_lvl1_0_reg_dflt_re_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_0_reg_dflt_re_next & ~h2d_rf_lvl2_1_rf_lvl1_0_reg_dflt_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_0_reg_dflt_nack_ex; + d2h_rf_lvl2_1_rf_lvl1_reg_l1_we_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_reg_l1_we_next & ~h2d_rf_lvl2_1_rf_lvl1_reg_l1_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_reg_l1_nack_ex; + d2h_rf_lvl2_1_rf_lvl1_reg_l1_re_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_reg_l1_re_next & ~h2d_rf_lvl2_1_rf_lvl1_reg_l1_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_reg_l1_nack_ex; + d2h_rf_lvl2_1_rf_lvl1_1_reg_dflt_we_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_1_reg_dflt_we_next & ~h2d_rf_lvl2_1_rf_lvl1_1_reg_dflt_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_1_reg_dflt_nack_ex; + d2h_rf_lvl2_1_rf_lvl1_1_reg_dflt_re_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_1_reg_dflt_re_next & ~h2d_rf_lvl2_1_rf_lvl1_1_reg_dflt_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_1_reg_dflt_nack_ex; + d2h_rf_lvl2_1_rf_lvl1_2_reg_dflt_we_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_2_reg_dflt_we_next & ~h2d_rf_lvl2_1_rf_lvl1_2_reg_dflt_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_2_reg_dflt_nack_ex; + d2h_rf_lvl2_1_rf_lvl1_2_reg_dflt_re_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_2_reg_dflt_re_next & ~h2d_rf_lvl2_1_rf_lvl1_2_reg_dflt_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_2_reg_dflt_nack_ex; + d2h_rf_lvl2_1_rf_lvl1_3_reg_dflt_we_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_3_reg_dflt_we_next & ~h2d_rf_lvl2_1_rf_lvl1_3_reg_dflt_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_3_reg_dflt_nack_ex; + d2h_rf_lvl2_1_rf_lvl1_3_reg_dflt_re_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_3_reg_dflt_re_next & ~h2d_rf_lvl2_1_rf_lvl1_3_reg_dflt_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_3_reg_dflt_nack_ex; + end d2h_ext_base_regs_w_ex <= #1 d2h_ext_base_regs_w_next; d2h_ext_base_regs_addr_ex <= #1 d2h_ext_base_regs_addr_next; d2h_l2_r16_child_w_ex <= #1 d2h_l2_r16_child_w_next; @@ -1691,9 +1775,9 @@ module base_map_jrdl_decode r16_singleton_rf_r16_cmdData_dly1 <= #1 r16_singleton_rf_r16_cmdData_dly0; r16_singleton_rf_r16_resValid_dly1 <= #1 r16_singleton_rf_r16_resValid_dly0; r16_singleton_rf_r16_resData_dly1 <= #1 r16_singleton_rf_r16_resData_dly0; - r16_singleton_rf_r16_rdata_accum <= #1 r16_singleton_rf_r16_rdata_accum_next; r16_singleton_rf_r16_data_cnt <= #1 r16_singleton_rf_r16_data_cnt_next; end + r16_singleton_rf_r16_rdata_accum <= #1 r16_singleton_rf_r16_rdata_accum_next; end //------- combinatorial assigns for pio ack/nack @@ -1722,98 +1806,6 @@ module base_map_jrdl_decode end end - //------- reg assigns for external i/f (reset signal = reset) - always @ (posedge uclk) begin - if (reset) begin - d2h_ext_base_regs_we_ex <= #1 1'b0; - d2h_ext_base_regs_re_ex <= #1 1'b0; - d2h_l2_r16_child_we_ex <= #1 1'b0; - d2h_l2_r16_child_re_ex <= #1 1'b0; - d2h_l2_s8_child_we_ex <= #1 1'b0; - d2h_l2_s8_child_re_ex <= #1 1'b0; - d2h_l2_dflt_child_we_ex <= #1 1'b0; - d2h_l2_dflt_child_re_ex <= #1 1'b0; - d2h_singleton_rf_s8_we_ex <= #1 1'b0; - d2h_singleton_rf_s8_re_ex <= #1 1'b0; - d2h_singleton_rf_r16_we_ex <= #1 1'b0; - d2h_singleton_rf_r16_re_ex <= #1 1'b0; - d2h_singleton_rf_dflt_we_ex <= #1 1'b0; - d2h_singleton_rf_dflt_re_ex <= #1 1'b0; - d2h_rf_lvl2_0_rf_lvl1_0_reg_dflt_we_ex <= #1 1'b0; - d2h_rf_lvl2_0_rf_lvl1_0_reg_dflt_re_ex <= #1 1'b0; - d2h_rf_lvl2_0_rf_lvl1_reg_l1_we_ex <= #1 1'b0; - d2h_rf_lvl2_0_rf_lvl1_reg_l1_re_ex <= #1 1'b0; - d2h_rf_lvl2_rf_lvl1_reg_l2_we_ex <= #1 1'b0; - d2h_rf_lvl2_rf_lvl1_reg_l2_re_ex <= #1 1'b0; - d2h_rf_lvl2_0_rf_lvl1_1_reg_dflt_we_ex <= #1 1'b0; - d2h_rf_lvl2_0_rf_lvl1_1_reg_dflt_re_ex <= #1 1'b0; - d2h_rf_lvl2_0_rf_lvl1_2_reg_dflt_we_ex <= #1 1'b0; - d2h_rf_lvl2_0_rf_lvl1_2_reg_dflt_re_ex <= #1 1'b0; - d2h_rf_lvl2_0_rf_lvl1_3_reg_dflt_we_ex <= #1 1'b0; - d2h_rf_lvl2_0_rf_lvl1_3_reg_dflt_re_ex <= #1 1'b0; - d2h_rf_lvl2_1_rf_lvl1_0_reg_dflt_we_ex <= #1 1'b0; - d2h_rf_lvl2_1_rf_lvl1_0_reg_dflt_re_ex <= #1 1'b0; - d2h_rf_lvl2_1_rf_lvl1_reg_l1_we_ex <= #1 1'b0; - d2h_rf_lvl2_1_rf_lvl1_reg_l1_re_ex <= #1 1'b0; - d2h_rf_lvl2_1_rf_lvl1_1_reg_dflt_we_ex <= #1 1'b0; - d2h_rf_lvl2_1_rf_lvl1_1_reg_dflt_re_ex <= #1 1'b0; - d2h_rf_lvl2_1_rf_lvl1_2_reg_dflt_we_ex <= #1 1'b0; - d2h_rf_lvl2_1_rf_lvl1_2_reg_dflt_re_ex <= #1 1'b0; - d2h_rf_lvl2_1_rf_lvl1_3_reg_dflt_we_ex <= #1 1'b0; - d2h_rf_lvl2_1_rf_lvl1_3_reg_dflt_re_ex <= #1 1'b0; - end - else begin - d2h_ext_base_regs_we_ex <= #1 d2h_ext_base_regs_we_next & ~h2d_ext_base_regs_ack_ex & ~h2d_ext_base_regs_nack_ex; - d2h_ext_base_regs_re_ex <= #1 d2h_ext_base_regs_re_next & ~h2d_ext_base_regs_ack_ex & ~h2d_ext_base_regs_nack_ex; - d2h_l2_r16_child_we_ex <= #1 d2h_l2_r16_child_we_next & ~h2d_l2_r16_child_ack_ex & ~h2d_l2_r16_child_nack_ex; - d2h_l2_r16_child_re_ex <= #1 d2h_l2_r16_child_re_next & ~h2d_l2_r16_child_ack_ex & ~h2d_l2_r16_child_nack_ex; - d2h_l2_s8_child_we_ex <= #1 d2h_l2_s8_child_we_next & ~h2d_l2_s8_child_ack_ex & ~h2d_l2_s8_child_nack_ex; - d2h_l2_s8_child_re_ex <= #1 d2h_l2_s8_child_re_next & ~h2d_l2_s8_child_ack_ex & ~h2d_l2_s8_child_nack_ex; - d2h_l2_dflt_child_we_ex <= #1 d2h_l2_dflt_child_we_next & ~h2d_l2_dflt_child_ack_ex & ~h2d_l2_dflt_child_nack_ex; - d2h_l2_dflt_child_re_ex <= #1 d2h_l2_dflt_child_re_next & ~h2d_l2_dflt_child_ack_ex & ~h2d_l2_dflt_child_nack_ex; - d2h_singleton_rf_s8_we_ex <= #1 d2h_singleton_rf_s8_we_next & ~h2d_singleton_rf_s8_ack_ex & ~h2d_singleton_rf_s8_nack_ex; - d2h_singleton_rf_s8_re_ex <= #1 d2h_singleton_rf_s8_re_next & ~h2d_singleton_rf_s8_ack_ex & ~h2d_singleton_rf_s8_nack_ex; - d2h_singleton_rf_r16_we_ex <= #1 d2h_singleton_rf_r16_we_next & ~h2d_singleton_rf_r16_ack_ex & ~h2d_singleton_rf_r16_nack_ex; - d2h_singleton_rf_r16_re_ex <= #1 d2h_singleton_rf_r16_re_next & ~h2d_singleton_rf_r16_ack_ex & ~h2d_singleton_rf_r16_nack_ex; - d2h_singleton_rf_dflt_we_ex <= #1 d2h_singleton_rf_dflt_we_next & ~h2d_singleton_rf_dflt_ack_ex & ~h2d_singleton_rf_dflt_nack_ex; - d2h_singleton_rf_dflt_re_ex <= #1 d2h_singleton_rf_dflt_re_next & ~h2d_singleton_rf_dflt_ack_ex & ~h2d_singleton_rf_dflt_nack_ex; - d2h_rf_lvl2_0_rf_lvl1_0_reg_dflt_we_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_0_reg_dflt_we_next & ~h2d_rf_lvl2_0_rf_lvl1_0_reg_dflt_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_0_reg_dflt_nack_ex; - d2h_rf_lvl2_0_rf_lvl1_0_reg_dflt_re_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_0_reg_dflt_re_next & ~h2d_rf_lvl2_0_rf_lvl1_0_reg_dflt_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_0_reg_dflt_nack_ex; - d2h_rf_lvl2_0_rf_lvl1_reg_l1_we_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_reg_l1_we_next & ~h2d_rf_lvl2_0_rf_lvl1_reg_l1_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_reg_l1_nack_ex; - d2h_rf_lvl2_0_rf_lvl1_reg_l1_re_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_reg_l1_re_next & ~h2d_rf_lvl2_0_rf_lvl1_reg_l1_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_reg_l1_nack_ex; - d2h_rf_lvl2_rf_lvl1_reg_l2_we_ex <= #1 d2h_rf_lvl2_rf_lvl1_reg_l2_we_next & ~h2d_rf_lvl2_rf_lvl1_reg_l2_ack_ex & ~h2d_rf_lvl2_rf_lvl1_reg_l2_nack_ex; - d2h_rf_lvl2_rf_lvl1_reg_l2_re_ex <= #1 d2h_rf_lvl2_rf_lvl1_reg_l2_re_next & ~h2d_rf_lvl2_rf_lvl1_reg_l2_ack_ex & ~h2d_rf_lvl2_rf_lvl1_reg_l2_nack_ex; - d2h_rf_lvl2_0_rf_lvl1_1_reg_dflt_we_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_1_reg_dflt_we_next & ~h2d_rf_lvl2_0_rf_lvl1_1_reg_dflt_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_1_reg_dflt_nack_ex; - d2h_rf_lvl2_0_rf_lvl1_1_reg_dflt_re_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_1_reg_dflt_re_next & ~h2d_rf_lvl2_0_rf_lvl1_1_reg_dflt_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_1_reg_dflt_nack_ex; - d2h_rf_lvl2_0_rf_lvl1_2_reg_dflt_we_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_2_reg_dflt_we_next & ~h2d_rf_lvl2_0_rf_lvl1_2_reg_dflt_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_2_reg_dflt_nack_ex; - d2h_rf_lvl2_0_rf_lvl1_2_reg_dflt_re_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_2_reg_dflt_re_next & ~h2d_rf_lvl2_0_rf_lvl1_2_reg_dflt_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_2_reg_dflt_nack_ex; - d2h_rf_lvl2_0_rf_lvl1_3_reg_dflt_we_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_3_reg_dflt_we_next & ~h2d_rf_lvl2_0_rf_lvl1_3_reg_dflt_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_3_reg_dflt_nack_ex; - d2h_rf_lvl2_0_rf_lvl1_3_reg_dflt_re_ex <= #1 d2h_rf_lvl2_0_rf_lvl1_3_reg_dflt_re_next & ~h2d_rf_lvl2_0_rf_lvl1_3_reg_dflt_ack_ex & ~h2d_rf_lvl2_0_rf_lvl1_3_reg_dflt_nack_ex; - d2h_rf_lvl2_1_rf_lvl1_0_reg_dflt_we_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_0_reg_dflt_we_next & ~h2d_rf_lvl2_1_rf_lvl1_0_reg_dflt_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_0_reg_dflt_nack_ex; - d2h_rf_lvl2_1_rf_lvl1_0_reg_dflt_re_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_0_reg_dflt_re_next & ~h2d_rf_lvl2_1_rf_lvl1_0_reg_dflt_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_0_reg_dflt_nack_ex; - d2h_rf_lvl2_1_rf_lvl1_reg_l1_we_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_reg_l1_we_next & ~h2d_rf_lvl2_1_rf_lvl1_reg_l1_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_reg_l1_nack_ex; - d2h_rf_lvl2_1_rf_lvl1_reg_l1_re_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_reg_l1_re_next & ~h2d_rf_lvl2_1_rf_lvl1_reg_l1_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_reg_l1_nack_ex; - d2h_rf_lvl2_1_rf_lvl1_1_reg_dflt_we_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_1_reg_dflt_we_next & ~h2d_rf_lvl2_1_rf_lvl1_1_reg_dflt_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_1_reg_dflt_nack_ex; - d2h_rf_lvl2_1_rf_lvl1_1_reg_dflt_re_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_1_reg_dflt_re_next & ~h2d_rf_lvl2_1_rf_lvl1_1_reg_dflt_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_1_reg_dflt_nack_ex; - d2h_rf_lvl2_1_rf_lvl1_2_reg_dflt_we_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_2_reg_dflt_we_next & ~h2d_rf_lvl2_1_rf_lvl1_2_reg_dflt_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_2_reg_dflt_nack_ex; - d2h_rf_lvl2_1_rf_lvl1_2_reg_dflt_re_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_2_reg_dflt_re_next & ~h2d_rf_lvl2_1_rf_lvl1_2_reg_dflt_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_2_reg_dflt_nack_ex; - d2h_rf_lvl2_1_rf_lvl1_3_reg_dflt_we_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_3_reg_dflt_we_next & ~h2d_rf_lvl2_1_rf_lvl1_3_reg_dflt_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_3_reg_dflt_nack_ex; - d2h_rf_lvl2_1_rf_lvl1_3_reg_dflt_re_ex <= #1 d2h_rf_lvl2_1_rf_lvl1_3_reg_dflt_re_next & ~h2d_rf_lvl2_1_rf_lvl1_3_reg_dflt_ack_ex & ~h2d_rf_lvl2_1_rf_lvl1_3_reg_dflt_nack_ex; - end - end - - //------- reg assigns for pio i/f (reset signal = reset) - always @ (posedge uclk) begin - if (reset) begin - pio_write_active <= #1 1'b0; - pio_read_active <= #1 1'b0; - end - else begin - pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; - pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; - end - end - //------- combinatorial assigns for l2_s8_child serial8 i/f always @ (*) begin s8_l2_s8_child_state_next = s8_l2_s8_child_state; @@ -1917,11 +1909,11 @@ module base_map_jrdl_decode s8_l2_s8_child_cmdData_dly1 <= #1 s8_l2_s8_child_cmdData_dly0; s8_l2_s8_child_resValid_dly1 <= #1 s8_l2_s8_child_resValid_dly0; s8_l2_s8_child_resData_dly1 <= #1 s8_l2_s8_child_resData_dly0; - s8_l2_s8_child_rdata_accum <= #1 s8_l2_s8_child_rdata_accum_next; h2d_l2_s8_child_nack_early <= #1 h2d_l2_s8_child_nack_early_next; s8_l2_s8_child_addr_cnt <= #1 s8_l2_s8_child_addr_cnt_next; s8_l2_s8_child_data_cnt <= #1 s8_l2_s8_child_data_cnt_next; end + s8_l2_s8_child_rdata_accum <= #1 s8_l2_s8_child_rdata_accum_next; end //------- combinatorial assigns for singleton_rf_s8 serial8 i/f @@ -2014,10 +2006,10 @@ module base_map_jrdl_decode s8_singleton_rf_s8_cmdData_dly1 <= #1 s8_singleton_rf_s8_cmdData_dly0; s8_singleton_rf_s8_resValid_dly1 <= #1 s8_singleton_rf_s8_resValid_dly0; s8_singleton_rf_s8_resData_dly1 <= #1 s8_singleton_rf_s8_resData_dly0; - s8_singleton_rf_s8_rdata_accum <= #1 s8_singleton_rf_s8_rdata_accum_next; h2d_singleton_rf_s8_nack_early <= #1 h2d_singleton_rf_s8_nack_early_next; s8_singleton_rf_s8_data_cnt <= #1 s8_singleton_rf_s8_data_cnt_next; end + s8_singleton_rf_s8_rdata_accum <= #1 s8_singleton_rf_s8_rdata_accum_next; end //------- combinatorial assigns for rf_lvl2_1_rf_lvl1_0_reg_dflt external field read data assigns @@ -2137,9 +2129,9 @@ module base_map_jrdl_decode r16_l2_r16_child_resData_dly1 <= #1 r16_l2_r16_child_resData_dly0; r16_l2_r16_child_resValid_dly2 <= #1 r16_l2_r16_child_resValid_dly1; r16_l2_r16_child_resData_dly2 <= #1 r16_l2_r16_child_resData_dly1; - r16_l2_r16_child_rdata_accum <= #1 r16_l2_r16_child_rdata_accum_next; r16_l2_r16_child_data_cnt <= #1 r16_l2_r16_child_data_cnt_next; end + r16_l2_r16_child_rdata_accum <= #1 r16_l2_r16_child_rdata_accum_next; end //------- combinatorial assigns for rf_lvl2_1_rf_lvl1_2_reg_dflt external field read data assigns @@ -4426,23 +4418,7 @@ module base_map_l2_r16_child_jrdl_decode end end - //------- reg assigns for external i/f (reset signal = reset) - always @ (posedge uclk) begin - if (reset) begin - d2h_l2_r16_child_ext_base_regs_we_ex <= #1 1'b0; - d2h_l2_r16_child_ext_base_regs_re_ex <= #1 1'b0; - d2h_l2_r16_child_l3_child_we_ex <= #1 1'b0; - d2h_l2_r16_child_l3_child_re_ex <= #1 1'b0; - end - else begin - d2h_l2_r16_child_ext_base_regs_we_ex <= #1 d2h_l2_r16_child_ext_base_regs_we_next & ~h2d_l2_r16_child_ext_base_regs_ack_ex & ~h2d_l2_r16_child_ext_base_regs_nack_ex; - d2h_l2_r16_child_ext_base_regs_re_ex <= #1 d2h_l2_r16_child_ext_base_regs_re_next & ~h2d_l2_r16_child_ext_base_regs_ack_ex & ~h2d_l2_r16_child_ext_base_regs_nack_ex; - d2h_l2_r16_child_l3_child_we_ex <= #1 d2h_l2_r16_child_l3_child_we_next & ~h2d_l2_r16_child_l3_child_ack_ex & ~h2d_l2_r16_child_l3_child_nack_ex; - d2h_l2_r16_child_l3_child_re_ex <= #1 d2h_l2_r16_child_l3_child_re_next & ~h2d_l2_r16_child_l3_child_ack_ex & ~h2d_l2_r16_child_l3_child_nack_ex; - end - end - - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always @ (posedge uclk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -4452,16 +4428,24 @@ module base_map_l2_r16_child_jrdl_decode pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; end - end - - //------- reg assigns for pio i/f - always @ (posedge uclk) begin pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; end //------- reg assigns for external i/f always @ (posedge uclk) begin + if (reset) begin + d2h_l2_r16_child_ext_base_regs_we_ex <= #1 1'b0; + d2h_l2_r16_child_ext_base_regs_re_ex <= #1 1'b0; + d2h_l2_r16_child_l3_child_we_ex <= #1 1'b0; + d2h_l2_r16_child_l3_child_re_ex <= #1 1'b0; + end + else begin + d2h_l2_r16_child_ext_base_regs_we_ex <= #1 d2h_l2_r16_child_ext_base_regs_we_next & ~h2d_l2_r16_child_ext_base_regs_ack_ex & ~h2d_l2_r16_child_ext_base_regs_nack_ex; + d2h_l2_r16_child_ext_base_regs_re_ex <= #1 d2h_l2_r16_child_ext_base_regs_re_next & ~h2d_l2_r16_child_ext_base_regs_ack_ex & ~h2d_l2_r16_child_ext_base_regs_nack_ex; + d2h_l2_r16_child_l3_child_we_ex <= #1 d2h_l2_r16_child_l3_child_we_next & ~h2d_l2_r16_child_l3_child_ack_ex & ~h2d_l2_r16_child_l3_child_nack_ex; + d2h_l2_r16_child_l3_child_re_ex <= #1 d2h_l2_r16_child_l3_child_re_next & ~h2d_l2_r16_child_l3_child_ack_ex & ~h2d_l2_r16_child_l3_child_nack_ex; + end d2h_l2_r16_child_ext_base_regs_w_ex <= #1 d2h_l2_r16_child_ext_base_regs_w_next; d2h_l2_r16_child_ext_base_regs_addr_ex <= #1 d2h_l2_r16_child_ext_base_regs_addr_next; d2h_l2_r16_child_l3_child_w_ex <= #1 d2h_l2_r16_child_l3_child_w_next; @@ -4786,11 +4770,11 @@ module base_map_l2_r16_child_jrdl_decode s8_l2_r16_child_l3_child_cmdData_dly1 <= #1 s8_l2_r16_child_l3_child_cmdData_dly0; s8_l2_r16_child_l3_child_resValid_dly1 <= #1 s8_l2_r16_child_l3_child_resValid_dly0; s8_l2_r16_child_l3_child_resData_dly1 <= #1 s8_l2_r16_child_l3_child_resData_dly0; - s8_l2_r16_child_l3_child_rdata_accum <= #1 s8_l2_r16_child_l3_child_rdata_accum_next; h2d_l2_r16_child_l3_child_nack_early <= #1 h2d_l2_r16_child_l3_child_nack_early_next; s8_l2_r16_child_l3_child_addr_cnt <= #1 s8_l2_r16_child_l3_child_addr_cnt_next; s8_l2_r16_child_l3_child_data_cnt <= #1 s8_l2_r16_child_l3_child_data_cnt_next; end + s8_l2_r16_child_l3_child_rdata_accum <= #1 s8_l2_r16_child_l3_child_rdata_accum_next; end //------- combinatorial assigns for pio ack/nack @@ -6279,18 +6263,6 @@ module base_map_l2_r16_child_l3_child_jrdl_decode end end - //------- reg assigns for external i/f (reset signal = reset) - always @ (posedge uclk) begin - if (reset) begin - d2h_l2_r16_child_l3_child_ext_base_regs_we_ex <= #1 1'b0; - d2h_l2_r16_child_l3_child_ext_base_regs_re_ex <= #1 1'b0; - end - else begin - d2h_l2_r16_child_l3_child_ext_base_regs_we_ex <= #1 d2h_l2_r16_child_l3_child_ext_base_regs_we_next & ~h2d_l2_r16_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_r16_child_l3_child_ext_base_regs_nack_ex; - d2h_l2_r16_child_l3_child_ext_base_regs_re_ex <= #1 d2h_l2_r16_child_l3_child_ext_base_regs_re_next & ~h2d_l2_r16_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_r16_child_l3_child_ext_base_regs_nack_ex; - end - end - //------- combinatorial assigns for serial8 i/f always @ (*) begin s8_state_next = s8_state; @@ -6389,16 +6361,16 @@ module base_map_l2_r16_child_l3_child_jrdl_decode end else begin s8_state <= #1 s8_state_next; - s8_addr_accum <= #1 s8_addr_accum_next; - s8_wdata_accum <= #1 s8_wdata_accum_next; - s8_wr_state_capture <= #1 s8_wr_state_capture_next; - s8_rdata_capture <= #1 s8_rdata_capture_next; s8_addr_cnt <= #1 s8_addr_cnt_next; s8_data_cnt <= #1 s8_data_cnt_next; end + s8_addr_accum <= #1 s8_addr_accum_next; + s8_wdata_accum <= #1 s8_wdata_accum_next; + s8_wr_state_capture <= #1 s8_wr_state_capture_next; + s8_rdata_capture <= #1 s8_rdata_capture_next; end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always @ (posedge uclk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -6408,16 +6380,20 @@ module base_map_l2_r16_child_l3_child_jrdl_decode pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; end - end - - //------- reg assigns for pio i/f - always @ (posedge uclk) begin pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; end //------- reg assigns for external i/f always @ (posedge uclk) begin + if (reset) begin + d2h_l2_r16_child_l3_child_ext_base_regs_we_ex <= #1 1'b0; + d2h_l2_r16_child_l3_child_ext_base_regs_re_ex <= #1 1'b0; + end + else begin + d2h_l2_r16_child_l3_child_ext_base_regs_we_ex <= #1 d2h_l2_r16_child_l3_child_ext_base_regs_we_next & ~h2d_l2_r16_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_r16_child_l3_child_ext_base_regs_nack_ex; + d2h_l2_r16_child_l3_child_ext_base_regs_re_ex <= #1 d2h_l2_r16_child_l3_child_ext_base_regs_re_next & ~h2d_l2_r16_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_r16_child_l3_child_ext_base_regs_nack_ex; + end d2h_l2_r16_child_l3_child_ext_base_regs_w_ex <= #1 d2h_l2_r16_child_l3_child_ext_base_regs_w_next; d2h_l2_r16_child_l3_child_ext_base_regs_addr_ex <= #1 d2h_l2_r16_child_l3_child_ext_base_regs_addr_next; end @@ -7958,22 +7934,6 @@ module base_map_l2_s8_child_jrdl_decode end end - //------- reg assigns for external i/f (reset signal = reset) - always @ (posedge uclk) begin - if (reset) begin - d2h_l2_s8_child_ext_base_regs_we_ex <= #1 1'b0; - d2h_l2_s8_child_ext_base_regs_re_ex <= #1 1'b0; - d2h_l2_s8_child_l3_child_we_ex <= #1 1'b0; - d2h_l2_s8_child_l3_child_re_ex <= #1 1'b0; - end - else begin - d2h_l2_s8_child_ext_base_regs_we_ex <= #1 d2h_l2_s8_child_ext_base_regs_we_next & ~h2d_l2_s8_child_ext_base_regs_ack_ex & ~h2d_l2_s8_child_ext_base_regs_nack_ex; - d2h_l2_s8_child_ext_base_regs_re_ex <= #1 d2h_l2_s8_child_ext_base_regs_re_next & ~h2d_l2_s8_child_ext_base_regs_ack_ex & ~h2d_l2_s8_child_ext_base_regs_nack_ex; - d2h_l2_s8_child_l3_child_we_ex <= #1 d2h_l2_s8_child_l3_child_we_next & ~h2d_l2_s8_child_l3_child_ack_ex & ~h2d_l2_s8_child_l3_child_nack_ex; - d2h_l2_s8_child_l3_child_re_ex <= #1 d2h_l2_s8_child_l3_child_re_next & ~h2d_l2_s8_child_l3_child_ack_ex & ~h2d_l2_s8_child_l3_child_nack_ex; - end - end - //------- combinatorial assigns for serial8 i/f always @ (*) begin s8_state_next = s8_state; @@ -8072,16 +8032,16 @@ module base_map_l2_s8_child_jrdl_decode end else begin s8_state <= #1 s8_state_next; - s8_addr_accum <= #1 s8_addr_accum_next; - s8_wdata_accum <= #1 s8_wdata_accum_next; - s8_wr_state_capture <= #1 s8_wr_state_capture_next; - s8_rdata_capture <= #1 s8_rdata_capture_next; s8_addr_cnt <= #1 s8_addr_cnt_next; s8_data_cnt <= #1 s8_data_cnt_next; end + s8_addr_accum <= #1 s8_addr_accum_next; + s8_wdata_accum <= #1 s8_wdata_accum_next; + s8_wr_state_capture <= #1 s8_wr_state_capture_next; + s8_rdata_capture <= #1 s8_rdata_capture_next; end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always @ (posedge uclk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -8091,16 +8051,24 @@ module base_map_l2_s8_child_jrdl_decode pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; end - end - - //------- reg assigns for pio i/f - always @ (posedge uclk) begin pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; end //------- reg assigns for external i/f always @ (posedge uclk) begin + if (reset) begin + d2h_l2_s8_child_ext_base_regs_we_ex <= #1 1'b0; + d2h_l2_s8_child_ext_base_regs_re_ex <= #1 1'b0; + d2h_l2_s8_child_l3_child_we_ex <= #1 1'b0; + d2h_l2_s8_child_l3_child_re_ex <= #1 1'b0; + end + else begin + d2h_l2_s8_child_ext_base_regs_we_ex <= #1 d2h_l2_s8_child_ext_base_regs_we_next & ~h2d_l2_s8_child_ext_base_regs_ack_ex & ~h2d_l2_s8_child_ext_base_regs_nack_ex; + d2h_l2_s8_child_ext_base_regs_re_ex <= #1 d2h_l2_s8_child_ext_base_regs_re_next & ~h2d_l2_s8_child_ext_base_regs_ack_ex & ~h2d_l2_s8_child_ext_base_regs_nack_ex; + d2h_l2_s8_child_l3_child_we_ex <= #1 d2h_l2_s8_child_l3_child_we_next & ~h2d_l2_s8_child_l3_child_ack_ex & ~h2d_l2_s8_child_l3_child_nack_ex; + d2h_l2_s8_child_l3_child_re_ex <= #1 d2h_l2_s8_child_l3_child_re_next & ~h2d_l2_s8_child_l3_child_ack_ex & ~h2d_l2_s8_child_l3_child_nack_ex; + end d2h_l2_s8_child_ext_base_regs_w_ex <= #1 d2h_l2_s8_child_ext_base_regs_w_next; d2h_l2_s8_child_ext_base_regs_addr_ex <= #1 d2h_l2_s8_child_ext_base_regs_addr_next; d2h_l2_s8_child_l3_child_w_ex <= #1 d2h_l2_s8_child_l3_child_w_next; @@ -8210,11 +8178,11 @@ module base_map_l2_s8_child_jrdl_decode s8_l2_s8_child_l3_child_cmdData_dly1 <= #1 s8_l2_s8_child_l3_child_cmdData_dly0; s8_l2_s8_child_l3_child_resValid_dly1 <= #1 s8_l2_s8_child_l3_child_resValid_dly0; s8_l2_s8_child_l3_child_resData_dly1 <= #1 s8_l2_s8_child_l3_child_resData_dly0; - s8_l2_s8_child_l3_child_rdata_accum <= #1 s8_l2_s8_child_l3_child_rdata_accum_next; h2d_l2_s8_child_l3_child_nack_early <= #1 h2d_l2_s8_child_l3_child_nack_early_next; s8_l2_s8_child_l3_child_addr_cnt <= #1 s8_l2_s8_child_l3_child_addr_cnt_next; s8_l2_s8_child_l3_child_data_cnt <= #1 s8_l2_s8_child_l3_child_data_cnt_next; end + s8_l2_s8_child_l3_child_rdata_accum <= #1 s8_l2_s8_child_l3_child_rdata_accum_next; end //------- reg assigns for clock gate delay @@ -9735,18 +9703,6 @@ module base_map_l2_s8_child_l3_child_jrdl_decode end end - //------- reg assigns for external i/f (reset signal = reset) - always @ (posedge uclk) begin - if (reset) begin - d2h_l2_s8_child_l3_child_ext_base_regs_we_ex <= #1 1'b0; - d2h_l2_s8_child_l3_child_ext_base_regs_re_ex <= #1 1'b0; - end - else begin - d2h_l2_s8_child_l3_child_ext_base_regs_we_ex <= #1 d2h_l2_s8_child_l3_child_ext_base_regs_we_next & ~h2d_l2_s8_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_s8_child_l3_child_ext_base_regs_nack_ex; - d2h_l2_s8_child_l3_child_ext_base_regs_re_ex <= #1 d2h_l2_s8_child_l3_child_ext_base_regs_re_next & ~h2d_l2_s8_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_s8_child_l3_child_ext_base_regs_nack_ex; - end - end - //------- combinatorial assigns for serial8 i/f always @ (*) begin s8_state_next = s8_state; @@ -9845,16 +9801,16 @@ module base_map_l2_s8_child_l3_child_jrdl_decode end else begin s8_state <= #1 s8_state_next; - s8_addr_accum <= #1 s8_addr_accum_next; - s8_wdata_accum <= #1 s8_wdata_accum_next; - s8_wr_state_capture <= #1 s8_wr_state_capture_next; - s8_rdata_capture <= #1 s8_rdata_capture_next; s8_addr_cnt <= #1 s8_addr_cnt_next; s8_data_cnt <= #1 s8_data_cnt_next; end + s8_addr_accum <= #1 s8_addr_accum_next; + s8_wdata_accum <= #1 s8_wdata_accum_next; + s8_wr_state_capture <= #1 s8_wr_state_capture_next; + s8_rdata_capture <= #1 s8_rdata_capture_next; end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always @ (posedge uclk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -9864,16 +9820,20 @@ module base_map_l2_s8_child_l3_child_jrdl_decode pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; end - end - - //------- reg assigns for pio i/f - always @ (posedge uclk) begin pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; end //------- reg assigns for external i/f always @ (posedge uclk) begin + if (reset) begin + d2h_l2_s8_child_l3_child_ext_base_regs_we_ex <= #1 1'b0; + d2h_l2_s8_child_l3_child_ext_base_regs_re_ex <= #1 1'b0; + end + else begin + d2h_l2_s8_child_l3_child_ext_base_regs_we_ex <= #1 d2h_l2_s8_child_l3_child_ext_base_regs_we_next & ~h2d_l2_s8_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_s8_child_l3_child_ext_base_regs_nack_ex; + d2h_l2_s8_child_l3_child_ext_base_regs_re_ex <= #1 d2h_l2_s8_child_l3_child_ext_base_regs_re_next & ~h2d_l2_s8_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_s8_child_l3_child_ext_base_regs_nack_ex; + end d2h_l2_s8_child_l3_child_ext_base_regs_w_ex <= #1 d2h_l2_s8_child_l3_child_ext_base_regs_w_next; d2h_l2_s8_child_l3_child_ext_base_regs_addr_ex <= #1 d2h_l2_s8_child_l3_child_ext_base_regs_addr_next; end @@ -11405,23 +11365,7 @@ module base_map_l2_dflt_child_jrdl_decode end end - //------- reg assigns for external i/f (reset signal = reset) - always @ (posedge uclk) begin - if (reset) begin - d2h_l2_dflt_child_ext_base_regs_we_ex <= #1 1'b0; - d2h_l2_dflt_child_ext_base_regs_re_ex <= #1 1'b0; - d2h_l2_dflt_child_l3_child_we_ex <= #1 1'b0; - d2h_l2_dflt_child_l3_child_re_ex <= #1 1'b0; - end - else begin - d2h_l2_dflt_child_ext_base_regs_we_ex <= #1 d2h_l2_dflt_child_ext_base_regs_we_next & ~h2d_l2_dflt_child_ext_base_regs_ack_ex & ~h2d_l2_dflt_child_ext_base_regs_nack_ex; - d2h_l2_dflt_child_ext_base_regs_re_ex <= #1 d2h_l2_dflt_child_ext_base_regs_re_next & ~h2d_l2_dflt_child_ext_base_regs_ack_ex & ~h2d_l2_dflt_child_ext_base_regs_nack_ex; - d2h_l2_dflt_child_l3_child_we_ex <= #1 d2h_l2_dflt_child_l3_child_we_next & ~h2d_l2_dflt_child_l3_child_ack_ex & ~h2d_l2_dflt_child_l3_child_nack_ex; - d2h_l2_dflt_child_l3_child_re_ex <= #1 d2h_l2_dflt_child_l3_child_re_next & ~h2d_l2_dflt_child_l3_child_ack_ex & ~h2d_l2_dflt_child_l3_child_nack_ex; - end - end - - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always @ (posedge uclk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -11431,16 +11375,24 @@ module base_map_l2_dflt_child_jrdl_decode pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; end - end - - //------- reg assigns for pio i/f - always @ (posedge uclk) begin pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; end //------- reg assigns for external i/f always @ (posedge uclk) begin + if (reset) begin + d2h_l2_dflt_child_ext_base_regs_we_ex <= #1 1'b0; + d2h_l2_dflt_child_ext_base_regs_re_ex <= #1 1'b0; + d2h_l2_dflt_child_l3_child_we_ex <= #1 1'b0; + d2h_l2_dflt_child_l3_child_re_ex <= #1 1'b0; + end + else begin + d2h_l2_dflt_child_ext_base_regs_we_ex <= #1 d2h_l2_dflt_child_ext_base_regs_we_next & ~h2d_l2_dflt_child_ext_base_regs_ack_ex & ~h2d_l2_dflt_child_ext_base_regs_nack_ex; + d2h_l2_dflt_child_ext_base_regs_re_ex <= #1 d2h_l2_dflt_child_ext_base_regs_re_next & ~h2d_l2_dflt_child_ext_base_regs_ack_ex & ~h2d_l2_dflt_child_ext_base_regs_nack_ex; + d2h_l2_dflt_child_l3_child_we_ex <= #1 d2h_l2_dflt_child_l3_child_we_next & ~h2d_l2_dflt_child_l3_child_ack_ex & ~h2d_l2_dflt_child_l3_child_nack_ex; + d2h_l2_dflt_child_l3_child_re_ex <= #1 d2h_l2_dflt_child_l3_child_re_next & ~h2d_l2_dflt_child_l3_child_ack_ex & ~h2d_l2_dflt_child_l3_child_nack_ex; + end d2h_l2_dflt_child_ext_base_regs_w_ex <= #1 d2h_l2_dflt_child_ext_base_regs_w_next; d2h_l2_dflt_child_ext_base_regs_addr_ex <= #1 d2h_l2_dflt_child_ext_base_regs_addr_next; d2h_l2_dflt_child_l3_child_w_ex <= #1 d2h_l2_dflt_child_l3_child_w_next; @@ -11550,11 +11502,11 @@ module base_map_l2_dflt_child_jrdl_decode s8_l2_dflt_child_l3_child_cmdData_dly1 <= #1 s8_l2_dflt_child_l3_child_cmdData_dly0; s8_l2_dflt_child_l3_child_resValid_dly1 <= #1 s8_l2_dflt_child_l3_child_resValid_dly0; s8_l2_dflt_child_l3_child_resData_dly1 <= #1 s8_l2_dflt_child_l3_child_resData_dly0; - s8_l2_dflt_child_l3_child_rdata_accum <= #1 s8_l2_dflt_child_l3_child_rdata_accum_next; h2d_l2_dflt_child_l3_child_nack_early <= #1 h2d_l2_dflt_child_l3_child_nack_early_next; s8_l2_dflt_child_l3_child_addr_cnt <= #1 s8_l2_dflt_child_l3_child_addr_cnt_next; s8_l2_dflt_child_l3_child_data_cnt <= #1 s8_l2_dflt_child_l3_child_data_cnt_next; end + s8_l2_dflt_child_l3_child_rdata_accum <= #1 s8_l2_dflt_child_l3_child_rdata_accum_next; end //------- reg assigns for clock gate delay @@ -13084,18 +13036,6 @@ module base_map_l2_dflt_child_l3_child_jrdl_decode end end - //------- reg assigns for external i/f (reset signal = reset) - always @ (posedge uclk) begin - if (reset) begin - d2h_l2_dflt_child_l3_child_ext_base_regs_we_ex <= #1 1'b0; - d2h_l2_dflt_child_l3_child_ext_base_regs_re_ex <= #1 1'b0; - end - else begin - d2h_l2_dflt_child_l3_child_ext_base_regs_we_ex <= #1 d2h_l2_dflt_child_l3_child_ext_base_regs_we_next & ~h2d_l2_dflt_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_dflt_child_l3_child_ext_base_regs_nack_ex; - d2h_l2_dflt_child_l3_child_ext_base_regs_re_ex <= #1 d2h_l2_dflt_child_l3_child_ext_base_regs_re_next & ~h2d_l2_dflt_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_dflt_child_l3_child_ext_base_regs_nack_ex; - end - end - //------- combinatorial assigns for serial8 i/f always @ (*) begin s8_state_next = s8_state; @@ -13194,16 +13134,16 @@ module base_map_l2_dflt_child_l3_child_jrdl_decode end else begin s8_state <= #1 s8_state_next; - s8_addr_accum <= #1 s8_addr_accum_next; - s8_wdata_accum <= #1 s8_wdata_accum_next; - s8_wr_state_capture <= #1 s8_wr_state_capture_next; - s8_rdata_capture <= #1 s8_rdata_capture_next; s8_addr_cnt <= #1 s8_addr_cnt_next; s8_data_cnt <= #1 s8_data_cnt_next; end + s8_addr_accum <= #1 s8_addr_accum_next; + s8_wdata_accum <= #1 s8_wdata_accum_next; + s8_wr_state_capture <= #1 s8_wr_state_capture_next; + s8_rdata_capture <= #1 s8_rdata_capture_next; end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always @ (posedge uclk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -13213,16 +13153,20 @@ module base_map_l2_dflt_child_l3_child_jrdl_decode pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; end - end - - //------- reg assigns for pio i/f - always @ (posedge uclk) begin pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; end //------- reg assigns for external i/f always @ (posedge uclk) begin + if (reset) begin + d2h_l2_dflt_child_l3_child_ext_base_regs_we_ex <= #1 1'b0; + d2h_l2_dflt_child_l3_child_ext_base_regs_re_ex <= #1 1'b0; + end + else begin + d2h_l2_dflt_child_l3_child_ext_base_regs_we_ex <= #1 d2h_l2_dflt_child_l3_child_ext_base_regs_we_next & ~h2d_l2_dflt_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_dflt_child_l3_child_ext_base_regs_nack_ex; + d2h_l2_dflt_child_l3_child_ext_base_regs_re_ex <= #1 d2h_l2_dflt_child_l3_child_ext_base_regs_re_next & ~h2d_l2_dflt_child_l3_child_ext_base_regs_ack_ex & ~h2d_l2_dflt_child_l3_child_ext_base_regs_nack_ex; + end d2h_l2_dflt_child_l3_child_ext_base_regs_w_ex <= #1 d2h_l2_dflt_child_l3_child_ext_base_regs_w_next; d2h_l2_dflt_child_l3_child_ext_base_regs_addr_ex <= #1 d2h_l2_dflt_child_l3_child_ext_base_regs_addr_next; end @@ -14083,14 +14027,14 @@ module base_map_singleton_rf_s8_jrdl_decode end else begin s8_state <= #1 s8_state_next; - s8_wdata_accum <= #1 s8_wdata_accum_next; - s8_wr_state_capture <= #1 s8_wr_state_capture_next; - s8_rdata_capture <= #1 s8_rdata_capture_next; s8_data_cnt <= #1 s8_data_cnt_next; end + s8_wdata_accum <= #1 s8_wdata_accum_next; + s8_wr_state_capture <= #1 s8_wr_state_capture_next; + s8_rdata_capture <= #1 s8_rdata_capture_next; end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always @ (posedge uclk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -14100,10 +14044,6 @@ module base_map_singleton_rf_s8_jrdl_decode pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; end - end - - //------- reg assigns for pio i/f - always @ (posedge uclk) begin pio_dec_write_data_d1 <= #1 pio_dec_write_data; end @@ -14459,7 +14399,7 @@ module base_map_singleton_rf_r16_jrdl_decode end end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always @ (posedge uclk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -14469,10 +14409,6 @@ module base_map_singleton_rf_r16_jrdl_decode pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; end - end - - //------- reg assigns for pio i/f - always @ (posedge uclk) begin pio_dec_write_data_d1 <= #1 pio_dec_write_data; end @@ -14974,7 +14910,7 @@ module base_map_singleton_rf_dflt_jrdl_decode end end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always @ (posedge uclk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -14984,10 +14920,6 @@ module base_map_singleton_rf_dflt_jrdl_decode pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; end - end - - //------- reg assigns for pio i/f - always @ (posedge uclk) begin pio_dec_write_data_d1 <= #1 pio_dec_write_data; end diff --git a/test/basic_tests/rdl_intr_01/golden/output.sv b/test/basic_tests/rdl_intr_01/golden/output.sv index 8ec8c48..63b0915 100644 --- a/test/basic_tests/rdl_intr_01/golden/output.sv +++ b/test/basic_tests/rdl_intr_01/golden/output.sv @@ -1,7 +1,7 @@ -// Ordt 190606.01 autogenerated file +// Ordt 190615.01 autogenerated file // Input: ./rdl_intr_01/test.rdl // Parms: ./rdl_intr_01/test.parms -// Date: Thu Jun 06 13:30:58 EDT 2019 +// Date: Sat Jun 15 21:05:43 EDT 2019 // // @@ -310,8 +310,8 @@ module foo_jrdl_logic end else begin rg_bar_a_reg_0_fld1 <= #1 reg_bar_a_reg_0_fld1_next; - rg_bar_a_reg_0_fld2 <= #1 reg_bar_a_reg_0_fld2_next; end + rg_bar_a_reg_0_fld2 <= #1 reg_bar_a_reg_0_fld2_next; end //------- combinatorial assigns for bar_intr_reg1 @@ -380,8 +380,8 @@ module foo_jrdl_logic end else begin rg_bar_a_reg_1_fld1 <= #1 reg_bar_a_reg_1_fld1_next; - rg_bar_a_reg_1_fld2 <= #1 reg_bar_a_reg_1_fld2_next; end + rg_bar_a_reg_1_fld2 <= #1 reg_bar_a_reg_1_fld2_next; end //------- combinatorial assigns for bar_sub_intr_reg3 (pio read data) @@ -826,7 +826,7 @@ module foo_jrdl_decode end end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always_ff @ (posedge clk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -836,10 +836,6 @@ module foo_jrdl_decode pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; end - end - - //------- reg assigns for pio i/f - always_ff @ (posedge clk) begin pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; end diff --git a/test/basic_tests/rdl_intr_01/golden/output.v b/test/basic_tests/rdl_intr_01/golden/output.v index 40cfa83..69334a5 100644 --- a/test/basic_tests/rdl_intr_01/golden/output.v +++ b/test/basic_tests/rdl_intr_01/golden/output.v @@ -1,7 +1,7 @@ -// Ordt 190606.01 autogenerated file +// Ordt 190615.01 autogenerated file // Input: ./rdl_intr_01/test.rdl // Parms: ./rdl_intr_01/test.parms -// Date: Thu Jun 06 13:30:58 EDT 2019 +// Date: Sat Jun 15 21:05:43 EDT 2019 // // @@ -310,8 +310,8 @@ module foo_jrdl_logic end else begin rg_bar_a_reg_0_fld1 <= #1 reg_bar_a_reg_0_fld1_next; - rg_bar_a_reg_0_fld2 <= #1 reg_bar_a_reg_0_fld2_next; end + rg_bar_a_reg_0_fld2 <= #1 reg_bar_a_reg_0_fld2_next; end //------- combinatorial assigns for bar_intr_reg1 @@ -380,8 +380,8 @@ module foo_jrdl_logic end else begin rg_bar_a_reg_1_fld1 <= #1 reg_bar_a_reg_1_fld1_next; - rg_bar_a_reg_1_fld2 <= #1 reg_bar_a_reg_1_fld2_next; end + rg_bar_a_reg_1_fld2 <= #1 reg_bar_a_reg_1_fld2_next; end //------- combinatorial assigns for bar_sub_intr_reg3 (pio read data) @@ -826,7 +826,7 @@ module foo_jrdl_decode end end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always @ (posedge clk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -836,10 +836,6 @@ module foo_jrdl_decode pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; end - end - - //------- reg assigns for pio i/f - always @ (posedge clk) begin pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; end diff --git a/test/basic_tests/rdl_iwrap/golden/output.sv b/test/basic_tests/rdl_iwrap/golden/output.sv index b82a7db..72e8c11 100644 --- a/test/basic_tests/rdl_iwrap/golden/output.sv +++ b/test/basic_tests/rdl_iwrap/golden/output.sv @@ -1,7 +1,7 @@ -// Ordt 190606.01 autogenerated file +// Ordt 190615.01 autogenerated file // Input: ./rdl_iwrap/test.rdl // Parms: ./rdl_iwrap/test.parms -// Date: Thu Jun 06 13:30:59 EDT 2019 +// Date: Sat Jun 15 21:05:44 EDT 2019 // // @@ -613,7 +613,7 @@ module top_jrdl_decode end end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always_ff @ (posedge clk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -623,10 +623,6 @@ module top_jrdl_decode pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; end - end - - //------- reg assigns for pio i/f - always_ff @ (posedge clk) begin pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; end diff --git a/test/basic_tests/rdl_iwrap/golden/output.v b/test/basic_tests/rdl_iwrap/golden/output.v index 9a3d562..bd747d7 100644 --- a/test/basic_tests/rdl_iwrap/golden/output.v +++ b/test/basic_tests/rdl_iwrap/golden/output.v @@ -1,7 +1,7 @@ -// Ordt 190606.01 autogenerated file +// Ordt 190615.01 autogenerated file // Input: ./rdl_iwrap/test.rdl // Parms: ./rdl_iwrap/test.parms -// Date: Thu Jun 06 13:30:59 EDT 2019 +// Date: Sat Jun 15 21:05:44 EDT 2019 // // @@ -613,7 +613,7 @@ module top_jrdl_decode end end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always @ (posedge clk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -623,10 +623,6 @@ module top_jrdl_decode pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; end - end - - //------- reg assigns for pio i/f - always @ (posedge clk) begin pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; end diff --git a/test/basic_tests/rdl_sec_if/golden/output.sv b/test/basic_tests/rdl_sec_if/golden/output.sv index 1a07ce5..494cc33 100644 --- a/test/basic_tests/rdl_sec_if/golden/output.sv +++ b/test/basic_tests/rdl_sec_if/golden/output.sv @@ -1,7 +1,7 @@ -// Ordt 190606.01 autogenerated file +// Ordt 190615.01 autogenerated file // Input: ./rdl_sec_if/test.rdl // Parms: ./rdl_sec_if/test.parms -// Date: Thu Jun 06 13:31:00 EDT 2019 +// Date: Sat Jun 15 21:05:44 EDT 2019 // // @@ -725,6 +725,193 @@ module base_map_jrdl_decode end end + //------- combinatorial assigns for secondary engine1 i/f sm + always_comb begin + p2_e1_state_next = p2_e1_status_state_w; + p2_pio_dec_read_next = 1'b0; + p2_pio_dec_write_next = 1'b0; + p2_arb_atomic_request_next = 1'b0; + p2_pio_dec_write_data_next = p2_pio_dec_write_data; + p2_e1_last_read_data_val_w_next = p2_e1_last_read_data_val_w; + p2_e1_status_nack_error_intr = 1'b0; + p2_e1_status_bad_address_error_intr = 1'b0; + p2_e1_trans_count_next = p2_e1_trans_count; + p2_pio_dec_address_next = {1'b0, p2_pio_dec_address}; + p2_e1_delay_count_next = 10'b0; + case (p2_e1_status_state_w) + 3'h0: begin // IDLE + p2_e1_trans_count_next = 41'b0; + p2_pio_dec_address_next = {1'b0, p2_e1_address_start_val_r}; + if (p2_e1_cntl_start_r && !p2_e1_cntl_force_stop_r) begin + if (p2_e1_cfg_read_capture_mode_r == 2'h1) + p2_e1_last_read_data_val_w_next = ~32'b0; + else + p2_e1_last_read_data_val_w_next = 32'b0; + if ((p2_e1_cfg_mode_r == 2'h1) || (p2_e1_cfg_mode_r == 2'h2)) begin + p2_e1_state_next = 3'h1; + end + else begin + p2_e1_state_next = 3'h2; + p2_pio_dec_write_data_next = p2_e1_write_data_val_r; + end + end + end + 3'h1: begin // READ_WAIT + p2_e1_delay_count_next = p2_e1_delay_count + 10'b1; + if (p2_e1_cntl_force_stop_r) begin + p2_e1_state_next = 3'h0; + end + else if (p2_e1_delay_count == p2_e1_cfg_trans_delay_r) begin + p2_e1_state_next = 3'h3; + p2_pio_dec_read_next = 1'b1; + p2_arb_atomic_request_next = (p2_e1_cfg_mode_r == 2'h2); + end + else if (|p2_e1_trans_count) begin + if ((p2_e1_cfg_stop_on_read_r == 2'h2) && ((p2_e1_last_read_data_val_w & ~p2_e1_read_mask_val_r) == p2_e1_read_match_data_val_r)) + p2_e1_state_next = 3'h0; + if ((p2_e1_cfg_stop_on_read_r == 2'h1) && ((p2_e1_last_read_data_val_w & ~p2_e1_read_mask_val_r) < p2_e1_read_match_data_val_r)) + p2_e1_state_next = 3'h0; + if ((p2_e1_cfg_stop_on_read_r == 2'h3) && ((p2_e1_last_read_data_val_w & ~p2_e1_read_mask_val_r) > p2_e1_read_match_data_val_r)) + p2_e1_state_next = 3'h0; + end + end + 3'h2: begin // WRITE_WAIT + p2_e1_delay_count_next = p2_e1_delay_count + 10'b1; + if (p2_e1_cntl_force_stop_r) begin + p2_e1_state_next = 3'h0; + end + else if (p2_e1_delay_count == p2_e1_cfg_trans_delay_r) begin + p2_e1_state_next = 3'h4; + p2_pio_dec_write_next = 1'b1; + end + else if (|p2_e1_trans_count) begin + if ((p2_e1_cfg_stop_on_read_r == 2'h2) && ((p2_e1_last_read_data_val_w & ~p2_e1_read_mask_val_r) == p2_e1_read_match_data_val_r)) + p2_e1_state_next = 3'h0; + if ((p2_e1_cfg_stop_on_read_r == 2'h1) && ((p2_e1_last_read_data_val_w & ~p2_e1_read_mask_val_r) < p2_e1_read_match_data_val_r)) + p2_e1_state_next = 3'h0; + if ((p2_e1_cfg_stop_on_read_r == 2'h3) && ((p2_e1_last_read_data_val_w & ~p2_e1_read_mask_val_r) > p2_e1_read_match_data_val_r)) + p2_e1_state_next = 3'h0; + end + end + 3'h3: begin // READ + if (p2_dec_pio_ack) begin + if (p2_e1_cfg_mode_r == 2'h1) begin + p2_e1_trans_count_next = p2_e1_trans_count + 41'b1; + p2_pio_dec_address_next = p2_pio_dec_address + p2_e1_address_step_val_r; + end + if (p2_e1_cfg_read_capture_mode_r == 2'h3) + p2_e1_last_read_data_val_w_next = p2_dec_pio_read_data; + if ((p2_e1_cfg_read_capture_mode_r == 2'h1) && (p2_dec_pio_read_data < p2_e1_last_read_data_val_w)) + p2_e1_last_read_data_val_w_next = p2_dec_pio_read_data; + if ((p2_e1_cfg_read_capture_mode_r == 2'h2) && (p2_dec_pio_read_data > p2_e1_last_read_data_val_w)) + p2_e1_last_read_data_val_w_next = p2_dec_pio_read_data; + if (p2_e1_cntl_force_stop_r) begin + p2_e1_state_next = 3'h0; + end + else if (p2_e1_cfg_mode_r == 2'h2) begin + p2_e1_state_next = 3'h4; + p2_pio_dec_write_next = 1'b1; + p2_pio_dec_write_data_next = ((p2_e1_write_data_val_r & ~p2_e1_write_mask_val_r) | (p2_dec_pio_read_data & p2_e1_write_mask_val_r)); + end + else if (p2_e1_cfg_mode_r == 2'h1) begin + if (p2_e1_cfg_stop_on_count_r && (p2_e1_trans_count_next == {1'b0,p2_e1_max_trans_count_val_r})) + p2_e1_state_next = 3'h0; + else if (p2_pio_dec_address_next [6] == 1'b1) begin + p2_e1_state_next = 3'h0; + p2_e1_status_bad_address_error_intr = 1'b1; + end + else begin + p2_e1_state_next = 3'h1; + end + end + else p2_e1_state_next = 3'h0; + end + else if (p2_dec_pio_nack) begin + p2_e1_state_next = 3'h0; + p2_e1_status_nack_error_intr = 1'b1; + end + else begin + p2_pio_dec_read_next = 1'b1; + p2_arb_atomic_request_next = (p2_e1_cfg_mode_r == 2'h2); + end + end + 3'h4: begin // WRITE + if (p2_dec_pio_ack) begin + if (p2_e1_cfg_mode_r != 2'h1) begin + p2_e1_trans_count_next = p2_e1_trans_count + 41'b1; + p2_pio_dec_address_next = p2_pio_dec_address + p2_e1_address_step_val_r; + end + if ((p2_e1_cfg_stop_on_count_r && (p2_e1_trans_count_next == {1'b0,p2_e1_max_trans_count_val_r})) || p2_e1_cntl_force_stop_r) begin + p2_e1_state_next = 3'h0; + end + else if (p2_pio_dec_address_next [6] == 1'b1) begin + p2_e1_state_next = 3'h0; + p2_e1_status_bad_address_error_intr = 1'b1; + end + else if (p2_e1_cfg_mode_r == 2'h2) begin + p2_e1_state_next = 3'h1; + end + else begin + p2_e1_state_next = 3'h2; + end + end + else if (p2_dec_pio_nack) begin + p2_e1_state_next = 3'h0; + p2_e1_status_nack_error_intr = 1'b1; + end + else begin + p2_pio_dec_write_next = 1'b1; + end + end + default: + p2_e1_state_next = 3'h0; + endcase + end + + //------- reg assigns for secondary engine1 i/f sm + always_ff @ (posedge clk) begin + if (reset) begin + p2_e1_status_state_w <= #1 3'b0; + p2_e1_trans_count <= #1 161'b0; + p2_e1_delay_count <= #1 10'b0; + end + else begin + p2_e1_status_state_w <= #1 p2_e1_state_next; + p2_e1_trans_count <= #1 p2_e1_trans_count_next; + p2_e1_delay_count <= #1 p2_e1_delay_count_next; + end + end + + //------- reg assigns for secondary engine1 i/f signals + always_ff @ (posedge clk) begin + if (reset) begin + p2_pio_dec_write_data <= #1 32'b0; + p2_pio_dec_address <= #1 4'b0; + p2_pio_dec_read <= #1 1'b0; + p2_pio_dec_write <= #1 1'b0; + p2_arb_atomic_request <= #1 1'b0; + p2_e1_last_read_data_val_w <= #1 32'b0; + end + else begin + p2_pio_dec_write_data <= #1 p2_pio_dec_write_data_next; + p2_pio_dec_address <= #1 p2_pio_dec_address_next [5:2] ; + p2_pio_dec_read <= #1 p2_pio_dec_read_next; + p2_pio_dec_write <= #1 p2_pio_dec_write_next; + p2_arb_atomic_request <= #1 p2_arb_atomic_request_next; + p2_e1_last_read_data_val_w <= #1 p2_e1_last_read_data_val_w_next; + end + end + + //------- combinatorial assigns for interface arbiter input select + always_comb begin + pio_dec_address = p1_pio_dec_address; + pio_dec_write_data = p1_pio_dec_write_data; + if (arbiter_state == 3'h2) begin + pio_dec_address = p2_pio_dec_address; + pio_dec_write_data = p2_pio_dec_write_data; + end + end + //------- combinatorial assigns for primary ring16 i/f always_comb begin r16_primary_state_next = r16_primary_state; @@ -807,9 +994,9 @@ module base_map_jrdl_decode r16_primary_cmdData_dly1 <= #1 r16_primary_cmdData_dly0; r16_primary_resValid_dly1 <= #1 r16_primary_resValid_dly0; r16_primary_resData_dly1 <= #1 r16_primary_resData_dly0; - r16_primary_rdata_accum <= #1 r16_primary_rdata_accum_next; r16_primary_data_cnt <= #1 r16_primary_data_cnt_next; end + r16_primary_rdata_accum <= #1 r16_primary_rdata_accum_next; end //------- combinatorial assigns for interface arbiter sm @@ -909,12 +1096,28 @@ module base_map_jrdl_decode //------- reg assigns for pio i/f always_ff @ (posedge clk) begin + if (reset) begin + pio_write_active <= #1 1'b0; + pio_read_active <= #1 1'b0; + end + else begin + pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; + pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; + end pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; end //------- reg assigns for external i/f always_ff @ (posedge clk) begin + if (reset) begin + d2h_primary_we_ex <= #1 1'b0; + d2h_primary_re_ex <= #1 1'b0; + end + else begin + d2h_primary_we_ex <= #1 d2h_primary_we_next & ~h2d_primary_ack_ex & ~h2d_primary_nack_ex; + d2h_primary_re_ex <= #1 d2h_primary_re_next & ~h2d_primary_ack_ex & ~h2d_primary_nack_ex; + end d2h_primary_w_ex <= #1 d2h_primary_w_next; d2h_primary_addr_ex <= #1 d2h_primary_addr_next; end @@ -981,217 +1184,6 @@ module base_map_jrdl_decode end end - //------- combinatorial assigns for secondary engine1 i/f sm - always_comb begin - p2_e1_state_next = p2_e1_status_state_w; - p2_pio_dec_read_next = 1'b0; - p2_pio_dec_write_next = 1'b0; - p2_arb_atomic_request_next = 1'b0; - p2_pio_dec_write_data_next = p2_pio_dec_write_data; - p2_e1_last_read_data_val_w_next = p2_e1_last_read_data_val_w; - p2_e1_status_nack_error_intr = 1'b0; - p2_e1_status_bad_address_error_intr = 1'b0; - p2_e1_trans_count_next = p2_e1_trans_count; - p2_pio_dec_address_next = {1'b0, p2_pio_dec_address}; - p2_e1_delay_count_next = 10'b0; - case (p2_e1_status_state_w) - 3'h0: begin // IDLE - p2_e1_trans_count_next = 41'b0; - p2_pio_dec_address_next = {1'b0, p2_e1_address_start_val_r}; - if (p2_e1_cntl_start_r && !p2_e1_cntl_force_stop_r) begin - if (p2_e1_cfg_read_capture_mode_r == 2'h1) - p2_e1_last_read_data_val_w_next = ~32'b0; - else - p2_e1_last_read_data_val_w_next = 32'b0; - if ((p2_e1_cfg_mode_r == 2'h1) || (p2_e1_cfg_mode_r == 2'h2)) begin - p2_e1_state_next = 3'h1; - end - else begin - p2_e1_state_next = 3'h2; - p2_pio_dec_write_data_next = p2_e1_write_data_val_r; - end - end - end - 3'h1: begin // READ_WAIT - p2_e1_delay_count_next = p2_e1_delay_count + 10'b1; - if (p2_e1_cntl_force_stop_r) begin - p2_e1_state_next = 3'h0; - end - else if (p2_e1_delay_count == p2_e1_cfg_trans_delay_r) begin - p2_e1_state_next = 3'h3; - p2_pio_dec_read_next = 1'b1; - p2_arb_atomic_request_next = (p2_e1_cfg_mode_r == 2'h2); - end - else if (|p2_e1_trans_count) begin - if ((p2_e1_cfg_stop_on_read_r == 2'h2) && ((p2_e1_last_read_data_val_w & ~p2_e1_read_mask_val_r) == p2_e1_read_match_data_val_r)) - p2_e1_state_next = 3'h0; - if ((p2_e1_cfg_stop_on_read_r == 2'h1) && ((p2_e1_last_read_data_val_w & ~p2_e1_read_mask_val_r) < p2_e1_read_match_data_val_r)) - p2_e1_state_next = 3'h0; - if ((p2_e1_cfg_stop_on_read_r == 2'h3) && ((p2_e1_last_read_data_val_w & ~p2_e1_read_mask_val_r) > p2_e1_read_match_data_val_r)) - p2_e1_state_next = 3'h0; - end - end - 3'h2: begin // WRITE_WAIT - p2_e1_delay_count_next = p2_e1_delay_count + 10'b1; - if (p2_e1_cntl_force_stop_r) begin - p2_e1_state_next = 3'h0; - end - else if (p2_e1_delay_count == p2_e1_cfg_trans_delay_r) begin - p2_e1_state_next = 3'h4; - p2_pio_dec_write_next = 1'b1; - end - else if (|p2_e1_trans_count) begin - if ((p2_e1_cfg_stop_on_read_r == 2'h2) && ((p2_e1_last_read_data_val_w & ~p2_e1_read_mask_val_r) == p2_e1_read_match_data_val_r)) - p2_e1_state_next = 3'h0; - if ((p2_e1_cfg_stop_on_read_r == 2'h1) && ((p2_e1_last_read_data_val_w & ~p2_e1_read_mask_val_r) < p2_e1_read_match_data_val_r)) - p2_e1_state_next = 3'h0; - if ((p2_e1_cfg_stop_on_read_r == 2'h3) && ((p2_e1_last_read_data_val_w & ~p2_e1_read_mask_val_r) > p2_e1_read_match_data_val_r)) - p2_e1_state_next = 3'h0; - end - end - 3'h3: begin // READ - if (p2_dec_pio_ack) begin - if (p2_e1_cfg_mode_r == 2'h1) begin - p2_e1_trans_count_next = p2_e1_trans_count + 41'b1; - p2_pio_dec_address_next = p2_pio_dec_address + p2_e1_address_step_val_r; - end - if (p2_e1_cfg_read_capture_mode_r == 2'h3) - p2_e1_last_read_data_val_w_next = p2_dec_pio_read_data; - if ((p2_e1_cfg_read_capture_mode_r == 2'h1) && (p2_dec_pio_read_data < p2_e1_last_read_data_val_w)) - p2_e1_last_read_data_val_w_next = p2_dec_pio_read_data; - if ((p2_e1_cfg_read_capture_mode_r == 2'h2) && (p2_dec_pio_read_data > p2_e1_last_read_data_val_w)) - p2_e1_last_read_data_val_w_next = p2_dec_pio_read_data; - if (p2_e1_cntl_force_stop_r) begin - p2_e1_state_next = 3'h0; - end - else if (p2_e1_cfg_mode_r == 2'h2) begin - p2_e1_state_next = 3'h4; - p2_pio_dec_write_next = 1'b1; - p2_pio_dec_write_data_next = ((p2_e1_write_data_val_r & ~p2_e1_write_mask_val_r) | (p2_dec_pio_read_data & p2_e1_write_mask_val_r)); - end - else if (p2_e1_cfg_mode_r == 2'h1) begin - if (p2_e1_cfg_stop_on_count_r && (p2_e1_trans_count_next == {1'b0,p2_e1_max_trans_count_val_r})) - p2_e1_state_next = 3'h0; - else if (p2_pio_dec_address_next [6] == 1'b1) begin - p2_e1_state_next = 3'h0; - p2_e1_status_bad_address_error_intr = 1'b1; - end - else begin - p2_e1_state_next = 3'h1; - end - end - else p2_e1_state_next = 3'h0; - end - else if (p2_dec_pio_nack) begin - p2_e1_state_next = 3'h0; - p2_e1_status_nack_error_intr = 1'b1; - end - else begin - p2_pio_dec_read_next = 1'b1; - p2_arb_atomic_request_next = (p2_e1_cfg_mode_r == 2'h2); - end - end - 3'h4: begin // WRITE - if (p2_dec_pio_ack) begin - if (p2_e1_cfg_mode_r != 2'h1) begin - p2_e1_trans_count_next = p2_e1_trans_count + 41'b1; - p2_pio_dec_address_next = p2_pio_dec_address + p2_e1_address_step_val_r; - end - if ((p2_e1_cfg_stop_on_count_r && (p2_e1_trans_count_next == {1'b0,p2_e1_max_trans_count_val_r})) || p2_e1_cntl_force_stop_r) begin - p2_e1_state_next = 3'h0; - end - else if (p2_pio_dec_address_next [6] == 1'b1) begin - p2_e1_state_next = 3'h0; - p2_e1_status_bad_address_error_intr = 1'b1; - end - else if (p2_e1_cfg_mode_r == 2'h2) begin - p2_e1_state_next = 3'h1; - end - else begin - p2_e1_state_next = 3'h2; - end - end - else if (p2_dec_pio_nack) begin - p2_e1_state_next = 3'h0; - p2_e1_status_nack_error_intr = 1'b1; - end - else begin - p2_pio_dec_write_next = 1'b1; - end - end - default: - p2_e1_state_next = 3'h0; - endcase - end - - //------- reg assigns for secondary engine1 i/f sm - always_ff @ (posedge clk) begin - if (reset) begin - p2_e1_status_state_w <= #1 3'b0; - p2_e1_trans_count <= #1 161'b0; - p2_e1_delay_count <= #1 10'b0; - end - else begin - p2_e1_status_state_w <= #1 p2_e1_state_next; - p2_e1_trans_count <= #1 p2_e1_trans_count_next; - p2_e1_delay_count <= #1 p2_e1_delay_count_next; - end - end - - //------- reg assigns for secondary engine1 i/f signals - always_ff @ (posedge clk) begin - if (reset) begin - p2_pio_dec_write_data <= #1 32'b0; - p2_pio_dec_address <= #1 4'b0; - p2_pio_dec_read <= #1 1'b0; - p2_pio_dec_write <= #1 1'b0; - p2_arb_atomic_request <= #1 1'b0; - p2_e1_last_read_data_val_w <= #1 32'b0; - end - else begin - p2_pio_dec_write_data <= #1 p2_pio_dec_write_data_next; - p2_pio_dec_address <= #1 p2_pio_dec_address_next [5:2] ; - p2_pio_dec_read <= #1 p2_pio_dec_read_next; - p2_pio_dec_write <= #1 p2_pio_dec_write_next; - p2_arb_atomic_request <= #1 p2_arb_atomic_request_next; - p2_e1_last_read_data_val_w <= #1 p2_e1_last_read_data_val_w_next; - end - end - - //------- reg assigns for external i/f (reset signal = reset) - always_ff @ (posedge clk) begin - if (reset) begin - d2h_primary_we_ex <= #1 1'b0; - d2h_primary_re_ex <= #1 1'b0; - end - else begin - d2h_primary_we_ex <= #1 d2h_primary_we_next & ~h2d_primary_ack_ex & ~h2d_primary_nack_ex; - d2h_primary_re_ex <= #1 d2h_primary_re_next & ~h2d_primary_ack_ex & ~h2d_primary_nack_ex; - end - end - - //------- combinatorial assigns for interface arbiter input select - always_comb begin - pio_dec_address = p1_pio_dec_address; - pio_dec_write_data = p1_pio_dec_write_data; - if (arbiter_state == 3'h2) begin - pio_dec_address = p2_pio_dec_address; - pio_dec_write_data = p2_pio_dec_write_data; - end - end - - //------- reg assigns for pio i/f (reset signal = reset) - always_ff @ (posedge clk) begin - if (reset) begin - pio_write_active <= #1 1'b0; - pio_read_active <= #1 1'b0; - end - else begin - pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; - pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; - end - end - //------- combinatorial assigns for interface arbiter acks/nacks always_comb begin p1_dec_pio_ack = 1'b0; diff --git a/test/basic_tests/rdl_sec_if/golden/output.v b/test/basic_tests/rdl_sec_if/golden/output.v index 5437976..da861b6 100644 --- a/test/basic_tests/rdl_sec_if/golden/output.v +++ b/test/basic_tests/rdl_sec_if/golden/output.v @@ -1,7 +1,7 @@ -// Ordt 190606.01 autogenerated file +// Ordt 190615.01 autogenerated file // Input: ./rdl_sec_if/test.rdl // Parms: ./rdl_sec_if/test.parms -// Date: Thu Jun 06 13:31:00 EDT 2019 +// Date: Sat Jun 15 21:05:44 EDT 2019 // // @@ -725,6 +725,193 @@ module base_map_jrdl_decode end end + //------- combinatorial assigns for secondary engine1 i/f sm + always @ (*) begin + p2_e1_state_next = p2_e1_status_state_w; + p2_pio_dec_read_next = 1'b0; + p2_pio_dec_write_next = 1'b0; + p2_arb_atomic_request_next = 1'b0; + p2_pio_dec_write_data_next = p2_pio_dec_write_data; + p2_e1_last_read_data_val_w_next = p2_e1_last_read_data_val_w; + p2_e1_status_nack_error_intr = 1'b0; + p2_e1_status_bad_address_error_intr = 1'b0; + p2_e1_trans_count_next = p2_e1_trans_count; + p2_pio_dec_address_next = {1'b0, p2_pio_dec_address}; + p2_e1_delay_count_next = 10'b0; + case (p2_e1_status_state_w) + 3'h0: begin // IDLE + p2_e1_trans_count_next = 41'b0; + p2_pio_dec_address_next = {1'b0, p2_e1_address_start_val_r}; + if (p2_e1_cntl_start_r && !p2_e1_cntl_force_stop_r) begin + if (p2_e1_cfg_read_capture_mode_r == 2'h1) + p2_e1_last_read_data_val_w_next = ~32'b0; + else + p2_e1_last_read_data_val_w_next = 32'b0; + if ((p2_e1_cfg_mode_r == 2'h1) || (p2_e1_cfg_mode_r == 2'h2)) begin + p2_e1_state_next = 3'h1; + end + else begin + p2_e1_state_next = 3'h2; + p2_pio_dec_write_data_next = p2_e1_write_data_val_r; + end + end + end + 3'h1: begin // READ_WAIT + p2_e1_delay_count_next = p2_e1_delay_count + 10'b1; + if (p2_e1_cntl_force_stop_r) begin + p2_e1_state_next = 3'h0; + end + else if (p2_e1_delay_count == p2_e1_cfg_trans_delay_r) begin + p2_e1_state_next = 3'h3; + p2_pio_dec_read_next = 1'b1; + p2_arb_atomic_request_next = (p2_e1_cfg_mode_r == 2'h2); + end + else if (|p2_e1_trans_count) begin + if ((p2_e1_cfg_stop_on_read_r == 2'h2) && ((p2_e1_last_read_data_val_w & ~p2_e1_read_mask_val_r) == p2_e1_read_match_data_val_r)) + p2_e1_state_next = 3'h0; + if ((p2_e1_cfg_stop_on_read_r == 2'h1) && ((p2_e1_last_read_data_val_w & ~p2_e1_read_mask_val_r) < p2_e1_read_match_data_val_r)) + p2_e1_state_next = 3'h0; + if ((p2_e1_cfg_stop_on_read_r == 2'h3) && ((p2_e1_last_read_data_val_w & ~p2_e1_read_mask_val_r) > p2_e1_read_match_data_val_r)) + p2_e1_state_next = 3'h0; + end + end + 3'h2: begin // WRITE_WAIT + p2_e1_delay_count_next = p2_e1_delay_count + 10'b1; + if (p2_e1_cntl_force_stop_r) begin + p2_e1_state_next = 3'h0; + end + else if (p2_e1_delay_count == p2_e1_cfg_trans_delay_r) begin + p2_e1_state_next = 3'h4; + p2_pio_dec_write_next = 1'b1; + end + else if (|p2_e1_trans_count) begin + if ((p2_e1_cfg_stop_on_read_r == 2'h2) && ((p2_e1_last_read_data_val_w & ~p2_e1_read_mask_val_r) == p2_e1_read_match_data_val_r)) + p2_e1_state_next = 3'h0; + if ((p2_e1_cfg_stop_on_read_r == 2'h1) && ((p2_e1_last_read_data_val_w & ~p2_e1_read_mask_val_r) < p2_e1_read_match_data_val_r)) + p2_e1_state_next = 3'h0; + if ((p2_e1_cfg_stop_on_read_r == 2'h3) && ((p2_e1_last_read_data_val_w & ~p2_e1_read_mask_val_r) > p2_e1_read_match_data_val_r)) + p2_e1_state_next = 3'h0; + end + end + 3'h3: begin // READ + if (p2_dec_pio_ack) begin + if (p2_e1_cfg_mode_r == 2'h1) begin + p2_e1_trans_count_next = p2_e1_trans_count + 41'b1; + p2_pio_dec_address_next = p2_pio_dec_address + p2_e1_address_step_val_r; + end + if (p2_e1_cfg_read_capture_mode_r == 2'h3) + p2_e1_last_read_data_val_w_next = p2_dec_pio_read_data; + if ((p2_e1_cfg_read_capture_mode_r == 2'h1) && (p2_dec_pio_read_data < p2_e1_last_read_data_val_w)) + p2_e1_last_read_data_val_w_next = p2_dec_pio_read_data; + if ((p2_e1_cfg_read_capture_mode_r == 2'h2) && (p2_dec_pio_read_data > p2_e1_last_read_data_val_w)) + p2_e1_last_read_data_val_w_next = p2_dec_pio_read_data; + if (p2_e1_cntl_force_stop_r) begin + p2_e1_state_next = 3'h0; + end + else if (p2_e1_cfg_mode_r == 2'h2) begin + p2_e1_state_next = 3'h4; + p2_pio_dec_write_next = 1'b1; + p2_pio_dec_write_data_next = ((p2_e1_write_data_val_r & ~p2_e1_write_mask_val_r) | (p2_dec_pio_read_data & p2_e1_write_mask_val_r)); + end + else if (p2_e1_cfg_mode_r == 2'h1) begin + if (p2_e1_cfg_stop_on_count_r && (p2_e1_trans_count_next == {1'b0,p2_e1_max_trans_count_val_r})) + p2_e1_state_next = 3'h0; + else if (p2_pio_dec_address_next [6] == 1'b1) begin + p2_e1_state_next = 3'h0; + p2_e1_status_bad_address_error_intr = 1'b1; + end + else begin + p2_e1_state_next = 3'h1; + end + end + else p2_e1_state_next = 3'h0; + end + else if (p2_dec_pio_nack) begin + p2_e1_state_next = 3'h0; + p2_e1_status_nack_error_intr = 1'b1; + end + else begin + p2_pio_dec_read_next = 1'b1; + p2_arb_atomic_request_next = (p2_e1_cfg_mode_r == 2'h2); + end + end + 3'h4: begin // WRITE + if (p2_dec_pio_ack) begin + if (p2_e1_cfg_mode_r != 2'h1) begin + p2_e1_trans_count_next = p2_e1_trans_count + 41'b1; + p2_pio_dec_address_next = p2_pio_dec_address + p2_e1_address_step_val_r; + end + if ((p2_e1_cfg_stop_on_count_r && (p2_e1_trans_count_next == {1'b0,p2_e1_max_trans_count_val_r})) || p2_e1_cntl_force_stop_r) begin + p2_e1_state_next = 3'h0; + end + else if (p2_pio_dec_address_next [6] == 1'b1) begin + p2_e1_state_next = 3'h0; + p2_e1_status_bad_address_error_intr = 1'b1; + end + else if (p2_e1_cfg_mode_r == 2'h2) begin + p2_e1_state_next = 3'h1; + end + else begin + p2_e1_state_next = 3'h2; + end + end + else if (p2_dec_pio_nack) begin + p2_e1_state_next = 3'h0; + p2_e1_status_nack_error_intr = 1'b1; + end + else begin + p2_pio_dec_write_next = 1'b1; + end + end + default: + p2_e1_state_next = 3'h0; + endcase + end + + //------- reg assigns for secondary engine1 i/f sm + always @ (posedge clk) begin + if (reset) begin + p2_e1_status_state_w <= #1 3'b0; + p2_e1_trans_count <= #1 161'b0; + p2_e1_delay_count <= #1 10'b0; + end + else begin + p2_e1_status_state_w <= #1 p2_e1_state_next; + p2_e1_trans_count <= #1 p2_e1_trans_count_next; + p2_e1_delay_count <= #1 p2_e1_delay_count_next; + end + end + + //------- reg assigns for secondary engine1 i/f signals + always @ (posedge clk) begin + if (reset) begin + p2_pio_dec_write_data <= #1 32'b0; + p2_pio_dec_address <= #1 4'b0; + p2_pio_dec_read <= #1 1'b0; + p2_pio_dec_write <= #1 1'b0; + p2_arb_atomic_request <= #1 1'b0; + p2_e1_last_read_data_val_w <= #1 32'b0; + end + else begin + p2_pio_dec_write_data <= #1 p2_pio_dec_write_data_next; + p2_pio_dec_address <= #1 p2_pio_dec_address_next [5:2] ; + p2_pio_dec_read <= #1 p2_pio_dec_read_next; + p2_pio_dec_write <= #1 p2_pio_dec_write_next; + p2_arb_atomic_request <= #1 p2_arb_atomic_request_next; + p2_e1_last_read_data_val_w <= #1 p2_e1_last_read_data_val_w_next; + end + end + + //------- combinatorial assigns for interface arbiter input select + always @ (*) begin + pio_dec_address = p1_pio_dec_address; + pio_dec_write_data = p1_pio_dec_write_data; + if (arbiter_state == 3'h2) begin + pio_dec_address = p2_pio_dec_address; + pio_dec_write_data = p2_pio_dec_write_data; + end + end + //------- combinatorial assigns for primary ring16 i/f always @ (*) begin r16_primary_state_next = r16_primary_state; @@ -807,9 +994,9 @@ module base_map_jrdl_decode r16_primary_cmdData_dly1 <= #1 r16_primary_cmdData_dly0; r16_primary_resValid_dly1 <= #1 r16_primary_resValid_dly0; r16_primary_resData_dly1 <= #1 r16_primary_resData_dly0; - r16_primary_rdata_accum <= #1 r16_primary_rdata_accum_next; r16_primary_data_cnt <= #1 r16_primary_data_cnt_next; end + r16_primary_rdata_accum <= #1 r16_primary_rdata_accum_next; end //------- combinatorial assigns for interface arbiter sm @@ -909,12 +1096,28 @@ module base_map_jrdl_decode //------- reg assigns for pio i/f always @ (posedge clk) begin + if (reset) begin + pio_write_active <= #1 1'b0; + pio_read_active <= #1 1'b0; + end + else begin + pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; + pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; + end pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; end //------- reg assigns for external i/f always @ (posedge clk) begin + if (reset) begin + d2h_primary_we_ex <= #1 1'b0; + d2h_primary_re_ex <= #1 1'b0; + end + else begin + d2h_primary_we_ex <= #1 d2h_primary_we_next & ~h2d_primary_ack_ex & ~h2d_primary_nack_ex; + d2h_primary_re_ex <= #1 d2h_primary_re_next & ~h2d_primary_ack_ex & ~h2d_primary_nack_ex; + end d2h_primary_w_ex <= #1 d2h_primary_w_next; d2h_primary_addr_ex <= #1 d2h_primary_addr_next; end @@ -981,217 +1184,6 @@ module base_map_jrdl_decode end end - //------- combinatorial assigns for secondary engine1 i/f sm - always @ (*) begin - p2_e1_state_next = p2_e1_status_state_w; - p2_pio_dec_read_next = 1'b0; - p2_pio_dec_write_next = 1'b0; - p2_arb_atomic_request_next = 1'b0; - p2_pio_dec_write_data_next = p2_pio_dec_write_data; - p2_e1_last_read_data_val_w_next = p2_e1_last_read_data_val_w; - p2_e1_status_nack_error_intr = 1'b0; - p2_e1_status_bad_address_error_intr = 1'b0; - p2_e1_trans_count_next = p2_e1_trans_count; - p2_pio_dec_address_next = {1'b0, p2_pio_dec_address}; - p2_e1_delay_count_next = 10'b0; - case (p2_e1_status_state_w) - 3'h0: begin // IDLE - p2_e1_trans_count_next = 41'b0; - p2_pio_dec_address_next = {1'b0, p2_e1_address_start_val_r}; - if (p2_e1_cntl_start_r && !p2_e1_cntl_force_stop_r) begin - if (p2_e1_cfg_read_capture_mode_r == 2'h1) - p2_e1_last_read_data_val_w_next = ~32'b0; - else - p2_e1_last_read_data_val_w_next = 32'b0; - if ((p2_e1_cfg_mode_r == 2'h1) || (p2_e1_cfg_mode_r == 2'h2)) begin - p2_e1_state_next = 3'h1; - end - else begin - p2_e1_state_next = 3'h2; - p2_pio_dec_write_data_next = p2_e1_write_data_val_r; - end - end - end - 3'h1: begin // READ_WAIT - p2_e1_delay_count_next = p2_e1_delay_count + 10'b1; - if (p2_e1_cntl_force_stop_r) begin - p2_e1_state_next = 3'h0; - end - else if (p2_e1_delay_count == p2_e1_cfg_trans_delay_r) begin - p2_e1_state_next = 3'h3; - p2_pio_dec_read_next = 1'b1; - p2_arb_atomic_request_next = (p2_e1_cfg_mode_r == 2'h2); - end - else if (|p2_e1_trans_count) begin - if ((p2_e1_cfg_stop_on_read_r == 2'h2) && ((p2_e1_last_read_data_val_w & ~p2_e1_read_mask_val_r) == p2_e1_read_match_data_val_r)) - p2_e1_state_next = 3'h0; - if ((p2_e1_cfg_stop_on_read_r == 2'h1) && ((p2_e1_last_read_data_val_w & ~p2_e1_read_mask_val_r) < p2_e1_read_match_data_val_r)) - p2_e1_state_next = 3'h0; - if ((p2_e1_cfg_stop_on_read_r == 2'h3) && ((p2_e1_last_read_data_val_w & ~p2_e1_read_mask_val_r) > p2_e1_read_match_data_val_r)) - p2_e1_state_next = 3'h0; - end - end - 3'h2: begin // WRITE_WAIT - p2_e1_delay_count_next = p2_e1_delay_count + 10'b1; - if (p2_e1_cntl_force_stop_r) begin - p2_e1_state_next = 3'h0; - end - else if (p2_e1_delay_count == p2_e1_cfg_trans_delay_r) begin - p2_e1_state_next = 3'h4; - p2_pio_dec_write_next = 1'b1; - end - else if (|p2_e1_trans_count) begin - if ((p2_e1_cfg_stop_on_read_r == 2'h2) && ((p2_e1_last_read_data_val_w & ~p2_e1_read_mask_val_r) == p2_e1_read_match_data_val_r)) - p2_e1_state_next = 3'h0; - if ((p2_e1_cfg_stop_on_read_r == 2'h1) && ((p2_e1_last_read_data_val_w & ~p2_e1_read_mask_val_r) < p2_e1_read_match_data_val_r)) - p2_e1_state_next = 3'h0; - if ((p2_e1_cfg_stop_on_read_r == 2'h3) && ((p2_e1_last_read_data_val_w & ~p2_e1_read_mask_val_r) > p2_e1_read_match_data_val_r)) - p2_e1_state_next = 3'h0; - end - end - 3'h3: begin // READ - if (p2_dec_pio_ack) begin - if (p2_e1_cfg_mode_r == 2'h1) begin - p2_e1_trans_count_next = p2_e1_trans_count + 41'b1; - p2_pio_dec_address_next = p2_pio_dec_address + p2_e1_address_step_val_r; - end - if (p2_e1_cfg_read_capture_mode_r == 2'h3) - p2_e1_last_read_data_val_w_next = p2_dec_pio_read_data; - if ((p2_e1_cfg_read_capture_mode_r == 2'h1) && (p2_dec_pio_read_data < p2_e1_last_read_data_val_w)) - p2_e1_last_read_data_val_w_next = p2_dec_pio_read_data; - if ((p2_e1_cfg_read_capture_mode_r == 2'h2) && (p2_dec_pio_read_data > p2_e1_last_read_data_val_w)) - p2_e1_last_read_data_val_w_next = p2_dec_pio_read_data; - if (p2_e1_cntl_force_stop_r) begin - p2_e1_state_next = 3'h0; - end - else if (p2_e1_cfg_mode_r == 2'h2) begin - p2_e1_state_next = 3'h4; - p2_pio_dec_write_next = 1'b1; - p2_pio_dec_write_data_next = ((p2_e1_write_data_val_r & ~p2_e1_write_mask_val_r) | (p2_dec_pio_read_data & p2_e1_write_mask_val_r)); - end - else if (p2_e1_cfg_mode_r == 2'h1) begin - if (p2_e1_cfg_stop_on_count_r && (p2_e1_trans_count_next == {1'b0,p2_e1_max_trans_count_val_r})) - p2_e1_state_next = 3'h0; - else if (p2_pio_dec_address_next [6] == 1'b1) begin - p2_e1_state_next = 3'h0; - p2_e1_status_bad_address_error_intr = 1'b1; - end - else begin - p2_e1_state_next = 3'h1; - end - end - else p2_e1_state_next = 3'h0; - end - else if (p2_dec_pio_nack) begin - p2_e1_state_next = 3'h0; - p2_e1_status_nack_error_intr = 1'b1; - end - else begin - p2_pio_dec_read_next = 1'b1; - p2_arb_atomic_request_next = (p2_e1_cfg_mode_r == 2'h2); - end - end - 3'h4: begin // WRITE - if (p2_dec_pio_ack) begin - if (p2_e1_cfg_mode_r != 2'h1) begin - p2_e1_trans_count_next = p2_e1_trans_count + 41'b1; - p2_pio_dec_address_next = p2_pio_dec_address + p2_e1_address_step_val_r; - end - if ((p2_e1_cfg_stop_on_count_r && (p2_e1_trans_count_next == {1'b0,p2_e1_max_trans_count_val_r})) || p2_e1_cntl_force_stop_r) begin - p2_e1_state_next = 3'h0; - end - else if (p2_pio_dec_address_next [6] == 1'b1) begin - p2_e1_state_next = 3'h0; - p2_e1_status_bad_address_error_intr = 1'b1; - end - else if (p2_e1_cfg_mode_r == 2'h2) begin - p2_e1_state_next = 3'h1; - end - else begin - p2_e1_state_next = 3'h2; - end - end - else if (p2_dec_pio_nack) begin - p2_e1_state_next = 3'h0; - p2_e1_status_nack_error_intr = 1'b1; - end - else begin - p2_pio_dec_write_next = 1'b1; - end - end - default: - p2_e1_state_next = 3'h0; - endcase - end - - //------- reg assigns for secondary engine1 i/f sm - always @ (posedge clk) begin - if (reset) begin - p2_e1_status_state_w <= #1 3'b0; - p2_e1_trans_count <= #1 161'b0; - p2_e1_delay_count <= #1 10'b0; - end - else begin - p2_e1_status_state_w <= #1 p2_e1_state_next; - p2_e1_trans_count <= #1 p2_e1_trans_count_next; - p2_e1_delay_count <= #1 p2_e1_delay_count_next; - end - end - - //------- reg assigns for secondary engine1 i/f signals - always @ (posedge clk) begin - if (reset) begin - p2_pio_dec_write_data <= #1 32'b0; - p2_pio_dec_address <= #1 4'b0; - p2_pio_dec_read <= #1 1'b0; - p2_pio_dec_write <= #1 1'b0; - p2_arb_atomic_request <= #1 1'b0; - p2_e1_last_read_data_val_w <= #1 32'b0; - end - else begin - p2_pio_dec_write_data <= #1 p2_pio_dec_write_data_next; - p2_pio_dec_address <= #1 p2_pio_dec_address_next [5:2] ; - p2_pio_dec_read <= #1 p2_pio_dec_read_next; - p2_pio_dec_write <= #1 p2_pio_dec_write_next; - p2_arb_atomic_request <= #1 p2_arb_atomic_request_next; - p2_e1_last_read_data_val_w <= #1 p2_e1_last_read_data_val_w_next; - end - end - - //------- reg assigns for external i/f (reset signal = reset) - always @ (posedge clk) begin - if (reset) begin - d2h_primary_we_ex <= #1 1'b0; - d2h_primary_re_ex <= #1 1'b0; - end - else begin - d2h_primary_we_ex <= #1 d2h_primary_we_next & ~h2d_primary_ack_ex & ~h2d_primary_nack_ex; - d2h_primary_re_ex <= #1 d2h_primary_re_next & ~h2d_primary_ack_ex & ~h2d_primary_nack_ex; - end - end - - //------- combinatorial assigns for interface arbiter input select - always @ (*) begin - pio_dec_address = p1_pio_dec_address; - pio_dec_write_data = p1_pio_dec_write_data; - if (arbiter_state == 3'h2) begin - pio_dec_address = p2_pio_dec_address; - pio_dec_write_data = p2_pio_dec_write_data; - end - end - - //------- reg assigns for pio i/f (reset signal = reset) - always @ (posedge clk) begin - if (reset) begin - pio_write_active <= #1 1'b0; - pio_read_active <= #1 1'b0; - end - else begin - pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; - pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; - end - end - //------- combinatorial assigns for interface arbiter acks/nacks always @ (*) begin p1_dec_pio_ack = 1'b0; diff --git a/test/basic_tests/rdl_uvmmem_default/golden/output.sv b/test/basic_tests/rdl_uvmmem_default/golden/output.sv index a746fd6..501dd8a 100644 --- a/test/basic_tests/rdl_uvmmem_default/golden/output.sv +++ b/test/basic_tests/rdl_uvmmem_default/golden/output.sv @@ -1,7 +1,7 @@ -// Ordt 190606.01 autogenerated file +// Ordt 190615.01 autogenerated file // Input: ./rdl_uvmmem_default/test.rdl // Parms: ./rdl_uvmmem_default/test.parms -// Date: Thu Jun 06 13:31:01 EDT 2019 +// Date: Sat Jun 15 21:05:45 EDT 2019 // // @@ -42660,7 +42660,7 @@ module top_jrdl_decode end end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always_ff @ (posedge clk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -42672,10 +42672,6 @@ module top_jrdl_decode pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; dec_pio_trans_size <= #1 reg_width; end - end - - //------- reg assigns for pio i/f - always_ff @ (posedge clk) begin pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; pio_dec_trans_size_d1 <= #1 pio_dec_trans_size; diff --git a/test/basic_tests/rdl_uvmmem_default/golden/output.v b/test/basic_tests/rdl_uvmmem_default/golden/output.v index 01ed14b..40bd115 100644 --- a/test/basic_tests/rdl_uvmmem_default/golden/output.v +++ b/test/basic_tests/rdl_uvmmem_default/golden/output.v @@ -1,7 +1,7 @@ -// Ordt 190606.01 autogenerated file +// Ordt 190615.01 autogenerated file // Input: ./rdl_uvmmem_default/test.rdl // Parms: ./rdl_uvmmem_default/test.parms -// Date: Thu Jun 06 13:31:01 EDT 2019 +// Date: Sat Jun 15 21:05:45 EDT 2019 // // @@ -42660,7 +42660,7 @@ module top_jrdl_decode end end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always @ (posedge clk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -42672,10 +42672,6 @@ module top_jrdl_decode pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; dec_pio_trans_size <= #1 reg_width; end - end - - //------- reg assigns for pio i/f - always @ (posedge clk) begin pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; pio_dec_trans_size_d1 <= #1 pio_dec_trans_size; diff --git a/test/basic_tests/rdl_uvmmem_lite/golden/output.sv b/test/basic_tests/rdl_uvmmem_lite/golden/output.sv index e5a7aa1..c6bc328 100644 --- a/test/basic_tests/rdl_uvmmem_lite/golden/output.sv +++ b/test/basic_tests/rdl_uvmmem_lite/golden/output.sv @@ -1,7 +1,7 @@ -// Ordt 190606.01 autogenerated file +// Ordt 190615.01 autogenerated file // Input: ./rdl_uvmmem_lite/test.rdl // Parms: ./rdl_uvmmem_lite/test.parms -// Date: Thu Jun 06 13:31:03 EDT 2019 +// Date: Sat Jun 15 21:05:47 EDT 2019 // // @@ -42660,7 +42660,7 @@ module top_jrdl_decode end end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always_ff @ (posedge clk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -42672,10 +42672,6 @@ module top_jrdl_decode pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; dec_pio_trans_size <= #1 reg_width; end - end - - //------- reg assigns for pio i/f - always_ff @ (posedge clk) begin pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; pio_dec_trans_size_d1 <= #1 pio_dec_trans_size; diff --git a/test/basic_tests/rdl_uvmmem_lite/golden/output.v b/test/basic_tests/rdl_uvmmem_lite/golden/output.v index 51ee30b..a99a8eb 100644 --- a/test/basic_tests/rdl_uvmmem_lite/golden/output.v +++ b/test/basic_tests/rdl_uvmmem_lite/golden/output.v @@ -1,7 +1,7 @@ -// Ordt 190606.01 autogenerated file +// Ordt 190615.01 autogenerated file // Input: ./rdl_uvmmem_lite/test.rdl // Parms: ./rdl_uvmmem_lite/test.parms -// Date: Thu Jun 06 13:31:03 EDT 2019 +// Date: Sat Jun 15 21:05:47 EDT 2019 // // @@ -42660,7 +42660,7 @@ module top_jrdl_decode end end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always @ (posedge clk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -42672,10 +42672,6 @@ module top_jrdl_decode pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; dec_pio_trans_size <= #1 reg_width; end - end - - //------- reg assigns for pio i/f - always @ (posedge clk) begin pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; pio_dec_trans_size_d1 <= #1 pio_dec_trans_size; diff --git a/test/basic_tests/rdl_uvmmem_mimic/golden/output.sv b/test/basic_tests/rdl_uvmmem_mimic/golden/output.sv index 643c561..b26cb47 100644 --- a/test/basic_tests/rdl_uvmmem_mimic/golden/output.sv +++ b/test/basic_tests/rdl_uvmmem_mimic/golden/output.sv @@ -1,7 +1,7 @@ -// Ordt 190606.01 autogenerated file +// Ordt 190615.01 autogenerated file // Input: ./rdl_uvmmem_mimic/test.rdl // Parms: ./rdl_uvmmem_mimic/test.parms -// Date: Thu Jun 06 13:31:05 EDT 2019 +// Date: Sat Jun 15 21:05:49 EDT 2019 // // @@ -42660,7 +42660,7 @@ module top_jrdl_decode end end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always_ff @ (posedge clk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -42672,10 +42672,6 @@ module top_jrdl_decode pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; dec_pio_trans_size <= #1 reg_width; end - end - - //------- reg assigns for pio i/f - always_ff @ (posedge clk) begin pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; pio_dec_trans_size_d1 <= #1 pio_dec_trans_size; diff --git a/test/basic_tests/rdl_uvmmem_mimic/golden/output.v b/test/basic_tests/rdl_uvmmem_mimic/golden/output.v index 5b2aa50..34a18db 100644 --- a/test/basic_tests/rdl_uvmmem_mimic/golden/output.v +++ b/test/basic_tests/rdl_uvmmem_mimic/golden/output.v @@ -1,7 +1,7 @@ -// Ordt 190606.01 autogenerated file +// Ordt 190615.01 autogenerated file // Input: ./rdl_uvmmem_mimic/test.rdl // Parms: ./rdl_uvmmem_mimic/test.parms -// Date: Thu Jun 06 13:31:05 EDT 2019 +// Date: Sat Jun 15 21:05:49 EDT 2019 // // @@ -42660,7 +42660,7 @@ module top_jrdl_decode end end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always @ (posedge clk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -42672,10 +42672,6 @@ module top_jrdl_decode pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; dec_pio_trans_size <= #1 reg_width; end - end - - //------- reg assigns for pio i/f - always @ (posedge clk) begin pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; pio_dec_trans_size_d1 <= #1 pio_dec_trans_size; diff --git a/test/basic_tests/rdl_uvmmem_nums/golden/output.sv b/test/basic_tests/rdl_uvmmem_nums/golden/output.sv index 52d7d7a..daa1493 100644 --- a/test/basic_tests/rdl_uvmmem_nums/golden/output.sv +++ b/test/basic_tests/rdl_uvmmem_nums/golden/output.sv @@ -1,7 +1,7 @@ -// Ordt 190606.01 autogenerated file +// Ordt 190615.01 autogenerated file // Input: ./rdl_uvmmem_nums/test.rdl // Parms: ./rdl_uvmmem_nums/test.parms -// Date: Thu Jun 06 13:31:07 EDT 2019 +// Date: Sat Jun 15 21:05:51 EDT 2019 // // @@ -42660,7 +42660,7 @@ module top_jrdl_decode end end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always_ff @ (posedge clk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -42672,10 +42672,6 @@ module top_jrdl_decode pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; dec_pio_trans_size <= #1 reg_width; end - end - - //------- reg assigns for pio i/f - always_ff @ (posedge clk) begin pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; pio_dec_trans_size_d1 <= #1 pio_dec_trans_size; diff --git a/test/basic_tests/rdl_uvmmem_nums/golden/output.v b/test/basic_tests/rdl_uvmmem_nums/golden/output.v index f88ef2d..5841f3c 100644 --- a/test/basic_tests/rdl_uvmmem_nums/golden/output.v +++ b/test/basic_tests/rdl_uvmmem_nums/golden/output.v @@ -1,7 +1,7 @@ -// Ordt 190606.01 autogenerated file +// Ordt 190615.01 autogenerated file // Input: ./rdl_uvmmem_nums/test.rdl // Parms: ./rdl_uvmmem_nums/test.parms -// Date: Thu Jun 06 13:31:07 EDT 2019 +// Date: Sat Jun 15 21:05:51 EDT 2019 // // @@ -42660,7 +42660,7 @@ module top_jrdl_decode end end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always @ (posedge clk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -42672,10 +42672,6 @@ module top_jrdl_decode pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; dec_pio_trans_size <= #1 reg_width; end - end - - //------- reg assigns for pio i/f - always @ (posedge clk) begin pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; pio_dec_trans_size_d1 <= #1 pio_dec_trans_size; diff --git a/test/basic_tests/rdl_write_enable/golden/output.sv b/test/basic_tests/rdl_write_enable/golden/output.sv index 4888fc8..7cfe04b 100644 --- a/test/basic_tests/rdl_write_enable/golden/output.sv +++ b/test/basic_tests/rdl_write_enable/golden/output.sv @@ -1,7 +1,7 @@ -// Ordt 190606.01 autogenerated file +// Ordt 190615.01 autogenerated file // Input: ./rdl_write_enable/test.rdl // Parms: ./rdl_write_enable/test.parms -// Date: Thu Jun 06 13:31:09 EDT 2019 +// Date: Sat Jun 15 21:05:53 EDT 2019 // // @@ -374,19 +374,7 @@ module foo_jrdl_decode end end - //------- reg assigns for external i/f (reset signal = reset) - always_ff @ (posedge clk) begin - if (reset) begin - d2h_childmap_32b_we_ex <= #1 1'b0; - d2h_childmap_32b_re_ex <= #1 1'b0; - end - else begin - d2h_childmap_32b_we_ex <= #1 d2h_childmap_32b_we_next & ~h2d_childmap_32b_ack_ex & ~h2d_childmap_32b_nack_ex; - d2h_childmap_32b_re_ex <= #1 d2h_childmap_32b_re_next & ~h2d_childmap_32b_ack_ex & ~h2d_childmap_32b_nack_ex; - end - end - - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always_ff @ (posedge clk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -398,10 +386,6 @@ module foo_jrdl_decode pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; dec_pio_trans_size <= #1 reg_width; end - end - - //------- reg assigns for pio i/f - always_ff @ (posedge clk) begin pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; pio_dec_write_enable_d1 <= #1 pio_dec_write_enable; @@ -410,6 +394,14 @@ module foo_jrdl_decode //------- reg assigns for external i/f always_ff @ (posedge clk) begin + if (reset) begin + d2h_childmap_32b_we_ex <= #1 1'b0; + d2h_childmap_32b_re_ex <= #1 1'b0; + end + else begin + d2h_childmap_32b_we_ex <= #1 d2h_childmap_32b_we_next & ~h2d_childmap_32b_ack_ex & ~h2d_childmap_32b_nack_ex; + d2h_childmap_32b_re_ex <= #1 d2h_childmap_32b_re_next & ~h2d_childmap_32b_ack_ex & ~h2d_childmap_32b_nack_ex; + end d2h_childmap_32b_w_ex <= #1 d2h_childmap_32b_w_next; d2h_childmap_32b_w_enable_ex <= #1 d2h_childmap_32b_w_enable_next; d2h_childmap_32b_addr_ex <= #1 d2h_childmap_32b_addr_next; @@ -1124,7 +1116,7 @@ module foo_childmap_32b_jrdl_decode end end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always_ff @ (posedge clk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -1134,10 +1126,6 @@ module foo_childmap_32b_jrdl_decode pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; end - end - - //------- reg assigns for pio i/f - always_ff @ (posedge clk) begin pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; pio_dec_write_enable_d1 <= #1 pio_dec_write_enable; diff --git a/test/basic_tests/rdl_write_enable/golden/output.v b/test/basic_tests/rdl_write_enable/golden/output.v index fbf8fe3..2b99cbc 100644 --- a/test/basic_tests/rdl_write_enable/golden/output.v +++ b/test/basic_tests/rdl_write_enable/golden/output.v @@ -1,7 +1,7 @@ -// Ordt 190606.01 autogenerated file +// Ordt 190615.01 autogenerated file // Input: ./rdl_write_enable/test.rdl // Parms: ./rdl_write_enable/test.parms -// Date: Thu Jun 06 13:31:09 EDT 2019 +// Date: Sat Jun 15 21:05:53 EDT 2019 // // @@ -374,19 +374,7 @@ module foo_jrdl_decode end end - //------- reg assigns for external i/f (reset signal = reset) - always @ (posedge clk) begin - if (reset) begin - d2h_childmap_32b_we_ex <= #1 1'b0; - d2h_childmap_32b_re_ex <= #1 1'b0; - end - else begin - d2h_childmap_32b_we_ex <= #1 d2h_childmap_32b_we_next & ~h2d_childmap_32b_ack_ex & ~h2d_childmap_32b_nack_ex; - d2h_childmap_32b_re_ex <= #1 d2h_childmap_32b_re_next & ~h2d_childmap_32b_ack_ex & ~h2d_childmap_32b_nack_ex; - end - end - - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always @ (posedge clk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -398,10 +386,6 @@ module foo_jrdl_decode pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; dec_pio_trans_size <= #1 reg_width; end - end - - //------- reg assigns for pio i/f - always @ (posedge clk) begin pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; pio_dec_write_enable_d1 <= #1 pio_dec_write_enable; @@ -410,6 +394,14 @@ module foo_jrdl_decode //------- reg assigns for external i/f always @ (posedge clk) begin + if (reset) begin + d2h_childmap_32b_we_ex <= #1 1'b0; + d2h_childmap_32b_re_ex <= #1 1'b0; + end + else begin + d2h_childmap_32b_we_ex <= #1 d2h_childmap_32b_we_next & ~h2d_childmap_32b_ack_ex & ~h2d_childmap_32b_nack_ex; + d2h_childmap_32b_re_ex <= #1 d2h_childmap_32b_re_next & ~h2d_childmap_32b_ack_ex & ~h2d_childmap_32b_nack_ex; + end d2h_childmap_32b_w_ex <= #1 d2h_childmap_32b_w_next; d2h_childmap_32b_w_enable_ex <= #1 d2h_childmap_32b_w_enable_next; d2h_childmap_32b_addr_ex <= #1 d2h_childmap_32b_addr_next; @@ -1188,7 +1180,7 @@ module foo_childmap_32b_jrdl_decode end end - //------- reg assigns for pio i/f (reset signal = reset) + //------- reg assigns for pio i/f always @ (posedge clk) begin if (reset) begin pio_write_active <= #1 1'b0; @@ -1198,10 +1190,6 @@ module foo_childmap_32b_jrdl_decode pio_write_active <= #1 pio_write_active ? pio_no_acks : pio_activate_write; pio_read_active <= #1 pio_read_active ? pio_no_acks : pio_activate_read; end - end - - //------- reg assigns for pio i/f - always @ (posedge clk) begin pio_dec_address_d1 <= #1 pio_dec_address; pio_dec_write_data_d1 <= #1 pio_dec_write_data; pio_dec_write_enable_d1 <= #1 pio_dec_write_enable;