Activity
Fix typo in CoreController
Fix typo in CoreController
Rename HazardDetection -> CoreController
Rename HazardDetection -> CoreController
Deleted branch
Add CSR support (#8)
Add CSR support (#8)
Pull request merge
Add CSR support
Add CSR support
Deleted branch
Bump version to Chisel 5.0.0 (#7)
Bump version to Chisel 5.0.0 (#7)
Pull request merge
Fix broken tests on 5.0.0, update sbt version
Fix broken tests on 5.0.0, update sbt version
Deleted branch
Deleted branch
Deleted branch
Deleted branch
Bump to chisel 5.0.0
Bump to chisel 5.0.0
Deleted branch
Update flow to simplify building and linking C programs (#6)
Update flow to simplify building and linking C programs (#6)
Pull request merge
Update flow to simplify building and linking C programs
Update flow to simplify building and linking C programs
Deleted branch
Add wrapper around core for easier SoC implementation (#5)
Add wrapper around core for easier SoC implementation (#5)
Add wrapper around core for easier SoC implementation (#5)
Add wrapper around core for easier SoC implementation (#5)
Pull request merge
Make tests more independent with distinct filenames
Make tests more independent with distinct filenames
Tweak assembly compilation, remove printf-debugging
Tweak assembly compilation, remove printf-debugging
Another attempt af fixing compilation issues
Another attempt af fixing compilation issues
Fix compilation issues on linux
Fix compilation issues on linux
Add flowchart and FSM diagram of cache
Add flowchart and FSM diagram of cache
Add Makefile, UART downloader, ysample programs that can be run on core
Add Makefile, UART downloader, ysample programs that can be run on core
Add HW bootloader for loading program from UART
Add HW bootloader for loading program from UART
Merge branch 'master' of https://github.com/KasperHesse/riscv-core
Merge branch 'master' of https://github.com/KasperHesse/riscv-core
Fix memOp being true if instr in memory stage is invalid (#4)
Fix memOp being true if instr in memory stage is invalid (#4)
Pull request merge
Fix memOp being true if instr in memory stage is invalid
Fix memOp being true if instr in memory stage is invalid
Sample instruction from I-cache in IF-ID pipeline register (#3)
Sample instruction from I-cache in IF-ID pipeline register (#3)
Pull request merge