diff --git a/.github/workflows/compile-examples.yml b/.github/workflows/compile-examples.yml index 563a8e78..e10169f9 100644 --- a/.github/workflows/compile-examples.yml +++ b/.github/workflows/compile-examples.yml @@ -511,6 +511,7 @@ jobs: if: ${{matrix.device.hasinternal == 1}} uses: arduino/compile-sketches@main with: + cli-version: 0.33.0 fqbn: ${{ env.job_fqbn }} sketch-paths: | ${{ env[format('available-flash-8kB-sketch-paths-{0}', matrix.device.available-flash-kB >= 7.5)] }} @@ -534,6 +535,7 @@ jobs: if: ${{matrix.device.hasinternal == 1}} uses: arduino/compile-sketches@main with: + cli-version: 0.33.0 fqbn: ${{ env.minspeed_job_fqbn }} sketch-paths: | ${{ env[format('available-flash-8kB-sketch-paths-{0}', matrix.device.available-flash-kB >= 7.5)] }} @@ -557,6 +559,7 @@ jobs: if: ${{matrix.device.crystal == 1}} uses: arduino/compile-sketches@main with: + cli-version: 0.33.0 fqbn: ${{ env.xtal_job_fqbn }} sketch-paths: | ${{ env[format('available-flash-8kB-sketch-paths-{0}', matrix.device.available-flash-kB >= 7.5)] }} @@ -580,6 +583,7 @@ jobs: if: ${{matrix.device.pll == 1}} uses: arduino/compile-sketches@main with: + cli-version: 0.33.0 fqbn: ${{ env.pll_job_fqbn }} sketch-paths: | ${{ env[format('available-flash-8kB-sketch-paths-{0}', matrix.device.available-flash-kB >= 7.5)] }} @@ -603,6 +607,7 @@ jobs: if: ${{matrix.device.pll == 1}} uses: arduino/compile-sketches@main with: + cli-version: 0.33.0 fqbn: ${{ env.pll165_job_fqbn }} sketch-paths: | ${{ env[format('available-flash-8kB-sketch-paths-{0}', matrix.device.available-flash-kB >= 7.5)] }} @@ -626,6 +631,7 @@ jobs: if: ${{matrix.device.extclk == 1}} uses: arduino/compile-sketches@main with: + cli-version: 0.33.0 fqbn: ${{ env.extclk_job_fqbn }} sketch-paths: | ${{ env[format('available-flash-8kB-sketch-paths-{0}', matrix.device.available-flash-kB >= 7.5)] }} @@ -649,6 +655,7 @@ jobs: if: ${{matrix.device.havespecialclock == 1}} uses: arduino/compile-sketches@main with: + cli-version: 0.33.0 fqbn: ${{ env.specclk_job_fqbn }} sketch-paths: | ${{ env[format('available-flash-8kB-sketch-paths-{0}', matrix.device.available-flash-kB >= 7.5)] }} diff --git a/avr/extras/Ref_ChangePWMFreq.md b/avr/extras/Ref_ChangePWMFreq.md index 4fcd66c7..4b6daaff 100644 --- a/avr/extras/Ref_ChangePWMFreq.md +++ b/avr/extras/Ref_ChangePWMFreq.md @@ -3,6 +3,8 @@ ## Classic AVR This is concerned with Classic AVRs (those released before 2016), specifically those supported by ATTinyCore. The ATmegas use essentially the same timer1, (usually with the normal 2 outputs, occasionally with a third compare channel) - but they also typically have a very different timer2 than we get. Because this is targeted at ATTinyCore users, we will not be discussing the Async timer2; however for ATmega parts with multiple 16-bit timers that are copies of timer1 (usually timer 1, and 3 through 5 if present are this kind of timer) - they have the same timer, sometimes with an third output compare channel +Modern AVRs supported by DxCore and megaTinyCore have analogous documentation, for information on those parts see the DxC and mTC documentation. + You can change the PWM frequency to a limited number of values on **Timer/Counter1** and (if present) **Timer/Counter2** by simply adjusting the prescaler *while still using analogWrite()*. A much wider range of frequencies are accessible if you take full control of the timer, but in these cases, you would need to change registers that analogWrite() assumes a computationally convenient value is stored in, and analogWrite() would no longer work. Note that since Timer/Counter0 is used for millis, no registers of Timer0 should ever be written unless millis is disabled from the tools menu. @@ -24,7 +26,7 @@ In a timer counter unit, when we're talking about PWM, we're talking about the s * Arbitrary TOP values, sometimes without the loss of an output, other times only at the cost of an output channel * Higher resolution on Timer1 and Timer2 (where present), at least on most parts, which have a 16-bit timer1 (and the x61's with a 10-bit one, though using that 10-bit one is tricky) * Asynchronous low speed operation from an external clock or watch crystal (x7, possibly a small number of others) - * Asynchronous high speed operration from a x8 PLL on the 8 MHz internal osc. (x5, x61 26 only) + * Asynchronous high speed operation from a x8 PLL on the 8 MHz internal osc. (x5, x61 26 only) ### What can I change without breaking analogWrite() or other core API functions? * TC0 cannot be reconfigured at all without breaking millis, and should only be used if millis is disabled from the tools submenu. diff --git a/avr/extras/SpecificationConventions.md b/avr/extras/SpecificationConventions.md index 2abbca21..2a8c5bc0 100644 --- a/avr/extras/SpecificationConventions.md +++ b/avr/extras/SpecificationConventions.md @@ -45,4 +45,4 @@ This control two things: Which microcontroller or family will be used (a "family Very simple. When a family (as opposed to single chip) is selected, this is where you choose which one you are using. ### Clock Source and Speed -Often a VERY long menu, this lists all supported combinations of clock source and clock speed for the system clock. The options are listed in descending order of popularity/usefulness. Internmal and PLL speeds (if present) are at the top. Then come Crystal speeds, starting with common ones, then USART-crystals (the speeds that provide perfect UART baud rates, at the expense of making timekeeping slower and worse). After that are the rarely used "tuned" bootloader options that allow a chip which has been "tuned" by running the tuning sketch. These speeds are generally 8 MHz (user calibration at operating temperature and voltage beats factory cal significantly), 12.0 MHz, and on most parts, 12.8 (12.8 is mathematically favorable since 64 divides evenly into it, vastly simplifying the math. All of these speeds can almost always be reached with the internal oscillator and tuning. On the ATtiny841 and 441, the oscillator is much fancier, and an additional 16 MHz tuning is attempted. Most chips can do it (as long as they're running at around 5v) a few have unusually slow oscillators and cannot. Finally, we end on the external CLOCK options. An external clock is a component that looks near identical to a square, golden crystal package most of the time, but the pins are typically Out and Enable in place of the two crystal pins (if enable control is to needed, enable should be tied high, low, or allowed to float depending on the device, refer to the datasheet). The other two opposite corners are Vdd and Gnd. It is imperitve that these never be powered baclwardsl they will burn out aslmost instantly. External clocks also cost a lot more money than crystals, and the "china discount" for buying parts direct from china is much smaller than with crystals". +Often a VERY long menu, this lists all supported combinations of clock source and clock speed for the system clock. The options are listed in approximately descending order of popularity/usefulness. Internmal and PLL speeds (if present) are at the top. Then come Crystal speeds, starting with common ones, then USART-crystals (the speeds that provide perfect UART baud rates, at the expense of making timekeeping slower and worse). After that are the rarely used "tuned" bootloader options that allow a chip which has been "tuned" by running the tuning sketch. These speeds are generally 8 MHz (user calibration at operating temperature and voltage beats factory cal significantly), 12.0 MHz, and on most parts, 12.8 (12.8 is mathematically favorable since 64 divides evenly into it, vastly simplifying the math. All of these speeds can almost always be reached with the internal oscillator and tuning. On the ATtiny841 and 441, the oscillator is much fancier, and an additional 16 MHz tuning is attempted. Most chips can do it (as long as they're running at around 5v) a few have unusually slow oscillators and cannot. Finally, we end on the external CLOCK options. An external clock is a component that looks near identical to a square, golden crystal package most of the time, but the pins are typically Out and Enable in place of the two crystal pins (if enable control pin is present, consult the datasheet to see if the enable is active high or low, or if it turns itself on automatically when alowed to float, and connect that pin appropriately. It is only extremely unusual use cases that will do something other than tie the pin high, low, or leave floating, whenever turns it on. The other two opposite corners are Vdd and Gnd. It is imperitve that these never be powered backwards (for example, by the easy mistake of the orientation being rotated 180 degrees) - the oscillators will destoy themselves essentially immediately if power is applied like that (this is almost always true of IC's, and though it looks like a crystal the active I've seen that's harder to see the orientation marks on. External clocks also cost a lot more money than crystals, and the "china discount" for buying parts direct from china is much smaller than with crystals".