-
Notifications
You must be signed in to change notification settings - Fork 25
/
Copy patharch_arm64.cpp
3562 lines (3214 loc) · 117 KB
/
arch_arm64.cpp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
#define _CRT_SECURE_NO_WARNINGS
#define NOMINMAX
#include <cstdint>
#include <inttypes.h>
#include <map>
#include <array>
#include <stdio.h>
#include <string.h>
#include "arm64dis.h"
#include "binaryninjaapi.h"
#include "il.h"
#include "lowlevelilinstruction.h"
#include "neon_intrinsics.h"
using namespace BinaryNinja;
using namespace std;
#if defined(_MSC_VER)
#define snprintf _snprintf
#endif
#define EMPTY(S) (S[0] == '\0')
#define BINARYNINJA_MANUAL_RELOCATION ((uint64_t)-2)
enum MachoArm64RelocationType : uint32_t
{
ARM64_RELOC_UNSIGNED = 0,
ARM64_RELOC_SUBTRACTOR = 1,
ARM64_RELOC_BRANCH26 = 2,
ARM64_RELOC_PAGE21 = 3,
ARM64_RELOC_PAGEOFF12 = 4,
ARM64_RELOC_GOT_LOAD_PAGE21 = 5,
ARM64_RELOC_GOT_LOAD_PAGEOFF12 = 6,
ARM64_RELOC_POINTER_TO_GOT = 7,
ARM64_RELOC_TLVP_LOAD_PAGE21 = 8,
ARM64_RELOC_TLVP_LOAD_PAGEOFF12 = 9,
ARM64_RELOC_ADDEND = 10,
MACHO_MAX_ARM64_RELOCATION = 11
};
enum ElfArm64RelocationType : uint32_t
{
R_ARM_NONE = 0,
R_AARCH64_P32_COPY = 180,
R_AARCH64_P32_GLOB_DAT = 181,
R_AARCH64_P32_JUMP_SLOT = 182,
R_AARCH64_P32_RELATIVE = 183,
R_AARCH64_NONE = 256,
// Data
R_AARCH64_ABS64 = 257,
R_AARCH64_ABS32 = 258,
R_AARCH64_ABS16 = 259,
R_AARCH64_PREL64 = 260,
R_AARCH64_PREL32 = 261,
R_AARCH64_PREL16 = 262,
// Instructions
R_AARCH64_MOVW_UABS_G0 = 263,
R_AARCH64_MOVW_UABS_G0_NC = 264,
R_AARCH64_MOVW_UABS_G1 = 265,
R_AARCH64_MOVW_UABS_G1_NC = 266,
R_AARCH64_MOVW_UABS_G2 = 267,
R_AARCH64_MOVW_UABS_G2_NC = 268,
R_AARCH64_MOVW_UABS_G3 = 269,
R_AARCH64_MOVW_SABS_G0 = 270,
R_AARCH64_MOVW_SABS_G1 = 271,
R_AARCH64_MOVW_SABS_G2 = 272,
R_AARCH64_LD_PREL_LO19 = 273,
R_AARCH64_ADR_PREL_LO21 = 274,
R_AARCH64_ADR_PREL_PG_HI21 = 275,
R_AARCH64_ADR_PREL_PG_HI21_NC = 276,
R_AARCH64_ADD_ABS_LO12_NC = 277,
R_AARCH64_LDST8_ABS_LO12_NC = 278,
R_AARCH64_TSTBR14 = 279,
R_AARCH64_CONDBR19 = 280,
R_AARCH64_JUMP26 = 282,
R_AARCH64_CALL26 = 283,
R_AARCH64_LDST16_ABS_LO12_NC = 284,
R_AARCH64_LDST32_ABS_LO12_NC = 285,
R_AARCH64_LDST64_ABS_LO12_NC = 286,
R_AARCH64_LDST128_ABS_LO12_NC = 299,
R_AARCH64_MOVW_PREL_G0 = 287,
R_AARCH64_MOVW_PREL_G0_NC = 288,
R_AARCH64_MOVW_PREL_G1 = 289,
R_AARCH64_MOVW_PREL_G1_NC = 290,
R_AARCH64_MOVW_PREL_G2 = 291,
R_AARCH64_MOVW_PREL_G2_NC = 292,
R_AARCH64_MOVW_PREL_G3 = 293,
R_AARCH64_MOVW_GOTOFF_G0 = 300,
R_AARCH64_MOVW_GOTOFF_G0_NC = 301,
R_AARCH64_MOVW_GOTOFF_G1 = 302,
R_AARCH64_MOVW_GOTOFF_G1_NC = 303,
R_AARCH64_MOVW_GOTOFF_G2 = 304,
R_AARCH64_MOVW_GOTOFF_G2_NC = 305,
R_AARCH64_MOVW_GOTOFF_G3 = 306,
R_AARCH64_GOTREL64 = 307,
R_AARCH64_GOTREL32 = 308,
R_AARCH64_GOT_LD_PREL19 = 309,
R_AARCH64_LD64_GOTOFF_LO15 = 310,
R_AARCH64_ADR_GOT_PAGE = 311,
R_AARCH64_LD64_GOT_LO12_NC = 312,
R_AARCH64_LD64_GOTPAGE_LO15 = 313,
R_AARCH64_COPY = 1024,
R_AARCH64_GLOB_DAT = 1025, // Create GOT entry.
R_AARCH64_JUMP_SLOT = 1026, // Create PLT entry.
R_AARCH64_RELATIVE = 1027, // Adjust by program base.
R_AARCH64_TLS_DTPREL64 = 1028,
R_AARCH64_TLS_DTPMOD64 = 1029,
R_AARCH64_TLS_TPREL64 = 1030,
R_AARCH64_TLS_DTPREL32 = 1031,
R_AARCH64_TLSDESC = 1031,
R_AARCH64_IRELATIVE = 1032,
};
enum PeArm64RelocationType : uint32_t
{
PE_IMAGE_REL_ARM64_ABSOLUTE = 0x0000, // The relocation is ignored.
PE_IMAGE_REL_ARM64_ADDR32 = 0x0001, // The 32-bit VA of the target.
PE_IMAGE_REL_ARM64_ADDR32NB = 0x0002, // The 32-bit RVA of the target.
PE_IMAGE_REL_ARM64_BRANCH26 = 0x0003, // The 26-bit relative displacement to the target, for B and BL instructions.
PE_IMAGE_REL_ARM64_PAGEBASE_REL21 = 0x0004, // The page base of the target, for ADRP instruction.
PE_IMAGE_REL_ARM64_REL21 = 0x0005, // The 12-bit relative displacement to the target, for instruction ADR
PE_IMAGE_REL_ARM64_PAGEOFFSET_12A = 0x0006, // The 12-bit page offset of the target, for instructions ADD/ADDS (immediate) with zero shift.
PE_IMAGE_REL_ARM64_PAGEOFFSET_12L = 0x0007, // The 12-bit page offset of the target, for instruction LDR (indexed, unsigned immediate).
PE_IMAGE_REL_ARM64_SECREL = 0x0008, // The 32-bit offset of the target from the beginning of its section. This is used to support debugging information and static thread local storage.
PE_IMAGE_REL_ARM64_SECREL_LOW12A = 0x0009, // Bit 0:11 of section offset of the target, for instructions ADD/ADDS (immediate) with zero shift.
PE_IMAGE_REL_ARM64_SECREL_HIGH12A = 0x000A, // Bit 12:23 of section offset of the target, for instructions ADD/ADDS (immediate) with zero shift.
PE_IMAGE_REL_ARM64_SECREL_LOW12L = 0x000B, // Bit 0:11 of section offset of the target, for instruction LDR (indexed, unsigned immediate).
PE_IMAGE_REL_ARM64_TOKEN = 0x000C, // CLR token.
PE_IMAGE_REL_ARM64_SECTION = 0x000D, // The 16-bit section index of the section that contains the target. This is used to support debugging information.
PE_IMAGE_REL_ARM64_ADDR64 = 0x000E, // The 64-bit VA of the relocation target.
PE_IMAGE_REL_ARM64_BRANCH19 = 0x000F, // The 19-bit offset to the relocation target, for conditional B instruction.
PE_IMAGE_REL_ARM64_BRANCH14 = 0x0010, // The 14-bit offset to the relocation target, for instructions TBZ and TBNZ.
IMAGE_REL_ARM64_REL32 = 0x0011, // The 32-bit relative address from the byte following the relocation.
MAX_PE_ARM64_RELOCATION = 0x0012
};
static const char* GetRelocationString(MachoArm64RelocationType rel)
{
static const char* relocTable[] = {"ARM64_RELOC_UNSIGNED", "ARM64_RELOC_SUBTRACTOR",
"ARM64_RELOC_BRANCH26", "ARM64_RELOC_PAGE21", "ARM64_RELOC_PAGEOFF12",
"ARM64_RELOC_GOT_LOAD_PAGE21", "ARM64_RELOC_GOT_LOAD_PAGEOFF12", "ARM64_RELOC_POINTER_TO_GOT",
"ARM64_RELOC_TLVP_LOAD_PAGE21", "ARM64_RELOC_TLVP_LOAD_PAGEOFF12", "ARM64_RELOC_ADDEND"};
if (rel < MACHO_MAX_ARM64_RELOCATION)
{
return relocTable[rel];
}
return "Unknown Aarch64 relocation";
}
static const char* GetRelocationString(PeArm64RelocationType rel)
{
static const char* relocTable[] = {
"IMAGE_REL_ARM64_ABSOLUTE",
"IMAGE_REL_ARM64_ADDR32",
"IMAGE_REL_ARM64_ADDR32NB",
"IMAGE_REL_ARM64_BRANCH26",
"IMAGE_REL_ARM64_PAGEBASE_REL21",
"IMAGE_REL_ARM64_REL21",
"IMAGE_REL_ARM64_PAGEOFFSET_12A",
"IMAGE_REL_ARM64_PAGEOFFSET_12L",
"IMAGE_REL_ARM64_SECREL",
"IMAGE_REL_ARM64_SECREL_LOW12A",
"IMAGE_REL_ARM64_SECREL_HIGH12A",
"IMAGE_REL_ARM64_SECREL_LOW12L",
"IMAGE_REL_ARM64_TOKEN",
"IMAGE_REL_ARM64_SECTION",
"IMAGE_REL_ARM64_ADDR64",
"IMAGE_REL_ARM64_BRANCH19",
"IMAGE_REL_ARM64_BRANCH14",
"IMAGE_REL_ARM64_REL32"
};
if (rel < MAX_PE_ARM64_RELOCATION)
{
return relocTable[rel];
}
return "Unknown Aarch64 relocation";
}
static const char* GetRelocationString(ElfArm64RelocationType rel)
{
static map<ElfArm64RelocationType, const char*> relocMap = {
{R_ARM_NONE, "R_ARM_NONE"},
{R_AARCH64_P32_COPY, "R_AARCH64_P32_COPY"},
{R_AARCH64_P32_GLOB_DAT, "R_AARCH64_P32_GLOB_DAT"},
{R_AARCH64_P32_JUMP_SLOT, "R_AARCH64_P32_JUMP_SLOT"},
{R_AARCH64_P32_RELATIVE, "R_AARCH64_P32_RELATIVE"},
{R_AARCH64_NONE, "R_AARCH64_NONE"},
{R_AARCH64_ABS64, "R_AARCH64_ABS64"},
{R_AARCH64_ABS32, "R_AARCH64_ABS32"},
{R_AARCH64_ABS16, "R_AARCH64_ABS16"},
{R_AARCH64_PREL64, "R_AARCH64_PREL64"},
{R_AARCH64_PREL32, "R_AARCH64_PREL32"},
{R_AARCH64_PREL16, "R_AARCH64_PREL16"},
{R_AARCH64_MOVW_UABS_G0, "R_AARCH64_MOVW_UABS_G0"},
{R_AARCH64_MOVW_UABS_G0_NC, "R_AARCH64_MOVW_UABS_G0_NC"},
{R_AARCH64_MOVW_UABS_G1, "R_AARCH64_MOVW_UABS_G1"},
{R_AARCH64_MOVW_UABS_G1_NC, "R_AARCH64_MOVW_UABS_G1_NC"},
{R_AARCH64_MOVW_UABS_G2, "R_AARCH64_MOVW_UABS_G2"},
{R_AARCH64_MOVW_UABS_G2_NC, "R_AARCH64_MOVW_UABS_G2_NC"},
{R_AARCH64_MOVW_UABS_G3, "R_AARCH64_MOVW_UABS_G3"},
{R_AARCH64_MOVW_SABS_G0, "R_AARCH64_MOVW_SABS_G0"},
{R_AARCH64_MOVW_SABS_G1, "R_AARCH64_MOVW_SABS_G1"},
{R_AARCH64_MOVW_SABS_G2, "R_AARCH64_MOVW_SABS_G2"},
{R_AARCH64_LD_PREL_LO19, "R_AARCH64_LD_PREL_LO19"},
{R_AARCH64_ADR_PREL_LO21, "R_AARCH64_ADR_PREL_LO21"},
{R_AARCH64_ADR_PREL_PG_HI21, "R_AARCH64_ADR_PREL_PG_HI21"},
{R_AARCH64_ADR_PREL_PG_HI21_NC, "R_AARCH64_ADR_PREL_PG_HI21_NC"},
{R_AARCH64_ADD_ABS_LO12_NC, "R_AARCH64_ADD_ABS_LO12_NC"},
{R_AARCH64_LDST8_ABS_LO12_NC, "R_AARCH64_LDST8_ABS_LO12_NC"},
{R_AARCH64_TSTBR14, "R_AARCH64_TSTBR14"},
{R_AARCH64_CONDBR19, "R_AARCH64_CONDBR19"},
{R_AARCH64_JUMP26, "R_AARCH64_JUMP26"},
{R_AARCH64_CALL26, "R_AARCH64_CALL26"},
{R_AARCH64_LDST16_ABS_LO12_NC, "R_AARCH64_LDST16_ABS_LO12_NC"},
{R_AARCH64_LDST32_ABS_LO12_NC, "R_AARCH64_LDST32_ABS_LO12_NC"},
{R_AARCH64_LDST64_ABS_LO12_NC, "R_AARCH64_LDST64_ABS_LO12_NC"},
{R_AARCH64_LDST128_ABS_LO12_NC, "R_AARCH64_LDST128_ABS_LO12_NC"},
{R_AARCH64_MOVW_PREL_G0, "R_AARCH64_MOVW_PREL_G0"},
{R_AARCH64_MOVW_PREL_G0_NC, "R_AARCH64_MOVW_PREL_G0_NC"},
{R_AARCH64_MOVW_PREL_G1, "R_AARCH64_MOVW_PREL_G1"},
{R_AARCH64_MOVW_PREL_G1_NC, "R_AARCH64_MOVW_PREL_G1_NC"},
{R_AARCH64_MOVW_PREL_G2, "R_AARCH64_MOVW_PREL_G2"},
{R_AARCH64_MOVW_PREL_G2_NC, "R_AARCH64_MOVW_PREL_G2_NC"},
{R_AARCH64_MOVW_PREL_G3, "R_AARCH64_MOVW_PREL_G3"},
{R_AARCH64_MOVW_GOTOFF_G0, "R_AARCH64_MOVW_GOTOFF_G0"},
{R_AARCH64_MOVW_GOTOFF_G0_NC, "R_AARCH64_MOVW_GOTOFF_G0_NC"},
{R_AARCH64_MOVW_GOTOFF_G1, "R_AARCH64_MOVW_GOTOFF_G1"},
{R_AARCH64_MOVW_GOTOFF_G1_NC, "R_AARCH64_MOVW_GOTOFF_G1_NC"},
{R_AARCH64_MOVW_GOTOFF_G2, "R_AARCH64_MOVW_GOTOFF_G2"},
{R_AARCH64_MOVW_GOTOFF_G2_NC, "R_AARCH64_MOVW_GOTOFF_G2_NC"},
{R_AARCH64_MOVW_GOTOFF_G3, "R_AARCH64_MOVW_GOTOFF_G3"},
{R_AARCH64_GOTREL64, "R_AARCH64_GOTREL64"},
{R_AARCH64_GOTREL32, "R_AARCH64_GOTREL32"},
{R_AARCH64_GOT_LD_PREL19, "R_AARCH64_GOT_LD_PREL19"},
{R_AARCH64_LD64_GOTOFF_LO15, "R_AARCH64_LD64_GOTOFF_LO15"},
{R_AARCH64_ADR_GOT_PAGE, "R_AARCH64_ADR_GOT_PAGE"},
{R_AARCH64_LD64_GOT_LO12_NC, "R_AARCH64_LD64_GOT_LO12_NC"},
{R_AARCH64_LD64_GOTPAGE_LO15, "R_AARCH64_LD64_GOTPAGE_LO15"},
{R_AARCH64_COPY, "R_AARCH64_COPY"},
{R_AARCH64_GLOB_DAT, "R_AARCH64_GLOB_DAT"},
{R_AARCH64_JUMP_SLOT, "R_AARCH64_JUMP_SLOT"},
{R_AARCH64_RELATIVE, "R_AARCH64_RELATIVE"},
{R_AARCH64_TLS_DTPREL64, "R_AARCH64_TLS_DTPREL64"},
{R_AARCH64_TLS_DTPMOD64, "R_AARCH64_TLS_DTPMOD64"},
{R_AARCH64_TLS_TPREL64, "R_AARCH64_TLS_TPREL64"},
{R_AARCH64_TLS_DTPREL32, "R_AARCH64_TLS_DTPREL32"},
{R_AARCH64_IRELATIVE, "R_AARCH64_IRELATIVE"}
};
if (relocMap.count(rel))
return relocMap.at(rel);
return "Unknown Aarch64 relocation";
}
class Arm64Architecture : public Architecture
{
protected:
size_t m_bits;
bool m_onlyDisassembleOnAlignedAddresses;
virtual bool Disassemble(const uint8_t* data, uint64_t addr, size_t maxLen, Instruction& result)
{
(void)addr;
(void)maxLen;
memset(&result, 0, sizeof(result));
if (m_onlyDisassembleOnAlignedAddresses && (addr % 4 != 0))
return false;
if (aarch64_decompose(*(uint32_t*)data, &result, addr) != 0)
return false;
return true;
}
virtual size_t GetAddressSize() const override { return 8; }
virtual size_t GetInstructionAlignment() const override { return 4; }
virtual size_t GetMaxInstructionLength() const override { return 4; }
bool IsTestAndBranch(const Instruction& instr)
{
return instr.operation == ARM64_TBZ || instr.operation == ARM64_TBNZ;
}
bool IsCompareAndBranch(const Instruction& instr)
{
return instr.operation == ARM64_CBZ || instr.operation == ARM64_CBNZ;
}
bool IsConditionalBranch(const Instruction& instr)
{
switch (instr.operation)
{
case ARM64_B_EQ:
case ARM64_B_NE:
case ARM64_B_CS:
case ARM64_B_CC:
case ARM64_B_MI:
case ARM64_B_PL:
case ARM64_B_VS:
case ARM64_B_VC:
case ARM64_B_HI:
case ARM64_B_LS:
case ARM64_B_GE:
case ARM64_B_LT:
case ARM64_B_GT:
case ARM64_B_LE:
case ARM64_B_AL:
case ARM64_B_NV:
return true;
default:
return false;
}
}
bool IsConditionalJump(const Instruction& instr)
{
return IsConditionalBranch(instr) || IsTestAndBranch(instr) || IsCompareAndBranch(instr);
}
void SetInstructionInfoForInstruction(
uint64_t addr, const Instruction& instr, InstructionInfo& result)
{
result.length = 4;
switch (instr.operation)
{
case ARM64_BL:
if (instr.operands[0].operandClass == LABEL)
result.AddBranch(CallDestination, instr.operands[0].immediate);
break;
case ARM64_B:
if (instr.operands[0].operandClass == LABEL)
result.AddBranch(UnconditionalBranch, instr.operands[0].immediate);
else
result.AddBranch(UnresolvedBranch);
break;
case ARM64_B_EQ:
case ARM64_B_NE:
case ARM64_B_CS:
case ARM64_B_CC:
case ARM64_B_MI:
case ARM64_B_PL:
case ARM64_B_VS:
case ARM64_B_VC:
case ARM64_B_HI:
case ARM64_B_LS:
case ARM64_B_GE:
case ARM64_B_LT:
case ARM64_B_GT:
case ARM64_B_LE:
case ARM64_B_AL:
case ARM64_B_NV:
result.AddBranch(TrueBranch, instr.operands[0].immediate);
result.AddBranch(FalseBranch, addr + 4);
break;
case ARM64_TBZ:
case ARM64_TBNZ:
result.AddBranch(TrueBranch, instr.operands[2].immediate);
result.AddBranch(FalseBranch, addr + 4);
break;
case ARM64_CBZ:
case ARM64_CBNZ:
result.AddBranch(TrueBranch, instr.operands[1].immediate);
result.AddBranch(FalseBranch, addr + 4);
break;
case ARM64_BR:
case ARM64_BRAA:
case ARM64_BRAAZ:
case ARM64_BRAB:
case ARM64_BRABZ:
case ARM64_DRPS:
result.AddBranch(UnresolvedBranch);
break;
case ARM64_ERET:
case ARM64_ERETAA:
case ARM64_ERETAB:
case ARM64_RET:
case ARM64_RETAA:
case ARM64_RETAB:
result.AddBranch(FunctionReturn);
break;
case ARM64_SVC:
case ARM64_HVC:
case ARM64_SMC:
result.AddBranch(SystemCall);
break;
case ARM64_UDF:
result.AddBranch(ExceptionBranch);
break;
default:
break;
}
}
uint32_t tokenize_shift(
const InstructionOperand* __restrict operand, vector<InstructionTextToken>& result)
{
if (operand->shiftType != ShiftType_NONE)
{
const char* shiftStr = get_shift(operand->shiftType);
if (shiftStr == NULL)
return FAILED_TO_DISASSEMBLE_OPERAND;
result.emplace_back(TextToken, ", ");
result.emplace_back(TextToken, shiftStr);
if (operand->shiftValueUsed != 0)
{
char buf[64] = {0};
snprintf(buf, sizeof(buf), "%#x", (uint32_t)operand->shiftValue);
result.emplace_back(TextToken, " #");
result.emplace_back(IntegerToken, buf, operand->shiftValue);
}
}
return DISASM_SUCCESS;
}
uint32_t tokenize_shifted_immediate(
const InstructionOperand* __restrict operand, vector<InstructionTextToken>& result)
{
char buf[64] = {0};
const char* sign = "";
if (operand == NULL)
return FAILED_TO_DISASSEMBLE_OPERAND;
uint64_t imm = operand->immediate;
if (operand->signedImm == 1 && ((int64_t)imm) < 0)
{
sign = "-";
imm = -(int64_t)imm;
}
switch (operand->operandClass)
{
case FIMM32:
{
union
{
uint32_t intValue;
float floatValue;
} f;
f.intValue = (uint32_t)operand->immediate;
snprintf(buf, sizeof(buf), "%.08f", f.floatValue);
result.emplace_back(TextToken, "#");
result.emplace_back(FloatingPointToken, buf);
break;
}
case IMM32:
snprintf(buf, sizeof(buf), "%s%#x", sign, (uint32_t)imm);
result.emplace_back(TextToken, "#");
result.emplace_back(IntegerToken, buf, operand->immediate);
break;
case IMM64:
snprintf(buf, sizeof(buf), "%s%#" PRIx64, sign, imm);
result.emplace_back(TextToken, "#");
result.emplace_back(IntegerToken, buf, operand->immediate);
break;
case LABEL:
snprintf(buf, sizeof(buf), "%#" PRIx64, operand->immediate);
result.emplace_back(PossibleAddressToken, buf, operand->immediate);
break;
default:
return FAILED_TO_DISASSEMBLE_OPERAND;
}
tokenize_shift(operand, result);
return DISASM_SUCCESS;
}
uint32_t tokenize_shifted_register(const InstructionOperand* restrict operand,
uint32_t registerNumber, vector<InstructionTextToken>& result)
{
const char* reg = get_register_name(operand->reg[registerNumber]);
if (EMPTY(reg))
return FAILED_TO_DISASSEMBLE_REGISTER;
result.emplace_back(RegisterToken, reg);
tokenize_shift(operand, result);
return DISASM_SUCCESS;
}
uint32_t tokenize_register(const InstructionOperand* restrict operand, uint32_t registerNumber,
vector<InstructionTextToken>& result)
{
char buf[64] = {0};
/* case: system registers */
if (operand->operandClass == SYS_REG)
{
snprintf(buf, sizeof(buf), "%s", get_system_register_name((SystemReg)operand->sysreg));
result.emplace_back(RegisterToken, buf);
return DISASM_SUCCESS;
}
if (operand->operandClass != REG && operand->operandClass != MULTI_REG)
return OPERAND_IS_NOT_REGISTER;
/* case: shifted registers */
if (operand->shiftType != ShiftType_NONE)
{
return tokenize_shifted_register(operand, registerNumber, result);
}
const char* reg = get_register_name(operand->reg[registerNumber]);
if (EMPTY(reg))
return FAILED_TO_DISASSEMBLE_REGISTER;
/* case: predicate registers */
if (operand->pred_qual && operand->reg[registerNumber] >= REG_P0 &&
operand->reg[registerNumber] <= REG_P31)
{
result.emplace_back(RegisterToken, reg);
result.emplace_back(TextToken, "/");
result.emplace_back(TextToken, string(1, operand->pred_qual));
return DISASM_SUCCESS;
}
/* case other regs */
result.emplace_back(RegisterToken, reg);
const char* arrspec = get_register_arrspec(operand->reg[registerNumber], operand);
if (arrspec)
result.emplace_back(TextToken, arrspec);
/* only use index if this is isolated REG (not, for example, MULTIREG */
if (operand->operandClass == REG && operand->laneUsed)
{
snprintf(buf, sizeof(buf), "%u", operand->lane);
result.emplace_back(TextToken, "[");
result.emplace_back(IntegerToken, buf);
result.emplace_back(TextToken, "]");
}
return DISASM_SUCCESS;
}
uint32_t tokenize_memory_operand(
const InstructionOperand* restrict operand, vector<InstructionTextToken>& result)
{
char immBuff[32] = {0};
char paramBuff[32] = {0};
const char *reg0, *reg1;
reg0 = get_register_name(operand->reg[0]);
if (EMPTY(reg0))
return FAILED_TO_DISASSEMBLE_REGISTER;
const char* sign = "";
int64_t imm = operand->immediate;
if (operand->signedImm && (int64_t)imm < 0)
{
sign = "-";
imm = -imm;
}
const char* startToken = "[";
const char* endToken = "]";
result.emplace_back(BeginMemoryOperandToken, startToken);
result.emplace_back(RegisterToken, reg0);
result.emplace_back(TextToken, get_register_arrspec(operand->reg[0], operand));
switch (operand->operandClass)
{
case MEM_REG:
break;
case MEM_PRE_IDX:
endToken = "]!";
snprintf(immBuff, sizeof(immBuff), "%s%#" PRIx64, sign, (uint64_t)imm);
result.emplace_back(TextToken, ", #");
result.emplace_back(IntegerToken, immBuff, operand->immediate);
break;
case MEM_POST_IDX: // [<reg>], <reg|imm>
endToken = NULL;
if (operand->reg[1] == REG_NONE)
{
snprintf(paramBuff, sizeof(paramBuff), "%s%#" PRIx64, sign, (uint64_t)imm);
result.emplace_back(EndMemoryOperandToken, "], #");
result.emplace_back(IntegerToken, paramBuff, operand->immediate);
}
else
{
reg1 = get_register_name(operand->reg[1]);
if (EMPTY(reg1))
return FAILED_TO_DISASSEMBLE_REGISTER;
result.emplace_back(EndMemoryOperandToken, "], ");
result.emplace_back(RegisterToken, reg1);
result.emplace_back(TextToken, get_register_arrspec(operand->reg[1], operand));
}
break;
case MEM_OFFSET: // [<reg> optional(imm)]
if (operand->immediate != 0)
{
snprintf(immBuff, sizeof(immBuff), "%s%#" PRIx64, sign, (uint64_t)imm);
result.emplace_back(TextToken, ", #");
result.emplace_back(IntegerToken, immBuff, operand->immediate);
if (operand->mul_vl)
result.emplace_back(TextToken, ", mul vl");
}
break;
case MEM_EXTENDED: // [<reg>, <reg> optional(shift optional(imm))]
result.emplace_back(TextToken, ", ");
reg1 = get_register_name(operand->reg[1]);
if (EMPTY(reg1))
return FAILED_TO_DISASSEMBLE_REGISTER;
result.emplace_back(RegisterToken, reg1);
result.emplace_back(TextToken, get_register_arrspec(operand->reg[1], operand));
tokenize_shift(operand, result);
break;
default:
return NOT_MEMORY_OPERAND;
}
if (endToken != NULL)
result.emplace_back(EndMemoryOperandToken, endToken);
return DISASM_SUCCESS;
}
uint32_t tokenize_multireg_operand(
const InstructionOperand* restrict operand, vector<InstructionTextToken>& result)
{
char index[32] = {0};
uint32_t elementCount = 0;
result.emplace_back(TextToken, "{");
for (; elementCount < 4 && operand->reg[elementCount] != REG_NONE; elementCount++)
{
if (elementCount != 0)
result.emplace_back(TextToken, ", ");
if (tokenize_register(operand, elementCount, result) != 0)
return FAILED_TO_DISASSEMBLE_OPERAND;
}
result.emplace_back(TextToken, "}");
if (operand->laneUsed)
{
result.emplace_back(TextToken, "[");
snprintf(index, sizeof(index), "%d", operand->lane);
result.emplace_back(IntegerToken, index, operand->lane);
result.emplace_back(TextToken, "]");
}
return DISASM_SUCCESS;
}
uint32_t tokenize_condition(
const InstructionOperand* restrict operand, vector<InstructionTextToken>& result)
{
const char* condStr = get_condition((Condition)operand->cond);
if (condStr == NULL)
return FAILED_TO_DISASSEMBLE_OPERAND;
result.emplace_back(TextToken, condStr);
return DISASM_SUCCESS;
}
uint32_t tokenize_implementation_specific(
const InstructionOperand* restrict operand, vector<InstructionTextToken>& result)
{
char buf[32] = {0};
get_implementation_specific(operand, buf, sizeof(buf));
result.emplace_back(RegisterToken, buf);
return DISASM_SUCCESS;
}
BNRegisterInfo RegisterInfo(
uint32_t fullWidthReg, size_t offset, size_t size, bool zeroExtend = false)
{
BNRegisterInfo result;
result.fullWidthRegister = fullWidthReg;
result.offset = offset;
result.size = size;
result.extend = zeroExtend ? ZeroExtendToFullWidth : NoExtend;
return result;
}
public:
Arm64Architecture() : Architecture("aarch64"), m_bits(64)
{
Ref<Settings> settings = Settings::Instance();
m_onlyDisassembleOnAlignedAddresses = settings->Get<bool>("arch.aarch64.disassembly.alignRequired") ? 1 : 0;
}
bool CanAssemble() override { return true; }
bool Assemble(const string& code, uint64_t addr, DataBuffer& result, string& errors) override
{
(void)addr;
int assembleResult;
char *instrBytes = NULL, *err = NULL;
int instrBytesLen = 0, errLen = 0;
string prepend = ".arch_extension crc\n" ".arch_extension sm4\n"
".arch_extension sha3\n" ".arch_extension sha2\n" ".arch_extension aes\n"
".arch_extension crypto\n" ".arch_extension fp\n" ".arch_extension simd\n"
".arch_extension ras\n" ".arch_extension lse\n" ".arch_extension predres\n"
".arch_extension ccdp\n" ".arch_extension mte\n" ".arch_extension memtag\n"
".arch_extension tlb-rmi\n" ".arch_extension pan\n" ".arch_extension pan-rwv\n"
".arch_extension ccpp\n" ".arch_extension rcpc\n" ".arch_extension rng\n"
".arch_extension sve\n" ".arch_extension sve2\n" ".arch_extension sve2-aes\n"
".arch_extension sve2-sm4\n" ".arch_extension sve2-sha3\n" ".arch_extension sve2-bitperm\n"
".arch_extension ls64\n" ".arch_extension xs\n" ".arch_extension pauth\n"
".arch_extension flagm\n" ".arch_extension rme\n" ".arch_extension sme\n"
".arch_extension sme-f64f64\n" ".arch_extension sme-i16i64\n" ".arch_extension hbc\n"
".arch_extension mops\n";
BNLlvmServicesInit();
errors.clear();
assembleResult =
BNLlvmServicesAssemble((prepend + code).c_str(), LLVM_SVCS_DIALECT_UNSPEC, "aarch64-none-none",
LLVM_SVCS_CM_DEFAULT, LLVM_SVCS_RM_STATIC, &instrBytes, &instrBytesLen, &err, &errLen);
if (assembleResult || errLen)
{
errors = err;
BNLlvmServicesAssembleFree(instrBytes, err);
return false;
}
result.Clear();
result.Append(instrBytes, instrBytesLen);
BNLlvmServicesAssembleFree(instrBytes, err);
return true;
}
virtual BNEndianness GetEndianness() const override { return LittleEndian; }
virtual bool GetInstructionInfo(
const uint8_t* data, uint64_t addr, size_t maxLen, InstructionInfo& result) override
{
if (maxLen < 4)
return false;
Instruction instr;
if (!Disassemble(data, addr, maxLen, instr))
return false;
SetInstructionInfoForInstruction(addr, instr, result);
return true;
}
virtual bool GetInstructionText(const uint8_t* data, uint64_t addr, size_t& len,
vector<InstructionTextToken>& result) override
{
len = 4;
Instruction instr;
bool tokenizeSuccess = false;
char buf[9];
if (!Disassemble(data, addr, len, instr))
return false;
memset(buf, 0x20, sizeof(buf));
const char* operation = get_operation(&instr);
if (operation == nullptr)
return false;
size_t operationLen = strlen(operation);
if (operationLen < 8)
{
buf[8 - operationLen] = '\0';
}
else
buf[1] = '\0';
result.emplace_back(InstructionToken, operation);
result.emplace_back(TextToken, buf);
for (size_t i = 0; i < MAX_OPERANDS; i++)
{
if (instr.operands[i].operandClass == NONE)
return true;
struct InstructionOperand *operand = &(instr.operands[i]);
if (i != 0)
result.emplace_back(OperandSeparatorToken, ", ");
switch (instr.operands[i].operandClass)
{
case FIMM32:
case IMM32:
case IMM64:
case LABEL:
tokenizeSuccess = tokenize_shifted_immediate(&instr.operands[i], result) == 0;
break;
case MEM_REG:
case MEM_PRE_IDX:
case MEM_POST_IDX:
case MEM_OFFSET:
case MEM_EXTENDED:
tokenizeSuccess = tokenize_memory_operand(&instr.operands[i], result) == 0;
break;
case REG:
case SYS_REG:
tokenizeSuccess = tokenize_register(&instr.operands[i], 0, result) == 0;
break;
case MULTI_REG:
tokenizeSuccess = tokenize_multireg_operand(&instr.operands[i], result) == 0;
break;
case CONDITION:
tokenizeSuccess = tokenize_condition(&instr.operands[i], result) == 0;
break;
case IMPLEMENTATION_SPECIFIC:
tokenizeSuccess = tokenize_implementation_specific(&instr.operands[i], result) == 0;
break;
case NAME:
result.emplace_back(TextToken, instr.operands[i].name);
tokenizeSuccess = true;
break;
case STR_IMM: /* eg: "mul #0xe" */
result.emplace_back(TextToken, instr.operands[i].name);
result.emplace_back(TextToken, " #");
snprintf(buf, sizeof(buf), "0x%" PRIx64, instr.operands[i].immediate);
result.emplace_back(IntegerToken, buf);
tokenizeSuccess = true;
break;
case ACCUM_ARRAY: /* eg: "za[w12, #0x6]" */
result.emplace_back(TextToken, "ZA");
result.emplace_back(TextToken, "[");
snprintf(buf, sizeof(buf), "%s", get_register_name(operand->reg[0]));
result.emplace_back(RegisterToken, buf);
result.emplace_back(OperandSeparatorToken, ", ");
result.emplace_back(TextToken, " #");
snprintf(buf, sizeof(buf), "0x%" PRIx64, operand->immediate);
result.emplace_back(IntegerToken, buf);
result.emplace_back(TextToken, "]");
tokenizeSuccess = true;
break;
case SME_TILE: /* eg: "z0v.b[w12, #0xb]" */
snprintf(buf, sizeof(buf), "Z%d", operand->tile);
result.emplace_back(TextToken, buf);
if (operand->slice == SLICE_HORIZONTAL)
result.emplace_back(TextToken, "h");
else if (operand->slice == SLICE_VERTICAL)
result.emplace_back(TextToken, "v");
result.emplace_back(TextToken, get_arrspec_str_truncated(operand->arrSpec));
if (operand->reg[0] != REG_NONE)
{
result.emplace_back(TextToken, "[");
snprintf(buf, sizeof(buf), "%s", get_register_name(operand->reg[0]));
result.emplace_back(RegisterToken, buf);
if (operand->arrSpec != ARRSPEC_FULL)
{
result.emplace_back(OperandSeparatorToken, ", ");
result.emplace_back(TextToken, " #");
snprintf(buf, sizeof(buf), "0x%" PRIx64, instr.operands[i].immediate);
result.emplace_back(IntegerToken, buf);
}
result.emplace_back(TextToken, "]");
}
tokenizeSuccess = true;
break;
case INDEXED_ELEMENT: /* eg: "p12.d[w15, #0xf]" */
result.emplace_back(RegisterToken, get_register_name(operand->reg[0]));
result.emplace_back(TextToken, get_arrspec_str_truncated(operand->arrSpec));
result.emplace_back(TextToken, "[");
result.emplace_back(RegisterToken, get_register_name(operand->reg[1]));
if (operand->immediate)
{
result.emplace_back(OperandSeparatorToken, ", ");
result.emplace_back(TextToken, "#");
snprintf(buf, sizeof(buf), "0x%" PRIx64, operand->immediate);
result.emplace_back(IntegerToken, buf);
}
result.emplace_back(TextToken, "]");
tokenizeSuccess = true;
break;
default:
LogError("operandClass %x\n", instr.operands[i].operandClass);
return false;
}
if (!tokenizeSuccess)
{
LogError("tokenize failed operandClass %x\n", instr.operands[i].operandClass);
return false;
}
}
return true;
}
virtual string GetIntrinsicName(uint32_t intrinsic) override
{
switch (intrinsic)
{
case ARM64_INTRIN_AUTDA:
return "__autda";
case ARM64_INTRIN_AUTDB:
return "__autdb";
case ARM64_INTRIN_AUTIA:
return "__autia";
case ARM64_INTRIN_AUTIB:
return "__autib";
case ARM64_INTRIN_ISB:
return "__isb";
case ARM64_INTRIN_WFE:
return "__wfe";
case ARM64_INTRIN_WFI:
return "__wfi";
case ARM64_INTRIN_MSR:
return "_WriteStatusReg";
case ARM64_INTRIN_MRS:
return "_ReadStatusReg";
case ARM64_INTRIN_HINT_DGH:
return "SystemHintOp_DGH";
case ARM64_INTRIN_ESB:
return "SystemHintOp_ESB";
case ARM64_INTRIN_PACDA:
return "__pacda";
case ARM64_INTRIN_PACDB:
return "__pacdb";
case ARM64_INTRIN_PACGA:
return "__pacga";
case ARM64_INTRIN_PACIA:
return "__pacia";
case ARM64_INTRIN_PACIB:
return "__pacib";
case ARM64_INTRIN_PSBCSYNC:
return "SystemHintOp_PSB";
case ARM64_INTRIN_HINT_TSB:
return "SystemHintOp_TSB";
case ARM64_INTRIN_HINT_CSDB:
return "SystemHintOp_CSDB";
case ARM64_INTRIN_HINT_BTI:
return "SystemHintOp_BTI";
case ARM64_INTRIN_SEV:
return "__sev";
case ARM64_INTRIN_SEVL:
return "__sevl";
case ARM64_INTRIN_DC:
return "__dc";
case ARM64_INTRIN_DMB:
return "__dmb";
case ARM64_INTRIN_DSB:
return "__dsb";
case ARM64_INTRIN_YIELD:
return "__yield";
case ARM64_INTRIN_PRFM:
return "__prefetch";
case ARM64_INTRIN_XPACD:
return "__xpacd";
case ARM64_INTRIN_XPACI:
return "__xpaci";
case ARM64_INTRIN_ERET:
return "_eret";
case ARM64_INTRIN_CLZ:
return "_CountLeadingZeros";
case ARM64_INTRIN_CLREX:
return "__clrex";
case ARM64_INTRIN_REV:
return "_byteswap";
case ARM64_INTRIN_RBIT:
return "__rbit";
case ARM64_INTRIN_AESD:
return "__aesd";
case ARM64_INTRIN_AESE:
return "__aese";
case ARM64_INTRIN_LDXR:
return "__ldxr";
case ARM64_INTRIN_LDXRB:
return "__ldxrb";
case ARM64_INTRIN_LDXRH:
return "__ldxrh";
case ARM64_INTRIN_LDAXR:
return "__ldaxr";
case ARM64_INTRIN_LDAXRB:
return "__ldaxrb";
case ARM64_INTRIN_LDAXRH:
return "__ldaxrh";
case ARM64_INTRIN_STXR:
return "__stxr";