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I have question regarding the returned value for RTLIL::Design::top_module().
I used this method in a pass to get the top module. This worked fine until I tested it in combination with a select command.
Here the top module was not the same as without the selection.
When using the command hierarchy this shows the 'actual' top module regardless of selected modules.
From the implementation it is clear that only the selected modules are considered to find the top module:
This discussion was converted from issue #2743 on August 13, 2021 09:54.
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I have question regarding the returned value for
RTLIL::Design::top_module()
.I used this method in a pass to get the top module. This worked fine until I tested it in combination with a
select
command.Here the top module was not the same as without the selection.
When using the command
hierarchy
this shows the 'actual' top module regardless of selected modules.From the implementation it is clear that only the selected modules are considered to find the top module:
yosys/kernel/rtlil.cc
Line 593 in 5c1e6a0
Is this the intended behavior?
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