Stuck trying to get my memory in BRAM rather than a list of registers....

[zaun]

This is my memory access logic:

// Memory array, addresses and offsets.
(* ram_style = "block" *)
reg [WIDTH-1:0] memory [0 : (SIZE/(WIDTH/8)) - 1];

localparam int WORD_SHIFT        = $clog2(WIDTH/8);
localparam int BYTE_OFFSET_WIDTH = (WIDTH > 8) ? $clog2(WIDTH/8) : 1;
wire [BYTE_OFFSET_WIDTH-1:0] byte_offset;
wire [XLEN-1:0] mem_word_addr;

generate
    if (WIDTH > 8) begin
        assign byte_offset = req_address[BYTE_OFFSET_WIDTH-1:0];
        assign mem_word_addr = req_address[XLEN-1:BYTE_OFFSET_WIDTH];
    end else begin
        assign byte_offset = 0;
        assign mem_word_addr = req_address;
    end
endgenerate

// Memory Access
localparam int MEM_PARTS = XLEN / WIDTH;    // number of reads/writes for each XLEN of data
reg [$clog2(MEM_PARTS):0]   mem_count;      // internal Counter for mem ops
reg                         mem_read;       // input set high for read mem op
reg                         mem_write;      // input set high for read mem op
reg                         mem_start;      // input set high to start mem op
reg                         mem_done;       // output will be high when mem op is done
reg [XLEN-1:0]              mem_data_reg;   // inout memory data register
always_ff @(posedge clk or posedge reset) begin
    if (reset) begin
        mem_count    <= 0;
        mem_done     <= 0;
        mem_data_reg <= 0;
    end else if (mem_start && ~mem_done) begin
        if (mem_count < MEM_PARTS) begin
            if (mem_read) begin
                // Read the current WIDTH bits from memory and place them into the correct position in mem_data_reg
                if (mem_count == 0) begin
                    `ifdef LOG_MEMORY `LOG("tl_ul_bios", ("/MEM_READ/ xlen=%0d width=%0d mem_word_addr=0x%0h mem_part=%0d mem_data_reg=0x%0h", XLEN, WIDTH, mem_word_addr, mem_count, memory[mem_word_addr + mem_count] << (WIDTH * mem_count))); `endif
                    mem_data_reg <= memory[mem_word_addr + mem_count] << (WIDTH * mem_count);
                end else begin
                    `ifdef LOG_MEMORY `LOG("tl_ul_bios", ("/MEM_READ/ xlen=%0d width=%0d mem_word_addr=0x%0h mem_part=%0d mem_data_reg=0x%0h", XLEN, WIDTH, mem_word_addr, mem_count, mem_data_reg | (memory[mem_word_addr + mem_count] << (WIDTH * mem_count)))); `endif
                    mem_data_reg <= mem_data_reg | (memory[mem_word_addr + mem_count] << (WIDTH * mem_count));
                end
            end begin
                // Extract the relevant WIDTH bits from mem_data_reg and write them to the current memory address
                `ifdef LOG_MEMORY `LOG("tl_ul_bios", ("/MEM_WRITE/ xlen=%0d width=%0d mem_word_addr=0x%0h mem_part=%0d part_data=0x%0h", XLEN, WIDTH, mem_word_addr, mem_count, mem_data_reg[WIDTH*mem_count +: WIDTH])); `endif
                memory[mem_word_addr + mem_count] <= mem_data_reg[WIDTH*mem_count + WIDTH-1 : WIDTH*mem_count];
            end

            // Increment the counter for the next part
            mem_count <= mem_count + 1;
            mem_done  <= 0;

            // Memory operation completed
            if (mem_count == MEM_PARTS - 1) begin
                `ifdef LOG_MEMORY `LOG("tl_ul_bios", ("/MEM_DONE/")); `endif
                mem_done   <= 1;
                mem_count  <= 0;
            end
        end
    end else begin
        // When not active, ensure mem_done is deasserted
        mem_done <= 0;
        mem_count  <= 0;
    end
end

If I comment out the memory write memory[mem_word_addr + mem_count] <= mem_data_reg[WIDTH*mem_count + WIDTH-1 : WIDTH*mem_count]; then the memory looks to use BRAM. If I keep it in, then I get the following warning...

Warning: Replacing memory \memory with list of registers. See src/tl_ul_bios.sv:169

I've tried all kinds of variations, but I'm at a loss and need some help. The full memory module is attached if it helps. My testbench works and I can simulate with this fine. It's just trying to use BRAM that I'm falling flat on.

tl_ul_bios.sv.txt

[zaun]

Answering this myself, as I finally figured it out.

always_ff @(posedge clk or posedge reset) begin

I can use posedge reset I can only look at clk. Removing the reset logic from the block and now it is BRAM.

[KrystalDelusion]

FWIW, you can prepend debug to the call to memory_libmap and it should give you debug information about memory type selection, see https://yosyshq.readthedocs.io/projects/yosys/en/latest/using_yosys/synthesis/memory.html#memory-mapping

[KrystalDelusion]

At a guess, your bram target doesn't support asynchronous reset, which is why triggering on reset causes it to downgrade to registers instead.