AXI BRAM fixed latency

[realtimeradio]

For a long time now, the shared_bram yellow block has had an option to embed pipelining registers, increasing the bram latency from 1 to either 2 or 3.
Seemingly, the AXI infrastructure always instantiates RAM with latency of 1. This can causes designs to misbehave if they rely on the BRAM latency being as advertised. Further, issues aren't picked up in simulation, since the Simulink simulation model does respect the user's latency choices.