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+# test_4_hls_identify_ctrl-data-reg
+e.g  
+in dft\dft_8_precomputed
+     cpp files 
+         main--------dft.cpp 
+         head--------dft.h
+         test--------dft_test.cpp
+ 
+ sythesis verilog files in dft\dft_8_precomputed\dft_8\solution1\impl\verilog
+ 
+ reports in dft\dft_8_precomputed\dft_8\solution1\syn\report
+ 
+ reports describe some details about the matching between codes & instances&modules and the meaning of some signals
+ 
+ 
+