2-Stage MIPS Processor

Code for the project for the course Introduction to Processor Architecture (Spring 2020)

processor.v - Contains the whole code in one module
instr_memory.mem - Contains 32-bit instructions written into 4 lines
main_memory.mem - Contains the register memory with the R0 initialized to zero
processor_tb.v - Contains the driver code to test the code
Instruction testbench - Contains examples which can be used to check the working of individual instructions (like add, sub, and,or,etc.)

Description

This a 2-stage MIPS ISA based processor capable of decoding and executing 28 instructions, namely