Init behavior between interpreter and verilator simulations is different.

[chick]

See example in Issue #109 for example traces.
The interpreter currently changes reset only on trailing edge of clock.
Verilator seems to do it at different times. I have examples from chisel tests with SimpleVending machine where interpreter does not match verilator behavior
Interpreter only allows reset changes based on it's peek poke interface
Verilator build does not appear to be restricted in the same way.

@jackkoenig notes that sometimes this can be non-deterministic and that it is important to have your DUT come out of reset in a deterministic way after reset had lowered.

[chick]

I need to dig deeper on this.
See also chisel-testers Issue chisel testers issue 159