diff --git a/docs_src/bazel_rules_macros.md b/docs_src/bazel_rules_macros.md index 0ab8a176e5..22e77869f2 100755 --- a/docs_src/bazel_rules_macros.md +++ b/docs_src/bazel_rules_macros.md @@ -10,6 +10,8 @@ ## check_sha256sum_frozen
+load("//xls/build_rules:xls_build_defs.bzl", "check_sha256sum_frozen")
+
 check_sha256sum_frozen(name, src, frozen_file, sha256sum)
 
@@ -95,6 +97,8 @@ Examples: ## check_sha256sum_test
+load("//xls/build_rules:xls_build_defs.bzl", "check_sha256sum_test")
+
 check_sha256sum_test(name, src, sha256sum)
 
@@ -130,6 +134,8 @@ Examples: ## proto_data
+load("//xls/build_rules:xls_build_defs.bzl", "proto_data")
+
 proto_data(name, src, proto_name, protobin_file)
 
@@ -165,6 +171,8 @@ Examples: ## xls_benchmark_verilog
+load("//xls/build_rules:xls_build_defs.bzl", "xls_benchmark_verilog")
+
 xls_benchmark_verilog(name, verilog_target)
 
@@ -192,6 +200,8 @@ Example: ## xls_dslx_library
+load("//xls/build_rules:xls_build_defs.bzl", "xls_dslx_library")
+
 xls_dslx_library(name, deps, srcs, warnings_as_errors)
 
@@ -251,6 +261,8 @@ Examples: ## xls_dslx_opt_ir_test
+load("//xls/build_rules:xls_build_defs.bzl", "xls_dslx_opt_ir_test")
+
 xls_dslx_opt_ir_test(name, benchmark_ir_args, dep, dslx_test_args, evaluator, expect_equivalent,
                      input_validator, input_validator_expr, ir_equivalence_args, ir_eval_args,
                      scheduling_options_proto, top)
@@ -306,6 +318,8 @@ Examples:
 ## xls_dslx_prove_quickcheck_test
 
 
+load("//xls/build_rules:xls_build_defs.bzl", "xls_dslx_prove_quickcheck_test")
+
 xls_dslx_prove_quickcheck_test(name, deps, srcs, library, test_filter)
 
@@ -359,6 +373,8 @@ Examples: ## xls_dslx_test
+load("//xls/build_rules:xls_build_defs.bzl", "xls_dslx_test")
+
 xls_dslx_test(name, deps, srcs, dslx_test_args, evaluator, library)
 
@@ -413,6 +429,8 @@ Examples: ## xls_eval_ir_test
+load("//xls/build_rules:xls_build_defs.bzl", "xls_eval_ir_test")
+
 xls_eval_ir_test(name, src, input_validator, input_validator_expr, ir_eval_args, top)
 
@@ -462,6 +480,8 @@ Examples: ## xls_ir_equivalence_test
+load("//xls/build_rules:xls_build_defs.bzl", "xls_ir_equivalence_test")
+
 xls_ir_equivalence_test(name, expect_equivalent, ir_equivalence_args, src_0, src_1, top)
 
@@ -512,6 +532,8 @@ Examples: ## xls_ir_verilog_fdo
+load("//xls/build_rules:xls_build_defs.bzl", "xls_ir_verilog_fdo")
+
 xls_ir_verilog_fdo(name, src, outs, block_ir_file, codegen_args, codegen_options_proto,
                    module_sig_file, schedule_file, schedule_ir_file, scheduling_options_proto,
                    sta_tool, standard_cells, synthesizer_linear_interpolation_factor, verilog_file,
@@ -568,6 +590,8 @@ Example:
 ## xls_model_generation
 
 
+load("//xls/build_rules:xls_build_defs.bzl", "xls_model_generation")
+
 xls_model_generation(name, samples_file, standard_cells)
 
@@ -608,7 +632,9 @@ currently produced should be considered INCOMPLETE. ## cc_xls_ir_jit_wrapper
-cc_xls_ir_jit_wrapper(name, src, jit_wrapper_args, wrapper_type, top, kwargs)
+load("//xls/build_rules:xls_build_defs.bzl", "cc_xls_ir_jit_wrapper")
+
+cc_xls_ir_jit_wrapper(name, src, jit_wrapper_args, wrapper_type, top, **kwargs)
 
Invokes the JIT wrapper generator and compiles the result as a cc_library. @@ -636,6 +662,8 @@ identical to this macro. ## get_mangled_ir_symbol
+load("//xls/build_rules:xls_build_defs.bzl", "get_mangled_ir_symbol")
+
 get_mangled_ir_symbol(module_name, function_name, parametric_values, is_implicit_token,
                       is_proc_next)
 
@@ -669,8 +697,10 @@ The "mangled" symbol string. ## xls_benchmark_ir
+load("//xls/build_rules:xls_build_defs.bzl", "xls_benchmark_ir")
+
 xls_benchmark_ir(name, src, synthesize, codegen_args, benchmark_ir_args, standard_cells, tags,
-                 ir_tags, synth_tags, kwargs)
+                 ir_tags, synth_tags, **kwargs)
 
Executes the benchmark tool on an IR file. @@ -741,6 +771,8 @@ Examples: ## xls_dslx_cpp_type_library
+load("//xls/build_rules:xls_build_defs.bzl", "xls_dslx_cpp_type_library")
+
 xls_dslx_cpp_type_library(name, src, deps, namespace)
 
@@ -766,6 +798,8 @@ a cc_library with its target name identical to this macro. ## xls_dslx_fmt_test
+load("//xls/build_rules:xls_build_defs.bzl", "xls_dslx_fmt_test")
+
 xls_dslx_fmt_test(name, src, opportunistic_postcondition)
 
@@ -786,8 +820,10 @@ Creates a test target that confirms `src` is auto-formatted. ## xls_dslx_ir
+load("//xls/build_rules:xls_build_defs.bzl", "xls_dslx_ir")
+
 xls_dslx_ir(name, dslx_top, srcs, deps, library, ir_conv_args, enable_generated_file,
-            enable_presubmit_generated_file, kwargs)
+            enable_presubmit_generated_file, **kwargs)
 
A macro that instantiates a build rule converting a DSLX source file to an IR file. @@ -832,8 +868,10 @@ An IR conversion with a top entity defined. ## xls_dslx_opt_ir
+load("//xls/build_rules:xls_build_defs.bzl", "xls_dslx_opt_ir")
+
 xls_dslx_opt_ir(name, dslx_top, srcs, deps, library, ir_conv_args, opt_ir_args,
-                enable_generated_file, enable_presubmit_generated_file, kwargs)
+                enable_generated_file, enable_presubmit_generated_file, **kwargs)
 
A macro that instantiates a build rule generating an optimized IR file from a DSLX source file. @@ -885,8 +923,10 @@ Examples: ## xls_dslx_verilog
+load("//xls/build_rules:xls_build_defs.bzl", "xls_dslx_verilog")
+
 xls_dslx_verilog(name, dslx_top, verilog_file, srcs, deps, library, ir_conv_args, opt_ir_args,
-                 codegen_args, enable_generated_file, enable_presubmit_generated_file, kwargs)
+                 codegen_args, enable_generated_file, enable_presubmit_generated_file, **kwargs)
 
A macro that instantiates a build rule generating a Verilog file from a DSLX source file and tests the build. @@ -944,6 +984,8 @@ Examples: ## xls_ir_cc_library
+load("//xls/build_rules:xls_build_defs.bzl", "xls_ir_cc_library")
+
 xls_ir_cc_library(name, src, top, namespaces)
 
@@ -985,8 +1027,10 @@ This will produce a cc_library that will execute the fn `bar` from the ## xls_ir_opt_ir
+load("//xls/build_rules:xls_build_defs.bzl", "xls_ir_opt_ir")
+
 xls_ir_opt_ir(name, src, opt_ir_args, enable_generated_file, enable_presubmit_generated_file,
-              debug_srcs, kwargs)
+              debug_srcs, **kwargs)
 
A macro that instantiates a build rule optimizing an IR file. @@ -1038,9 +1082,11 @@ Examples: ## xls_ir_verilog
+load("//xls/build_rules:xls_build_defs.bzl", "xls_ir_verilog")
+
 xls_ir_verilog(name, src, verilog_file, codegen_args, codegen_options_proto,
                scheduling_options_proto, enable_generated_file, enable_presubmit_generated_file,
-               kwargs)
+               **kwargs)
 
A macro that instantiates a build rule generating a Verilog file from an IR file and tests the build. @@ -1084,7 +1130,9 @@ Example: ## xls_synthesis_metrics
-xls_synthesis_metrics(name, srcs, kwargs)
+load("//xls/build_rules:xls_build_defs.bzl", "xls_synthesis_metrics")
+
+xls_synthesis_metrics(name, srcs, **kwargs)
 
Gather per-pipeline-stage metrics from log files. diff --git a/xls/contrib/xlscc/bazel_rules_macros.md b/xls/contrib/xlscc/bazel_rules_macros.md index 675eca0ff1..a94a2523ce 100755 --- a/xls/contrib/xlscc/bazel_rules_macros.md +++ b/xls/contrib/xlscc/bazel_rules_macros.md @@ -10,8 +10,10 @@ ## xls_cc_ir
+load("//xls/contrib/xlscc/build_rules:xlscc_build_defs.bzl", "xls_cc_ir")
+
 xls_cc_ir(name, src, block, block_pb_out, block_from_class, src_deps, xlscc_args,
-          enable_generated_file, enable_presubmit_generated_file, metadata_out, kwargs)
+          enable_generated_file, enable_presubmit_generated_file, metadata_out, **kwargs)
 
A macro that instantiates a build rule generating an IR file from a C/C++ source file. @@ -56,8 +58,10 @@ Examples: ## xls_cc_verilog
+load("//xls/contrib/xlscc/build_rules:xlscc_build_defs.bzl", "xls_cc_verilog")
+
 xls_cc_verilog(name, src, block, verilog_file, src_deps, xlscc_args, opt_ir_args, codegen_args,
-               enable_generated_file, enable_presubmit_generated_file, kwargs)
+               enable_generated_file, enable_presubmit_generated_file, **kwargs)
 
A macro that instantiates a build rule generating a Verilog file from a C/C++ source file.