diff --git a/verilog/dot11.v b/verilog/dot11.v
index 04b447a..ed32094 100644
--- a/verilog/dot11.v
+++ b/verilog/dot11.v
@@ -19,12 +19,12 @@ module dot11 (
     //input [31:0] set_data,
     
     // add ports for register based inputs
-    input [10:0] power_thres,
+    input signed [10:0] power_thres,
     input [31:0] min_plateau,
     input threshold_scale,
 
     // INPUT: RSSI
-    input [10:0] rssi_half_db,
+    input signed [10:0] rssi_half_db,
     // INPUT: I/Q sample
     input [31:0] sample_in,
     input sample_in_strobe,