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RVM23 Profiles

Table of Contents
Warning
This document is in the development state.

Do not use for implementations. Assume everything can change.

Initial draft version, in progress

1. RVM23 Profiles

The RMV23 profile is intended for microcontrollers, with the goal of simplifying the demands on the software ecosystem particularly toolchains and library suppliers.

The RVM23 profile only specifies unprivileged ISA features. ISA features related to interrupt and exception handling or privileged execution are not included as these are often highly platform-specific. The separate RVM-CSI effort is tackling source-code level portability for certain platform-level features.

A non-goal of RVM23 is to provide maximum flexibility for microcontroller developers. Maximim flexibility can already be achieved using individual RISC-V extensions. The goal of RVM23 is mandate a common set of standard extensions to simplify software support.

1.1. RVM23U32

RVM23U32 corresponds to a 32-bit address-space microcontroller.

Note
 Initially only 32b RVM profiles are defined, but a corresponding RVM64 profile can also be developed.

1.1.1. RVM23U32 Mandatory Base

RV32I is the mandatory base ISA for RVM23U32, and is little-endian.

Note
 A separate RV32ME profile uses RV32E as the base ISA.

As per the unprivileged architecture specification, the ecall instruction causes a requested trap to the execution environment.

Misaligned loads and stores might not be supported.

Note
 Software should not assume that misaligned loads and stores will work, or that all misaligned loads and stores will necessarily cause a trap.

1.1.2. RVM23U32 Mandatory Extensions

  • M Integer multiplication and division.

Note
 Mandating divide instructions versus only multiplies (Zmmul) is likely controversial, but RVM is not intended for the smallest possible microcontrollers, and including divide instructions reduces optionality.

  • Zba Address computation.

  • Zbb Basic bit manipulation.

  • Zbs Single-bit instructions.

  • Zicond Conditional Zeroing instructions.

  • Zihintpause

Note
 These are hints, so implementations are allowed to treat as NOPs.

  • Zihintntl

Note
 These are hints, so implementations are allowed to treat as NOPs.

  • Zce Code size extension. The jvt CSR must be writable and support the jump table mode.

Note
 Zce includes Zicsr. Whether and what support is mandated for jvt in the profile is a topic for discussion.

  • Zicbop Cache-Block Prefetch Operations.

Note
 These are hints, so implementations are allowed to treat as NOPs.

  • Zimop Maybe-Operations

  • Zcmop Compressed Maybe-Operations

Note
 Implementations can treat as NOPS.

1.1.3. RVM23U32 Optional Extensions

  • Zaamo Atomic instructions.

Note
 Many microcontroller systems will not have caches and so will naturally be able to support Zalrsc.

  • A Atomic instructions.

Note
 The assumption is that Zalrsc will not generally be implemented with Zaamo on a microcontroller, so is not made available as a separate option.

  • F Single-precision floating-point instructions.

Note
 This profile does not support Zfinx and related options. A similar set of profiles, tenatively named RVN, would define Zfinx systems.

  • D Double-precision floating-point instructions.

  • V Vector Extension.

  • P Packed-SIMD Extension

Note
 The P extension has not yet been frozen or ratified.

  • Zawrs Wait on reservation set.

Note
 Zawrs includes Zalrsc.

  • Zifencei Instruction-fetch fence instruction.

Note
 Zifencei is only an option because how instruction-cache coherence is maintained is considered a platform issue for microcontrollers.

  • Misaligned loads and stores may be supported.

  • Zicntr Basic counters.

  • Zihpm Hardware performance counters.

  • Zicbom Cache-Block Management Operations.

  • Zicboz Cache-Block Zero Operations.

  • Zicfisslp Shadow-stack and landing pads.

  • Zkt Data-independent execution time.

  • Zfa Additional scalar FP instructions.

  • Zfhmin Half-Precision Floating-point transfer and convert.

  • Zfh Half-precision floating-point instructions.

  • Zfbfmin Scalar BF16 FP conversions.

  • Zvfbfmin Vector BF16 FP conversions.

  • Zvfbfwma Vector BF16 widening mul-add.

  • Zbc Scalar carryless multiply.

  • Zve32x

  • Zve32f

  • Zve64x

  • Zve64f

  • Zve64d

  • Zvfhmin Vector FP16 conversion instructions.

  • Zvfh Vector FP16 instructions.

  • Zkn Scalar Crypto NIST Algorithms.

  • Zks Scalar Crypto ShangMi Algorithms.

  • Zkr Entropy CSR.

  • Zvkng Vector Crypto NIST Algorithms including GHASH.

  • Zvksg Vector Crypto ShangMi Algorithms including GHASH.

  • Zvbb Vector bitmanip extension.

  • Zvbc Vector carryless multiply.

  • Zvkg Vector GHASH instructions

  • Zvkn Vector Crypto NIST Algorithms

  • Zvks Vector Crypto ShangMi Algorithms

but where either of Zvkn or Zvks is implemented, either Zvbc or Zvkg must also be implemented.

Note
 Should probably define new Zvknc and Zvksc extensions to represent Zvknn + Zvbc and Zvsn + Zvbc respectively.

2. Glossary of ISA Extensions

The following unprivileged ISA extensions are defined in Volume I of the RISC-V Instruction Set Manual.

  • M Extension for Integer Multiplication and Division

  • A Extension for Atomic Memory Operations

  • F Extension for Single-Precision Floating-Point

  • D Extension for Double-Precision Floating-Point

  • Q Extension for Quad-Precision Floating-Point

  • C Extension for Compressed Instructions

  • Zifencei Instruction-Fetch Synchronization Extension

  • Zicsr Extension for Control and Status Register Access

  • Zicntr Extension for Basic Performance Counters

  • Zihpm Extension for Hardware Performance Counters

  • Zihintpause Pause Hint Extension

  • Zfh Extension for Half-Precision Floating-Point

  • Zfhmin Minimal Extension for Half-Precision Floating-Point

  • Zfinx Extension for Single-Precision Floating-Point in x-registers

  • Zdinx Extension for Double-Precision Floating-Point in x-registers

  • Zhinx Extension for Half-Precision Floating-Point in x-registers

  • Zhinxmin Minimal Extension for Half-Precision Floating-Point in x-registers

The following privileged ISA extensions are defined in Volume II of the RISC-V Instruction Set Manual.

  • Sv32 Page-based Virtual Memory Extension, 32-bit

  • Sv39 Page-based Virtual Memory Extension, 39-bit

  • Sv48 Page-based Virtual Memory Extension, 48-bit

  • Sv57 Page-based Virtual Memory Extension, 57-bit

  • Svpbmt, Page-Based Memory Types

  • Svnapot, NAPOT Translation Contiguity

  • Svinval, Fine-Grained Address-Translation Cache Invalidation

  • Hypervisor Extension

  • Sm1p11, Machine Architecture v1.11

  • Sm1p12, Machine Architecture v1.12

  • Ss1p11, Supervisor Architecture v1.11

  • Ss1p12, Supervisor Architecture v1.12

  • Ss1p13, Supervisor Architecture v1.13

The following extensions have not yet been incorporated into the RISC-V Instruction Set Manual; the hyperlinks lead to their separate specifications.