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bfxp.tex
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\chapter{RISC-V XBitfield Extension}
\label{bfxp}
This chapter describes the {\tt bfxp} and {\tt bfxpc} instructions that implement
bit-field extract and place operations with optional complement.
Because of the large immediate required for those instructions they are encoded
using a 48-bit instruction format.
{\it There are no standard instruction formats for 48-bit instructions yet, and
no RISC-V processors that support instructions $>32$ bits. The encodings listed
below are merely for demonstrating that there is sufficient encoding space in
48-bit opcode space to easily implement {\tt bfxp} and {\tt bfxpc}
instructions.}
This chapter also describes an ``XBitfield32'' extension that provides a compressed
encoding of {\tt bfxp} and {\tt bfxpc} that uses almost the entire major opcode
1111011 ({\it custom-3}).
{\it Note that we do not propose XBitfield32 as a standard extension. There
will never be a ZBitfield32 extension.}
\section{Bit-field extract and place ({\tt bfxp}, {\tt bfxpc})}
The bit-field extract and place instruction extracts a bitfield of length
{\tt len} starting at bit position {\tt start}, creates a new value with
the extraced bitfield at offset {\tt dest}, and fills the other bits
in the output with {\tt rs2}.
The bit-field extract and place complement instruction does the same thing,
but first complements {\tt rs1}.
Instruction words with $\texttt{start}+\texttt{len}>\textrm{XLEN}$ or
$\texttt{dest}+\texttt{len}>\textrm{XLEN}$ or $\texttt{len} = 0$ are
reserved for other instructions.
\input{bextcref-bfxp}
The assembler mnemonics for {\tt bfxp} and {\tt bfxpc} are as follows.
\begin{verbatim}
bfxp rd, rs1, rs2, start, len, dest
bfxpc rd, rs1, rs2, start, len, dest
\end{verbatim}
The {\tt bfxp}/{\tt bfxpc} instructions can be cleanly encoded using a 48-bit
instruction format. For example:
\begin{center}
\begin{tabular}{F@{}F@{}F@{}F@{}F@{}F@{}S@{}F@{}}
\instbitrange{47}{41} &
\instbitrange{40}{34} &
\instbitrange{33}{27} &
\instbitrange{26}{22} &
\instbitrange{21}{17} &
\instbitrange{16}{12} &
\instbitrange{11}{6} &
\instbitrange{5}{0} \\
\hline
\multicolumn{1}{|c|}{start} &
\multicolumn{1}{c|}{len} &
\multicolumn{1}{c|}{dest} &
\multicolumn{1}{c|}{rs2} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{OP-BFXP} &
\multicolumn{1}{c|}{011111} \\
\hline
\multicolumn{1}{|c|}{start} &
\multicolumn{1}{c|}{len} &
\multicolumn{1}{c|}{dest} &
\multicolumn{1}{c|}{rs2} &
\multicolumn{1}{c|}{rs1} &
\multicolumn{1}{c|}{rd} &
\multicolumn{1}{c|}{OP-BFXPC} &
\multicolumn{1}{c|}{011111} \\
\hline
7 & 7 & 7 & 5 & 5 & 5 & 6 & 6 \\
\end{tabular}
\end{center}
There are no standard instruction formats for 48-bit instructions yet, and no
RISC-V processors that support instructions $>32$ bits. Therefore the above
encoding merely serves the purpose of demonstrating that there is sufficient
encoding space in 48-bit opcode space to implement the instruction.
\section{XBitfield32 extension using compressed 32-bit encoding}
XBitfield32 proposes a compressed encoding of {\tt bfxp}/{\tt bfxpc} inside the
32-bit encoding space.
The compressed {\tt bfxp}/{\tt bfxpc} encoding has the following limitations:
\begin{itemize}
\item Uses almost an entire custom opcode ({\it custom-3}) because there is not
enough encoding space anywhere else in the 32-bit opcode space.
\item {\tt rs2} can only be {\tt x0 (zero)} or equal to {\tt rd}.
\item {\tt rs1} and {\tt rd} can only be in the range {\tt x8 ... x15}.
\item Only available on RV32/RV64.
\item {\tt len} can not be larger than 32.
\end{itemize}
In XBitfield32 {\tt bfxp}/{\tt bfxpc} occupy the {\it custom-3} major opcode:
\begin{center}
\begin{tabular}{M@{}F@{}R@{}W@{}F@{}O}
\instbitrange{31}{18} &
\instbitrange{17}{15} &
\instbitrange{14}{11} &
\multicolumn{1}{c}{\scriptsize 10} &
\instbitrange{9}{7} &
\instbitrange{6}{0} \\
\hline
\multicolumn{1}{|c|}{imm} &
\multicolumn{1}{c|}{rs1$'$} &
\multicolumn{1}{c|}{imm} &
\multicolumn{1}{c|}{rs2$^*$} &
\multicolumn{1}{c|}{rd$'$} &
\multicolumn{1}{c|}{1111011} \\
\hline
14 & 3 & 4 & 1 & 3 & 7 \\
\cline{1-1}
\cline{3-3}
\multicolumn{1}{c}{
\rotatebox{90}{\tt \ \ len[3]} % 31
\rotatebox{90}{\tt \ \ len[2]} % 30
\rotatebox{90}{\tt \ \ len[1]} % 29
\rotatebox{90}{\tt \ \ len[0]} % 28
\rotatebox{90}{\tt start[3]} % 27
\rotatebox{90}{\tt start[2]} % 26
\rotatebox{90}{\tt start[1]} % 25
\rotatebox{90}{\tt start[0]} % 24
\rotatebox{90}{\tt \ dest[5]} % 23
\rotatebox{90}{\tt \ dest[4]} % 22
\rotatebox{90}{\tt \ dest[3]} % 21
\rotatebox{90}{\tt \ dest[2]} % 20
\rotatebox{90}{\tt \ dest[1]} % 19
\rotatebox{90}{\tt \ dest[0]} % 18
} & &
\multicolumn{1}{c}{
\rotatebox{90}{\tt \ \ len[4]} % 12
\rotatebox{90}{\tt start[5]} % 14
\rotatebox{90}{\tt start[4]} % 13
\rotatebox{90}{\tt \ \ bfxpc} % 11
} & & &
\end{tabular}
\end{center}
With rs1$'$ and rd$'$ interpreted as in ``C'' opcodes
($\textrm{rs1} = \textrm{rs1$'$}+8$, $\textrm{rd} = \textrm{rd$'$}+8$),
and rs2$^* = 0$ encoding for $\textrm{rs2} = \textrm{x0 (zero)}$ and
rs2$^* = 1$ encoding for $\textrm{rs2} = \textrm{rd}$.
On RV64 $\texttt{len} = 0$ encodes for $\texttt{len} = 32$. On RV32
$\texttt{len} = 0$ is reserved.
The bits from {\tt start}, {\tt len}, and {\tt dest} are placed in the
immediate fields in a manner that aims at maximizing the usefulness of the
remaining brownfield in the {\it custom-3} opcode: On RV64 and RV32, if
instruction bits 14:12 are all set (funct3 = 111), then the instruction is
reserved if any of the bits 31:24 are set.