intro.tex

\chapter{Introduction}

This is the RISC-V XBitmanip Extension draft spec. Originally it was the
B-Extension draft spec, but the work group got dissolved for bureaucratic
reasons in November 2017.

It is currently an independently maintained document. We'd happily donate
it to the RISC-V foundation as starting point for a new B-Extension work
group, if there will be one.

\section{ISA Extension Proposal Design Criteria}

Any proposed changes to the ISA should be evaluated according to the following
criteria.

\begin{itemize}
\item
  Architecture Consistency: Decisions must be consistent with RISC-V
  philosophy. ISA changes should deviate as little as possible from
  existing RISC-V standards (such as instruction encodings), and should
  not re-implement features that are already found in the base
  specification or other extensions.
\item
  Threshold Metric: The proposal should provide a \emph{significant}
  savings in terms of clocks or instructions. As a heuristic, any
  proposal should replace at least four instructions. An instruction
  that only replaces three may be considered, but only if the frequency
  of use is very high and/or the implementation very cheap.
\item
  Data-Driven Value: Usage in real world applications, and corresponding
  benchmarks showing a performance increase, will contribute to the
  score of a proposal. A proposal will not be accepted on the merits of
  its \emph{theoretical} value alone, unless it is used in the real
  world.
\item
  Hardware Simplicity: Though instructions saved is the primary benefit,
  proposals that dramatically increase the hardware complexity and area,
  or are difficult to implement, should be penalized and given extra
  scrutiny. The final proposals should only be made if a test
  implementation can be produced.
\item
  Compiler Support: ISA changes that can be natively detected by the
  compiler, or are already used as intrinsics, will score higher than
  instructions which do not fit that criteria.
\end{itemize}

\section{B Extension Adoption Strategy}

The overall goal of this extension is pervasive adoption by minimizing
potential barriers and ensuring the instructions can be mapped to the
largest number of ops, either direct or pseudo, that are supported by
the most popular processors and compilers. By adding generic
instructions and taking advantage of the RISC-V base instructions that
already operate on bits, the minimal set of instructions need to be added
while at the same time enabling a rich of operations.

The instructions cover the four major categories of bit manipulation: Count,
Extract, Insert, Swap. The spec supports RV32, RV64, and RV128. ``Clever''
obscure and/or overly specific instructions are avoided in favor of more
straightforward, fast, generic ones.  Coordination with other emerging RISC-V
ISA extensions groups is required to ensure our instruction sets are
architecturally consistent.

\section{Next steps}

\begin{itemize}
\item
  Assign concrete instruction encodings so that we can start
  implementing the extension in processor cores and compilers.
\item
  Add support for this extension to processor cores and compilers
  so we can run quantitative evaluations on the instructions.
\item
  Create assembler snippets for common operations that do not map 1:1
  to any instruction in this spec, but can be implemented easily using
  clever combinations of the instructions. Add support for those snippets
  to compilers.
\end{itemize}