diff --git a/.github/workflows/Openwrt-AutoBuild.yml b/.github/workflows/Openwrt-AutoBuild.yml index 15c89c22df87..7fdef93ed05d 100644 --- a/.github/workflows/Openwrt-AutoBuild.yml +++ b/.github/workflows/Openwrt-AutoBuild.yml @@ -168,6 +168,9 @@ jobs: - name: Apply patches run: | cd openwrt + rm -rf target/linux/rockchip/patches-5.4/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz-for-NanoPi4.patch + rm -rf target/linux/rockchip/patches-5.10/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz-for-NanoPi4.patch + rm -rf target/linux/rockchip/patches-5.15/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz-for-NanoPi4.patch find "devices/common/patches" -type f ! -name 'china_mirrors.patch' -name '*.patch' -print0 | sort -z | xargs -I % -t -0 -n 1 sh -c "cat '%' | patch -d './' -p1 -E --forward" if [ -n "$(ls -A "devices/${{matrix.target}}/patches" 2>/dev/null)" ]; then find "devices/${{matrix.target}}/patches" -type f -name '*.patch' -print0 | sort -z | xargs -I % -t -0 -n 1 sh -c "cat '%' | patch -d './' -p1 -E --forward" @@ -325,7 +328,6 @@ jobs: - name: Upload firmware for release uses: softprops/action-gh-release@master continue-on-error: true - if: env.REPO_TOKEN && env.UPLOAD_FIRMWARE_FOR_RELEASE == 'true' env: GITHUB_TOKEN: ${{ secrets.REPO_TOKEN }} with: diff --git a/devices/rockchip_armv8/patches/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz-for-NanoPi4.patch b/devices/rockchip_armv8/patches/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz-for-NanoPi4.patch new file mode 100644 index 000000000000..cea911995f2a --- /dev/null +++ b/devices/rockchip_armv8/patches/992-rockchip-rk3399-overclock-to-2.2-1.8-GHz-for-NanoPi4.patch @@ -0,0 +1,182 @@ +From 04202df5cb497b1934c95211cf43784ef62245a4 Mon Sep 17 00:00:00 2001 +From: Tianling Shen +Date: Sat, 19 Dec 2020 12:42:27 +0000 +Subject: [PATCH] rockchip: rk3399: overclock to 2.2/1.8 GHz for NanoPi4 devices + +It's stable enough to overclock cpu frequency to 2.2/1.8 GHz, +and for better performance. + +Signed-off-by: Tianling Shen +Co-authored-by: gzelvis +--- + .../boot/dts/rockchip/rk3399-nanopi4-opp.dtsi | 156 ++++++++++++++++++ + .../boot/dts/rockchip/rk3399-nanopi4.dtsi | 2 +- + 2 files changed, 157 insertions(+), 1 deletion(-) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopi4-opp.dtsi + +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4-opp.dtsi +@@ -0,0 +1,152 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd ++ * ++ * Copyright (c) 2020 Tianling Shen ++ * Copyright (c) 2020 gzelvis ++ */ ++ ++/ { ++ cluster0_opp: opp-table0 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp00 { ++ opp-hz = /bits/ 64 <408000000>; ++ opp-microvolt = <800000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp01 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <800000>; ++ }; ++ opp02 { ++ opp-hz = /bits/ 64 <816000000>; ++ opp-microvolt = <850000>; ++ }; ++ opp03 { ++ opp-hz = /bits/ 64 <1008000000>; ++ opp-microvolt = <925000>; ++ }; ++ opp04 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <1000000>; ++ }; ++ opp05 { ++ opp-hz = /bits/ 64 <1416000000>; ++ opp-microvolt = <1125000>; ++ }; ++ opp06 { ++ opp-hz = /bits/ 64 <1608000000>; ++ opp-microvolt = <1225000>; ++ }; ++ opp07 { ++ opp-hz = /bits/ 64 <1800000000>; ++ opp-microvolt = <1275000>; ++ }; ++ }; ++ ++ cluster1_opp: opp-table1 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ opp00 { ++ opp-hz = /bits/ 64 <408000000>; ++ opp-microvolt = <800000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp01 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <800000>; ++ }; ++ opp02 { ++ opp-hz = /bits/ 64 <816000000>; ++ opp-microvolt = <825000>; ++ }; ++ opp03 { ++ opp-hz = /bits/ 64 <1008000000>; ++ opp-microvolt = <875000>; ++ }; ++ opp04 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <950000>; ++ }; ++ opp05 { ++ opp-hz = /bits/ 64 <1416000000>; ++ opp-microvolt = <1025000>; ++ }; ++ opp06 { ++ opp-hz = /bits/ 64 <1608000000>; ++ opp-microvolt = <1100000>; ++ }; ++ opp07 { ++ opp-hz = /bits/ 64 <1800000000>; ++ opp-microvolt = <1200000>; ++ }; ++ opp08 { ++ opp-hz = /bits/ 64 <2016000000>; ++ opp-microvolt = <1250000>; ++ }; ++ opp09 { ++ opp-hz = /bits/ 64 <2208000000>; ++ opp-microvolt = <1325000>; ++ }; ++ }; ++ ++ gpu_opp_table: opp-table2 { ++ compatible = "operating-points-v2"; ++ ++ opp00 { ++ opp-hz = /bits/ 64 <200000000>; ++ opp-microvolt = <800000>; ++ }; ++ opp01 { ++ opp-hz = /bits/ 64 <297000000>; ++ opp-microvolt = <800000>; ++ }; ++ opp02 { ++ opp-hz = /bits/ 64 <400000000>; ++ opp-microvolt = <825000>; ++ }; ++ opp03 { ++ opp-hz = /bits/ 64 <500000000>; ++ opp-microvolt = <875000>; ++ }; ++ opp04 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <925000>; ++ }; ++ opp05 { ++ opp-hz = /bits/ 64 <800000000>; ++ opp-microvolt = <1100000>; ++ }; ++ }; ++}; ++ ++&cpu_l0 { ++ operating-points-v2 = <&cluster0_opp>; ++}; ++ ++&cpu_l1 { ++ operating-points-v2 = <&cluster0_opp>; ++}; ++ ++&cpu_l2 { ++ operating-points-v2 = <&cluster0_opp>; ++}; ++ ++&cpu_l3 { ++ operating-points-v2 = <&cluster0_opp>; ++}; ++ ++&cpu_b0 { ++ operating-points-v2 = <&cluster1_opp>; ++}; ++ ++&cpu_b1 { ++ operating-points-v2 = <&cluster1_opp>; ++}; ++ ++&gpu { ++ operating-points-v2 = <&gpu_opp_table>; ++}; +--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi +@@ -14,7 +14,7 @@ + /dts-v1/; + #include + #include "rk3399.dtsi" +-#include "rk3399-opp.dtsi" ++#include "rk3399-nanopi4-opp.dtsi" + + / { + aliases { \ No newline at end of file diff --git a/devices/rockchip_armv8/patches/993-rockchip-rk3399-overclock-to-2.2-1.8-GHz-for-DoorNet2.patch b/devices/rockchip_armv8/patches/993-rockchip-rk3399-overclock-to-2.2-1.8-GHz-for-DoorNet2.patch new file mode 100644 index 000000000000..2905faa10932 --- /dev/null +++ b/devices/rockchip_armv8/patches/993-rockchip-rk3399-overclock-to-2.2-1.8-GHz-for-DoorNet2.patch @@ -0,0 +1,468 @@ +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3399-doornet2-opp.dtsi +@@ -0,0 +1,328 @@ ++#include "rk3399-sched-energy.dtsi" ++ ++/ { ++ cluster0_opp: opp-table0 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ rockchip,temp-hysteresis = <5000>; ++ rockchip,low-temp = <0>; ++ rockchip,low-temp-min-volt = <900000>; ++ ++ nvmem-cells = <&cpul_leakage>; ++ nvmem-cell-names = "cpu_leakage"; ++ ++ rockchip,pvtm-voltage-sel = < ++ 0 143500 0 ++ 143501 148500 1 ++ 148501 152000 2 ++ 152001 999999 3 ++ >; ++ rockchip,pvtm-freq = <408000>; ++ rockchip,pvtm-volt = <1000000>; ++ rockchip,pvtm-ch = <0 0>; ++ rockchip,pvtm-sample-time = <1000>; ++ rockchip,pvtm-number = <10>; ++ rockchip,pvtm-error = <1000>; ++ rockchip,pvtm-ref-temp = <41>; ++ rockchip,pvtm-temp-prop = <115 66>; ++ rockchip,thermal-zone = "soc-thermal"; ++ ++ opp-408000000 { ++ opp-hz = /bits/ 64 <408000000>; ++ opp-microvolt = <800000 800000 1250000>; ++ opp-microvolt-L0 = <800000 800000 1250000>; ++ opp-microvolt-L1 = <800000 800000 1250000>; ++ opp-microvolt-L2 = <800000 800000 1250000>; ++ opp-microvolt-L3 = <800000 800000 1250000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-600000000 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <800000 800000 1250000>; ++ opp-microvolt-L0 = <800000 800000 1250000>; ++ opp-microvolt-L1 = <800000 800000 1250000>; ++ opp-microvolt-L2 = <800000 800000 1250000>; ++ opp-microvolt-L3 = <800000 800000 1250000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-816000000 { ++ opp-hz = /bits/ 64 <816000000>; ++ opp-microvolt = <850000 850000 1250000>; ++ opp-microvolt-L0 = <850000 850000 1250000>; ++ opp-microvolt-L1 = <825000 825000 1250000>; ++ opp-microvolt-L2 = <800000 800000 1250000>; ++ opp-microvolt-L3 = <800000 800000 1250000>; ++ clock-latency-ns = <40000>; ++ opp-suspend; ++ }; ++ opp-1008000000 { ++ opp-hz = /bits/ 64 <1008000000>; ++ opp-microvolt = <925000 925000 1250000>; ++ opp-microvolt-L0 = <925000 925000 1250000>; ++ opp-microvolt-L1 = <900000 900000 1250000>; ++ opp-microvolt-L2 = <875000 875000 1250000>; ++ opp-microvolt-L3 = <850000 850000 1250000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1200000000 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <1000000 1000000 1250000>; ++ opp-microvolt-L0 = <1000000 1000000 1250000>; ++ opp-microvolt-L1 = <975000 975000 1250000>; ++ opp-microvolt-L2 = <950000 950000 1250000>; ++ opp-microvolt-L3 = <925000 925000 1250000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1416000000 { ++ opp-hz = /bits/ 64 <1416000000>; ++ opp-microvolt = <1175000 1175000 1250000>; ++ opp-microvolt-L0 = <1175000 1175000 1250000>; ++ opp-microvolt-L1 = <1100000 1100000 1250000>; ++ opp-microvolt-L2 = <1050000 1050000 1250000>; ++ opp-microvolt-L3 = <975000 975000 1250000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1608000000 { ++ opp-hz = /bits/ 64 <1608000000>; ++ opp-microvolt = <1200000 1200000 1250000>; ++ opp-microvolt-L0 = <1200000 1200000 1250000>; ++ opp-microvolt-L1 = <1175000 1175000 1250000>; ++ opp-microvolt-L2 = <1125000 1125000 1250000>; ++ opp-microvolt-L3 = <1100000 1100000 1250000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1800000000 { ++ opp-hz = /bits/ 64 <1800000000>; ++ opp-microvolt = <1250000 1250000 1250000>; ++ opp-microvolt-L0 = <1250000 1250000 1250000>; ++ opp-microvolt-L1 = <1200000 1200000 1250000>; ++ opp-microvolt-L2 = <1175000 1175000 1250000>; ++ opp-microvolt-L3 = <1125000 1125000 1250000>; ++ clock-latency-ns = <40000>; ++ }; ++ }; ++ ++ cluster1_opp: opp-table1 { ++ compatible = "operating-points-v2"; ++ opp-shared; ++ ++ rockchip,temp-hysteresis = <5000>; ++ rockchip,low-temp = <0>; ++ rockchip,low-temp-min-volt = <900000>; ++ ++ nvmem-cells = <&cpub_leakage>; ++ nvmem-cell-names = "cpu_leakage"; ++ ++ rockchip,pvtm-voltage-sel = < ++ 0 149000 0 ++ 149001 155000 1 ++ 155001 160000 2 ++ 160001 999999 3 ++ >; ++ rockchip,pvtm-freq = <408000>; ++ rockchip,pvtm-volt = <1000000>; ++ rockchip,pvtm-ch = <1 0>; ++ rockchip,pvtm-sample-time = <1000>; ++ rockchip,pvtm-number = <10>; ++ rockchip,pvtm-error = <1000>; ++ rockchip,pvtm-ref-temp = <41>; ++ rockchip,pvtm-temp-prop = <71 35>; ++ rockchip,thermal-zone = "soc-thermal"; ++ ++ opp-408000000 { ++ opp-hz = /bits/ 64 <408000000>; ++ opp-microvolt = <800000 800000 1275000>; ++ opp-microvolt-L0 = <800000 800000 1275000>; ++ opp-microvolt-L1 = <800000 800000 1275000>; ++ opp-microvolt-L2 = <800000 800000 1275000>; ++ opp-microvolt-L3 = <800000 800000 1275000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-600000000 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <800000 800000 1275000>; ++ opp-microvolt-L0 = <800000 800000 1275000>; ++ opp-microvolt-L1 = <800000 800000 1275000>; ++ opp-microvolt-L2 = <800000 800000 1275000>; ++ opp-microvolt-L3 = <800000 800000 1275000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-816000000 { ++ opp-hz = /bits/ 64 <816000000>; ++ opp-microvolt = <825000 825000 1275000>; ++ opp-microvolt-L0 = <825000 825000 1275000>; ++ opp-microvolt-L1 = <825000 825000 1275000>; ++ opp-microvolt-L2 = <800000 800000 1275000>; ++ opp-microvolt-L3 = <800000 800000 1275000>; ++ clock-latency-ns = <40000>; ++ opp-suspend; ++ }; ++ opp-1008000000 { ++ opp-hz = /bits/ 64 <1008000000>; ++ opp-microvolt = <875000 875000 1275000>; ++ opp-microvolt-L0 = <875000 875000 1275000>; ++ opp-microvolt-L1 = <850000 850000 1275000>; ++ opp-microvolt-L2 = <850000 850000 1275000>; ++ opp-microvolt-L3 = <850000 850000 1275000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1200000000 { ++ opp-hz = /bits/ 64 <1200000000>; ++ opp-microvolt = <950000 950000 1275000>; ++ opp-microvolt-L0 = <950000 950000 1275000>; ++ opp-microvolt-L1 = <925000 925000 1275000>; ++ opp-microvolt-L2 = <900000 900000 1275000>; ++ opp-microvolt-L3 = <875000 875000 1275000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1416000000 { ++ opp-hz = /bits/ 64 <1416000000>; ++ opp-microvolt = <1025000 1025000 1275000>; ++ opp-microvolt-L0 = <1025000 1025000 1275000>; ++ opp-microvolt-L1 = <1000000 1000000 1275000>; ++ opp-microvolt-L2 = <1000000 1000000 1275000>; ++ opp-microvolt-L3 = <975000 975000 1275000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1608000000 { ++ opp-hz = /bits/ 64 <1608000000>; ++ opp-microvolt = <1100000 1100000 1275000>; ++ opp-microvolt-L0 = <1100000 1100000 1275000>; ++ opp-microvolt-L1 = <1075000 1075000 1275000>; ++ opp-microvolt-L2 = <1050000 1050000 1275000>; ++ opp-microvolt-L3 = <1025000 1025000 1275000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-1800000000 { ++ opp-hz = /bits/ 64 <1800000000>; ++ opp-microvolt = <1200000 1200000 1275000>; ++ opp-microvolt-L0 = <1200000 1200000 1275000>; ++ opp-microvolt-L1 = <1175000 1175000 1275000>; ++ opp-microvolt-L2 = <1150000 1150000 1275000>; ++ opp-microvolt-L3 = <1125000 1125000 1275000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-2016000000 { ++ opp-hz = /bits/ 64 <2016000000>; ++ opp-microvolt = <1250000 1250000 1275000>; ++ opp-microvolt-L0 = <1250000 1250000 1275000>; ++ opp-microvolt-L1 = <1200000 1200000 1275000>; ++ opp-microvolt-L2 = <1175000 1175000 1275000>; ++ opp-microvolt-L3 = <1150000 1150000 1275000>; ++ clock-latency-ns = <40000>; ++ }; ++ opp-2208000000 { ++ opp-hz = /bits/ 64 <2208000000>; ++ opp-microvolt = <1275000 1275000 1275000>; ++ opp-microvolt-L0 = <1275000 1275000 1275000>; ++ opp-microvolt-L1 = <1250000 1250000 1275000>; ++ opp-microvolt-L2 = <1200000 1200000 1275000>; ++ opp-microvolt-L3 = <1175000 1175000 1275000>; ++ clock-latency-ns = <40000>; ++ }; ++ }; ++ ++ gpu_opp_table: opp-table2 { ++ compatible = "operating-points-v2"; ++ ++ rockchip,thermal-zone = "soc-thermal"; ++ rockchip,temp-hysteresis = <5000>; ++ rockchip,low-temp = <0>; ++ rockchip,low-temp-min-volt = <900000>; ++ ++ nvmem-cells = <&gpu_leakage>; ++ nvmem-cell-names = "gpu_leakage"; ++ ++ rockchip,pvtm-voltage-sel = < ++ 0 121000 0 ++ 121001 125500 1 ++ 125501 128500 2 ++ 128501 999999 3 ++ >; ++ rockchip,pvtm-freq = <200000>; ++ rockchip,pvtm-volt = <900000>; ++ rockchip,pvtm-ch = <3 0>; ++ rockchip,pvtm-sample-time = <1000>; ++ rockchip,pvtm-number = <10>; ++ rockchip,pvtm-error = <1000>; ++ rockchip,pvtm-ref-temp = <41>; ++ rockchip,pvtm-temp-prop = <46 12>; ++ rockchip,pvtm-thermal-zone = "gpu-thermal"; ++ ++ opp-200000000 { ++ opp-hz = /bits/ 64 <200000000>; ++ opp-microvolt = <800000>; ++ opp-microvolt-L0 = <800000>; ++ opp-microvolt-L1 = <800000>; ++ opp-microvolt-L2 = <800000>; ++ opp-microvolt-L3 = <800000>; ++ }; ++ opp-300000000 { ++ opp-hz = /bits/ 64 <300000000>; ++ opp-microvolt = <800000>; ++ opp-microvolt-L0 = <800000>; ++ opp-microvolt-L1 = <800000>; ++ opp-microvolt-L2 = <800000>; ++ opp-microvolt-L3 = <800000>; ++ }; ++ opp-400000000 { ++ opp-hz = /bits/ 64 <400000000>; ++ opp-microvolt = <825000>; ++ opp-microvolt-L0 = <825000>; ++ opp-microvolt-L1 = <825000>; ++ opp-microvolt-L2 = <800000>; ++ opp-microvolt-L3 = <800000>; ++ }; ++ opp-600000000 { ++ opp-hz = /bits/ 64 <600000000>; ++ opp-microvolt = <925000>; ++ opp-microvolt-L0 = <925000>; ++ opp-microvolt-L1 = <925000>; ++ opp-microvolt-L2 = <900000>; ++ opp-microvolt-L3 = <900000>; ++ }; ++ opp-800000000 { ++ opp-hz = /bits/ 64 <800000000>; ++ opp-microvolt = <1100000>; ++ opp-microvolt-L0 = <1100000>; ++ opp-microvolt-L1 = <1075000>; ++ opp-microvolt-L2 = <1050000>; ++ opp-microvolt-L3 = <1025000>; ++ }; ++ }; ++}; ++ ++&cpu_l0 { ++ operating-points-v2 = <&cluster0_opp>; ++ sched-energy-costs = <&RK3399_CPU_COST_0 &RK3399_CLUSTER_COST_0>; ++}; ++ ++&cpu_l1 { ++ operating-points-v2 = <&cluster0_opp>; ++ sched-energy-costs = <&RK3399_CPU_COST_0 &RK3399_CLUSTER_COST_0>; ++}; ++ ++&cpu_l2 { ++ operating-points-v2 = <&cluster0_opp>; ++ sched-energy-costs = <&RK3399_CPU_COST_0 &RK3399_CLUSTER_COST_0>; ++}; ++ ++&cpu_l3 { ++ operating-points-v2 = <&cluster0_opp>; ++ sched-energy-costs = <&RK3399_CPU_COST_0 &RK3399_CLUSTER_COST_0>; ++}; ++ ++&cpu_b0 { ++ operating-points-v2 = <&cluster1_opp>; ++ sched-energy-costs = <&RK3399_CPU_COST_1 &RK3399_CLUSTER_COST_1>; ++}; ++ ++&cpu_b1 { ++ operating-points-v2 = <&cluster1_opp>; ++ sched-energy-costs = <&RK3399_CPU_COST_1 &RK3399_CLUSTER_COST_1>; ++}; ++ ++&gpu { ++ operating-points-v2 = <&gpu_opp_table>; ++}; + +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3399-sched-energy.dtsi +@@ -0,0 +1,121 @@ ++/* ++ * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPL or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This library is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This library is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++/ { ++ energy-costs { ++ RK3399_CPU_COST_0: rk3399-core-cost0 { ++ busy-cost-data = < ++ 108 46 /* 408M */ ++ 159 67 /* 600M */ ++ 216 90 /* 816M */ ++ 267 120 /* 1008M */ ++ 318 153 /* 1200M */ ++ 375 198 /* 1416M */ ++ 401 222 /* 1512M */ ++ >; ++ idle-cost-data = < ++ 6 ++ 6 ++ 0 ++ 0 ++ >; ++ }; ++ ++ RK3399_CPU_COST_1: rk3399-core-cost1 { ++ busy-cost-data = < ++ 210 129 /* 408MHz */ ++ 308 184 /* 600MHz */ ++ 419 246 /* 816MHz */ ++ 518 335 /* 1008MHz */ ++ 617 428 /* 1200MHz */ ++ 728 573 /* 1416MHz */ ++ 827 724 /* 1608MHz */ ++ 925 900 /* 1800MHz */ ++ 1024 1108 /* 1992MHz */ ++ >; ++ idle-cost-data = < ++ 15 ++ 15 ++ 0 ++ 0 ++ >; ++ }; ++ ++ RK3399_CLUSTER_COST_0: rk3399-cluster-cost0 { ++ busy-cost-data = < ++ 108 46 /* 408M */ ++ 159 67 /* 600M */ ++ 216 90 /* 816M */ ++ 267 120 /* 1008M */ ++ 318 153 /* 1200M */ ++ 375 198 /* 1416M */ ++ 401 222 /* 1512M */ ++ >; ++ idle-cost-data = < ++ 56 ++ 56 ++ 56 ++ 56 ++ >; ++ }; ++ ++ RK3399_CLUSTER_COST_1: rk3399-cluster-cost1 { ++ busy-cost-data = < ++ 210 129 /* 408MHz */ ++ 308 184 /* 600MHz */ ++ 419 246 /* 816MHz */ ++ 518 335 /* 1008MHz */ ++ 617 428 /* 1200MHz */ ++ 728 573 /* 1416MHz */ ++ 827 724 /* 1608MHz */ ++ 925 900 /* 1800MHz */ ++ 1024 1108 /* 1992MHz */ ++ >; ++ idle-cost-data = < ++ 65 ++ 65 ++ 65 ++ 65 ++ >; ++ }; ++ }; ++}; + +--- a/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3399-doornet2.dtsi +@@ -3,7 +3,7 @@ + /dts-v1/; + #include + #include "rk3399.dtsi" +-#include "rk3399-opp.dtsi" ++#include "rk3399-doornet2-opp.dtsi" + + / { + chosen { \ No newline at end of file