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1.patch
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From 9229c54b0ab8540070b16708ffecb8cf3229a444 Mon Sep 17 00:00:00 2001
From: Ps3itaTeam <[email protected]>
Date: Thu, 7 Feb 2019 13:46:49 +0100
Subject: [PATCH] Added ps4 patch
---
arch/x86/Kconfig | 8 +
arch/x86/include/asm/msi.h | 2 +
arch/x86/include/asm/ps4.h | 60 ++
arch/x86/include/asm/setup.h | 6 +
arch/x86/include/uapi/asm/bootparam.h | 1 +
arch/x86/kernel/apic/msi.c | 2 +-
arch/x86/kernel/head64.c | 7 +-
arch/x86/platform/Makefile | 1 +
arch/x86/platform/ps4/Makefile | 1 +
arch/x86/platform/ps4/calibrate.c | 116 +++
arch/x86/platform/ps4/ps4.c | 76 ++
drivers/Makefile | 1 +
drivers/ata/ahci.c | 42 +-
drivers/gpu/drm/amd/amdgpu/Makefile | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 2 +
.../gpu/drm/amd/amdgpu/amdgpu_connectors.c | 44 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 19 +
drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c | 19 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 6 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 2 +
drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 9 +-
.../gpu/drm/amd/amdgpu/atombios_encoders.c | 7 +-
drivers/gpu/drm/amd/amdgpu/cik.c | 318 ++++++++
drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 55 +-
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 44 +-
drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 2 +
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 738 ++++++++++++++++-
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 19 +-
drivers/gpu/drm/amd/amdgpu/ps4_bridge.c | 758 +++++++++++++++++
drivers/gpu/drm/amd/include/amd_shared.h | 3 +-
.../drm/amd/include/asic_reg/gmc/gmc_7_1_d.h | 28 +
drivers/gpu/drm/drm_pci.c | 2 +-
drivers/gpu/drm/radeon/Makefile | 2 +
drivers/gpu/drm/radeon/atombios_encoders.c | 2 +-
drivers/gpu/drm/radeon/cik.c | 765 ++++++++++++++++--
drivers/gpu/drm/radeon/cik_sdma.c | 47 +-
drivers/gpu/drm/radeon/cikd.h | 28 +-
drivers/gpu/drm/radeon/ps4_bridge.c | 756 +++++++++++++++++
drivers/gpu/drm/radeon/radeon.h | 3 +-
drivers/gpu/drm/radeon/radeon_asic.c | 14 +-
drivers/gpu/drm/radeon/radeon_audio.c | 7 +-
drivers/gpu/drm/radeon/radeon_connectors.c | 50 +-
drivers/gpu/drm/radeon/radeon_device.c | 1 +
drivers/gpu/drm/radeon/radeon_display.c | 2 +-
drivers/gpu/drm/radeon/radeon_drv.c | 16 +-
drivers/gpu/drm/radeon/radeon_encoders.c | 18 +
drivers/gpu/drm/radeon/radeon_family.h | 1 +
drivers/gpu/drm/radeon/radeon_ib.c | 2 +-
drivers/gpu/drm/radeon/radeon_pm.c | 1 +
drivers/gpu/drm/radeon/radeon_ucode.h | 3 +
drivers/gpu/drm/radeon/radeon_uvd.c | 1 +
drivers/gpu/drm/radeon/radeon_vce.c | 1 +
drivers/iommu/amd_iommu_init.c | 6 +-
drivers/mmc/host/sdhci-pci-core.c | 72 +-
drivers/mmc/host/sdhci-pci.h | 3 +-
drivers/net/ethernet/marvell/sky2.c | 139 +++-
drivers/net/ethernet/marvell/sky2.h | 4 +-
drivers/pci/probe.c | 17 +-
drivers/ps4/Makefile | 9 +
drivers/ps4/aeolia.h | 172 ++++
drivers/ps4/icc/i2c.c | 156 ++++
drivers/ps4/ps4-apcie-icc.c | 602 ++++++++++++++
drivers/ps4/ps4-apcie-pwrbutton.c | 69 ++
drivers/ps4/ps4-apcie-uart.c | 67 ++
drivers/ps4/ps4-apcie.c | 534 ++++++++++++
drivers/usb/host/Kconfig | 7 +
drivers/usb/host/Makefile | 1 +
drivers/usb/host/xhci-aeolia.c | 304 +++++++
drivers/usb/host/xhci.c | 31 +-
drivers/usb/host/xhci.h | 1 +
include/linux/pci_ids.h | 24 +
75 files changed, 6146 insertions(+), 205 deletions(-)
create mode 100644 arch/x86/include/asm/ps4.h
create mode 100644 arch/x86/platform/ps4/Makefile
create mode 100644 arch/x86/platform/ps4/calibrate.c
create mode 100644 arch/x86/platform/ps4/ps4.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/ps4_bridge.c
create mode 100644 drivers/gpu/drm/radeon/ps4_bridge.c
create mode 100644 drivers/ps4/Makefile
create mode 100644 drivers/ps4/aeolia.h
create mode 100644 drivers/ps4/icc/i2c.c
create mode 100644 drivers/ps4/ps4-apcie-icc.c
create mode 100644 drivers/ps4/ps4-apcie-pwrbutton.c
create mode 100644 drivers/ps4/ps4-apcie-uart.c
create mode 100644 drivers/ps4/ps4-apcie.c
create mode 100644 drivers/usb/host/xhci-aeolia.c
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 4f393eb9745f38..a357714839587d 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -507,6 +507,14 @@ config X86_NUMACHIP
Adds support for Numascale NumaChip large-SMP systems. Needed to
enable more than ~168 cores.
If you don't have one of these, you should say N here.
+
+config X86_PS4
+ bool "Sony PlayStation 4"
+ depends on X86_64
+ depends on X86_EXTENDED_PLATFORM
+ depends on PCI
+ ---help---
+ Select to include support for the Sony PlayStation 4 game console.
config X86_VSMP
bool "ScaleMP vSMP"
diff --git a/arch/x86/include/asm/msi.h b/arch/x86/include/asm/msi.h
index 25ddd0916bb2f4..154b0f6069db69 100644
--- a/arch/x86/include/asm/msi.h
+++ b/arch/x86/include/asm/msi.h
@@ -11,4 +11,6 @@ int pci_msi_prepare(struct irq_domain *domain, struct device *dev, int nvec,
void pci_msi_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc);
+void irq_msi_compose_msg(struct irq_data *data, struct msi_msg *msg);
+
#endif /* _ASM_X86_MSI_H */
diff --git a/arch/x86/include/asm/ps4.h b/arch/x86/include/asm/ps4.h
new file mode 100644
index 00000000000000..60ee1c4f4f1841
--- /dev/null
+++ b/arch/x86/include/asm/ps4.h
@@ -0,0 +1,60 @@
+/*
+ * ps4.h: Sony PS4 platform setup code
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; version 2
+ * of the License.
+ */
+#ifndef _ASM_X86_PS4_H
+#define _ASM_X86_PS4_H
+
+#ifdef CONFIG_X86_PS4
+
+#include <linux/irqdomain.h>
+
+#define PS4_DEFAULT_TSC_FREQ 1594000000
+
+#define EMC_TIMER_BASE 0xd0281000
+#define EMC_TIMER_VALUE 0x28
+
+extern unsigned long ps4_calibrate_tsc(void);
+
+/*
+ * The PS4 Aeolia southbridge device is a composite device containing some
+ * standard-ish, some not-so-standard, and some completely custom functions,
+ * all using special MSI handling. This function does the equivalent of
+ * pci_enable_msi_range and friends, for those devices. Only works after the
+ * Aeolia MSR routing function device (function 4) has been probed.
+ * Returns 1 or count, depending on IRQ allocation constraints, or negative on
+ * error. Assigned IRQ(s) start at dev->irq.
+ */
+extern int apcie_assign_irqs(struct pci_dev *dev, int nvec);
+extern void apcie_free_irqs(unsigned int virq, unsigned int nr_irqs);
+
+extern int apcie_status(void);
+extern int apcie_icc_cmd(u8 major, u16 minor, const void *data,
+ u16 length, void *reply, u16 reply_length);
+
+
+#else
+
+static inline int apcie_assign_irqs(struct pci_dev *dev, int nvec)
+{
+ return -ENODEV;
+}
+static inline void apcie_free_irqs(unsigned int virq, unsigned int nvec)
+{
+}
+static inline int apcie_status(void)
+{
+ return -ENODEV;
+}
+static inline int apcie_icc_cmd(u8 major, u16 minor, const void *data,
+ u16 length, void *reply, u16 reply_length)
+{
+ return -ENODEV;
+}
+
+#endif
+#endif
diff --git a/arch/x86/include/asm/setup.h b/arch/x86/include/asm/setup.h
index ae13bc974416fd..0a81ae7e888602 100644
--- a/arch/x86/include/asm/setup.h
+++ b/arch/x86/include/asm/setup.h
@@ -59,6 +59,12 @@ extern void x86_ce4100_early_setup(void);
static inline void x86_ce4100_early_setup(void) { }
#endif
+#ifdef CONFIG_X86_PS4
+extern void x86_ps4_early_setup(void);
+#else
+static inline void x86_ps4_early_setup(void) { }
+#endif
+
#ifndef _SETUP
#include <asm/espfix.h>
diff --git a/arch/x86/include/uapi/asm/bootparam.h b/arch/x86/include/uapi/asm/bootparam.h
index afdd5ae0fcc41d..aedecf11acbb2f 100644
--- a/arch/x86/include/uapi/asm/bootparam.h
+++ b/arch/x86/include/uapi/asm/bootparam.h
@@ -219,6 +219,7 @@ enum x86_hardware_subarch {
X86_SUBARCH_XEN,
X86_SUBARCH_INTEL_MID,
X86_SUBARCH_CE4100,
+ X86_SUBARCH_PS4,
X86_NR_SUBARCHS,
};
diff --git a/arch/x86/kernel/apic/msi.c b/arch/x86/kernel/apic/msi.c
index f10e7f93b0e2c0..b84d39aa7dd8a8 100644
--- a/arch/x86/kernel/apic/msi.c
+++ b/arch/x86/kernel/apic/msi.c
@@ -26,7 +26,7 @@
static struct irq_domain *msi_default_domain;
-static void irq_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
+void irq_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
{
struct irq_cfg *cfg = irqd_cfg(data);
diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c
index 45b5c6c4a55eda..a0f1092ef11bcb 100644
--- a/arch/x86/kernel/head64.c
+++ b/arch/x86/kernel/head64.c
@@ -376,6 +376,11 @@ void __init x86_64_start_reservations(char *real_mode_data)
default:
break;
}
-
+ /* Call the subarch specific early setup function */
+ switch (boot_params.hdr.hardware_subarch) {
+ case X86_SUBARCH_PS4:
+ x86_ps4_early_setup();
+ break;
+ }
start_kernel();
}
diff --git a/arch/x86/platform/Makefile b/arch/x86/platform/Makefile
index d0e835470d01af..66bc0cf7ef25f5 100644
--- a/arch/x86/platform/Makefile
+++ b/arch/x86/platform/Makefile
@@ -10,6 +10,7 @@ obj-y += intel/
obj-y += intel-mid/
obj-y += intel-quark/
obj-y += olpc/
+obj-y += ps4/
obj-y += scx200/
obj-y += sfi/
obj-y += ts5500/
diff --git a/arch/x86/platform/ps4/Makefile b/arch/x86/platform/ps4/Makefile
new file mode 100644
index 00000000000000..4d5fcde3a08077
--- /dev/null
+++ b/arch/x86/platform/ps4/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_X86_PS4) += ps4.o calibrate.o
diff --git a/arch/x86/platform/ps4/calibrate.c b/arch/x86/platform/ps4/calibrate.c
new file mode 100644
index 00000000000000..c8375c797ea3dd
--- /dev/null
+++ b/arch/x86/platform/ps4/calibrate.c
@@ -0,0 +1,116 @@
+/*
+ * calibrate.c: Sony PS4 TSC/LAPIC calibration
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; version 2
+ * of the License.
+ */
+
+#define pr_fmt(fmt) "ps4: " fmt
+
+#include <linux/jiffies.h>
+#include <asm/io.h>
+#include <asm/msr.h>
+#include <asm/ps4.h>
+#include <asm/delay.h>
+#include <asm/apic.h>
+
+/* The PS4 southbridge (Aeolia) has an EMC timer that ticks at 32.768kHz,
+ * which seems to be an appropriate clock reference for calibration. Both TSC
+ * and the LAPIC timer are based on the core clock frequency and thus can be
+ * calibrated together. */
+static void __iomem *emc_timer = NULL;
+
+static __init inline u32 emctimer_read32(unsigned int reg)
+{
+ return ioread32(emc_timer + reg);
+}
+
+static __init inline void emctimer_write32(unsigned int reg, u32 val)
+{
+ iowrite32(val, emc_timer + reg);
+}
+
+static __init inline u32 emctimer_read(void)
+{
+ u32 t1, t2;
+ t1 = emctimer_read32(EMC_TIMER_VALUE);
+ while (1) {
+ t2 = emctimer_read32(EMC_TIMER_VALUE);
+ if (t1 == t2)
+ return t1;
+ t1 = t2;
+ }
+}
+
+static __init unsigned long ps4_measure_tsc_freq(void)
+{
+ unsigned long ret = 0;
+ u32 t1, t2;
+ u64 tsc1, tsc2;
+
+ // This is part of the Aeolia pcie device, but it's too early to
+ // do this in a driver.
+ emc_timer = ioremap(EMC_TIMER_BASE, 0x100);
+ if (!emc_timer)
+ goto fail;
+
+ // reset/start the timer
+ emctimer_write32(0x84, emctimer_read32(0x84) & (~0x01));
+ // udelay is not calibrated yet, so this is likely wildly off, but good
+ // enough to work.
+ udelay(300);
+ emctimer_write32(0x00, emctimer_read32(0x00) | 0x01);
+ emctimer_write32(0x84, emctimer_read32(0x84) | 0x01);
+
+ t1 = emctimer_read();
+ tsc1 = tsc2 = rdtsc();
+
+ while (emctimer_read() == t1) {
+ // 0.1s timeout should be enough
+ tsc2 = rdtsc();
+ if ((tsc2 - tsc1) > (PS4_DEFAULT_TSC_FREQ/10)) {
+ pr_warn("EMC timer is broken.\n");
+ goto fail;
+ }
+ }
+ pr_info("EMC timer started in %lld TSC ticks\n", tsc2 - tsc1);
+
+ // Wait for a tick boundary
+ t1 = emctimer_read();
+ while ((t2 = emctimer_read()) == t1);
+ tsc1 = rdtsc();
+
+ // Wait for 1024 ticks to elapse (31.25ms)
+ // We don't need to wait very long, as we are looking for transitions.
+ // At this value, a TSC uncertainty of ~50 ticks corresponds to 1ppm of
+ // clock accuracy.
+ while ((emctimer_read() - t2) < 1024);
+ tsc2 = rdtsc();
+
+ // TSC rate is 32 times the elapsed time
+ ret = (tsc2 - tsc1) * 32;
+
+ pr_info("Calibrated TSC frequency: %ld kHz\n", ret);
+fail:
+ if (emc_timer) {
+ iounmap(emc_timer);
+ emc_timer = NULL;
+ }
+ return ret;
+}
+
+unsigned long __init ps4_calibrate_tsc(void)
+{
+ unsigned long tsc_freq = ps4_measure_tsc_freq();
+
+ if (!tsc_freq) {
+ pr_warn("Unable to measure TSC frequency, assuming default.\n");
+ tsc_freq = PS4_DEFAULT_TSC_FREQ;
+ }
+
+ lapic_timer_frequency = (tsc_freq + 8 * HZ) / (16 * HZ);
+
+ return (tsc_freq + 500) / 1000;
+}
diff --git a/arch/x86/platform/ps4/ps4.c b/arch/x86/platform/ps4/ps4.c
new file mode 100644
index 00000000000000..a077df74003e76
--- /dev/null
+++ b/arch/x86/platform/ps4/ps4.c
@@ -0,0 +1,76 @@
+/*
+ * ps4.c: Sony PS4 platform setup code
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; version 2
+ * of the License.
+ */
+
+#define pr_fmt(fmt) "ps4: " fmt
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/scatterlist.h>
+#include <linux/sfi.h>
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <linux/notifier.h>
+
+#include <asm/setup.h>
+#include <asm/mpspec_def.h>
+#include <asm/hw_irq.h>
+#include <asm/apic.h>
+#include <asm/io_apic.h>
+#include <asm/io.h>
+#include <asm/i8259.h>
+#include <asm/apb_timer.h>
+#include <asm/reboot.h>
+#include <asm/msr.h>
+#include <asm/ps4.h>
+
+static bool is_ps4;
+bool apcie_initialized;
+
+/*
+ * The RTC is part of the Aeolia PCI device and will be implemented there as
+ * an RTC class device; stub these out.
+ */
+static void dummy_get_wallclock(struct timespec64 *now)
+{
+ now->tv_sec = now->tv_nsec = 0;
+}
+static int dummy_set_wallclock(const struct timespec64 *now)
+{
+ return -ENODEV;
+}
+
+/*
+ * Provide a way for generic drivers to query for the availability of the
+ * PS4 apcie driver/device, which is a dependency for them.
+ */
+int apcie_status(void)
+{
+ if (!is_ps4)
+ return -ENODEV;
+ return apcie_initialized;
+}
+EXPORT_SYMBOL_GPL(apcie_status);
+
+void icc_reboot(void);
+
+/*
+ * PS4 specific x86_init function overrides and early setup calls.
+ */
+void __init x86_ps4_early_setup(void)
+{
+ pr_info("x86_ps4_early_setup: PS4 early setup\n");
+ is_ps4 = true;
+ x86_platform.calibrate_tsc = ps4_calibrate_tsc;
+ x86_platform.get_wallclock = dummy_get_wallclock;
+ x86_platform.set_wallclock = dummy_set_wallclock;
+
+ legacy_pic = &null_legacy_pic;
+ machine_ops.emergency_restart = icc_reboot;
+}
diff --git a/drivers/Makefile b/drivers/Makefile
index 5f5ccdbad21ae0..8acdd8abfabafa 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -87,6 +87,7 @@ obj-$(CONFIG_MTD) += mtd/
obj-$(CONFIG_SPI) += spi/
obj-$(CONFIG_SPMI) += spmi/
obj-$(CONFIG_HSI) += hsi/
+obj-$(CONFIG_X86_PS4) += ps4/
obj-y += net/
obj-$(CONFIG_ATM) += atm/
obj-$(CONFIG_FUSION) += message/
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index f003e301723a4a..87e97184b6ffb8 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -50,6 +50,10 @@
#include <linux/io-64-nonatomic-lo-hi.h>
#include "ahci.h"
+#ifdef CONFIG_X86_PS4
+#include <asm/ps4.h>
+#endif
+
#define DRV_NAME "ahci"
#define DRV_VERSION "3.0"
@@ -568,6 +572,11 @@ static const struct pci_device_id ahci_pci_tbl[] = {
/* Enmotus */
{ PCI_DEVICE(0x1c44, 0x8000), board_ahci },
+ /* Sony (PS4) */
+ { PCI_VDEVICE(SONY, PCI_DEVICE_ID_SONY_AEOLIA_AHCI), board_ahci },
+ { PCI_VDEVICE(SONY, PCI_DEVICE_ID_SONY_BELIZE_AHCI), board_ahci },
+ { PCI_VDEVICE(SONY, PCI_DEVICE_ID_SONY_BAIKAL_AHCI), board_ahci },
+
/* Generic, PCI class code for AHCI */
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
@@ -911,7 +920,22 @@ static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
*/
if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
return 0;
-
+#ifdef CONFIG_X86_PS4
+ if (pdev->vendor == PCI_VENDOR_ID_SONY) {
+ rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(31));
+ if (rc) {
+ dev_err(&pdev->dev, "31-bit DMA enable failed\n");
+ return rc;
+ }
+ rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(31));
+ if (rc) {
+ dev_err(&pdev->dev,
+ "31-bit consistent DMA enable failed\n");
+ return rc;
+ }
+ return 0;
+ }
+#endif
if (using_dac &&
!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
@@ -1552,6 +1576,11 @@ static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
{
int nvec;
+#ifdef CONFIG_X86_PS4
+ if (pdev->vendor == PCI_VENDOR_ID_SONY) {
+ return apcie_assign_irqs(pdev, n_ports);
+ }
+#endif
if (hpriv->flags & AHCI_HFLAG_NO_MSI)
return -ENODEV;
@@ -1604,7 +1633,11 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
VPRINTK("ENTER\n");
WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
-
+#ifdef CONFIG_X86_PS4
+ /* This will return negative on non-PS4 platforms */
+ if (apcie_status() == 0)
+ return -EPROBE_DEFER;
+#endif
ata_print_version_once(&pdev->dev, DRV_VERSION);
/* The AHCI driver can only drive the SATA ports, the PATA driver
@@ -1827,6 +1860,11 @@ static void ahci_remove_one(struct pci_dev *pdev)
{
pm_runtime_get_noresume(&pdev->dev);
ata_pci_remove_one(pdev);
+#ifdef CONFIG_X86_PS4
+ if (pdev->vendor == PCI_VENDOR_ID_SONY) {
+ apcie_free_irqs(pdev->irq, 1);
+ }
+#endif
}
module_pci_driver(ahci_pci_driver);
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 567b0377e1e21e..cd4fbfedb3c7ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -128,7 +128,7 @@ amdgpu-$(CONFIG_COMPAT) += amdgpu_ioc32.o
amdgpu-$(CONFIG_VGA_SWITCHEROO) += amdgpu_atpx_handler.o
amdgpu-$(CONFIG_ACPI) += amdgpu_acpi.o
amdgpu-$(CONFIG_MMU_NOTIFIER) += amdgpu_mn.o
-
+amdgpu-$(CONFIG_X86_PS4) += ps4_bridge.o
include $(FULL_AMD_PATH)/powerplay/Makefile
amdgpu-y += $(AMD_POWERPLAY_FILES)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 712ad8c2bdc5d5..cd1374d6d4316e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -171,7 +171,8 @@ extern int amdgpu_cik_support;
/* max cursor sizes (in pixels) */
#define CIK_CURSOR_WIDTH 128
#define CIK_CURSOR_HEIGHT 128
-
+#define LVP_CURSOR_WIDTH 64
+#define LVP_CURSOR_HEIGHT 64
struct amdgpu_device;
struct amdgpu_ib;
struct amdgpu_cs_parser;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index f7fa7675215c27..14fae8858f6f50 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -78,6 +78,8 @@ void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
switch (adev->asic_type) {
#ifdef CONFIG_DRM_AMDGPU_CIK
case CHIP_KAVERI:
+ case CHIP_GLADIUS:
+ case CHIP_LIVERPOOL:
kfd2kgd = amdgpu_amdkfd_gfx_7_get_functions();
break;
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
index 1eff36a8759581..e1e4e4e6a13b39 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
@@ -1517,7 +1517,29 @@ static const struct drm_connector_funcs amdgpu_connector_dp_funcs = {
.destroy = amdgpu_connector_destroy,
.force = amdgpu_connector_dvi_force,
};
+#ifdef CONFIG_X86_PS4
+int ps4_bridge_get_modes(struct drm_connector *connector);
+int ps4_bridge_mode_valid(struct drm_connector *connector,
+ struct drm_display_mode *mode);
+enum drm_connector_status ps4_bridge_detect(struct drm_connector *connector,
+ bool force);
+
+static const struct drm_connector_helper_funcs amdgpu_ps4_dp_connector_helper_funcs = {
+ .get_modes = ps4_bridge_get_modes,
+ .mode_valid = ps4_bridge_mode_valid,
+ .best_encoder = amdgpu_connector_dvi_encoder,
+};
+
+static const struct drm_connector_funcs amdgpu_ps4_dp_connector_funcs = {
+ .dpms = drm_helper_connector_dpms,
+ .detect = ps4_bridge_detect,
+ .fill_modes = drm_helper_probe_single_connector_modes,
+ //.set_property = amdgpu_connector_set_property,
+ .destroy = amdgpu_connector_destroy,
+ .force = amdgpu_connector_dvi_force,
+};
+#endif
static const struct drm_connector_funcs amdgpu_connector_edp_funcs = {
.dpms = drm_helper_connector_dpms,
.detect = amdgpu_connector_dp_detect,
@@ -1547,6 +1569,7 @@ amdgpu_connector_add(struct amdgpu_device *adev,
uint32_t subpixel_order = SubPixelNone;
bool shared_ddc = false;
bool is_dp_bridge = false;
+ bool is_ps4_bridge = false;
bool has_aux = false;
if (connector_type == DRM_MODE_CONNECTOR_Unknown)
@@ -1590,7 +1613,16 @@ amdgpu_connector_add(struct amdgpu_device *adev,
amdgpu_connector = kzalloc(sizeof(struct amdgpu_connector), GFP_KERNEL);
if (!amdgpu_connector)
return;
-
+ /* Liverpool (PS4) has an DP bridge which needs a special driver, and
+ * a fake HDMI port that doesn't really exist. */
+ if (adev->asic_type == CHIP_LIVERPOOL || adev->asic_type == CHIP_GLADIUS) {
+ if (connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
+ connector_type = DRM_MODE_CONNECTOR_HDMIA;
+ is_dp_bridge = true;
+ } else {
+ return;
+ }
+ }
connector = &amdgpu_connector->base;
amdgpu_connector->connector_id = connector_id;
@@ -1641,10 +1673,20 @@ amdgpu_connector_add(struct amdgpu_device *adev,
case DRM_MODE_CONNECTOR_HDMIA:
case DRM_MODE_CONNECTOR_HDMIB:
case DRM_MODE_CONNECTOR_DisplayPort:
+ if (is_ps4_bridge) {
drm_connector_init(dev, &amdgpu_connector->base,
&amdgpu_connector_dp_funcs, connector_type);
drm_connector_helper_add(&amdgpu_connector->base,
&amdgpu_connector_dp_helper_funcs);
+ } else {
+ drm_connector_init(dev, &amdgpu_connector->base,
+ &amdgpu_ps4_dp_connector_funcs, connector_type);
+ drm_connector_helper_add(&amdgpu_connector->base,
+ &amdgpu_ps4_dp_connector_helper_funcs);
+ //&amdgpu_connector_dp_helper_funcs);
+
+
+ }
drm_object_attach_property(&amdgpu_connector->base.base,
adev->mode_info.underscan_property,
UNDERSCAN_OFF);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index bc746a6e0eccf2..5c92b41a03350b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -75,6 +75,8 @@ static const char *amdgpu_asic_name[] = {
"BONAIRE",
"KAVERI",
"KABINI",
+ "LIVERPOOL",
+ "GLADIUS",
"HAWAII",
"MULLINS",
"TOPAZ",
@@ -1382,6 +1384,8 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
case CHIP_KAVERI:
case CHIP_KABINI:
case CHIP_MULLINS:
+ case CHIP_LIVERPOOL:
+ case CHIP_GLADIUS:
#endif
default:
return 0;
@@ -1491,6 +1495,8 @@ static int amdgpu_early_init(struct amdgpu_device *adev)
case CHIP_KAVERI:
case CHIP_KABINI:
case CHIP_MULLINS:
+ case CHIP_LIVERPOOL:
+ case CHIP_GLADIUS:
if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
adev->family = AMDGPU_FAMILY_CI;
else
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 4dd68d8213538e..9dcb4f0f3d31ab 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -46,6 +46,9 @@
#include "amdgpu_amdkfd.h"
+#ifdef CONFIG_X86_PS4
+#include <asm/ps4.h>
+#endif
/*
* KMS wrapper.
* - 3.0.0 - initial driver
@@ -449,6 +452,13 @@ static const struct pci_device_id pciidlist[] = {
{0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
{0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
{0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
+ /* liverpool */
+ {0x1002, 0x9920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_LIVERPOOL|AMD_IS_APU},
+ {0x1002, 0x9922, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_LIVERPOOL|AMD_IS_APU},
+ {0x1002, 0x9923, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_LIVERPOOL|AMD_IS_APU},
+ /* gladius */
+ {0x1002, 0x9924, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_GLADIUS|AMD_IS_APU},
+
#endif
/* topaz */
{0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
@@ -577,6 +587,15 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,
if (ret)
return ret;
+#ifdef CONFIG_X86_PS4
+ /* On the PS4 (Liverpool graphics) we have a hard dependency on the
+ * Aeolia driver to set up the HDMI encoder which is connected to it,
+ * so defer probe until it is ready. This test passes if this isn't
+ * a PS4 (returns -ENODEV).
+ */
+ if (apcie_status() == 0)
+ return -EPROBE_DEFER;
+#endif
dev = drm_dev_alloc(&kms_driver, &pdev->dev);
if (IS_ERR(dev))
return PTR_ERR(dev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c
index 94138abe093b1a..319909a00b969e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c
@@ -31,6 +31,22 @@
#include "atom.h"
#include "atombios_encoders.h"
+#ifdef CONFIG_X86_PS4
+int ps4_bridge_register(struct drm_connector *connector,
+ struct drm_encoder *encoder);
+
+static void amdgpu_maybe_add_bridge(struct drm_connector *connector,
+ struct drm_encoder *encoder)
+{
+ struct drm_device *dev = connector->dev;
+ struct amdgpu_device *adev = dev->dev_private;
+
+ if (adev->asic_type == CHIP_LIVERPOOL || adev->asic_type == CHIP_GLADIUS) {
+ ps4_bridge_register(connector, encoder);
+ }
+}
+#endif
+
void
amdgpu_link_encoder_connector(struct drm_device *dev)
{
@@ -46,6 +62,9 @@ amdgpu_link_encoder_connector(struct drm_device *dev)
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
amdgpu_encoder = to_amdgpu_encoder(encoder);
if (amdgpu_encoder->devices & amdgpu_connector->devices) {
+#ifdef CONFIG_X86_PS4
+ amdgpu_maybe_add_bridge(connector, encoder);
+#endif
drm_mode_connector_attach_encoder(connector, encoder);
if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
amdgpu_atombios_encoder_init_backlight(amdgpu_encoder, connector);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index cd84bd0b1eafdc..76609c3de95c71 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -343,7 +343,7 @@ int amdgpu_ib_ring_tests(struct amdgpu_device *adev)
tmo_gfx = 8 * AMDGPU_IB_TEST_TIMEOUT;
}
- for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
+ for (i = 0; i < 1; ++i) {
struct amdgpu_ring *ring = adev->rings[i];
long tmo;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
index 3ab4c65ecc8b4e..3ead7c82d06126 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
@@ -161,7 +161,7 @@ int amdgpu_ih_process(struct amdgpu_device *adev)
if (atomic_xchg(&adev->irq.ih.lock, 1))
return IRQ_NONE;
- DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, adev->irq.ih.rptr, wptr);
+ //DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, adev->irq.ih.rptr, wptr);
/* Order reading of wptr vs. reading of IH ring data */
rmb();
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index 538e5f27d12058..0fabe4421f854a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -386,9 +386,13 @@ void amdgpu_irq_dispatch(struct amdgpu_device *adev,
src = adev->irq.client[client_id].sources[src_id];
if (!src) {
- DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id);
+ //DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id);
return;
}
+ else
+ {
+ //DRM_DEBUG("Interrupt src_id: %d client_id: %d\n", src_id, client_id);
+ }
r = src->funcs->process(adev, src, entry);
if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index 684769c9a48e2d..4ad6d0c31ba97f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -256,6 +256,8 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
case CHIP_KABINI:
case CHIP_HAWAII:
case CHIP_MULLINS:
+ case CHIP_LIVERPOOL:
+ case CHIP_GLADIUS:
return AMDGPU_FW_LOAD_DIRECT;
#endif
case CHIP_TOPAZ:
diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
index f81068ba4cc67c..ac74cec17d3b25 100644
--- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
+++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
@@ -261,12 +261,19 @@ static int amdgpu_atombios_dp_get_dp_link_config(struct drm_connector *connector
amdgpu_atombios_dp_convert_bpc_to_bpp(amdgpu_connector_get_monitor_bpc(connector));
static const unsigned link_rates[3] = { 162000, 270000, 540000 };
unsigned max_link_rate = drm_dp_max_link_rate(dpcd);
+ unsigned min_lane_num = 1;
unsigned max_lane_num = drm_dp_max_lane_count(dpcd);
unsigned lane_num, i, max_pix_clock;
+ struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
+ struct drm_device *dev = amdgpu_connector->base.dev;
+ struct amdgpu_device *adev = dev->dev_private;
+ /* Liverpool is always connected to an encoder that needs 4 lanes */
+ if (adev->asic_type == CHIP_LIVERPOOL)
+ min_lane_num = 4;
if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) ==
ENCODER_OBJECT_ID_NUTMEG) {
- for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) {
+ for (lane_num = min_lane_num; lane_num <= max_lane_num; lane_num <<= 1) {
max_pix_clock = (lane_num * 270000 * 8) / bpp;
if (max_pix_clock >= pix_clock) {
*dp_lanes = lane_num;
diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
index 2af26d2da12779..21f8fbfc2f2456 100644
--- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
+++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
@@ -444,9 +444,11 @@ int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder *encoder)
struct drm_connector *connector;
struct amdgpu_connector *amdgpu_connector;
struct amdgpu_connector_atom_dig *dig_connector;
-
+ struct drm_device *dev = encoder->dev;
+ struct amdgpu_device *adev = dev->dev_private;
/* dp bridges are always DP */
- if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
+ if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE ||
+ adev->asic_type == CHIP_LIVERPOOL || adev->asic_type == CHIP_GLADIUS)
return ATOM_ENCODER_MODE_DP;
/* DVO is always DVO */
@@ -2152,4 +2154,3 @@ amdgpu_atombios_encoder_get_dig_info(struct amdgpu_encoder *amdgpu_encoder)
return dig;
}
-
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 567c4a5cf90cc2..d0f602318a2ba4 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -747,6 +747,206 @@ static const u32 godavari_golden_registers[] =
0xc24d, 0xffffffff, 0x00000000
};
+static const u32 liverpool_golden_common_registers[] =
+{
+ 0x31dc, 0xffffffff, 0x00000800, /* SPI_RESOURCE_RESERVE_CU_0 */
+ 0x31dd, 0xffffffff, 0x00000800, /* SPI_RESOURCE_RESERVE_CU_1 */
+ 0x31e6, 0xffffffff, 0x00ffffbf, /* SPI_RESOURCE_RESERVE_EN_CU_0 */
+ 0x31e7, 0xffffffff, 0x00ffffaf, /* SPI_RESOURCE_RESERVE_EN_CU_1 */
+ 0x31e8, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_2 */
+ 0x31e9, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_3*/
+ 0x31ea, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_4 */
+ 0x31eb, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_5 */
+ 0x31ec, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_6 */
+ 0x31ed, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_7 */
+ 0x31ee, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_8 */
+ 0x31ef, 0xffffffff, 0x00fffffe, /* SPI_RESOURCE_RESERVE_EN_CU_9 */
+ 0xa0d4, 0xffffffff, 0x2a00161a, /* PA_SC_RASTER_CONFIG */
+ 0xa0d5, 0xffffffff, 0x00000000, /* PA_SC_RASTER_CONFIG_1 */
+ 0x1401, 0x00002000, 0x00002000, /* GARLIC_FLUSH_CNTL */
+};
+
+static const u32 liverpool_golden_registers[] =
+{
+ 0x3108, 0xffffffff, 0xfffffffc, /* RLC_CGTT_MGCG_OVERRIDE */
+ 0xc200, 0xffffffff, 0xe0000000, /* GRBM_GFX_INDEX */
+ /* These are all setting OFF_HYSTERESIS = 0x10 */
+ 0xf0a8, 0xffffffff, 0x00000100, /* CB_CGTT_SCLK_CTRL */
+ 0xf082, 0xffffffff, 0x00000100, /* CGTT_BCI_CLK_CTRL */
+ 0xf0b0, 0xffffffff, 0x00000100, /* CGTT_CP_CLK_CTRL */
+ 0xf0b2, 0xffffffff, 0x00000100, /* CGTT_CPC_CLK_CTRL */
+ 0xf0b1, 0xffffffff, 0x00000100, /* CGTT_CPF_CLK_CTRL */
+ 0x1579, 0xffffffff, 0x00600100, /* CGTT_DRM_CLK_CTRL0 */
+ 0xf0a0, 0xffffffff, 0x00000100, /* CGTT_GDS_CLK_CTRL */
+ 0xf085, 0xffffffff, 0x06000100, /* CGTT_IA_CLK_CTRL */
+ 0xf088, 0xffffffff, 0x00000100, /* CGTT_PA_CLK_CTRL */
+ 0xf086, 0xffffffff, 0x06000100, /* CGTT_WD_CLK_CTRL */
+ 0xf081, 0xffffffff, 0x00000100, /* CGTT_PC_CLK_CTRL */
+ 0xf0b8, 0xffffffff, 0x00000100, /* CGTT_RLC_CLK_CTRL */
+ 0xf089, 0xffffffff, 0x00000100, /* CGTT_SC_CLK_CTRL */
+ 0xf080, 0xffffffff, 0x00000100, /* CGTT_SPI_CLK_CTRL */
+ 0xf08c, 0xffffffff, 0x00000100, /* CGTT_SQ_CLK_CTRL */
+ 0xf08d, 0xffffffff, 0x00000100, /* CGTT_SQG_CLK_CTRL */
+ 0xf094, 0xffffffff, 0x00000100, /* CGTT_SX_CLK_CTRL0 */
+ 0xf095, 0xffffffff, 0x00000100, /* CGTT_SX_CLK_CTRL1 */
+ 0xf096, 0xffffffff, 0x00000100, /* CGTT_SX_CLK_CTRL2 */
+ 0xf097, 0xffffffff, 0x00000100, /* CGTT_SX_CLK_CTRL3 */
+ 0xf098, 0xffffffff, 0x00000100, /* CGTT_SX_CLK_CTRL4 */
+ 0xf09f, 0xffffffff, 0x00000100, /* CGTT_TCI_CLK_CTRL */
+ 0xf09e, 0xffffffff, 0x00000100, /* CGTT_TCP_CLK_CTRL */
+ 0xf084, 0xffffffff, 0x06000100, /* CGTT_VGT_CLK_CTRL */
+ 0xf0a4, 0xffffffff, 0x00000100, /* DB_CGTT_CLK_CTRL_0 */
+ 0xf09d, 0xffffffff, 0x00000100, /* TA_CGTT_CTRL */
+ 0xf0ad, 0xffffffff, 0x00000100, /* TCA_CGTT_SCLK_CTRL */
+ 0xf0ac, 0xffffffff, 0x00000100, /* TCC_CGTT_SCLK_CTRL */
+ 0xf09c, 0xffffffff, 0x00000100, /* TD_CGTT_CTRL */
+ /* */
+ 0xc200, 0xffffffff, 0xe0000000, /* GRBM_GFX_INDEX */
+ 0xf008, 0xffffffff, 0x00010000, /* CGTS_CU0_SP0_CTRL_REG */
+ 0xf009, 0xffffffff, 0x00030002, /* CGTS_CU0_LDS_SQ_CTRL_REG */
+ 0xf00a, 0xffffffff, 0x00040007, /* CGTS_CU0_TA_SQC_CTRL_REG */
+ 0xf00b, 0xffffffff, 0x00060005, /* CGTS_CU0_SP1_CTRL_REG */
+ 0xf00c, 0xffffffff, 0x00090008, /* CGTS_CU0_TD_TCP_CTRL_REG */
+ 0xf00d, 0xffffffff, 0x00010000, /* CGTS_CU1_SP0_CTRL_REG */
+ 0xf00e, 0xffffffff, 0x00030002, /* CGTS_CU1_LDS_SQ_CTRL_REG */
+ 0xf00f, 0xffffffff, 0x00040007, /* CGTS_CU1_TA_CTRL_REG */
+ 0xf010, 0xffffffff, 0x00060005, /* CGTS_CU1_SP1_CTRL_REG */
+ 0xf011, 0xffffffff, 0x00090008, /* CGTS_CU1_TD_TCP_CTRL_REG */
+ 0xf012, 0xffffffff, 0x00010000, /* CGTS_CU2_SP0_CTRL_REG */
+ 0xf013, 0xffffffff, 0x00030002, /* CGTS_CU2_LDS_SQ_CTRL_REG */
+ 0xf014, 0xffffffff, 0x00040007, /* CGTS_CU2_TA_CTRL_REG */
+ 0xf015, 0xffffffff, 0x00060005, /* CGTS_CU2_SP1_CTRL_REG */
+ 0xf016, 0xffffffff, 0x00090008, /* CGTS_CU2_TD_TCP_CTRL_REG */
+ 0xf017, 0xffffffff, 0x00010000, /* CGTS_CU3_SP0_CTRL_REG */
+ 0xf018, 0xffffffff, 0x00030002, /* CGTS_CU3_LDS_SQ_CTRL_REG */
+ 0xf019, 0xffffffff, 0x00040007, /* CGTS_CU3_TA_SQC_CTRL_REG */
+ 0xf01a, 0xffffffff, 0x00060005, /* CGTS_CU3_SP1_CTRL_REG */
+ 0xf01b, 0xffffffff, 0x00090008, /* CGTS_CU3_TD_TCP_CTRL_REG */
+ 0xf01c, 0xffffffff, 0x00010000, /* CGTS_CU4_SP0_CTRL_REG */
+ 0xf01d, 0xffffffff, 0x00030002, /* CGTS_CU4_LDS_SQ_CTRL_REG */
+ 0xf01e, 0xffffffff, 0x00040007, /* CGTS_CU4_TA_CTRL_REG */