From 6e54069435f1279dce83768ae23f00e05568eabb Mon Sep 17 00:00:00 2001 From: Marno van der Maas Date: Thu, 23 Jan 2025 11:59:27 +0000 Subject: [PATCH] Verilator unoptflat stop for rvfi_rd_addr This is introduced upstream and mainly indicates that Verilator cannot simulate this efficiently. Functionality is fine though. --- dv/verilator/sonata_verilator_lint.vlt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/dv/verilator/sonata_verilator_lint.vlt b/dv/verilator/sonata_verilator_lint.vlt index 6c0d42bc..05c09b51 100644 --- a/dv/verilator/sonata_verilator_lint.vlt +++ b/dv/verilator/sonata_verilator_lint.vlt @@ -90,6 +90,9 @@ lint_off -rule UNOPTFLAT -file "*/rtl/prim_fifo_async_simple.sv" lint_off -rule UNOPTFLAT -file "*/rtl/prim_subreg_ext.sv" lint_off -rule BLKSEQ -file "*/rtl/ibex_tracer.sv" +// Build warns of circular logic, but this is functioning correctly so it is safe to ignore. +lint_off -rule UNOPTFLAT -file "*/rtl/ibexc_top_tracing.sv" -match "*rvfi_rd_addr*" + // Bug seem in Verilator v5.020 where trace chandles produces a C++ compilation // error (generated C++ doesn't currently specify a type an internal verilator // function)