From d1b8cb3eca3e56619d70997f79ccc98fff1942d5 Mon Sep 17 00:00:00 2001 From: Marno van der Maas Date: Fri, 29 Nov 2024 16:03:09 +0000 Subject: [PATCH 1/2] Simulator boot stub for SRAM added --- .gitignore | 1 + sw/cheri/sim_boot_stub/Makefile | 7 ++++++- sw/cheri/sim_boot_stub/boot_sram.S | 20 ++++++++++++++++++++ 3 files changed, 27 insertions(+), 1 deletion(-) create mode 100644 sw/cheri/sim_boot_stub/boot_sram.S diff --git a/.gitignore b/.gitignore index b4563d578..2448cc9a3 100644 --- a/.gitignore +++ b/.gitignore @@ -6,6 +6,7 @@ target/ # FuseSoC and Sofware builds are placed in build build/ sw/cheri/sim_boot_stub/sim_boot_stub +sw/cheri/sim_boot_stub/sim_sram_boot_stub # Nix based builds a placed are symlinked to result result diff --git a/sw/cheri/sim_boot_stub/Makefile b/sw/cheri/sim_boot_stub/Makefile index bc0ce6beb..070bc6454 100644 --- a/sw/cheri/sim_boot_stub/Makefile +++ b/sw/cheri/sim_boot_stub/Makefile @@ -4,9 +4,14 @@ CFLAGS=-target riscv32-unknown-unknown -mcpu=cheriot -mabi=cheriot \ -mxcheri-rvc -mrelax -fshort-wchar -nodefaultlibs +all: sim_boot_stub sim_sram_boot_stub + sim_boot_stub: boot.S link.ld clang ${CFLAGS} -Tlink.ld -o sim_boot_stub boot.S +sim_sram_boot_stub: boot_sram.S link.ld + clang ${CFLAGS} -Tlink.ld -o sim_sram_boot_stub boot_sram.S + .PHONY: clean clean: - rm sim_boot_stub + rm sim_boot_stub sim_sram_boot_stub diff --git a/sw/cheri/sim_boot_stub/boot_sram.S b/sw/cheri/sim_boot_stub/boot_sram.S new file mode 100644 index 000000000..3396f9085 --- /dev/null +++ b/sw/cheri/sim_boot_stub/boot_sram.S @@ -0,0 +1,20 @@ +# Copyright lowRISC contributors. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + .section .text.start, "ax", @progbits + .zero 0x80 + + .globl start + .p2align 2 + .type start,@function + +#define SRAM_BASE 0x00101000 + +start: + // Enable the ICache + csrsi 0x7c0, 1 + auipcc ct1, 0 + # Jumping to the start of code in SRAM located at 0x00101000 by default. + li t0, SRAM_BASE + csetaddr ct1, ct1, t0 + cjr ct1 From 84bf938b0232531841bd3e0359a0c59c2ef221f3 Mon Sep 17 00:00:00 2001 From: Marno van der Maas Date: Mon, 2 Dec 2024 11:34:47 +0000 Subject: [PATCH 2/2] Boot stub for HyperRAM reformatted This does not have any functional changes, just removes some tabs and defines HYPERRAM_BASE for readability --- sw/cheri/sim_boot_stub/boot.S | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/sw/cheri/sim_boot_stub/boot.S b/sw/cheri/sim_boot_stub/boot.S index c8a814673..bdc5a8859 100644 --- a/sw/cheri/sim_boot_stub/boot.S +++ b/sw/cheri/sim_boot_stub/boot.S @@ -1,16 +1,20 @@ # Copyright lowRISC contributors. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 - .section .text.start, "ax", @progbits -.zero 0x80 + .section .text.start, "ax", @progbits + .zero 0x80 + + .globl start + .p2align 2 + .type start,@function + +#define HYPERRAM_BASE 0x40000000 - .globl start - .p2align 2 - .type start,@function start: // Enable the ICache csrsi 0x7c0, 1 auipcc ct1, 0 - li t0, 0x40000000 + // Jump to HyperRAM to start executing + li t0, HYPERRAM_BASE csetaddr ct1, ct1, t0 cjr ct1