diff --git a/arch/risc-v/include/jh7110/irq.h b/arch/risc-v/include/jh7110/irq.h
index 8c5b93b9a4877..2c8124c68e694 100644
--- a/arch/risc-v/include/jh7110/irq.h
+++ b/arch/risc-v/include/jh7110/irq.h
@@ -31,6 +31,6 @@
 
 /* Map RISC-V exception code to NuttX IRQ */
 
-#define NR_IRQS (RISCV_IRQ_SEXT + 127)
+#define NR_IRQS (RISCV_IRQ_SEXT + 83)
 
 #endif /* __ARCH_RISCV_INCLUDE_JH7110_IRQ_H */
diff --git a/arch/risc-v/src/jh7110/bl602_serial.c b/arch/risc-v/src/jh7110/bl602_serial.c
index eaf5815561d2c..11b11eae6557f 100644
--- a/arch/risc-v/src/jh7110/bl602_serial.c
+++ b/arch/risc-v/src/jh7110/bl602_serial.c
@@ -418,9 +418,6 @@ static int bl602_attach(struct uart_dev_s *dev)
   putreg32(1 << 3, BL602_UART_FIFO_CONFIG_0(0));
   _info("BL602_UART_FIFO_CONFIG_0=0x%x\n", getreg32(BL602_UART_FIFO_CONFIG_0(0)));
 
-  // Enable all IRQs
-  // _info("Enable all IRQs\n");
-  // for (int i = 1; i <= 64; i++) { up_enable_irq(i); }
   // Dump the UART and PLIC
   infodumpbuffer("UART Registers", 0x30002000, 0x36 * 4);
   infodumpbuffer("PLIC Interrupt Priority", 0xe0000004, 0x50 * 4);
@@ -440,9 +437,6 @@ static int bl602_attach(struct uart_dev_s *dev)
 
   // Set PLIC Interrupt Priority to 1
   _info("Set PLIC Interrupt Priority to 1\n");
-  // for (uintptr_t addr=0xe0000004; addr < 0xe0000004 + (0x50 * 4); addr+=4) {
-  //   putreg32(1, addr);
-  // }
   putreg32(1, (uintptr_t)0xe0000050); // IRQ 20
   infodumpbuffer("PLIC Interrupt Priority", 0xe0000004, 0x50 * 4);
   infodumpbuffer("PLIC Interrupt Pending", 0xe0001000, 2 * 4);
@@ -453,33 +447,23 @@ static int bl602_attach(struct uart_dev_s *dev)
 // Test the setting of PLIC Interrupt Priority
 void test_interrupt_priority(void)
 {
-  static uint32_t before1 = 0xFF;
-  static uint32_t before2 = 0xFF;
-  static uint32_t after1 = 0xFF;
-  static uint32_t after2 = 0xFF;
-
-  // Disable MMU
-  // _info("Disable MMU\n");
-  // uintptr_t satp = mmu_read_satp();
-  // mmu_write_satp(0);
-
   // Read the values before setting Interrupt Priority
-  before1 = *(volatile uint32_t *) 0xe0000050UL;
-  before2 = *(volatile uint32_t *) 0xe0000054UL;
+  uint32_t before50 = *(volatile uint32_t *) 0xe0000050UL;
+  uint32_t before54 = *(volatile uint32_t *) 0xe0000054UL;
 
   // Set the Interrupt Priority
+  // for 50 but NOT 54
   *(volatile uint32_t *) 0xe0000050UL = 1;
 
   // Read the values after setting Interrupt Priority
-  after1 = *(volatile uint32_t *) 0xe0000050UL;
-  after2 = *(volatile uint32_t *) 0xe0000054UL;
-
-  // Enable MMU
-  // mmu_write_satp(satp);
-  // _info("Enable MMU\n");
-
-  // Dump before and after values
-  _info("before1=%u, before2=%u, after1=%u, after2=%u\n", before1, before2, after1, after2);
+  uint32_t after50 = *(volatile uint32_t *) 0xe0000050UL;
+  uint32_t after54 = *(volatile uint32_t *) 0xe0000054UL;
+
+  // Dump before and after values:
+  // before50=0 before54=0
+  // after50=1  after54=1
+  // Why after54=1 ???
+  _info("before50=%u, before54=%u, after50=%u, after54=%u\n", before50, before54, after50, after54);
 }
 
 // Test in RISC-V Assembly the setting of PLIC Interrupt Priority
diff --git a/arch/risc-v/src/jh7110/jh7110_irq.c b/arch/risc-v/src/jh7110/jh7110_irq.c
index 4434588d62bf9..0cb9c43e27472 100644
--- a/arch/risc-v/src/jh7110/jh7110_irq.c
+++ b/arch/risc-v/src/jh7110/jh7110_irq.c
@@ -75,13 +75,14 @@ void up_irqinitialize(void)
 
   /* Set priority for all global interrupts to 1 (lowest) */
 
-  ////TODO
-  // int id;
+  int id;
 
-  // for (id = 1; id <= NR_IRQS; id++)
-  //   {
-  //     putreg32(1, (uintptr_t)(JH7110_PLIC_PRIORITY + 4 * id));
-  //   }
+  infodumpbuffer("PLIC Interrupt Priority: Before", 0xe0000004, 0x50 * 4); ////
+  for (id = 1; id <= NR_IRQS; id++)
+    {
+      putreg32(1, (uintptr_t)(JH7110_PLIC_PRIORITY + 4 * id));
+    }
+  infodumpbuffer("PLIC Interrupt Priority: After", 0xe0000004, 0x50 * 4); ////
 
   /* Set irq threshold to 0 (permits all global interrupts) */
 
@@ -184,9 +185,11 @@ void up_enable_irq(int irq)
 
       if (0 <= extirq && extirq <= 63)
         {
+          infodumpbuffer("PLIC Hart 0 S-Mode Interrupt Enable: Before", 0xe0002080, 2 * 4);////
           _info("extirq=%d, addr=%p, val=0x%d\n", extirq, (uintptr_t)JH7110_PLIC_ENABLE1 + (4 * (extirq / 32)), 1 << (extirq % 32)); ////
           modifyreg32(JH7110_PLIC_ENABLE1 + (4 * (extirq / 32)),
                       0, 1 << (extirq % 32));
+          infodumpbuffer("PLIC Hart 0 S-Mode Interrupt Enable: After", 0xe0002080, 2 * 4);////
         }
       else
         {