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Copy pathST_channel_prefixer_hw.tcl
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ST_channel_prefixer_hw.tcl
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# TCL File Generated by Component Editor 14.1
# Sun Apr 26 19:38:38 BST 2015
# DO NOT MODIFY
#
# ST_channel_prefixer "ST Channel prefixer" v1.0
# 2015.04.26.19:38:38
#
#
#
# request TCL package from ACDS 14.1
#
package require -exact qsys 14.1
#
# module ST_channel_prefixer
#
set_module_property DESCRIPTION ""
set_module_property NAME ST_channel_prefixer
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME "ST Channel prefixer"
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL ST_channel_prefixer
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file ST_channel_prefixer.v VERILOG PATH ST_channel_prefixer.v TOP_LEVEL_FILE
add_fileset SIM_VERILOG SIM_VERILOG "" ""
set_fileset_property SIM_VERILOG TOP_LEVEL ST_channel_prefixer
set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file ST_channel_prefixer.v VERILOG PATH ST_channel_prefixer.v
#
# parameters
#
#
# display items
#
#
# connection point clock_sink
#
add_interface clock_sink clock end
set_interface_property clock_sink clockRate 0
set_interface_property clock_sink ENABLED true
set_interface_property clock_sink EXPORT_OF ""
set_interface_property clock_sink PORT_NAME_MAP ""
set_interface_property clock_sink CMSIS_SVD_VARIABLES ""
set_interface_property clock_sink SVD_ADDRESS_GROUP ""
add_interface_port clock_sink clk clk Input 1
#
# connection point reset_sink
#
add_interface reset_sink reset end
set_interface_property reset_sink associatedClock clock_sink
set_interface_property reset_sink synchronousEdges DEASSERT
set_interface_property reset_sink ENABLED true
set_interface_property reset_sink EXPORT_OF ""
set_interface_property reset_sink PORT_NAME_MAP ""
set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
set_interface_property reset_sink SVD_ADDRESS_GROUP ""
add_interface_port reset_sink reset_n reset_n Input 1
#
# connection point prefix
#
add_interface prefix avalon_streaming end
set_interface_property prefix associatedClock clock_sink
set_interface_property prefix associatedReset reset_sink
set_interface_property prefix dataBitsPerSymbol 2
set_interface_property prefix errorDescriptor ""
set_interface_property prefix firstSymbolInHighOrderBits true
set_interface_property prefix maxChannel 0
set_interface_property prefix readyLatency 0
set_interface_property prefix ENABLED true
set_interface_property prefix EXPORT_OF ""
set_interface_property prefix PORT_NAME_MAP ""
set_interface_property prefix CMSIS_SVD_VARIABLES ""
set_interface_property prefix SVD_ADDRESS_GROUP ""
add_interface_port prefix prefix_ready ready Output 1
add_interface_port prefix prefix_valid valid Input 1
add_interface_port prefix prefix_data data Input 2
#
# connection point avalon_streaming_sink
#
add_interface avalon_streaming_sink avalon_streaming end
set_interface_property avalon_streaming_sink associatedClock clock_sink
set_interface_property avalon_streaming_sink associatedReset reset_sink
set_interface_property avalon_streaming_sink dataBitsPerSymbol 12
set_interface_property avalon_streaming_sink errorDescriptor ""
set_interface_property avalon_streaming_sink firstSymbolInHighOrderBits true
set_interface_property avalon_streaming_sink maxChannel 31
set_interface_property avalon_streaming_sink readyLatency 0
set_interface_property avalon_streaming_sink ENABLED true
set_interface_property avalon_streaming_sink EXPORT_OF ""
set_interface_property avalon_streaming_sink PORT_NAME_MAP ""
set_interface_property avalon_streaming_sink CMSIS_SVD_VARIABLES ""
set_interface_property avalon_streaming_sink SVD_ADDRESS_GROUP ""
add_interface_port avalon_streaming_sink STin_ready ready Output 1
add_interface_port avalon_streaming_sink STin_valid valid Input 1
add_interface_port avalon_streaming_sink STin_data data Input 12
add_interface_port avalon_streaming_sink STin_channel channel Input 5
add_interface_port avalon_streaming_sink STin_startofpacket startofpacket Input 1
add_interface_port avalon_streaming_sink STin_endofpacket endofpacket Input 1
#
# connection point avalon_streaming_source
#
add_interface avalon_streaming_source avalon_streaming start
set_interface_property avalon_streaming_source associatedClock clock_sink
set_interface_property avalon_streaming_source associatedReset reset_sink
set_interface_property avalon_streaming_source dataBitsPerSymbol 12
set_interface_property avalon_streaming_source errorDescriptor ""
set_interface_property avalon_streaming_source firstSymbolInHighOrderBits true
set_interface_property avalon_streaming_source maxChannel 127
set_interface_property avalon_streaming_source readyLatency 0
set_interface_property avalon_streaming_source ENABLED true
set_interface_property avalon_streaming_source EXPORT_OF ""
set_interface_property avalon_streaming_source PORT_NAME_MAP ""
set_interface_property avalon_streaming_source CMSIS_SVD_VARIABLES ""
set_interface_property avalon_streaming_source SVD_ADDRESS_GROUP ""
add_interface_port avalon_streaming_source STout_ready ready Input 1
add_interface_port avalon_streaming_source STout_valid valid Output 1
add_interface_port avalon_streaming_source STout_data data Output 12
add_interface_port avalon_streaming_source STout_channel channel Output 7
add_interface_port avalon_streaming_source STout_startofpacket startofpacket Output 1
add_interface_port avalon_streaming_source STout_endofpacket endofpacket Output 1