-
Notifications
You must be signed in to change notification settings - Fork 59
/
Copy pathqsystem.csv
We can make this file beautiful and searchable if this error is corrected: It looks like row 3 should actually have 1 column, instead of 2 in line 2.
132 lines (132 loc) · 11.3 KB
/
qsystem.csv
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
# system info qsystem on 2015.01.18.20:09:05
system_info:
name,value
DEVICE,EP3C16F484C6
DEVICE_FAMILY,Cyclone III
GENERATION_ID,1421611724
#
#
# Files generated for qsystem on 2015.01.18.20:09:05
files:
filepath,kind,attributes,module,is_top
qsystem/simulation/qsystem.v,VERILOG,,qsystem,true
qsystem/simulation/submodules/qsystem_nios2_qsys_0_rf_ram_a.dat,DAT,,qsystem_nios2_qsys_0,false
qsystem/simulation/submodules/qsystem_nios2_qsys_0_jtag_debug_module_wrapper.v,VERILOG,,qsystem_nios2_qsys_0,false
qsystem/simulation/submodules/qsystem_nios2_qsys_0_rf_ram_b.hex,HEX,,qsystem_nios2_qsys_0,false
qsystem/simulation/submodules/qsystem_nios2_qsys_0_oci_test_bench.v,VERILOG,,qsystem_nios2_qsys_0,false
qsystem/simulation/submodules/qsystem_nios2_qsys_0_nios2_waves.do,OTHER,,qsystem_nios2_qsys_0,false
qsystem/simulation/submodules/qsystem_nios2_qsys_0_ociram_default_contents.mif,MIF,,qsystem_nios2_qsys_0,false
qsystem/simulation/submodules/qsystem_nios2_qsys_0.sdc,SDC,,qsystem_nios2_qsys_0,false
qsystem/simulation/submodules/qsystem_nios2_qsys_0_ociram_default_contents.dat,DAT,,qsystem_nios2_qsys_0,false
qsystem/simulation/submodules/qsystem_nios2_qsys_0_jtag_debug_module_sysclk.v,VERILOG,,qsystem_nios2_qsys_0,false
qsystem/simulation/submodules/qsystem_nios2_qsys_0.v,VERILOG,,qsystem_nios2_qsys_0,false
qsystem/simulation/submodules/qsystem_nios2_qsys_0_rf_ram_b.dat,DAT,,qsystem_nios2_qsys_0,false
qsystem/simulation/submodules/qsystem_nios2_qsys_0_rf_ram_b.mif,MIF,,qsystem_nios2_qsys_0,false
qsystem/simulation/submodules/qsystem_nios2_qsys_0_ociram_default_contents.hex,HEX,,qsystem_nios2_qsys_0,false
qsystem/simulation/submodules/qsystem_nios2_qsys_0_rf_ram_a.mif,MIF,,qsystem_nios2_qsys_0,false
qsystem/simulation/submodules/qsystem_nios2_qsys_0_jtag_debug_module_tck.v,VERILOG,,qsystem_nios2_qsys_0,false
qsystem/simulation/submodules/qsystem_nios2_qsys_0_rf_ram_a.hex,HEX,,qsystem_nios2_qsys_0,false
qsystem/simulation/submodules/qsystem_nios2_qsys_0_test_bench.v,VERILOG,,qsystem_nios2_qsys_0,false
qsystem/simulation/submodules/qsystem_onchip_memory2_0.v,VERILOG,,qsystem_onchip_memory2_0,false
qsystem/simulation/submodules/qsystem_onchip_memory2_0.hex,HEX,,qsystem_onchip_memory2_0,false
qsystem/simulation/submodules/qsystem_jtag_uart_0.v,VERILOG,,qsystem_jtag_uart_0,false
qsystem/simulation/submodules/qsystem_sysid_qsys_0.vo,VERILOG,,qsystem_sysid_qsys_0,false
qsystem/simulation/submodules/qsystem_mm_interconnect_0.v,VERILOG,,qsystem_mm_interconnect_0,false
qsystem/simulation/submodules/qsystem_irq_mapper.sv,SYSTEM_VERILOG,,qsystem_irq_mapper,false
qsystem/simulation/submodules/altera_reset_controller.v,VERILOG,,altera_reset_controller,false
qsystem/simulation/submodules/altera_reset_synchronizer.v,VERILOG,,altera_reset_controller,false
qsystem/simulation/submodules/altera_reset_controller.sdc,SDC,,altera_reset_controller,false
qsystem/simulation/submodules/altera_merlin_master_translator.sv,SYSTEM_VERILOG,,altera_merlin_master_translator,false
qsystem/simulation/submodules/altera_merlin_slave_translator.sv,SYSTEM_VERILOG,,altera_merlin_slave_translator,false
qsystem/simulation/submodules/altera_merlin_master_agent.sv,SYSTEM_VERILOG,,altera_merlin_master_agent,false
qsystem/simulation/submodules/altera_merlin_slave_agent.sv,SYSTEM_VERILOG,,altera_merlin_slave_agent,false
qsystem/simulation/submodules/altera_merlin_burst_uncompressor.sv,SYSTEM_VERILOG,,altera_merlin_slave_agent,false
qsystem/simulation/submodules/altera_avalon_sc_fifo.v,VERILOG,,altera_avalon_sc_fifo,false
qsystem/simulation/submodules/qsystem_mm_interconnect_0_addr_router.sv,SYSTEM_VERILOG,,qsystem_mm_interconnect_0_addr_router,false
qsystem/simulation/submodules/qsystem_mm_interconnect_0_addr_router_001.sv,SYSTEM_VERILOG,,qsystem_mm_interconnect_0_addr_router_001,false
qsystem/simulation/submodules/qsystem_mm_interconnect_0_id_router.sv,SYSTEM_VERILOG,,qsystem_mm_interconnect_0_id_router,false
qsystem/simulation/submodules/qsystem_mm_interconnect_0_id_router_002.sv,SYSTEM_VERILOG,,qsystem_mm_interconnect_0_id_router_002,false
qsystem/simulation/submodules/qsystem_mm_interconnect_0_cmd_xbar_demux.sv,SYSTEM_VERILOG,,qsystem_mm_interconnect_0_cmd_xbar_demux,false
qsystem/simulation/submodules/qsystem_mm_interconnect_0_cmd_xbar_demux_001.sv,SYSTEM_VERILOG,,qsystem_mm_interconnect_0_cmd_xbar_demux_001,false
qsystem/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,qsystem_mm_interconnect_0_cmd_xbar_mux,false
qsystem/simulation/submodules/qsystem_mm_interconnect_0_cmd_xbar_mux.sv,SYSTEM_VERILOG,,qsystem_mm_interconnect_0_cmd_xbar_mux,false
qsystem/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,qsystem_mm_interconnect_0_cmd_xbar_mux_002,false
qsystem/simulation/submodules/qsystem_mm_interconnect_0_cmd_xbar_mux_002.sv,SYSTEM_VERILOG,,qsystem_mm_interconnect_0_cmd_xbar_mux_002,false
qsystem/simulation/submodules/qsystem_mm_interconnect_0_rsp_xbar_demux_002.sv,SYSTEM_VERILOG,,qsystem_mm_interconnect_0_rsp_xbar_demux_002,false
qsystem/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,qsystem_mm_interconnect_0_rsp_xbar_mux,false
qsystem/simulation/submodules/qsystem_mm_interconnect_0_rsp_xbar_mux.sv,SYSTEM_VERILOG,,qsystem_mm_interconnect_0_rsp_xbar_mux,false
qsystem/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,qsystem_mm_interconnect_0_rsp_xbar_mux_001,false
qsystem/simulation/submodules/qsystem_mm_interconnect_0_rsp_xbar_mux_001.sv,SYSTEM_VERILOG,,qsystem_mm_interconnect_0_rsp_xbar_mux_001,false
#
# Map from instance-path to kind of module
instances:
instancePath,module
qsystem.PWM_0,qsystem_PWM_0
qsystem.PWM_1,qsystem_PWM_0
qsystem.QEI_0,QEI
qsystem.QEI_1,QEI
qsystem.nios2_qsys_0,qsystem_nios2_qsys_0
qsystem.onchip_memory2_0,qsystem_onchip_memory2_0
qsystem.jtag_uart_0,qsystem_jtag_uart_0
qsystem.sysid_qsys_0,qsystem_sysid_qsys_0
qsystem.mm_interconnect_0,qsystem_mm_interconnect_0
qsystem.mm_interconnect_0.nios2_qsys_0_instruction_master_translator,altera_merlin_master_translator
qsystem.mm_interconnect_0.nios2_qsys_0_data_master_translator,altera_merlin_master_translator
qsystem.mm_interconnect_0.nios2_qsys_0_jtag_debug_module_translator,altera_merlin_slave_translator
qsystem.mm_interconnect_0.onchip_memory2_0_s1_translator,altera_merlin_slave_translator
qsystem.mm_interconnect_0.QEI_1_avalon_slave_translator,altera_merlin_slave_translator
qsystem.mm_interconnect_0.PWM_1_avalon_slave_translator,altera_merlin_slave_translator
qsystem.mm_interconnect_0.QEI_0_avalon_slave_translator,altera_merlin_slave_translator
qsystem.mm_interconnect_0.PWM_0_avalon_slave_translator,altera_merlin_slave_translator
qsystem.mm_interconnect_0.jtag_uart_0_avalon_jtag_slave_translator,altera_merlin_slave_translator
qsystem.mm_interconnect_0.sysid_qsys_0_control_slave_translator,altera_merlin_slave_translator
qsystem.mm_interconnect_0.nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent,altera_merlin_master_agent
qsystem.mm_interconnect_0.nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent,altera_merlin_master_agent
qsystem.mm_interconnect_0.nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent,altera_merlin_slave_agent
qsystem.mm_interconnect_0.onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent,altera_merlin_slave_agent
qsystem.mm_interconnect_0.QEI_1_avalon_slave_translator_avalon_universal_slave_0_agent,altera_merlin_slave_agent
qsystem.mm_interconnect_0.PWM_1_avalon_slave_translator_avalon_universal_slave_0_agent,altera_merlin_slave_agent
qsystem.mm_interconnect_0.QEI_0_avalon_slave_translator_avalon_universal_slave_0_agent,altera_merlin_slave_agent
qsystem.mm_interconnect_0.PWM_0_avalon_slave_translator_avalon_universal_slave_0_agent,altera_merlin_slave_agent
qsystem.mm_interconnect_0.jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent,altera_merlin_slave_agent
qsystem.mm_interconnect_0.sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent,altera_merlin_slave_agent
qsystem.mm_interconnect_0.nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo,altera_avalon_sc_fifo
qsystem.mm_interconnect_0.onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo,altera_avalon_sc_fifo
qsystem.mm_interconnect_0.QEI_1_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo,altera_avalon_sc_fifo
qsystem.mm_interconnect_0.PWM_1_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo,altera_avalon_sc_fifo
qsystem.mm_interconnect_0.QEI_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo,altera_avalon_sc_fifo
qsystem.mm_interconnect_0.PWM_0_avalon_slave_translator_avalon_universal_slave_0_agent_rsp_fifo,altera_avalon_sc_fifo
qsystem.mm_interconnect_0.jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo,altera_avalon_sc_fifo
qsystem.mm_interconnect_0.sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo,altera_avalon_sc_fifo
qsystem.mm_interconnect_0.addr_router,qsystem_mm_interconnect_0_addr_router
qsystem.mm_interconnect_0.addr_router_001,qsystem_mm_interconnect_0_addr_router_001
qsystem.mm_interconnect_0.id_router,qsystem_mm_interconnect_0_id_router
qsystem.mm_interconnect_0.id_router_001,qsystem_mm_interconnect_0_id_router
qsystem.mm_interconnect_0.id_router_002,qsystem_mm_interconnect_0_id_router_002
qsystem.mm_interconnect_0.id_router_003,qsystem_mm_interconnect_0_id_router_002
qsystem.mm_interconnect_0.id_router_004,qsystem_mm_interconnect_0_id_router_002
qsystem.mm_interconnect_0.id_router_005,qsystem_mm_interconnect_0_id_router_002
qsystem.mm_interconnect_0.id_router_006,qsystem_mm_interconnect_0_id_router_002
qsystem.mm_interconnect_0.id_router_007,qsystem_mm_interconnect_0_id_router_002
qsystem.mm_interconnect_0.cmd_xbar_demux,qsystem_mm_interconnect_0_cmd_xbar_demux
qsystem.mm_interconnect_0.rsp_xbar_demux,qsystem_mm_interconnect_0_cmd_xbar_demux
qsystem.mm_interconnect_0.rsp_xbar_demux_001,qsystem_mm_interconnect_0_cmd_xbar_demux
qsystem.mm_interconnect_0.cmd_xbar_demux_001,qsystem_mm_interconnect_0_cmd_xbar_demux_001
qsystem.mm_interconnect_0.cmd_xbar_mux,qsystem_mm_interconnect_0_cmd_xbar_mux
qsystem.mm_interconnect_0.cmd_xbar_mux_001,qsystem_mm_interconnect_0_cmd_xbar_mux
qsystem.mm_interconnect_0.cmd_xbar_mux_002,qsystem_mm_interconnect_0_cmd_xbar_mux_002
qsystem.mm_interconnect_0.cmd_xbar_mux_003,qsystem_mm_interconnect_0_cmd_xbar_mux_002
qsystem.mm_interconnect_0.cmd_xbar_mux_004,qsystem_mm_interconnect_0_cmd_xbar_mux_002
qsystem.mm_interconnect_0.cmd_xbar_mux_005,qsystem_mm_interconnect_0_cmd_xbar_mux_002
qsystem.mm_interconnect_0.cmd_xbar_mux_006,qsystem_mm_interconnect_0_cmd_xbar_mux_002
qsystem.mm_interconnect_0.cmd_xbar_mux_007,qsystem_mm_interconnect_0_cmd_xbar_mux_002
qsystem.mm_interconnect_0.rsp_xbar_demux_002,qsystem_mm_interconnect_0_rsp_xbar_demux_002
qsystem.mm_interconnect_0.rsp_xbar_demux_003,qsystem_mm_interconnect_0_rsp_xbar_demux_002
qsystem.mm_interconnect_0.rsp_xbar_demux_004,qsystem_mm_interconnect_0_rsp_xbar_demux_002
qsystem.mm_interconnect_0.rsp_xbar_demux_005,qsystem_mm_interconnect_0_rsp_xbar_demux_002
qsystem.mm_interconnect_0.rsp_xbar_demux_006,qsystem_mm_interconnect_0_rsp_xbar_demux_002
qsystem.mm_interconnect_0.rsp_xbar_demux_007,qsystem_mm_interconnect_0_rsp_xbar_demux_002
qsystem.mm_interconnect_0.rsp_xbar_mux,qsystem_mm_interconnect_0_rsp_xbar_mux
qsystem.mm_interconnect_0.rsp_xbar_mux_001,qsystem_mm_interconnect_0_rsp_xbar_mux_001
qsystem.irq_mapper,qsystem_irq_mapper
qsystem.rst_controller,altera_reset_controller