From f44a9dabb2192ffb203ddd0c71f6373c7d82faed Mon Sep 17 00:00:00 2001 From: Yi Wang Date: Fri, 12 May 2023 13:33:26 -0700 Subject: [PATCH 01/60] Enable tvOS and watchOS (#147) I realized that we need this when I was building the OpenXLA/IREE runtime for tvOS and watchOS. 1. Before this change, the `CMakeLists.txt` file uses CMake built-in variable `IOS`, which is equivalent to `CMAKE_SYSTEM_NAME STREQUAL "iOS"`, to tell if it is building for Apple mobile platforms. This trick prevents CMake from recognizing tvOS and watchOS. Introduce `IS_APPLE_OS` variable which is true if `CMAKE_SYSTEM_NAME MATCHES "^(Darwin|iOS|tvOS|watchOS)"`. 2. Before this change, the `CMakeLists.txt` assumes that Apple's ARM64 platform has the name "arm64". However, M2 chip has the name "arm64e". This pull request changes `MATCHES "arm64"` into `MATCHES "arm64.*"`. --------- Co-authored-by: Nikita Shulga --- CMakeLists.txt | 24 ++++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 9f4d1d19..c4e26cd3 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -55,9 +55,16 @@ MACRO(CPUINFO_TARGET_RUNTIME_LIBRARY target) ENDIF() ENDMACRO() +# -- [ Determine whether building for Apple's desktop or mobile OSes +IF(CMAKE_SYSTEM_NAME MATCHES "^(Darwin|iOS|tvOS|watchOS)$") + SET(IS_APPLE_OS TRUE) +ELSE() + SET(IS_APPLE_OS FALSE) +ENDIF() + # -- [ Determine target processor SET(CPUINFO_TARGET_PROCESSOR "${CMAKE_SYSTEM_PROCESSOR}") -IF(IOS OR (CMAKE_SYSTEM_NAME STREQUAL "Darwin" AND CMAKE_OSX_ARCHITECTURES MATCHES "^(x86_64|arm64)$")) +IF(IS_APPLE_OS AND CMAKE_OSX_ARCHITECTURES MATCHES "^(x86_64|arm64.*)$") SET(CPUINFO_TARGET_PROCESSOR "${CMAKE_OSX_ARCHITECTURES}") ELSEIF(CMAKE_GENERATOR MATCHES "^Visual Studio " AND CMAKE_GENERATOR_PLATFORM) IF(CMAKE_GENERATOR_PLATFORM STREQUAL "Win32") @@ -66,7 +73,7 @@ ELSEIF(CMAKE_GENERATOR MATCHES "^Visual Studio " AND CMAKE_GENERATOR_PLATFORM) SET(CPUINFO_TARGET_PROCESSOR "x86_64") ELSEIF(CMAKE_GENERATOR_PLATFORM STREQUAL "ARM64") SET(CPUINFO_TARGET_PROCESSOR "arm64") - ELSEIF(CMAKE_GENERATOR_PLATFORM STREQUAL "ARM64EC") + ELSEIF(CMAKE_GENERATOR_PLATFORM MATCHES "^(ARM64EC|arm64ec|ARM64E|arm64e)") SET(CPUINFO_TARGET_PROCESSOR "arm64") ELSE() MESSAGE(FATAL_ERROR "Unsupported Visual Studio architecture \"${CMAKE_GENERATOR_PLATFORM}\"") @@ -82,20 +89,21 @@ IF(NOT CMAKE_SYSTEM_PROCESSOR) "cpuinfo will compile, but cpuinfo_initialize() will always fail.") SET(CPUINFO_SUPPORTED_PLATFORM FALSE) ENDIF() -ELSEIF(NOT CPUINFO_TARGET_PROCESSOR MATCHES "^(i[3-6]86|AMD64|x86(_64)?|armv[5-8].*|aarch64|arm64|ARM64)$") +ELSEIF(NOT CPUINFO_TARGET_PROCESSOR MATCHES "^(i[3-6]86|AMD64|x86(_64)?|armv[5-8].*|aarch64|arm64.*|ARM64.*)$") MESSAGE(WARNING "Target processor architecture \"${CPUINFO_TARGET_PROCESSOR}\" is not supported in cpuinfo. " "cpuinfo will compile, but cpuinfo_initialize() will always fail.") SET(CPUINFO_SUPPORTED_PLATFORM FALSE) ENDIF() + IF(NOT CMAKE_SYSTEM_NAME) MESSAGE(WARNING "Target operating system is not specified. " "cpuinfo will compile, but cpuinfo_initialize() will always fail.") SET(CPUINFO_SUPPORTED_PLATFORM FALSE) ELSEIF(NOT CMAKE_SYSTEM_NAME MATCHES "^(Windows|WindowsStore|CYGWIN|MSYS|Darwin|Linux|Android)$") - IF(${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.14" AND NOT CMAKE_SYSTEM_NAME STREQUAL "iOS") + IF(${CMAKE_VERSION} VERSION_GREATER_EQUAL "3.14" AND NOT IS_APPLE_OS) MESSAGE(WARNING "Target operating system \"${CMAKE_SYSTEM_NAME}\" is not supported in cpuinfo. " "cpuinfo will compile, but cpuinfo_initialize() will always fail.") @@ -153,7 +161,7 @@ IF(CPUINFO_SUPPORTED_PLATFORM) LIST(APPEND CPUINFO_SRCS src/x86/linux/init.c src/x86/linux/cpuinfo.c) - ELSEIF(CMAKE_SYSTEM_NAME STREQUAL "Darwin" OR CMAKE_SYSTEM_NAME STREQUAL "iOS") + ELSEIF(IS_APPLE_OS) LIST(APPEND CPUINFO_SRCS src/x86/mach/init.c) ELSEIF(CMAKE_SYSTEM_NAME MATCHES "^(Windows|WindowsStore|CYGWIN|MSYS)$") LIST(APPEND CPUINFO_SRCS src/x86/windows/init.c) @@ -162,7 +170,7 @@ IF(CPUINFO_SUPPORTED_PLATFORM) LIST(APPEND CPUINFO_SRCS src/arm/windows/init-by-logical-sys-info.c src/arm/windows/init.c) - ELSEIF(CPUINFO_TARGET_PROCESSOR MATCHES "^(armv[5-8].*|aarch64|arm64)$" OR IOS_ARCH MATCHES "^(armv7.*|arm64.*)$") + ELSEIF(CPUINFO_TARGET_PROCESSOR MATCHES "^(armv[5-8].*|aarch64|arm64.*)$" OR IOS_ARCH MATCHES "^(armv7.*|arm64.*)$") LIST(APPEND CPUINFO_SRCS src/arm/uarch.c src/arm/cache.c) @@ -182,7 +190,7 @@ IF(CPUINFO_SUPPORTED_PLATFORM) ELSEIF(CMAKE_SYSTEM_PROCESSOR MATCHES "^(aarch64|arm64)$") LIST(APPEND CPUINFO_SRCS src/arm/linux/aarch64-isa.c) ENDIF() - ELSEIF(IOS OR (CMAKE_SYSTEM_NAME STREQUAL "Darwin" AND CPUINFO_TARGET_PROCESSOR STREQUAL "arm64")) + ELSEIF(IS_APPLE_OS AND CPUINFO_TARGET_PROCESSOR MATCHES "arm64.*") LIST(APPEND CPUINFO_SRCS src/arm/mach/init.c) ENDIF() IF(CMAKE_SYSTEM_NAME STREQUAL "Android") @@ -202,7 +210,7 @@ IF(CPUINFO_SUPPORTED_PLATFORM) src/linux/multiline.c src/linux/cpulist.c src/linux/processors.c) - ELSEIF(CMAKE_SYSTEM_NAME STREQUAL "Darwin" OR CMAKE_SYSTEM_NAME STREQUAL "iOS") + ELSEIF(IS_APPLE_OS) LIST(APPEND CPUINFO_SRCS src/mach/topology.c) ENDIF() From a4dc1da46c9206797d4a354201c27d7a01090095 Mon Sep 17 00:00:00 2001 From: Naveen Kumar <114990429+naveenthangudu@users.noreply.github.com> Date: Sat, 24 Jun 2023 06:55:57 +0530 Subject: [PATCH 02/60] Adding support for detection of AMD Zen4 CPUs (#151) * Adding support for detection of AMD Zen4 CPUs added following changes new enum `cpuinfo_uarch_zen4` for zen4 CPUs added CPU model ranges under CPU family 0x19 for identifying AMD Zen4 CPUs Signed-off-by: Naveen Kumar * Update src/x86/uarch.c --------- Signed-off-by: Naveen Kumar Co-authored-by: Nikita Shulga --- include/cpuinfo.h | 2 ++ src/x86/uarch.c | 6 ++++++ tools/cpu-info.c | 2 ++ 3 files changed, 10 insertions(+) diff --git a/include/cpuinfo.h b/include/cpuinfo.h index a7f17c2a..10f15f0f 100644 --- a/include/cpuinfo.h +++ b/include/cpuinfo.h @@ -365,6 +365,8 @@ enum cpuinfo_uarch { cpuinfo_uarch_zen2 = 0x0020010A, /** AMD Zen 3 microarchitecture. */ cpuinfo_uarch_zen3 = 0x0020010B, + /** AMD Zen 4 microarchitecture. */ + cpuinfo_uarch_zen4 = 0x0020010C, /** NSC Geode and AMD Geode GX and LX. */ cpuinfo_uarch_geode = 0x00200200, diff --git a/src/x86/uarch.c b/src/x86/uarch.c index 37054994..ad14eca2 100644 --- a/src/x86/uarch.c +++ b/src/x86/uarch.c @@ -225,6 +225,12 @@ enum cpuinfo_uarch cpuinfo_x86_decode_uarch( case 0x50: // Cezanne return cpuinfo_uarch_zen3; } + if ((model_info->model >= 0x10 && model_info->model <= 0x1F) || // Stones + (model_info->model >= 0x60 && model_info->model <= 0x6F) || // Raphael + (model_info->model >= 0x70 && model_info->model <= 0x77) || // Phoenix, Hawkpoint1 + (model_info->model >= 0x78 && model_info->model <= 0x7F) || // Phoenix 2, Hawkpoint2 + (model_info->model >= 0xA0 && model_info->model <= 0xAF)) // Stones-Dense + return cpuinfo_uarch_zen4; break; } break; diff --git a/tools/cpu-info.c b/tools/cpu-info.c index 8602fc07..bc09f8fe 100644 --- a/tools/cpu-info.c +++ b/tools/cpu-info.c @@ -131,6 +131,8 @@ static const char* uarch_to_string(enum cpuinfo_uarch uarch) { return "Zen 2"; case cpuinfo_uarch_zen3: return "Zen 3"; + case cpuinfo_uarch_zen4: + return "Zen 4"; case cpuinfo_uarch_geode: return "Geode"; case cpuinfo_uarch_bobcat: From 5366f69c0f998e943a338f282b774c6a4386b005 Mon Sep 17 00:00:00 2001 From: Richard Townsend Date: Tue, 27 Jun 2023 17:37:28 +0100 Subject: [PATCH 03/60] Improve Windows Unicode support (#141) This PR adds support for the Snapdragon Compute Platform used in the Windows Dev Kit 2023 (aka Project Volterra). It also fixes an issue that showed up when enumerating the cache structures and improves string handling to work even if the UTF-16 UNICODE header is set. --- src/arm/windows/init-by-logical-sys-info.c | 15 +++- src/arm/windows/init.c | 80 +++++++++++----------- src/arm/windows/windows-arm-init.h | 2 +- 3 files changed, 54 insertions(+), 43 deletions(-) diff --git a/src/arm/windows/init-by-logical-sys-info.c b/src/arm/windows/init-by-logical-sys-info.c index fe2611ca..1b715edf 100644 --- a/src/arm/windows/init-by-logical-sys-info.c +++ b/src/arm/windows/init-by-logical-sys-info.c @@ -832,8 +832,19 @@ static bool connect_packages_cores_clusters_by_processors( processor->cluster = cluster; if (chip_info) { - strncpy_s(package->name, CPUINFO_PACKAGE_NAME_MAX, chip_info->chip_name_string, - strnlen(chip_info->chip_name_string, CPUINFO_PACKAGE_NAME_MAX)); + size_t converted_chars = 0; + if (!WideCharToMultiByte( + CP_UTF8, + WC_ERR_INVALID_CHARS, + chip_info->chip_name_string, + -1, + package->name, + CPUINFO_PACKAGE_NAME_MAX, + NULL, + NULL)) { + cpuinfo_log_error("cpu name character conversion error"); + return false; + }; } /* Set start indexes and counts per packages / clusters / cores - going backwards */ diff --git a/src/arm/windows/init.c b/src/arm/windows/init.c index d2bd576f..f0de4ec0 100644 --- a/src/arm/windows/init.c +++ b/src/arm/windows/init.c @@ -21,24 +21,24 @@ static bool get_system_info_from_registry( enum cpuinfo_vendor* vendor); struct vendor_info { - char vendor_name[VENDOR_NAME_MAX]; + wchar_t vendor_name[VENDOR_NAME_MAX]; enum cpuinfo_vendor vendor; }; /* Please add new vendor here! */ static struct vendor_info vendors[] = { { - "Qualcomm", + L"Qualcomm", cpuinfo_vendor_qualcomm }, { - "Ampere(R)", + L"Ampere(R)", cpuinfo_vendor_ampere } }; static struct woa_chip_info woa_chip_unknown = { - "Unknown", + L"Unknown", woa_chip_name_unknown, { { @@ -52,7 +52,7 @@ static struct woa_chip_info woa_chip_unknown = { static struct woa_chip_info woa_chips[] = { /* Microsoft SQ1 Kryo 495 4 + 4 cores (3 GHz + 1.80 GHz) */ { - "Microsoft SQ1", + L"Microsoft SQ1", woa_chip_name_microsoft_sq_1, { { @@ -67,7 +67,7 @@ static struct woa_chip_info woa_chips[] = { }, /* Microsoft SQ2 Kryo 495 4 + 4 cores (3.15 GHz + 2.42 GHz) */ { - "Microsoft SQ2", + L"Microsoft SQ2", woa_chip_name_microsoft_sq_2, { { @@ -82,7 +82,7 @@ static struct woa_chip_info woa_chips[] = { }, /* Microsoft Windows Dev Kit 2023 */ { - "Snapdragon (TM) 8cx Gen 3 @ 3.0 GHz", + L"Snapdragon (TM) 8cx Gen 3 @ 3.0 GHz", woa_chip_name_microsoft_sq_3, { { @@ -97,7 +97,7 @@ static struct woa_chip_info woa_chips[] = { }, /* Ampere Altra */ { - "Ampere(R) Altra(R) Processor", + L"Ampere(R) Altra(R) Processor", woa_chip_name_ampere_altra, { { @@ -146,46 +146,46 @@ bool get_core_uarch_for_efficiency( /* Static helper functions */ static bool read_registry( - LPCTSTR subkey, - LPCTSTR value, - char** textBuffer) + LPCWSTR subkey, + LPCWSTR value, + char** text_buffer) { - DWORD keyType = 0; - DWORD dataSize = 0; + DWORD key_type = 0; + DWORD data_size = 0; const DWORD flags = RRF_RT_REG_SZ; /* Only read strings (REG_SZ) */ LSTATUS result = 0; HANDLE heap = GetProcessHeap(); - result = RegGetValue( - HKEY_LOCAL_MACHINE, + result = RegGetValueW( + HKEY_LOCAL_MACHINE, subkey, value, flags, - &keyType, + &key_type, NULL, /* Request buffer size */ - &dataSize); - if (result != 0 || dataSize == 0) { + &data_size); + if (result != 0 || data_size == 0) { cpuinfo_log_error("Registry entry size read error"); return false; } - if (*textBuffer) { - HeapFree(heap, 0, *textBuffer); + if (*text_buffer) { + HeapFree(heap, 0, *text_buffer); } - *textBuffer = HeapAlloc(heap, HEAP_ZERO_MEMORY, dataSize); - if (*textBuffer == NULL) { + *text_buffer = HeapAlloc(heap, HEAP_ZERO_MEMORY, data_size * sizeof(wchar_t)); + if (*text_buffer == NULL) { cpuinfo_log_error("Registry textbuffer allocation error"); return false; } - result = RegGetValue( + result = RegGetValueW( HKEY_LOCAL_MACHINE, subkey, value, flags, NULL, - *textBuffer, /* Write string in this destination buffer */ - &dataSize); + *text_buffer, /* Write string in this destination buffer */ + &data_size); if (result != 0) { cpuinfo_log_error("Registry read error"); return false; @@ -198,56 +198,56 @@ static bool get_system_info_from_registry( enum cpuinfo_vendor* vendor) { bool result = false; - char* textBuffer = NULL; - LPCTSTR cpu0_subkey = - (LPCTSTR)"HARDWARE\\DESCRIPTION\\System\\CentralProcessor\\0"; - LPCTSTR chip_name_value = (LPCTSTR)"ProcessorNameString"; - LPCTSTR vendor_name_value = (LPCTSTR)"VendorIdentifier"; + char* text_buffer = NULL; + LPCWSTR cpu0_subkey = L"HARDWARE\\DESCRIPTION\\System\\CentralProcessor\\0"; + LPCWSTR chip_name_value = L"ProcessorNameString"; + LPCWSTR vendor_name_value = L"VendorIdentifier"; *chip_info = NULL; *vendor = cpuinfo_vendor_unknown; HANDLE heap = GetProcessHeap(); /* 1. Read processor model name from registry and find in the hard-coded list. */ - if (!read_registry(cpu0_subkey, chip_name_value, &textBuffer)) { + if (!read_registry(cpu0_subkey, chip_name_value, &text_buffer)) { cpuinfo_log_error("Registry read error"); goto cleanup; } for (uint32_t i = 0; i < (uint32_t) woa_chip_name_last; i++) { - size_t compare_length = strnlen(woa_chips[i].chip_name_string, CPUINFO_PACKAGE_NAME_MAX); - int compare_result = strncmp(textBuffer, woa_chips[i].chip_name_string, compare_length); + size_t compare_length = wcsnlen(woa_chips[i].chip_name_string, CPUINFO_PACKAGE_NAME_MAX); + int compare_result = wcsncmp(text_buffer, woa_chips[i].chip_name_string, compare_length); if (compare_result == 0) { *chip_info = woa_chips+i; break; } } if (*chip_info == NULL) { - cpuinfo_log_error("Unknown chip model name.\n Please add new Windows on Arm SoC/chip support!"); + /* No match was found, so print a warning and assign the unknown case. */ + cpuinfo_log_error("Unknown chip model name '%ls'.\nPlease add new Windows on Arm SoC/chip support to arm/windows/init.c!", text_buffer); goto cleanup; } cpuinfo_log_debug("detected chip model name: %s", (**chip_info).chip_name_string); /* 2. Read vendor/manufacturer name from registry. */ - if (!read_registry(cpu0_subkey, vendor_name_value, &textBuffer)) { + if (!read_registry(cpu0_subkey, vendor_name_value, &text_buffer)) { cpuinfo_log_error("Registry read error"); goto cleanup; } for (uint32_t i = 0; i < (sizeof(vendors) / sizeof(struct vendor_info)); i++) { - if (strncmp(textBuffer, vendors[i].vendor_name, - strlen(vendors[i].vendor_name)) == 0) { + if (wcsncmp(text_buffer, vendors[i].vendor_name, + wcslen(vendors[i].vendor_name)) == 0) { *vendor = vendors[i].vendor; result = true; break; } } if (*vendor == cpuinfo_vendor_unknown) { - cpuinfo_log_error("Unexpected vendor: %s", textBuffer); + cpuinfo_log_error("Unexpected vendor: %ls", text_buffer); } cleanup: - HeapFree(heap, 0, textBuffer); - textBuffer = NULL; + HeapFree(heap, 0, text_buffer); + text_buffer = NULL; return result; } diff --git a/src/arm/windows/windows-arm-init.h b/src/arm/windows/windows-arm-init.h index fcd0f388..a13add64 100644 --- a/src/arm/windows/windows-arm-init.h +++ b/src/arm/windows/windows-arm-init.h @@ -20,7 +20,7 @@ struct core_info_by_chip_name { * but can be read from registry. */ struct woa_chip_info { - char* chip_name_string; + wchar_t* chip_name_string; enum woa_chip_name chip_name; struct core_info_by_chip_name uarchs[woa_chip_name_last]; }; From 512e9d0258212d6759729330b445fa41f4fa0a49 Mon Sep 17 00:00:00 2001 From: Connor Baker Date: Sat, 8 Jul 2023 17:35:44 -0400 Subject: [PATCH 04/60] cmake: add USE_SYSTEM_* options (#153) Similar to the work done in https://github.com/pytorch/pytorch/pull/37137, this adds the following CMake options: - `USE_SYSTEM_LIBS` - `USE_SYSTEM_GOOGLEBENCHMARK` - `USE_SYSTEM_GOOGLETEST` This is particularly useful in the context of Nix, where we can build these libraries once and then re-use them elsewhere to avoid rebuilding vendors dependencies. --- CMakeLists.txt | 19 +++++++++++++------ deps/clog/CMakeLists.txt | 8 ++++++-- 2 files changed, 19 insertions(+), 8 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index c4e26cd3..338403ff 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -23,6 +23,9 @@ OPTION(CPUINFO_BUILD_UNIT_TESTS "Build cpuinfo unit tests" ON) OPTION(CPUINFO_BUILD_MOCK_TESTS "Build cpuinfo mock tests" ON) OPTION(CPUINFO_BUILD_BENCHMARKS "Build cpuinfo micro-benchmarks" ON) OPTION(CPUINFO_BUILD_PKG_CONFIG "Build pkg-config manifest" ON) +OPTION(USE_SYSTEM_LIBS "Use system libraries instead of downloading and building them" OFF) +OPTION(USE_SYSTEM_GOOGLEBENCHMARK "Use system Google Benchmark library instead of downloading and building it" ${USE_SYSTEM_LIBS}) +OPTION(USE_SYSTEM_GOOGLETEST "Use system Google Test library instead of downloading and building it" ${USE_SYSTEM_LIBS}) # ---[ CMake options INCLUDE(GNUInstallDirs) @@ -117,8 +120,10 @@ SET(CONFU_DEPENDENCIES_SOURCE_DIR ${CMAKE_SOURCE_DIR}/deps SET(CONFU_DEPENDENCIES_BINARY_DIR ${CMAKE_BINARY_DIR}/deps CACHE PATH "Confu-style dependencies binary directory") -IF(CPUINFO_BUILD_MOCK_TESTS OR CPUINFO_BUILD_UNIT_TESTS) - IF(CPUINFO_SUPPORTED_PLATFORM AND NOT DEFINED GOOGLETEST_SOURCE_DIR) +IF(CPUINFO_SUPPORTED_PLATFORM AND (CPUINFO_BUILD_MOCK_TESTS OR CPUINFO_BUILD_UNIT_TESTS)) + IF(USE_SYSTEM_GOOGLETEST) + FIND_PACKAGE(GTest REQUIRED) + ELSEIF(NOT DEFINED GOOGLETEST_SOURCE_DIR) MESSAGE(STATUS "Downloading Google Test to ${CONFU_DEPENDENCIES_SOURCE_DIR}/googletest (define GOOGLETEST_SOURCE_DIR to avoid it)") CONFIGURE_FILE(cmake/DownloadGoogleTest.cmake "${CONFU_DEPENDENCIES_BINARY_DIR}/googletest-download/CMakeLists.txt") EXECUTE_PROCESS(COMMAND "${CMAKE_COMMAND}" -G "${CMAKE_GENERATOR}" . @@ -129,8 +134,10 @@ IF(CPUINFO_BUILD_MOCK_TESTS OR CPUINFO_BUILD_UNIT_TESTS) ENDIF() ENDIF() -IF(CPUINFO_BUILD_BENCHMARKS) - IF(CPUINFO_SUPPORTED_PLATFORM AND NOT DEFINED GOOGLEBENCHMARK_SOURCE_DIR) +IF(CPUINFO_SUPPORTED_PLATFORM AND CPUINFO_BUILD_BENCHMARKS) + IF(USE_SYSTEM_GOOGLEBENCHMARK) + FIND_PACKAGE(benchmark REQUIRED) + ELSEIF(NOT DEFINED GOOGLEBENCHMARK_SOURCE_DIR) MESSAGE(STATUS "Downloading Google Benchmark to ${CONFU_DEPENDENCIES_SOURCE_DIR}/googlebenchmark (define GOOGLEBENCHMARK_SOURCE_DIR to avoid it)") CONFIGURE_FILE(cmake/DownloadGoogleBenchmark.cmake "${CONFU_DEPENDENCIES_BINARY_DIR}/googlebenchmark-download/CMakeLists.txt") EXECUTE_PROCESS(COMMAND "${CMAKE_COMMAND}" -G "${CMAKE_GENERATOR}" . @@ -308,7 +315,7 @@ INSTALL(EXPORT cpuinfo-targets # ---[ cpuinfo micro-benchmarks IF(CPUINFO_SUPPORTED_PLATFORM AND CPUINFO_BUILD_BENCHMARKS) # ---[ Build google benchmark - IF(NOT TARGET benchmark) + IF(NOT TARGET benchmark AND NOT USE_SYSTEM_GOOGLEBENCHMARK) SET(BENCHMARK_ENABLE_TESTING OFF CACHE BOOL "") ADD_SUBDIRECTORY( "${GOOGLEBENCHMARK_SOURCE_DIR}" @@ -327,7 +334,7 @@ ENDIF() IF(CPUINFO_SUPPORTED_PLATFORM) IF(CPUINFO_BUILD_MOCK_TESTS OR CPUINFO_BUILD_UNIT_TESTS) # ---[ Build google test - IF(NOT TARGET gtest) + IF(NOT TARGET gtest AND NOT USE_SYSTEM_GOOGLETEST) IF(MSVC AND NOT CPUINFO_RUNTIME_TYPE STREQUAL "static") SET(gtest_force_shared_crt ON CACHE BOOL "" FORCE) ENDIF() diff --git a/deps/clog/CMakeLists.txt b/deps/clog/CMakeLists.txt index 4f34d23c..6e50c41c 100644 --- a/deps/clog/CMakeLists.txt +++ b/deps/clog/CMakeLists.txt @@ -14,6 +14,8 @@ ELSE() OPTION(CLOG_LOG_TO_STDIO "Log errors, warnings, and information to stdout/stderr" ON) ENDIF() OPTION(CLOG_BUILD_TESTS "Build clog tests" ON) +OPTION(USE_SYSTEM_LIBS "Use system libraries instead of downloading and building them" OFF) +OPTION(USE_SYSTEM_GOOGLETEST "Use system Google Test library instead of downloading and building it" ${USE_SYSTEM_LIBS}) # ---[ CMake options IF(CLOG_BUILD_TESTS) @@ -39,7 +41,9 @@ SET(CONFU_DEPENDENCIES_BINARY_DIR ${CMAKE_BINARY_DIR}/deps CACHE PATH "Confu-style dependencies binary directory") IF(CLOG_BUILD_TESTS) - IF(NOT DEFINED GOOGLETEST_SOURCE_DIR) + IF(USE_SYSTEM_GOOGLETEST) + FIND_PACKAGE(GTest REQUIRED) + ELSEIF(NOT DEFINED GOOGLETEST_SOURCE_DIR) MESSAGE(STATUS "Downloading Google Test to ${CONFU_DEPENDENCIES_SOURCE_DIR}/googletest (define GOOGLETEST_SOURCE_DIR to avoid it)") CONFIGURE_FILE(cmake/DownloadGoogleTest.cmake "${CONFU_DEPENDENCIES_BINARY_DIR}/googletest-download/CMakeLists.txt") EXECUTE_PROCESS(COMMAND "${CMAKE_COMMAND}" -G "${CMAKE_GENERATOR}" . @@ -78,7 +82,7 @@ INSTALL(TARGETS clog # ---[ clog tests IF(CLOG_BUILD_TESTS) # ---[ Build google test - IF(NOT TARGET gtest) + IF(NOT TARGET gtest AND NOT USE_SYSTEM_GOOGLETEST) IF(MSVC AND NOT CLOG_RUNTIME_TYPE STREQUAL "static") SET(gtest_force_shared_crt ON CACHE BOOL "" FORCE) ENDIF() From ba6d42e40924360895aa8fe37ba1c5f87545e1f0 Mon Sep 17 00:00:00 2001 From: Marat Dukhan Date: Thu, 13 Jul 2023 20:12:57 -0500 Subject: [PATCH 05/60] Refactor detection of AMD Zen..Zen 4 cores (#154) Use solely extended model for distinguishing Zen/Zen 2/Zen 3/Zen 4 --- src/x86/uarch.c | 44 ++++++++++++++++++++------------------------ 1 file changed, 20 insertions(+), 24 deletions(-) diff --git a/src/x86/uarch.c b/src/x86/uarch.c index ad14eca2..a38d7b05 100644 --- a/src/x86/uarch.c +++ b/src/x86/uarch.c @@ -195,42 +195,38 @@ enum cpuinfo_uarch cpuinfo_x86_decode_uarch( } break; case 0x16: - if (model_info->model >= 0x03) { + if (model_info->extended_model >= 0x03) { return cpuinfo_uarch_puma; } else { return cpuinfo_uarch_jaguar; } case 0x17: - switch (model_info->model) { - case 0x01: // 14 nm Naples, Whitehaven, Summit Ridge, Snowy Owl - case 0x08: // 12 nm Pinnacle Ridge - case 0x11: // 14 nm Raven Ridge, Great Horned Owl - case 0x18: // 12 nm Picasso + switch (model_info->extended_model) { + case 0x0: // model 01h -> 14 nm Naples/Whitehaven/Summit Ridge/Snowy Owl, model 08h -> 12 nm Colfax/Pinnacle Ridge + case 0x1: // model 11h -> 14 nm Raven Ridge/Great Horned Owl, model 18h -> 14 nm Banded Kestrel / 12 nm Picasso return cpuinfo_uarch_zen; - case 0x31: // Rome, Castle Peak - case 0x60: // Renoir - case 0x68: // Lucienne - case 0x71: // Matisse - case 0x90: // Van Gogh - case 0x98: // Mero + case 0x3: // model 31h -> Rome/Castle Peak + case 0x4: // model 47h -> Xbox Series X + case 0x6: // model 60h -> Renoir/Grey Hawk, model 68h -> Lucienne + case 0x7: // model 71h -> Matisse + case 0x9: // model 90h -> Van Gogh, model 98h -> Mero return cpuinfo_uarch_zen2; } break; case 0x19: - switch (model_info->model) { - case 0x01: // Genesis - case 0x21: // Vermeer - case 0x30: // Badami, Trento - case 0x40: // Rembrandt - case 0x50: // Cezanne + switch (model_info->extended_model) { + case 0x0: // model 00h -> Genesis, model 01h -> Milan, model 08h -> Chagall + case 0x2: // model 21h -> Vermeer + case 0x3: // model 30h -> Badami, Trento + case 0x4: // model 40h -> Rembrandt + case 0x5: // model 50h -> Cezanne return cpuinfo_uarch_zen3; - } - if ((model_info->model >= 0x10 && model_info->model <= 0x1F) || // Stones - (model_info->model >= 0x60 && model_info->model <= 0x6F) || // Raphael - (model_info->model >= 0x70 && model_info->model <= 0x77) || // Phoenix, Hawkpoint1 - (model_info->model >= 0x78 && model_info->model <= 0x7F) || // Phoenix 2, Hawkpoint2 - (model_info->model >= 0xA0 && model_info->model <= 0xAF)) // Stones-Dense + case 0x1: // model 10h..1Fh -> Stones + case 0x6: // model 60h..6Fh -> Raphael + case 0x7: // model 70h..77h -> Phoenix/Hawkpoint1, model 78h..7Fh -> Phoenix 2/Hawkpoint2 + case 0xA: // model A0h..AFh -> Stones-Dense return cpuinfo_uarch_zen4; + } break; } break; From 2345d3a19114fbc95c332adea4d1846df7156ffc Mon Sep 17 00:00:00 2001 From: Marat Dukhan Date: Thu, 13 Jul 2023 20:13:32 -0500 Subject: [PATCH 06/60] Detect Cortex-A715 and Cortex-X3 cores (#155) --- include/cpuinfo.h | 4 ++++ src/arm/midr.h | 4 +++- src/arm/uarch.c | 6 ++++++ tools/cpu-info.c | 4 ++++ 4 files changed, 17 insertions(+), 1 deletion(-) diff --git a/include/cpuinfo.h b/include/cpuinfo.h index 10f15f0f..0abf07da 100644 --- a/include/cpuinfo.h +++ b/include/cpuinfo.h @@ -439,11 +439,15 @@ enum cpuinfo_uarch { cpuinfo_uarch_cortex_x1 = 0x00300501, /** ARM Cortex-X2. */ cpuinfo_uarch_cortex_x2 = 0x00300502, + /** ARM Cortex-X3. */ + cpuinfo_uarch_cortex_x3 = 0x00300503, /** ARM Cortex-A510. */ cpuinfo_uarch_cortex_a510 = 0x00300551, /** ARM Cortex-A710. */ cpuinfo_uarch_cortex_a710 = 0x00300571, + /** ARM Cortex-A715. */ + cpuinfo_uarch_cortex_a715 = 0x00300572, /** Qualcomm Scorpion. */ cpuinfo_uarch_scorpion = 0x00400100, diff --git a/src/arm/midr.h b/src/arm/midr.h index b0e244c0..7255cfcf 100644 --- a/src/arm/midr.h +++ b/src/arm/midr.h @@ -175,7 +175,8 @@ inline static uint32_t midr_score_core(uint32_t midr) { case UINT32_C(0x53000040): /* Exynos M5 */ case UINT32_C(0x4100D440): /* Cortex-X1 */ case UINT32_C(0x4100D480): /* Cortex-X2 */ - /* These cores are in big role w.r.t Cortex-A75/-A76/-A77/-A78/-A710 */ + case UINT32_C(0x4100D4E0): /* Cortex-X3 */ + /* These cores are in big role w.r.t Cortex-A75/-A76/-A77/-A78/-A710/-A715 */ return 6; case UINT32_C(0x4100D080): /* Cortex-A72 */ case UINT32_C(0x4100D090): /* Cortex-A73 */ @@ -185,6 +186,7 @@ inline static uint32_t midr_score_core(uint32_t midr) { case UINT32_C(0x4100D0E0): /* Cortex-A76AE */ case UINT32_C(0x4100D410): /* Cortex-A78 */ case UINT32_C(0x4100D470): /* Cortex-A710 */ + case UINT32_C(0x4100D4D0): /* Cortex-A715 */ case UINT32_C(0x4800D400): /* Cortex-A76 (HiSilicon) */ case UINT32_C(0x4E000030): /* Denver 2 */ case UINT32_C(0x51002050): /* Kryo Gold */ diff --git a/src/arm/uarch.c b/src/arm/uarch.c index 1d4c6eef..97fb2d7c 100644 --- a/src/arm/uarch.c +++ b/src/arm/uarch.c @@ -119,6 +119,12 @@ void cpuinfo_arm_decode_vendor_uarch( *uarch = cpuinfo_uarch_neoverse_e1; break; #endif /* CPUINFO_ARCH_ARM64 && !defined(__ANDROID__) */ + case 0xD4D: /* Cortex-A715 */ + *uarch = cpuinfo_uarch_cortex_a715; + break; + case 0xD4E: /* Cortex-X3 */ + *uarch = cpuinfo_uarch_cortex_x3; + break; default: switch (midr_get_part(midr) >> 8) { #if CPUINFO_ARCH_ARM diff --git a/tools/cpu-info.c b/tools/cpu-info.c index bc09f8fe..05d13b90 100644 --- a/tools/cpu-info.c +++ b/tools/cpu-info.c @@ -193,10 +193,14 @@ static const char* uarch_to_string(enum cpuinfo_uarch uarch) { return "Cortex-A510"; case cpuinfo_uarch_cortex_a710: return "Cortex-A710"; + case cpuinfo_uarch_cortex_a715: + return "Cortex-A715"; case cpuinfo_uarch_cortex_x1: return "Cortex-X1"; case cpuinfo_uarch_cortex_x2: return "Cortex-X2"; + case cpuinfo_uarch_cortex_x3: + return "Cortex-X3"; case cpuinfo_uarch_neoverse_n1: return "Neoverse-N1"; case cpuinfo_uarch_neoverse_v1: From afb02fce33b03029da3e2aa070780ec8490ac884 Mon Sep 17 00:00:00 2001 From: Marat Dukhan Date: Thu, 13 Jul 2023 20:13:53 -0500 Subject: [PATCH 07/60] Fix potential uninitialized variable UB (#157) Fix potential undefined behavior when parsing /proc/cpuinfo Hardware string --- src/arm/linux/cpuinfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/arm/linux/cpuinfo.c b/src/arm/linux/cpuinfo.c index 817da122..b7805b5e 100644 --- a/src/arm/linux/cpuinfo.c +++ b/src/arm/linux/cpuinfo.c @@ -904,6 +904,7 @@ bool cpuinfo_arm_linux_parse_proc_cpuinfo( uint32_t max_processors_count, struct cpuinfo_arm_linux_processor processors[restrict static max_processors_count]) { + hardware[0] = '\0'; struct proc_cpuinfo_parser_state state = { .hardware = hardware, .revision = revision, From 139e58ef8c456eac14b0cbd888a906a3e6b8903e Mon Sep 17 00:00:00 2001 From: Marat Dukhan Date: Thu, 13 Jul 2023 20:27:17 -0500 Subject: [PATCH 08/60] Fix detection of CPU vendor on ARM (#156) - cpuinfo_vendor is the vendor of the CPU core, not CPU package --- include/cpuinfo.h | 2 -- src/arm/windows/init.c | 58 +++++++----------------------- src/arm/windows/windows-arm-init.h | 1 + 3 files changed, 14 insertions(+), 47 deletions(-) diff --git a/include/cpuinfo.h b/include/cpuinfo.h index 0abf07da..c46b65e9 100644 --- a/include/cpuinfo.h +++ b/include/cpuinfo.h @@ -188,8 +188,6 @@ enum cpuinfo_vendor { * Processors are variants of AMD cores. */ cpuinfo_vendor_hygon = 16, - /** Ampere Computing LLC. Vendor of ARM64 processor microarchitectures. */ - cpuinfo_vendor_ampere = 17, /* Active vendors of embedded CPUs */ diff --git a/src/arm/windows/init.c b/src/arm/windows/init.c index f0de4ec0..fc1f64bc 100644 --- a/src/arm/windows/init.c +++ b/src/arm/windows/init.c @@ -11,37 +11,19 @@ /* Efficiency class = 0 means little core, while 1 means big core for now */ #define MAX_WOA_VALID_EFFICIENCY_CLASSES 2 -#define VENDOR_NAME_MAX CPUINFO_PACKAGE_NAME_MAX struct cpuinfo_arm_isa cpuinfo_isa; static void set_cpuinfo_isa_fields(void); static bool get_system_info_from_registry( - struct woa_chip_info** chip_info, - enum cpuinfo_vendor* vendor); - -struct vendor_info { - wchar_t vendor_name[VENDOR_NAME_MAX]; - enum cpuinfo_vendor vendor; -}; - -/* Please add new vendor here! */ -static struct vendor_info vendors[] = { - { - L"Qualcomm", - cpuinfo_vendor_qualcomm - }, - { - L"Ampere(R)", - cpuinfo_vendor_ampere - } -}; + struct woa_chip_info** chip_info); static struct woa_chip_info woa_chip_unknown = { L"Unknown", woa_chip_name_unknown, { { + cpuinfo_vendor_unknown, cpuinfo_uarch_unknown, 0 } @@ -56,10 +38,12 @@ static struct woa_chip_info woa_chips[] = { woa_chip_name_microsoft_sq_1, { { + cpuinfo_vendor_arm, cpuinfo_uarch_cortex_a55, 1800000000, }, { + cpuinfo_vendor_arm, cpuinfo_uarch_cortex_a76, 3000000000, } @@ -71,10 +55,12 @@ static struct woa_chip_info woa_chips[] = { woa_chip_name_microsoft_sq_2, { { + cpuinfo_vendor_arm, cpuinfo_uarch_cortex_a55, 2420000000, }, { + cpuinfo_vendor_arm, cpuinfo_uarch_cortex_a76, 3150000000 } @@ -86,10 +72,12 @@ static struct woa_chip_info woa_chips[] = { woa_chip_name_microsoft_sq_3, { { + cpuinfo_vendor_arm, cpuinfo_uarch_cortex_a78, 2420000000, }, { + cpuinfo_vendor_arm, cpuinfo_uarch_cortex_x1, 3000000000 } @@ -101,6 +89,7 @@ static struct woa_chip_info woa_chips[] = { woa_chip_name_ampere_altra, { { + cpuinfo_vendor_arm, cpuinfo_uarch_neoverse_n1, 3000000000 } @@ -116,12 +105,12 @@ BOOL CALLBACK cpuinfo_arm_windows_init( set_cpuinfo_isa_fields(); - const bool system_result = get_system_info_from_registry(&chip_info, &vendor); + const bool system_result = get_system_info_from_registry(&chip_info); if (!system_result) { chip_info = &woa_chip_unknown; } - cpuinfo_is_initialized = cpu_info_init_by_logical_sys_info(chip_info, vendor); + cpuinfo_is_initialized = cpu_info_init_by_logical_sys_info(chip_info, chip_info->uarchs[0].vendor); return (system_result && cpuinfo_is_initialized ? TRUE : FALSE); } @@ -194,20 +183,17 @@ static bool read_registry( } static bool get_system_info_from_registry( - struct woa_chip_info** chip_info, - enum cpuinfo_vendor* vendor) + struct woa_chip_info** chip_info) { bool result = false; char* text_buffer = NULL; LPCWSTR cpu0_subkey = L"HARDWARE\\DESCRIPTION\\System\\CentralProcessor\\0"; LPCWSTR chip_name_value = L"ProcessorNameString"; - LPCWSTR vendor_name_value = L"VendorIdentifier"; *chip_info = NULL; - *vendor = cpuinfo_vendor_unknown; HANDLE heap = GetProcessHeap(); - /* 1. Read processor model name from registry and find in the hard-coded list. */ + /* Read processor model name from registry and find in the hard-coded list. */ if (!read_registry(cpu0_subkey, chip_name_value, &text_buffer)) { cpuinfo_log_error("Registry read error"); goto cleanup; @@ -227,24 +213,6 @@ static bool get_system_info_from_registry( } cpuinfo_log_debug("detected chip model name: %s", (**chip_info).chip_name_string); - /* 2. Read vendor/manufacturer name from registry. */ - if (!read_registry(cpu0_subkey, vendor_name_value, &text_buffer)) { - cpuinfo_log_error("Registry read error"); - goto cleanup; - } - - for (uint32_t i = 0; i < (sizeof(vendors) / sizeof(struct vendor_info)); i++) { - if (wcsncmp(text_buffer, vendors[i].vendor_name, - wcslen(vendors[i].vendor_name)) == 0) { - *vendor = vendors[i].vendor; - result = true; - break; - } - } - if (*vendor == cpuinfo_vendor_unknown) { - cpuinfo_log_error("Unexpected vendor: %ls", text_buffer); - } - cleanup: HeapFree(heap, 0, text_buffer); text_buffer = NULL; diff --git a/src/arm/windows/windows-arm-init.h b/src/arm/windows/windows-arm-init.h index a13add64..a90cb45f 100644 --- a/src/arm/windows/windows-arm-init.h +++ b/src/arm/windows/windows-arm-init.h @@ -12,6 +12,7 @@ enum woa_chip_name { /* Topology information hard-coded by SoC/chip name */ struct core_info_by_chip_name { + enum cpuinfo_vendor vendor; enum cpuinfo_uarch uarch; uint64_t frequency; /* Hz */ }; From 9b44b01b43e4162b4eefe2100e05f3a307500de2 Mon Sep 17 00:00:00 2001 From: Marat Dukhan Date: Thu, 13 Jul 2023 23:20:00 -0500 Subject: [PATCH 09/60] Fix arm-cache-test on AArch64 Exclude AArch32-only Broadcom SoC test cases from AArch64 builds --- test/arm-cache.cc | 78 ++++++++++++++++++++++++----------------------- 1 file changed, 40 insertions(+), 38 deletions(-) diff --git a/test/arm-cache.cc b/test/arm-cache.cc index 67113735..398c099d 100644 --- a/test/arm-cache.cc +++ b/test/arm-cache.cc @@ -1665,49 +1665,51 @@ TEST(ROCKCHIP, rk3368) { EXPECT_EQ(0, little_l3.size); } -TEST(BROADCOM, bcm2835) { - const struct cpuinfo_arm_chipset chipset = { - .vendor = cpuinfo_arm_chipset_vendor_broadcom, - .series = cpuinfo_arm_chipset_series_broadcom_bcm, - .model = 2835, - }; +#if CPUINFO_ARCH_ARM + TEST(BROADCOM, bcm2835) { + const struct cpuinfo_arm_chipset chipset = { + .vendor = cpuinfo_arm_chipset_vendor_broadcom, + .series = cpuinfo_arm_chipset_series_broadcom_bcm, + .model = 2835, + }; - struct cpuinfo_cache l1i = { 0 }; - struct cpuinfo_cache l1d = { 0 }; - struct cpuinfo_cache l2 = { 0 }; - struct cpuinfo_cache l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_arm11, 4, UINT32_C(0x410FB767), - &chipset, 0, 4, - &l1i, &l1d, &l2, &l3); + struct cpuinfo_cache l1i = { 0 }; + struct cpuinfo_cache l1d = { 0 }; + struct cpuinfo_cache l2 = { 0 }; + struct cpuinfo_cache l3 = { 0 }; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_arm11, 4, UINT32_C(0x410FB767), + &chipset, 0, 4, + &l1i, &l1d, &l2, &l3); - EXPECT_EQ(16 * 1024, l1i.size); - EXPECT_EQ(16 * 1024, l1d.size); - EXPECT_EQ(0, l2.size); - EXPECT_EQ(0, l3.size); -} + EXPECT_EQ(16 * 1024, l1i.size); + EXPECT_EQ(16 * 1024, l1d.size); + EXPECT_EQ(0, l2.size); + EXPECT_EQ(0, l3.size); + } -TEST(BROADCOM, bcm2836) { - const struct cpuinfo_arm_chipset chipset = { - .vendor = cpuinfo_arm_chipset_vendor_broadcom, - .series = cpuinfo_arm_chipset_series_broadcom_bcm, - .model = 2836, - }; + TEST(BROADCOM, bcm2836) { + const struct cpuinfo_arm_chipset chipset = { + .vendor = cpuinfo_arm_chipset_vendor_broadcom, + .series = cpuinfo_arm_chipset_series_broadcom_bcm, + .model = 2836, + }; - struct cpuinfo_cache l1i = { 0 }; - struct cpuinfo_cache l1d = { 0 }; - struct cpuinfo_cache l2 = { 0 }; - struct cpuinfo_cache l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a7, 4, UINT32_C(0x410FC075), - &chipset, 0, 4, - &l1i, &l1d, &l2, &l3); + struct cpuinfo_cache l1i = { 0 }; + struct cpuinfo_cache l1d = { 0 }; + struct cpuinfo_cache l2 = { 0 }; + struct cpuinfo_cache l3 = { 0 }; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a7, 4, UINT32_C(0x410FC075), + &chipset, 0, 4, + &l1i, &l1d, &l2, &l3); - EXPECT_EQ(32 * 1024, l1i.size); - EXPECT_EQ(32 * 1024, l1d.size); - EXPECT_EQ(512 * 1024, l2.size); - EXPECT_EQ(0, l3.size); -} + EXPECT_EQ(32 * 1024, l1i.size); + EXPECT_EQ(32 * 1024, l1d.size); + EXPECT_EQ(512 * 1024, l2.size); + EXPECT_EQ(0, l3.size); + } +#endif /* CPUINFO_ARCH_ARM */ TEST(BROADCOM, bcm2837) { const struct cpuinfo_arm_chipset chipset = { From 6daa51d347f6fc1bf2f12d3307c79e8815b01a27 Mon Sep 17 00:00:00 2001 From: Keith Smiley Date: Wed, 22 Feb 2023 15:31:28 -0800 Subject: [PATCH 10/60] Add darwin_x86_64 CPU handling Currently bazel supports `darwin` and `darwin_x86_64` as meaning the same thing. The fully qualified version is normally used if you're cross compiling from M1 machines to intel machines. I'm also hoping to remove the unqualified version to reduce confusion. This change makes cpuinfo compatible with both for now. --- BUILD.bazel | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/BUILD.bazel b/BUILD.bazel index 0c920648..231d18f9 100644 --- a/BUILD.bazel +++ b/BUILD.bazel @@ -114,6 +114,7 @@ cc_library( ":linux_riscv64": COMMON_SRCS + LINUX_SRCS, ":linux_s390x": COMMON_SRCS + LINUX_SRCS, ":macos_x86_64": COMMON_SRCS + X86_SRCS + MACH_SRCS + MACH_X86_SRCS, + ":macos_x86_64_legacy": COMMON_SRCS + X86_SRCS + MACH_SRCS + MACH_X86_SRCS, ":macos_arm64": COMMON_SRCS + MACH_SRCS + MACH_ARM_SRCS, ":windows_x86_64": COMMON_SRCS + X86_SRCS + WINDOWS_X86_SRCS, ":android_armv7": COMMON_SRCS + ARM_SRCS + LINUX_SRCS + LINUX_ARM32_SRCS + ANDROID_ARM_SRCS, @@ -149,6 +150,7 @@ cc_library( linkstatic = select({ # https://github.com/bazelbuild/bazel/issues/11552 ":macos_x86_64": False, + ":macos_x86_64_legacy": False, "//conditions:default": True, }), # Headers must be in textual_hdrs to allow us to set the standard to C99 @@ -240,13 +242,21 @@ config_setting( ) config_setting( - name = "macos_x86_64", + name = "macos_x86_64_legacy", values = { "apple_platform_type": "macos", "cpu": "darwin", }, ) +config_setting( + name = "macos_x86_64", + values = { + "apple_platform_type": "macos", + "cpu": "darwin_x86_64", + }, +) + config_setting( name = "windows_x86_64", values = {"cpu": "x64_windows"}, From 374c0bb22dc4a10000ce5595e3887306fe1be302 Mon Sep 17 00:00:00 2001 From: Marat Dukhan Date: Fri, 14 Jul 2023 00:31:38 -0500 Subject: [PATCH 11/60] Clean-up CPU Part -> uArch decoding on ARM - Detect server-side cores on Android - Clarify AArch32 support on Neoverse cores - Clarify AArch32 support on Cortex-A510/-A715/-X2/-X3 cores --- README.md | 2 +- src/arm/uarch.c | 28 ++++++++++++---------------- 2 files changed, 13 insertions(+), 17 deletions(-) diff --git a/README.md b/README.md index 87848b4b..b76601ad 100644 --- a/README.md +++ b/README.md @@ -272,7 +272,7 @@ LDFLAGS+= $(pkg-config --libs libcpuinfo) - [x] AMD-designed x86/x86-64 cores (up to Puma/Jaguar and Zen 2) - [ ] VIA-designed x86/x86-64 cores - [ ] Other x86 cores (DM&P, RDC, Transmeta, Cyrix, Rise) - - [x] ARM-designed ARM cores (up to Cortex-A55, Cortex-A77, and Neoverse E1/N1/V1/N2) + - [x] ARM-designed ARM cores (up to Cortex-A55, Cortex-A77, and Neoverse E1/V1/N2) - [x] Qualcomm-designed ARM cores (Scorpion, Krait, and Kryo) - [x] Nvidia-designed ARM cores (Denver and Carmel) - [x] Samsung-designed ARM cores (Exynos) diff --git a/src/arm/uarch.c b/src/arm/uarch.c index 97fb2d7c..2614a2e3 100644 --- a/src/arm/uarch.c +++ b/src/arm/uarch.c @@ -80,22 +80,18 @@ void cpuinfo_arm_decode_vendor_uarch( case 0xD0B: *uarch = cpuinfo_uarch_cortex_a76; break; -#if CPUINFO_ARCH_ARM64 && !defined(__ANDROID__) case 0xD0C: *uarch = cpuinfo_uarch_neoverse_n1; break; -#endif /* CPUINFO_ARCH_ARM64 && !defined(__ANDROID__) */ case 0xD0D: *uarch = cpuinfo_uarch_cortex_a77; break; case 0xD0E: /* Cortex-A76AE */ *uarch = cpuinfo_uarch_cortex_a76; break; -#if CPUINFO_ARCH_ARM64 && !defined(__ANDROID__) case 0xD40: *uarch = cpuinfo_uarch_neoverse_v1; break; -#endif /* CPUINFO_ARCH_ARM64 && !defined(__ANDROID__) */ case 0xD41: /* Cortex-A78 */ *uarch = cpuinfo_uarch_cortex_a78; break; @@ -108,23 +104,25 @@ void cpuinfo_arm_decode_vendor_uarch( case 0xD47: /* Cortex-A710 */ *uarch = cpuinfo_uarch_cortex_a710; break; +#if CPUINFO_ARCH_ARM64 case 0xD48: /* Cortex-X2 */ *uarch = cpuinfo_uarch_cortex_x2; break; -#if CPUINFO_ARCH_ARM64 && !defined(__ANDROID__) +#endif /* CPUINFO_ARCH_ARM64 */ case 0xD49: *uarch = cpuinfo_uarch_neoverse_n2; break; +#if CPUINFO_ARCH_ARM64 case 0xD4A: *uarch = cpuinfo_uarch_neoverse_e1; break; -#endif /* CPUINFO_ARCH_ARM64 && !defined(__ANDROID__) */ case 0xD4D: /* Cortex-A715 */ *uarch = cpuinfo_uarch_cortex_a715; break; case 0xD4E: /* Cortex-X3 */ *uarch = cpuinfo_uarch_cortex_x3; break; +#endif /* CPUINFO_ARCH_ARM64 */ default: switch (midr_get_part(midr) >> 8) { #if CPUINFO_ARCH_ARM @@ -152,18 +150,18 @@ void cpuinfo_arm_decode_vendor_uarch( case 0x100: *uarch = cpuinfo_uarch_brahma_b53; break; -#if CPUINFO_ARCH_ARM64 && !defined(__ANDROID__) +#if CPUINFO_ARCH_ARM64 case 0x516: /* Broadcom Vulkan was sold to Cavium before it reached the market, so we identify it as Cavium ThunderX2 */ *vendor = cpuinfo_vendor_cavium; *uarch = cpuinfo_uarch_thunderx2; break; -#endif +#endif /* CPUINFO_ARCH_ARM64 */ default: cpuinfo_log_warning("unknown Broadcom CPU part 0x%03"PRIx32" ignored", midr_get_part(midr)); } break; -#if CPUINFO_ARCH_ARM64 && !defined(__ANDROID__) +#if CPUINFO_ARCH_ARM64 case 'C': *vendor = cpuinfo_vendor_cavium; switch (midr_get_part(midr)) { @@ -180,15 +178,15 @@ void cpuinfo_arm_decode_vendor_uarch( cpuinfo_log_warning("unknown Cavium CPU part 0x%03"PRIx32" ignored", midr_get_part(midr)); } break; -#endif +#endif /* CPUINFO_ARCH_ARM64 */ case 'H': *vendor = cpuinfo_vendor_huawei; switch (midr_get_part(midr)) { -#if CPUINFO_ARCH_ARM64 && !defined(__ANDROID__) +#if CPUINFO_ARCH_ARM64 case 0xD01: /* Kunpeng 920 series */ *uarch = cpuinfo_uarch_taishan_v110; break; -#endif +#endif /* CPUINFO_ARCH_ARM64 */ case 0xD40: /* Kirin 980 Big/Medium cores -> Cortex-A76 */ *vendor = cpuinfo_vendor_arm; *uarch = cpuinfo_uarch_cortex_a76; @@ -227,7 +225,6 @@ void cpuinfo_arm_decode_vendor_uarch( cpuinfo_log_warning("unknown Nvidia CPU part 0x%03"PRIx32" ignored", midr_get_part(midr)); } break; -#if !defined(__ANDROID__) case 'P': *vendor = cpuinfo_vendor_apm; switch (midr_get_part(midr)) { @@ -238,7 +235,6 @@ void cpuinfo_arm_decode_vendor_uarch( cpuinfo_log_warning("unknown Applied Micro CPU part 0x%03"PRIx32" ignored", midr_get_part(midr)); } break; -#endif case 'Q': *vendor = cpuinfo_vendor_qualcomm; switch (midr_get_part(midr)) { @@ -305,14 +301,14 @@ void cpuinfo_arm_decode_vendor_uarch( *vendor = cpuinfo_vendor_arm; *uarch = cpuinfo_uarch_cortex_a55; break; -#if CPUINFO_ARCH_ARM64 && !defined(__ANDROID__) +#if CPUINFO_ARCH_ARM64 case 0xC00: *uarch = cpuinfo_uarch_falkor; break; case 0xC01: *uarch = cpuinfo_uarch_saphira; break; -#endif /* CPUINFO_ARCH_ARM64 && !defined(__ANDROID__) */ +#endif /* CPUINFO_ARCH_ARM64 */ default: cpuinfo_log_warning("unknown Qualcomm CPU part 0x%03"PRIx32" ignored", midr_get_part(midr)); } From 87d8234510367db49a65535021af5e1838a65ac2 Mon Sep 17 00:00:00 2001 From: Marat Dukhan Date: Fri, 14 Jul 2023 01:34:21 -0500 Subject: [PATCH 12/60] Detect ARMv8 AArch32 ISA via features --- src/arm/linux/aarch32-isa.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/arm/linux/aarch32-isa.c b/src/arm/linux/aarch32-isa.c index 2510911e..4fc2eb14 100644 --- a/src/arm/linux/aarch32-isa.c +++ b/src/arm/linux/aarch32-isa.c @@ -33,6 +33,13 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( const struct cpuinfo_arm_chipset chipset[restrict static 1], struct cpuinfo_arm_isa isa[restrict static 1]) { + if (architecture_version < 8) { + const uint32_t armv8_features2_mask = CPUINFO_ARM_LINUX_FEATURE2_AES | CPUINFO_ARM_LINUX_FEATURE2_PMULL | + CPUINFO_ARM_LINUX_FEATURE2_SHA1 | CPUINFO_ARM_LINUX_FEATURE2_SHA2 | CPUINFO_ARM_LINUX_FEATURE2_CRC32; + if ((features2 & armv8_features2_mask) != 0 && architecture_version < 8) { + architecture_version = 8; + } + } if (architecture_version >= 8) { /* * ARMv7 code running on ARMv8: IDIV, VFP, NEON are always supported, From 81a5aaeaec4000f0e35f8c3ddd707bdefb20bad8 Mon Sep 17 00:00:00 2001 From: Marat Dukhan Date: Tue, 18 Jul 2023 13:44:11 -0500 Subject: [PATCH 13/60] Detect AArch64-only big.LITTLE cores in AArch32 Some cores don't support AArch32, but can be used in heterogeneous SoC in combination with other cores which do support AArch32. In this case the cores are still reported in /proc/cpuinfo, and thus should be propertly handled to the uarch decoding code. --- src/arm/uarch.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/arm/uarch.c b/src/arm/uarch.c index 2614a2e3..e843a5b8 100644 --- a/src/arm/uarch.c +++ b/src/arm/uarch.c @@ -104,11 +104,9 @@ void cpuinfo_arm_decode_vendor_uarch( case 0xD47: /* Cortex-A710 */ *uarch = cpuinfo_uarch_cortex_a710; break; -#if CPUINFO_ARCH_ARM64 case 0xD48: /* Cortex-X2 */ *uarch = cpuinfo_uarch_cortex_x2; break; -#endif /* CPUINFO_ARCH_ARM64 */ case 0xD49: *uarch = cpuinfo_uarch_neoverse_n2; break; @@ -116,13 +114,13 @@ void cpuinfo_arm_decode_vendor_uarch( case 0xD4A: *uarch = cpuinfo_uarch_neoverse_e1; break; +#endif /* CPUINFO_ARCH_ARM64 */ case 0xD4D: /* Cortex-A715 */ *uarch = cpuinfo_uarch_cortex_a715; break; case 0xD4E: /* Cortex-X3 */ *uarch = cpuinfo_uarch_cortex_x3; break; -#endif /* CPUINFO_ARCH_ARM64 */ default: switch (midr_get_part(midr) >> 8) { #if CPUINFO_ARCH_ARM From 47727656bd89a8243fc4aa25eec34732c0394a75 Mon Sep 17 00:00:00 2001 From: Marat Dukhan Date: Tue, 18 Jul 2023 17:58:51 -0500 Subject: [PATCH 14/60] Fix warning in cpuinfo_arm_fixup_raspberry_pi_chipset Close #78 --- src/arm/linux/chipset.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arm/linux/chipset.c b/src/arm/linux/chipset.c index f2a002d7..7cc4feee 100644 --- a/src/arm/linux/chipset.c +++ b/src/arm/linux/chipset.c @@ -3854,7 +3854,7 @@ void cpuinfo_arm_chipset_to_string( */ void cpuinfo_arm_fixup_raspberry_pi_chipset( struct cpuinfo_arm_chipset chipset[restrict static 1], - const char revision[restrict static CPUINFO_HARDWARE_VALUE_MAX]) + const char revision[restrict static CPUINFO_REVISION_VALUE_MAX]) { const size_t revision_length = strnlen(revision, CPUINFO_REVISION_VALUE_MAX); From 4e72fe75989da328a6c52b3fb2e87f25aa71b0c8 Mon Sep 17 00:00:00 2001 From: Marat Dukhan Date: Wed, 19 Jul 2023 22:32:04 -0600 Subject: [PATCH 15/60] Fix ISA detection on ARM64 Windows --- src/arm/windows/init.c | 54 ++++++++++++++++-------------------------- 1 file changed, 20 insertions(+), 34 deletions(-) diff --git a/src/arm/windows/init.c b/src/arm/windows/init.c index fc1f64bc..0ff797f3 100644 --- a/src/arm/windows/init.c +++ b/src/arm/windows/init.c @@ -221,46 +221,32 @@ static bool get_system_info_from_registry( static void set_cpuinfo_isa_fields(void) { - bool armv8 = IsProcessorFeaturePresent(PF_ARM_V8_INSTRUCTIONS_AVAILABLE); - bool crypto = IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE); - bool load_store_atomic = IsProcessorFeaturePresent(PF_ARM_64BIT_LOADSTORE_ATOMIC); - bool float_multiply_accumulate = IsProcessorFeaturePresent(PF_ARM_FMAC_INSTRUCTIONS_AVAILABLE); - bool crc32 = IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE); - bool float_emulated = IsProcessorFeaturePresent(PF_FLOATING_POINT_EMULATED); + cpuinfo_isa.atomics = IsProcessorFeaturePresent(PF_ARM_V81_ATOMIC_INSTRUCTIONS_AVAILABLE) != 0; - /* Read all Arm related Windows features for debug purposes, even if we can't - * pair Arm ISA feature to that now. - */ -#if CPUINFO_LOG_DEBUG_PARSERS - bool divide = IsProcessorFeaturePresent(PF_ARM_DIVIDE_INSTRUCTION_AVAILABLE); - bool ext_cache = IsProcessorFeaturePresent(PF_ARM_EXTERNAL_CACHE_AVAILABLE); - bool vfp_registers = IsProcessorFeaturePresent(PF_ARM_VFP_32_REGISTERS_AVAILABLE); - bool arm_v81 = IsProcessorFeaturePresent(PF_ARM_V81_ATOMIC_INSTRUCTIONS_AVAILABLE); - - cpuinfo_log_debug("divide present: %d", divide); - cpuinfo_log_debug("ext_cache present: %d", ext_cache); - cpuinfo_log_debug("vfp_registers present: %d", vfp_registers); - cpuinfo_log_debug("arm_v81 present: %d", arm_v81); -#endif + const bool dotprod = IsProcessorFeaturePresent(PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE) != 0; + cpuinfo_isa.dot = dotprod; - cpuinfo_log_debug("armv8 present: %d", armv8); - cpuinfo_log_debug("crypto present: %d", crypto); - cpuinfo_log_debug("load_store_atomic present: %d", load_store_atomic); - cpuinfo_log_debug("float_multiply_accumulate present: %d", float_multiply_accumulate); - cpuinfo_log_debug("crc32 present: %d", crc32); - cpuinfo_log_debug("float_emulated: %d", float_emulated); + SYSTEM_INFO system_info; + GetSystemInfo(&system_info); + switch (system_info.wProcessorLevel) { + case 0x803: // Kryo 385 Silver (Snapdragon 850) + cpuinfo_isa.fp16arith = dotprod; + cpuinfo_isa.rdm = dotprod; + break; + default: + // Assume that Dot Product support implies FP16 arithmetics and RDM support. + // ARM manuals don't guarantee that, but it holds in practice. + cpuinfo_isa.fp16arith = dotprod; + cpuinfo_isa.rdm = dotprod; + break; + } -#if CPUINFO_ARCH_ARM - cpuinfo_isa.armv8 = armv8; -#endif -#if CPUINFO_ARCH_ARM64 - cpuinfo_isa.atomics = load_store_atomic; -#endif - cpuinfo_isa.crc32 = crc32; /* Windows API reports all or nothing for cryptographic instructions. */ + const bool crypto = IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE) != 0; cpuinfo_isa.aes = crypto; cpuinfo_isa.sha1 = crypto; cpuinfo_isa.sha2 = crypto; cpuinfo_isa.pmull = crypto; - cpuinfo_isa.fp16arith = !float_emulated && float_multiply_accumulate; + + cpuinfo_isa.crc32 = IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE) != 0; } From 60480b7098c8ddc73d611285fc478dec66e4edf9 Mon Sep 17 00:00:00 2001 From: Marat Dukhan Date: Thu, 20 Jul 2023 12:14:25 -0600 Subject: [PATCH 16/60] Use AArch64-only big.LITTLE cores to detect AArch32 ISA --- src/arm/linux/aarch32-isa.c | 47 +++++++++++++++++++++++++++++++++---- 1 file changed, 42 insertions(+), 5 deletions(-) diff --git a/src/arm/linux/aarch32-isa.c b/src/arm/linux/aarch32-isa.c index 4fc2eb14..fb3fce27 100644 --- a/src/arm/linux/aarch32-isa.c +++ b/src/arm/linux/aarch32-isa.c @@ -68,11 +68,18 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( * - Processors with Cortex-A75 cores * - Processors with Cortex-A76 cores * - Processors with Cortex-A77 cores + * - Processors with Cortex-A78 cores + * - Processors with Cortex-A510 cores + * - Processors with Cortex-A710 cores + * - Processors with Cortex-A715 cores + * - Processors with Cortex-X1 cores + * - Processors with Cortex-X2 cores + * - Processors with Cortex-X3 cores * - Processors with Exynos M4 cores * - Processors with Exynos M5 cores * - Neoverse N1 cores - * - Neoverse V1 cores * - Neoverse N2 cores + * - Neoverse V1 cores */ if (chipset->series == cpuinfo_arm_chipset_series_samsung_exynos && chipset->model == 9810) { /* Only little cores of Exynos 9810 support FP16 & RDM */ @@ -83,11 +90,18 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( case UINT32_C(0x4100D060): /* Cortex-A65 */ case UINT32_C(0x4100D0A0): /* Cortex-A75 */ case UINT32_C(0x4100D0B0): /* Cortex-A76 */ + case UINT32_C(0x4100D0C0): /* Neoverse N1 */ case UINT32_C(0x4100D0D0): /* Cortex-A77 */ case UINT32_C(0x4100D0E0): /* Cortex-A76AE */ + case UINT32_C(0x4100D400): /* Neoverse V1 */ + case UINT32_C(0x4100D410): /* Cortex-A78 */ + case UINT32_C(0x4100D440): /* Cortex-X1 */ case UINT32_C(0x4100D460): /* Cortex-A510 */ case UINT32_C(0x4100D470): /* Cortex-A710 */ case UINT32_C(0x4100D480): /* Cortex-X2 */ + case UINT32_C(0x4100D490): /* Neoverse N2 */ + case UINT32_C(0x4100D4D0): /* Cortex-A715 */ + case UINT32_C(0x4100D4E0): /* Cortex-X3 */ case UINT32_C(0x4800D400): /* Cortex-A76 (HiSilicon) */ case UINT32_C(0x51008020): /* Kryo 385 Gold (Cortex-A75) */ case UINT32_C(0x51008030): /* Kryo 385 Silver (Cortex-A55) */ @@ -103,20 +117,43 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( /* * NEON VDOT instructions are not indicated in /proc/cpuinfo. - * Use a MIDR-based heuristic to whitelist processors known to support it. + * Use a MIDR-based heuristic to whitelist processors known to support it: + * - Processors with Cortex-A65 cores + * - Processors with Cortex-A76 cores + * - Processors with Cortex-A77 cores + * - Processors with Cortex-A78 cores + * - Processors with Cortex-A510 cores + * - Processors with Cortex-A710 cores + * - Processors with Cortex-A715 cores + * - Processors with Cortex-X1 cores + * - Processors with Cortex-X2 cores + * - Processors with Cortex-X3 cores + * - Processors with Exynos M4 cores + * - Processors with Exynos M5 cores + * - Neoverse N1 cores + * - Neoverse N2 cores + * - Neoverse V1 cores */ switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) { + case UINT32_C(0x4100D060): /* Cortex-A65 */ case UINT32_C(0x4100D0B0): /* Cortex-A76 */ + case UINT32_C(0x4100D0C0): /* Neoverse N1 */ case UINT32_C(0x4100D0D0): /* Cortex-A77 */ case UINT32_C(0x4100D0E0): /* Cortex-A76AE */ - case UINT32_C(0x4800D400): /* Cortex-A76 (HiSilicon) */ + case UINT32_C(0x4100D400): /* Neoverse V1 */ + case UINT32_C(0x4100D410): /* Cortex-A78 */ + case UINT32_C(0x4100D440): /* Cortex-X1 */ case UINT32_C(0x4100D460): /* Cortex-A510 */ case UINT32_C(0x4100D470): /* Cortex-A710 */ case UINT32_C(0x4100D480): /* Cortex-X2 */ + case UINT32_C(0x4100D490): /* Neoverse N2 */ + case UINT32_C(0x4100D4D0): /* Cortex-A715 */ + case UINT32_C(0x4100D4E0): /* Cortex-X3 */ + case UINT32_C(0x4800D400): /* Cortex-A76 (HiSilicon) */ case UINT32_C(0x51008040): /* Kryo 485 Gold (Cortex-A76) */ case UINT32_C(0x51008050): /* Kryo 485 Silver (Cortex-A55) */ - case UINT32_C(0x53000030): /* Exynos-M4 */ - case UINT32_C(0x53000040): /* Exynos-M5 */ + case UINT32_C(0x53000030): /* Exynos M4 */ + case UINT32_C(0x53000040): /* Exynos M5 */ isa->dot = true; break; case UINT32_C(0x4100D050): /* Cortex A55: revision 1 or later only */ From d7069b3919d1b65da5e8e333cb5817570a30b49a Mon Sep 17 00:00:00 2001 From: Marat Dukhan Date: Wed, 19 Jul 2023 22:01:53 -0600 Subject: [PATCH 17/60] Revert "Add support for some special qualcomm SoCs. (#67)" Hard-coding special Hardware strings should be used only as a last resort, as it bloats the library size and doesn't scale to newer chipsets. --- src/arm/cache.c | 1 - src/arm/linux/chipset.c | 91 ++++------------------------------------- 2 files changed, 7 insertions(+), 85 deletions(-) diff --git a/src/arm/cache.c b/src/arm/cache.c index 1a6dd381..190815d7 100644 --- a/src/arm/cache.c +++ b/src/arm/cache.c @@ -535,7 +535,6 @@ void cpuinfo_arm_decode_cache( l2_size = 1024 * 1024; break; case 660: - case 662: /* Snapdragon 660: 1 MB L2 (little cores only) */ l2_size = 1024 * 1024; break; diff --git a/src/arm/linux/chipset.c b/src/arm/linux/chipset.c index 7cc4feee..34237882 100644 --- a/src/arm/linux/chipset.c +++ b/src/arm/linux/chipset.c @@ -282,82 +282,6 @@ static bool match_sm( return true; } - -struct special_map_entry { - const char* platform; - uint16_t model; - uint8_t series; - char suffix; -}; - -static const struct special_map_entry qualcomm_hardware_map_entries[] = { - { - /* "Kona" -> Qualcomm Kona */ - .platform = "Kona", - .series = cpuinfo_arm_chipset_series_qualcomm_snapdragon, - .model = 865, - }, - { - /* "Bengal" -> Qualcomm Bengal */ - .platform = "Bengal", - .series = cpuinfo_arm_chipset_series_qualcomm_snapdragon, - .model = 662, - }, - { - /* "Bengalp" -> Qualcomm Bengalp */ - .platform = "Bengalp", - .series = cpuinfo_arm_chipset_series_qualcomm_snapdragon, - .model = 662, - }, - { - /* "Lito" -> Qualcomm Lito */ - .platform = "Lito", - .series = cpuinfo_arm_chipset_series_qualcomm_snapdragon, - .model = 765, - .suffix = 'G' - }, - { - /* "Lagoon" -> Qualcomm Lagoon */ - .platform = "Lagoon", - .series = cpuinfo_arm_chipset_series_qualcomm_snapdragon, - .model = 0, - }, -}; - - -int strcicmp(char const *a, char const *b) -{ - for (;; a++, b++) { - int d = tolower((unsigned char)*a) - tolower((unsigned char)*b); - if (d != 0 || !*a) - return d; - } -} - -static bool match_qualcomm_special( - const char* start, const char* end, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ - for (size_t i = 0; i < CPUINFO_COUNT_OF(qualcomm_hardware_map_entries); i++) { - int length = end - start; - if (strcicmp(qualcomm_hardware_map_entries[i].platform, start) == 0 && - qualcomm_hardware_map_entries[i].platform[length] == 0) - { - *chipset = (struct cpuinfo_arm_chipset) { - .vendor = chipset_series_vendor[qualcomm_hardware_map_entries[i].series], - .series = (enum cpuinfo_arm_chipset_series) qualcomm_hardware_map_entries[i].series, - .model = qualcomm_hardware_map_entries[i].model, - .suffix = { - [0] = qualcomm_hardware_map_entries[i].suffix, - }, - }; - return true; - } - } - return false; - -} - /** * Tries to match /Samsung Exynos\d{4}$/ signature (case-insensitive) for Samsung Exynos chipsets. * If match successful, extracts model information into \p chipset argument. @@ -1829,6 +1753,13 @@ static bool is_tegra(const char* start, const char* end) { return (length == 5 || start[5] == '3'); } +struct special_map_entry { + const char* platform; + uint16_t model; + uint8_t series; + char suffix; +}; + static const struct special_map_entry special_hardware_map_entries[] = { #if CPUINFO_ARCH_ARM { @@ -2387,14 +2318,6 @@ struct cpuinfo_arm_chipset cpuinfo_arm_linux_decode_chipset_from_proc_cpuinfo_ha (int) hardware_length, hardware); return chipset; } - - if (match_qualcomm_special(pos, hardware_end, &chipset)) { - cpuinfo_log_debug( - "matched Qualcomm signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) hardware_length, hardware); - return chipset; - } - } word_start = false; break; From f4c41699cd252e1c86d43054aead3830f49eae31 Mon Sep 17 00:00:00 2001 From: Lingkai Dong Date: Thu, 13 Jul 2023 16:23:22 +0100 Subject: [PATCH 18/60] Match the chip name of Microsoft Windows Dev Kit 2023 Change-Id: Ib6bc7dfd1b3b6282bde5798f9e225eb21ba673cc --- src/arm/windows/init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arm/windows/init.c b/src/arm/windows/init.c index 0ff797f3..79e60b38 100644 --- a/src/arm/windows/init.c +++ b/src/arm/windows/init.c @@ -68,7 +68,7 @@ static struct woa_chip_info woa_chips[] = { }, /* Microsoft Windows Dev Kit 2023 */ { - L"Snapdragon (TM) 8cx Gen 3 @ 3.0 GHz", + L"Snapdragon Compute Platform", woa_chip_name_microsoft_sq_3, { { From fb31a58205cdc1673205e1d9e27d837a44a29ad3 Mon Sep 17 00:00:00 2001 From: Lingkai Dong Date: Thu, 13 Jul 2023 17:04:13 +0100 Subject: [PATCH 19/60] Ensure initialization is done only once on Windows on Arm The function cpuinfo_arm_windows_init is called with InitOnceExecuteOnce (a Windows API) which ensures the init is called only once if it returns TRUE, even if multiple threads call it. However, if the init returns FALSE, it will be called again from other threads until TRUE is returned. In our case, init should happen only once regardless of success or failure, so cpuinfo_arm_windows_init should always return TRUE. The actual status of initialization is indicated by setting the global variable cpuinfo_is_initialized. This is consistent with how the x86 initialization is implemented. Change-Id: I016a988f10e8484f81c55838b182819e6cd8c880 --- src/arm/windows/init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arm/windows/init.c b/src/arm/windows/init.c index 79e60b38..3ed7471e 100644 --- a/src/arm/windows/init.c +++ b/src/arm/windows/init.c @@ -112,7 +112,7 @@ BOOL CALLBACK cpuinfo_arm_windows_init( cpuinfo_is_initialized = cpu_info_init_by_logical_sys_info(chip_info, chip_info->uarchs[0].vendor); - return (system_result && cpuinfo_is_initialized ? TRUE : FALSE); + return true; } bool get_core_uarch_for_efficiency( From d2a729c3093dab1ec4d6e8d8ce40a4c06cb013df Mon Sep 17 00:00:00 2001 From: Lingkai Dong Date: Fri, 14 Jul 2023 11:49:22 +0100 Subject: [PATCH 20/60] Fix reporting of processor found in Windows registry on Arm There was a bug that get_system_info_from_registry() always returned false regardless of what happened. To fix this, we could have returned the success or failure of the function. However, the status can also be inferred from whether the pointer to the chip info is NULL or not, so we remove the redundant return type for simplicity. Change-Id: If468000bf60f917892f776188a8fa29fcc0d4b7f --- src/arm/windows/init.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/src/arm/windows/init.c b/src/arm/windows/init.c index 3ed7471e..0fe09988 100644 --- a/src/arm/windows/init.c +++ b/src/arm/windows/init.c @@ -15,7 +15,7 @@ struct cpuinfo_arm_isa cpuinfo_isa; static void set_cpuinfo_isa_fields(void); -static bool get_system_info_from_registry( +static void get_system_info_from_registry( struct woa_chip_info** chip_info); static struct woa_chip_info woa_chip_unknown = { @@ -105,8 +105,8 @@ BOOL CALLBACK cpuinfo_arm_windows_init( set_cpuinfo_isa_fields(); - const bool system_result = get_system_info_from_registry(&chip_info); - if (!system_result) { + get_system_info_from_registry(&chip_info); + if (chip_info == NULL) { chip_info = &woa_chip_unknown; } @@ -182,10 +182,9 @@ static bool read_registry( return true; } -static bool get_system_info_from_registry( +static void get_system_info_from_registry( struct woa_chip_info** chip_info) { - bool result = false; char* text_buffer = NULL; LPCWSTR cpu0_subkey = L"HARDWARE\\DESCRIPTION\\System\\CentralProcessor\\0"; LPCWSTR chip_name_value = L"ProcessorNameString"; @@ -216,7 +215,6 @@ static bool get_system_info_from_registry( cleanup: HeapFree(heap, 0, text_buffer); text_buffer = NULL; - return result; } static void set_cpuinfo_isa_fields(void) From a00dacd6c72f6308a0b8edc636b758211ec62ee3 Mon Sep 17 00:00:00 2001 From: Lingkai Dong Date: Fri, 14 Jul 2023 15:49:08 +0100 Subject: [PATCH 21/60] Fix the size of uarchs array on Windows on Arm The number of elements in woa_chip_info.uarchs[] corresponds to the maximum number of efficiency classes, rather than the number of chip names. Change-Id: I2166dccf085a5de52e80577617c8112cc026c961 --- src/arm/windows/init.c | 3 --- src/arm/windows/windows-arm-init.h | 5 ++++- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/arm/windows/init.c b/src/arm/windows/init.c index 0fe09988..9cfb522f 100644 --- a/src/arm/windows/init.c +++ b/src/arm/windows/init.c @@ -9,9 +9,6 @@ #include "windows-arm-init.h" -/* Efficiency class = 0 means little core, while 1 means big core for now */ -#define MAX_WOA_VALID_EFFICIENCY_CLASSES 2 - struct cpuinfo_arm_isa cpuinfo_isa; static void set_cpuinfo_isa_fields(void); diff --git a/src/arm/windows/windows-arm-init.h b/src/arm/windows/windows-arm-init.h index a90cb45f..31181c03 100644 --- a/src/arm/windows/windows-arm-init.h +++ b/src/arm/windows/windows-arm-init.h @@ -1,5 +1,8 @@ #pragma once +/* Efficiency class = 0 means little core, while 1 means big core for now. */ +#define MAX_WOA_VALID_EFFICIENCY_CLASSES 2 + /* List of known and supported Windows on Arm SoCs/chips. */ enum woa_chip_name { woa_chip_name_microsoft_sq_1 = 0, @@ -23,7 +26,7 @@ struct core_info_by_chip_name { struct woa_chip_info { wchar_t* chip_name_string; enum woa_chip_name chip_name; - struct core_info_by_chip_name uarchs[woa_chip_name_last]; + struct core_info_by_chip_name uarchs[MAX_WOA_VALID_EFFICIENCY_CLASSES]; }; bool get_core_uarch_for_efficiency( From 6c983c50879759ac0ab6652fbea0052a72fc9a0e Mon Sep 17 00:00:00 2001 From: Lingkai Dong Date: Mon, 17 Jul 2023 13:38:13 +0100 Subject: [PATCH 22/60] Fix buffer overflow when counting uarchs on Windows on Arm Fix an issue that the index of the uarchs[] array is incremented at a wrong time which causes buffer overflow. For example, if uarchs[] has two elements, with the first four cores having one uarch and four cores having the other uarch, then * without this fix, the wrong counts are uarchs[0].core_count == 1 uarchs[1].core_count == 4 uarchs[2].core_count == 3 (this overflows uarchs[]) * with this fix, the correct counts are uarchs[0].core_count == 4 uarchs[1].core_count == 4 Change-Id: I9584aabf7859997f2826f8acb1b96aa3b8a5ee54 --- src/arm/windows/init-by-logical-sys-info.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/src/arm/windows/init-by-logical-sys-info.c b/src/arm/windows/init-by-logical-sys-info.c index 1b715edf..fe1b328d 100644 --- a/src/arm/windows/init-by-logical-sys-info.c +++ b/src/arm/windows/init-by-logical-sys-info.c @@ -283,16 +283,21 @@ bool cpu_info_init_by_logical_sys_info( goto clean_up; } prev_uarch = cpuinfo_uarch_unknown; - for (uint32_t i = 0, uarch_counter = 0; i < nr_of_cores; i++) { + for (uint32_t i = 0, uarch_index = 0; i < nr_of_cores; i++) { if (prev_uarch != cores[i].uarch) { + if (i != 0) { + uarch_index++; + } + if (uarch_index >= nr_of_uarchs) { + cpuinfo_log_error("more uarchs detected than reported"); + } prev_uarch = cores[i].uarch; - uarchs[uarch_counter].uarch = cores[i].uarch; - uarchs[uarch_counter].core_count = 1; - uarchs[uarch_counter].processor_count = cores[i].processor_count; - uarch_counter++; + uarchs[uarch_index].uarch = cores[i].uarch; + uarchs[uarch_index].core_count = 1; + uarchs[uarch_index].processor_count = cores[i].processor_count; } else if (prev_uarch != cpuinfo_uarch_unknown) { - uarchs[uarch_counter].core_count++; - uarchs[uarch_counter].processor_count += cores[i].processor_count; + uarchs[uarch_index].core_count++; + uarchs[uarch_index].processor_count += cores[i].processor_count; } } From 645c28c2b56ca5eee6ad0e676c7dbed2e7fe11fc Mon Sep 17 00:00:00 2001 From: Lingkai Dong Date: Mon, 17 Jul 2023 14:07:25 +0100 Subject: [PATCH 23/60] Fix char width mismatch on Windows on Arm Note: The data size reported by the last argument of RegGetValueW() is the number of bytes, not the number of wchar_t in the string. Change-Id: Ib57083791b5dc7ef97baf1e1e48bd070148a2032 --- src/arm/windows/init.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/arm/windows/init.c b/src/arm/windows/init.c index 9cfb522f..2a7d9e92 100644 --- a/src/arm/windows/init.c +++ b/src/arm/windows/init.c @@ -134,7 +134,7 @@ bool get_core_uarch_for_efficiency( static bool read_registry( LPCWSTR subkey, LPCWSTR value, - char** text_buffer) + wchar_t** text_buffer) { DWORD key_type = 0; DWORD data_size = 0; @@ -158,7 +158,7 @@ static bool read_registry( if (*text_buffer) { HeapFree(heap, 0, *text_buffer); } - *text_buffer = HeapAlloc(heap, HEAP_ZERO_MEMORY, data_size * sizeof(wchar_t)); + *text_buffer = HeapAlloc(heap, HEAP_ZERO_MEMORY, data_size); if (*text_buffer == NULL) { cpuinfo_log_error("Registry textbuffer allocation error"); return false; @@ -182,7 +182,7 @@ static bool read_registry( static void get_system_info_from_registry( struct woa_chip_info** chip_info) { - char* text_buffer = NULL; + wchar_t* text_buffer = NULL; LPCWSTR cpu0_subkey = L"HARDWARE\\DESCRIPTION\\System\\CentralProcessor\\0"; LPCWSTR chip_name_value = L"ProcessorNameString"; From 2ad28d1409ed42fc5f27ed5791a7319fffc6c2fc Mon Sep 17 00:00:00 2001 From: Lingkai Dong Date: Thu, 10 Aug 2023 10:42:55 +0100 Subject: [PATCH 24/60] Simplify registry helper functions for Windows on Arm The helper functions read_registry() and get_system_info_from_registry() now return pointers to requested data on success or NULL on failure. --- src/arm/windows/init.c | 50 +++++++++++++++++++----------------------- 1 file changed, 23 insertions(+), 27 deletions(-) diff --git a/src/arm/windows/init.c b/src/arm/windows/init.c index 2a7d9e92..ec835560 100644 --- a/src/arm/windows/init.c +++ b/src/arm/windows/init.c @@ -12,8 +12,7 @@ struct cpuinfo_arm_isa cpuinfo_isa; static void set_cpuinfo_isa_fields(void); -static void get_system_info_from_registry( - struct woa_chip_info** chip_info); +static struct woa_chip_info* get_system_info_from_registry(void); static struct woa_chip_info woa_chip_unknown = { L"Unknown", @@ -102,7 +101,7 @@ BOOL CALLBACK cpuinfo_arm_windows_init( set_cpuinfo_isa_fields(); - get_system_info_from_registry(&chip_info); + chip_info = get_system_info_from_registry(); if (chip_info == NULL) { chip_info = &woa_chip_unknown; } @@ -131,14 +130,14 @@ bool get_core_uarch_for_efficiency( /* Static helper functions */ -static bool read_registry( +static wchar_t* read_registry( LPCWSTR subkey, - LPCWSTR value, - wchar_t** text_buffer) + LPCWSTR value) { DWORD key_type = 0; DWORD data_size = 0; const DWORD flags = RRF_RT_REG_SZ; /* Only read strings (REG_SZ) */ + wchar_t *text_buffer = NULL; LSTATUS result = 0; HANDLE heap = GetProcessHeap(); @@ -152,16 +151,13 @@ static bool read_registry( &data_size); if (result != 0 || data_size == 0) { cpuinfo_log_error("Registry entry size read error"); - return false; + return NULL; } - if (*text_buffer) { - HeapFree(heap, 0, *text_buffer); - } - *text_buffer = HeapAlloc(heap, HEAP_ZERO_MEMORY, data_size); - if (*text_buffer == NULL) { + text_buffer = HeapAlloc(heap, HEAP_ZERO_MEMORY, data_size); + if (text_buffer == NULL) { cpuinfo_log_error("Registry textbuffer allocation error"); - return false; + return NULL; } result = RegGetValueW( @@ -170,48 +166,48 @@ static bool read_registry( value, flags, NULL, - *text_buffer, /* Write string in this destination buffer */ + text_buffer, /* Write string in this destination buffer */ &data_size); if (result != 0) { cpuinfo_log_error("Registry read error"); - return false; + HeapFree(heap, 0, text_buffer); + return NULL; } - return true; + return text_buffer; } -static void get_system_info_from_registry( - struct woa_chip_info** chip_info) +static struct woa_chip_info* get_system_info_from_registry(void) { wchar_t* text_buffer = NULL; LPCWSTR cpu0_subkey = L"HARDWARE\\DESCRIPTION\\System\\CentralProcessor\\0"; LPCWSTR chip_name_value = L"ProcessorNameString"; + struct woa_chip_info* chip_info = NULL; - *chip_info = NULL; HANDLE heap = GetProcessHeap(); /* Read processor model name from registry and find in the hard-coded list. */ - if (!read_registry(cpu0_subkey, chip_name_value, &text_buffer)) { + text_buffer = read_registry(cpu0_subkey, chip_name_value); + if (text_buffer == NULL) { cpuinfo_log_error("Registry read error"); - goto cleanup; + return NULL; } for (uint32_t i = 0; i < (uint32_t) woa_chip_name_last; i++) { size_t compare_length = wcsnlen(woa_chips[i].chip_name_string, CPUINFO_PACKAGE_NAME_MAX); int compare_result = wcsncmp(text_buffer, woa_chips[i].chip_name_string, compare_length); if (compare_result == 0) { - *chip_info = woa_chips+i; + chip_info = woa_chips+i; break; } } - if (*chip_info == NULL) { + if (chip_info == NULL) { /* No match was found, so print a warning and assign the unknown case. */ cpuinfo_log_error("Unknown chip model name '%ls'.\nPlease add new Windows on Arm SoC/chip support to arm/windows/init.c!", text_buffer); - goto cleanup; + } else { + cpuinfo_log_debug("detected chip model name: %s", chip_info->chip_name_string); } - cpuinfo_log_debug("detected chip model name: %s", (**chip_info).chip_name_string); -cleanup: HeapFree(heap, 0, text_buffer); - text_buffer = NULL; + return chip_info; } static void set_cpuinfo_isa_fields(void) From c13d0bbb266d200a13532b5915d704c30d21081b Mon Sep 17 00:00:00 2001 From: Marat Dukhan Date: Tue, 8 Aug 2023 21:39:59 -0600 Subject: [PATCH 25/60] Refactor reporting of Neoverse cores in cpu-info --- tools/cpu-info.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/tools/cpu-info.c b/tools/cpu-info.c index 05d13b90..f9e8b792 100644 --- a/tools/cpu-info.c +++ b/tools/cpu-info.c @@ -202,11 +202,13 @@ static const char* uarch_to_string(enum cpuinfo_uarch uarch) { case cpuinfo_uarch_cortex_x3: return "Cortex-X3"; case cpuinfo_uarch_neoverse_n1: - return "Neoverse-N1"; + return "Neoverse N1"; + case cpuinfo_uarch_neoverse_e1: + return "Neoverse E1"; case cpuinfo_uarch_neoverse_v1: - return "Neoverse-V1"; + return "Neoverse V1"; case cpuinfo_uarch_neoverse_n2: - return "Neoverse-N2"; + return "Neoverse N2"; case cpuinfo_uarch_scorpion: return "Scorpion"; case cpuinfo_uarch_krait: From 859edec185f1013e5f7d0463fa3a9415ecf2a8d8 Mon Sep 17 00:00:00 2001 From: Changming Sun Date: Mon, 14 Aug 2023 21:26:49 -0700 Subject: [PATCH 26/60] Update CMakeLists.txt: Add cmake 3.27 support --- CMakeLists.txt | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 338403ff..f71fbfd2 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -69,17 +69,17 @@ ENDIF() SET(CPUINFO_TARGET_PROCESSOR "${CMAKE_SYSTEM_PROCESSOR}") IF(IS_APPLE_OS AND CMAKE_OSX_ARCHITECTURES MATCHES "^(x86_64|arm64.*)$") SET(CPUINFO_TARGET_PROCESSOR "${CMAKE_OSX_ARCHITECTURES}") -ELSEIF(CMAKE_GENERATOR MATCHES "^Visual Studio " AND CMAKE_GENERATOR_PLATFORM) - IF(CMAKE_GENERATOR_PLATFORM STREQUAL "Win32") +ELSEIF(CMAKE_GENERATOR MATCHES "^Visual Studio " AND CMAKE_VS_PLATFORM_NAME) + IF(CMAKE_VS_PLATFORM_NAME STREQUAL "Win32") SET(CPUINFO_TARGET_PROCESSOR "x86") - ELSEIF(CMAKE_GENERATOR_PLATFORM STREQUAL "x64") + ELSEIF(CMAKE_VS_PLATFORM_NAME STREQUAL "x64") SET(CPUINFO_TARGET_PROCESSOR "x86_64") - ELSEIF(CMAKE_GENERATOR_PLATFORM STREQUAL "ARM64") + ELSEIF(CMAKE_VS_PLATFORM_NAME STREQUAL "ARM64") SET(CPUINFO_TARGET_PROCESSOR "arm64") - ELSEIF(CMAKE_GENERATOR_PLATFORM MATCHES "^(ARM64EC|arm64ec|ARM64E|arm64e)") + ELSEIF(CMAKE_VS_PLATFORM_NAME MATCHES "^(ARM64EC|arm64ec|ARM64E|arm64e)") SET(CPUINFO_TARGET_PROCESSOR "arm64") ELSE() - MESSAGE(FATAL_ERROR "Unsupported Visual Studio architecture \"${CMAKE_GENERATOR_PLATFORM}\"") + MESSAGE(FATAL_ERROR "Unsupported Visual Studio architecture \"${CMAKE_VS_PLATFORM_NAME}\"") ENDIF() ENDIF() From 0a85bfea98ea6b24c94439eee8cb2c0a41d32836 Mon Sep 17 00:00:00 2001 From: Marat Dukhan Date: Wed, 16 Aug 2023 13:06:54 -0600 Subject: [PATCH 27/60] Remove redudant ctype.h include --- src/arm/linux/chipset.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/arm/linux/chipset.c b/src/arm/linux/chipset.c index 34237882..7bddfb10 100644 --- a/src/arm/linux/chipset.c +++ b/src/arm/linux/chipset.c @@ -1,4 +1,3 @@ -#include #include #include #include From e4a50730900245f1c07b2f9ff5fff2b2da9e07f3 Mon Sep 17 00:00:00 2001 From: James Hilliard Date: Sun, 29 Jan 2023 16:55:08 -0700 Subject: [PATCH 28/60] Enable CXX only when needed for tests/benchmarks --- CMakeLists.txt | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index f71fbfd2..b5db1a7e 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -3,7 +3,7 @@ CMAKE_MINIMUM_REQUIRED(VERSION 3.5 FATAL_ERROR) # ---[ Setup project PROJECT( cpuinfo - LANGUAGES C CXX + LANGUAGES C ) # ---[ Options. @@ -114,6 +114,12 @@ ELSEIF(NOT CMAKE_SYSTEM_NAME MATCHES "^(Windows|WindowsStore|CYGWIN|MSYS|Darwin| ENDIF() ENDIF() +IF(CPUINFO_SUPPORTED_PLATFORM) + IF(CPUINFO_BUILD_MOCK_TESTS OR CPUINFO_BUILD_UNIT_TESTS OR CPUINFO_BUILD_BENCHMARKS) + ENABLE_LANGUAGE(CXX) + ENDIF() +ENDIF() + # ---[ Download deps SET(CONFU_DEPENDENCIES_SOURCE_DIR ${CMAKE_SOURCE_DIR}/deps CACHE PATH "Confu-style dependencies source directory") From baa1ee9df218a9adf568f39587c4339e1adf81a8 Mon Sep 17 00:00:00 2001 From: Marat Dukhan Date: Wed, 16 Aug 2023 13:50:50 -0600 Subject: [PATCH 29/60] Fix UB in load_u16le/load_u24le/load_u32le --- src/arm/linux/chipset.c | 17 +++-------------- 1 file changed, 3 insertions(+), 14 deletions(-) diff --git a/src/arm/linux/chipset.c b/src/arm/linux/chipset.c index 7bddfb10..5b52764a 100644 --- a/src/arm/linux/chipset.c +++ b/src/arm/linux/chipset.c @@ -37,29 +37,18 @@ static inline bool is_ascii_numeric(char c) { } static inline uint16_t load_u16le(const void* ptr) { -#if defined(__ARM_ARCH_7A__) || defined(__aarch64__) - return *((const uint16_t*) ptr); -#else const uint8_t* byte_ptr = (const uint8_t*) ptr; return ((uint16_t) byte_ptr[1] << 8) | (uint16_t) byte_ptr[0]; -#endif } static inline uint32_t load_u24le(const void* ptr) { -#if defined(__ARM_ARCH_7A__) || defined(__aarch64__) - return ((uint32_t) ((const uint8_t*) ptr)[2] << 16) | ((uint32_t) *((const uint16_t*) ptr)); -#else const uint8_t* byte_ptr = (const uint8_t*) ptr; - return ((uint32_t) byte_ptr[2] << 16) | ((uint32_t) byte_ptr[1] << 8) | (uint32_t) byte_ptr[0]; -#endif + return ((uint32_t) byte_ptr[2] << 16) | (uint32_t) load_u16le(byte_ptr + 1); } static inline uint32_t load_u32le(const void* ptr) { -#if defined(__ARM_ARCH_7A__) || defined(__aarch64__) - return *((const uint32_t*) ptr); -#else - return ((uint32_t) ((const uint8_t*) ptr)[3] << 24) | load_u24le(ptr); -#endif + const uint8_t* byte_ptr = (const uint8_t*) ptr; + return ((uint32_t) byte_ptr[3] << 24) | ((uint32_t) byte_ptr[2] << 16) | ((uint32_t) byte_ptr[1] << 8) | (uint32_t) byte_ptr[0]; } /* From 8dd681754889258cf134dd42362cd2a8d2c9028e Mon Sep 17 00:00:00 2001 From: Marat Dukhan Date: Wed, 16 Aug 2023 14:08:35 -0600 Subject: [PATCH 30/60] Workaround unimplemented GetMaximumProcessorGroupCount on WINE --- src/x86/windows/init.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/src/x86/windows/init.c b/src/x86/windows/init.c index 9a23bd71..274075c0 100644 --- a/src/x86/windows/init.c +++ b/src/x86/windows/init.c @@ -95,6 +95,15 @@ static void cpuinfo_x86_count_caches( *l4_count_ptr = l4_count; } +static bool cpuinfo_x86_windows_is_wine(void) { + HMODULE ntdll = GetModuleHandleW(L"ntdll.dll"); + if (ntdll == NULL) { + return false; + } + + return GetProcAddress(ntdll, "wine_get_version") != NULL; +} + BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PVOID* context) { struct cpuinfo_processor* processors = NULL; struct cpuinfo_core* cores = NULL; @@ -108,6 +117,7 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX processor_infos = NULL; HANDLE heap = GetProcessHeap(); + const bool is_wine = cpuinfo_x86_windows_is_wine(); struct cpuinfo_x86_processor x86_processor; ZeroMemory(&x86_processor, sizeof(x86_processor)); @@ -121,7 +131,8 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV x86_processor.topology.thread_bits_offset + x86_processor.topology.thread_bits_length, x86_processor.topology.core_bits_offset + x86_processor.topology.core_bits_length); - const uint32_t max_group_count = (uint32_t) GetMaximumProcessorGroupCount(); + /* WINE doesn't implement GetMaximumProcessorGroupCount and aborts when calling it */ + const uint32_t max_group_count = is_wine ? 1 : (uint32_t) GetMaximumProcessorGroupCount(); cpuinfo_log_debug("detected %"PRIu32" processor groups", max_group_count); uint32_t processors_count = 0; From 6bd16265d150d7d44f7daf22fe7fb559f22ed563 Mon Sep 17 00:00:00 2001 From: Marat Dukhan Date: Wed, 16 Aug 2023 14:31:28 -0600 Subject: [PATCH 31/60] Fix a bug in load_u24le introduced in #178 --- src/arm/linux/chipset.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/arm/linux/chipset.c b/src/arm/linux/chipset.c index 5b52764a..180f1a69 100644 --- a/src/arm/linux/chipset.c +++ b/src/arm/linux/chipset.c @@ -42,8 +42,7 @@ static inline uint16_t load_u16le(const void* ptr) { } static inline uint32_t load_u24le(const void* ptr) { - const uint8_t* byte_ptr = (const uint8_t*) ptr; - return ((uint32_t) byte_ptr[2] << 16) | (uint32_t) load_u16le(byte_ptr + 1); + return ((uint32_t) ((const uint8_t*) ptr)[2] << 16) | (uint32_t) load_u16le(ptr); } static inline uint32_t load_u32le(const void* ptr) { From 8eab20281d2648db5b88c47ace6540396435dbae Mon Sep 17 00:00:00 2001 From: Marat Dukhan Date: Wed, 16 Aug 2023 15:04:59 -0600 Subject: [PATCH 32/60] Remove redundant architecture version check in aarch32-isa.c --- src/arm/linux/aarch32-isa.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arm/linux/aarch32-isa.c b/src/arm/linux/aarch32-isa.c index fb3fce27..f3fcbacf 100644 --- a/src/arm/linux/aarch32-isa.c +++ b/src/arm/linux/aarch32-isa.c @@ -36,7 +36,7 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( if (architecture_version < 8) { const uint32_t armv8_features2_mask = CPUINFO_ARM_LINUX_FEATURE2_AES | CPUINFO_ARM_LINUX_FEATURE2_PMULL | CPUINFO_ARM_LINUX_FEATURE2_SHA1 | CPUINFO_ARM_LINUX_FEATURE2_SHA2 | CPUINFO_ARM_LINUX_FEATURE2_CRC32; - if ((features2 & armv8_features2_mask) != 0 && architecture_version < 8) { + if (features2 & armv8_features2_mask) { architecture_version = 8; } } From e00b4854ca4600022c4f942dee1bddf52bafc9cb Mon Sep 17 00:00:00 2001 From: Marat Dukhan Date: Wed, 16 Aug 2023 14:55:57 -0600 Subject: [PATCH 33/60] Detect Unisoc T-series chipsets --- src/arm/api.h | 2 ++ src/arm/linux/api.h | 2 +- src/arm/linux/chipset.c | 75 +++++++++++++++++++++++++++++++++++++++-- 3 files changed, 76 insertions(+), 3 deletions(-) diff --git a/src/arm/api.h b/src/arm/api.h index 48b99ddc..469c84bd 100644 --- a/src/arm/api.h +++ b/src/arm/api.h @@ -28,6 +28,7 @@ enum cpuinfo_arm_chipset_vendor { cpuinfo_arm_chipset_vendor_spreadtrum, cpuinfo_arm_chipset_vendor_telechips, cpuinfo_arm_chipset_vendor_texas_instruments, + cpuinfo_arm_chipset_vendor_unisoc, cpuinfo_arm_chipset_vendor_wondermedia, cpuinfo_arm_chipset_vendor_max, }; @@ -62,6 +63,7 @@ enum cpuinfo_arm_chipset_series { cpuinfo_arm_chipset_series_spreadtrum_sc, cpuinfo_arm_chipset_series_telechips_tcc, cpuinfo_arm_chipset_series_texas_instruments_omap, + cpuinfo_arm_chipset_series_unisoc_t, cpuinfo_arm_chipset_series_wondermedia_wm, cpuinfo_arm_chipset_series_max, }; diff --git a/src/arm/linux/api.h b/src/arm/linux/api.h index 1c09f827..2e849431 100644 --- a/src/arm/linux/api.h +++ b/src/arm/linux/api.h @@ -314,7 +314,7 @@ CPUINFO_INTERNAL bool cpuinfo_arm_linux_parse_proc_cpuinfo( struct cpuinfo_arm_isa isa[restrict static 1]); #endif -#ifdef __ANDROID__ +#if defined(__ANDROID__) CPUINFO_INTERNAL struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset( const struct cpuinfo_android_properties properties[restrict static 1], diff --git a/src/arm/linux/chipset.c b/src/arm/linux/chipset.c index 180f1a69..e70e6ede 100644 --- a/src/arm/linux/chipset.c +++ b/src/arm/linux/chipset.c @@ -84,6 +84,7 @@ static enum cpuinfo_arm_chipset_vendor chipset_series_vendor[cpuinfo_arm_chipset [cpuinfo_arm_chipset_series_spreadtrum_sc] = cpuinfo_arm_chipset_vendor_spreadtrum, [cpuinfo_arm_chipset_series_telechips_tcc] = cpuinfo_arm_chipset_vendor_telechips, [cpuinfo_arm_chipset_series_texas_instruments_omap] = cpuinfo_arm_chipset_vendor_texas_instruments, + [cpuinfo_arm_chipset_series_unisoc_t] = cpuinfo_arm_chipset_vendor_unisoc, [cpuinfo_arm_chipset_series_wondermedia_wm] = cpuinfo_arm_chipset_vendor_wondermedia, }; @@ -865,6 +866,64 @@ static bool match_sc( return true; } +/** + * Tries to match, case-sentitively, /Unisoc T\d{3,4}/ signature for Unisoc T chipset. + * If match successful, extracts model information into \p chipset argument. + * + * @param start - start of the platform identifier (/proc/cpuinfo Hardware string, ro.product.board, + * ro.board.platform, or ro.chipname) to match. + * @param end - end of the platform identifier (/proc/cpuinfo Hardware string, ro.product.board, + * ro.board.platform, or ro.chipname) to match. + * @param[out] chipset - location where chipset information will be stored upon a successful match. + * + * @returns true if signature matched, false otherwise. + */ +static bool match_t( + const char* start, const char* end, + struct cpuinfo_arm_chipset chipset[restrict static 1]) +{ + /* Expect 11-12 symbols: "Unisoc T" (8 symbols) + 3-4-digit model number */ + const size_t length = end - start; + switch (length) { + case 11: + case 12: + break; + default: + return false; + } + + /* Check that string starts with "Unisoc T". The first four characters are loaded as 32-bit little endian word */ + const uint32_t expected_unis = load_u32le(start); + if (expected_unis != UINT32_C(0x73696E55) /* "sinU" = reverse("Unis") */) { + return false; + } + + /* The next four characters are loaded as 32-bit little endian word */ + const uint32_t expected_oc_t = load_u32le(start + 4); + if (expected_oc_t != UINT32_C(0x5420636F) /* "T co" = reverse("oc T") */) { + return false; + } + + /* Validate and parse 3-4 digit model number */ + uint32_t model = 0; + for (uint32_t i = 8; i < length; i++) { + const uint32_t digit = (uint32_t) (uint8_t) start[i] - '0'; + if (digit >= 10) { + /* Not really a digit */ + return false; + } + model = model * 10 + digit; + } + + *chipset = (struct cpuinfo_arm_chipset) { + .vendor = cpuinfo_arm_chipset_vendor_unisoc, + .series = cpuinfo_arm_chipset_series_unisoc_t, + .model = model, + }; + return true; +} + + /** * Tries to match /lc\d{4}[a-z]?$/ signature for Leadcore LC chipsets. * If match successful, extracts model information into \p chipset argument. @@ -879,7 +938,7 @@ static bool match_lc( const char* start, const char* end, struct cpuinfo_arm_chipset chipset[restrict static 1]) { - /* Expect at 6-7 symbols: "lc" (2 symbols) + 4-digit model number + optional 1-letter suffix */ + /* Expect 6-7 symbols: "lc" (2 symbols) + 4-digit model number + optional 1-letter suffix */ const size_t length = end - start; switch (length) { case 6: @@ -2342,6 +2401,16 @@ struct cpuinfo_arm_chipset cpuinfo_arm_linux_decode_chipset_from_proc_cpuinfo_ha cpuinfo_log_debug( "matched Spreadtrum SC signature in /proc/cpuinfo Hardware string \"%.*s\"", (int) hardware_length, hardware); + + return chipset; + } + + /* Check Unisoc T signature */ + if (match_t(hardware, hardware_end, &chipset)) { + cpuinfo_log_debug( + "matched Unisoc T signature in /proc/cpuinfo Hardware string \"%.*s\"", + (int) hardware_length, hardware); + return chipset; } @@ -3405,6 +3474,7 @@ static const char* chipset_vendor_string[cpuinfo_arm_chipset_vendor_max] = { [cpuinfo_arm_chipset_vendor_spreadtrum] = "Spreadtrum", [cpuinfo_arm_chipset_vendor_telechips] = "Telechips", [cpuinfo_arm_chipset_vendor_texas_instruments] = "Texas Instruments", + [cpuinfo_arm_chipset_vendor_unisoc] = "Unisoc", [cpuinfo_arm_chipset_vendor_wondermedia] = "WonderMedia", }; @@ -3439,6 +3509,7 @@ static const char* chipset_series_string[cpuinfo_arm_chipset_series_max] = { [cpuinfo_arm_chipset_series_spreadtrum_sc] = "SC", [cpuinfo_arm_chipset_series_telechips_tcc] = "TCC", [cpuinfo_arm_chipset_series_texas_instruments_omap] = "OMAP", + [cpuinfo_arm_chipset_series_unisoc_t] = "T", [cpuinfo_arm_chipset_series_wondermedia_wm] = "WM", }; @@ -3472,7 +3543,7 @@ void cpuinfo_arm_chipset_to_string( } } -#ifdef __ANDROID__ +#if defined(__ANDROID__) static inline struct cpuinfo_arm_chipset disambiguate_qualcomm_chipset( const struct cpuinfo_arm_chipset proc_cpuinfo_hardware_chipset[restrict static 1], const struct cpuinfo_arm_chipset ro_product_board_chipset[restrict static 1], From c15d537323081f188e4643f31bd93e6732992311 Mon Sep 17 00:00:00 2001 From: Marat Dukhan Date: Wed, 16 Aug 2023 15:25:24 -0600 Subject: [PATCH 34/60] Remove redundant newline after match_t --- src/arm/linux/chipset.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/arm/linux/chipset.c b/src/arm/linux/chipset.c index e70e6ede..0e9191fd 100644 --- a/src/arm/linux/chipset.c +++ b/src/arm/linux/chipset.c @@ -923,7 +923,6 @@ static bool match_t( return true; } - /** * Tries to match /lc\d{4}[a-z]?$/ signature for Leadcore LC chipsets. * If match successful, extracts model information into \p chipset argument. From 3c8583da7fe36c9fe1367cf18907b479c115759d Mon Sep 17 00:00:00 2001 From: Marat Dukhan Date: Wed, 16 Aug 2023 15:36:09 -0600 Subject: [PATCH 35/60] Don't consider Cortex-A65 in AArch32 ISA detection Cortex-A65 is AArch64-only and not paired with AArch32-capable cores --- src/arm/linux/aarch32-isa.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/arm/linux/aarch32-isa.c b/src/arm/linux/aarch32-isa.c index f3fcbacf..1b9683ea 100644 --- a/src/arm/linux/aarch32-isa.c +++ b/src/arm/linux/aarch32-isa.c @@ -64,7 +64,6 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( * NEON FP16 compute extension and VQRDMLAH/VQRDMLSH instructions are not indicated in /proc/cpuinfo. * Use a MIDR-based heuristic to whitelist processors known to support it: * - Processors with Cortex-A55 cores - * - Processors with Cortex-A65 cores * - Processors with Cortex-A75 cores * - Processors with Cortex-A76 cores * - Processors with Cortex-A77 cores @@ -87,7 +86,6 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( } else { switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) { case UINT32_C(0x4100D050): /* Cortex-A55 */ - case UINT32_C(0x4100D060): /* Cortex-A65 */ case UINT32_C(0x4100D0A0): /* Cortex-A75 */ case UINT32_C(0x4100D0B0): /* Cortex-A76 */ case UINT32_C(0x4100D0C0): /* Neoverse N1 */ @@ -118,7 +116,6 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( /* * NEON VDOT instructions are not indicated in /proc/cpuinfo. * Use a MIDR-based heuristic to whitelist processors known to support it: - * - Processors with Cortex-A65 cores * - Processors with Cortex-A76 cores * - Processors with Cortex-A77 cores * - Processors with Cortex-A78 cores @@ -135,7 +132,6 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( * - Neoverse V1 cores */ switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) { - case UINT32_C(0x4100D060): /* Cortex-A65 */ case UINT32_C(0x4100D0B0): /* Cortex-A76 */ case UINT32_C(0x4100D0C0): /* Neoverse N1 */ case UINT32_C(0x4100D0D0): /* Cortex-A77 */ From dce131b242c5282e2e5ee254364ff2ea7e1b0999 Mon Sep 17 00:00:00 2001 From: Marat Dukhan Date: Wed, 16 Aug 2023 15:46:07 -0600 Subject: [PATCH 36/60] Work around faulty implementations of NEON DOT instructions Prevent detection of NEON DOT instruction set on Spreadtrum SC9863A and Unisoc T310, where these instructions occasionally trigger SIGILL --- src/arm/linux/aarch32-isa.c | 60 ++++++++++++++++++++----------------- 1 file changed, 33 insertions(+), 27 deletions(-) diff --git a/src/arm/linux/aarch32-isa.c b/src/arm/linux/aarch32-isa.c index 1b9683ea..e814cb69 100644 --- a/src/arm/linux/aarch32-isa.c +++ b/src/arm/linux/aarch32-isa.c @@ -131,33 +131,39 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( * - Neoverse N2 cores * - Neoverse V1 cores */ - switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) { - case UINT32_C(0x4100D0B0): /* Cortex-A76 */ - case UINT32_C(0x4100D0C0): /* Neoverse N1 */ - case UINT32_C(0x4100D0D0): /* Cortex-A77 */ - case UINT32_C(0x4100D0E0): /* Cortex-A76AE */ - case UINT32_C(0x4100D400): /* Neoverse V1 */ - case UINT32_C(0x4100D410): /* Cortex-A78 */ - case UINT32_C(0x4100D440): /* Cortex-X1 */ - case UINT32_C(0x4100D460): /* Cortex-A510 */ - case UINT32_C(0x4100D470): /* Cortex-A710 */ - case UINT32_C(0x4100D480): /* Cortex-X2 */ - case UINT32_C(0x4100D490): /* Neoverse N2 */ - case UINT32_C(0x4100D4D0): /* Cortex-A715 */ - case UINT32_C(0x4100D4E0): /* Cortex-X3 */ - case UINT32_C(0x4800D400): /* Cortex-A76 (HiSilicon) */ - case UINT32_C(0x51008040): /* Kryo 485 Gold (Cortex-A76) */ - case UINT32_C(0x51008050): /* Kryo 485 Silver (Cortex-A55) */ - case UINT32_C(0x53000030): /* Exynos M4 */ - case UINT32_C(0x53000040): /* Exynos M5 */ - isa->dot = true; - break; - case UINT32_C(0x4100D050): /* Cortex A55: revision 1 or later only */ - isa->dot = !!(midr_get_variant(midr) >= 1); - break; - case UINT32_C(0x4100D0A0): /* Cortex A75: revision 2 or later only */ - isa->dot = !!(midr_get_variant(midr) >= 2); - break; + if (chipset->series == cpuinfo_arm_chipset_series_spreadtrum_sc && chipset->model == 9863) { + cpuinfo_log_warning("VDOT instructions disabled: cause occasional SIGILL on Spreadtrum SC9863A"); + } else if (chipset->series == cpuinfo_arm_chipset_series_unisoc_t && chipset->model == 310) { + cpuinfo_log_warning("VDOT instructions disabled: cause occasional SIGILL on Unisoc T310"); + } else { + switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) { + case UINT32_C(0x4100D0B0): /* Cortex-A76 */ + case UINT32_C(0x4100D0C0): /* Neoverse N1 */ + case UINT32_C(0x4100D0D0): /* Cortex-A77 */ + case UINT32_C(0x4100D0E0): /* Cortex-A76AE */ + case UINT32_C(0x4100D400): /* Neoverse V1 */ + case UINT32_C(0x4100D410): /* Cortex-A78 */ + case UINT32_C(0x4100D440): /* Cortex-X1 */ + case UINT32_C(0x4100D460): /* Cortex-A510 */ + case UINT32_C(0x4100D470): /* Cortex-A710 */ + case UINT32_C(0x4100D480): /* Cortex-X2 */ + case UINT32_C(0x4100D490): /* Neoverse N2 */ + case UINT32_C(0x4100D4D0): /* Cortex-A715 */ + case UINT32_C(0x4100D4E0): /* Cortex-X3 */ + case UINT32_C(0x4800D400): /* Cortex-A76 (HiSilicon) */ + case UINT32_C(0x51008040): /* Kryo 485 Gold (Cortex-A76) */ + case UINT32_C(0x51008050): /* Kryo 485 Silver (Cortex-A55) */ + case UINT32_C(0x53000030): /* Exynos M4 */ + case UINT32_C(0x53000040): /* Exynos M5 */ + isa->dot = true; + break; + case UINT32_C(0x4100D050): /* Cortex A55: revision 1 or later only */ + isa->dot = !!(midr_get_variant(midr) >= 1); + break; + case UINT32_C(0x4100D0A0): /* Cortex A75: revision 2 or later only */ + isa->dot = !!(midr_get_variant(midr) >= 2); + break; + } } } else { /* ARMv7 or lower: use feature flags to detect optional features */ From 9df83faa65d4c5db3ad6630cbb944a0b4e5e4a84 Mon Sep 17 00:00:00 2001 From: Marat Dukhan Date: Wed, 16 Aug 2023 16:03:06 -0600 Subject: [PATCH 37/60] Support building for ARM Linux with GLibC older than 2.16 --- src/arm/linux/hwcap.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/src/arm/linux/hwcap.c b/src/arm/linux/hwcap.c index 35e9994f..984ab43c 100644 --- a/src/arm/linux/hwcap.c +++ b/src/arm/linux/hwcap.c @@ -1,3 +1,4 @@ +#include #include #include @@ -15,7 +16,8 @@ #include #include -#if CPUINFO_ARCH_ARM64 || CPUINFO_ARCH_ARM && !defined(__ANDROID__) +#if CPUINFO_ARCH_ARM64 || CPUINFO_ARCH_ARM && \ + defined(__GLIBC__) && defined(__GLIBC_MINOR__) && (__GLIBC__ > 2 || __GLIBC__ == 2 && __GLIBC_MINOR__ >= 16) #include #else #define AT_HWCAP 16 @@ -74,11 +76,13 @@ libc = NULL; } return getauxval != NULL; - #else - /* GNU/Linux: getauxval is always supported */ + #elif defined(__GLIBC__) && defined(__GLIBC_MINOR__) && (__GLIBC__ > 2 || __GLIBC__ == 2 && __GLIBC_MINOR__ >= 16) + /* GNU/Linux: getauxval is supported since glibc-2.16 */ *hwcap = getauxval(AT_HWCAP); *hwcap2 = getauxval(AT_HWCAP2); return true; + #else + return false; #endif } From 959002f82d7962a473d8bf301845f2af720e0aa4 Mon Sep 17 00:00:00 2001 From: Marat Dukhan Date: Wed, 16 Aug 2023 16:30:44 -0600 Subject: [PATCH 38/60] Include intrin.h MSVC header in cpuinfo/utils.h --- src/cpuinfo/utils.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/cpuinfo/utils.h b/src/cpuinfo/utils.h index 157baad9..6cfaca7b 100644 --- a/src/cpuinfo/utils.h +++ b/src/cpuinfo/utils.h @@ -1,5 +1,8 @@ #pragma once +#ifdef _MSC_VER +#include +#endif #include From 76d5e8f5b563daa65340a60fce0e9aec73a936df Mon Sep 17 00:00:00 2001 From: Paolo <142514942+paolotricerri@users.noreply.github.com> Date: Thu, 19 Oct 2023 20:37:38 +0100 Subject: [PATCH 39/60] Add support for Arm Neoverse V2 (#194) --- README.md | 2 +- include/cpuinfo.h | 2 ++ src/arm/cache.c | 51 +++++++++++++++++-------------------- src/arm/linux/aarch32-isa.c | 4 +++ src/arm/linux/aarch64-isa.c | 3 +++ src/arm/uarch.c | 7 +++-- tools/cpu-info.c | 2 ++ 7 files changed, 40 insertions(+), 31 deletions(-) diff --git a/README.md b/README.md index b76601ad..82cadea6 100644 --- a/README.md +++ b/README.md @@ -272,7 +272,7 @@ LDFLAGS+= $(pkg-config --libs libcpuinfo) - [x] AMD-designed x86/x86-64 cores (up to Puma/Jaguar and Zen 2) - [ ] VIA-designed x86/x86-64 cores - [ ] Other x86 cores (DM&P, RDC, Transmeta, Cyrix, Rise) - - [x] ARM-designed ARM cores (up to Cortex-A55, Cortex-A77, and Neoverse E1/V1/N2) + - [x] ARM-designed ARM cores (up to Cortex-A55, Cortex-A77, and Neoverse E1/V1/N2/V2) - [x] Qualcomm-designed ARM cores (Scorpion, Krait, and Kryo) - [x] Nvidia-designed ARM cores (Denver and Carmel) - [x] Samsung-designed ARM cores (Exynos) diff --git a/include/cpuinfo.h b/include/cpuinfo.h index c46b65e9..f1440a73 100644 --- a/include/cpuinfo.h +++ b/include/cpuinfo.h @@ -432,6 +432,8 @@ enum cpuinfo_uarch { cpuinfo_uarch_neoverse_v1 = 0x00300402, /** ARM Neoverse N2. */ cpuinfo_uarch_neoverse_n2 = 0x00300403, + /** ARM Neoverse V2. */ + cpuinfo_uarch_neoverse_v2 = 0x00300404, /** ARM Cortex-X1. */ cpuinfo_uarch_cortex_x1 = 0x00300501, diff --git a/src/arm/cache.c b/src/arm/cache.c index 190815d7..953abb72 100644 --- a/src/arm/cache.c +++ b/src/arm/cache.c @@ -1241,35 +1241,29 @@ void cpuinfo_arm_decode_cache( case cpuinfo_uarch_neoverse_n1: case cpuinfo_uarch_neoverse_v1: case cpuinfo_uarch_neoverse_n2: + case cpuinfo_uarch_neoverse_v2: { - /* - * ARM Neoverse-n1 Core Technical Reference Manual - * A6.1. About the L1 memory system - * The L1 memory system consists of separate instruction and data caches. Both have a fixed size of 64KB. - * - * A6.1.1 L1 instruction-side memory system - * The L1 instruction memory system has the following key features: - * - Virtually Indexed, Physically Tagged (VIPT), which behaves as a Physically Indexed, - * Physically Tagged (PIPT) 4-way set-associative L1 data cache. - * - Fixed cache line length of 64 bytes. - * - * A6.1.2 L1 data-side memory system - * The L1 data memory system has the following features: - * - Virtually Indexed, Physically Tagged (VIPT), which behaves as a Physically Indexed, - * Physically Tagged (PIPT) 4-way set-associative L1 data cache. - * - Fixed cache line length of 64 bytes. - * - Pseudo-LRU cache replacement policy. - * - * A7.1 About the L2 memory system - * The L2 memory subsystem consist of: - * - An 8-way set associative L2 cache with a configurable size of 256KB, 512KB, or 1024KB. Cache lines - * have a fixed length of 64 bytes. - * - Strictly inclusive with L1 data cache. - * - When configured with instruction cache hardware coherency, strictly inclusive with L1 instruction cache. - * - When configured without instruction cache hardware coherency, weakly inclusive with L1 instruction cache. - */ - - const uint32_t min_l2_size_KB= 256; + /* + * The specifications here below are taken from the + * Arm Core Technical Reference Manuals for + * - Neoverse N1: https://developer.arm.com/documentation/100616/0401/?lang=en + * - Neoverse N2: https://developer.arm.com/documentation/102099/0003/?lang=en + * - Neoverse V1: https://developer.arm.com/documentation/101427/0102/?lang=en + * - Neoverse V2: https://developer.arm.com/documentation/102375/0002/?lang=en + * + * All four Arm architectures have L1 memory system with instruction and data caches, + * both of fixed size of 64KB. The instruction side memory system is 4-way set associative + * with a cache line length of 64 bytes. The data cache is also 4-way set associative with + * a cache line length of 64 bytes. + * + * The L2 memory system differs across the four Architectures in the minimum + * length of the L2 cache. Namely: + * - Arm Neoverse N1/N2/V1 have a L2 cache of configurable size of 256KB, 512KB, or 1024KB + * - Arm Neoverse V2 has a L2 cache of configurable size of 1MB or 2MB + * For all four architectures, the L2 cache is 8-way set associative + * For all other information, please refer to the technical manuals linked above + */ + const uint32_t min_l2_size_KB = uarch == cpuinfo_uarch_neoverse_v2 ? 1024 : 256; const uint32_t min_l3_size_KB = 0; *l1i = (struct cpuinfo_cache) { @@ -1715,6 +1709,7 @@ uint32_t cpuinfo_arm_compute_max_cache_size(const struct cpuinfo_processor* proc case cpuinfo_uarch_neoverse_n1: case cpuinfo_uarch_neoverse_v1: case cpuinfo_uarch_neoverse_n2: + case cpuinfo_uarch_neoverse_v2: case cpuinfo_uarch_cortex_a75: case cpuinfo_uarch_cortex_a76: case cpuinfo_uarch_exynos_m4: diff --git a/src/arm/linux/aarch32-isa.c b/src/arm/linux/aarch32-isa.c index e814cb69..65c7826f 100644 --- a/src/arm/linux/aarch32-isa.c +++ b/src/arm/linux/aarch32-isa.c @@ -79,6 +79,7 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( * - Neoverse N1 cores * - Neoverse N2 cores * - Neoverse V1 cores + * - Neoverse V2 cores */ if (chipset->series == cpuinfo_arm_chipset_series_samsung_exynos && chipset->model == 9810) { /* Only little cores of Exynos 9810 support FP16 & RDM */ @@ -100,6 +101,7 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( case UINT32_C(0x4100D490): /* Neoverse N2 */ case UINT32_C(0x4100D4D0): /* Cortex-A715 */ case UINT32_C(0x4100D4E0): /* Cortex-X3 */ + case UINT32_C(0x4100D4F0): /* Neoverse V2 */ case UINT32_C(0x4800D400): /* Cortex-A76 (HiSilicon) */ case UINT32_C(0x51008020): /* Kryo 385 Gold (Cortex-A75) */ case UINT32_C(0x51008030): /* Kryo 385 Silver (Cortex-A55) */ @@ -130,6 +132,7 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( * - Neoverse N1 cores * - Neoverse N2 cores * - Neoverse V1 cores + * - Neoverse V2 cores */ if (chipset->series == cpuinfo_arm_chipset_series_spreadtrum_sc && chipset->model == 9863) { cpuinfo_log_warning("VDOT instructions disabled: cause occasional SIGILL on Spreadtrum SC9863A"); @@ -150,6 +153,7 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( case UINT32_C(0x4100D490): /* Neoverse N2 */ case UINT32_C(0x4100D4D0): /* Cortex-A715 */ case UINT32_C(0x4100D4E0): /* Cortex-X3 */ + case UINT32_C(0x4100D4F0): /* Neoverse V2 */ case UINT32_C(0x4800D400): /* Cortex-A76 (HiSilicon) */ case UINT32_C(0x51008040): /* Kryo 485 Gold (Cortex-A76) */ case UINT32_C(0x51008050): /* Kryo 485 Silver (Cortex-A55) */ diff --git a/src/arm/linux/aarch64-isa.c b/src/arm/linux/aarch64-isa.c index 9d4aebbb..5dd4c4d0 100644 --- a/src/arm/linux/aarch64-isa.c +++ b/src/arm/linux/aarch64-isa.c @@ -43,6 +43,7 @@ void cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo( * - Neoverse N1 cores * - Neoverse V1 cores * - Neoverse N2 cores + * - Neoverse V2 cores */ if (chipset->series == cpuinfo_arm_chipset_series_samsung_exynos && chipset->model == 9810) { /* Exynos 9810 reports that it supports FP16 compute, but in fact only little cores do */ @@ -59,6 +60,7 @@ void cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo( case UINT32_C(0x4100D0E0): /* Cortex-A76AE */ case UINT32_C(0x4100D400): /* Neoverse V1 */ case UINT32_C(0x4100D490): /* Neoverse N2 */ + case UINT32_C(0x4100D4F0): /* Neoverse V2 */ case UINT32_C(0x4800D400): /* Cortex-A76 (HiSilicon) */ case UINT32_C(0x51008020): /* Kryo 385 Gold (Cortex-A75) */ case UINT32_C(0x51008030): /* Kryo 385 Silver (Cortex-A55) */ @@ -100,6 +102,7 @@ void cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo( case UINT32_C(0x4100D400): /* Neoverse V1 */ case UINT32_C(0x4100D490): /* Neoverse N2 */ case UINT32_C(0x4100D4A0): /* Neoverse E1 */ + case UINT32_C(0x4100D4F0): /* Neoverse V2 */ case UINT32_C(0x4800D400): /* Cortex-A76 (HiSilicon) */ case UINT32_C(0x51008040): /* Kryo 485 Gold (Cortex-A76) */ case UINT32_C(0x51008050): /* Kryo 485 Silver (Cortex-A55) */ diff --git a/src/arm/uarch.c b/src/arm/uarch.c index e843a5b8..f1dd4934 100644 --- a/src/arm/uarch.c +++ b/src/arm/uarch.c @@ -89,7 +89,7 @@ void cpuinfo_arm_decode_vendor_uarch( case 0xD0E: /* Cortex-A76AE */ *uarch = cpuinfo_uarch_cortex_a76; break; - case 0xD40: + case 0xD40: /* Neoverse V1 */ *uarch = cpuinfo_uarch_neoverse_v1; break; case 0xD41: /* Cortex-A78 */ @@ -107,7 +107,7 @@ void cpuinfo_arm_decode_vendor_uarch( case 0xD48: /* Cortex-X2 */ *uarch = cpuinfo_uarch_cortex_x2; break; - case 0xD49: + case 0xD49: /* Neoverse N2 */ *uarch = cpuinfo_uarch_neoverse_n2; break; #if CPUINFO_ARCH_ARM64 @@ -121,6 +121,9 @@ void cpuinfo_arm_decode_vendor_uarch( case 0xD4E: /* Cortex-X3 */ *uarch = cpuinfo_uarch_cortex_x3; break; + case 0xD4F: /* Neoverse V2 */ + *uarch = cpuinfo_uarch_neoverse_v2; + break; default: switch (midr_get_part(midr) >> 8) { #if CPUINFO_ARCH_ARM diff --git a/tools/cpu-info.c b/tools/cpu-info.c index f9e8b792..5b82dd0a 100644 --- a/tools/cpu-info.c +++ b/tools/cpu-info.c @@ -209,6 +209,8 @@ static const char* uarch_to_string(enum cpuinfo_uarch uarch) { return "Neoverse V1"; case cpuinfo_uarch_neoverse_n2: return "Neoverse N2"; + case cpuinfo_uarch_neoverse_v2: + return "Neoverse V2"; case cpuinfo_uarch_scorpion: return "Scorpion"; case cpuinfo_uarch_krait: From d6860c477c99f1fce9e28eb206891af3c0e1a1d7 Mon Sep 17 00:00:00 2001 From: Quentin Khan Date: Sat, 4 Nov 2023 01:50:14 +0100 Subject: [PATCH 40/60] Add detection of Intel x86 AVX-VNNI instructions. (#196) Tested using Intel SDE: ``` bash scripts/local-build.sh OPTIONS=() PLATFORMS=() OPTIONS+=(-quark); PLATFORMS+=("Quark") OPTIONS+=(-p4); PLATFORMS+=("Pentium4") OPTIONS+=(-p4p); PLATFORMS+=("Pentium4 Prescott") OPTIONS+=(-mrm); PLATFORMS+=("Merom") OPTIONS+=(-pnr); PLATFORMS+=("Penryn") OPTIONS+=(-nhm); PLATFORMS+=("Nehalem") OPTIONS+=(-wsm); PLATFORMS+=("Westmere") OPTIONS+=(-snb); PLATFORMS+=("Sandy Bridge") OPTIONS+=(-ivb); PLATFORMS+=("Ivy Bridge") OPTIONS+=(-hsw); PLATFORMS+=("Haswell") OPTIONS+=(-bdw); PLATFORMS+=("Broadwell") OPTIONS+=(-slt); PLATFORMS+=("Saltwell") OPTIONS+=(-slm); PLATFORMS+=("Silvermont") OPTIONS+=(-glm); PLATFORMS+=("Goldmont") OPTIONS+=(-glp); PLATFORMS+=("Goldmont Plus") OPTIONS+=(-tnt); PLATFORMS+=("Tremont") OPTIONS+=(-snr); PLATFORMS+=("Snow Ridge") OPTIONS+=(-skl); PLATFORMS+=("Skylake") OPTIONS+=(-cnl); PLATFORMS+=("Cannon Lake") OPTIONS+=(-icl); PLATFORMS+=("Ice Lake") OPTIONS+=(-skx); PLATFORMS+=("Skylake server") OPTIONS+=(-clx); PLATFORMS+=("Cascade Lake") OPTIONS+=(-cpx); PLATFORMS+=("Cooper Lake") OPTIONS+=(-icx); PLATFORMS+=("Ice Lake server") OPTIONS+=(-knl); PLATFORMS+=("Knights landing") OPTIONS+=(-knm); PLATFORMS+=("Knights mill") OPTIONS+=(-tgl); PLATFORMS+=("Tiger Lake") OPTIONS+=(-adl); PLATFORMS+=("Alder Lake") OPTIONS+=(-mtl); PLATFORMS+=("Meteor Lake") OPTIONS+=(-rpl); PLATFORMS+=("Raptor Lake") OPTIONS+=(-spr); PLATFORMS+=("Sapphire Rapids") OPTIONS+=(-gnr); PLATFORMS+=("Granite Rapids") OPTIONS+=(-srf); PLATFORMS+=("Sierra Forest") OPTIONS+=(-grr); PLATFORMS+=("Grand Ridge") OPTIONS+=(-future); PLATFORMS+=("Future chip") SDE_BIN="path/to/sde" for I in "${!PLATFORMS[@]}"; do echo "${PLATFORMS["${I}"]}" "${SDE_BIN}" "${OPTIONS[$I]}" -- ./build/local/isa-info | grep "AVXVNNI" done ``` Result: ``` Quark [error] Merom [error] Penryn [error] Nehalem [error] Westmere AVXVNNI: no Sandy Bridge AVXVNNI: no Ivy Bridge AVXVNNI: no Haswell AVXVNNI: no Broadwell AVXVNNI: no Saltwell [error] Silvermont AVXVNNI: no Goldmont AVXVNNI: no Goldmont Plus AVXVNNI: no Tremont AVXVNNI: no Snow Ridge AVXVNNI: no Skylake AVXVNNI: no Cannon Lake AVXVNNI: no Ice Lake AVXVNNI: no Skylake server AVXVNNI: no Cascade Lake AVXVNNI: no Cooper Lake AVXVNNI: no Ice Lake server AVXVNNI: no Knights landing AVXVNNI: no Knights mill AVXVNNI: no Tiger Lake AVXVNNI: no Alder Lake AVXVNNI: yes Meteor Lake AVXVNNI: yes Raptor Lake AVXVNNI: yes Sapphire Rapids AVXVNNI: yes Granite Rapids AVXVNNI: yes Sierra Forest AVXVNNI: yes Grand Ridge AVXVNNI: yes Future chip AVXVNNI: yes ``` --- include/cpuinfo.h | 9 +++++++++ src/x86/isa.c | 6 ++++++ tools/isa-info.c | 1 + 3 files changed, 16 insertions(+) diff --git a/include/cpuinfo.h b/include/cpuinfo.h index f1440a73..dfb535f1 100644 --- a/include/cpuinfo.h +++ b/include/cpuinfo.h @@ -729,6 +729,7 @@ void CPUINFO_ABI cpuinfo_deinitialize(void); bool sse4a; bool misaligned_sse; bool avx; + bool avxvnni; bool fma3; bool fma4; bool xop; @@ -1076,6 +1077,14 @@ static inline bool cpuinfo_has_x86_avx(void) { #endif } +static inline bool cpuinfo_has_x86_avxvnni(void) { + #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avxvnni; + #else + return false; + #endif +} + static inline bool cpuinfo_has_x86_fma3(void) { #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 return cpuinfo_isa.fma3; diff --git a/src/x86/isa.c b/src/x86/isa.c index dff1af41..3f36cee1 100644 --- a/src/x86/isa.c +++ b/src/x86/isa.c @@ -496,6 +496,12 @@ struct cpuinfo_x86_isa cpuinfo_x86_detect_isa( */ isa.avx512fp16 = avx512_regs && !!(structured_feature_info0.edx & UINT32_C(0x00800000)); + /* + * AVX_VNNI instructions: + * - Intel: eax[bit 4] in structured feature info (ecx = 1). + */ + isa.avxvnni = avx_regs && !!(structured_feature_info1.eax & UINT32_C(0x00000010)); + /* * AVX512_BF16 instructions: * - Intel: eax[bit 5] in structured feature info (ecx = 1). diff --git a/tools/isa-info.c b/tools/isa-info.c index ddd2212c..9a4151b6 100644 --- a/tools/isa-info.c +++ b/tools/isa-info.c @@ -72,6 +72,7 @@ int main(int argc, char** argv) { printf("\tAVX512VP2INTERSECT: %s\n", cpuinfo_has_x86_avx512vp2intersect() ? "yes" : "no"); printf("\tAVX512_4VNNIW: %s\n", cpuinfo_has_x86_avx512_4vnniw() ? "yes" : "no"); printf("\tAVX512_4FMAPS: %s\n", cpuinfo_has_x86_avx512_4fmaps() ? "yes" : "no"); + printf("\tAVXVNNI: %s\n", cpuinfo_has_x86_avxvnni() ? "yes" : "no"); printf("Multi-threading extensions:\n"); From 4e5be9e1c6c5895bc5105a92d587bc9df8d2522b Mon Sep 17 00:00:00 2001 From: Prashanth Swaminathan <40780424+prashanthswami@users.noreply.github.com> Date: Tue, 14 Nov 2023 11:24:07 -0800 Subject: [PATCH 41/60] Add limited support for RISC-V initialization (#190) * Adds header definitions for RISCV32 and RISCV64, and support in Bazel files for RISCV64. Adds ISA information for RISC-V and hwcap support. * Adds support to construct the processor, core, cluster and package information reported by the system. * Remaining support required for: - Inferring uarch of each processor (reports unknown for now). - Reading cache information (left empty for now). Test: Build and ran cpu_info and isa_info on RISC-V QEMU instance and RISC-V Android emulator. Confirmed that it properly reports the ISA information as well as processor and cluster counts. --- BUILD.bazel | 21 +- CMakeLists.txt | 11 +- configure.py | 6 + include/cpuinfo.h | 121 +++++++ src/api.c | 25 +- src/cpuinfo/internal-api.h | 3 +- src/init.c | 6 + src/linux/api.h | 19 +- src/linux/processors.c | 135 +++++++- src/riscv/api.h | 42 +++ src/riscv/linux/api.h | 69 ++++ src/riscv/linux/init.c | 620 ++++++++++++++++++++++++++++++++++++ src/riscv/linux/riscv-hw.c | 62 ++++ src/riscv/linux/riscv-isa.c | 44 +++ src/riscv/uarch.c | 27 ++ tools/isa-info.c | 10 + 16 files changed, 1196 insertions(+), 25 deletions(-) create mode 100644 src/riscv/api.h create mode 100644 src/riscv/linux/api.h create mode 100644 src/riscv/linux/init.c create mode 100644 src/riscv/linux/riscv-hw.c create mode 100644 src/riscv/linux/riscv-isa.c create mode 100644 src/riscv/uarch.c diff --git a/BUILD.bazel b/BUILD.bazel index 231d18f9..049c7f86 100644 --- a/BUILD.bazel +++ b/BUILD.bazel @@ -43,6 +43,10 @@ ARM_SRCS = [ "src/arm/uarch.c", ] +RISCV_SRCS = [ + "src/riscv/uarch.c", +] + # Platform-specific sources and headers LINUX_SRCS = [ "src/linux/cpulist.c", @@ -81,6 +85,12 @@ LINUX_ARM32_SRCS = LINUX_ARM_SRCS + ["src/arm/linux/aarch32-isa.c"] LINUX_ARM64_SRCS = LINUX_ARM_SRCS + ["src/arm/linux/aarch64-isa.c"] +LINUX_RISCV_SRCS = [ + "src/riscv/linux/init.c", + "src/riscv/linux/riscv-isa.c", + "src/riscv/linux/riscv-hw.c", +] + ANDROID_ARM_SRCS = [ "src/arm/android/properties.c", ] @@ -111,7 +121,8 @@ cc_library( ":linux_armeabi": COMMON_SRCS + ARM_SRCS + LINUX_SRCS + LINUX_ARM32_SRCS, ":linux_aarch64": COMMON_SRCS + ARM_SRCS + LINUX_SRCS + LINUX_ARM64_SRCS, ":linux_mips64": COMMON_SRCS + LINUX_SRCS, - ":linux_riscv64": COMMON_SRCS + LINUX_SRCS, + ":linux_riscv32": COMMON_SRCS + RISCV_SRCS + LINUX_SRCS + LINUX_RISCV_SRCS, + ":linux_riscv64": COMMON_SRCS + RISCV_SRCS + LINUX_SRCS + LINUX_RISCV_SRCS, ":linux_s390x": COMMON_SRCS + LINUX_SRCS, ":macos_x86_64": COMMON_SRCS + X86_SRCS + MACH_SRCS + MACH_X86_SRCS, ":macos_x86_64_legacy": COMMON_SRCS + X86_SRCS + MACH_SRCS + MACH_X86_SRCS, @@ -121,6 +132,7 @@ cc_library( ":android_arm64": COMMON_SRCS + ARM_SRCS + LINUX_SRCS + LINUX_ARM64_SRCS + ANDROID_ARM_SRCS, ":android_x86": COMMON_SRCS + X86_SRCS + LINUX_SRCS + LINUX_X86_SRCS, ":android_x86_64": COMMON_SRCS + X86_SRCS + LINUX_SRCS + LINUX_X86_SRCS, + ":android_riscv64": COMMON_SRCS + RISCV_SRCS + LINUX_SRCS + LINUX_RISCV_SRCS, ":ios_x86_64": COMMON_SRCS + X86_SRCS + MACH_SRCS + MACH_X86_SRCS, ":ios_x86": COMMON_SRCS + X86_SRCS + MACH_SRCS + MACH_X86_SRCS, ":ios_armv7": COMMON_SRCS + MACH_SRCS + MACH_ARM_SRCS, @@ -170,6 +182,8 @@ cc_library( "src/arm/linux/cp.h", "src/arm/api.h", "src/arm/midr.h", + "src/riscv/api.h", + "src/riscv/linux/api.h", ], ) @@ -231,6 +245,11 @@ config_setting( values = {"cpu": "mips64"}, ) +config_setting( + name = "linux_riscv32", + values = {"cpu": "riscv32"}, +) + config_setting( name = "linux_riscv64", values = {"cpu": "riscv64"}, diff --git a/CMakeLists.txt b/CMakeLists.txt index b5db1a7e..99047e58 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -92,7 +92,7 @@ IF(NOT CMAKE_SYSTEM_PROCESSOR) "cpuinfo will compile, but cpuinfo_initialize() will always fail.") SET(CPUINFO_SUPPORTED_PLATFORM FALSE) ENDIF() -ELSEIF(NOT CPUINFO_TARGET_PROCESSOR MATCHES "^(i[3-6]86|AMD64|x86(_64)?|armv[5-8].*|aarch64|arm64.*|ARM64.*)$") +ELSEIF(NOT CPUINFO_TARGET_PROCESSOR MATCHES "^(i[3-6]86|AMD64|x86(_64)?|armv[5-8].*|aarch64|arm64.*|ARM64.*|riscv(32|64))$") MESSAGE(WARNING "Target processor architecture \"${CPUINFO_TARGET_PROCESSOR}\" is not supported in cpuinfo. " "cpuinfo will compile, but cpuinfo_initialize() will always fail.") @@ -210,6 +210,15 @@ IF(CPUINFO_SUPPORTED_PLATFORM) LIST(APPEND CPUINFO_SRCS src/arm/android/properties.c) ENDIF() + ELSEIF(CPUINFO_TARGET_PROCESSOR MATCHES "^(riscv(32|64))$") + LIST(APPEND CPUINFO_SRCS + src/riscv/uarch.c) + IF(CMAKE_SYSTEM_NAME STREQUAL "Linux") + LIST(APPEND CPUINFO_SRCS + src/riscv/linux/init.c + src/riscv/linux/riscv-hw.c + src/riscv/linux/riscv-isa.c) + ENDIF() ENDIF() IF(CMAKE_SYSTEM_NAME STREQUAL "Emscripten") diff --git a/configure.py b/configure.py index 66f2ec99..00bba24b 100755 --- a/configure.py +++ b/configure.py @@ -56,6 +56,12 @@ def main(args): sources += [ "arm/android/properties.c", ] + if build.target.is_riscv: + if build.target.is_linux: + sources += [ + "riscv/linux/init.c", + "riscv/linux/riscv-isa.c", + ] if build.target.is_macos: sources += ["mach/topology.c"] diff --git a/include/cpuinfo.h b/include/cpuinfo.h index dfb535f1..3fbcad2a 100644 --- a/include/cpuinfo.h +++ b/include/cpuinfo.h @@ -46,6 +46,14 @@ #endif #endif +#if defined(__riscv) + #if (__riscv_xlen == 32) + #define CPUINFO_ARCH_RISCV32 1 + #elif (__riscv_xlen == 64) + #define CPUINFO_ARCH_RISCV64 1 + #endif +#endif + /* Define other architecture-specific macros as 0 */ #ifndef CPUINFO_ARCH_X86 @@ -80,6 +88,14 @@ #define CPUINFO_ARCH_WASMSIMD 0 #endif +#ifndef CPUINFO_ARCH_RISCV32 + #define CPUINFO_ARCH_RISCV32 0 +#endif + +#ifndef CPUINFO_ARCH_RISCV64 + #define CPUINFO_ARCH_RISCV64 0 +#endif + #if CPUINFO_ARCH_X86 && defined(_MSC_VER) #define CPUINFO_ABI __cdecl #elif CPUINFO_ARCH_X86 && defined(__GNUC__) @@ -188,6 +204,8 @@ enum cpuinfo_vendor { * Processors are variants of AMD cores. */ cpuinfo_vendor_hygon = 16, + /** SiFive, Inc. Vendor of RISC-V processor microarchitectures. */ + cpuinfo_vendor_sifive = 17, /* Active vendors of embedded CPUs */ @@ -1877,6 +1895,109 @@ static inline bool cpuinfo_has_arm_sve2(void) { #endif } +#if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 + /* This structure is not a part of stable API. Use cpuinfo_has_riscv_* functions instead. */ + struct cpuinfo_riscv_isa { + /** + * Keep fields in line with the canonical order as defined by + * Section 27.11 Subset Naming Convention. + */ + /* RV32I/64I/128I Base ISA. */ + bool i; + #if CPUINFO_ARCH_RISCV32 + /* RV32E Base ISA. */ + bool e; + #endif + /* Integer Multiply/Divide Extension. */ + bool m; + /* Atomic Extension. */ + bool a; + /* Single-Precision Floating-Point Extension. */ + bool f; + /* Double-Precision Floating-Point Extension. */ + bool d; + /* Compressed Extension. */ + bool c; + /* Vector Extension. */ + bool v; + }; + + extern struct cpuinfo_riscv_isa cpuinfo_isa; +#endif + +static inline bool cpuinfo_has_riscv_i(void) { + #if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 + return cpuinfo_isa.i; + #else + return false; + #endif +} + +static inline bool cpuinfo_has_riscv_e(void) { + #if CPUINFO_ARCH_RISCV32 + return cpuinfo_isa.e; + #else + return false; + #endif +} + +static inline bool cpuinfo_has_riscv_m(void) { + #if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 + return cpuinfo_isa.m; + #else + return false; + #endif +} + +static inline bool cpuinfo_has_riscv_a(void) { + #if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 + return cpuinfo_isa.a; + #else + return false; + #endif +} + +static inline bool cpuinfo_has_riscv_f(void) { + #if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 + return cpuinfo_isa.f; + #else + return false; + #endif +} + +static inline bool cpuinfo_has_riscv_d(void) { + #if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 + return cpuinfo_isa.d; + #else + return false; + #endif +} + +static inline bool cpuinfo_has_riscv_g(void) { + // The 'G' extension is simply shorthand for 'IMAFD'. + return cpuinfo_has_riscv_i() + && cpuinfo_has_riscv_m() + && cpuinfo_has_riscv_a() + && cpuinfo_has_riscv_f() + && cpuinfo_has_riscv_d(); +} + +static inline bool cpuinfo_has_riscv_c(void) { + #if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 + return cpuinfo_isa.c; + #else + return false; + #endif +} + +static inline bool cpuinfo_has_riscv_v(void) { + #if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 + return cpuinfo_isa.v; + #else + return false; + #endif +} + const struct cpuinfo_processor* CPUINFO_ABI cpuinfo_get_processors(void); const struct cpuinfo_core* CPUINFO_ABI cpuinfo_get_cores(void); const struct cpuinfo_cluster* CPUINFO_ABI cpuinfo_get_clusters(void); diff --git a/src/api.c b/src/api.c index f91b421c..2f70aeff 100644 --- a/src/api.c +++ b/src/api.c @@ -30,7 +30,8 @@ uint32_t cpuinfo_packages_count = 0; uint32_t cpuinfo_cache_count[cpuinfo_cache_level_max] = { 0 }; uint32_t cpuinfo_max_cache_size = 0; -#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 \ + || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 struct cpuinfo_uarch_info* cpuinfo_uarchs = NULL; uint32_t cpuinfo_uarchs_count = 0; #else @@ -41,7 +42,8 @@ uint32_t cpuinfo_max_cache_size = 0; uint32_t cpuinfo_linux_cpu_max = 0; const struct cpuinfo_processor** cpuinfo_linux_cpu_to_processor_map = NULL; const struct cpuinfo_core** cpuinfo_linux_cpu_to_core_map = NULL; - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 + #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 \ + || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 const uint32_t* cpuinfo_linux_cpu_to_uarch_index_map = NULL; #endif #endif @@ -79,7 +81,8 @@ const struct cpuinfo_uarch_info* cpuinfo_get_uarchs() { if (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "uarchs"); } - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 + #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 \ + || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 return cpuinfo_uarchs; #else return &cpuinfo_global_uarch; @@ -130,7 +133,8 @@ const struct cpuinfo_uarch_info* cpuinfo_get_uarch(uint32_t index) { if (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "uarch"); } - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 + #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 \ + || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 if CPUINFO_UNLIKELY(index >= cpuinfo_uarchs_count) { return NULL; } @@ -175,7 +179,8 @@ uint32_t cpuinfo_get_uarchs_count(void) { if (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "uarchs_count"); } - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 + #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 \ + || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 return cpuinfo_uarchs_count; #else return 1; @@ -351,7 +356,8 @@ uint32_t CPUINFO_ABI cpuinfo_get_current_uarch_index(void) { if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "current_uarch_index"); } - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 + #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 \ + || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 #ifdef __linux__ if (cpuinfo_linux_cpu_to_uarch_index_map == NULL) { /* Special case: avoid syscall on systems with only a single type of cores */ @@ -373,7 +379,7 @@ uint32_t CPUINFO_ABI cpuinfo_get_current_uarch_index(void) { return 0; #endif #else - /* Only ARM/ARM64 processors may include cores of different types in the same package. */ + /* Only ARM/ARM64/RISCV processors may include cores of different types in the same package. */ return 0; #endif } @@ -382,7 +388,8 @@ uint32_t CPUINFO_ABI cpuinfo_get_current_uarch_index_with_default(uint32_t defau if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "current_uarch_index_with_default"); } - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 + #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 \ + || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 #ifdef __linux__ if (cpuinfo_linux_cpu_to_uarch_index_map == NULL) { /* Special case: avoid syscall on systems with only a single type of cores */ @@ -404,7 +411,7 @@ uint32_t CPUINFO_ABI cpuinfo_get_current_uarch_index_with_default(uint32_t defau return default_uarch_index; #endif #else - /* Only ARM/ARM64 processors may include cores of different types in the same package. */ + /* Only ARM/ARM64/RISCV processors may include cores of different types in the same package. */ return 0; #endif } diff --git a/src/cpuinfo/internal-api.h b/src/cpuinfo/internal-api.h index c04620e5..69a9ec98 100644 --- a/src/cpuinfo/internal-api.h +++ b/src/cpuinfo/internal-api.h @@ -35,7 +35,7 @@ extern CPUINFO_INTERNAL uint32_t cpuinfo_packages_count; extern CPUINFO_INTERNAL uint32_t cpuinfo_cache_count[cpuinfo_cache_level_max]; extern CPUINFO_INTERNAL uint32_t cpuinfo_max_cache_size; -#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 extern CPUINFO_INTERNAL struct cpuinfo_uarch_info* cpuinfo_uarchs; extern CPUINFO_INTERNAL uint32_t cpuinfo_uarchs_count; #else @@ -59,6 +59,7 @@ CPUINFO_PRIVATE void cpuinfo_x86_linux_init(void); #endif CPUINFO_PRIVATE void cpuinfo_arm_mach_init(void); CPUINFO_PRIVATE void cpuinfo_arm_linux_init(void); +CPUINFO_PRIVATE void cpuinfo_riscv_linux_init(void); CPUINFO_PRIVATE void cpuinfo_emscripten_init(void); CPUINFO_PRIVATE uint32_t cpuinfo_compute_max_cache_size(const struct cpuinfo_processor* processor); diff --git a/src/init.c b/src/init.c index ed37c079..57482715 100644 --- a/src/init.c +++ b/src/init.c @@ -42,6 +42,12 @@ bool CPUINFO_ABI cpuinfo_initialize(void) { #else cpuinfo_log_error("operating system is not supported in cpuinfo"); #endif +#elif CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 + #if defined(__linux__) + pthread_once(&init_guard, &cpuinfo_riscv_linux_init); + #else + cpuinfo_log_error("operating system is not supported in cpuinfo"); + #endif #elif CPUINFO_ARCH_ASMJS || CPUINFO_ARCH_WASM || CPUINFO_ARCH_WASMSIMD #if defined(__EMSCRIPTEN_PTHREADS__) pthread_once(&init_guard, &cpuinfo_emscripten_init); diff --git a/src/linux/api.h b/src/linux/api.h index f55b8ac7..d33cbd7d 100644 --- a/src/linux/api.h +++ b/src/linux/api.h @@ -21,7 +21,8 @@ #define CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER UINT32_C(0x00000400) #define CPUINFO_LINUX_FLAG_PROC_CPUINFO UINT32_C(0x00000800) #define CPUINFO_LINUX_FLAG_VALID UINT32_C(0x00001000) - +#define CPUINFO_LINUX_FLAG_CUR_FREQUENCY UINT32_C(0x00002000) +#define CPUINFO_LINUX_FLAG_CLUSTER_CLUSTER UINT32_C(0x00004000) typedef bool (*cpuinfo_cpulist_callback)(uint32_t, uint32_t, void*); CPUINFO_INTERNAL bool cpuinfo_linux_parse_cpulist(const char* filename, cpuinfo_cpulist_callback callback, void* context); @@ -33,6 +34,7 @@ CPUINFO_INTERNAL bool cpuinfo_linux_parse_multiline_file(const char* filename, s CPUINFO_INTERNAL uint32_t cpuinfo_linux_get_max_processors_count(void); CPUINFO_INTERNAL uint32_t cpuinfo_linux_get_max_possible_processor(uint32_t max_processors_count); CPUINFO_INTERNAL uint32_t cpuinfo_linux_get_max_present_processor(uint32_t max_processors_count); +CPUINFO_INTERNAL uint32_t cpuinfo_linux_get_processor_cur_frequency(uint32_t processor); CPUINFO_INTERNAL uint32_t cpuinfo_linux_get_processor_min_frequency(uint32_t processor); CPUINFO_INTERNAL uint32_t cpuinfo_linux_get_processor_max_frequency(uint32_t processor); CPUINFO_INTERNAL bool cpuinfo_linux_get_processor_package_id(uint32_t processor, uint32_t package_id[restrict static 1]); @@ -54,6 +56,21 @@ CPUINFO_INTERNAL bool cpuinfo_linux_detect_thread_siblings( uint32_t processor, cpuinfo_siblings_callback callback, void* context); +CPUINFO_INTERNAL bool cpuinfo_linux_detect_cluster_cpus( + uint32_t max_processors_count, + uint32_t processor, + cpuinfo_siblings_callback callback, + void* context); +CPUINFO_INTERNAL bool cpuinfo_linux_detect_core_cpus( + uint32_t max_processors_count, + uint32_t processor, + cpuinfo_siblings_callback callback, + void* context); +CPUINFO_INTERNAL bool cpuinfo_linux_detect_package_cpus( + uint32_t max_processors_count, + uint32_t processor, + cpuinfo_siblings_callback callback, + void* context); extern CPUINFO_INTERNAL const struct cpuinfo_processor** cpuinfo_linux_cpu_to_processor_map; extern CPUINFO_INTERNAL const struct cpuinfo_core** cpuinfo_linux_cpu_to_core_map; diff --git a/src/linux/processors.c b/src/linux/processors.c index aedba743..246b4a2e 100644 --- a/src/linux/processors.c +++ b/src/linux/processors.c @@ -21,6 +21,7 @@ #define KERNEL_MAX_FILENAME "/sys/devices/system/cpu/kernel_max" #define KERNEL_MAX_FILESIZE 32 #define FREQUENCY_FILENAME_SIZE (sizeof("/sys/devices/system/cpu/cpu" STRINGIFY(UINT32_MAX) "/cpufreq/cpuinfo_max_freq")) +#define CUR_FREQUENCY_FILENAME_FORMAT "/sys/devices/system/cpu/cpu%" PRIu32 "/cpufreq/cpuinfo_cur_freq" #define MAX_FREQUENCY_FILENAME_FORMAT "/sys/devices/system/cpu/cpu%" PRIu32 "/cpufreq/cpuinfo_max_freq" #define MIN_FREQUENCY_FILENAME_FORMAT "/sys/devices/system/cpu/cpu%" PRIu32 "/cpufreq/cpuinfo_min_freq" #define FREQUENCY_FILESIZE 32 @@ -31,8 +32,14 @@ #define CORE_ID_FILENAME_FORMAT "/sys/devices/system/cpu/cpu%" PRIu32 "/topology/core_id" #define CORE_ID_FILESIZE 32 +#define CORE_CPUS_FILENAME_SIZE (sizeof("/sys/devices/system/cpu/cpu" STRINGIFY(UINT32_MAX) "/topology/core_cpus_list")) +#define CORE_CPUS_FILENAME_FORMAT "/sys/devices/system/cpu/cpu%" PRIu32 "/topology/core_cpus_list" #define CORE_SIBLINGS_FILENAME_SIZE (sizeof("/sys/devices/system/cpu/cpu" STRINGIFY(UINT32_MAX) "/topology/core_siblings_list")) #define CORE_SIBLINGS_FILENAME_FORMAT "/sys/devices/system/cpu/cpu%" PRIu32 "/topology/core_siblings_list" +#define CLUSTER_CPUS_FILENAME_SIZE (sizeof("/sys/devices/system/cpu/cpu" STRINGIFY(UINT32_MAX) "/topology/cluster_cpus_list")) +#define CLUSTER_CPUS_FILENAME_FORMAT "/sys/devices/system/cpu/cpu%" PRIu32 "/topology/cluster_cpus_list" +#define PACKAGE_CPUS_FILENAME_SIZE (sizeof("/sys/devices/system/cpu/cpu" STRINGIFY(UINT32_MAX) "/topology/package_cpus_list")) +#define PACKAGE_CPUS_FILENAME_FORMAT "/sys/devices/system/cpu/cpu%" PRIu32 "/topology/package_cpus_list" #define THREAD_SIBLINGS_FILENAME_SIZE (sizeof("/sys/devices/system/cpu/cpu" STRINGIFY(UINT32_MAX) "/topology/thread_siblings_list")) #define THREAD_SIBLINGS_FILENAME_FORMAT "/sys/devices/system/cpu/cpu%" PRIu32 "/topology/thread_siblings_list" @@ -125,6 +132,27 @@ uint32_t cpuinfo_linux_get_max_processors_count(void) { } } +uint32_t cpuinfo_linux_get_processor_cur_frequency(uint32_t processor) { + char cur_frequency_filename[FREQUENCY_FILENAME_SIZE]; + const int chars_formatted = snprintf( + cur_frequency_filename, FREQUENCY_FILENAME_SIZE, CUR_FREQUENCY_FILENAME_FORMAT, processor); + if ((unsigned int) chars_formatted >= FREQUENCY_FILENAME_SIZE) { + cpuinfo_log_warning("failed to format filename for current frequency of processor %"PRIu32, processor); + return 0; + } + + uint32_t cur_frequency; + if (cpuinfo_linux_parse_small_file(cur_frequency_filename, FREQUENCY_FILESIZE, uint32_parser, &cur_frequency)) { + cpuinfo_log_debug("parsed currrent frequency value of %"PRIu32" KHz for logical processor %"PRIu32" from %s", + cur_frequency, processor, cur_frequency_filename); + return cur_frequency; + } else { + cpuinfo_log_warning("failed to parse current frequency for processor %"PRIu32" from %s", + processor, cur_frequency_filename); + return 0; + } +} + uint32_t cpuinfo_linux_get_processor_max_frequency(uint32_t processor) { char max_frequency_filename[FREQUENCY_FILENAME_SIZE]; const int chars_formatted = snprintf( @@ -285,8 +313,7 @@ static bool detect_processor_parser(uint32_t processor_list_start, uint32_t proc } bool cpuinfo_linux_detect_possible_processors(uint32_t max_processors_count, - uint32_t* processor0_flags, uint32_t processor_struct_size, uint32_t possible_flag) -{ + uint32_t* processor0_flags, uint32_t processor_struct_size, uint32_t possible_flag) { struct detect_processors_context context = { .max_processors_count = max_processors_count, .processor0_flags = processor0_flags, @@ -302,8 +329,7 @@ bool cpuinfo_linux_detect_possible_processors(uint32_t max_processors_count, } bool cpuinfo_linux_detect_present_processors(uint32_t max_processors_count, - uint32_t* processor0_flags, uint32_t processor_struct_size, uint32_t present_flag) -{ + uint32_t* processor0_flags, uint32_t processor_struct_size, uint32_t present_flag) { struct detect_processors_context context = { .max_processors_count = max_processors_count, .processor0_flags = processor0_flags, @@ -340,12 +366,41 @@ static bool siblings_parser(uint32_t sibling_list_start, uint32_t sibling_list_e return context->callback(processor, sibling_list_start, sibling_list_end, context->callback_context); } +bool cpuinfo_linux_detect_core_cpus( + uint32_t max_processors_count, + uint32_t processor, + cpuinfo_siblings_callback callback, + void* context) { + char core_cpus_filename[CORE_CPUS_FILENAME_SIZE]; + const int chars_formatted = snprintf( + core_cpus_filename, CORE_CPUS_FILENAME_SIZE, CORE_CPUS_FILENAME_FORMAT, processor); + if ((unsigned int) chars_formatted >= CORE_CPUS_FILENAME_SIZE) { + cpuinfo_log_warning("failed to format filename for core cpus of processor %"PRIu32, processor); + return false; + } + + struct siblings_context siblings_context = { + .group_name = "cpus", + .max_processors_count = max_processors_count, + .processor = processor, + .callback = callback, + .callback_context = context, + }; + if (cpuinfo_linux_parse_cpulist(core_cpus_filename, + (cpuinfo_cpulist_callback) siblings_parser, &siblings_context)) { + return true; + } else { + cpuinfo_log_info("failed to parse the list of core cpus for processor %"PRIu32" from %s", + processor, core_cpus_filename); + return false; + } +} + bool cpuinfo_linux_detect_core_siblings( uint32_t max_processors_count, uint32_t processor, cpuinfo_siblings_callback callback, - void* context) -{ + void* context) { char core_siblings_filename[CORE_SIBLINGS_FILENAME_SIZE]; const int chars_formatted = snprintf( core_siblings_filename, CORE_SIBLINGS_FILENAME_SIZE, CORE_SIBLINGS_FILENAME_FORMAT, processor); @@ -362,8 +417,7 @@ bool cpuinfo_linux_detect_core_siblings( .callback_context = context, }; if (cpuinfo_linux_parse_cpulist(core_siblings_filename, - (cpuinfo_cpulist_callback) siblings_parser, &siblings_context)) - { + (cpuinfo_cpulist_callback) siblings_parser, &siblings_context)) { return true; } else { cpuinfo_log_info("failed to parse the list of core siblings for processor %"PRIu32" from %s", @@ -376,8 +430,7 @@ bool cpuinfo_linux_detect_thread_siblings( uint32_t max_processors_count, uint32_t processor, cpuinfo_siblings_callback callback, - void* context) -{ + void* context) { char thread_siblings_filename[THREAD_SIBLINGS_FILENAME_SIZE]; const int chars_formatted = snprintf( thread_siblings_filename, THREAD_SIBLINGS_FILENAME_SIZE, THREAD_SIBLINGS_FILENAME_FORMAT, processor); @@ -394,8 +447,7 @@ bool cpuinfo_linux_detect_thread_siblings( .callback_context = context, }; if (cpuinfo_linux_parse_cpulist(thread_siblings_filename, - (cpuinfo_cpulist_callback) siblings_parser, &siblings_context)) - { + (cpuinfo_cpulist_callback) siblings_parser, &siblings_context)) { return true; } else { cpuinfo_log_info("failed to parse the list of thread siblings for processor %"PRIu32" from %s", @@ -404,3 +456,62 @@ bool cpuinfo_linux_detect_thread_siblings( } } +bool cpuinfo_linux_detect_cluster_cpus( + uint32_t max_processors_count, + uint32_t processor, + cpuinfo_siblings_callback callback, + void* context) { + char cluster_cpus_filename[CLUSTER_CPUS_FILENAME_SIZE]; + const int chars_formatted = snprintf( + cluster_cpus_filename, CLUSTER_CPUS_FILENAME_SIZE, CLUSTER_CPUS_FILENAME_FORMAT, processor); + if ((unsigned int) chars_formatted >= CLUSTER_CPUS_FILENAME_SIZE) { + cpuinfo_log_warning("failed to format filename for cluster cpus of processor %"PRIu32, processor); + return false; + } + + struct siblings_context siblings_context = { + .group_name = "cluster", + .max_processors_count = max_processors_count, + .processor = processor, + .callback = callback, + .callback_context = context, + }; + if (cpuinfo_linux_parse_cpulist(cluster_cpus_filename, + (cpuinfo_cpulist_callback) siblings_parser, &siblings_context)) { + return true; + } else { + cpuinfo_log_info("failed to parse the list of cluster cpus for processor %"PRIu32" from %s", + processor, cluster_cpus_filename); + return false; + } +} + +bool cpuinfo_linux_detect_package_cpus( + uint32_t max_processors_count, + uint32_t processor, + cpuinfo_siblings_callback callback, + void* context) { + char package_cpus_filename[PACKAGE_CPUS_FILENAME_SIZE]; + const int chars_formatted = snprintf( + package_cpus_filename, PACKAGE_CPUS_FILENAME_SIZE, PACKAGE_CPUS_FILENAME_FORMAT, processor); + if ((unsigned int) chars_formatted >= PACKAGE_CPUS_FILENAME_SIZE) { + cpuinfo_log_warning("failed to format filename for package cpus of processor %"PRIu32, processor); + return false; + } + + struct siblings_context siblings_context = { + .group_name = "package", + .max_processors_count = max_processors_count, + .processor = processor, + .callback = callback, + .callback_context = context, + }; + if (cpuinfo_linux_parse_cpulist(package_cpus_filename, + (cpuinfo_cpulist_callback) siblings_parser, &siblings_context)) { + return true; + } else { + cpuinfo_log_info("failed to parse the list of package cpus for processor %"PRIu32" from %s", + processor, package_cpus_filename); + return false; + } +} diff --git a/src/riscv/api.h b/src/riscv/api.h new file mode 100644 index 00000000..cd4bf464 --- /dev/null +++ b/src/riscv/api.h @@ -0,0 +1,42 @@ +#pragma once + +#include + +#include +#include + +/* RISC-V Vendor IDs. */ +enum cpuinfo_riscv_chipset_vendor { + cpuinfo_riscv_chipset_vendor_unknown = 0, + cpuinfo_riscv_chipset_sifive = 0x489, + cpuinfo_riscv_chipset_vendor_max, +}; + +/* RISC-V Architecture IDs. */ +enum cpuinfo_riscv_chipset_arch { + cpuinfo_riscv_chipset_arch_unknown = 0, + cpuinfo_riscv_chipset_arch_max, +}; + +/* RISC-V Implementation IDs. */ +enum cpuinfo_riscv_chipset_impl { + cpuinfo_riscv_chipset_impl_unknown = 0, + cpuinfo_riscv_chipset_impl_max, +}; + +/** + * Decodes the vendor and micro-architecture based on the provided input + * parameters, regardless of underlying operating system. + * + * @param[vendor_id]: The 'mvendorid' as described by the RISC-V Manual. + * @param[arch_id]: The 'marchid' as described by the RISC-V Manual. + * @param[imp_id]: The 'mimplid' as described by the RISC-V Manual. + * @param[vendor] - Reference to the cpuinfo_vendor to populate. + * @param[uarch] - Reference to the cpuinfo_uarch to populate. + */ +CPUINFO_INTERNAL void cpuinfo_riscv_decode_vendor_uarch( + uint32_t vendor_id, + uint32_t arch_id, + uint32_t imp_id, + enum cpuinfo_vendor vendor[restrict static 1], + enum cpuinfo_uarch uarch[restrict static 1]); diff --git a/src/riscv/linux/api.h b/src/riscv/linux/api.h new file mode 100644 index 00000000..5f1a8cf3 --- /dev/null +++ b/src/riscv/linux/api.h @@ -0,0 +1,69 @@ +#pragma once + +#include +#include + +/** + * Definition of a RISC-V Linux processor. It is composed of the base processor + * definition in "include/cpuinfo.h" and flags specific to RISC-V Linux + * implementations. + */ +struct cpuinfo_riscv_linux_processor { + /* Public ABI cpuinfo structures. */ + struct cpuinfo_processor processor; + struct cpuinfo_core core; + struct cpuinfo_cluster cluster; + struct cpuinfo_package package; + + /** + * Linux-specific flags for the logical processor: + * - Bit field that can be masked with CPUINFO_LINUX_FLAG_*. + */ + uint32_t flags; + + /** + * Minimum processor ID on the cluster which includes this logical processor. + * This value can serve as an ID for the cluster of logical processors: it is the + * same for all logical processors on the same package. + */ + uint32_t cluster_leader_id; + + /** + * Minimum processor ID on the core which includes this logical processor. + * This value can serve as an ID for the core of logical processors: it + * is the same for all logical processors on the same core. + */ + uint32_t core_leader_id; + + /** + * Minimum processor ID on the package which includes this logical processor. + * This value can serve as an ID for the package of logical processors: it + * is the same for all logical processors on the same package. + */ + uint32_t package_leader_id; +}; + +/** + * Reads AT_HWCAP from `getauxval` and populates the cpuinfo_riscv_isa + * structure. + * + * @param[isa] - Reference to cpuinfo_riscv_isa structure to populate. + */ +CPUINFO_INTERNAL void cpuinfo_riscv_linux_decode_isa_from_hwcap( + struct cpuinfo_riscv_isa isa[restrict static 1]); + +/** + * Reads `sys_riscv_hwprobe` and determines the processor vendor and + * micro-architecture. + * + * @param[processor] - The Linux ID of the target processor. + * @param[vendor] - Reference to the cpuinfo_vendor to populate. + * @param[uarch] - Reference to the cpuinfo_uarch to populate. + */ +CPUINFO_INTERNAL void cpuinfo_riscv_linux_decode_vendor_uarch_from_hwprobe( + uint32_t processor, + enum cpuinfo_vendor vendor[restrict static 1], + enum cpuinfo_uarch uarch[restrict static 1]); + +/* Used to determine which uarch is associated with the current thread. */ +extern CPUINFO_INTERNAL const uint32_t* cpuinfo_linux_cpu_to_uarch_index_map; diff --git a/src/riscv/linux/init.c b/src/riscv/linux/init.c new file mode 100644 index 00000000..491a3f25 --- /dev/null +++ b/src/riscv/linux/init.c @@ -0,0 +1,620 @@ +#include + +#include +#include +#include +#include + +/* ISA structure to hold supported extensions. */ +struct cpuinfo_riscv_isa cpuinfo_isa; + +/* Helper function to bitmask flags and ensure operator precedence. */ +static inline bool bitmask_all(uint32_t flags, uint32_t mask) { + return (flags & mask) == mask; +} + +static int compare_riscv_linux_processors(const void* a, const void* b) { + /** + * For our purposes, it is only relevant that the list is sorted by + * micro-architecture, so the nature of ordering is irrelevant. + */ + return ((const struct cpuinfo_riscv_linux_processor*)a)->core.uarch + - ((const struct cpuinfo_riscv_linux_processor*)b)->core.uarch; +} + +/** + * Parses the core cpus list for each processor. This function is called once + * per-processor, with the IDs of all other processors in the core list. + * + * The 'processor_[start|count]' are populated in the processor's 'core' + * attribute, with 'start' being the smallest ID in the core list. + * + * The 'core_leader_id' of each processor is set to the smallest ID in it's + * cluster CPU list. + * + * Precondition: The element in the 'processors' list must be initialized with + * their 'core_leader_id' to their index in the list. + + * E.g. processors[0].core_leader_id = 0. + */ +static bool core_cpus_parser(uint32_t processor, + uint32_t core_cpus_start, + uint32_t core_cpus_end, + struct cpuinfo_riscv_linux_processor* processors) { + uint32_t processor_start = UINT32_MAX; + uint32_t processor_count = 0; + + /* If the processor already has a leader, use it. */ + if (bitmask_all(processors[processor].flags, CPUINFO_LINUX_FLAG_CORE_CLUSTER)) { + processor_start = processors[processor].core_leader_id; + } + + for (size_t core_cpu = core_cpus_start; core_cpu < core_cpus_end; core_cpu++) { + if (!bitmask_all(processors[core_cpu].flags, CPUINFO_LINUX_FLAG_VALID)) { + continue; + } + /** + * The first valid processor observed is the smallest ID in the + * list that attaches to this core. + */ + if (processor_start == UINT32_MAX) { + processor_start = core_cpu; + } + processors[core_cpu].core_leader_id = processor_start; + processor_count++; + } + /** + * If the cluster flag has not been set, assign the processor start. If + * it has been set, only apply the processor start if it's less than the + * held value. This can happen if the callback is invoked twice: + * + * e.g. core_cpu_list=1,10-12 + */ + if (!bitmask_all(processors[processor].flags, CPUINFO_LINUX_FLAG_CORE_CLUSTER) + || processors[processor].core.processor_start > processor_start) { + processors[processor].core.processor_start = processor_start; + processors[processor].core_leader_id = processor_start; + } + processors[processor].core.processor_count += processor_count; + processors[processor].flags |= CPUINFO_LINUX_FLAG_CORE_CLUSTER; + /* The parser has failed only if no processors were found. */ + return processor_count != 0; +} + +/** + * Parses the cluster cpu list for each processor. This function is called once + * per-processor, with the IDs of all other processors in the cluster. + * + * The 'cluster_leader_id' of each processor is set to the smallest ID in it's + * cluster CPU list. + * + * Precondition: The element in the 'processors' list must be initialized with + * their 'cluster_leader_id' to their index in the list. + * E.g. processors[0].cluster_leader_id = 0. + */ +static bool cluster_cpus_parser(uint32_t processor, + uint32_t cluster_cpus_start, + uint32_t cluster_cpus_end, + struct cpuinfo_riscv_linux_processor* processors) { + uint32_t processor_start = UINT32_MAX; + uint32_t processor_count = 0; + uint32_t core_count = 0; + + /* If the processor already has a leader, use it. */ + if (bitmask_all(processors[processor].flags, CPUINFO_LINUX_FLAG_CLUSTER_CLUSTER)) { + processor_start = processors[processor].cluster_leader_id; + } + + for (size_t cluster_cpu = cluster_cpus_start; cluster_cpu < cluster_cpus_end; cluster_cpu++) { + if (!bitmask_all(processors[cluster_cpu].flags, CPUINFO_LINUX_FLAG_VALID)) { + continue; + } + /** + * The first valid processor observed is the smallest ID in the + * list that attaches to this core. + */ + if (processor_start == UINT32_MAX) { + processor_start = cluster_cpu; + } + processors[cluster_cpu].cluster_leader_id = processor_start; + processor_count++; + /** + * A processor should only represent it's core if it is the + * assigned leader of that core. + */ + if (processors[cluster_cpu].core_leader_id == cluster_cpu) { + core_count++; + } + } + /** + * If the cluster flag has not been set, assign the processor start. If + * it has been set, only apply the processor start if it's less than the + * held value. This can happen if the callback is invoked twice: + * + * e.g. cluster_cpus_list=1,10-12 + */ + if (!bitmask_all(processors[processor].flags, CPUINFO_LINUX_FLAG_CLUSTER_CLUSTER) + || processors[processor].cluster.processor_start > processor_start) { + processors[processor].cluster.processor_start = processor_start; + processors[processor].cluster.core_start = processor_start; + processors[processor].cluster.cluster_id = processor_start; + processors[processor].cluster_leader_id = processor_start; + } + processors[processor].cluster.processor_count += processor_count; + processors[processor].cluster.core_count += core_count; + processors[processor].flags |= CPUINFO_LINUX_FLAG_CLUSTER_CLUSTER; + return true; +} + +/** + * Parses the package cpus list for each processor. This function is called once + * per-processor, with the IDs of all other processors in the package list. + * + * The 'processor_[start|count]' are populated in the processor's 'package' + * attribute, with 'start' being the smallest ID in the package list. + * + * The 'package_leader_id' of each processor is set to the smallest ID in it's + * cluster CPU list. + * + * Precondition: The element in the 'processors' list must be initialized with + * their 'package_leader_id' to their index in the list. + * E.g. processors[0].package_leader_id = 0. + */ +static bool package_cpus_parser(uint32_t processor, + uint32_t package_cpus_start, + uint32_t package_cpus_end, + struct cpuinfo_riscv_linux_processor* processors) { + uint32_t processor_start = UINT32_MAX; + uint32_t processor_count = 0; + uint32_t cluster_count = 0; + uint32_t core_count = 0; + + /* If the processor already has a leader, use it. */ + if (bitmask_all(processors[processor].flags, CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER)) { + processor_start = processors[processor].package_leader_id; + } + + for (size_t package_cpu = package_cpus_start; package_cpu < package_cpus_end; package_cpu++) { + if (!bitmask_all(processors[package_cpu].flags, CPUINFO_LINUX_FLAG_VALID)) { + continue; + } + /** + * The first valid processor observed is the smallest ID in the + * list that attaches to this package. + */ + if (processor_start == UINT32_MAX) { + processor_start = package_cpu; + } + processors[package_cpu].package_leader_id = processor_start; + processor_count++; + /** + * A processor should only represent it's core if it is the + * assigned leader of that core, and similarly for it's cluster. + */ + if (processors[package_cpu].cluster_leader_id == package_cpu) { + cluster_count++; + } + if (processors[package_cpu].core_leader_id == package_cpu) { + core_count++; + } + } + /** + * If the cluster flag has not been set, assign the processor start. If + * it has been set, only apply the processor start if it's less than the + * held value. This can happen if the callback is invoked twice: + * + * e.g. package_cpus_list=1,10-12 + */ + if (!bitmask_all(processors[processor].flags, CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER) + || processors[processor].package.processor_start > processor_start) { + processors[processor].package.processor_start = processor_start; + processors[processor].package.cluster_start = processor_start; + processors[processor].package.core_start = processor_start; + processors[processor].package_leader_id = processor_start; + } + processors[processor].package.processor_count += processor_count; + processors[processor].package.cluster_count += cluster_count; + processors[processor].package.core_count += core_count; + processors[processor].flags |= CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER; + return true; +} + +/* Initialization for the RISC-V Linux system. */ +void cpuinfo_riscv_linux_init(void) { + struct cpuinfo_riscv_linux_processor* riscv_linux_processors = NULL; + struct cpuinfo_processor* processors = NULL; + struct cpuinfo_package* packages = NULL; + struct cpuinfo_cluster* clusters = NULL; + struct cpuinfo_core* cores = NULL; + struct cpuinfo_uarch_info* uarchs = NULL; + const struct cpuinfo_processor** linux_cpu_to_processor_map = NULL; + const struct cpuinfo_core** linux_cpu_to_core_map = NULL; + uint32_t* linux_cpu_to_uarch_index_map = NULL; + + /** + * The interesting set of processors are the number of 'present' + * processors on the system. There may be more 'possible' processors, but + * processor information cannot be gathered on non-present processors. + * + * Note: For SoCs, it is largely the case that all processors are known + * at boot and no processors are hotplugged at runtime, so the + * 'present' and 'possible' list is often the same. + * + * Note: This computes the maximum processor ID of the 'present' + * processors. It is not a count of the number of processors on the + * system. + */ + const size_t max_processor_id = 1 + + cpuinfo_linux_get_max_present_processor( + cpuinfo_linux_get_max_processors_count()); + if (max_processor_id == 0) { + cpuinfo_log_error("failed to discover any processors"); + return; + } + + /** + * Allocate space to store all processor information. This array is + * sized to the max processor ID as opposed to the number of 'present' + * processors, to leverage pointer math in the common utility functions. + */ + riscv_linux_processors = calloc(max_processor_id, + sizeof(struct cpuinfo_riscv_linux_processor)); + if (riscv_linux_processors == NULL) { + cpuinfo_log_error("failed to allocate %zu bytes for %zu processors.", + max_processor_id * sizeof(struct cpuinfo_riscv_linux_processor), + max_processor_id); + goto cleanup; + } + + /** + * Attempt to detect all processors and apply the corresponding flag to + * each processor struct that we find. + */ + if (!cpuinfo_linux_detect_present_processors(max_processor_id, + &riscv_linux_processors->flags, + sizeof(struct cpuinfo_riscv_linux_processor), + CPUINFO_LINUX_FLAG_PRESENT | CPUINFO_LINUX_FLAG_VALID)) { + cpuinfo_log_error("failed to detect present processors"); + goto cleanup; + } + + /* Populate processor information. */ + for (size_t processor = 0; processor < max_processor_id; processor++) { + if (!bitmask_all(riscv_linux_processors[processor].flags, CPUINFO_LINUX_FLAG_VALID)) { + continue; + } + /* TODO: Determine if an 'smt_id' is available. */ + riscv_linux_processors[processor].processor.linux_id = processor; + } + + /* Populate core information. */ + for (size_t processor = 0; processor < max_processor_id; processor++) { + if (!bitmask_all(riscv_linux_processors[processor].flags, CPUINFO_LINUX_FLAG_VALID)) { + continue; + } + + /* Populate processor start and count information. */ + if (!cpuinfo_linux_detect_core_cpus( + max_processor_id, + processor, + (cpuinfo_siblings_callback) core_cpus_parser, + riscv_linux_processors)) { + cpuinfo_log_error("failed to detect core cpus for processor %zu.", processor); + goto cleanup; + } + + /* Populate core ID information. */ + if (cpuinfo_linux_get_processor_core_id( + processor, + &riscv_linux_processors[processor].core.core_id)) { + riscv_linux_processors[processor].flags |= CPUINFO_LINUX_FLAG_CORE_ID; + } + + /** + * Populate the vendor and uarch of this core from this + * processor. When the final 'cores' list is constructed, only + * the values from the core leader will be honored. + */ + cpuinfo_riscv_linux_decode_vendor_uarch_from_hwprobe( + processor, + &riscv_linux_processors[processor].core.vendor, + &riscv_linux_processors[processor].core.uarch); + + /* Populate frequency information of this core. */ + uint32_t frequency = cpuinfo_linux_get_processor_cur_frequency(processor); + if (frequency != 0) { + riscv_linux_processors[processor].core.frequency = frequency; + riscv_linux_processors[processor].flags |= CPUINFO_LINUX_FLAG_CUR_FREQUENCY; + } + } + + /* Populate cluster information. */ + for (size_t processor = 0; processor < max_processor_id; processor++) { + if (!bitmask_all(riscv_linux_processors[processor].flags, CPUINFO_LINUX_FLAG_VALID)) { + continue; + } + if (!cpuinfo_linux_detect_cluster_cpus( + max_processor_id, + processor, + (cpuinfo_siblings_callback) cluster_cpus_parser, + riscv_linux_processors)) { + cpuinfo_log_warning("failed to detect cluster cpus for processor %zu.", processor); + goto cleanup; + } + + /** + * Populate the vendor, uarch and frequency of this cluster from + * this logical processor. When the 'clusters' list is constructed, + * only the values from the cluster leader will be honored. + */ + riscv_linux_processors[processor].cluster.vendor = + riscv_linux_processors[processor].core.vendor; + riscv_linux_processors[processor].cluster.uarch = + riscv_linux_processors[processor].core.uarch; + riscv_linux_processors[processor].cluster.frequency = + riscv_linux_processors[processor].core.frequency; + } + + /* Populate package information. */ + for (size_t processor = 0; processor < max_processor_id; processor++) { + if (!bitmask_all(riscv_linux_processors[processor].flags, CPUINFO_LINUX_FLAG_VALID)) { + continue; + } + if (!cpuinfo_linux_detect_package_cpus( + max_processor_id, + processor, + (cpuinfo_siblings_callback) package_cpus_parser, + riscv_linux_processors)) { + cpuinfo_log_warning("failed to detect package cpus for processor %zu.", processor); + goto cleanup; + } + } + + /* Populate ISA structure with hwcap information. */ + cpuinfo_riscv_linux_decode_isa_from_hwcap(&cpuinfo_isa); + + /** + * To efficiently compute the number of unique micro-architectures + * present on the system, sort the processor list by micro-architecture + * and then scan through the list to count the differences. + * + * Ensure this is done at the end of composing the processor list - the + * parsing functions assume that the position of the processor in the + * list matches it's Linux ID, which this sorting operation breaks. + */ + qsort(riscv_linux_processors, + max_processor_id, + sizeof(struct cpuinfo_riscv_linux_processor), + compare_riscv_linux_processors); + + /** + * Determine the number of *valid* detected processors, cores, + * clusters, packages and uarchs in the list. + */ + size_t valid_processors_count = 0; + size_t valid_cores_count = 0; + size_t valid_clusters_count = 0; + size_t valid_packages_count = 0; + size_t valid_uarchs_count = 0; + enum cpuinfo_uarch last_uarch = cpuinfo_uarch_unknown; + for (size_t processor = 0; processor < max_processor_id; processor++) { + if (!bitmask_all(riscv_linux_processors[processor].flags, CPUINFO_LINUX_FLAG_VALID)) { + continue; + } + + /** + * All comparisons to the leader id values MUST be done against + * the 'linux_id' as opposed to 'processor'. The sort function + * above no longer allows us to make the assumption that these + * two values are the same. + */ + uint32_t linux_id = riscv_linux_processors[processor].processor.linux_id; + + valid_processors_count++; + if (riscv_linux_processors[processor].core_leader_id == linux_id) { + valid_cores_count++; + } + if (riscv_linux_processors[processor].cluster_leader_id == linux_id) { + valid_clusters_count++; + } + if (riscv_linux_processors[processor].package_leader_id == linux_id) { + valid_packages_count++; + } + /** + * As we've sorted by micro-architecture, when the uarch differs + * between two entries, a unique uarch has been observed. + */ + if (last_uarch != riscv_linux_processors[processor].core.uarch + || valid_uarchs_count == 0) { + valid_uarchs_count++; + last_uarch = riscv_linux_processors[processor].core.uarch; + } + } + + /* Allocate and populate final public ABI structures. */ + processors = calloc(valid_processors_count, + sizeof(struct cpuinfo_processor)); + if (processors == NULL) { + cpuinfo_log_error("failed to allocate %zu bytes for %zu processors.", + valid_processors_count * sizeof(struct cpuinfo_processor), + valid_processors_count); + goto cleanup; + } + + cores = calloc(valid_cores_count, + sizeof(struct cpuinfo_core)); + if (cores == NULL) { + cpuinfo_log_error("failed to allocate %zu bytes for %zu cores.", + valid_cores_count * sizeof(struct cpuinfo_core), + valid_cores_count); + goto cleanup; + } + + clusters = calloc(valid_clusters_count, + sizeof(struct cpuinfo_cluster)); + if (clusters == NULL) { + cpuinfo_log_error("failed to allocate %zu bytes for %zu clusters.", + valid_clusters_count * sizeof(struct cpuinfo_cluster), + valid_clusters_count); + goto cleanup; + } + + packages = calloc(valid_packages_count, + sizeof(struct cpuinfo_package)); + if (packages == NULL) { + cpuinfo_log_error("failed to allocate %zu bytes for %zu packages.", + valid_packages_count * sizeof(struct cpuinfo_package), + valid_packages_count); + goto cleanup; + } + + uarchs = calloc(valid_uarchs_count, sizeof(struct cpuinfo_uarch_info)); + if (uarchs == NULL) { + cpuinfo_log_error("failed to allocate %zu bytes for %zu packages.", + valid_uarchs_count * sizeof(struct cpuinfo_uarch_info), + valid_uarchs_count); + goto cleanup; + } + + linux_cpu_to_processor_map = calloc(max_processor_id, + sizeof(struct cpuinfo_processor*)); + if (linux_cpu_to_processor_map == NULL) { + cpuinfo_log_error("failed to allocate %zu bytes for %zu processor map.", + max_processor_id * sizeof(struct cpuinfo_processor*), + max_processor_id); + goto cleanup; + } + + linux_cpu_to_core_map = calloc(max_processor_id, + sizeof(struct cpuinfo_core*)); + if (linux_cpu_to_core_map == NULL) { + cpuinfo_log_error("failed to allocate %zu bytes for %zu core map.", + max_processor_id * sizeof(struct cpuinfo_core*), + max_processor_id); + goto cleanup; + } + + linux_cpu_to_uarch_index_map = calloc(max_processor_id, + sizeof(struct cpuinfo_uarch_info*)); + if (linux_cpu_to_uarch_index_map == NULL) { + cpuinfo_log_error("failed to allocate %zu bytes for %zu uarch map.", + max_processor_id * sizeof(struct cpuinfo_uarch_info*), + max_processor_id); + goto cleanup; + } + + /* Transfer contents of processor list to ABI structures. */ + size_t valid_processors_index = 0; + size_t valid_cores_index = 0; + size_t valid_clusters_index = 0; + size_t valid_packages_index = 0; + size_t valid_uarchs_index = 0; + last_uarch = cpuinfo_uarch_unknown; + for (size_t processor = 0; processor < max_processor_id; processor++) { + if (!bitmask_all(riscv_linux_processors[processor].flags, CPUINFO_LINUX_FLAG_VALID)) { + continue; + } + + /** + * All comparisons to the leader id values MUST be done against + * the 'linux_id' as opposed to 'processor'. The sort function + * above no longer allows us to make the assumption that these + * two values are the same. + */ + uint32_t linux_id = riscv_linux_processors[processor].processor.linux_id; + + /* Create uarch entry if this uarch has not been seen before. */ + if (last_uarch != riscv_linux_processors[processor].core.uarch + || valid_uarchs_index == 0) { + uarchs[valid_uarchs_index++].uarch = + riscv_linux_processors[processor].core.uarch; + last_uarch = riscv_linux_processors[processor].core.uarch; + } + + /* Copy cpuinfo_processor information. */ + memcpy(&processors[valid_processors_index++], + &riscv_linux_processors[processor].processor, + sizeof(struct cpuinfo_processor)); + + /* Update uarch processor count. */ + uarchs[valid_uarchs_index - 1].processor_count++; + + /* Copy cpuinfo_core information, if this is the leader. */ + if (riscv_linux_processors[processor].core_leader_id == linux_id) { + memcpy(&cores[valid_cores_index++], + &riscv_linux_processors[processor].core, + sizeof(struct cpuinfo_core)); + /* Update uarch core count. */ + uarchs[valid_uarchs_index - 1].core_count++; + } + + /* Copy cpuinfo_cluster information, if this is the leader. */ + if (riscv_linux_processors[processor].cluster_leader_id == linux_id) { + memcpy(&clusters[valid_clusters_index++], + &riscv_linux_processors[processor].cluster, + sizeof(struct cpuinfo_cluster)); + } + + /* Copy cpuinfo_package information, if this is the leader. */ + if (riscv_linux_processors[processor].package_leader_id == linux_id) { + memcpy(&packages[valid_packages_index++], + &riscv_linux_processors[processor].package, + sizeof(struct cpuinfo_package)); + } + + /* Commit pointers on the final structures. */ + processors[valid_processors_index - 1].core = &cores[valid_cores_index - 1]; + processors[valid_processors_index - 1].cluster = &clusters[valid_clusters_index - 1]; + processors[valid_processors_index - 1].package = &packages[valid_packages_index - 1]; + + cores[valid_cores_index - 1].cluster = &clusters[valid_clusters_index - 1]; + cores[valid_cores_index - 1].package = &packages[valid_packages_index - 1]; + + clusters[valid_clusters_index - 1].package = &packages[valid_packages_index - 1]; + + linux_cpu_to_processor_map[linux_id] = &processors[valid_processors_index - 1]; + linux_cpu_to_core_map[linux_id] = &cores[valid_cores_index - 1]; + linux_cpu_to_uarch_index_map[linux_id] = valid_uarchs_index - 1; + } + + /* Commit */ + cpuinfo_processors = processors; + cpuinfo_processors_count = valid_processors_count; + cpuinfo_cores = cores; + cpuinfo_cores_count = valid_cores_count; + cpuinfo_clusters = clusters; + cpuinfo_clusters_count = valid_clusters_count; + cpuinfo_packages = packages; + cpuinfo_packages_count = valid_packages_count; + cpuinfo_uarchs = uarchs; + cpuinfo_uarchs_count = valid_uarchs_count; + + cpuinfo_linux_cpu_max = max_processor_id; + cpuinfo_linux_cpu_to_processor_map = linux_cpu_to_processor_map; + cpuinfo_linux_cpu_to_core_map = linux_cpu_to_core_map; + cpuinfo_linux_cpu_to_uarch_index_map = linux_cpu_to_uarch_index_map; + + __sync_synchronize(); + + cpuinfo_is_initialized = true; + + /* Mark all public structures NULL to prevent cleanup from erasing them. */ + processors = NULL; + cores = NULL; + clusters = NULL; + packages = NULL; + uarchs = NULL; + linux_cpu_to_processor_map = NULL; + linux_cpu_to_core_map = NULL; + linux_cpu_to_uarch_index_map = NULL; +cleanup: + free(riscv_linux_processors); + free(processors); + free(cores); + free(clusters); + free(packages); + free(uarchs); + free(linux_cpu_to_processor_map); + free(linux_cpu_to_core_map); + free(linux_cpu_to_uarch_index_map); +} diff --git a/src/riscv/linux/riscv-hw.c b/src/riscv/linux/riscv-hw.c new file mode 100644 index 00000000..ccee848c --- /dev/null +++ b/src/riscv/linux/riscv-hw.c @@ -0,0 +1,62 @@ +#include +#include + +#include +#include +#include + +void cpuinfo_riscv_linux_decode_vendor_uarch_from_hwprobe( + uint32_t processor, + enum cpuinfo_vendor vendor[restrict static 1], + enum cpuinfo_uarch uarch[restrict static 1]) { + struct riscv_hwprobe pairs[] = { + { .key = RISCV_HWPROBE_KEY_MVENDORID, }, + { .key = RISCV_HWPROBE_KEY_MARCHID, }, + { .key = RISCV_HWPROBE_KEY_MIMPID, }, + }; + const size_t pairs_count = sizeof(pairs) / sizeof(struct riscv_hwprobe); + + /* In case of failure, report unknown. */ + *vendor = cpuinfo_vendor_unknown; + *uarch = cpuinfo_uarch_unknown; + + /* Create a CPU set with this processor flagged. */ + const size_t cpu_set_size = processor + 1; + cpu_set_t* cpu_set = CPU_ALLOC(cpu_set_size); + CPU_SET(processor, cpu_set); + + /* Request all available information from hwprobe. */ + int ret = __riscv_hwprobe(pairs, pairs_count, + cpu_set_size, (unsigned long*)cpu_set, + 0 /* flags */); + if (ret < 0) { + cpuinfo_log_warning("failed to get hwprobe information, err: %d", ret); + return; + } + + /** + * The syscall may not have populated all requested keys, loop through + * the list and store the values that were discovered. + */ + uint32_t vendor_id = 0; + uint32_t arch_id = 0; + uint32_t imp_id = 0; + for (size_t pair = 0; pair < pairs_count; pair++) { + switch (pairs[pair].key) { + case RISCV_HWPROBE_KEY_MVENDORID: + vendor_id = pairs[pair].value; + break; + case RISCV_HWPROBE_KEY_MARCHID: + arch_id = pairs[pair].value; + break; + case RISCV_HWPROBE_KEY_MIMPID: + imp_id = pairs[pair].value; + break; + default: + /* The key value may be -1 if unsupported. */ + break; + } + } + cpuinfo_riscv_decode_vendor_uarch(vendor_id, arch_id, imp_id, + vendor, uarch); +} diff --git a/src/riscv/linux/riscv-isa.c b/src/riscv/linux/riscv-isa.c new file mode 100644 index 00000000..ace451b8 --- /dev/null +++ b/src/riscv/linux/riscv-isa.c @@ -0,0 +1,44 @@ +#include +#include + +#include + +/** + * arch/riscv/include/uapi/asm/hwcap.h + * + * This must be kept in sync with the upstream kernel header. + */ +#define COMPAT_HWCAP_ISA_I (1 << ('I' - 'A')) +#define COMPAT_HWCAP_ISA_M (1 << ('M' - 'A')) +#define COMPAT_HWCAP_ISA_A (1 << ('A' - 'A')) +#define COMPAT_HWCAP_ISA_F (1 << ('F' - 'A')) +#define COMPAT_HWCAP_ISA_D (1 << ('D' - 'A')) +#define COMPAT_HWCAP_ISA_C (1 << ('C' - 'A')) +#define COMPAT_HWCAP_ISA_V (1 << ('V' - 'A')) + +void cpuinfo_riscv_linux_decode_isa_from_hwcap( + struct cpuinfo_riscv_isa isa[restrict static 1]) { + const unsigned long hwcap = getauxval(AT_HWCAP); + + if (hwcap & COMPAT_HWCAP_ISA_I) { + isa->i = true; + } + if (hwcap & COMPAT_HWCAP_ISA_M) { + isa->m = true; + } + if (hwcap & COMPAT_HWCAP_ISA_A) { + isa->a = true; + } + if (hwcap & COMPAT_HWCAP_ISA_F) { + isa->f = true; + } + if (hwcap & COMPAT_HWCAP_ISA_D) { + isa->d = true; + } + if (hwcap & COMPAT_HWCAP_ISA_C) { + isa->c = true; + } + if (hwcap & COMPAT_HWCAP_ISA_V) { + isa->v = true; + } +} diff --git a/src/riscv/uarch.c b/src/riscv/uarch.c new file mode 100644 index 00000000..bf93e867 --- /dev/null +++ b/src/riscv/uarch.c @@ -0,0 +1,27 @@ +#include + +#include +#include + +void cpuinfo_riscv_decode_vendor_uarch( + uint32_t vendor_id, + uint32_t arch_id, + uint32_t imp_id, + enum cpuinfo_vendor vendor[restrict static 1], + enum cpuinfo_uarch uarch[restrict static 1]) { + /* The vendor ID is sufficient to determine the cpuinfo_vendor. */ + switch(vendor_id) { + case cpuinfo_riscv_chipset_sifive: + *vendor = cpuinfo_vendor_sifive; + break; + default: + *vendor = cpuinfo_vendor_unknown; + cpuinfo_log_warning("unknown vendor ID: %"PRIu32, vendor_id); + break; + } + /** + * TODO: Add support for parsing chipset architecture and implementation + * IDs here, when a chipset of interest comes along. + */ + *uarch = cpuinfo_uarch_unknown; +} diff --git a/tools/isa-info.c b/tools/isa-info.c index 9a4151b6..ff69791d 100644 --- a/tools/isa-info.c +++ b/tools/isa-info.c @@ -178,5 +178,15 @@ int main(int argc, char** argv) { printf("\tPMULL: %s\n", cpuinfo_has_arm_pmull() ? "yes" : "no"); printf("\tCRC32: %s\n", cpuinfo_has_arm_crc32() ? "yes" : "no"); #endif +#if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 + printf("Instruction sets:\n"); + printf("\tBase Integer: %s\n", cpuinfo_has_riscv_i() ? "yes" : "no"); + printf("\tInteger Multiply/Divide: %s\n", cpuinfo_has_riscv_m() ? "yes" : "no"); + printf("\tAtomics: %s\n", cpuinfo_has_riscv_a() ? "yes" : "no"); + printf("\tSingle-Precision Floating-Point: %s\n", cpuinfo_has_riscv_f() ? "yes" : "no"); + printf("\tDouble-Precision Floating-Point: %s\n", cpuinfo_has_riscv_d() ? "yes" : "no"); + printf("\tCompressed: %s\n", cpuinfo_has_riscv_c() ? "yes" : "no"); + printf("\tVector: %s\n", cpuinfo_has_riscv_v() ? "yes" : "no"); +#endif } From 9f13d15a88de63cfb516f12cc9ac330ad8b9cadb Mon Sep 17 00:00:00 2001 From: Prashanth Swaminathan <40780424+prashanthswami@users.noreply.github.com> Date: Thu, 16 Nov 2023 09:07:26 -0800 Subject: [PATCH 42/60] Fix size check of max processor count (#199) On 64-bit systems, size_t will not overflow when the function to get max processors returns UINT32_MAX. Use the appropriate uint32_t type. --- src/riscv/linux/init.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/riscv/linux/init.c b/src/riscv/linux/init.c index 491a3f25..d1c43c54 100644 --- a/src/riscv/linux/init.c +++ b/src/riscv/linux/init.c @@ -244,7 +244,7 @@ void cpuinfo_riscv_linux_init(void) { * processors. It is not a count of the number of processors on the * system. */ - const size_t max_processor_id = 1 + + const uint32_t max_processor_id = 1 + cpuinfo_linux_get_max_present_processor( cpuinfo_linux_get_max_processors_count()); if (max_processor_id == 0) { @@ -260,7 +260,7 @@ void cpuinfo_riscv_linux_init(void) { riscv_linux_processors = calloc(max_processor_id, sizeof(struct cpuinfo_riscv_linux_processor)); if (riscv_linux_processors == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for %zu processors.", + cpuinfo_log_error("failed to allocate %zu bytes for %"PRIu32" processors.", max_processor_id * sizeof(struct cpuinfo_riscv_linux_processor), max_processor_id); goto cleanup; @@ -479,7 +479,7 @@ void cpuinfo_riscv_linux_init(void) { linux_cpu_to_processor_map = calloc(max_processor_id, sizeof(struct cpuinfo_processor*)); if (linux_cpu_to_processor_map == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for %zu processor map.", + cpuinfo_log_error("failed to allocate %zu bytes for %"PRIu32" processor map.", max_processor_id * sizeof(struct cpuinfo_processor*), max_processor_id); goto cleanup; @@ -488,7 +488,7 @@ void cpuinfo_riscv_linux_init(void) { linux_cpu_to_core_map = calloc(max_processor_id, sizeof(struct cpuinfo_core*)); if (linux_cpu_to_core_map == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for %zu core map.", + cpuinfo_log_error("failed to allocate %zu bytes for %"PRIu32" core map.", max_processor_id * sizeof(struct cpuinfo_core*), max_processor_id); goto cleanup; @@ -497,7 +497,7 @@ void cpuinfo_riscv_linux_init(void) { linux_cpu_to_uarch_index_map = calloc(max_processor_id, sizeof(struct cpuinfo_uarch_info*)); if (linux_cpu_to_uarch_index_map == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for %zu uarch map.", + cpuinfo_log_error("failed to allocate %zu bytes for %"PRIu32" uarch map.", max_processor_id * sizeof(struct cpuinfo_uarch_info*), max_processor_id); goto cleanup; From 20bd32c1b50d8d70f8ddd67e7e8782bf3847ebad Mon Sep 17 00:00:00 2001 From: snadampal <87143774+snadampal@users.noreply.github.com> Date: Thu, 16 Nov 2023 16:47:25 -0600 Subject: [PATCH 43/60] [arm] fix the logic for identifying the valid processors (#197) The current logic for valid processor detection is reporting all cpus irrespective of whether they are online or not. so, it's causing thread over-subscription for the scenarios where the online cpu count < the actual cpus. This is fixed by publishing only the online cpu count as the valid processors. --- src/arm/linux/init.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/src/arm/linux/init.c b/src/arm/linux/init.c index d3da5a9d..2501f39c 100644 --- a/src/arm/linux/init.c +++ b/src/arm/linux/init.c @@ -199,9 +199,13 @@ void cpuinfo_arm_linux_init(void) { for (uint32_t i = 0; i < arm_linux_processors_count; i++) { arm_linux_processors[i].system_processor_id = i; if (bitmask_all(arm_linux_processors[i].flags, CPUINFO_LINUX_FLAG_VALID)) { - valid_processors += 1; - - if (!(arm_linux_processors[i].flags & CPUINFO_ARM_LINUX_VALID_PROCESSOR)) { + if (arm_linux_processors[i].flags & CPUINFO_ARM_LINUX_VALID_PROCESSOR) { + /* + * Processor is in possible and present lists, and also reported in /proc/cpuinfo. + * This processor is availble for compute. + */ + valid_processors += 1; + } else { /* * Processor is in possible and present lists, but not reported in /proc/cpuinfo. * This is fairly common: high-index processors can be not reported if they are offline. From ef634603954d88d2643d5809011288b890ac126e Mon Sep 17 00:00:00 2001 From: Prashanth Swaminathan <40780424+prashanthswami@users.noreply.github.com> Date: Mon, 20 Nov 2023 10:46:35 -0800 Subject: [PATCH 44/60] Add android_riscv64 to BUILD.bazel (#201) --- BUILD.bazel | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/BUILD.bazel b/BUILD.bazel index 049c7f86..dc9634e7 100644 --- a/BUILD.bazel +++ b/BUILD.bazel @@ -299,6 +299,15 @@ config_setting( visibility = ["//visibility:public"], ) +config_setting( + name = "android_riscv64", + values = { + "crosstool_top": "//external:android/crosstool", + "cpu": "riscv64", + }, + visibility = ["//visibility:public"], +) + config_setting( name = "android_x86", values = { From 9d809924011af8ff49dadbda1499dc5193f1659c Mon Sep 17 00:00:00 2001 From: Prashanth Swaminathan <40780424+prashanthswami@users.noreply.github.com> Date: Tue, 28 Nov 2023 08:06:02 -0800 Subject: [PATCH 45/60] Fix CPU_SET dynamic allocation and leak (#205) The initial implementation had a number of issues: - The allocation of the CPU_SET should be checked for a NULL return. - The CPU_*_S macros should be used when working with dynamic sets. - The CPU_SET needs to be cleared via CPU_ZERO_S before use. - Dynamic CPU_SETs need to be freed after use. - The __riscv_hwprobe syscall is expecting a set *size* not a *count*. --- src/riscv/linux/riscv-hw.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/src/riscv/linux/riscv-hw.c b/src/riscv/linux/riscv-hw.c index ccee848c..befdf3f6 100644 --- a/src/riscv/linux/riscv-hw.c +++ b/src/riscv/linux/riscv-hw.c @@ -21,9 +21,16 @@ void cpuinfo_riscv_linux_decode_vendor_uarch_from_hwprobe( *uarch = cpuinfo_uarch_unknown; /* Create a CPU set with this processor flagged. */ - const size_t cpu_set_size = processor + 1; - cpu_set_t* cpu_set = CPU_ALLOC(cpu_set_size); - CPU_SET(processor, cpu_set); + const size_t cpu_count = processor + 1; + cpu_set_t* cpu_set = CPU_ALLOC(cpu_count); + if (cpu_set == NULL) { + cpuinfo_log_warning("failed to allocate space for cpu_set"); + return; + } + + const size_t cpu_set_size = CPU_ALLOC_SIZE(cpu_count); + CPU_ZERO_S(cpu_set_size, cpu_set); + CPU_SET_S(processor, cpu_set_size, cpu_set); /* Request all available information from hwprobe. */ int ret = __riscv_hwprobe(pairs, pairs_count, @@ -31,7 +38,7 @@ void cpuinfo_riscv_linux_decode_vendor_uarch_from_hwprobe( 0 /* flags */); if (ret < 0) { cpuinfo_log_warning("failed to get hwprobe information, err: %d", ret); - return; + goto cleanup; } /** @@ -59,4 +66,7 @@ void cpuinfo_riscv_linux_decode_vendor_uarch_from_hwprobe( } cpuinfo_riscv_decode_vendor_uarch(vendor_id, arch_id, imp_id, vendor, uarch); + +cleanup: + CPU_FREE(cpu_set); } From b8b29a164e7704b75ad66b072aa2db409cc941fd Mon Sep 17 00:00:00 2001 From: Prashanth Swaminathan <40780424+prashanthswami@users.noreply.github.com> Date: Thu, 30 Nov 2023 06:47:12 -0800 Subject: [PATCH 46/60] Fix chipset enum name to include 'vendor_' (#210) The original change that introduced this should have used a consistent prefix for all enum types, for consistency sake. --- src/riscv/api.h | 2 +- src/riscv/uarch.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/riscv/api.h b/src/riscv/api.h index cd4bf464..fc2220cb 100644 --- a/src/riscv/api.h +++ b/src/riscv/api.h @@ -8,7 +8,7 @@ /* RISC-V Vendor IDs. */ enum cpuinfo_riscv_chipset_vendor { cpuinfo_riscv_chipset_vendor_unknown = 0, - cpuinfo_riscv_chipset_sifive = 0x489, + cpuinfo_riscv_chipset_vendor_sifive = 0x489, cpuinfo_riscv_chipset_vendor_max, }; diff --git a/src/riscv/uarch.c b/src/riscv/uarch.c index bf93e867..6f4ff57d 100644 --- a/src/riscv/uarch.c +++ b/src/riscv/uarch.c @@ -11,7 +11,7 @@ void cpuinfo_riscv_decode_vendor_uarch( enum cpuinfo_uarch uarch[restrict static 1]) { /* The vendor ID is sufficient to determine the cpuinfo_vendor. */ switch(vendor_id) { - case cpuinfo_riscv_chipset_sifive: + case cpuinfo_riscv_chipset_vendor_sifive: *vendor = cpuinfo_vendor_sifive; break; default: From 2f4c278f7aa3e9a451c14c3e9a02c3e091140d96 Mon Sep 17 00:00:00 2001 From: Iacopo Colonnelli Date: Fri, 8 Dec 2023 06:34:03 +0100 Subject: [PATCH 47/60] Improve smallfile callback (#211) This PR improves the smallfile callback error reporting, passing the name of the inspected file in the `filename` argument instead of forcing it to be `KERNEL_MAX_FILENAME` as before. --- src/linux/api.h | 2 +- src/linux/processors.c | 6 +++--- src/linux/smallfile.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/linux/api.h b/src/linux/api.h index d33cbd7d..df02802c 100644 --- a/src/linux/api.h +++ b/src/linux/api.h @@ -26,7 +26,7 @@ typedef bool (*cpuinfo_cpulist_callback)(uint32_t, uint32_t, void*); CPUINFO_INTERNAL bool cpuinfo_linux_parse_cpulist(const char* filename, cpuinfo_cpulist_callback callback, void* context); -typedef bool (*cpuinfo_smallfile_callback)(const char*, const char*, void*); +typedef bool (*cpuinfo_smallfile_callback)(const char*, const char*, const char*, void*); CPUINFO_INTERNAL bool cpuinfo_linux_parse_small_file(const char* filename, size_t buffer_size, cpuinfo_smallfile_callback, void* context); typedef bool (*cpuinfo_line_callback)(const char*, const char*, void*, uint64_t); CPUINFO_INTERNAL bool cpuinfo_linux_parse_multiline_file(const char* filename, size_t buffer_size, cpuinfo_line_callback, void* context); diff --git a/src/linux/processors.c b/src/linux/processors.c index 246b4a2e..dcdd4e7c 100644 --- a/src/linux/processors.c +++ b/src/linux/processors.c @@ -88,7 +88,7 @@ inline static bool is_whitespace(char c) { static const uint32_t default_max_processors_count = CPU_SETSIZE; #endif -static bool uint32_parser(const char* text_start, const char* text_end, void* context) { +static bool uint32_parser(const char* filename, const char* text_start, const char* text_end, void* context) { if (text_start == text_end) { cpuinfo_log_error("failed to parse file %s: file is empty", KERNEL_MAX_FILENAME); return false; @@ -98,13 +98,13 @@ static bool uint32_parser(const char* text_start, const char* text_end, void* co const char* parsed_end = parse_number(text_start, text_end, &kernel_max); if (parsed_end == text_start) { cpuinfo_log_error("failed to parse file %s: \"%.*s\" is not an unsigned number", - KERNEL_MAX_FILENAME, (int) (text_end - text_start), text_start); + filename, (int) (text_end - text_start), text_start); return false; } else { for (const char* char_ptr = parsed_end; char_ptr != text_end; char_ptr++) { if (!is_whitespace(*char_ptr)) { cpuinfo_log_warning("non-whitespace characters \"%.*s\" following number in file %s are ignored", - (int) (text_end - char_ptr), char_ptr, KERNEL_MAX_FILENAME); + (int) (text_end - char_ptr), char_ptr, filename); break; } } diff --git a/src/linux/smallfile.c b/src/linux/smallfile.c index 98cde00e..dbe023bb 100644 --- a/src/linux/smallfile.c +++ b/src/linux/smallfile.c @@ -55,7 +55,7 @@ bool cpuinfo_linux_parse_small_file(const char* filename, size_t buffer_size, cp } } while (bytes_read != 0); - status = callback(buffer, &buffer[buffer_position], context); + status = callback(filename, buffer, &buffer[buffer_position], context); cleanup: if (file != -1) { From 313524ab20d2041854af8ad07bf726ddd485d258 Mon Sep 17 00:00:00 2001 From: Mark Ryan Date: Fri, 5 Jan 2024 18:26:21 +0000 Subject: [PATCH 48/60] Fix RISC-V Linux build (#212) Cpuinfo was failing to build on RISC-V Linux distributions, e.g., Ubuntu 23.10, as it includes a header file sys/hwprobe.h that is not yet provided by glibc (although it is provided by bionic). We fix the issue by only including sys/hwprobe.h when building for Android, and invoking the hwprobe syscall directly on other Linux distributions. The Android specific check can be removed in the future once sys/hwprobe.h becomes available in glibc. --- src/riscv/linux/riscv-hw.c | 80 +++++++++++++++++++++++++++++++++++++- 1 file changed, 79 insertions(+), 1 deletion(-) diff --git a/src/riscv/linux/riscv-hw.c b/src/riscv/linux/riscv-hw.c index befdf3f6..f589b3fc 100644 --- a/src/riscv/linux/riscv-hw.c +++ b/src/riscv/linux/riscv-hw.c @@ -1,10 +1,74 @@ -#include +/* + * Only enable the C standard library hwprobe interface on Android for now. + * Patches to add a compatible hwprobe API to glibc are available but not + * merged at the time of writing and so cannot easily be tested. The + * #ifdef __ANDROID__ check will be removed in the future. + */ +#ifdef __ANDROID__ + #ifdef __has_include + #if __has_include () + #define CPUINFO_RISCV_LINUX_HAVE_C_HWPROBE + #include + #endif + #endif +#endif + #include #include #include #include +#ifndef CPUINFO_RISCV_LINUX_HAVE_C_HWPROBE + + #include + #include + #include + + struct riscv_hwprobe { + int64_t key; + uint64_t value; + }; + + /* + * The standard C library our binary was compiled with does not support + * hwprobe but the kernel on which we are running might do. The + * constants below are copied from + * /usr/include/riscv64-linux-gnu/asm/hwprobe.h. They allow us to + * invoke the hwprobe syscall directly. We duplicate the constants + * rather than including the kernel hwprobe.h header, as this header + * will only be present if we're building Linux 6.4 or greater. + */ + + #define RISCV_HWPROBE_KEY_MVENDORID 0 + #define RISCV_HWPROBE_KEY_MARCHID 1 + #define RISCV_HWPROBE_KEY_MIMPID 2 + #define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3 + #define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0) + #define RISCV_HWPROBE_KEY_IMA_EXT_0 4 + #define RISCV_HWPROBE_IMA_FD (1 << 0) + #define RISCV_HWPROBE_IMA_C (1 << 1) + #define RISCV_HWPROBE_IMA_V (1 << 2) + #define RISCV_HWPROBE_EXT_ZBA (1 << 3) + #define RISCV_HWPROBE_EXT_ZBB (1 << 4) + #define RISCV_HWPROBE_EXT_ZBS (1 << 5) + #define RISCV_HWPROBE_EXT_ZICBOZ (1 << 6) + #define RISCV_HWPROBE_KEY_CPUPERF_0 5 + #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) + #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) + #define RISCV_HWPROBE_MISALIGNED_SLOW (2 << 0) + #define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0) + #define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0) + #define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0) + + #ifndef NR_riscv_hwprobe + #ifndef NR_arch_specific_syscall + #define NR_arch_specific_syscall 244 + #endif + #define NR_riscv_hwprobe (NR_arch_specific_syscall + 14) + #endif +#endif + void cpuinfo_riscv_linux_decode_vendor_uarch_from_hwprobe( uint32_t processor, enum cpuinfo_vendor vendor[restrict static 1], @@ -33,9 +97,23 @@ void cpuinfo_riscv_linux_decode_vendor_uarch_from_hwprobe( CPU_SET_S(processor, cpu_set_size, cpu_set); /* Request all available information from hwprobe. */ +#ifndef CPUINFO_RISCV_LINUX_HAVE_C_HWPROBE + /* + * No standard library support for hwprobe. We'll need to invoke the + * syscall directly. See + * + * https://docs.kernel.org/arch/riscv/hwprobe.html + * + * for more details. + */ + int ret = syscall(NR_riscv_hwprobe, pairs, pairs_count, + cpu_set_size, (unsigned long*)cpu_set, + 0 /* flags */); +#else int ret = __riscv_hwprobe(pairs, pairs_count, cpu_set_size, (unsigned long*)cpu_set, 0 /* flags */); +#endif if (ret < 0) { cpuinfo_log_warning("failed to get hwprobe information, err: %d", ret); goto cleanup; From 42bff7ad39de3eb520cb20ab27f51ed816935edc Mon Sep 17 00:00:00 2001 From: Prashanth Swaminathan <40780424+prashanthswami@users.noreply.github.com> Date: Fri, 5 Jan 2024 17:17:27 -0800 Subject: [PATCH 49/60] Add .clang-format to enforce project style (#204) * Add .clang-format to enforce project style The settings here match the current settings for the pytorch/pytorch project, with the exception that 8-character-width tabs are preferred in place of spaces. * Mass reformat of all .c and .h files Now that we have a clang-format file defined, clean up all usages once. * Enable clang-format-check workflow Enforce clang-format consistency on all new changes. --- .clang-format | 85 + .github/workflows/clang-format-check.yml | 12 + bench/get-current.cc | 1 - bench/init.cc | 1 - include/cpuinfo-mock.h | 56 +- include/cpuinfo.h | 2286 ++++++------ src/api.c | 327 +- src/arm/android/api.h | 4 +- src/arm/android/properties.c | 53 +- src/arm/api.h | 74 +- src/arm/cache.c | 1632 ++++---- src/arm/linux/aarch32-isa.c | 212 +- src/arm/linux/aarch64-isa.c | 33 +- src/arm/linux/api.h | 399 +- src/arm/linux/chipset.c | 3245 ++++++++-------- src/arm/linux/clusters.c | 403 +- src/arm/linux/cp.h | 81 +- src/arm/linux/cpuinfo.c | 596 +-- src/arm/linux/hwcap.c | 259 +- src/arm/linux/init.c | 499 +-- src/arm/linux/midr.c | 1239 ++++--- src/arm/mach/init.c | 204 +- src/arm/midr.h | 75 +- src/arm/tlb.c | 163 +- src/arm/uarch.c | 126 +- src/arm/windows/init-by-logical-sys-info.c | 518 +-- src/arm/windows/init.c | 156 +- src/arm/windows/windows-arm-init.h | 12 +- src/cache.c | 21 +- src/cpuinfo/common.h | 39 +- src/cpuinfo/internal-api.h | 37 +- src/cpuinfo/log.h | 87 +- src/cpuinfo/utils.h | 15 +- src/emscripten/init.c | 79 +- src/init.c | 78 +- src/linux/api.h | 68 +- src/linux/cpulist.c | 128 +- src/linux/mockfile.c | 26 +- src/linux/multiline.c | 51 +- src/linux/processors.c | 355 +- src/linux/smallfile.c | 38 +- src/log.c | 301 +- src/mach/api.h | 2 - src/mach/topology.c | 14 +- src/riscv/api.h | 10 +- src/riscv/linux/api.h | 24 +- src/riscv/linux/init.c | 203 +- src/riscv/linux/riscv-hw.c | 126 +- src/riscv/linux/riscv-isa.c | 17 +- src/riscv/uarch.c | 4 +- src/x86/api.h | 24 +- src/x86/cache/descriptor.c | 916 +++-- src/x86/cache/deterministic.c | 90 +- src/x86/cache/init.c | 39 +- src/x86/cpuid.h | 122 +- src/x86/info.c | 13 +- src/x86/init.c | 35 +- src/x86/isa.c | 214 +- src/x86/linux/api.h | 3 +- src/x86/linux/cpuinfo.c | 96 +- src/x86/linux/init.c | 295 +- src/x86/mach/init.c | 194 +- src/x86/mockcpuid.c | 8 +- src/x86/name.c | 282 +- src/x86/topology.c | 102 +- src/x86/uarch.c | 289 +- src/x86/vendor.c | 20 +- src/x86/windows/api.h | 24 +- src/x86/windows/init.c | 349 +- test/arm-cache.cc | 2346 +++++++----- test/get-current.cc | 1 - test/init.cc | 16 +- test/mock/alcatel-revvl.cc | 97 +- test/mock/alcatel-revvl.h | 825 +++-- test/mock/alldocube-iwork8.cc | 27 +- test/mock/alldocube-iwork8.h | 259 +- test/mock/atm7029b-tablet.cc | 27 +- test/mock/atm7029b-tablet.h | 44 +- test/mock/blu-r1-hd.cc | 27 +- test/mock/blu-r1-hd.h | 75 +- test/mock/galaxy-a3-2016-eu.cc | 97 +- test/mock/galaxy-a3-2016-eu.h | 150 +- test/mock/galaxy-a8-2016-duos.cc | 27 +- test/mock/galaxy-a8-2016-duos.h | 235 +- test/mock/galaxy-a8-2018.cc | 97 +- test/mock/galaxy-a8-2018.h | 341 +- test/mock/galaxy-c9-pro.cc | 97 +- test/mock/galaxy-c9-pro.h | 522 ++- test/mock/galaxy-grand-prime-value-edition.cc | 27 +- test/mock/galaxy-grand-prime-value-edition.h | 140 +- test/mock/galaxy-j1-2016.cc | 27 +- test/mock/galaxy-j1-2016.h | 130 +- test/mock/galaxy-j5.cc | 27 +- test/mock/galaxy-j5.h | 81 +- test/mock/galaxy-j7-prime.cc | 97 +- test/mock/galaxy-j7-prime.h | 144 +- test/mock/galaxy-j7-tmobile.cc | 97 +- test/mock/galaxy-j7-tmobile.h | 205 +- test/mock/galaxy-j7-uae.cc | 97 +- test/mock/galaxy-j7-uae.h | 503 ++- test/mock/galaxy-s3-us.cc | 31 +- test/mock/galaxy-s3-us.h | 510 ++- test/mock/galaxy-s4-us.cc | 31 +- test/mock/galaxy-s4-us.h | 720 ++-- test/mock/galaxy-s5-global.cc | 27 +- test/mock/galaxy-s5-global.h | 680 ++-- test/mock/galaxy-s5-us.cc | 31 +- test/mock/galaxy-s5-us.h | 731 ++-- test/mock/galaxy-s6.cc | 97 +- test/mock/galaxy-s6.h | 269 +- test/mock/galaxy-s7-global.cc | 97 +- test/mock/galaxy-s7-global.h | 683 ++-- test/mock/galaxy-s7-us.cc | 97 +- test/mock/galaxy-s7-us.h | 387 +- test/mock/galaxy-s8-global.cc | 97 +- test/mock/galaxy-s8-global.h | 333 +- test/mock/galaxy-s8-us.cc | 97 +- test/mock/galaxy-s8-us.h | 1081 +++--- test/mock/galaxy-s9-global.cc | 113 +- test/mock/galaxy-s9-global.h | 393 +- test/mock/galaxy-s9-us.cc | 113 +- test/mock/galaxy-s9-us.h | 1059 +++--- test/mock/galaxy-tab-3-7.0.cc | 27 +- test/mock/galaxy-tab-3-7.0.h | 55 +- test/mock/galaxy-tab-3-lite.cc | 27 +- test/mock/galaxy-tab-3-lite.h | 42 +- test/mock/galaxy-win-duos.cc | 27 +- test/mock/galaxy-win-duos.h | 81 +- test/mock/huawei-ascend-p7.cc | 27 +- test/mock/huawei-ascend-p7.h | 96 +- test/mock/huawei-honor-6.cc | 27 +- test/mock/huawei-honor-6.h | 179 +- test/mock/huawei-mate-10.cc | 97 +- test/mock/huawei-mate-10.h | 361 +- test/mock/huawei-mate-20.cc | 113 +- test/mock/huawei-mate-20.h | 357 +- test/mock/huawei-mate-8.cc | 97 +- test/mock/huawei-mate-8.h | 407 +- test/mock/huawei-mate-9.cc | 97 +- test/mock/huawei-mate-9.h | 359 +- test/mock/huawei-p20-pro.cc | 97 +- test/mock/huawei-p20-pro.h | 361 +- test/mock/huawei-p8-lite.cc | 97 +- test/mock/huawei-p8-lite.h | 96 +- test/mock/huawei-p9-lite.cc | 97 +- test/mock/huawei-p9-lite.h | 786 ++-- test/mock/iconia-one-10.cc | 97 +- test/mock/iconia-one-10.h | 188 +- test/mock/leagoo-t5c.cc | 27 +- test/mock/leagoo-t5c.h | 784 ++-- test/mock/lenovo-a6600-plus.cc | 27 +- test/mock/lenovo-a6600-plus.h | 92 +- test/mock/lenovo-vibe-x2.cc | 27 +- test/mock/lenovo-vibe-x2.h | 57 +- test/mock/lg-k10-eu.cc | 27 +- test/mock/lg-k10-eu.h | 161 +- test/mock/lg-optimus-g-pro.cc | 31 +- test/mock/lg-optimus-g-pro.h | 144 +- test/mock/meizu-pro-6.cc | 97 +- test/mock/meizu-pro-6.h | 1010 +++-- test/mock/meizu-pro-6s.cc | 97 +- test/mock/meizu-pro-6s.h | 2610 ++++++------- test/mock/meizu-pro-7-plus.cc | 97 +- test/mock/meizu-pro-7-plus.h | 3269 ++++++++--------- test/mock/memo-pad-7.cc | 27 +- test/mock/memo-pad-7.h | 99 +- test/mock/moto-e-gen1.cc | 27 +- test/mock/moto-e-gen1.h | 58 +- test/mock/moto-g-gen1.cc | 27 +- test/mock/moto-g-gen1.h | 72 +- test/mock/moto-g-gen2.cc | 27 +- test/mock/moto-g-gen2.h | 117 +- test/mock/moto-g-gen3.cc | 27 +- test/mock/moto-g-gen3.h | 80 +- test/mock/moto-g-gen4.cc | 97 +- test/mock/moto-g-gen4.h | 62 +- test/mock/moto-g-gen5.cc | 27 +- test/mock/moto-g-gen5.h | 215 +- test/mock/nexus-s.cc | 15 +- test/mock/nexus-s.h | 40 +- test/mock/nexus10.cc | 27 +- test/mock/nexus10.h | 140 +- test/mock/nexus4.cc | 27 +- test/mock/nexus4.h | 137 +- test/mock/nexus5x.cc | 97 +- test/mock/nexus5x.h | 179 +- test/mock/nexus6.cc | 27 +- test/mock/nexus6.h | 177 +- test/mock/nexus6p.cc | 97 +- test/mock/nexus6p.h | 162 +- test/mock/nexus9.cc | 97 +- test/mock/nexus9.h | 342 +- test/mock/oneplus-3t.cc | 97 +- test/mock/oneplus-3t.h | 381 +- test/mock/oneplus-5.cc | 97 +- test/mock/oneplus-5.h | 1131 +++--- test/mock/oneplus-5t.cc | 97 +- test/mock/oneplus-5t.h | 1131 +++--- test/mock/oppo-a37.cc | 107 +- test/mock/oppo-a37.h | 130 +- test/mock/oppo-r15.cc | 97 +- test/mock/oppo-r15.h | 2855 +++++++------- test/mock/oppo-r9.cc | 147 +- test/mock/oppo-r9.h | 90 +- test/mock/padcod-10.1.cc | 27 +- test/mock/padcod-10.1.h | 261 +- test/mock/pixel-2-xl.cc | 97 +- test/mock/pixel-2-xl.h | 718 ++-- test/mock/pixel-c.cc | 97 +- test/mock/pixel-c.h | 288 +- test/mock/pixel-xl.cc | 97 +- test/mock/pixel-xl.h | 287 +- test/mock/pixel.cc | 97 +- test/mock/pixel.h | 287 +- test/mock/scaleway.cc | 3 +- test/mock/scaleway.h | 111 +- test/mock/xiaomi-mi-5c.cc | 97 +- test/mock/xiaomi-mi-5c.h | 697 ++-- test/mock/xiaomi-redmi-2a.cc | 27 +- test/mock/xiaomi-redmi-2a.h | 193 +- test/mock/xiaomi-redmi-note-3.cc | 97 +- test/mock/xiaomi-redmi-note-3.h | 409 +-- test/mock/xiaomi-redmi-note-4.cc | 97 +- test/mock/xiaomi-redmi-note-4.h | 408 +- test/mock/xperia-c4-dual.cc | 147 +- test/mock/xperia-c4-dual.h | 72 +- test/mock/xperia-sl.cc | 31 +- test/mock/xperia-sl.h | 89 +- test/mock/zenfone-2.cc | 27 +- test/mock/zenfone-2.h | 2709 +++++++------- test/mock/zenfone-2e.cc | 27 +- test/mock/zenfone-2e.h | 95 +- test/mock/zenfone-c.cc | 27 +- test/mock/zenfone-c.h | 79 +- test/name/android-properties-interface.c | 56 +- test/name/android-properties.cc | 156 +- test/name/brand-string.cc | 879 ++--- test/name/proc-cpuinfo-hardware.cc | 1051 ++---- test/name/ro-arch.cc | 64 +- test/name/ro-board-platform.cc | 365 +- test/name/ro-chipname.cc | 231 +- test/name/ro-mediatek-platform.cc | 133 +- test/name/ro-product-board.cc | 633 ++-- test/size.c | 1 - tools/auxv-dump.c | 15 +- tools/cache-info.c | 31 +- tools/cpu-info.c | 75 +- tools/cpuid-dump.c | 45 +- tools/cpuinfo-dump.c | 16 +- tools/gpu-dump.c | 70 +- tools/isa-info.c | 267 +- 251 files changed, 33425 insertions(+), 32250 deletions(-) create mode 100644 .clang-format create mode 100644 .github/workflows/clang-format-check.yml diff --git a/.clang-format b/.clang-format new file mode 100644 index 00000000..5a5b71d6 --- /dev/null +++ b/.clang-format @@ -0,0 +1,85 @@ +--- +AccessModifierOffset: -1 +AlignAfterOpenBracket: AlwaysBreak +AlignConsecutiveAssignments: false +AlignConsecutiveDeclarations: false +AlignEscapedNewlinesLeft: true +AlignOperands: false +AlignTrailingComments: false +AllowAllParametersOfDeclarationOnNextLine: false +AllowShortBlocksOnASingleLine: false +AllowShortCaseLabelsOnASingleLine: false +AllowShortFunctionsOnASingleLine: Empty +AllowShortIfStatementsOnASingleLine: false +AllowShortLoopsOnASingleLine: false +AlwaysBreakAfterReturnType: None +AlwaysBreakBeforeMultilineStrings: true +AlwaysBreakTemplateDeclarations: true +BinPackArguments: false +BinPackParameters: false +BraceWrapping: + AfterClass: false + AfterControlStatement: false + AfterEnum: false + AfterFunction: false + AfterNamespace: false + AfterObjCDeclaration: false + AfterStruct: false + AfterUnion: false + BeforeCatch: false + BeforeElse: false + IndentBraces: false +BreakBeforeBinaryOperators: None +BreakBeforeBraces: Attach +BreakBeforeTernaryOperators: true +BreakConstructorInitializersBeforeComma: false +BreakAfterJavaFieldAnnotations: false +BreakStringLiterals: false +ColumnLimit: 120 +CommentPragmas: '^ IWYU pragma:' +CompactNamespaces: false +ConstructorInitializerAllOnOneLineOrOnePerLine: true +ConstructorInitializerIndentWidth: 8 +ContinuationIndentWidth: 8 +Cpp11BracedListStyle: true +DerivePointerAlignment: false +DisableFormat: false +ForEachMacros: [ FOR_EACH_RANGE, FOR_EACH, ] +IncludeCategories: + - Regex: '^<.*\.h(pp)?>' + Priority: 1 + - Regex: '^<.*' + Priority: 2 + - Regex: '.*' + Priority: 3 +IndentCaseLabels: true +IndentWidth: 8 +IndentWrappedFunctionNames: false +KeepEmptyLinesAtTheStartOfBlocks: false +MacroBlockBegin: '' +MacroBlockEnd: '' +MaxEmptyLinesToKeep: 1 +NamespaceIndentation: None +PenaltyBreakBeforeFirstCallParameter: 1 +PenaltyBreakComment: 300 +PenaltyBreakFirstLessLess: 120 +PenaltyBreakString: 1000 +PenaltyExcessCharacter: 1000000 +PenaltyReturnTypeOnItsOwnLine: 2000000 +PointerAlignment: Left +ReflowComments: true +SortIncludes: true +SpaceAfterCStyleCast: false +SpaceBeforeAssignmentOperators: true +SpaceBeforeParens: ControlStatements +SpaceInEmptyParentheses: false +SpacesBeforeTrailingComments: 1 +SpacesInAngles: false +SpacesInContainerLiterals: true +SpacesInCStyleCastParentheses: false +SpacesInParentheses: false +SpacesInSquareBrackets: false +Standard: Cpp11 +TabWidth: 8 +UseTab: Always +--- diff --git a/.github/workflows/clang-format-check.yml b/.github/workflows/clang-format-check.yml new file mode 100644 index 00000000..9ea18e5a --- /dev/null +++ b/.github/workflows/clang-format-check.yml @@ -0,0 +1,12 @@ +name: clang-format +on: [push, pull_request] +jobs: + formatting-check: + name: Formatting Check + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v2 + - name: Run clang-format style check. + uses: jidicula/clang-format-action@v4.5.0 + with: + exclude-regex: 'deps\/' diff --git a/bench/get-current.cc b/bench/get-current.cc index e4757674..9fbcf51b 100644 --- a/bench/get-current.cc +++ b/bench/get-current.cc @@ -2,7 +2,6 @@ #include - static void cpuinfo_get_current_processor(benchmark::State& state) { cpuinfo_initialize(); while (state.KeepRunning()) { diff --git a/bench/init.cc b/bench/init.cc index 6df8e0e6..14cc7208 100644 --- a/bench/init.cc +++ b/bench/init.cc @@ -2,7 +2,6 @@ #include - static void cpuinfo_initialize(benchmark::State& state) { while (state.KeepRunning()) { cpuinfo_initialize(); diff --git a/include/cpuinfo-mock.h b/include/cpuinfo-mock.h index 3c1f637d..5e129aa6 100644 --- a/include/cpuinfo-mock.h +++ b/include/cpuinfo-mock.h @@ -7,37 +7,35 @@ #include #if defined(__linux__) - #include +#include #endif #if !defined(CPUINFO_MOCK) || !(CPUINFO_MOCK) - #error This header is intended only for test use +#error This header is intended only for test use #endif - #ifdef __cplusplus extern "C" { #endif - #if CPUINFO_ARCH_ARM - void CPUINFO_ABI cpuinfo_set_fpsid(uint32_t fpsid); - void CPUINFO_ABI cpuinfo_set_wcid(uint32_t wcid); +void CPUINFO_ABI cpuinfo_set_fpsid(uint32_t fpsid); +void CPUINFO_ABI cpuinfo_set_wcid(uint32_t wcid); #endif /* CPUINFO_ARCH_ARM */ #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - struct cpuinfo_mock_cpuid { - uint32_t input_eax; - uint32_t input_ecx; - uint32_t eax; - uint32_t ebx; - uint32_t ecx; - uint32_t edx; - }; +struct cpuinfo_mock_cpuid { + uint32_t input_eax; + uint32_t input_ecx; + uint32_t eax; + uint32_t ebx; + uint32_t ecx; + uint32_t edx; +}; - void CPUINFO_ABI cpuinfo_mock_set_cpuid(struct cpuinfo_mock_cpuid* dump, size_t entries); - void CPUINFO_ABI cpuinfo_mock_get_cpuid(uint32_t eax, uint32_t regs[4]); - void CPUINFO_ABI cpuinfo_mock_get_cpuidex(uint32_t eax, uint32_t ecx, uint32_t regs[4]); +void CPUINFO_ABI cpuinfo_mock_set_cpuid(struct cpuinfo_mock_cpuid* dump, size_t entries); +void CPUINFO_ABI cpuinfo_mock_get_cpuid(uint32_t eax, uint32_t regs[4]); +void CPUINFO_ABI cpuinfo_mock_get_cpuidex(uint32_t eax, uint32_t ecx, uint32_t regs[4]); #endif /* CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 */ struct cpuinfo_mock_file { @@ -53,22 +51,22 @@ struct cpuinfo_mock_property { }; #if defined(__linux__) - void CPUINFO_ABI cpuinfo_mock_filesystem(struct cpuinfo_mock_file* files); - int CPUINFO_ABI cpuinfo_mock_open(const char* path, int oflag); - int CPUINFO_ABI cpuinfo_mock_close(int fd); - ssize_t CPUINFO_ABI cpuinfo_mock_read(int fd, void* buffer, size_t capacity); +void CPUINFO_ABI cpuinfo_mock_filesystem(struct cpuinfo_mock_file* files); +int CPUINFO_ABI cpuinfo_mock_open(const char* path, int oflag); +int CPUINFO_ABI cpuinfo_mock_close(int fd); +ssize_t CPUINFO_ABI cpuinfo_mock_read(int fd, void* buffer, size_t capacity); - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 - void CPUINFO_ABI cpuinfo_set_hwcap(uint32_t hwcap); - #endif - #if CPUINFO_ARCH_ARM - void CPUINFO_ABI cpuinfo_set_hwcap2(uint32_t hwcap2); - #endif +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 +void CPUINFO_ABI cpuinfo_set_hwcap(uint32_t hwcap); +#endif +#if CPUINFO_ARCH_ARM +void CPUINFO_ABI cpuinfo_set_hwcap2(uint32_t hwcap2); +#endif #endif #if defined(__ANDROID__) - void CPUINFO_ABI cpuinfo_mock_android_properties(struct cpuinfo_mock_property* properties); - void CPUINFO_ABI cpuinfo_mock_gl_renderer(const char* renderer); +void CPUINFO_ABI cpuinfo_mock_android_properties(struct cpuinfo_mock_property* properties); +void CPUINFO_ABI cpuinfo_mock_gl_renderer(const char* renderer); #endif #ifdef __cplusplus diff --git a/include/cpuinfo.h b/include/cpuinfo.h index 3fbcad2a..275c83f9 100644 --- a/include/cpuinfo.h +++ b/include/cpuinfo.h @@ -3,11 +3,11 @@ #define CPUINFO_H #ifndef __cplusplus - #include +#include #endif #ifdef __APPLE__ - #include +#include #endif #include @@ -15,97 +15,97 @@ /* Identify architecture and define corresponding macro */ #if defined(__i386__) || defined(__i486__) || defined(__i586__) || defined(__i686__) || defined(_M_IX86) - #define CPUINFO_ARCH_X86 1 +#define CPUINFO_ARCH_X86 1 #endif #if defined(__x86_64__) || defined(__x86_64) || defined(_M_X64) || defined(_M_AMD64) - #define CPUINFO_ARCH_X86_64 1 +#define CPUINFO_ARCH_X86_64 1 #endif #if defined(__arm__) || defined(_M_ARM) - #define CPUINFO_ARCH_ARM 1 +#define CPUINFO_ARCH_ARM 1 #endif #if defined(__aarch64__) || defined(_M_ARM64) - #define CPUINFO_ARCH_ARM64 1 +#define CPUINFO_ARCH_ARM64 1 #endif #if defined(__PPC64__) || defined(__powerpc64__) || defined(_ARCH_PPC64) - #define CPUINFO_ARCH_PPC64 1 +#define CPUINFO_ARCH_PPC64 1 #endif #if defined(__asmjs__) - #define CPUINFO_ARCH_ASMJS 1 +#define CPUINFO_ARCH_ASMJS 1 #endif #if defined(__wasm__) - #if defined(__wasm_simd128__) - #define CPUINFO_ARCH_WASMSIMD 1 - #else - #define CPUINFO_ARCH_WASM 1 - #endif +#if defined(__wasm_simd128__) +#define CPUINFO_ARCH_WASMSIMD 1 +#else +#define CPUINFO_ARCH_WASM 1 +#endif #endif #if defined(__riscv) - #if (__riscv_xlen == 32) - #define CPUINFO_ARCH_RISCV32 1 - #elif (__riscv_xlen == 64) - #define CPUINFO_ARCH_RISCV64 1 - #endif +#if (__riscv_xlen == 32) +#define CPUINFO_ARCH_RISCV32 1 +#elif (__riscv_xlen == 64) +#define CPUINFO_ARCH_RISCV64 1 +#endif #endif /* Define other architecture-specific macros as 0 */ #ifndef CPUINFO_ARCH_X86 - #define CPUINFO_ARCH_X86 0 +#define CPUINFO_ARCH_X86 0 #endif #ifndef CPUINFO_ARCH_X86_64 - #define CPUINFO_ARCH_X86_64 0 +#define CPUINFO_ARCH_X86_64 0 #endif #ifndef CPUINFO_ARCH_ARM - #define CPUINFO_ARCH_ARM 0 +#define CPUINFO_ARCH_ARM 0 #endif #ifndef CPUINFO_ARCH_ARM64 - #define CPUINFO_ARCH_ARM64 0 +#define CPUINFO_ARCH_ARM64 0 #endif #ifndef CPUINFO_ARCH_PPC64 - #define CPUINFO_ARCH_PPC64 0 +#define CPUINFO_ARCH_PPC64 0 #endif #ifndef CPUINFO_ARCH_ASMJS - #define CPUINFO_ARCH_ASMJS 0 +#define CPUINFO_ARCH_ASMJS 0 #endif #ifndef CPUINFO_ARCH_WASM - #define CPUINFO_ARCH_WASM 0 +#define CPUINFO_ARCH_WASM 0 #endif #ifndef CPUINFO_ARCH_WASMSIMD - #define CPUINFO_ARCH_WASMSIMD 0 +#define CPUINFO_ARCH_WASMSIMD 0 #endif #ifndef CPUINFO_ARCH_RISCV32 - #define CPUINFO_ARCH_RISCV32 0 +#define CPUINFO_ARCH_RISCV32 0 #endif #ifndef CPUINFO_ARCH_RISCV64 - #define CPUINFO_ARCH_RISCV64 0 +#define CPUINFO_ARCH_RISCV64 0 #endif #if CPUINFO_ARCH_X86 && defined(_MSC_VER) - #define CPUINFO_ABI __cdecl +#define CPUINFO_ABI __cdecl #elif CPUINFO_ARCH_X86 && defined(__GNUC__) - #define CPUINFO_ABI __attribute__((__cdecl__)) +#define CPUINFO_ABI __attribute__((__cdecl__)) #else - #define CPUINFO_ABI +#define CPUINFO_ABI #endif -#define CPUINFO_CACHE_UNIFIED 0x00000001 -#define CPUINFO_CACHE_INCLUSIVE 0x00000002 +#define CPUINFO_CACHE_UNIFIED 0x00000001 +#define CPUINFO_CACHE_INCLUSIVE 0x00000002 #define CPUINFO_CACHE_COMPLEX_INDEXING 0x00000004 struct cpuinfo_cache { @@ -120,9 +120,11 @@ struct cpuinfo_cache { /** Line size in bytes */ uint32_t line_size; /** - * Binary characteristics of the cache (unified cache, inclusive cache, cache with complex indexing). + * Binary characteristics of the cache (unified cache, inclusive cache, + * cache with complex indexing). * - * @see CPUINFO_CACHE_UNIFIED, CPUINFO_CACHE_INCLUSIVE, CPUINFO_CACHE_COMPLEX_INDEXING + * @see CPUINFO_CACHE_UNIFIED, CPUINFO_CACHE_INCLUSIVE, + * CPUINFO_CACHE_COMPLEX_INDEXING */ uint32_t flags; /** Index of the first logical processor that shares this cache */ @@ -136,12 +138,12 @@ struct cpuinfo_trace_cache { uint32_t associativity; }; -#define CPUINFO_PAGE_SIZE_4KB 0x1000 -#define CPUINFO_PAGE_SIZE_1MB 0x100000 -#define CPUINFO_PAGE_SIZE_2MB 0x200000 -#define CPUINFO_PAGE_SIZE_4MB 0x400000 +#define CPUINFO_PAGE_SIZE_4KB 0x1000 +#define CPUINFO_PAGE_SIZE_1MB 0x100000 +#define CPUINFO_PAGE_SIZE_2MB 0x200000 +#define CPUINFO_PAGE_SIZE_4MB 0x400000 #define CPUINFO_PAGE_SIZE_16MB 0x1000000 -#define CPUINFO_PAGE_SIZE_1GB 0x40000000 +#define CPUINFO_PAGE_SIZE_1GB 0x40000000 struct cpuinfo_tlb { uint32_t entries; @@ -151,74 +153,95 @@ struct cpuinfo_tlb { /** Vendor of processor core design */ enum cpuinfo_vendor { - /** Processor vendor is not known to the library, or the library failed to get vendor information from the OS. */ + /** Processor vendor is not known to the library, or the library failed + to get vendor information from the OS. */ cpuinfo_vendor_unknown = 0, /* Active vendors of modern CPUs */ /** - * Intel Corporation. Vendor of x86, x86-64, IA64, and ARM processor microarchitectures. + * Intel Corporation. Vendor of x86, x86-64, IA64, and ARM processor + * microarchitectures. * - * Sold its ARM design subsidiary in 2006. The last ARM processor design was released in 2004. + * Sold its ARM design subsidiary in 2006. The last ARM processor design + * was released in 2004. */ - cpuinfo_vendor_intel = 1, - /** Advanced Micro Devices, Inc. Vendor of x86 and x86-64 processor microarchitectures. */ - cpuinfo_vendor_amd = 2, - /** ARM Holdings plc. Vendor of ARM and ARM64 processor microarchitectures. */ - cpuinfo_vendor_arm = 3, - /** Qualcomm Incorporated. Vendor of ARM and ARM64 processor microarchitectures. */ + cpuinfo_vendor_intel = 1, + /** Advanced Micro Devices, Inc. Vendor of x86 and x86-64 processor + microarchitectures. */ + cpuinfo_vendor_amd = 2, + /** ARM Holdings plc. Vendor of ARM and ARM64 processor + microarchitectures. */ + cpuinfo_vendor_arm = 3, + /** Qualcomm Incorporated. Vendor of ARM and ARM64 processor + microarchitectures. */ cpuinfo_vendor_qualcomm = 4, /** Apple Inc. Vendor of ARM and ARM64 processor microarchitectures. */ - cpuinfo_vendor_apple = 5, - /** Samsung Electronics Co., Ltd. Vendir if ARM64 processor microarchitectures. */ - cpuinfo_vendor_samsung = 6, - /** Nvidia Corporation. Vendor of ARM64-compatible processor microarchitectures. */ - cpuinfo_vendor_nvidia = 7, - /** MIPS Technologies, Inc. Vendor of MIPS processor microarchitectures. */ - cpuinfo_vendor_mips = 8, - /** International Business Machines Corporation. Vendor of PowerPC processor microarchitectures. */ - cpuinfo_vendor_ibm = 9, - /** Ingenic Semiconductor. Vendor of MIPS processor microarchitectures. */ - cpuinfo_vendor_ingenic = 10, + cpuinfo_vendor_apple = 5, + /** Samsung Electronics Co., Ltd. Vendir if ARM64 processor + microarchitectures. */ + cpuinfo_vendor_samsung = 6, + /** Nvidia Corporation. Vendor of ARM64-compatible processor + microarchitectures. */ + cpuinfo_vendor_nvidia = 7, + /** MIPS Technologies, Inc. Vendor of MIPS processor microarchitectures. + */ + cpuinfo_vendor_mips = 8, + /** International Business Machines Corporation. Vendor of PowerPC + processor microarchitectures. */ + cpuinfo_vendor_ibm = 9, + /** Ingenic Semiconductor. Vendor of MIPS processor microarchitectures. + */ + cpuinfo_vendor_ingenic = 10, /** - * VIA Technologies, Inc. Vendor of x86 and x86-64 processor microarchitectures. + * VIA Technologies, Inc. Vendor of x86 and x86-64 processor + * microarchitectures. * - * Processors are designed by Centaur Technology, a subsidiary of VIA Technologies. + * Processors are designed by Centaur Technology, a subsidiary of VIA + * Technologies. */ - cpuinfo_vendor_via = 11, + cpuinfo_vendor_via = 11, /** Cavium, Inc. Vendor of ARM64 processor microarchitectures. */ - cpuinfo_vendor_cavium = 12, + cpuinfo_vendor_cavium = 12, /** Broadcom, Inc. Vendor of ARM processor microarchitectures. */ cpuinfo_vendor_broadcom = 13, - /** Applied Micro Circuits Corporation (APM). Vendor of ARM64 processor microarchitectures. */ - cpuinfo_vendor_apm = 14, + /** Applied Micro Circuits Corporation (APM). Vendor of ARM64 processor + microarchitectures. */ + cpuinfo_vendor_apm = 14, /** - * Huawei Technologies Co., Ltd. Vendor of ARM64 processor microarchitectures. + * Huawei Technologies Co., Ltd. Vendor of ARM64 processor + * microarchitectures. * * Processors are designed by HiSilicon, a subsidiary of Huawei. */ - cpuinfo_vendor_huawei = 15, + cpuinfo_vendor_huawei = 15, /** - * Hygon (Chengdu Haiguang Integrated Circuit Design Co., Ltd), Vendor of x86-64 processor microarchitectures. + * Hygon (Chengdu Haiguang Integrated Circuit Design Co., Ltd), Vendor + * of x86-64 processor microarchitectures. * * Processors are variants of AMD cores. */ - cpuinfo_vendor_hygon = 16, + cpuinfo_vendor_hygon = 16, /** SiFive, Inc. Vendor of RISC-V processor microarchitectures. */ - cpuinfo_vendor_sifive = 17, + cpuinfo_vendor_sifive = 17, /* Active vendors of embedded CPUs */ - /** Texas Instruments Inc. Vendor of ARM processor microarchitectures. */ + /** Texas Instruments Inc. Vendor of ARM processor microarchitectures. + */ cpuinfo_vendor_texas_instruments = 30, - /** Marvell Technology Group Ltd. Vendor of ARM processor microarchitectures. */ - cpuinfo_vendor_marvell = 31, - /** RDC Semiconductor Co., Ltd. Vendor of x86 processor microarchitectures. */ - cpuinfo_vendor_rdc = 32, + /** Marvell Technology Group Ltd. Vendor of ARM processor + * microarchitectures. + */ + cpuinfo_vendor_marvell = 31, + /** RDC Semiconductor Co., Ltd. Vendor of x86 processor + microarchitectures. */ + cpuinfo_vendor_rdc = 32, /** DM&P Electronics Inc. Vendor of x86 processor microarchitectures. */ - cpuinfo_vendor_dmp = 33, - /** Motorola, Inc. Vendor of PowerPC and ARM processor microarchitectures. */ - cpuinfo_vendor_motorola = 34, + cpuinfo_vendor_dmp = 33, + /** Motorola, Inc. Vendor of PowerPC and ARM processor + microarchitectures. */ + cpuinfo_vendor_motorola = 34, /* Defunct CPU vendors */ @@ -226,7 +249,8 @@ enum cpuinfo_vendor { * Transmeta Corporation. Vendor of x86 processor microarchitectures. * * Now defunct. The last processor design was released in 2004. - * Transmeta processors implemented VLIW ISA and used binary translation to execute x86 code. + * Transmeta processors implemented VLIW ISA and used binary translation + * to execute x86 code. */ cpuinfo_vendor_transmeta = 50, /** @@ -234,133 +258,144 @@ enum cpuinfo_vendor { * * Now defunct. The last processor design was released in 1996. */ - cpuinfo_vendor_cyrix = 51, + cpuinfo_vendor_cyrix = 51, /** * Rise Technology. Vendor of x86 processor microarchitectures. * * Now defunct. The last processor design was released in 1999. */ - cpuinfo_vendor_rise = 52, + cpuinfo_vendor_rise = 52, /** * National Semiconductor. Vendor of x86 processor microarchitectures. * - * Sold its x86 design subsidiary in 1999. The last processor design was released in 1998. + * Sold its x86 design subsidiary in 1999. The last processor design was + * released in 1998. */ - cpuinfo_vendor_nsc = 53, + cpuinfo_vendor_nsc = 53, /** - * Silicon Integrated Systems. Vendor of x86 processor microarchitectures. + * Silicon Integrated Systems. Vendor of x86 processor + * microarchitectures. * - * Sold its x86 design subsidiary in 2001. The last processor design was released in 2001. + * Sold its x86 design subsidiary in 2001. The last processor design was + * released in 2001. */ - cpuinfo_vendor_sis = 54, + cpuinfo_vendor_sis = 54, /** * NexGen. Vendor of x86 processor microarchitectures. * * Now defunct. The last processor design was released in 1994. - * NexGen designed the first x86 microarchitecture which decomposed x86 instructions into simple microoperations. + * NexGen designed the first x86 microarchitecture which decomposed x86 + * instructions into simple microoperations. */ - cpuinfo_vendor_nexgen = 55, + cpuinfo_vendor_nexgen = 55, /** - * United Microelectronics Corporation. Vendor of x86 processor microarchitectures. + * United Microelectronics Corporation. Vendor of x86 processor + * microarchitectures. * - * Ceased x86 in the early 1990s. The last processor design was released in 1991. - * Designed U5C and U5D processors. Both are 486 level. + * Ceased x86 in the early 1990s. The last processor design was released + * in 1991. Designed U5C and U5D processors. Both are 486 level. */ - cpuinfo_vendor_umc = 56, + cpuinfo_vendor_umc = 56, /** - * Digital Equipment Corporation. Vendor of ARM processor microarchitecture. + * Digital Equipment Corporation. Vendor of ARM processor + * microarchitecture. * - * Sold its ARM designs in 1997. The last processor design was released in 1997. + * Sold its ARM designs in 1997. The last processor design was released + * in 1997. */ - cpuinfo_vendor_dec = 57, + cpuinfo_vendor_dec = 57, }; /** * Processor microarchitecture * - * Processors with different microarchitectures often have different instruction performance characteristics, - * and may have dramatically different pipeline organization. + * Processors with different microarchitectures often have different instruction + * performance characteristics, and may have dramatically different pipeline + * organization. */ enum cpuinfo_uarch { - /** Microarchitecture is unknown, or the library failed to get information about the microarchitecture from OS */ + /** Microarchitecture is unknown, or the library failed to get + information about the microarchitecture from OS */ cpuinfo_uarch_unknown = 0, /** Pentium and Pentium MMX microarchitecture. */ - cpuinfo_uarch_p5 = 0x00100100, + cpuinfo_uarch_p5 = 0x00100100, /** Intel Quark microarchitecture. */ cpuinfo_uarch_quark = 0x00100101, /** Pentium Pro, Pentium II, and Pentium III. */ - cpuinfo_uarch_p6 = 0x00100200, + cpuinfo_uarch_p6 = 0x00100200, /** Pentium M. */ - cpuinfo_uarch_dothan = 0x00100201, + cpuinfo_uarch_dothan = 0x00100201, /** Intel Core microarchitecture. */ - cpuinfo_uarch_yonah = 0x00100202, + cpuinfo_uarch_yonah = 0x00100202, /** Intel Core 2 microarchitecture on 65 nm process. */ - cpuinfo_uarch_conroe = 0x00100203, + cpuinfo_uarch_conroe = 0x00100203, /** Intel Core 2 microarchitecture on 45 nm process. */ - cpuinfo_uarch_penryn = 0x00100204, - /** Intel Nehalem and Westmere microarchitectures (Core i3/i5/i7 1st gen). */ - cpuinfo_uarch_nehalem = 0x00100205, + cpuinfo_uarch_penryn = 0x00100204, + /** Intel Nehalem and Westmere microarchitectures (Core i3/i5/i7 1st + gen). */ + cpuinfo_uarch_nehalem = 0x00100205, /** Intel Sandy Bridge microarchitecture (Core i3/i5/i7 2nd gen). */ cpuinfo_uarch_sandy_bridge = 0x00100206, /** Intel Ivy Bridge microarchitecture (Core i3/i5/i7 3rd gen). */ - cpuinfo_uarch_ivy_bridge = 0x00100207, + cpuinfo_uarch_ivy_bridge = 0x00100207, /** Intel Haswell microarchitecture (Core i3/i5/i7 4th gen). */ - cpuinfo_uarch_haswell = 0x00100208, + cpuinfo_uarch_haswell = 0x00100208, /** Intel Broadwell microarchitecture. */ - cpuinfo_uarch_broadwell = 0x00100209, - /** Intel Sky Lake microarchitecture (14 nm, including Kaby/Coffee/Whiskey/Amber/Comet/Cascade/Cooper Lake). */ - cpuinfo_uarch_sky_lake = 0x0010020A, + cpuinfo_uarch_broadwell = 0x00100209, + /** Intel Sky Lake microarchitecture (14 nm, including + Kaby/Coffee/Whiskey/Amber/Comet/Cascade/Cooper Lake). */ + cpuinfo_uarch_sky_lake = 0x0010020A, /** DEPRECATED (Intel Kaby Lake microarchitecture). */ - cpuinfo_uarch_kaby_lake = 0x0010020A, + cpuinfo_uarch_kaby_lake = 0x0010020A, /** Intel Palm Cove microarchitecture (10 nm, Cannon Lake). */ - cpuinfo_uarch_palm_cove = 0x0010020B, + cpuinfo_uarch_palm_cove = 0x0010020B, /** Intel Sunny Cove microarchitecture (10 nm, Ice Lake). */ - cpuinfo_uarch_sunny_cove = 0x0010020C, + cpuinfo_uarch_sunny_cove = 0x0010020C, /** Pentium 4 with Willamette, Northwood, or Foster cores. */ cpuinfo_uarch_willamette = 0x00100300, /** Pentium 4 with Prescott and later cores. */ - cpuinfo_uarch_prescott = 0x00100301, + cpuinfo_uarch_prescott = 0x00100301, /** Intel Atom on 45 nm process. */ - cpuinfo_uarch_bonnell = 0x00100400, + cpuinfo_uarch_bonnell = 0x00100400, /** Intel Atom on 32 nm process. */ - cpuinfo_uarch_saltwell = 0x00100401, + cpuinfo_uarch_saltwell = 0x00100401, /** Intel Silvermont microarchitecture (22 nm out-of-order Atom). */ - cpuinfo_uarch_silvermont = 0x00100402, + cpuinfo_uarch_silvermont = 0x00100402, /** Intel Airmont microarchitecture (14 nm out-of-order Atom). */ - cpuinfo_uarch_airmont = 0x00100403, + cpuinfo_uarch_airmont = 0x00100403, /** Intel Goldmont microarchitecture (Denverton, Apollo Lake). */ - cpuinfo_uarch_goldmont = 0x00100404, + cpuinfo_uarch_goldmont = 0x00100404, /** Intel Goldmont Plus microarchitecture (Gemini Lake). */ cpuinfo_uarch_goldmont_plus = 0x00100405, /** Intel Knights Ferry HPC boards. */ - cpuinfo_uarch_knights_ferry = 0x00100500, + cpuinfo_uarch_knights_ferry = 0x00100500, /** Intel Knights Corner HPC boards (aka Xeon Phi). */ - cpuinfo_uarch_knights_corner = 0x00100501, + cpuinfo_uarch_knights_corner = 0x00100501, /** Intel Knights Landing microarchitecture (second-gen MIC). */ cpuinfo_uarch_knights_landing = 0x00100502, /** Intel Knights Hill microarchitecture (third-gen MIC). */ - cpuinfo_uarch_knights_hill = 0x00100503, + cpuinfo_uarch_knights_hill = 0x00100503, /** Intel Knights Mill Xeon Phi. */ - cpuinfo_uarch_knights_mill = 0x00100504, + cpuinfo_uarch_knights_mill = 0x00100504, /** Intel/Marvell XScale series. */ cpuinfo_uarch_xscale = 0x00100600, /** AMD K5. */ - cpuinfo_uarch_k5 = 0x00200100, + cpuinfo_uarch_k5 = 0x00200100, /** AMD K6 and alike. */ - cpuinfo_uarch_k6 = 0x00200101, + cpuinfo_uarch_k6 = 0x00200101, /** AMD Athlon and Duron. */ - cpuinfo_uarch_k7 = 0x00200102, + cpuinfo_uarch_k7 = 0x00200102, /** AMD Athlon 64, Opteron 64. */ - cpuinfo_uarch_k8 = 0x00200103, + cpuinfo_uarch_k8 = 0x00200103, /** AMD Family 10h (Barcelona, Istambul, Magny-Cours). */ - cpuinfo_uarch_k10 = 0x00200104, + cpuinfo_uarch_k10 = 0x00200104, /** * AMD Bulldozer microarchitecture * Zambezi FX-series CPUs, Zurich, Valencia and Interlagos Opteron CPUs. @@ -368,46 +403,47 @@ enum cpuinfo_uarch { cpuinfo_uarch_bulldozer = 0x00200105, /** * AMD Piledriver microarchitecture - * Vishera FX-series CPUs, Trinity and Richland APUs, Delhi, Seoul, Abu Dhabi Opteron CPUs. + * Vishera FX-series CPUs, Trinity and Richland APUs, Delhi, Seoul, Abu + * Dhabi Opteron CPUs. */ - cpuinfo_uarch_piledriver = 0x00200106, + cpuinfo_uarch_piledriver = 0x00200106, /** AMD Steamroller microarchitecture (Kaveri APUs). */ cpuinfo_uarch_steamroller = 0x00200107, /** AMD Excavator microarchitecture (Carizzo APUs). */ - cpuinfo_uarch_excavator = 0x00200108, + cpuinfo_uarch_excavator = 0x00200108, /** AMD Zen microarchitecture (12/14 nm Ryzen and EPYC CPUs). */ - cpuinfo_uarch_zen = 0x00200109, + cpuinfo_uarch_zen = 0x00200109, /** AMD Zen 2 microarchitecture (7 nm Ryzen and EPYC CPUs). */ - cpuinfo_uarch_zen2 = 0x0020010A, + cpuinfo_uarch_zen2 = 0x0020010A, /** AMD Zen 3 microarchitecture. */ - cpuinfo_uarch_zen3 = 0x0020010B, + cpuinfo_uarch_zen3 = 0x0020010B, /** AMD Zen 4 microarchitecture. */ - cpuinfo_uarch_zen4 = 0x0020010C, + cpuinfo_uarch_zen4 = 0x0020010C, /** NSC Geode and AMD Geode GX and LX. */ - cpuinfo_uarch_geode = 0x00200200, + cpuinfo_uarch_geode = 0x00200200, /** AMD Bobcat mobile microarchitecture. */ cpuinfo_uarch_bobcat = 0x00200201, /** AMD Jaguar mobile microarchitecture. */ cpuinfo_uarch_jaguar = 0x00200202, /** AMD Puma mobile microarchitecture. */ - cpuinfo_uarch_puma = 0x00200203, + cpuinfo_uarch_puma = 0x00200203, /** ARM7 series. */ - cpuinfo_uarch_arm7 = 0x00300100, + cpuinfo_uarch_arm7 = 0x00300100, /** ARM9 series. */ - cpuinfo_uarch_arm9 = 0x00300101, + cpuinfo_uarch_arm9 = 0x00300101, /** ARM 1136, ARM 1156, ARM 1176, or ARM 11MPCore. */ cpuinfo_uarch_arm11 = 0x00300102, /** ARM Cortex-A5. */ - cpuinfo_uarch_cortex_a5 = 0x00300205, + cpuinfo_uarch_cortex_a5 = 0x00300205, /** ARM Cortex-A7. */ - cpuinfo_uarch_cortex_a7 = 0x00300207, + cpuinfo_uarch_cortex_a7 = 0x00300207, /** ARM Cortex-A8. */ - cpuinfo_uarch_cortex_a8 = 0x00300208, + cpuinfo_uarch_cortex_a8 = 0x00300208, /** ARM Cortex-A9. */ - cpuinfo_uarch_cortex_a9 = 0x00300209, + cpuinfo_uarch_cortex_a9 = 0x00300209, /** ARM Cortex-A12. */ cpuinfo_uarch_cortex_a12 = 0x00300212, /** ARM Cortex-A15. */ @@ -416,124 +452,125 @@ enum cpuinfo_uarch { cpuinfo_uarch_cortex_a17 = 0x00300217, /** ARM Cortex-A32. */ - cpuinfo_uarch_cortex_a32 = 0x00300332, + cpuinfo_uarch_cortex_a32 = 0x00300332, /** ARM Cortex-A35. */ - cpuinfo_uarch_cortex_a35 = 0x00300335, + cpuinfo_uarch_cortex_a35 = 0x00300335, /** ARM Cortex-A53. */ - cpuinfo_uarch_cortex_a53 = 0x00300353, - /** ARM Cortex-A55 revision 0 (restricted dual-issue capabilities compared to revision 1+). */ + cpuinfo_uarch_cortex_a53 = 0x00300353, + /** ARM Cortex-A55 revision 0 (restricted dual-issue capabilities + compared to revision 1+). */ cpuinfo_uarch_cortex_a55r0 = 0x00300354, /** ARM Cortex-A55. */ - cpuinfo_uarch_cortex_a55 = 0x00300355, + cpuinfo_uarch_cortex_a55 = 0x00300355, /** ARM Cortex-A57. */ - cpuinfo_uarch_cortex_a57 = 0x00300357, + cpuinfo_uarch_cortex_a57 = 0x00300357, /** ARM Cortex-A65. */ - cpuinfo_uarch_cortex_a65 = 0x00300365, + cpuinfo_uarch_cortex_a65 = 0x00300365, /** ARM Cortex-A72. */ - cpuinfo_uarch_cortex_a72 = 0x00300372, + cpuinfo_uarch_cortex_a72 = 0x00300372, /** ARM Cortex-A73. */ - cpuinfo_uarch_cortex_a73 = 0x00300373, + cpuinfo_uarch_cortex_a73 = 0x00300373, /** ARM Cortex-A75. */ - cpuinfo_uarch_cortex_a75 = 0x00300375, + cpuinfo_uarch_cortex_a75 = 0x00300375, /** ARM Cortex-A76. */ - cpuinfo_uarch_cortex_a76 = 0x00300376, + cpuinfo_uarch_cortex_a76 = 0x00300376, /** ARM Cortex-A77. */ - cpuinfo_uarch_cortex_a77 = 0x00300377, + cpuinfo_uarch_cortex_a77 = 0x00300377, /** ARM Cortex-A78. */ - cpuinfo_uarch_cortex_a78 = 0x00300378, + cpuinfo_uarch_cortex_a78 = 0x00300378, /** ARM Neoverse N1. */ - cpuinfo_uarch_neoverse_n1 = 0x00300400, + cpuinfo_uarch_neoverse_n1 = 0x00300400, /** ARM Neoverse E1. */ - cpuinfo_uarch_neoverse_e1 = 0x00300401, + cpuinfo_uarch_neoverse_e1 = 0x00300401, /** ARM Neoverse V1. */ - cpuinfo_uarch_neoverse_v1 = 0x00300402, + cpuinfo_uarch_neoverse_v1 = 0x00300402, /** ARM Neoverse N2. */ - cpuinfo_uarch_neoverse_n2 = 0x00300403, + cpuinfo_uarch_neoverse_n2 = 0x00300403, /** ARM Neoverse V2. */ - cpuinfo_uarch_neoverse_v2 = 0x00300404, + cpuinfo_uarch_neoverse_v2 = 0x00300404, /** ARM Cortex-X1. */ - cpuinfo_uarch_cortex_x1 = 0x00300501, + cpuinfo_uarch_cortex_x1 = 0x00300501, /** ARM Cortex-X2. */ - cpuinfo_uarch_cortex_x2 = 0x00300502, + cpuinfo_uarch_cortex_x2 = 0x00300502, /** ARM Cortex-X3. */ - cpuinfo_uarch_cortex_x3 = 0x00300503, + cpuinfo_uarch_cortex_x3 = 0x00300503, /** ARM Cortex-A510. */ - cpuinfo_uarch_cortex_a510 = 0x00300551, + cpuinfo_uarch_cortex_a510 = 0x00300551, /** ARM Cortex-A710. */ - cpuinfo_uarch_cortex_a710 = 0x00300571, + cpuinfo_uarch_cortex_a710 = 0x00300571, /** ARM Cortex-A715. */ - cpuinfo_uarch_cortex_a715 = 0x00300572, + cpuinfo_uarch_cortex_a715 = 0x00300572, /** Qualcomm Scorpion. */ cpuinfo_uarch_scorpion = 0x00400100, /** Qualcomm Krait. */ - cpuinfo_uarch_krait = 0x00400101, + cpuinfo_uarch_krait = 0x00400101, /** Qualcomm Kryo. */ - cpuinfo_uarch_kryo = 0x00400102, + cpuinfo_uarch_kryo = 0x00400102, /** Qualcomm Falkor. */ - cpuinfo_uarch_falkor = 0x00400103, + cpuinfo_uarch_falkor = 0x00400103, /** Qualcomm Saphira. */ - cpuinfo_uarch_saphira = 0x00400104, + cpuinfo_uarch_saphira = 0x00400104, /** Nvidia Denver. */ - cpuinfo_uarch_denver = 0x00500100, + cpuinfo_uarch_denver = 0x00500100, /** Nvidia Denver 2. */ - cpuinfo_uarch_denver2 = 0x00500101, + cpuinfo_uarch_denver2 = 0x00500101, /** Nvidia Carmel. */ - cpuinfo_uarch_carmel = 0x00500102, + cpuinfo_uarch_carmel = 0x00500102, /** Samsung Exynos M1 (Exynos 8890 big cores). */ cpuinfo_uarch_exynos_m1 = 0x00600100, /** Samsung Exynos M2 (Exynos 8895 big cores). */ cpuinfo_uarch_exynos_m2 = 0x00600101, /** Samsung Exynos M3 (Exynos 9810 big cores). */ - cpuinfo_uarch_exynos_m3 = 0x00600102, + cpuinfo_uarch_exynos_m3 = 0x00600102, /** Samsung Exynos M4 (Exynos 9820 big cores). */ - cpuinfo_uarch_exynos_m4 = 0x00600103, + cpuinfo_uarch_exynos_m4 = 0x00600103, /** Samsung Exynos M5 (Exynos 9830 big cores). */ - cpuinfo_uarch_exynos_m5 = 0x00600104, + cpuinfo_uarch_exynos_m5 = 0x00600104, /* Deprecated synonym for Cortex-A76 */ cpuinfo_uarch_cortex_a76ae = 0x00300376, /* Deprecated names for Exynos. */ cpuinfo_uarch_mongoose_m1 = 0x00600100, cpuinfo_uarch_mongoose_m2 = 0x00600101, - cpuinfo_uarch_meerkat_m3 = 0x00600102, - cpuinfo_uarch_meerkat_m4 = 0x00600103, + cpuinfo_uarch_meerkat_m3 = 0x00600102, + cpuinfo_uarch_meerkat_m4 = 0x00600103, /** Apple A6 and A6X processors. */ - cpuinfo_uarch_swift = 0x00700100, + cpuinfo_uarch_swift = 0x00700100, /** Apple A7 processor. */ - cpuinfo_uarch_cyclone = 0x00700101, + cpuinfo_uarch_cyclone = 0x00700101, /** Apple A8 and A8X processor. */ - cpuinfo_uarch_typhoon = 0x00700102, + cpuinfo_uarch_typhoon = 0x00700102, /** Apple A9 and A9X processor. */ - cpuinfo_uarch_twister = 0x00700103, + cpuinfo_uarch_twister = 0x00700103, /** Apple A10 and A10X processor. */ cpuinfo_uarch_hurricane = 0x00700104, /** Apple A11 processor (big cores). */ - cpuinfo_uarch_monsoon = 0x00700105, + cpuinfo_uarch_monsoon = 0x00700105, /** Apple A11 processor (little cores). */ - cpuinfo_uarch_mistral = 0x00700106, + cpuinfo_uarch_mistral = 0x00700106, /** Apple A12 processor (big cores). */ - cpuinfo_uarch_vortex = 0x00700107, + cpuinfo_uarch_vortex = 0x00700107, /** Apple A12 processor (little cores). */ - cpuinfo_uarch_tempest = 0x00700108, + cpuinfo_uarch_tempest = 0x00700108, /** Apple A13 processor (big cores). */ cpuinfo_uarch_lightning = 0x00700109, /** Apple A13 processor (little cores). */ - cpuinfo_uarch_thunder = 0x0070010A, + cpuinfo_uarch_thunder = 0x0070010A, /** Apple A14 / M1 processor (big cores). */ cpuinfo_uarch_firestorm = 0x0070010B, /** Apple A14 / M1 processor (little cores). */ - cpuinfo_uarch_icestorm = 0x0070010C, + cpuinfo_uarch_icestorm = 0x0070010C, /** Apple A15 / M2 processor (big cores). */ cpuinfo_uarch_avalanche = 0x0070010D, /** Apple A15 / M2 processor (little cores). */ - cpuinfo_uarch_blizzard = 0x0070010E, + cpuinfo_uarch_blizzard = 0x0070010E, /** Cavium ThunderX. */ cpuinfo_uarch_thunderx = 0x00800100, @@ -570,17 +607,20 @@ struct cpuinfo_processor { #if defined(__linux__) /** * Linux-specific ID for the logical processor: - * - Linux kernel exposes information about this logical processor in /sys/devices/system/cpu/cpu/ + * - Linux kernel exposes information about this logical processor in + * /sys/devices/system/cpu/cpu/ * - Bit in the cpu_set_t identifies this logical processor */ int linux_id; #endif #if defined(_WIN32) || defined(__CYGWIN__) - /** Windows-specific ID for the group containing the logical processor. */ + /** Windows-specific ID for the group containing the logical processor. + */ uint16_t windows_group_id; /** * Windows-specific ID of the logical processor within its group: - * - Bit in the KAFFINITY mask identifies this logical processor within its group. + * - Bit in the KAFFINITY mask identifies this + * logical processor within its group. */ uint16_t windows_processor_id; #endif @@ -700,1302 +740,1302 @@ bool CPUINFO_ABI cpuinfo_initialize(void); void CPUINFO_ABI cpuinfo_deinitialize(void); #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - /* This structure is not a part of stable API. Use cpuinfo_has_x86_* functions instead. */ - struct cpuinfo_x86_isa { - #if CPUINFO_ARCH_X86 - bool rdtsc; - #endif - bool rdtscp; - bool rdpid; - bool sysenter; - #if CPUINFO_ARCH_X86 - bool syscall; - #endif - bool msr; - bool clzero; - bool clflush; - bool clflushopt; - bool mwait; - bool mwaitx; - #if CPUINFO_ARCH_X86 - bool emmx; - #endif - bool fxsave; - bool xsave; - #if CPUINFO_ARCH_X86 - bool fpu; - bool mmx; - bool mmx_plus; - #endif - bool three_d_now; - bool three_d_now_plus; - #if CPUINFO_ARCH_X86 - bool three_d_now_geode; - #endif - bool prefetch; - bool prefetchw; - bool prefetchwt1; - #if CPUINFO_ARCH_X86 - bool daz; - bool sse; - bool sse2; - #endif - bool sse3; - bool ssse3; - bool sse4_1; - bool sse4_2; - bool sse4a; - bool misaligned_sse; - bool avx; - bool avxvnni; - bool fma3; - bool fma4; - bool xop; - bool f16c; - bool avx2; - bool avx512f; - bool avx512pf; - bool avx512er; - bool avx512cd; - bool avx512dq; - bool avx512bw; - bool avx512vl; - bool avx512ifma; - bool avx512vbmi; - bool avx512vbmi2; - bool avx512bitalg; - bool avx512vpopcntdq; - bool avx512vnni; - bool avx512bf16; - bool avx512fp16; - bool avx512vp2intersect; - bool avx512_4vnniw; - bool avx512_4fmaps; - bool hle; - bool rtm; - bool xtest; - bool mpx; - #if CPUINFO_ARCH_X86 - bool cmov; - bool cmpxchg8b; - #endif - bool cmpxchg16b; - bool clwb; - bool movbe; - #if CPUINFO_ARCH_X86_64 - bool lahf_sahf; - #endif - bool fs_gs_base; - bool lzcnt; - bool popcnt; - bool tbm; - bool bmi; - bool bmi2; - bool adx; - bool aes; - bool vaes; - bool pclmulqdq; - bool vpclmulqdq; - bool gfni; - bool rdrand; - bool rdseed; - bool sha; - bool rng; - bool ace; - bool ace2; - bool phe; - bool pmm; - bool lwp; - }; - - extern struct cpuinfo_x86_isa cpuinfo_isa; +/* This structure is not a part of stable API. Use cpuinfo_has_x86_* functions + * instead. */ +struct cpuinfo_x86_isa { +#if CPUINFO_ARCH_X86 + bool rdtsc; +#endif + bool rdtscp; + bool rdpid; + bool sysenter; +#if CPUINFO_ARCH_X86 + bool syscall; +#endif + bool msr; + bool clzero; + bool clflush; + bool clflushopt; + bool mwait; + bool mwaitx; +#if CPUINFO_ARCH_X86 + bool emmx; +#endif + bool fxsave; + bool xsave; +#if CPUINFO_ARCH_X86 + bool fpu; + bool mmx; + bool mmx_plus; +#endif + bool three_d_now; + bool three_d_now_plus; +#if CPUINFO_ARCH_X86 + bool three_d_now_geode; +#endif + bool prefetch; + bool prefetchw; + bool prefetchwt1; +#if CPUINFO_ARCH_X86 + bool daz; + bool sse; + bool sse2; +#endif + bool sse3; + bool ssse3; + bool sse4_1; + bool sse4_2; + bool sse4a; + bool misaligned_sse; + bool avx; + bool avxvnni; + bool fma3; + bool fma4; + bool xop; + bool f16c; + bool avx2; + bool avx512f; + bool avx512pf; + bool avx512er; + bool avx512cd; + bool avx512dq; + bool avx512bw; + bool avx512vl; + bool avx512ifma; + bool avx512vbmi; + bool avx512vbmi2; + bool avx512bitalg; + bool avx512vpopcntdq; + bool avx512vnni; + bool avx512bf16; + bool avx512fp16; + bool avx512vp2intersect; + bool avx512_4vnniw; + bool avx512_4fmaps; + bool hle; + bool rtm; + bool xtest; + bool mpx; +#if CPUINFO_ARCH_X86 + bool cmov; + bool cmpxchg8b; +#endif + bool cmpxchg16b; + bool clwb; + bool movbe; +#if CPUINFO_ARCH_X86_64 + bool lahf_sahf; +#endif + bool fs_gs_base; + bool lzcnt; + bool popcnt; + bool tbm; + bool bmi; + bool bmi2; + bool adx; + bool aes; + bool vaes; + bool pclmulqdq; + bool vpclmulqdq; + bool gfni; + bool rdrand; + bool rdseed; + bool sha; + bool rng; + bool ace; + bool ace2; + bool phe; + bool pmm; + bool lwp; +}; + +extern struct cpuinfo_x86_isa cpuinfo_isa; #endif static inline bool cpuinfo_has_x86_rdtsc(void) { - #if CPUINFO_ARCH_X86_64 - return true; - #elif CPUINFO_ARCH_X86 - #if defined(__ANDROID__) - return true; - #else - return cpuinfo_isa.rdtsc; - #endif - #else - return false; - #endif +#if CPUINFO_ARCH_X86_64 + return true; +#elif CPUINFO_ARCH_X86 +#if defined(__ANDROID__) + return true; +#else + return cpuinfo_isa.rdtsc; +#endif +#else + return false; +#endif } static inline bool cpuinfo_has_x86_rdtscp(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.rdtscp; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.rdtscp; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_rdpid(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.rdpid; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.rdpid; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_clzero(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.clzero; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.clzero; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_mwait(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.mwait; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.mwait; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_mwaitx(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.mwaitx; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.mwaitx; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_fxsave(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.fxsave; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.fxsave; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_xsave(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.xsave; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.xsave; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_fpu(void) { - #if CPUINFO_ARCH_X86_64 - return true; - #elif CPUINFO_ARCH_X86 - #if defined(__ANDROID__) - return true; - #else - return cpuinfo_isa.fpu; - #endif - #else - return false; - #endif +#if CPUINFO_ARCH_X86_64 + return true; +#elif CPUINFO_ARCH_X86 +#if defined(__ANDROID__) + return true; +#else + return cpuinfo_isa.fpu; +#endif +#else + return false; +#endif } static inline bool cpuinfo_has_x86_mmx(void) { - #if CPUINFO_ARCH_X86_64 - return true; - #elif CPUINFO_ARCH_X86 - #if defined(__ANDROID__) - return true; - #else - return cpuinfo_isa.mmx; - #endif - #else - return false; - #endif +#if CPUINFO_ARCH_X86_64 + return true; +#elif CPUINFO_ARCH_X86 +#if defined(__ANDROID__) + return true; +#else + return cpuinfo_isa.mmx; +#endif +#else + return false; +#endif } static inline bool cpuinfo_has_x86_mmx_plus(void) { - #if CPUINFO_ARCH_X86_64 - return true; - #elif CPUINFO_ARCH_X86 - #if defined(__ANDROID__) - return true; - #else - return cpuinfo_isa.mmx_plus; - #endif - #else - return false; - #endif +#if CPUINFO_ARCH_X86_64 + return true; +#elif CPUINFO_ARCH_X86 +#if defined(__ANDROID__) + return true; +#else + return cpuinfo_isa.mmx_plus; +#endif +#else + return false; +#endif } static inline bool cpuinfo_has_x86_3dnow(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.three_d_now; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.three_d_now; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_3dnow_plus(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.three_d_now_plus; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.three_d_now_plus; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_3dnow_geode(void) { - #if CPUINFO_ARCH_X86_64 - return false; - #elif CPUINFO_ARCH_X86 - #if defined(__ANDROID__) - return false; - #else - return cpuinfo_isa.three_d_now_geode; - #endif - #else - return false; - #endif +#if CPUINFO_ARCH_X86_64 + return false; +#elif CPUINFO_ARCH_X86 +#if defined(__ANDROID__) + return false; +#else + return cpuinfo_isa.three_d_now_geode; +#endif +#else + return false; +#endif } static inline bool cpuinfo_has_x86_prefetch(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.prefetch; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.prefetch; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_prefetchw(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.prefetchw; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.prefetchw; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_prefetchwt1(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.prefetchwt1; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.prefetchwt1; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_daz(void) { - #if CPUINFO_ARCH_X86_64 - return true; - #elif CPUINFO_ARCH_X86 - #if defined(__ANDROID__) - return true; - #else - return cpuinfo_isa.daz; - #endif - #else - return false; - #endif +#if CPUINFO_ARCH_X86_64 + return true; +#elif CPUINFO_ARCH_X86 +#if defined(__ANDROID__) + return true; +#else + return cpuinfo_isa.daz; +#endif +#else + return false; +#endif } static inline bool cpuinfo_has_x86_sse(void) { - #if CPUINFO_ARCH_X86_64 - return true; - #elif CPUINFO_ARCH_X86 - #if defined(__ANDROID__) - return true; - #else - return cpuinfo_isa.sse; - #endif - #else - return false; - #endif +#if CPUINFO_ARCH_X86_64 + return true; +#elif CPUINFO_ARCH_X86 +#if defined(__ANDROID__) + return true; +#else + return cpuinfo_isa.sse; +#endif +#else + return false; +#endif } static inline bool cpuinfo_has_x86_sse2(void) { - #if CPUINFO_ARCH_X86_64 - return true; - #elif CPUINFO_ARCH_X86 - #if defined(__ANDROID__) - return true; - #else - return cpuinfo_isa.sse2; - #endif - #else - return false; - #endif +#if CPUINFO_ARCH_X86_64 + return true; +#elif CPUINFO_ARCH_X86 +#if defined(__ANDROID__) + return true; +#else + return cpuinfo_isa.sse2; +#endif +#else + return false; +#endif } static inline bool cpuinfo_has_x86_sse3(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - #if defined(__ANDROID__) - return true; - #else - return cpuinfo_isa.sse3; - #endif - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 +#if defined(__ANDROID__) + return true; +#else + return cpuinfo_isa.sse3; +#endif +#else + return false; +#endif } static inline bool cpuinfo_has_x86_ssse3(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - #if defined(__ANDROID__) - return true; - #else - return cpuinfo_isa.ssse3; - #endif - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 +#if defined(__ANDROID__) + return true; +#else + return cpuinfo_isa.ssse3; +#endif +#else + return false; +#endif } static inline bool cpuinfo_has_x86_sse4_1(void) { - #if CPUINFO_ARCH_X86_64 - #if defined(__ANDROID__) - return true; - #else - return cpuinfo_isa.sse4_1; - #endif - #elif CPUINFO_ARCH_X86 - return cpuinfo_isa.sse4_1; - #else - return false; - #endif +#if CPUINFO_ARCH_X86_64 +#if defined(__ANDROID__) + return true; +#else + return cpuinfo_isa.sse4_1; +#endif +#elif CPUINFO_ARCH_X86 + return cpuinfo_isa.sse4_1; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_sse4_2(void) { - #if CPUINFO_ARCH_X86_64 - #if defined(__ANDROID__) - return true; - #else - return cpuinfo_isa.sse4_2; - #endif - #elif CPUINFO_ARCH_X86 - return cpuinfo_isa.sse4_2; - #else - return false; - #endif +#if CPUINFO_ARCH_X86_64 +#if defined(__ANDROID__) + return true; +#else + return cpuinfo_isa.sse4_2; +#endif +#elif CPUINFO_ARCH_X86 + return cpuinfo_isa.sse4_2; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_sse4a(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.sse4a; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.sse4a; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_misaligned_sse(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.misaligned_sse; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.misaligned_sse; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avxvnni(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avxvnni; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avxvnni; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_fma3(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.fma3; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.fma3; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_fma4(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.fma4; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.fma4; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_xop(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.xop; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.xop; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_f16c(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.f16c; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.f16c; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx2(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx2; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx2; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx512f(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx512f; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx512f; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx512pf(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx512pf; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx512pf; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx512er(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx512er; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx512er; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx512cd(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx512cd; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx512cd; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx512dq(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx512dq; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx512dq; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx512bw(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx512bw; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx512bw; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx512vl(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx512vl; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx512vl; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx512ifma(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx512ifma; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx512ifma; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx512vbmi(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx512vbmi; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx512vbmi; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx512vbmi2(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx512vbmi2; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx512vbmi2; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx512bitalg(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx512bitalg; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx512bitalg; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx512vpopcntdq(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx512vpopcntdq; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx512vpopcntdq; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx512vnni(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx512vnni; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx512vnni; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx512bf16(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx512bf16; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx512bf16; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx512fp16(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx512fp16; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx512fp16; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx512vp2intersect(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx512vp2intersect; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx512vp2intersect; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx512_4vnniw(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx512_4vnniw; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx512_4vnniw; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_avx512_4fmaps(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.avx512_4fmaps; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx512_4fmaps; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_hle(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.hle; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.hle; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_rtm(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.rtm; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.rtm; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_xtest(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.xtest; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.xtest; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_mpx(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.mpx; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.mpx; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_cmov(void) { - #if CPUINFO_ARCH_X86_64 - return true; - #elif CPUINFO_ARCH_X86 - return cpuinfo_isa.cmov; - #else - return false; - #endif +#if CPUINFO_ARCH_X86_64 + return true; +#elif CPUINFO_ARCH_X86 + return cpuinfo_isa.cmov; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_cmpxchg8b(void) { - #if CPUINFO_ARCH_X86_64 - return true; - #elif CPUINFO_ARCH_X86 - return cpuinfo_isa.cmpxchg8b; - #else - return false; - #endif +#if CPUINFO_ARCH_X86_64 + return true; +#elif CPUINFO_ARCH_X86 + return cpuinfo_isa.cmpxchg8b; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_cmpxchg16b(void) { - #if CPUINFO_ARCH_X86_64 - return cpuinfo_isa.cmpxchg16b; - #else - return false; - #endif +#if CPUINFO_ARCH_X86_64 + return cpuinfo_isa.cmpxchg16b; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_clwb(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.clwb; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.clwb; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_movbe(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.movbe; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.movbe; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_lahf_sahf(void) { - #if CPUINFO_ARCH_X86 - return true; - #elif CPUINFO_ARCH_X86_64 - return cpuinfo_isa.lahf_sahf; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 + return true; +#elif CPUINFO_ARCH_X86_64 + return cpuinfo_isa.lahf_sahf; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_lzcnt(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.lzcnt; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.lzcnt; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_popcnt(void) { - #if CPUINFO_ARCH_X86_64 - #if defined(__ANDROID__) - return true; - #else - return cpuinfo_isa.popcnt; - #endif - #elif CPUINFO_ARCH_X86 - return cpuinfo_isa.popcnt; - #else - return false; - #endif +#if CPUINFO_ARCH_X86_64 +#if defined(__ANDROID__) + return true; +#else + return cpuinfo_isa.popcnt; +#endif +#elif CPUINFO_ARCH_X86 + return cpuinfo_isa.popcnt; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_tbm(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.tbm; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.tbm; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_bmi(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.bmi; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.bmi; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_bmi2(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.bmi2; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.bmi2; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_adx(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.adx; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.adx; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_aes(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.aes; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.aes; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_vaes(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.vaes; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.vaes; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_pclmulqdq(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.pclmulqdq; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.pclmulqdq; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_vpclmulqdq(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.vpclmulqdq; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.vpclmulqdq; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_gfni(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.gfni; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.gfni; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_rdrand(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.rdrand; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.rdrand; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_rdseed(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.rdseed; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.rdseed; +#else + return false; +#endif } static inline bool cpuinfo_has_x86_sha(void) { - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - return cpuinfo_isa.sha; - #else - return false; - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.sha; +#else + return false; +#endif } #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 - /* This structure is not a part of stable API. Use cpuinfo_has_arm_* functions instead. */ - struct cpuinfo_arm_isa { - #if CPUINFO_ARCH_ARM - bool thumb; - bool thumb2; - bool thumbee; - bool jazelle; - bool armv5e; - bool armv6; - bool armv6k; - bool armv7; - bool armv7mp; - bool armv8; - bool idiv; - - bool vfpv2; - bool vfpv3; - bool d32; - bool fp16; - bool fma; - - bool wmmx; - bool wmmx2; - bool neon; - #endif - #if CPUINFO_ARCH_ARM64 - bool atomics; - bool bf16; - bool sve; - bool sve2; - bool i8mm; - #endif - bool rdm; - bool fp16arith; - bool dot; - bool jscvt; - bool fcma; - bool fhm; - - bool aes; - bool sha1; - bool sha2; - bool pmull; - bool crc32; - }; - - extern struct cpuinfo_arm_isa cpuinfo_isa; +/* This structure is not a part of stable API. Use cpuinfo_has_arm_* functions + * instead. */ +struct cpuinfo_arm_isa { +#if CPUINFO_ARCH_ARM + bool thumb; + bool thumb2; + bool thumbee; + bool jazelle; + bool armv5e; + bool armv6; + bool armv6k; + bool armv7; + bool armv7mp; + bool armv8; + bool idiv; + + bool vfpv2; + bool vfpv3; + bool d32; + bool fp16; + bool fma; + + bool wmmx; + bool wmmx2; + bool neon; +#endif +#if CPUINFO_ARCH_ARM64 + bool atomics; + bool bf16; + bool sve; + bool sve2; + bool i8mm; +#endif + bool rdm; + bool fp16arith; + bool dot; + bool jscvt; + bool fcma; + bool fhm; + + bool aes; + bool sha1; + bool sha2; + bool pmull; + bool crc32; +}; + +extern struct cpuinfo_arm_isa cpuinfo_isa; #endif static inline bool cpuinfo_has_arm_thumb(void) { - #if CPUINFO_ARCH_ARM - return cpuinfo_isa.thumb; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM + return cpuinfo_isa.thumb; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_thumb2(void) { - #if CPUINFO_ARCH_ARM - return cpuinfo_isa.thumb2; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM + return cpuinfo_isa.thumb2; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_v5e(void) { - #if CPUINFO_ARCH_ARM - return cpuinfo_isa.armv5e; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM + return cpuinfo_isa.armv5e; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_v6(void) { - #if CPUINFO_ARCH_ARM - return cpuinfo_isa.armv6; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM + return cpuinfo_isa.armv6; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_v6k(void) { - #if CPUINFO_ARCH_ARM - return cpuinfo_isa.armv6k; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM + return cpuinfo_isa.armv6k; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_v7(void) { - #if CPUINFO_ARCH_ARM - return cpuinfo_isa.armv7; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM + return cpuinfo_isa.armv7; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_v7mp(void) { - #if CPUINFO_ARCH_ARM - return cpuinfo_isa.armv7mp; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM + return cpuinfo_isa.armv7mp; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_v8(void) { - #if CPUINFO_ARCH_ARM64 - return true; - #elif CPUINFO_ARCH_ARM - return cpuinfo_isa.armv8; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return true; +#elif CPUINFO_ARCH_ARM + return cpuinfo_isa.armv8; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_idiv(void) { - #if CPUINFO_ARCH_ARM64 - return true; - #elif CPUINFO_ARCH_ARM - return cpuinfo_isa.idiv; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return true; +#elif CPUINFO_ARCH_ARM + return cpuinfo_isa.idiv; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_vfpv2(void) { - #if CPUINFO_ARCH_ARM - return cpuinfo_isa.vfpv2; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM + return cpuinfo_isa.vfpv2; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_vfpv3(void) { - #if CPUINFO_ARCH_ARM64 - return true; - #elif CPUINFO_ARCH_ARM - return cpuinfo_isa.vfpv3; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return true; +#elif CPUINFO_ARCH_ARM + return cpuinfo_isa.vfpv3; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_vfpv3_d32(void) { - #if CPUINFO_ARCH_ARM64 - return true; - #elif CPUINFO_ARCH_ARM - return cpuinfo_isa.vfpv3 && cpuinfo_isa.d32; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return true; +#elif CPUINFO_ARCH_ARM + return cpuinfo_isa.vfpv3 && cpuinfo_isa.d32; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_vfpv3_fp16(void) { - #if CPUINFO_ARCH_ARM64 - return true; - #elif CPUINFO_ARCH_ARM - return cpuinfo_isa.vfpv3 && cpuinfo_isa.fp16; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return true; +#elif CPUINFO_ARCH_ARM + return cpuinfo_isa.vfpv3 && cpuinfo_isa.fp16; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_vfpv3_fp16_d32(void) { - #if CPUINFO_ARCH_ARM64 - return true; - #elif CPUINFO_ARCH_ARM - return cpuinfo_isa.vfpv3 && cpuinfo_isa.fp16 && cpuinfo_isa.d32; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return true; +#elif CPUINFO_ARCH_ARM + return cpuinfo_isa.vfpv3 && cpuinfo_isa.fp16 && cpuinfo_isa.d32; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_vfpv4(void) { - #if CPUINFO_ARCH_ARM64 - return true; - #elif CPUINFO_ARCH_ARM - return cpuinfo_isa.vfpv3 && cpuinfo_isa.fma; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return true; +#elif CPUINFO_ARCH_ARM + return cpuinfo_isa.vfpv3 && cpuinfo_isa.fma; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_vfpv4_d32(void) { - #if CPUINFO_ARCH_ARM64 - return true; - #elif CPUINFO_ARCH_ARM - return cpuinfo_isa.vfpv3 && cpuinfo_isa.fma && cpuinfo_isa.d32; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return true; +#elif CPUINFO_ARCH_ARM + return cpuinfo_isa.vfpv3 && cpuinfo_isa.fma && cpuinfo_isa.d32; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_fp16_arith(void) { - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 - return cpuinfo_isa.fp16arith; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 + return cpuinfo_isa.fp16arith; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_bf16(void) { - #if CPUINFO_ARCH_ARM64 - return cpuinfo_isa.bf16; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return cpuinfo_isa.bf16; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_wmmx(void) { - #if CPUINFO_ARCH_ARM - return cpuinfo_isa.wmmx; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM + return cpuinfo_isa.wmmx; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_wmmx2(void) { - #if CPUINFO_ARCH_ARM - return cpuinfo_isa.wmmx2; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM + return cpuinfo_isa.wmmx2; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_neon(void) { - #if CPUINFO_ARCH_ARM64 - return true; - #elif CPUINFO_ARCH_ARM - return cpuinfo_isa.neon; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return true; +#elif CPUINFO_ARCH_ARM + return cpuinfo_isa.neon; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_neon_fp16(void) { - #if CPUINFO_ARCH_ARM64 - return true; - #elif CPUINFO_ARCH_ARM - return cpuinfo_isa.neon && cpuinfo_isa.fp16; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return true; +#elif CPUINFO_ARCH_ARM + return cpuinfo_isa.neon && cpuinfo_isa.fp16; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_neon_fma(void) { - #if CPUINFO_ARCH_ARM64 - return true; - #elif CPUINFO_ARCH_ARM - return cpuinfo_isa.neon && cpuinfo_isa.fma; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return true; +#elif CPUINFO_ARCH_ARM + return cpuinfo_isa.neon && cpuinfo_isa.fma; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_neon_v8(void) { - #if CPUINFO_ARCH_ARM64 - return true; - #elif CPUINFO_ARCH_ARM - return cpuinfo_isa.neon && cpuinfo_isa.armv8; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return true; +#elif CPUINFO_ARCH_ARM + return cpuinfo_isa.neon && cpuinfo_isa.armv8; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_atomics(void) { - #if CPUINFO_ARCH_ARM64 - return cpuinfo_isa.atomics; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return cpuinfo_isa.atomics; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_neon_rdm(void) { - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 - return cpuinfo_isa.rdm; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 + return cpuinfo_isa.rdm; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_neon_fp16_arith(void) { - #if CPUINFO_ARCH_ARM - return cpuinfo_isa.neon && cpuinfo_isa.fp16arith; - #elif CPUINFO_ARCH_ARM64 - return cpuinfo_isa.fp16arith; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM + return cpuinfo_isa.neon && cpuinfo_isa.fp16arith; +#elif CPUINFO_ARCH_ARM64 + return cpuinfo_isa.fp16arith; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_fhm(void) { - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 - return cpuinfo_isa.fhm; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 + return cpuinfo_isa.fhm; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_neon_dot(void) { - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 - return cpuinfo_isa.dot; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 + return cpuinfo_isa.dot; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_neon_bf16(void) { - #if CPUINFO_ARCH_ARM64 - return cpuinfo_isa.bf16; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return cpuinfo_isa.bf16; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_jscvt(void) { - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 - return cpuinfo_isa.jscvt; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 + return cpuinfo_isa.jscvt; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_fcma(void) { - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 - return cpuinfo_isa.fcma; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 + return cpuinfo_isa.fcma; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_i8mm(void) { - #if CPUINFO_ARCH_ARM64 - return cpuinfo_isa.i8mm; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return cpuinfo_isa.i8mm; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_aes(void) { - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 - return cpuinfo_isa.aes; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 + return cpuinfo_isa.aes; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_sha1(void) { - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 - return cpuinfo_isa.sha1; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 + return cpuinfo_isa.sha1; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_sha2(void) { - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 - return cpuinfo_isa.sha2; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 + return cpuinfo_isa.sha2; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_pmull(void) { - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 - return cpuinfo_isa.pmull; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 + return cpuinfo_isa.pmull; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_crc32(void) { - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 - return cpuinfo_isa.crc32; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 + return cpuinfo_isa.crc32; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_sve(void) { - #if CPUINFO_ARCH_ARM64 - return cpuinfo_isa.sve; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return cpuinfo_isa.sve; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_sve_bf16(void) { - #if CPUINFO_ARCH_ARM64 - return cpuinfo_isa.sve && cpuinfo_isa.bf16; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return cpuinfo_isa.sve && cpuinfo_isa.bf16; +#else + return false; +#endif } static inline bool cpuinfo_has_arm_sve2(void) { - #if CPUINFO_ARCH_ARM64 - return cpuinfo_isa.sve2; - #else - return false; - #endif +#if CPUINFO_ARCH_ARM64 + return cpuinfo_isa.sve2; +#else + return false; +#endif } #if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 - /* This structure is not a part of stable API. Use cpuinfo_has_riscv_* functions instead. */ - struct cpuinfo_riscv_isa { - /** - * Keep fields in line with the canonical order as defined by - * Section 27.11 Subset Naming Convention. - */ - /* RV32I/64I/128I Base ISA. */ - bool i; - #if CPUINFO_ARCH_RISCV32 - /* RV32E Base ISA. */ - bool e; - #endif - /* Integer Multiply/Divide Extension. */ - bool m; - /* Atomic Extension. */ - bool a; - /* Single-Precision Floating-Point Extension. */ - bool f; - /* Double-Precision Floating-Point Extension. */ - bool d; - /* Compressed Extension. */ - bool c; - /* Vector Extension. */ - bool v; - }; - - extern struct cpuinfo_riscv_isa cpuinfo_isa; +/* This structure is not a part of stable API. Use cpuinfo_has_riscv_* functions + * instead. */ +struct cpuinfo_riscv_isa { + /** + * Keep fields in line with the canonical order as defined by + * Section 27.11 Subset Naming Convention. + */ + /* RV32I/64I/128I Base ISA. */ + bool i; +#if CPUINFO_ARCH_RISCV32 + /* RV32E Base ISA. */ + bool e; +#endif + /* Integer Multiply/Divide Extension. */ + bool m; + /* Atomic Extension. */ + bool a; + /* Single-Precision Floating-Point Extension. */ + bool f; + /* Double-Precision Floating-Point Extension. */ + bool d; + /* Compressed Extension. */ + bool c; + /* Vector Extension. */ + bool v; +}; + +extern struct cpuinfo_riscv_isa cpuinfo_isa; #endif static inline bool cpuinfo_has_riscv_i(void) { - #if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 - return cpuinfo_isa.i; - #else - return false; - #endif +#if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 + return cpuinfo_isa.i; +#else + return false; +#endif } static inline bool cpuinfo_has_riscv_e(void) { - #if CPUINFO_ARCH_RISCV32 - return cpuinfo_isa.e; - #else - return false; - #endif +#if CPUINFO_ARCH_RISCV32 + return cpuinfo_isa.e; +#else + return false; +#endif } static inline bool cpuinfo_has_riscv_m(void) { - #if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 - return cpuinfo_isa.m; - #else - return false; - #endif +#if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 + return cpuinfo_isa.m; +#else + return false; +#endif } static inline bool cpuinfo_has_riscv_a(void) { - #if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 - return cpuinfo_isa.a; - #else - return false; - #endif +#if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 + return cpuinfo_isa.a; +#else + return false; +#endif } static inline bool cpuinfo_has_riscv_f(void) { - #if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 - return cpuinfo_isa.f; - #else - return false; - #endif +#if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 + return cpuinfo_isa.f; +#else + return false; +#endif } static inline bool cpuinfo_has_riscv_d(void) { - #if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 - return cpuinfo_isa.d; - #else - return false; - #endif +#if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 + return cpuinfo_isa.d; +#else + return false; +#endif } static inline bool cpuinfo_has_riscv_g(void) { // The 'G' extension is simply shorthand for 'IMAFD'. - return cpuinfo_has_riscv_i() - && cpuinfo_has_riscv_m() - && cpuinfo_has_riscv_a() - && cpuinfo_has_riscv_f() - && cpuinfo_has_riscv_d(); + return cpuinfo_has_riscv_i() && cpuinfo_has_riscv_m() && cpuinfo_has_riscv_a() && cpuinfo_has_riscv_f() && + cpuinfo_has_riscv_d(); } static inline bool cpuinfo_has_riscv_c(void) { - #if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 - return cpuinfo_isa.c; - #else - return false; - #endif +#if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 + return cpuinfo_isa.c; +#else + return false; +#endif } static inline bool cpuinfo_has_riscv_v(void) { - #if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 - return cpuinfo_isa.v; - #else - return false; - #endif +#if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 + return cpuinfo_isa.v; +#else + return false; +#endif } const struct cpuinfo_processor* CPUINFO_ABI cpuinfo_get_processors(void); @@ -2039,34 +2079,38 @@ uint32_t CPUINFO_ABI cpuinfo_get_max_cache_size(void); /** * Identify the logical processor that executes the current thread. * - * There is no guarantee that the thread will stay on the same logical processor for any time. - * Callers should treat the result as only a hint, and be prepared to handle NULL return value. + * There is no guarantee that the thread will stay on the same logical processor + * for any time. Callers should treat the result as only a hint, and be prepared + * to handle NULL return value. */ const struct cpuinfo_processor* CPUINFO_ABI cpuinfo_get_current_processor(void); /** * Identify the core that executes the current thread. * - * There is no guarantee that the thread will stay on the same core for any time. - * Callers should treat the result as only a hint, and be prepared to handle NULL return value. + * There is no guarantee that the thread will stay on the same core for any + * time. Callers should treat the result as only a hint, and be prepared to + * handle NULL return value. */ const struct cpuinfo_core* CPUINFO_ABI cpuinfo_get_current_core(void); /** - * Identify the microarchitecture index of the core that executes the current thread. - * If the system does not support such identification, the function returns 0. + * Identify the microarchitecture index of the core that executes the current + * thread. If the system does not support such identification, the function + * returns 0. * - * There is no guarantee that the thread will stay on the same type of core for any time. - * Callers should treat the result as only a hint. + * There is no guarantee that the thread will stay on the same type of core for + * any time. Callers should treat the result as only a hint. */ uint32_t CPUINFO_ABI cpuinfo_get_current_uarch_index(void); /** - * Identify the microarchitecture index of the core that executes the current thread. - * If the system does not support such identification, the function returns the user-specified default value. + * Identify the microarchitecture index of the core that executes the current + * thread. If the system does not support such identification, the function + * returns the user-specified default value. * - * There is no guarantee that the thread will stay on the same type of core for any time. - * Callers should treat the result as only a hint. + * There is no guarantee that the thread will stay on the same type of core for + * any time. Callers should treat the result as only a hint. */ uint32_t CPUINFO_ABI cpuinfo_get_current_uarch_index_with_default(uint32_t default_uarch_index); diff --git a/src/api.c b/src/api.c index 2f70aeff..b8c999f3 100644 --- a/src/api.c +++ b/src/api.c @@ -6,13 +6,13 @@ #include #ifdef __linux__ - #include +#include - #include - #include - #if !defined(__NR_getcpu) - #include - #endif +#include +#include +#if !defined(__NR_getcpu) +#include +#endif #endif bool cpuinfo_is_initialized = false; @@ -21,57 +21,54 @@ struct cpuinfo_processor* cpuinfo_processors = NULL; struct cpuinfo_core* cpuinfo_cores = NULL; struct cpuinfo_cluster* cpuinfo_clusters = NULL; struct cpuinfo_package* cpuinfo_packages = NULL; -struct cpuinfo_cache* cpuinfo_cache[cpuinfo_cache_level_max] = { NULL }; +struct cpuinfo_cache* cpuinfo_cache[cpuinfo_cache_level_max] = {NULL}; uint32_t cpuinfo_processors_count = 0; uint32_t cpuinfo_cores_count = 0; uint32_t cpuinfo_clusters_count = 0; uint32_t cpuinfo_packages_count = 0; -uint32_t cpuinfo_cache_count[cpuinfo_cache_level_max] = { 0 }; +uint32_t cpuinfo_cache_count[cpuinfo_cache_level_max] = {0}; uint32_t cpuinfo_max_cache_size = 0; -#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 \ - || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 - struct cpuinfo_uarch_info* cpuinfo_uarchs = NULL; - uint32_t cpuinfo_uarchs_count = 0; +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 +struct cpuinfo_uarch_info* cpuinfo_uarchs = NULL; +uint32_t cpuinfo_uarchs_count = 0; #else - struct cpuinfo_uarch_info cpuinfo_global_uarch = { cpuinfo_uarch_unknown }; +struct cpuinfo_uarch_info cpuinfo_global_uarch = {cpuinfo_uarch_unknown}; #endif #ifdef __linux__ - uint32_t cpuinfo_linux_cpu_max = 0; - const struct cpuinfo_processor** cpuinfo_linux_cpu_to_processor_map = NULL; - const struct cpuinfo_core** cpuinfo_linux_cpu_to_core_map = NULL; - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 \ - || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 - const uint32_t* cpuinfo_linux_cpu_to_uarch_index_map = NULL; - #endif +uint32_t cpuinfo_linux_cpu_max = 0; +const struct cpuinfo_processor** cpuinfo_linux_cpu_to_processor_map = NULL; +const struct cpuinfo_core** cpuinfo_linux_cpu_to_core_map = NULL; +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 +const uint32_t* cpuinfo_linux_cpu_to_uarch_index_map = NULL; +#endif #endif - const struct cpuinfo_processor* cpuinfo_get_processors(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "processors"); } return cpuinfo_processors; } const struct cpuinfo_core* cpuinfo_get_cores(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "core"); } return cpuinfo_cores; } const struct cpuinfo_cluster* cpuinfo_get_clusters(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "clusters"); } return cpuinfo_clusters; } const struct cpuinfo_package* cpuinfo_get_packages(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "packages"); } return cpuinfo_packages; @@ -81,49 +78,48 @@ const struct cpuinfo_uarch_info* cpuinfo_get_uarchs() { if (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "uarchs"); } - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 \ - || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 - return cpuinfo_uarchs; - #else - return &cpuinfo_global_uarch; - #endif +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 + return cpuinfo_uarchs; +#else + return &cpuinfo_global_uarch; +#endif } const struct cpuinfo_processor* cpuinfo_get_processor(uint32_t index) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "processor"); } - if CPUINFO_UNLIKELY(index >= cpuinfo_processors_count) { + if CPUINFO_UNLIKELY (index >= cpuinfo_processors_count) { return NULL; } return &cpuinfo_processors[index]; } const struct cpuinfo_core* cpuinfo_get_core(uint32_t index) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "core"); } - if CPUINFO_UNLIKELY(index >= cpuinfo_cores_count) { + if CPUINFO_UNLIKELY (index >= cpuinfo_cores_count) { return NULL; } return &cpuinfo_cores[index]; } const struct cpuinfo_cluster* cpuinfo_get_cluster(uint32_t index) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "cluster"); } - if CPUINFO_UNLIKELY(index >= cpuinfo_clusters_count) { + if CPUINFO_UNLIKELY (index >= cpuinfo_clusters_count) { return NULL; } return &cpuinfo_clusters[index]; } const struct cpuinfo_package* cpuinfo_get_package(uint32_t index) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "package"); } - if CPUINFO_UNLIKELY(index >= cpuinfo_packages_count) { + if CPUINFO_UNLIKELY (index >= cpuinfo_packages_count) { return NULL; } return &cpuinfo_packages[index]; @@ -133,43 +129,42 @@ const struct cpuinfo_uarch_info* cpuinfo_get_uarch(uint32_t index) { if (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "uarch"); } - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 \ - || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 - if CPUINFO_UNLIKELY(index >= cpuinfo_uarchs_count) { - return NULL; - } - return &cpuinfo_uarchs[index]; - #else - if CPUINFO_UNLIKELY(index != 0) { - return NULL; - } - return &cpuinfo_global_uarch; - #endif +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 + if CPUINFO_UNLIKELY (index >= cpuinfo_uarchs_count) { + return NULL; + } + return &cpuinfo_uarchs[index]; +#else + if CPUINFO_UNLIKELY (index != 0) { + return NULL; + } + return &cpuinfo_global_uarch; +#endif } uint32_t cpuinfo_get_processors_count(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "processors_count"); } return cpuinfo_processors_count; } uint32_t cpuinfo_get_cores_count(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "cores_count"); } return cpuinfo_cores_count; } uint32_t cpuinfo_get_clusters_count(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "clusters_count"); } return cpuinfo_clusters_count; } uint32_t cpuinfo_get_packages_count(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "packages_count"); } return cpuinfo_packages_count; @@ -179,239 +174,243 @@ uint32_t cpuinfo_get_uarchs_count(void) { if (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "uarchs_count"); } - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 \ - || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 - return cpuinfo_uarchs_count; - #else - return 1; - #endif +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 + return cpuinfo_uarchs_count; +#else + return 1; +#endif } const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l1i_caches(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "l1i_caches"); } return cpuinfo_cache[cpuinfo_cache_level_1i]; } const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l1d_caches(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "l1d_caches"); } return cpuinfo_cache[cpuinfo_cache_level_1d]; } const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l2_caches(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "l2_caches"); } return cpuinfo_cache[cpuinfo_cache_level_2]; } const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l3_caches(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "l3_caches"); } return cpuinfo_cache[cpuinfo_cache_level_3]; } const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l4_caches(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "l4_caches"); } return cpuinfo_cache[cpuinfo_cache_level_4]; } const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l1i_cache(uint32_t index) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "l1i_cache"); } - if CPUINFO_UNLIKELY(index >= cpuinfo_cache_count[cpuinfo_cache_level_1i]) { + if CPUINFO_UNLIKELY (index >= cpuinfo_cache_count[cpuinfo_cache_level_1i]) { return NULL; } return &cpuinfo_cache[cpuinfo_cache_level_1i][index]; } const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l1d_cache(uint32_t index) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "l1d_cache"); } - if CPUINFO_UNLIKELY(index >= cpuinfo_cache_count[cpuinfo_cache_level_1d]) { + if CPUINFO_UNLIKELY (index >= cpuinfo_cache_count[cpuinfo_cache_level_1d]) { return NULL; } return &cpuinfo_cache[cpuinfo_cache_level_1d][index]; } const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l2_cache(uint32_t index) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "l2_cache"); } - if CPUINFO_UNLIKELY(index >= cpuinfo_cache_count[cpuinfo_cache_level_2]) { + if CPUINFO_UNLIKELY (index >= cpuinfo_cache_count[cpuinfo_cache_level_2]) { return NULL; } return &cpuinfo_cache[cpuinfo_cache_level_2][index]; } const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l3_cache(uint32_t index) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "l3_cache"); } - if CPUINFO_UNLIKELY(index >= cpuinfo_cache_count[cpuinfo_cache_level_3]) { + if CPUINFO_UNLIKELY (index >= cpuinfo_cache_count[cpuinfo_cache_level_3]) { return NULL; } return &cpuinfo_cache[cpuinfo_cache_level_3][index]; } const struct cpuinfo_cache* CPUINFO_ABI cpuinfo_get_l4_cache(uint32_t index) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "l4_cache"); } - if CPUINFO_UNLIKELY(index >= cpuinfo_cache_count[cpuinfo_cache_level_4]) { + if CPUINFO_UNLIKELY (index >= cpuinfo_cache_count[cpuinfo_cache_level_4]) { return NULL; } return &cpuinfo_cache[cpuinfo_cache_level_4][index]; } uint32_t CPUINFO_ABI cpuinfo_get_l1i_caches_count(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "l1i_caches_count"); } return cpuinfo_cache_count[cpuinfo_cache_level_1i]; } uint32_t CPUINFO_ABI cpuinfo_get_l1d_caches_count(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "l1d_caches_count"); } return cpuinfo_cache_count[cpuinfo_cache_level_1d]; } uint32_t CPUINFO_ABI cpuinfo_get_l2_caches_count(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "l2_caches_count"); } return cpuinfo_cache_count[cpuinfo_cache_level_2]; } uint32_t CPUINFO_ABI cpuinfo_get_l3_caches_count(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "l3_caches_count"); } return cpuinfo_cache_count[cpuinfo_cache_level_3]; } uint32_t CPUINFO_ABI cpuinfo_get_l4_caches_count(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "l4_caches_count"); } return cpuinfo_cache_count[cpuinfo_cache_level_4]; } uint32_t CPUINFO_ABI cpuinfo_get_max_cache_size(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "max_cache_size"); } return cpuinfo_max_cache_size; } const struct cpuinfo_processor* CPUINFO_ABI cpuinfo_get_current_processor(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "current_processor"); } - #ifdef __linux__ - /* Initializing this variable silences a MemorySanitizer error. */ - unsigned cpu = 0; - if CPUINFO_UNLIKELY(syscall(__NR_getcpu, &cpu, NULL, NULL) != 0) { - return 0; - } - if CPUINFO_UNLIKELY((uint32_t) cpu >= cpuinfo_linux_cpu_max) { - return 0; - } - return cpuinfo_linux_cpu_to_processor_map[cpu]; - #else - return NULL; - #endif +#ifdef __linux__ + /* Initializing this variable silences a MemorySanitizer error. */ + unsigned cpu = 0; + if CPUINFO_UNLIKELY (syscall(__NR_getcpu, &cpu, NULL, NULL) != 0) { + return 0; + } + if CPUINFO_UNLIKELY ((uint32_t)cpu >= cpuinfo_linux_cpu_max) { + return 0; + } + return cpuinfo_linux_cpu_to_processor_map[cpu]; +#else + return NULL; +#endif } const struct cpuinfo_core* CPUINFO_ABI cpuinfo_get_current_core(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "current_core"); } - #ifdef __linux__ - /* Initializing this variable silences a MemorySanitizer error. */ - unsigned cpu = 0; - if CPUINFO_UNLIKELY(syscall(__NR_getcpu, &cpu, NULL, NULL) != 0) { - return 0; - } - if CPUINFO_UNLIKELY((uint32_t) cpu >= cpuinfo_linux_cpu_max) { - return 0; - } - return cpuinfo_linux_cpu_to_core_map[cpu]; - #else - return NULL; - #endif +#ifdef __linux__ + /* Initializing this variable silences a MemorySanitizer error. */ + unsigned cpu = 0; + if CPUINFO_UNLIKELY (syscall(__NR_getcpu, &cpu, NULL, NULL) != 0) { + return 0; + } + if CPUINFO_UNLIKELY ((uint32_t)cpu >= cpuinfo_linux_cpu_max) { + return 0; + } + return cpuinfo_linux_cpu_to_core_map[cpu]; +#else + return NULL; +#endif } uint32_t CPUINFO_ABI cpuinfo_get_current_uarch_index(void) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "current_uarch_index"); } - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 \ - || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 - #ifdef __linux__ - if (cpuinfo_linux_cpu_to_uarch_index_map == NULL) { - /* Special case: avoid syscall on systems with only a single type of cores */ - return 0; - } - - /* General case */ - /* Initializing this variable silences a MemorySanitizer error. */ - unsigned cpu = 0; - if CPUINFO_UNLIKELY(syscall(__NR_getcpu, &cpu, NULL, NULL) != 0) { - return 0; - } - if CPUINFO_UNLIKELY((uint32_t) cpu >= cpuinfo_linux_cpu_max) { - return 0; - } - return cpuinfo_linux_cpu_to_uarch_index_map[cpu]; - #else - /* Fallback: pretend to be on the big core. */ - return 0; - #endif - #else - /* Only ARM/ARM64/RISCV processors may include cores of different types in the same package. */ +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 +#ifdef __linux__ + if (cpuinfo_linux_cpu_to_uarch_index_map == NULL) { + /* Special case: avoid syscall on systems with only a single + * type of cores + */ return 0; - #endif + } + + /* General case */ + /* Initializing this variable silences a MemorySanitizer error. */ + unsigned cpu = 0; + if CPUINFO_UNLIKELY (syscall(__NR_getcpu, &cpu, NULL, NULL) != 0) { + return 0; + } + if CPUINFO_UNLIKELY ((uint32_t)cpu >= cpuinfo_linux_cpu_max) { + return 0; + } + return cpuinfo_linux_cpu_to_uarch_index_map[cpu]; +#else + /* Fallback: pretend to be on the big core. */ + return 0; +#endif +#else + /* Only ARM/ARM64/RISCV processors may include cores of different types + * in the same package. */ + return 0; +#endif } uint32_t CPUINFO_ABI cpuinfo_get_current_uarch_index_with_default(uint32_t default_uarch_index) { - if CPUINFO_UNLIKELY(!cpuinfo_is_initialized) { - cpuinfo_log_fatal("cpuinfo_get_%s called before cpuinfo is initialized", "current_uarch_index_with_default"); - } - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 \ - || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 - #ifdef __linux__ - if (cpuinfo_linux_cpu_to_uarch_index_map == NULL) { - /* Special case: avoid syscall on systems with only a single type of cores */ - return 0; - } - - /* General case */ - /* Initializing this variable silences a MemorySanitizer error. */ - unsigned cpu = 0; - if CPUINFO_UNLIKELY(syscall(__NR_getcpu, &cpu, NULL, NULL) != 0) { - return default_uarch_index; - } - if CPUINFO_UNLIKELY((uint32_t) cpu >= cpuinfo_linux_cpu_max) { - return default_uarch_index; - } - return cpuinfo_linux_cpu_to_uarch_index_map[cpu]; - #else - /* Fallback: no API to query current core, use default uarch index. */ - return default_uarch_index; - #endif - #else - /* Only ARM/ARM64/RISCV processors may include cores of different types in the same package. */ + if CPUINFO_UNLIKELY (!cpuinfo_is_initialized) { + cpuinfo_log_fatal( + "cpuinfo_get_%s called before cpuinfo is initialized", "current_uarch_index_with_default"); + } +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 +#ifdef __linux__ + if (cpuinfo_linux_cpu_to_uarch_index_map == NULL) { + /* Special case: avoid syscall on systems with only a single + * type of cores + */ return 0; - #endif + } + + /* General case */ + /* Initializing this variable silences a MemorySanitizer error. */ + unsigned cpu = 0; + if CPUINFO_UNLIKELY (syscall(__NR_getcpu, &cpu, NULL, NULL) != 0) { + return default_uarch_index; + } + if CPUINFO_UNLIKELY ((uint32_t)cpu >= cpuinfo_linux_cpu_max) { + return default_uarch_index; + } + return cpuinfo_linux_cpu_to_uarch_index_map[cpu]; +#else + /* Fallback: no API to query current core, use default uarch index. */ + return default_uarch_index; +#endif +#else + /* Only ARM/ARM64/RISCV processors may include cores of different types + * in the same package. */ + return 0; +#endif } diff --git a/src/arm/android/api.h b/src/arm/android/api.h index 228632ac..48ef1427 100644 --- a/src/arm/android/api.h +++ b/src/arm/android/api.h @@ -1,9 +1,9 @@ #pragma once -#include -#include #include #include +#include +#include enum cpuinfo_android_chipset_property { cpuinfo_android_chipset_property_proc_cpuinfo_hardware = 0, diff --git a/src/arm/android/properties.c b/src/arm/android/properties.c index 5f93889d..51a2def9 100644 --- a/src/arm/android/properties.c +++ b/src/arm/android/properties.c @@ -1,42 +1,42 @@ #include +#include #include #include -#include #include #include -#include #include #include #include +#include #if CPUINFO_MOCK - #include +#include - static struct cpuinfo_mock_property* cpuinfo_mock_properties = NULL; +static struct cpuinfo_mock_property* cpuinfo_mock_properties = NULL; - void CPUINFO_ABI cpuinfo_mock_android_properties(struct cpuinfo_mock_property* properties) { - cpuinfo_log_info("Android properties mocking enabled"); - cpuinfo_mock_properties = properties; - } +void CPUINFO_ABI cpuinfo_mock_android_properties(struct cpuinfo_mock_property* properties) { + cpuinfo_log_info("Android properties mocking enabled"); + cpuinfo_mock_properties = properties; +} - static int cpuinfo_android_property_get(const char* key, char* value) { - if (cpuinfo_mock_properties != NULL) { - for (const struct cpuinfo_mock_property* prop = cpuinfo_mock_properties; prop->key != NULL; prop++) { - if (strncmp(key, prop->key, CPUINFO_BUILD_PROP_NAME_MAX) == 0) { - strncpy(value, prop->value, CPUINFO_BUILD_PROP_VALUE_MAX); - return (int) strnlen(prop->value, CPUINFO_BUILD_PROP_VALUE_MAX); - } +static int cpuinfo_android_property_get(const char* key, char* value) { + if (cpuinfo_mock_properties != NULL) { + for (const struct cpuinfo_mock_property* prop = cpuinfo_mock_properties; prop->key != NULL; prop++) { + if (strncmp(key, prop->key, CPUINFO_BUILD_PROP_NAME_MAX) == 0) { + strncpy(value, prop->value, CPUINFO_BUILD_PROP_VALUE_MAX); + return (int)strnlen(prop->value, CPUINFO_BUILD_PROP_VALUE_MAX); } } - *value = '\0'; - return 0; } + *value = '\0'; + return 0; +} #else - static inline int cpuinfo_android_property_get(const char* key, char* value) { - return __system_property_get(key, value); - } +static inline int cpuinfo_android_property_get(const char* key, char* value) { + return __system_property_get(key, value); +} #endif void cpuinfo_arm_android_parse_properties(struct cpuinfo_android_properties properties[restrict static 1]) { @@ -50,18 +50,17 @@ void cpuinfo_arm_android_parse_properties(struct cpuinfo_android_properties prop const int ro_mediatek_platform_length = cpuinfo_android_property_get("ro.mediatek.platform", properties->ro_mediatek_platform); - cpuinfo_log_debug("read ro.mediatek.platform = \"%.*s\"", - ro_mediatek_platform_length, properties->ro_mediatek_platform); + cpuinfo_log_debug( + "read ro.mediatek.platform = \"%.*s\"", ro_mediatek_platform_length, properties->ro_mediatek_platform); - const int ro_arch_length = - cpuinfo_android_property_get("ro.arch", properties->ro_arch); + const int ro_arch_length = cpuinfo_android_property_get("ro.arch", properties->ro_arch); cpuinfo_log_debug("read ro.arch = \"%.*s\"", ro_arch_length, properties->ro_arch); - const int ro_chipname_length = - cpuinfo_android_property_get("ro.chipname", properties->ro_chipname); + const int ro_chipname_length = cpuinfo_android_property_get("ro.chipname", properties->ro_chipname); cpuinfo_log_debug("read ro.chipname = \"%.*s\"", ro_chipname_length, properties->ro_chipname); const int ro_hardware_chipname_length = cpuinfo_android_property_get("ro.hardware.chipname", properties->ro_hardware_chipname); - cpuinfo_log_debug("read ro.hardware.chipname = \"%.*s\"", ro_hardware_chipname_length, properties->ro_hardware_chipname); + cpuinfo_log_debug( + "read ro.hardware.chipname = \"%.*s\"", ro_hardware_chipname_length, properties->ro_hardware_chipname); } diff --git a/src/arm/api.h b/src/arm/api.h index 469c84bd..9cfedf60 100644 --- a/src/arm/api.h +++ b/src/arm/api.h @@ -80,45 +80,47 @@ struct cpuinfo_arm_chipset { #define CPUINFO_ARM_CHIPSET_NAME_MAX CPUINFO_PACKAGE_NAME_MAX #ifndef __cplusplus - CPUINFO_INTERNAL void cpuinfo_arm_chipset_to_string( - const struct cpuinfo_arm_chipset chipset[restrict static 1], - char name[restrict static CPUINFO_ARM_CHIPSET_NAME_MAX]); +CPUINFO_INTERNAL void cpuinfo_arm_chipset_to_string( + const struct cpuinfo_arm_chipset chipset[restrict static 1], + char name[restrict static CPUINFO_ARM_CHIPSET_NAME_MAX]); - CPUINFO_INTERNAL void cpuinfo_arm_fixup_chipset( - struct cpuinfo_arm_chipset chipset[restrict static 1], uint32_t cores, uint32_t max_cpu_freq_max); +CPUINFO_INTERNAL void cpuinfo_arm_fixup_chipset( + struct cpuinfo_arm_chipset chipset[restrict static 1], + uint32_t cores, + uint32_t max_cpu_freq_max); - CPUINFO_INTERNAL void cpuinfo_arm_decode_vendor_uarch( - uint32_t midr, - #if CPUINFO_ARCH_ARM - bool has_vfpv4, - #endif - enum cpuinfo_vendor vendor[restrict static 1], - enum cpuinfo_uarch uarch[restrict static 1]); +CPUINFO_INTERNAL void cpuinfo_arm_decode_vendor_uarch( + uint32_t midr, +#if CPUINFO_ARCH_ARM + bool has_vfpv4, +#endif + enum cpuinfo_vendor vendor[restrict static 1], + enum cpuinfo_uarch uarch[restrict static 1]); - CPUINFO_INTERNAL void cpuinfo_arm_decode_cache( - enum cpuinfo_uarch uarch, - uint32_t cluster_cores, - uint32_t midr, - const struct cpuinfo_arm_chipset chipset[restrict static 1], - uint32_t cluster_id, - uint32_t arch_version, - struct cpuinfo_cache l1i[restrict static 1], - struct cpuinfo_cache l1d[restrict static 1], - struct cpuinfo_cache l2[restrict static 1], - struct cpuinfo_cache l3[restrict static 1]); +CPUINFO_INTERNAL void cpuinfo_arm_decode_cache( + enum cpuinfo_uarch uarch, + uint32_t cluster_cores, + uint32_t midr, + const struct cpuinfo_arm_chipset chipset[restrict static 1], + uint32_t cluster_id, + uint32_t arch_version, + struct cpuinfo_cache l1i[restrict static 1], + struct cpuinfo_cache l1d[restrict static 1], + struct cpuinfo_cache l2[restrict static 1], + struct cpuinfo_cache l3[restrict static 1]); - CPUINFO_INTERNAL uint32_t cpuinfo_arm_compute_max_cache_size( - const struct cpuinfo_processor processor[restrict static 1]); +CPUINFO_INTERNAL uint32_t +cpuinfo_arm_compute_max_cache_size(const struct cpuinfo_processor processor[restrict static 1]); #else /* defined(__cplusplus) */ - CPUINFO_INTERNAL void cpuinfo_arm_decode_cache( - enum cpuinfo_uarch uarch, - uint32_t cluster_cores, - uint32_t midr, - const struct cpuinfo_arm_chipset chipset[1], - uint32_t cluster_id, - uint32_t arch_version, - struct cpuinfo_cache l1i[1], - struct cpuinfo_cache l1d[1], - struct cpuinfo_cache l2[1], - struct cpuinfo_cache l3[1]); +CPUINFO_INTERNAL void cpuinfo_arm_decode_cache( + enum cpuinfo_uarch uarch, + uint32_t cluster_cores, + uint32_t midr, + const struct cpuinfo_arm_chipset chipset[1], + uint32_t cluster_id, + uint32_t arch_version, + struct cpuinfo_cache l1i[1], + struct cpuinfo_cache l1d[1], + struct cpuinfo_cache l2[1], + struct cpuinfo_cache l3[1]); #endif diff --git a/src/arm/cache.c b/src/arm/cache.c index 953abb72..dd199193 100644 --- a/src/arm/cache.c +++ b/src/arm/cache.c @@ -1,11 +1,10 @@ #include +#include +#include #include #include #include -#include -#include - void cpuinfo_arm_decode_cache( enum cpuinfo_uarch uarch, @@ -17,8 +16,7 @@ void cpuinfo_arm_decode_cache( struct cpuinfo_cache l1i[restrict static 1], struct cpuinfo_cache l1d[restrict static 1], struct cpuinfo_cache l2[restrict static 1], - struct cpuinfo_cache l3[restrict static 1]) -{ + struct cpuinfo_cache l3[restrict static 1]) { switch (uarch) { #if CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_7A__) && !defined(__ARM_ARCH_8A__) case cpuinfo_uarch_xscale: @@ -27,238 +25,221 @@ void cpuinfo_arm_decode_cache( /* * PXA 210/25X/26X * - * See "Computer Organization and Design, Revised Printing: The Hardware/Software Interface" - * by David A. Patterson, John L. Hennessy + * See "Computer Organization and + * Design, Revised Printing: The + * Hardware/Software Interface" by David + * A. Patterson, John L. Hennessy */ - *l1i = (struct cpuinfo_cache) { - .size = 16 * 1024, - .associativity = 32, - .line_size = 32 - }; - *l1d = (struct cpuinfo_cache) { - .size = 16 * 1024, - .associativity = 4, - .line_size = 64 - }; + *l1i = (struct cpuinfo_cache){ + .size = 16 * 1024, .associativity = 32, .line_size = 32}; + *l1d = (struct cpuinfo_cache){ + .size = 16 * 1024, .associativity = 4, .line_size = 64}; break; case 4: /* PXA 27X */ - *l1i = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 32, - .line_size = 32 - }; - *l1d = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 32, - .line_size = 32 - }; + *l1i = (struct cpuinfo_cache){ + .size = 32 * 1024, .associativity = 32, .line_size = 32}; + *l1d = (struct cpuinfo_cache){ + .size = 32 * 1024, .associativity = 32, .line_size = 32}; break; case 6: /* * PXA 3XX * - * See http://download.intel.com/design/intelxscale/31628302.pdf + * See + * http://download.intel.com/design/intelxscale/31628302.pdf */ - *l1i = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 4, - .line_size = 32 - }; - *l1d = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 4, - .line_size = 32 - }; - *l2 = (struct cpuinfo_cache) { - .size = 256 * 1024, - .associativity = 8, - .line_size = 32 - }; + *l1i = (struct cpuinfo_cache){ + .size = 32 * 1024, .associativity = 4, .line_size = 32}; + *l1d = (struct cpuinfo_cache){ + .size = 32 * 1024, .associativity = 4, .line_size = 32}; + *l2 = (struct cpuinfo_cache){ + .size = 256 * 1024, .associativity = 8, .line_size = 32}; break; } break; case cpuinfo_uarch_arm11: - *l1i = (struct cpuinfo_cache) { - .size = 16 * 1024, - .associativity = 4, - .line_size = 32 - }; - *l1d = (struct cpuinfo_cache) { - .size = 16 * 1024, - .associativity = 4, - .line_size = 32 - }; + *l1i = (struct cpuinfo_cache){.size = 16 * 1024, .associativity = 4, .line_size = 32}; + *l1d = (struct cpuinfo_cache){.size = 16 * 1024, .associativity = 4, .line_size = 32}; break; -#endif /* CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_7A__) && !defined(__ARM_ARCH_8A__) */ +#endif /* CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_7A__) && \ + !defined(__ARM_ARCH_8A__) */ #if CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_8A__) case cpuinfo_uarch_cortex_a5: /* * Cortex-A5 Technical Reference Manual: * 7.1.1. Memory system - * The Cortex-A5 processor has separate instruction and data caches. - * The caches have the following features: + * The Cortex-A5 processor has separate instruction + * and data caches. The caches have the following + * features: * - Data cache is 4-way set-associative. * - Instruction cache is 2-way set-associative. * - The cache line length is eight words. - * - You can configure the instruction and data caches independently during implementation - * to sizes of 4KB, 8KB, 16KB, 32KB, or 64KB. - * 1.1.3. System design components - * PrimeCell Level 2 Cache Controller (PL310) - * The addition of an on-chip secondary cache, also referred to as a Level 2 or L2 cache, is a - * recognized method of improving the performance of ARM-based systems when significant memory traffic - * is generated by the processor. The PrimeCell Level 2 Cache Controller reduces the number of external - * memory accesses and has been optimized for use with the Cortex-A5 processor. - * 8.1.7. Exclusive L2 cache - * The Cortex-A5 processor can be connected to an L2 cache that supports an exclusive cache mode. - * This mode must be activated both in the Cortex-A5 processor and in the L2 cache controller. + * - You can configure the instruction and data + * caches independently during implementation to sizes + * of 4KB, 8KB, 16KB, 32KB, or 64KB. 1.1.3. System + * design components PrimeCell Level 2 Cache Controller + * (PL310) The addition of an on-chip secondary cache, + * also referred to as a Level 2 or L2 cache, is a + * recognized method of improving the performance of + * ARM-based systems when significant memory traffic is + * generated by the processor. The PrimeCell Level 2 + * Cache Controller reduces the number of external + * memory accesses and has been optimized for use with + * the Cortex-A5 processor. 8.1.7. Exclusive L2 cache + * The Cortex-A5 processor can be connected to an L2 + * cache that supports an exclusive cache mode. This + * mode must be activated both in the Cortex-A5 + * processor and in the L2 cache controller. * * +--------------------+-----------+-----------+----------+-----------+ - * | Processor model | L1D cache | L1I cache | L2 cache | Reference | + * | Processor model | L1D cache | L1I cache | L2 + * cache | Reference | * +--------------------+-----------+-----------+----------+-----------+ - * | Qualcomm MSM7225A | | | | | - * | Qualcomm MSM7625A | | | | | - * | Qualcomm MSM7227A | | | | | - * | Qualcomm MSM7627A | 32K | 32K | 256K | Wiki [1] | - * | Qualcomm MSM7225AB | | | | | - * | Qualcomm MSM7225AB | | | | | - * | Qualcomm QSD8250 | | | | | - * | Qualcomm QSD8650 | | | | | + * | Qualcomm MSM7225A | | | | | + * | Qualcomm MSM7625A | | | | | + * | Qualcomm MSM7227A | | | | | + * | Qualcomm MSM7627A | 32K | 32K | 256K + * | Wiki [1] | | Qualcomm MSM7225AB | | | | + * | | Qualcomm MSM7225AB | | | | | + * | Qualcomm QSD8250 | | | | | + * | Qualcomm QSD8650 | | | | | * +--------------------+-----------+-----------+----------+-----------+ - * | Spreadtrum SC6821 | 32K | 32K | ? | | - * | Spreadtrum SC6825 | 32K | 32K | 256K | Wiki [2] | - * | Spreadtrum SC8810 | ? | ? | ? | | - * | Spreadtrum SC8825 | 32K | 32K | ? | | + * | Spreadtrum SC6821 | 32K | 32K | ? + * | | | Spreadtrum SC6825 | 32K | 32K + * | 256K | Wiki [2] | | Spreadtrum SC8810 | ? + * | ? | ? | | | Spreadtrum + * SC8825 | 32K | 32K | ? | | * +--------------------+-----------+-----------+----------+-----------+ * - * [1] https://en.wikipedia.org/wiki/List_of_Qualcomm_Snapdragon_systems-on-chip#Snapdragon_S1 + * [1] + * https://en.wikipedia.org/wiki/List_of_Qualcomm_Snapdragon_systems-on-chip#Snapdragon_S1 * [2] https://en.wikipedia.org/wiki/Spreadtrum */ - *l1i = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 2, - .line_size = 32 - }; - *l1d = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 4, - .line_size = 32 - }; - *l2 = (struct cpuinfo_cache) { + *l1i = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 2, .line_size = 32}; + *l1d = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 32}; + *l2 = (struct cpuinfo_cache){ .size = 256 * 1024, /* - * Follow NXP specification: "Eight-way set-associative 512 kB L2 cache with 32B line size" - * Reference: http://www.nxp.com/assets/documents/data/en/application-notes/AN4947.pdf + * Follow NXP specification: "Eight-way + * set-associative 512 kB L2 cache with 32B line + * size" Reference: + * http://www.nxp.com/assets/documents/data/en/application-notes/AN4947.pdf */ .associativity = 8, - .line_size = 32 - }; + .line_size = 32}; break; case cpuinfo_uarch_cortex_a7: /* * Cortex-A7 MPCore Technical Reference Manual: * 6.1. About the L1 memory system - * The L1 memory system consists of separate instruction and data caches. You can configure the - * instruction and data caches independently during implementation to sizes of 8KB, 16KB, 32KB, or 64KB. + * The L1 memory system consists of separate + * instruction and data caches. You can configure the + * instruction and data caches independently during + * implementation to sizes of 8KB, 16KB, 32KB, or 64KB. * - * The L1 instruction memory system has the following features: + * The L1 instruction memory system has the following + * features: * - Instruction side cache line length of 32-bytes. * - 2-way set-associative instruction cache. * - * The L1 data memory system has the following features: + * The L1 data memory system has the following + * features: * - Data side cache line length of 64-bytes. * - 4-way set-associative data cache. * * 7.1. About the L2 Memory system * The L2 memory system consists of an: * - Optional tightly-coupled L2 cache that includes: - * - Configurable L2 cache size of 128KB, 256KB, 512KB, and 1MB. + * - Configurable L2 cache size of 128KB, 256KB, + * 512KB, and 1MB. * - Fixed line length of 64 bytes * - 8-way set-associative cache structure * * +--------------------+-------+-----------+-----------+-----------+-----------+ - * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference | + * | Processor model | Cores | L1D cache | L1I cache + * | L2 cache | Reference | * +--------------------+-------+-----------+-----------+-----------+-----------+ - * | Allwinner A20 | 2 | 32K | 32K | 256K | [1] | - * | Allwinner A23 | 2 | 32K | 32K | 256K | [2] | - * | Allwinner A31 | 4 | 32K | 32K | 1M | [3] | - * | Allwinner A31s | 4 | 32K | 32K | 1M | [4] | - * | Allwinner A33 | 4 | 32K | 32K | 512K | [5] | - * | Allwinner A80 Octa | 4(+4) | 32K | 32K | 512K(+2M) | [6] | - * | Allwinner A81T | 8 | 32K | 32K | 1M | [7] | + * | Allwinner A20 | 2 | 32K | 32K | + * 256K | [1] | | Allwinner A23 | 2 | 32K + * | 32K | 256K | [2] | | Allwinner A31 | + * 4 | 32K | 32K | 1M | [3] | | + * Allwinner A31s | 4 | 32K | 32K | + * 1M | [4] | | Allwinner A33 | 4 | 32K + * | 32K | 512K | [5] | | Allwinner A80 + * Octa | 4(+4) | 32K | 32K | 512K(+2M) | [6] + * | | Allwinner A81T | 8 | 32K | 32K | + * 1M | [7] | * +--------------------+-------+-----------+-----------+-----------+-----------+ - * | Broadcom BCM2836 | 4 | 32K | 32K | 512K | [8] | + * | Broadcom BCM2836 | 4 | 32K | 32K | + * 512K | [8] + * | * +--------------------+-------+-----------+-----------+-----------+-----------+ - * | Kirin 920 | 4(+4) | ? | ? | 512K | [9] | + * | Kirin 920 | 4(+4) | ? | ? | + * 512K | [9] + * | * +--------------------+-------+-----------+-----------+-----------+-----------+ * * [1] https://linux-sunxi.org/A20 * [2] https://linux-sunxi.org/A23 - * [3] http://dl.linux-sunxi.org/A31/A3x_release_document/A31/IC/A31%20datasheet%20V1.3%2020131106.pdf - * [4] https://github.com/allwinner-zh/documents/blob/master/A31s/A31s_Datasheet_v1.5_20150510.pdf - * [5] http://dl.linux-sunxi.org/A33/A33_Datasheet_release1.0.pdf - * [6] https://linux-sunxi.org/images/1/10/A80_Datasheet_Revision_1.0_0404.pdf - * [7] http://dl.linux-sunxi.org/A83T/A83T_datasheet_Revision_1.1.pdf - * [8] https://www.raspberrypi.org/forums/viewtopic.php?t=98428 - * [9] http://www.gizmochina.com/2014/10/07/hisilicon-kirin-920-tear-down/ + * [3] + * http://dl.linux-sunxi.org/A31/A3x_release_document/A31/IC/A31%20datasheet%20V1.3%2020131106.pdf + * [4] + * https://github.com/allwinner-zh/documents/blob/master/A31s/A31s_Datasheet_v1.5_20150510.pdf + * [5] + * http://dl.linux-sunxi.org/A33/A33_Datasheet_release1.0.pdf + * [6] + * https://linux-sunxi.org/images/1/10/A80_Datasheet_Revision_1.0_0404.pdf + * [7] + * http://dl.linux-sunxi.org/A83T/A83T_datasheet_Revision_1.1.pdf + * [8] + * https://www.raspberrypi.org/forums/viewtopic.php?t=98428 + * [9] + * http://www.gizmochina.com/2014/10/07/hisilicon-kirin-920-tear-down/ */ - *l1i = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 2, - .line_size = 32 - }; - *l1d = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 4, - .line_size = 64 - }; - *l2 = (struct cpuinfo_cache) { - .size = 128 * 1024 * cluster_cores, - .associativity = 8, - .line_size = 64 - }; + *l1i = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 2, .line_size = 32}; + *l1d = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 64}; + *l2 = (struct cpuinfo_cache){ + .size = 128 * 1024 * cluster_cores, .associativity = 8, .line_size = 64}; break; case cpuinfo_uarch_cortex_a8: /* * Cortex-A8 Technical Reference Manual: * 7.1. About the L1 memory system - * The L1 memory system consists of separate instruction and data caches in a Harvard arrangement. - * The L1 memory system provides the core with: + * The L1 memory system consists of separate + * instruction and data caches in a Harvard arrangement. + * The L1 memory system provides the core with: * - fixed line length of 64 bytes * - support for 16KB or 32KB caches * - 4-way set associative cache structure * 8.1. About the L2 memory system - * The L2 memory system is tightly coupled to the L1 data cache and L1 instruction cache. - * The key features of the L2 memory system include: - * - configurable cache size of 0KB, 128KB, 256KB, 512KB, and 1MB + * The L2 memory system is tightly coupled to the L1 + * data cache and L1 instruction cache. The key features + * of the L2 memory system include: + * - configurable cache size of 0KB, 128KB, 256KB, + * 512KB, and 1MB * - fixed line length of 64 bytes * - 8-way set associative cache structure * * +----------------------+-----------+-----------+-----------+-----------+ - * | Processor model | L1D cache | L1I cache | L2 cache | Reference | + * | Processor model | L1D cache | L1I cache | L2 + * cache | Reference + * | * +----------------------+-----------+-----------+-----------+-----------+ - * | Exynos 3 Single 3110 | 32K | 32K | 512K | [1] | + * | Exynos 3 Single 3110 | 32K | 32K | + * 512K | [1] | * +----------------------+-----------+-----------+-----------+-----------+ - * | TI DM 3730 | 32K | 32K | 256K | [2] | + * | TI DM 3730 | 32K | 32K | + * 256K | [2] | * +----------------------+-----------+-----------+-----------+-----------+ * - * [1] https://en.wikichip.org/w/images/0/04/Exynos_3110.pdf + * [1] + * https://en.wikichip.org/w/images/0/04/Exynos_3110.pdf * [2] https://www.ti.com/lit/ds/symlink/dm3725.pdf */ - *l1i = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 4, - .line_size = 64 - }; - *l1d = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 4, - .line_size = 64 - }; - *l2 = (struct cpuinfo_cache) { - .associativity = 8, - .line_size = 64 - }; + *l1i = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 64}; + *l1d = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 64}; + *l2 = (struct cpuinfo_cache){.associativity = 8, .line_size = 64}; switch (chipset->vendor) { case cpuinfo_arm_chipset_vendor_samsung: l2->size = 512 * 1024; @@ -273,111 +254,117 @@ void cpuinfo_arm_decode_cache( /* * ARM Cortex‑A9 Technical Reference Manual: * 7.1.1 Memory system - * The Cortex‑A9 processor has separate instruction and data caches. - * The caches have the following features: + * The Cortex‑A9 processor has separate instruction + * and data caches. The caches have the following + * features: * - Both caches are 4-way set-associative. * - The cache line length is eight words. - * - You can configure the instruction and data caches independently during implementation - * to sizes of 16KB, 32KB, or 64KB. - * 8.1.5 Exclusive L2 cache - * The Cortex‑A9 processor can be connected to an L2 cache that supports an exclusive cache mode. - * This mode must be activated both in the Cortex‑A9 processor and in the L2 cache controller. + * - You can configure the instruction and data + * caches independently during implementation to sizes + * of 16KB, 32KB, or 64KB. 8.1.5 Exclusive L2 cache The + * Cortex‑A9 processor can be connected to an L2 cache + * that supports an exclusive cache mode. This mode must + * be activated both in the Cortex‑A9 processor and in + * the L2 cache controller. * * +--------------------+-------+-----------+-----------+-----------+-----------+ - * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference | + * | Processor model | Cores | L1D cache | L1I cache + * | L2 cache | Reference | * +--------------------+-------+-----------+-----------+-----------+-----------+ - * | Exynos 4 Dual 4210 | 2 | 32K | 32K | 1M | [1] | - * | Exynos 4 Dual 4212 | 2 | 32K | 32K | 1M | [2] | - * | Exynos 4 Quad 4412 | 4 | 32K | 32K | 1M | [3] | - * | Exynos 4 Quad 4415 | 4 | 32K | 32K | 1M | | - * | TI OMAP 4430 | 2 | 32K | 32K | 1M | [4] | - * | TI OMAP 4460 | 2 | 32K | 32K | 1M | [5] | + * | Exynos 4 Dual 4210 | 2 | 32K | 32K | + * 1M | [1] | | Exynos 4 Dual 4212 | 2 | 32K + * | 32K | 1M | [2] | | Exynos 4 Quad + * 4412 | 4 | 32K | 32K | 1M | [3] + * | | Exynos 4 Quad 4415 | 4 | 32K | 32K + * | 1M | | | TI OMAP 4430 | 2 | 32K + * | 32K | 1M | [4] | | TI OMAP 4460 | + * 2 | 32K | 32K | 1M | [5] | * +--------------------+-------+-----------+-----------+-----------+-----------+ * - * [1] http://www.samsung.com/global/business/semiconductor/file/product/Exynos_4_Dual_45nm_User_Manaul_Public_REV1.00-0.pdf - * [2] http://www.samsung.com/global/business/semiconductor/file/product/Exynos_4_Dual_32nm_User_Manaul_Public_REV100-0.pdf - * [3] http://www.samsung.com/global/business/semiconductor/file/product/Exynos_4_Quad_User_Manaul_Public_REV1.00-0.pdf - * [4] https://www.hotchips.org/wp-content/uploads/hc_archives/hc21/2_mon/HC21.24.400.ClientProcessors-Epub/HC21.24.421.Witt-OMAP4430.pdf - * [5] http://www.anandtech.com/show/5310/samsung-galaxy-nexus-ice-cream-sandwich-review/9 + * [1] + * http://www.samsung.com/global/business/semiconductor/file/product/Exynos_4_Dual_45nm_User_Manaul_Public_REV1.00-0.pdf + * [2] + * http://www.samsung.com/global/business/semiconductor/file/product/Exynos_4_Dual_32nm_User_Manaul_Public_REV100-0.pdf + * [3] + * http://www.samsung.com/global/business/semiconductor/file/product/Exynos_4_Quad_User_Manaul_Public_REV1.00-0.pdf + * [4] + * https://www.hotchips.org/wp-content/uploads/hc_archives/hc21/2_mon/HC21.24.400.ClientProcessors-Epub/HC21.24.421.Witt-OMAP4430.pdf + * [5] + * http://www.anandtech.com/show/5310/samsung-galaxy-nexus-ice-cream-sandwich-review/9 */ /* Use Exynos 4 specs */ - *l1i = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 4, - .line_size = 32 - }; - *l1d = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 4, - .line_size = 32 - }; - *l2 = (struct cpuinfo_cache) { + *l1i = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 32}; + *l1d = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 32}; + *l2 = (struct cpuinfo_cache){ .size = 1024 * 1024, - /* OMAP4460 in Pandaboard ES has 16-way set-associative L2 cache */ + /* OMAP4460 in Pandaboard ES has 16-way + set-associative L2 cache */ .associativity = 16, - .line_size = 32 - }; + .line_size = 32}; break; case cpuinfo_uarch_cortex_a15: /* * 6.1. About the L1 memory system - * The L1 memory system consists of separate instruction and data caches. - * The L1 instruction memory system has the following features: + * The L1 memory system consists of separate + * instruction and data caches. The L1 instruction + * memory system has the following features: * - 32KB 2-way set-associative instruction cache. * - Fixed line length of 64 bytes. - * The L1 data memory system has the following features: + * The L1 data memory system has the following + * features: * - 32KB 2-way set-associative data cache. * - Fixed line length of 64 bytes. * 7.1. About the L2 memory system * The features of the L2 memory system include: - * - Configurable L2 cache size of 512KB, 1MB, 2MB and 4MB. + * - Configurable L2 cache size of 512KB, 1MB, 2MB + * and 4MB. * - Fixed line length of 64 bytes. * - 16-way set-associative cache structure. * * +--------------------+-------+-----------+-----------+-----------+-----------+ - * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference | + * | Processor model | Cores | L1D cache | L1I cache + * | L2 cache | Reference | * +--------------------+-------+-----------+-----------+-----------+-----------+ - * | Exynos 5 Dual 5250 | 2 | 32K | 32K | 1M | [1] | - * | Exynos 5 Hexa 5260 | 2(+4) | 32K | 32K | 1M(+512K) | [2] | - * | Exynos 5 Octa 5410 | 4(+4) | 32K | 32K | 2M(+512K) | [3] | - * | Exynos 5 Octa 5420 | 4(+4) | 32K | 32K | 2M(+512K) | [3] | - * | Exynos 5 Octa 5422 | 4(+4) | 32K | 32K | 2M(+512K) | [3] | - * | Exynos 5 Octa 5430 | 4(+4) | 32K | 32K | 2M(+512K) | [3] | - * | Exynos 5 Octa 5800 | 4(+4) | 32K | 32K | 2M(+512K) | [3] | - * | Kirin 920 | 4(+4) | ? | ? | 2M(+512K) | [4] | + * | Exynos 5 Dual 5250 | 2 | 32K | 32K | + * 1M | [1] | | Exynos 5 Hexa 5260 | 2(+4) | 32K + * | 32K | 1M(+512K) | [2] | | Exynos 5 Octa + * 5410 | 4(+4) | 32K | 32K | 2M(+512K) | + * [3] | | Exynos 5 Octa 5420 | 4(+4) | 32K | + * 32K | 2M(+512K) | [3] | | Exynos 5 Octa 5422 | + * 4(+4) | 32K | 32K | 2M(+512K) | [3] | + * | Exynos 5 Octa 5430 | 4(+4) | 32K | 32K | + * 2M(+512K) | [3] | | Exynos 5 Octa 5800 | 4(+4) + * | 32K | 32K | 2M(+512K) | [3] | | + * Kirin 920 | 4(+4) | ? | ? | + * 2M(+512K) | [4] | * +--------------------+-------+-----------+-----------+-----------+-----------+ * - * [1] http://www.arndaleboard.org/wiki/downloads/supports/Exynos_5_Dual_User_Manaul_Public_REV1.00.pdf - * [2] http://www.yicsystem.com/wp-content/uploads/2014/08/Espresso5260P-Guide-Book.pdf - * [3] http://www.anandtech.com/show/6768/samsung-details-exynos-5-octa-architecture-power-at-isscc-13 - * [4] http://www.gizmochina.com/2014/10/07/hisilicon-kirin-920-tear-down/ + * [1] + * http://www.arndaleboard.org/wiki/downloads/supports/Exynos_5_Dual_User_Manaul_Public_REV1.00.pdf + * [2] + * http://www.yicsystem.com/wp-content/uploads/2014/08/Espresso5260P-Guide-Book.pdf + * [3] + * http://www.anandtech.com/show/6768/samsung-details-exynos-5-octa-architecture-power-at-isscc-13 + * [4] + * http://www.gizmochina.com/2014/10/07/hisilicon-kirin-920-tear-down/ */ - *l1i = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 2, - .line_size = 64 - }; - *l1d = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 2, - .line_size = 64 - }; - *l2 = (struct cpuinfo_cache) { - .size = cluster_cores * 512 * 1024, - .associativity = 16, - .line_size = 64 - }; + *l1i = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 2, .line_size = 64}; + *l1d = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 2, .line_size = 64}; + *l2 = (struct cpuinfo_cache){ + .size = cluster_cores * 512 * 1024, .associativity = 16, .line_size = 64}; break; case cpuinfo_uarch_cortex_a17: /* - * ARM Cortex-A17 MPCore Processor Technical Reference Manual: - * 6.1. About the L1 memory system - * The L1 memory system consists of separate instruction and data caches. - * The size of the instruction cache is implemented as either 32KB or 64KB. - * The size of the data cache is 32KB. - * - * The L1 instruction cache has the following features: + * ARM Cortex-A17 MPCore Processor Technical Reference + * Manual: 6.1. About the L1 memory system The L1 memory + * system consists of separate instruction and data + * caches. The size of the instruction cache is + * implemented as either 32KB or 64KB. The size of the + * data cache is 32KB. + * + * The L1 instruction cache has the following + * features: * - Instruction side cache line length of 64-bytes. * - 4-way set-associative instruction cache. * @@ -387,138 +374,158 @@ void cpuinfo_arm_decode_cache( * * 7.1. About the L2 Memory system * An integrated L2 cache: - * - The cache size is implemented as either 256KB, 512KB, 1MB, 2MB, 4MB or 8MB. + * - The cache size is implemented as either 256KB, + * 512KB, 1MB, 2MB, 4MB or 8MB. * - A fixed line length of 64 bytes. * - 16-way set-associative cache structure. * * +------------------+-------+-----------+-----------+-----------+-----------+ - * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference | + * | Processor model | Cores | L1D cache | L1I cache | + * L2 cache | Reference | * +------------------+-------+-----------+-----------+-----------+-----------+ - * | MediaTek MT6595 | 4(+4) | 32K | 32K | 2M(+512K) | [1] | + * | MediaTek MT6595 | 4(+4) | 32K | 32K | + * 2M(+512K) | [1] | * +------------------+-------+-----------+-----------+-----------+-----------+ * * [1] https://blog.osakana.net/archives/5268 */ - *l1i = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 4, - .line_size = 64 - }; - *l1d = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 4, - .line_size = 64 - }; - *l2 = (struct cpuinfo_cache) { - .size = cluster_cores * 512 * 1024, - .associativity = 16, - .line_size = 64 - }; + *l1i = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 64}; + *l1d = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 64}; + *l2 = (struct cpuinfo_cache){ + .size = cluster_cores * 512 * 1024, .associativity = 16, .line_size = 64}; break; #endif /* CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_8A__) */ case cpuinfo_uarch_cortex_a35: /* * ARM Cortex‑A35 Processor Technical Reference Manual: * 6.1. About the L1 memory system - * The L1 memory system includes several power-saving and performance-enhancing features. - * These include separate instruction and data caches, which can be configured - * independently during implementation to sizes of 8KB, 16KB, 32KB, or 64KB. + * The L1 memory system includes several power-saving + * and performance-enhancing features. These include + * separate instruction and data caches, which can be + * configured independently during implementation to + * sizes of 8KB, 16KB, 32KB, or 64KB. * * L1 instruction-side memory system * A dedicated instruction cache that: * - is virtually indexed and physically tagged. * - is 2-way set associative. - * - is configurable to be 8KB, 16KB, 32KB, or 64KB. + * - is configurable to be 8KB, 16KB, 32KB, or + * 64KB. * - uses a cache line length of 64 bytes. * * L1 data-side memory system * A dedicated data cache that: * - is physically indexed and physically tagged. * - is 4-way set associative. - * - is configurable to be 8KB, 16KB, 32KB, or 64KB. + * - is configurable to be 8KB, 16KB, 32KB, or + * 64KB. * - uses a cache line length of 64 bytes. * * 7.1. About the L2 memory system * The L2 cache is 8-way set associative. * Further features of the L2 cache are: - * - Configurable size of 128KB, 256KB, 512KB, and 1MB. + * - Configurable size of 128KB, 256KB, 512KB, and + * 1MB. * - Fixed line length of 64 bytes. * - Physically indexed and tagged. * * +-----------------+---------+-----------+-----------+-----------+-----------+ - * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference | + * | Processor model | Cores | L1D cache | L1I cache + * | L2 cache | Reference | * +-----------------+---------+-----------+-----------+-----------+-----------+ - * | MediaTek MT6599 | 4(+4+2) | ? | ? | ? | | + * | MediaTek MT6599 | 4(+4+2) | ? | ? | ? + * | | * +-----------------+---------+-----------+-----------+-----------+-----------+ */ - *l1i = (struct cpuinfo_cache) { - .size = 16 * 1024, /* assumption based on low-end Cortex-A53 */ + *l1i = (struct cpuinfo_cache){ + .size = 16 * 1024, /* assumption based on + low-end Cortex-A53 */ .associativity = 2, - .line_size = 64 - }; - *l1d = (struct cpuinfo_cache) { - .size = 16 * 1024, /* assumption based on low-end Cortex-A53 */ + .line_size = 64}; + *l1d = (struct cpuinfo_cache){ + .size = 16 * 1024, /* assumption based on + low-end Cortex-A53 */ .associativity = 4, - .line_size = 64 - }; - *l2 = (struct cpuinfo_cache) { - .size = 256 * 1024, /* assumption based on low-end Cortex-A53 */ + .line_size = 64}; + *l2 = (struct cpuinfo_cache){ + .size = 256 * 1024, /* assumption based on + low-end Cortex-A53 */ .associativity = 8, - .line_size = 64 - }; + .line_size = 64}; break; case cpuinfo_uarch_cortex_a53: /* - * ARM Cortex-A53 MPCore Processor Technical Reference Manual: - * 6.1. About the L1 memory system - * The L1 memory system consists of separate instruction and data caches. The implementer configures the - * instruction and data caches independently during implementation, to sizes of 8KB, 16KB, 32KB, or 64KB. - * - * The L1 Instruction memory system has the following key features: + * ARM Cortex-A53 MPCore Processor Technical Reference + * Manual: 6.1. About the L1 memory system The L1 memory + * system consists of separate instruction and data + * caches. The implementer configures the instruction + * and data caches independently during implementation, + * to sizes of 8KB, 16KB, 32KB, or 64KB. + * + * The L1 Instruction memory system has the following + * key features: * - Instruction side cache line length of 64 bytes. * - 2-way set associative L1 Instruction cache. * - * The L1 Data memory system has the following features: + * The L1 Data memory system has the following + * features: * - Data side cache line length of 64 bytes. * - 4-way set associative L1 Data cache. * * 7.1. About the L2 memory system * The L2 memory system consists of an: * - Optional tightly-coupled L2 cache that includes: - * - Configurable L2 cache size of 128KB, 256KB, 512KB, 1MB and 2MB. + * - Configurable L2 cache size of 128KB, 256KB, + * 512KB, 1MB and 2MB. * - Fixed line length of 64 bytes. * - 16-way set-associative cache structure. * * +--------------------+-------+-----------+-----------+-----------+-----------+ - * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference | + * | Processor model | Cores | L1D cache | L1I cache + * | L2 cache | Reference | * +--------------------+-------+-----------+-----------+-----------+-----------+ - * | Broadcom BCM2837 | 4 | 16K | 16K | 512K | [1] | - * | Exynos 7420 | 4(+4) | 32K | 32K | 256K | [2, 3] | - * | Exynos 8890 | 4(+4) | 32K | 32K | 256K | [4] | - * | Rochchip RK3368 | 4+4 | 32K | 32K | 512K+256K | sysfs | - * | MediaTek MT8173C | 2(+2) | 32K | 32K | 512K(+1M) | sysfs | - * | Snapdragon 410 | 4 | 32K | 32K | 512K | [3] | - * | Snapdragon 630 | 4+4 | 32K | 32K | 1M+512K | sysfs | - * | Snapdragon 636 | 4(+4) | 32K+64K | 32K+64K | 1M+1M | sysfs | - * | Snapdragon 660 | 4(+4) | 32K+64K | 32K+64K | 1M+1M | sysfs | - * | Snapdragon 835 | 4(+4) | 32K+64K | 32K+64K | 1M(+2M) | sysfs | - * | Kirin 620 | 4+4 | 32K | 32K | 512K | [5] | + * | Broadcom BCM2837 | 4 | 16K | 16K | + * 512K | [1] | | Exynos 7420 | 4(+4) | 32K + * | 32K | 256K | [2, 3] | | Exynos 8890 | + * 4(+4) | 32K | 32K | 256K | [4] | | + * Rochchip RK3368 | 4+4 | 32K | 32K | + * 512K+256K | sysfs | | MediaTek MT8173C | 2(+2) + * | 32K | 32K | 512K(+1M) | sysfs | | + * Snapdragon 410 | 4 | 32K | 32K | + * 512K | [3] | | Snapdragon 630 | 4+4 | + * 32K | 32K | 1M+512K | sysfs | | + * Snapdragon 636 | 4(+4) | 32K+64K | 32K+64K | + * 1M+1M | sysfs | | Snapdragon 660 | 4(+4) | + * 32K+64K | 32K+64K | 1M+1M | sysfs | | + * Snapdragon 835 | 4(+4) | 32K+64K | 32K+64K | + * 1M(+2M) | sysfs | | Kirin 620 | 4+4 | + * 32K | 32K | 512K | [5] + * | * +--------------------+-------+-----------+-----------+-----------+-----------+ * - * [1] https://www.raspberrypi.org/forums/viewtopic.php?f=91&t=145766 - * [2] http://www.anandtech.com/show/9330/exynos-7420-deep-dive/2 - * [3] https://www.usenix.org/system/files/conference/usenixsecurity16/sec16_paper_lipp.pdf - * [4] http://www.boardset.com/products/products_v8890.php - * [5] http://mirror.lemaker.org/Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf + * [1] + * https://www.raspberrypi.org/forums/viewtopic.php?f=91&t=145766 + * [2] + * http://www.anandtech.com/show/9330/exynos-7420-deep-dive/2 + * [3] + * https://www.usenix.org/system/files/conference/usenixsecurity16/sec16_paper_lipp.pdf + * [4] + * http://www.boardset.com/products/products_v8890.php + * [5] + * http://mirror.lemaker.org/Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf */ if (midr_is_qualcomm_cortex_a53_silver(midr)) { - /* Qualcomm-modified Cortex-A53 in Snapdragon 630/660/835 */ + /* Qualcomm-modified Cortex-A53 in Snapdragon + * 630/660/835 */ uint32_t l2_size = 512 * 1024; switch (chipset->series) { case cpuinfo_arm_chipset_series_qualcomm_msm: if (chipset->model == 8998) { - /* Snapdragon 835 (MSM8998): 1 MB L2 (little cores only) */ + /* Snapdragon 835 + * (MSM8998): 1 MB L2 + * (little cores only) + */ l2_size = 1024 * 1024; } break; @@ -526,16 +533,30 @@ void cpuinfo_arm_decode_cache( switch (chipset->model) { case 630: if (cluster_id == 0) { - /* Snapdragon 630: 1 MB L2 for the big cores */ + /* Snapdragon + * 630: + * 1 MB + * L2 + * for + * the + * big + * cores + */ l2_size = 1024 * 1024; } break; case 636: - /* Snapdragon 636: 1 MB L2 (little cores only) */ + /* Snapdragon + * 636: 1 MB L2 + * (little cores + * only) */ l2_size = 1024 * 1024; break; case 660: - /* Snapdragon 660: 1 MB L2 (little cores only) */ + /* Snapdragon + * 660: 1 MB L2 + * (little cores + * only) */ l2_size = 1024 * 1024; break; } @@ -544,21 +565,9 @@ void cpuinfo_arm_decode_cache( break; } - *l1i = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 2, - .line_size = 64 - }; - *l1d = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 4, - .line_size = 64 - }; - *l2 = (struct cpuinfo_cache) { - .size = l2_size, - .associativity = 16, - .line_size = 64 - }; + *l1i = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 2, .line_size = 64}; + *l1d = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 64}; + *l2 = (struct cpuinfo_cache){.size = l2_size, .associativity = 16, .line_size = 64}; } else { /* Standard Cortex-A53 */ @@ -570,22 +579,42 @@ void cpuinfo_arm_decode_cache( l1_size = 32 * 1024; l2_size = 512 * 1024; switch (chipset->model) { - case 8937: /* Snapdragon 430 */ - case 8940: /* Snapdragon 435 */ - case 8953: /* Snapdragon 625 or 626 (8953PRO) */ + case 8937: /* Snapdragon + 430 */ + case 8940: /* Snapdragon + 435 */ + case 8953: /* Snapdragon + 625 or 626 + (8953PRO) + */ if (cluster_id == 0) { - /* 1M L2 for big cluster */ + /* 1M L2 + * for + * big + * cluster + */ l2_size = 1024 * 1024; } break; - case 8952: /* Snapdragon 617 */ + case 8952: /* Snapdragon + 617 */ if (cluster_id != 0) { - /* 256K L2 for LITTLE cluster */ + /* 256K + * L2 + * for + * LITTLE + * cluster + */ l2_size = 256 * 1024; } break; default: - /* Silence compiler warning about unhandled enum values */ + /* Silence + * compiler + * warning about + * unhandled + * enum values + */ break; } break; @@ -597,7 +626,8 @@ void cpuinfo_arm_decode_cache( l1_size = 32 * 1024; l2_size = 512 * 1024; if (chipset->model == 450 && cluster_id == 0) { - /* Snapdragon 450: 1M L2 for big cluster */ + /* Snapdragon 450: 1M L2 + * for big cluster */ l2_size = 1024 * 1024; } break; @@ -608,7 +638,8 @@ void cpuinfo_arm_decode_cache( case cpuinfo_arm_chipset_series_hisilicon_kirin: l1_size = 32 * 1024; switch (chipset->model) { - case 970: /* Kirin 970 */ + case 970: /* Kirin 970 + */ l2_size = 1024 * 1024; break; default: @@ -629,7 +660,14 @@ void cpuinfo_arm_decode_cache( switch (chipset->model) { case 3368: if (cluster_id == 0) { - /* RK3368: 512 KB L2 for the big cores */ + /* RK3368: + * 512 + * KB L2 + * for + * the + * big + * cores + */ l2_size = 512 * 1024; } break; @@ -646,24 +684,14 @@ void cpuinfo_arm_decode_cache( l1_size = 32 * 1024; break; default: - /* Silence compiler warning about unhandled enum values */ + /* Silence compiler warning + * about unhandled enum values + */ break; } - *l1i = (struct cpuinfo_cache) { - .size = l1_size, - .associativity = 2, - .line_size = 64 - }; - *l1d = (struct cpuinfo_cache) { - .size = l1_size, - .associativity = 4, - .line_size = 64 - }; - *l2 = (struct cpuinfo_cache) { - .size = l2_size, - .associativity = 16, - .line_size = 64 - }; + *l1i = (struct cpuinfo_cache){.size = l1_size, .associativity = 2, .line_size = 64}; + *l1d = (struct cpuinfo_cache){.size = l1_size, .associativity = 4, .line_size = 64}; + *l2 = (struct cpuinfo_cache){.size = l2_size, .associativity = 16, .line_size = 64}; } break; case cpuinfo_uarch_cortex_a55r0: @@ -671,12 +699,16 @@ void cpuinfo_arm_decode_cache( /* * ARM Cortex-A55 Core Technical Reference Manual * A6.1. About the L1 memory system - * The Cortex®-A55 core's L1 memory system enhances core performance and power efficiency. - * It consists of separate instruction and data caches. You can configure instruction and data caches - * independently during implementation to sizes of 16KB, 32KB, or 64KB. + * The Cortex®-A55 core's L1 memory system enhances + * core performance and power efficiency. It consists of + * separate instruction and data caches. You can + * configure instruction and data caches independently + * during implementation to sizes of 16KB, 32KB, or + * 64KB. * * L1 instruction-side memory system - * The L1 instruction-side memory system provides an instruction stream to the DPU. Its key features are: + * The L1 instruction-side memory system provides an + * instruction stream to the DPU. Its key features are: * - 64-byte instruction side cache line length. * - 4-way set associative L1 instruction cache. * @@ -685,10 +717,12 @@ void cpuinfo_arm_decode_cache( * - 4-way set associative L1 data cache. * * A7.1 About the L2 memory system - * The Cortex-A55 L2 memory system is required to interface the Cortex-A55 cores to the L3 memory system. - * The L2 memory subsystem consists of: - * - An optional 4-way, set-associative L2 cache with a configurable size of 64KB, 128KB or 256KB. Cache - * lines have a fixed length of 64 bytes. + * The Cortex-A55 L2 memory system is required to + * interface the Cortex-A55 cores to the L3 memory + * system. The L2 memory subsystem consists of: + * - An optional 4-way, set-associative L2 cache with + * a configurable size of 64KB, 128KB or 256KB. Cache + * lines have a fixed length of 64 bytes. * * The main features of the L2 memory system are: * - Strictly exclusive with L1 data cache. @@ -696,23 +730,30 @@ void cpuinfo_arm_decode_cache( * - Private per-core unified L2 cache. * * +--------------------+-------+-----------+-----------+-----------+----------+------------+ - * | Processor model | Cores | L1D cache | L1I cache | L2 cache | L3 cache | Reference | + * | Processor model | Cores | L1D cache | L1I cache + * | L2 cache | L3 cache | Reference | * +--------------------+-------+-----------+-----------+-----------+----------+------------+ - * | Snapdragon 845 | 4(+4) | 32K | 32K | 128K | 2M | [1], sysfs | - * | Exynos 9810 | 4(+4) | ? | ? | None | 512K | [2] | - * | Kirin 980 | 4(+4) | 32K | 32K | 128K | 4M | [3] | + * | Snapdragon 845 | 4(+4) | 32K | 32K | + * 128K | 2M | [1], sysfs | | Exynos 9810 | + * 4(+4) | ? | ? | None | 512K | + * [2] | | Kirin 980 | 4(+4) | 32K | 32K + * | 128K | 4M | [3] | * +--------------------+-------+-----------+-----------+-----------+----------+------------+ * - * [1] https://www.anandtech.com/show/12114/qualcomm-announces-snapdragon-845-soc - * [2] https://www.anandtech.com/show/12478/exynos-9810-handson-awkward-first-results + * [1] + * https://www.anandtech.com/show/12114/qualcomm-announces-snapdragon-845-soc + * [2] + * https://www.anandtech.com/show/12478/exynos-9810-handson-awkward-first-results * [3] https://en.wikichip.org/wiki/hisilicon/kirin/980 */ if (midr_is_qualcomm_cortex_a55_silver(midr)) { - /* Qualcomm-modified Cortex-A55 in Snapdragon 670 / 710 / 845 */ + /* Qualcomm-modified Cortex-A55 in Snapdragon + * 670 / 710 / 845 */ uint32_t l3_size = 1024 * 1024; switch (chipset->series) { case cpuinfo_arm_chipset_series_qualcomm_snapdragon: - /* Snapdragon 845: 2M L3 cache */ + /* Snapdragon 845: 2M L3 cache + */ if (chipset->model == 845) { l3_size = 2 * 1024 * 1024; } @@ -721,22 +762,22 @@ void cpuinfo_arm_decode_cache( break; } - *l1i = (struct cpuinfo_cache) { + *l1i = (struct cpuinfo_cache){ .size = 32 * 1024, .associativity = 4, .line_size = 64, }; - *l1d = (struct cpuinfo_cache) { + *l1d = (struct cpuinfo_cache){ .size = 32 * 1024, .associativity = 4, .line_size = 64, }; - *l2 = (struct cpuinfo_cache) { + *l2 = (struct cpuinfo_cache){ .size = 128 * 1024, .associativity = 4, .line_size = 64, }; - *l3 = (struct cpuinfo_cache) { + *l3 = (struct cpuinfo_cache){ .size = l3_size, .associativity = 16, .line_size = 64, @@ -744,18 +785,18 @@ void cpuinfo_arm_decode_cache( } else { /* Standard Cortex-A55 */ - *l1i = (struct cpuinfo_cache) { + *l1i = (struct cpuinfo_cache){ .size = 32 * 1024, .associativity = 4, .line_size = 64, }; - *l1d = (struct cpuinfo_cache) { + *l1d = (struct cpuinfo_cache){ .size = 32 * 1024, .associativity = 4, .line_size = 64, }; if (chipset->series == cpuinfo_arm_chipset_series_samsung_exynos) { - *l2 = (struct cpuinfo_cache) { + *l2 = (struct cpuinfo_cache){ .size = 512 * 1024, /* DynamIQ */ .associativity = 16, @@ -765,7 +806,8 @@ void cpuinfo_arm_decode_cache( uint32_t l3_size = 1024 * 1024; switch (chipset->series) { case cpuinfo_arm_chipset_series_hisilicon_kirin: - /* Kirin 980: 4M L3 cache */ + /* Kirin 980: 4M L3 + * cache */ if (chipset->model == 980) { l3_size = 4 * 1024 * 1024; } @@ -773,12 +815,12 @@ void cpuinfo_arm_decode_cache( default: break; } - *l2 = (struct cpuinfo_cache) { + *l2 = (struct cpuinfo_cache){ .size = 128 * 1024, .associativity = 4, .line_size = 64, }; - *l3 = (struct cpuinfo_cache) { + *l3 = (struct cpuinfo_cache){ .size = l3_size, /* DynamIQ */ .associativity = 16, @@ -789,65 +831,67 @@ void cpuinfo_arm_decode_cache( break; case cpuinfo_uarch_cortex_a57: /* - * ARM Cortex-A57 MPCore Processor Technical Reference Manual: - * 6.1. About the L1 memory system - * The L1 memory system consists of separate instruction and data caches. + * ARM Cortex-A57 MPCore Processor Technical Reference + * Manual: 6.1. About the L1 memory system The L1 memory + * system consists of separate instruction and data + * caches. * - * The L1 instruction memory system has the following features: + * The L1 instruction memory system has the following + * features: * - 48KB 3-way set-associative instruction cache. * - Fixed line length of 64 bytes. * - * The L1 data memory system has the following features: + * The L1 data memory system has the following + * features: * - 32KB 2-way set-associative data cache. * - Fixed line length of 64 bytes. * * 7.1 About the L2 memory system * The features of the L2 memory system include: - * - Configurable L2 cache size of 512KB, 1MB, and 2MB. + * - Configurable L2 cache size of 512KB, 1MB, and + * 2MB. * - Fixed line length of 64 bytes. * - 16-way set-associative cache structure. * - Inclusion property with L1 data caches. * * +--------------------+-------+-----------+-----------+-----------+-----------+ - * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference | + * | Processor model | Cores | L1D cache | L1I cache + * | L2 cache | Reference | * +--------------------+-------+-----------+-----------+-----------+-----------+ - * | Snapdragon 810 | 4(+4) | 32K | 48K | 2M | [1] | - * | Exynos 7420 | 4(+4) | 32K | 48K | 2M | [2] | - * | Jetson TX1 | 4 | 32K | 48K | 2M | [3] | + * | Snapdragon 810 | 4(+4) | 32K | 48K | + * 2M | [1] | | Exynos 7420 | 4(+4) | 32K + * | 48K | 2M | [2] | | Jetson TX1 | 4 + * | 32K | 48K | 2M | [3] | * +--------------------+-------+-----------+-----------+-----------+-----------+ * - * [1] http://www.anandtech.com/show/9837/snapdragon-820-preview - * [2] http://www.anandtech.com/show/9330/exynos-7420-deep-dive/2 - * [3] https://devblogs.nvidia.com/parallelforall/jetson-tx2-delivers-twice-intelligence-edge/ + * [1] + * http://www.anandtech.com/show/9837/snapdragon-820-preview + * [2] + * http://www.anandtech.com/show/9330/exynos-7420-deep-dive/2 + * [3] + * https://devblogs.nvidia.com/parallelforall/jetson-tx2-delivers-twice-intelligence-edge/ */ - *l1i = (struct cpuinfo_cache) { - .size = 48 * 1024, - .associativity = 3, - .line_size = 64 - }; - *l1d = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 2, - .line_size = 64 - }; - *l2 = (struct cpuinfo_cache) { + *l1i = (struct cpuinfo_cache){.size = 48 * 1024, .associativity = 3, .line_size = 64}; + *l1d = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 2, .line_size = 64}; + *l2 = (struct cpuinfo_cache){ .size = cluster_cores * 512 * 1024, .associativity = 16, .line_size = 64, - .flags = CPUINFO_CACHE_INCLUSIVE - }; + .flags = CPUINFO_CACHE_INCLUSIVE}; break; - case cpuinfo_uarch_cortex_a65: - { + case cpuinfo_uarch_cortex_a65: { /* * ARM Cortex‑A65 Core Technical Reference Manual * A6.1. About the L1 memory system - * The L1 memory system enhances the performance and power efficiency in the Cortex‑A65 core. - * It consists of separate instruction and data caches. You can configure instruction and data caches - * independently during implementation to sizes of 32KB or 64KB. + * The L1 memory system enhances the performance and + * power efficiency in the Cortex‑A65 core. It consists + * of separate instruction and data caches. You can + * configure instruction and data caches independently + * during implementation to sizes of 32KB or 64KB. * * L1 instruction-side memory system - * The L1 instruction-side memory system provides an instruction stream to the DPU. Its key features are: + * The L1 instruction-side memory system provides an + * instruction stream to the DPU. Its key features are: * - 64-byte instruction side cache line length. * - 4-way set associative L1 instruction cache. * @@ -856,10 +900,12 @@ void cpuinfo_arm_decode_cache( * - 4-way set associative L1 data cache. * * A7.1 About the L2 memory system - * The Cortex‑A65 L2 memory system is required to interface the Cortex‑A65 cores to the L3 memory system. - * The L2 memory subsystem consists of: - * - An optional 4-way, set-associative L2 cache with a configurable size of 64KB, 128KB, or 256KB. - * Cache lines have a fixed length of 64 bytes. + * The Cortex‑A65 L2 memory system is required to + * interface the Cortex‑A65 cores to the L3 memory + * system. The L2 memory subsystem consists of: + * - An optional 4-way, set-associative L2 cache with + * a configurable size of 64KB, 128KB, or 256KB. Cache + * lines have a fixed length of 64 bytes. * * The main features of the L2 memory system are: * - Strictly exclusive with L1 data cache. @@ -869,23 +915,19 @@ void cpuinfo_arm_decode_cache( const uint32_t l1_size = 32 * 1024; const uint32_t l2_size = 128 * 1024; const uint32_t l3_size = 512 * 1024; - *l1i = (struct cpuinfo_cache) { + *l1i = (struct cpuinfo_cache){ .size = l1_size, .associativity = 4, .line_size = 64, }; - *l1d = (struct cpuinfo_cache) { + *l1d = (struct cpuinfo_cache){ .size = l1_size, .associativity = 4, .line_size = 64, }; - *l2 = (struct cpuinfo_cache) { - .size = l2_size, - .associativity = 4, - .line_size = 64, - .flags = CPUINFO_CACHE_INCLUSIVE - }; - *l3 = (struct cpuinfo_cache) { + *l2 = (struct cpuinfo_cache){ + .size = l2_size, .associativity = 4, .line_size = 64, .flags = CPUINFO_CACHE_INCLUSIVE}; + *l3 = (struct cpuinfo_cache){ .size = l3_size, /* DynamIQ */ .associativity = 16, @@ -893,49 +935,63 @@ void cpuinfo_arm_decode_cache( }; break; } - case cpuinfo_uarch_cortex_a72: - { + case cpuinfo_uarch_cortex_a72: { /* - * ARM Cortex-A72 MPCore Processor Technical Reference Manual - * 6.1. About the L1 memory system - * The L1 memory system consists of separate instruction and data caches. + * ARM Cortex-A72 MPCore Processor Technical Reference + * Manual 6.1. About the L1 memory system The L1 memory + * system consists of separate instruction and data + * caches. * - * The L1 instruction memory system has the following features: + * The L1 instruction memory system has the following + * features: * - 48KB 3-way set-associative instruction cache. * - Fixed line length of 64 bytes. * - * The L1 data memory system has the following features: + * The L1 data memory system has the following + * features: * - 32KB 2-way set-associative data cache. * - Fixed cache line length of 64 bytes. * * 7.1 About the L2 memory system * The features of the L2 memory system include: - * - Configurable L2 cache size of 512KB, 1MB, 2MB and 4MB. + * - Configurable L2 cache size of 512KB, 1MB, 2MB + * and 4MB. * - Fixed line length of 64 bytes. * - Banked pipeline structures. * - Inclusion property with L1 data caches. * - 16-way set-associative cache structure. * * +---------------------+---------+-----------+-----------+------------+-----------+ - * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference | + * | Processor model | Cores | L1D cache | L1I + * cache | L2 cache | Reference | * +---------------------+---------+-----------+-----------+------------+-----------+ - * | Snapdragon 650 | 2(+4) | 32K(+32K) | 48K(+32K) | 1M(+512K) | [1] | - * | Snapdragon 652 | 4(+4) | 32K(+32K) | 48K(+32K) | 1M(+512K) | [2] | - * | Snapdragon 653 | 4(+4) | 32K(+32K) | 48K(+32K) | 1M(+512K) | [3] | - * | HiSilicon Kirin 950 | 4(+4) | 32K+32K | 48K+32K | ? | | - * | HiSilicon Kirin 955 | 4(+4) | 32K+32K | 48K+32K | ? | | - * | MediaTek MT8173C | 2(+2) | 32K(+32K) | 48K(+32K) | 1M(+512K) | sysfs | - * | MediaTek Helio X20 | 2(+4+4) | ? | ? | ? | | - * | MediaTek Helio X23 | 2(+4+4) | ? | ? | ? | | - * | MediaTek Helio X25 | 2(+4+4) | ? | ? | ? | | - * | MediaTek Helio X27 | 2(+4+4) | ? | ? | ? | | - * | Broadcom BCM2711 | 4 | 32K | 48K | 1M | [4] | + * | Snapdragon 650 | 2(+4) | 32K(+32K) | + * 48K(+32K) | 1M(+512K) | [1] | | Snapdragon 652 | + * 4(+4) | 32K(+32K) | 48K(+32K) | 1M(+512K) | [2] + * | | Snapdragon 653 | 4(+4) | 32K(+32K) | + * 48K(+32K) | 1M(+512K) | [3] | | HiSilicon + * Kirin 950 | 4(+4) | 32K+32K | 48K+32K | ? | + * | | HiSilicon Kirin 955 | 4(+4) | 32K+32K | + * 48K+32K | ? | | | MediaTek + * MT8173C | 2(+2) | 32K(+32K) | 48K(+32K) | + * 1M(+512K) | sysfs | | MediaTek Helio X20 | + * 2(+4+4) | ? | ? | ? | | | + * MediaTek Helio X23 | 2(+4+4) | ? | ? | + * ? | | | MediaTek Helio X25 | 2(+4+4) | ? | + * ? | ? | | | MediaTek Helio X27 | + * 2(+4+4) | ? | ? | ? | | | + * Broadcom BCM2711 | 4 | 32K | 48K | + * 1M | [4] | * +---------------------+---------+-----------+-----------+------------+-----------+ * - * [1] http://pdadb.net/index.php?m=processor&id=578&c=qualcomm_snapdragon_618_msm8956__snapdragon_650 - * [2] http://pdadb.net/index.php?m=processor&id=667&c=qualcomm_snapdragon_620_apq8076__snapdragon_652 - * [3] http://pdadb.net/index.php?m=processor&id=692&c=qualcomm_snapdragon_653_msm8976sg__msm8976_pro - * [4] https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711/README.md + * [1] + * http://pdadb.net/index.php?m=processor&id=578&c=qualcomm_snapdragon_618_msm8956__snapdragon_650 + * [2] + * http://pdadb.net/index.php?m=processor&id=667&c=qualcomm_snapdragon_620_apq8076__snapdragon_652 + * [3] + * http://pdadb.net/index.php?m=processor&id=692&c=qualcomm_snapdragon_653_msm8976sg__msm8976_pro + * [4] + * https://www.raspberrypi.org/documentation/hardware/raspberrypi/bcm2711/README.md */ uint32_t l2_size; switch (chipset->series) { @@ -947,66 +1003,72 @@ void cpuinfo_arm_decode_cache( break; } - *l1i = (struct cpuinfo_cache) { - .size = 48 * 1024, - .associativity = 3, - .line_size = 64 - }; - *l1d = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 2, - .line_size = 64 - }; - *l2 = (struct cpuinfo_cache) { + *l1i = (struct cpuinfo_cache){.size = 48 * 1024, .associativity = 3, .line_size = 64}; + *l1d = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 2, .line_size = 64}; + *l2 = (struct cpuinfo_cache){ .size = l2_size, .associativity = 16, .line_size = 64, - .flags = CPUINFO_CACHE_INCLUSIVE - }; + .flags = CPUINFO_CACHE_INCLUSIVE}; break; } - case cpuinfo_uarch_cortex_a73: - { + case cpuinfo_uarch_cortex_a73: { /* - * ARM Cortex‑A73 MPCore Processor Technical Reference Manual - * 6.1. About the L1 memory system - * The L1 memory system consists of separate instruction and data caches. - * The size of the instruction cache is 64KB. - * The size of the data cache is configurable to either 32KB or 64KB. - * - * The L1 instruction memory system has the following key features: - * - Virtually Indexed, Physically Tagged (VIPT), four-way set-associative instruction cache. + * ARM Cortex‑A73 MPCore Processor Technical Reference + * Manual 6.1. About the L1 memory system The L1 memory + * system consists of separate instruction and data + * caches. The size of the instruction cache is 64KB. + * The size of the data cache is configurable to either + * 32KB or 64KB. + * + * The L1 instruction memory system has the following + * key features: + * - Virtually Indexed, Physically Tagged (VIPT), + * four-way set-associative instruction cache. * - Fixed cache line length of 64 bytes. * - * The L1 data memory system has the following features: - * - ...the data cache behaves like an eight-way set associative PIPT cache (for 32KB configurations) - * and a 16-way set associative PIPT cache (for 64KB configurations). + * The L1 data memory system has the following + * features: + * - ...the data cache behaves like an eight-way set + * associative PIPT cache (for 32KB configurations) and + * a 16-way set associative PIPT cache (for 64KB + * configurations). * - Fixed cache line length of 64 bytes. * * 7.1 About the L2 memory system * The L2 memory system consists of: * - A tightly-integrated L2 cache with: - * - A configurable size of 256KB, 512KB, 1MB, 2MB, 4MB, or 8MB. + * - A configurable size of 256KB, 512KB, 1MB, 2MB, + * 4MB, or 8MB. * - A 16-way, set-associative structure. * - A fixed line length of 64 bytes. * * The ARM Cortex A73 - Artemis Unveiled [1] - * "ARM still envisions that most vendors will choose to use configurations of 1 to - * 2MB in consumer products. The L2 cache is inclusive of the L1 cache. " + * "ARM still envisions that most vendors will choose + * to use configurations of 1 to 2MB in consumer + * products. The L2 cache is inclusive of the L1 cache. + * " * * +---------------------+---------+-----------+-----------+-----------+-----------+ - * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference | + * | Processor model | Cores | L1D cache | L1I + * cache | L2 cache | Reference | * +---------------------+---------+-----------+-----------+-----------+-----------+ - * | HiSilicon Kirin 960 | 4(+4) | 64K+32K | 64K+32K | ? | [2] | - * | MediaTek Helio X30 | 2(+4+4) | ? | 64K+ ? | ? | | - * | Snapdragon 636 | 4(+4) | 64K(+32K) | 64K(+32K) | 1M(+1M) | sysfs | - * | Snapdragon 660 | 4(+4) | 64K+32K | 64K+32K | 1M(+1M) | [3] | - * | Snapdragon 835 | 4(+4) | 64K+32K | 64K+32K | 2M(+1M) | sysfs | + * | HiSilicon Kirin 960 | 4(+4) | 64K+32K | + * 64K+32K | ? | [2] | | MediaTek Helio X30 + * | 2(+4+4) | ? | 64K+ ? | ? | | | + * Snapdragon 636 | 4(+4) | 64K(+32K) | 64K(+32K) + * | 1M(+1M) | sysfs | | Snapdragon 660 | 4(+4) + * | 64K+32K | 64K+32K | 1M(+1M) | [3] | | + * Snapdragon 835 | 4(+4) | 64K+32K | 64K+32K + * | 2M(+1M) | sysfs | * +---------------------+---------+-----------+-----------+-----------+-----------+ * - * [1] http://www.anandtech.com/show/10347/arm-cortex-a73-artemis-unveiled/2 - * [2] http://www.anandtech.com/show/11088/hisilicon-kirin-960-performance-and-power/3 - * [3] https://arstechnica.com/gadgets/2017/05/qualcomms-snapdragon-660-and-630-bring-more-high-end-features-to-midrange-chips/ + * [1] + * http://www.anandtech.com/show/10347/arm-cortex-a73-artemis-unveiled/2 + * [2] + * http://www.anandtech.com/show/11088/hisilicon-kirin-960-performance-and-power/3 + * [3] + * https://arstechnica.com/gadgets/2017/05/qualcomms-snapdragon-660-and-630-bring-more-high-end-features-to-midrange-chips/ */ uint32_t l1d_size = 32 * 1024; uint32_t l2_size = 512 * 1024; @@ -1017,69 +1079,73 @@ void cpuinfo_arm_decode_cache( break; case cpuinfo_arm_chipset_series_mediatek_mt: l1d_size = 64 * 1024; - l2_size = 1 * 1024 * 1024; /* TODO: verify assumption */ + l2_size = 1 * 1024 * 1024; /* TODO: verify assumption + */ break; default: switch (midr) { - case UINT32_C(0x51AF8001): /* Kryo 280 Gold */ + case UINT32_C(0x51AF8001): /* Kryo 280 + Gold */ l1d_size = 64 * 1024; l2_size = 2 * 1024 * 1024; break; - case UINT32_C(0x51AF8002): /* Kryo 260 Gold */ + case UINT32_C(0x51AF8002): /* Kryo 260 + Gold */ l1d_size = 64 * 1024; l2_size = 1 * 1024 * 1024; break; } } - *l1i = (struct cpuinfo_cache) { - .size = 64 * 1024, - .associativity = 4, - .line_size = 64 - }; - *l1d = (struct cpuinfo_cache) { - .size = l1d_size, - .associativity = (l1d_size >> 12), - .line_size = 64 - }; - *l2 = (struct cpuinfo_cache) { + *l1i = (struct cpuinfo_cache){.size = 64 * 1024, .associativity = 4, .line_size = 64}; + *l1d = (struct cpuinfo_cache){ + .size = l1d_size, .associativity = (l1d_size >> 12), .line_size = 64}; + *l2 = (struct cpuinfo_cache){ .size = l2_size, .associativity = 16, .line_size = 64, - .flags = CPUINFO_CACHE_INCLUSIVE - }; + .flags = CPUINFO_CACHE_INCLUSIVE}; break; } - case cpuinfo_uarch_cortex_a75: - { + case cpuinfo_uarch_cortex_a75: { /* * ARM Cortex-A75 Core Technical Reference Manual * A6.1. About the L1 memory system - * The L1 memory system consists of separate instruction and data caches. Both have a fixed size of 64KB. + * The L1 memory system consists of separate + * instruction and data caches. Both have a fixed size + * of 64KB. * * A6.1.1 L1 instruction-side memory system - * The L1 instruction memory system has the following key features: - * - Virtually Indexed, Physically Tagged (VIPT), four-way set-associative instruction cache. + * The L1 instruction memory system has the following + * key features: + * - Virtually Indexed, Physically Tagged (VIPT), + * four-way set-associative instruction cache. * - Fixed cache line length of 64 bytes. * * A6.1.2 L1 data-side memory system - * The L1 data memory system has the following features: - * - Physically Indexed, Physically Tagged (PIPT), 16-way set-associative L1 data cache. + * The L1 data memory system has the following + * features: + * - Physically Indexed, Physically Tagged (PIPT), + * 16-way set-associative L1 data cache. * - Fixed cache line length of 64 bytes. * - Pseudo-random cache replacement policy. * * A7.1 About the L2 memory system * The L2 memory subsystem consist of: - * - An 8-way set associative L2 cache with a configurable size of 256KB or 512KB. - * Cache lines have a fixed length of 64 bytes. + * - An 8-way set associative L2 cache with a + * configurable size of 256KB or 512KB. Cache lines have + * a fixed length of 64 bytes. * * +--------------------+-------+-----------+-----------+-----------+----------+------------+ - * | Processor model | Cores | L1D cache | L1I cache | L2 cache | L3 cache | Reference | + * | Processor model | Cores | L1D cache | L1I cache + * | L2 cache | L3 cache | Reference | * +--------------------+-------+-----------+-----------+-----------+----------+------------+ - * | Snapdragon 845 | 4(+4) | 64K | 64K | 256K | 2M | [1], sysfs | + * | Snapdragon 845 | 4(+4) | 64K | 64K | + * 256K | 2M | [1], sysfs | * +--------------------+-------+-----------+-----------+-----------+----------+------------+ * - * [1] https://www.anandtech.com/show/12114/qualcomm-announces-snapdragon-845-soc + * [1] + * https://www.anandtech.com/show/12114/qualcomm-announces-snapdragon-845-soc */ uint32_t l3_size = 1024 * 1024; switch (chipset->series) { @@ -1092,70 +1158,66 @@ void cpuinfo_arm_decode_cache( default: break; } - *l1i = (struct cpuinfo_cache) { - .size = 64 * 1024, - .associativity = 4, - .line_size = 64 - }; - *l1d = (struct cpuinfo_cache) { - .size = 64 * 1024, - .associativity = 16, - .line_size = 64 - }; - *l2 = (struct cpuinfo_cache) { - .size = 256 * 1024, - .associativity = 8, - .line_size = 64 - }; - *l3 = (struct cpuinfo_cache) { - .size = l3_size, - .associativity = 16, - .line_size = 64 - }; + *l1i = (struct cpuinfo_cache){.size = 64 * 1024, .associativity = 4, .line_size = 64}; + *l1d = (struct cpuinfo_cache){.size = 64 * 1024, .associativity = 16, .line_size = 64}; + *l2 = (struct cpuinfo_cache){.size = 256 * 1024, .associativity = 8, .line_size = 64}; + *l3 = (struct cpuinfo_cache){.size = l3_size, .associativity = 16, .line_size = 64}; break; } - case cpuinfo_uarch_cortex_a76: - { + case cpuinfo_uarch_cortex_a76: { /* * ARM Cortex-A76 Core Technical Reference Manual * A6.1. About the L1 memory system - * The L1 memory system consists of separate instruction and data caches. Both have a fixed size of 64KB. + * The L1 memory system consists of separate + * instruction and data caches. Both have a fixed size + * of 64KB. * * A6.1.1 L1 instruction-side memory system - * The L1 instruction memory system has the following key features: - * - Virtually Indexed, Physically Tagged (VIPT), which behaves as a Physically Indexed, - * Physically Tagged (PIPT) 4-way set-associative L1 data cache. + * The L1 instruction memory system has the following + * key features: + * - Virtually Indexed, Physically Tagged (VIPT), + * which behaves as a Physically Indexed, Physically + * Tagged (PIPT) 4-way set-associative L1 data cache. * - Fixed cache line length of 64 bytes. * * A6.1.2 L1 data-side memory system - * The L1 data memory system has the following features: - * - Virtually Indexed, Physically Tagged (VIPT), which behaves as a Physically Indexed, - * Physically Tagged (PIPT) 4-way set-associative L1 data cache. + * The L1 data memory system has the following + * features: + * - Virtually Indexed, Physically Tagged (VIPT), + * which behaves as a Physically Indexed, Physically + * Tagged (PIPT) 4-way set-associative L1 data cache. * - Fixed cache line length of 64 bytes. * - Pseudo-LRU cache replacement policy. * * A7.1 About the L2 memory system * The L2 memory subsystem consist of: - * - An 8-way set associative L2 cache with a configurable size of 128KB, 256KB or 512KB. - * Cache lines have a fixed length of 64 bytes. - * - Strictly inclusive with L1 data cache. Weakly inclusive with L1 instruction cache. + * - An 8-way set associative L2 cache with a + * configurable size of 128KB, 256KB or 512KB. Cache + * lines have a fixed length of 64 bytes. + * - Strictly inclusive with L1 data cache. Weakly + * inclusive with L1 instruction cache. * - Dynamic biased replacement policy. - * - Modified Exclusive Shared Invalid (MESI) coherency. + * - Modified Exclusive Shared Invalid (MESI) + * coherency. * * +--------------------+-------+-----------+-----------+-----------+----------+------------+ - * | Processor model | Cores | L1D cache | L1I cache | L2 cache | L3 cache | Reference | + * | Processor model | Cores | L1D cache | L1I cache + * | L2 cache | L3 cache | Reference | * +--------------------+-------+-----------+-----------+-----------+----------+------------+ - * | Kirin 980 | 4(+4) | 64K | 64K | 512K | 4M | [1], [2] | + * | Kirin 980 | 4(+4) | 64K | 64K | + * 512K | 4M | [1], [2] | * +--------------------+-------+-----------+-----------+-----------+----------+------------+ * - * [1] https://www.anandtech.com/show/13298/hisilicon-announces-the-kirin-980-first-a76-g76-on-7nm + * [1] + * https://www.anandtech.com/show/13298/hisilicon-announces-the-kirin-980-first-a76-g76-on-7nm * [2] https://en.wikichip.org/wiki/hisilicon/kirin/980 */ uint32_t l2_size = 256 * 1024; uint32_t l3_size = 1024 * 1024; switch (chipset->series) { case cpuinfo_arm_chipset_series_hisilicon_kirin: - /* Kirin 980: 512K L2 cache + 4M L3 cache */ + /* Kirin 980: 512K L2 cache + 4M L3 + * cache */ if (chipset->model == 980) { l2_size = 512 * 1024; l3_size = 4 * 1024 * 1024; @@ -1164,74 +1226,81 @@ void cpuinfo_arm_decode_cache( default: break; } - *l1i = (struct cpuinfo_cache) { + *l1i = (struct cpuinfo_cache){ .size = 64 * 1024, .associativity = 4, .line_size = 64, }; - *l1d = (struct cpuinfo_cache) { + *l1d = (struct cpuinfo_cache){ .size = 64 * 1024, .associativity = 4, .line_size = 64, }; - *l2 = (struct cpuinfo_cache) { + *l2 = (struct cpuinfo_cache){ .size = l2_size, .associativity = 8, .line_size = 64, .flags = CPUINFO_CACHE_INCLUSIVE, }; - *l3 = (struct cpuinfo_cache) { + *l3 = (struct cpuinfo_cache){ .size = l3_size, .associativity = 16, .line_size = 64, }; break; } - case cpuinfo_uarch_cortex_a77: - { + case cpuinfo_uarch_cortex_a77: { /* * ARM Cortex-A77 Core Technical Reference Manual * A6.1. About the L1 memory system - * The L1 memory system consists of separate instruction and data caches. Both have a fixed size of 64KB. + * The L1 memory system consists of separate + * instruction and data caches. Both have a fixed size + * of 64KB. * * A6.1.1 L1 instruction-side memory system - * The L1 instruction memory system has the following key features: - * - Virtually Indexed, Physically Tagged (VIPT), which behaves as a Physically Indexed, - * Physically Tagged (PIPT) 4-way set-associative L1 data cache. + * The L1 instruction memory system has the following + * key features: + * - Virtually Indexed, Physically Tagged (VIPT), + * which behaves as a Physically Indexed, Physically + * Tagged (PIPT) 4-way set-associative L1 data cache. * - Fixed cache line length of 64 bytes. * * A6.1.2 L1 data-side memory system - * The L1 data memory system has the following features: - * - Virtually Indexed, Physically Tagged (VIPT), which behaves as a Physically Indexed, - * Physically Tagged (PIPT) 4-way set-associative L1 data cache. + * The L1 data memory system has the following + * features: + * - Virtually Indexed, Physically Tagged (VIPT), + * which behaves as a Physically Indexed, Physically + * Tagged (PIPT) 4-way set-associative L1 data cache. * - Fixed cache line length of 64 bytes. * - Pseudo-LRU cache replacement policy. * * A7.1 About the L2 memory system * The L2 memory subsystem consist of: - * - An 8-way set associative L2 cache with a configurable size of 128KB, 256KB or 512KB. Cache lines - * have a fixed length of 64 bytes. - * - Strictly inclusive with L1 data cache. Weakly inclusive with L1 instruction cache. + * - An 8-way set associative L2 cache with a + * configurable size of 128KB, 256KB or 512KB. Cache + * lines have a fixed length of 64 bytes. + * - Strictly inclusive with L1 data cache. Weakly + * inclusive with L1 instruction cache. */ const uint32_t l2_size = 256 * 1024; const uint32_t l3_size = 1024 * 1024; - *l1i = (struct cpuinfo_cache) { + *l1i = (struct cpuinfo_cache){ .size = 64 * 1024, .associativity = 4, .line_size = 64, }; - *l1d = (struct cpuinfo_cache) { + *l1d = (struct cpuinfo_cache){ .size = 64 * 1024, .associativity = 4, .line_size = 64, }; - *l2 = (struct cpuinfo_cache) { + *l2 = (struct cpuinfo_cache){ .size = l2_size, .associativity = 8, .line_size = 64, .flags = CPUINFO_CACHE_INCLUSIVE, }; - *l3 = (struct cpuinfo_cache) { + *l3 = (struct cpuinfo_cache){ .size = l3_size, .associativity = 16, .line_size = 64, @@ -1241,48 +1310,57 @@ void cpuinfo_arm_decode_cache( case cpuinfo_uarch_neoverse_n1: case cpuinfo_uarch_neoverse_v1: case cpuinfo_uarch_neoverse_n2: - case cpuinfo_uarch_neoverse_v2: - { + case cpuinfo_uarch_neoverse_v2: { /* - * The specifications here below are taken from the - * Arm Core Technical Reference Manuals for - * - Neoverse N1: https://developer.arm.com/documentation/100616/0401/?lang=en - * - Neoverse N2: https://developer.arm.com/documentation/102099/0003/?lang=en - * - Neoverse V1: https://developer.arm.com/documentation/101427/0102/?lang=en - * - Neoverse V2: https://developer.arm.com/documentation/102375/0002/?lang=en - * - * All four Arm architectures have L1 memory system with instruction and data caches, - * both of fixed size of 64KB. The instruction side memory system is 4-way set associative - * with a cache line length of 64 bytes. The data cache is also 4-way set associative with - * a cache line length of 64 bytes. - * - * The L2 memory system differs across the four Architectures in the minimum - * length of the L2 cache. Namely: - * - Arm Neoverse N1/N2/V1 have a L2 cache of configurable size of 256KB, 512KB, or 1024KB - * - Arm Neoverse V2 has a L2 cache of configurable size of 1MB or 2MB - * For all four architectures, the L2 cache is 8-way set associative - * For all other information, please refer to the technical manuals linked above - */ + * The specifications here below are taken from the + * Arm Core Technical Reference Manuals for + * - Neoverse N1: + * https://developer.arm.com/documentation/100616/0401/?lang=en + * - Neoverse N2: + * https://developer.arm.com/documentation/102099/0003/?lang=en + * - Neoverse V1: + * https://developer.arm.com/documentation/101427/0102/?lang=en + * - Neoverse V2: + * https://developer.arm.com/documentation/102375/0002/?lang=en + * + * All four Arm architectures have L1 memory system with + * instruction and data caches, both of fixed size of + * 64KB. The instruction side memory system is 4-way set + * associative with a cache line length of 64 bytes. The + * data cache is also 4-way set associative with a cache + * line length of 64 bytes. + * + * The L2 memory system differs across the four + * Architectures in the minimum length of the L2 cache. + * Namely: + * - Arm Neoverse N1/N2/V1 have a L2 cache of + * configurable size of 256KB, 512KB, or 1024KB + * - Arm Neoverse V2 has a L2 cache of configurable + * size of 1MB or 2MB For all four architectures, the L2 + * cache is 8-way set associative For all other + * information, please refer to the technical manuals + * linked above + */ const uint32_t min_l2_size_KB = uarch == cpuinfo_uarch_neoverse_v2 ? 1024 : 256; const uint32_t min_l3_size_KB = 0; - *l1i = (struct cpuinfo_cache) { + *l1i = (struct cpuinfo_cache){ .size = 64 * 1024, .associativity = 4, .line_size = 64, }; - *l1d = (struct cpuinfo_cache) { + *l1d = (struct cpuinfo_cache){ .size = 64 * 1024, .associativity = 4, .line_size = 64, }; - *l2 = (struct cpuinfo_cache) { + *l2 = (struct cpuinfo_cache){ .size = min_l2_size_KB * 1024, .associativity = 8, .line_size = 64, .flags = CPUINFO_CACHE_INCLUSIVE, }; - *l3 = (struct cpuinfo_cache) { + *l3 = (struct cpuinfo_cache){ .size = min_l3_size_KB * 1024, .associativity = 16, .line_size = 64, @@ -1292,37 +1370,29 @@ void cpuinfo_arm_decode_cache( #if CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_8A__) case cpuinfo_uarch_scorpion: /* - * - "The CPU includes 32KB instruction and data caches as - * well as a complete memory-management unit (MMU) suitable - * for high-level operating systems. The CPU also has - * 256KB of SRAM that can be allocated in 64KB increments - * to level-two (L2) cache or tightly coupled memory (TCM)." [1] - * We interpret it as L2 cache being 4-way set-associative on single-core Scorpion. + * - "The CPU includes 32KB instruction and data caches + * as well as a complete memory-management unit (MMU) + * suitable for high-level operating systems. The CPU + * also has 256KB of SRAM that can be allocated in 64KB + * increments to level-two (L2) cache or tightly coupled + * memory (TCM)." [1] We interpret it as L2 cache being + * 4-way set-associative on single-core Scorpion. * - L1 Data Cache = 32 KB. 32 B/line. [2] - * - L2 Cache = 256 KB. 128 B/line. [2] - * - 256 KB (single-core) or 512 KB (dual-core) L2 cache [3] + * - L2 Cache = 256 KB. 128 B/line. [2] + * - 256 KB (single-core) or 512 KB (dual-core) L2 cache + * [3] * - Single or dual-core configuration [3] * - For L1 cache assume the same associativity as Krait * - * [1] https://www.qualcomm.com/media/documents/files/linley-report-on-dual-core-snapdragon.pdf + * [1] + * https://www.qualcomm.com/media/documents/files/linley-report-on-dual-core-snapdragon.pdf * [2] http://www.7-cpu.com/cpu/Snapdragon.html * [3] https://en.wikipedia.org/wiki/Scorpion_(CPU) */ - *l1i = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 4, - .line_size = 32 - }; - *l1d = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 4, - .line_size = 32 - }; - *l2 = (struct cpuinfo_cache) { - .size = cluster_cores * 256 * 1024, - .associativity = 4, - .line_size = 128 - }; + *l1i = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 32}; + *l1d = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 32}; + *l2 = (struct cpuinfo_cache){ + .size = cluster_cores * 256 * 1024, .associativity = 4, .line_size = 128}; break; case cpuinfo_uarch_krait: /* @@ -1330,155 +1400,141 @@ void cpuinfo_arm_decode_cache( * - L0 Instruction cache = 4 KB. [1] * - L1 Data cache = 16 KB. 64 B/line, 4-way [1] * - L1 Instruction cache = 16 KB, 4-way [1] - * - L2 Cache = 1 MB, 128 B/line, 8-way. Each core has fast access only to 512 KB of L2 cache. [1] - * - L2 = 1MB (dual core) or 2MB (quad core), 8-way set associative [2] + * - L2 Cache = 1 MB, 128 B/line, 8-way. Each core has + * fast access only to 512 KB of L2 cache. [1] + * - L2 = 1MB (dual core) or 2MB (quad core), 8-way set + * associative [2] * * [1] http://www.7-cpu.com/cpu/Krait.html - * [2] http://www.anandtech.com/show/4940/qualcomm-new-snapdragon-s4-msm8960-krait-architecture/2 + * [2] + * http://www.anandtech.com/show/4940/qualcomm-new-snapdragon-s4-msm8960-krait-architecture/2 */ - *l1i = (struct cpuinfo_cache) { - .size = 16 * 1024, - .associativity = 4, - .line_size = 64 /* assume same as L1D */ - }; - *l1d = (struct cpuinfo_cache) { - .size = 16 * 1024, - .associativity = 4, - .line_size = 64 - }; - *l2 = (struct cpuinfo_cache) { - .size = cluster_cores * 512 * 1024, - .associativity = 8, - .line_size = 128 + *l1i = (struct cpuinfo_cache){ + .size = 16 * 1024, .associativity = 4, .line_size = 64 /* assume same as L1D */ }; + *l1d = (struct cpuinfo_cache){.size = 16 * 1024, .associativity = 4, .line_size = 64}; + *l2 = (struct cpuinfo_cache){ + .size = cluster_cores * 512 * 1024, .associativity = 8, .line_size = 128}; break; #endif /* CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_8A__) */ case cpuinfo_uarch_kryo: /* * +-----------------+-------+-----------+-----------+-----------+-----------+ - * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference | + * | Processor model | Cores | L1D cache | L1I cache | + * L2 cache | Reference | * +-----------------+-------+-----------+-----------+-----------+-----------+ - * | Snapdragon 820 | 2+2 | 24K | 32K | 1M+512K | [1, 2] | - * | Snapdragon 821 | 2+2 | ? | ? | 1M+512K | [1] | + * | Snapdragon 820 | 2+2 | 24K | 32K | + * 1M+512K | [1, 2] | | Snapdragon 821 | 2+2 | ? + * | ? | 1M+512K | [1] | * +-----------------+-------+-----------+-----------+-----------+-----------+ * - * [1] http://www.anandtech.com/show/9837/snapdragon-820-preview/2 - * [2] https://www.inforcecomputing.com/public_docs/Inforce6601/Inforce_6601_Micro-SOM_FAQs_04-2016-1.pdf + * [1] + * http://www.anandtech.com/show/9837/snapdragon-820-preview/2 + * [2] + * https://www.inforcecomputing.com/public_docs/Inforce6601/Inforce_6601_Micro-SOM_FAQs_04-2016-1.pdf */ - *l1i = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 4, - .line_size = 64 - }; - *l1d = (struct cpuinfo_cache) { - .size = 24 * 1024, - .associativity = 3, - .line_size = 64 - }; + *l1i = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 64}; + *l1d = (struct cpuinfo_cache){.size = 24 * 1024, .associativity = 3, .line_size = 64}; if (midr_is_kryo_silver(midr)) { /* Kryo "Silver" */ - *l2 = (struct cpuinfo_cache) { - .size = 512 * 1024, - .associativity = 8, - .line_size = 128 - }; + *l2 = (struct cpuinfo_cache){.size = 512 * 1024, .associativity = 8, .line_size = 128}; } else { /* Kryo "Gold" */ - *l2 = (struct cpuinfo_cache) { - .size = 1024 * 1024, - .associativity = 8, - .line_size = 128 - }; + *l2 = (struct cpuinfo_cache){.size = 1024 * 1024, .associativity = 8, .line_size = 128}; } break; case cpuinfo_uarch_denver: case cpuinfo_uarch_denver2: /* - * The Denver chip includes a 128KB, 4-way level 1 instruction cache, a 64KB, 4-way level 2 data cache, - * and a 2MB, 16-way level 2 cache, all of which can service both cores. [1] + * The Denver chip includes a 128KB, 4-way level 1 + * instruction cache, a 64KB, 4-way level 2 data cache, + * and a 2MB, 16-way level 2 cache, all of which can + * service both cores. [1] * * All the caches have 64-byte lines. [2] * - * [1] http://www.pcworld.com/article/2463900/nvidia-reveals-pc-like-performance-for-denver-tegra-k1.html - * [2] http://linleygroup.com/newsletters/newsletter_detail.php?num=5205&year=2014 + * [1] + * http://www.pcworld.com/article/2463900/nvidia-reveals-pc-like-performance-for-denver-tegra-k1.html + * [2] + * http://linleygroup.com/newsletters/newsletter_detail.php?num=5205&year=2014 */ - *l1i = (struct cpuinfo_cache) { - .size = 128 * 1024, - .associativity = 4, - .line_size = 64 - }; - *l1d = (struct cpuinfo_cache) { - .size = 64 * 1024, - .associativity = 4, - .line_size = 64 - }; - *l2 = (struct cpuinfo_cache) { - .size = 2 * 1024 * 1024, - .associativity = 16, - .line_size = 64 - }; + *l1i = (struct cpuinfo_cache){.size = 128 * 1024, .associativity = 4, .line_size = 64}; + *l1d = (struct cpuinfo_cache){.size = 64 * 1024, .associativity = 4, .line_size = 64}; + *l2 = (struct cpuinfo_cache){.size = 2 * 1024 * 1024, .associativity = 16, .line_size = 64}; break; case cpuinfo_uarch_exynos_m1: case cpuinfo_uarch_exynos_m2: /* - * - "Moving past branch prediction we can see some elements of how the cache is set up for the L1 I$, - * namely 64 KB split into four sets with 128-byte line sizes for 128 cache lines per set" [1] - * - "For loads and stores, a 32 KB, 8-way set associative cache with 64 byte line size is used" [1] - * - "The L2 cache here is 2MB shared across all cores split into 16 sets. This memory is also split - * into 4 banks and has a 22 cycle latency" [1] + * - "Moving past branch prediction we can see some + * elements of how the cache is set up for the L1 I$, + * namely 64 KB split into four sets with 128-byte line + * sizes for 128 cache lines per set" [1] + * - "For loads and stores, a 32 KB, 8-way set + * associative cache with 64 byte line size is used" [1] + * - "The L2 cache here is 2MB shared across all cores + * split into 16 sets. This memory is also split into 4 + * banks and has a 22 cycle latency" [1] * * +--------------------+-------+-----------+-----------+-----------+-----------+ - * | Processor model | Cores | L1D cache | L1I cache | L2 cache | Reference | + * | Processor model | Cores | L1D cache | L1I cache + * | L2 cache | Reference | * +--------------------+-------+-----------+-----------+-----------+-----------+ - * | Exynos 8 Octa 8890 | 4(+4) | 64K | 32K | 2M | [1] | - * | Exynos 8 Octa 8895 | 4(+4) | 64K | 32K | 2M | [2] | + * | Exynos 8 Octa 8890 | 4(+4) | 64K | 32K | + * 2M | [1] | | Exynos 8 Octa 8895 | 4(+4) | 64K + * | 32K | 2M | [2] | * +--------------------+-------+-----------+-----------+-----------+-----------+ * - * [1] http://www.anandtech.com/show/10590/hot-chips-2016-exynos-m1-architecture-disclosed - * [2] https://www.extremetech.com/mobile/244949-samsungs-exynos-8895-features-custom-cpu-cores-first-10nm-chip-market + * [1] + * http://www.anandtech.com/show/10590/hot-chips-2016-exynos-m1-architecture-disclosed + * [2] + * https://www.extremetech.com/mobile/244949-samsungs-exynos-8895-features-custom-cpu-cores-first-10nm-chip-market */ - *l1i = (struct cpuinfo_cache) { - .size = 64 * 1024, - .associativity = 4, - .line_size = 128 - }; - *l1d = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 8, - .line_size = 64 - }; - *l2 = (struct cpuinfo_cache) { - .size = 2 * 1024 * 1024, - .associativity = 16, - .line_size = 64 - }; + *l1i = (struct cpuinfo_cache){.size = 64 * 1024, .associativity = 4, .line_size = 128}; + *l1d = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 8, .line_size = 64}; + *l2 = (struct cpuinfo_cache){.size = 2 * 1024 * 1024, .associativity = 16, .line_size = 64}; break; case cpuinfo_uarch_exynos_m3: /* * +--------------------+-------+-----------+-----------+-----------+----------+------------+ - * | Processor model | Cores | L1D cache | L1I cache | L2 cache | L3 cache | Reference | + * | Processor model | Cores | L1D cache | L1I cache + * | L2 cache | L3 cache | Reference | * +--------------------+-------+-----------+-----------+-----------+----------+------------+ - * | Exynos 9810 | 4(+4) | 64K | ? | 512K | 4M | [1] | + * | Exynos 9810 | 4(+4) | 64K | ? | + * 512K | 4M | [1] | * +--------------------+-------+-----------+-----------+-----------+----------+------------+ * - * [1] https://www.anandtech.com/show/12478/exynos-9810-handson-awkward-first-results + * [1] + * https://www.anandtech.com/show/12478/exynos-9810-handson-awkward-first-results */ - *l1i = (struct cpuinfo_cache) { - .size = 64 * 1024 /* assume same as in Exynos M1/M2 cores */, - .associativity = 4 /* assume same as in Exynos M1/M2 cores */, - .line_size = 128 /* assume same as in Exynos M1/M2 cores */ - }; - *l1d = (struct cpuinfo_cache) { + *l1i = (struct cpuinfo_cache){ + .size = 64 * 1024 /* assume same as in Exynos + M1/M2 cores */ + , + .associativity = 4 /* assume same as in Exynos + M1/M2 cores */ + , + .line_size = 128 /* assume same as in Exynos + M1/M2 cores */ + }; + *l1d = (struct cpuinfo_cache){ .size = 64 * 1024, - .associativity = 8 /* assume same as in Exynos M1/M2 cores */, - .line_size = 64 /* assume same as in Exynos M1/M2 cores */, - }; - *l2 = (struct cpuinfo_cache) { + .associativity = 8 /* assume same as in Exynos + M1/M2 cores */ + , + .line_size = 64 /* assume same as in Exynos + M1/M2 cores */ + , + }; + *l2 = (struct cpuinfo_cache){ .size = 512 * 1024, - .associativity = 16 /* assume same as in Exynos M1/M2 cores */, - .line_size = 64 /* assume same as in Exynos M1/M2 cores */, - }; - *l3 = (struct cpuinfo_cache) { + .associativity = 16 /* assume same as in Exynos + M1/M2 cores */ + , + .line_size = 64 /* assume same as in Exynos + M1/M2 cores */ + , + }; + *l3 = (struct cpuinfo_cache){ .size = 4 * 1024 * 1024, .associativity = 16 /* assume DynamIQ cache */, .line_size = 64 /* assume DynamIQ cache */, @@ -1487,21 +1543,19 @@ void cpuinfo_arm_decode_cache( #if CPUINFO_ARCH_ARM64 && !defined(__ANDROID__) case cpuinfo_uarch_thunderx: /* - * "78K-Icache and 32K-D cache per core, 16 MB shared L2 cache" [1] + * "78K-Icache and 32K-D cache per core, 16 MB shared L2 + * cache" [1] * - * [1] https://www.cavium.com/pdfFiles/ThunderX_CP_PB_Rev1.pdf + * [1] + * https://www.cavium.com/pdfFiles/ThunderX_CP_PB_Rev1.pdf */ - *l1i = (struct cpuinfo_cache) { - .size = 78 * 1024, - .associativity = 4 /* assumption */, - .line_size = 64 /* assumption */ + *l1i = (struct cpuinfo_cache){ + .size = 78 * 1024, .associativity = 4 /* assumption */, .line_size = 64 /* assumption */ }; - *l1d = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 4 /* assumption */, - .line_size = 64 /* assumption */ + *l1d = (struct cpuinfo_cache){ + .size = 32 * 1024, .associativity = 4 /* assumption */, .line_size = 64 /* assumption */ }; - *l2 = (struct cpuinfo_cache) { + *l2 = (struct cpuinfo_cache){ .size = 16 * 1024 * 1024, .associativity = 8 /* assumption */, .line_size = 64 /* assumption */ @@ -1509,40 +1563,50 @@ void cpuinfo_arm_decode_cache( break; case cpuinfo_uarch_taishan_v110: /* - * It features private 64 KiB L1 instruction and data caches as well as 512 KiB of private L2. [1] + * It features private 64 KiB L1 instruction and data + * caches as well as 512 KiB of private L2. [1] * * +------------------+-------+-----------+-----------+-----------+----------+-----------+ - * | Processor model | Cores | L1D cache | L1I cache | L2 cache | L3 cache | Reference | + * | Processor model | Cores | L1D cache | L1I cache | + * L2 cache | L3 cache | Reference | * +------------------+-------+-----------+-----------+-----------+----------+-----------+ - * | Kunpeng 920-3226 | 32 | 64K | 64K | 512K | 32M | [2] | + * | Kunpeng 920-3226 | 32 | 64K | 64K | + * 512K | 32M | [2] | * +------------------+-------+-----------+-----------+-----------+----------+-----------+ - * | Kunpeng 920-4826 | 48 | 64K | 64K | 512K | 48M | [3] | + * | Kunpeng 920-4826 | 48 | 64K | 64K | + * 512K | 48M | [3] | * +------------------+-------+-----------+-----------+-----------+----------+-----------+ - * | Kunpeng 920-6426 | 64 | 64K | 64K | 512K | 64M | [4] | + * | Kunpeng 920-6426 | 64 | 64K | 64K | + * 512K | 64M | [4] | * +------------------+-------+-----------+-----------+-----------+----------+-----------+ * - * [1] https://en.wikichip.org/wiki/hisilicon/microarchitectures/taishan_v110 - * [2] https://en.wikichip.org/wiki/hisilicon/kunpeng/920-3226 - * [3] https://en.wikichip.org/wiki/hisilicon/kunpeng/920-4826 - * [4] https://en.wikichip.org/wiki/hisilicon/kunpeng/920-6426 + * [1] + * https://en.wikichip.org/wiki/hisilicon/microarchitectures/taishan_v110 + * [2] + * https://en.wikichip.org/wiki/hisilicon/kunpeng/920-3226 + * [3] + * https://en.wikichip.org/wiki/hisilicon/kunpeng/920-4826 + * [4] + * https://en.wikichip.org/wiki/hisilicon/kunpeng/920-6426 */ - *l1i = (struct cpuinfo_cache) { + *l1i = (struct cpuinfo_cache){ .size = 64 * 1024, .associativity = 4 /* assumption */, .line_size = 128 /* assumption */, }; - *l1d = (struct cpuinfo_cache) { + *l1d = (struct cpuinfo_cache){ .size = 64 * 1024, .associativity = 4 /* assumption */, .line_size = 128 /* assumption */, }; - *l2 = (struct cpuinfo_cache) { + *l2 = (struct cpuinfo_cache){ .size = 512 * 1024, .associativity = 8 /* assumption */, .line_size = 128 /* assumption */, - .flags = CPUINFO_CACHE_INCLUSIVE /* assumption */, + .flags = CPUINFO_CACHE_INCLUSIVE /* assumption */ + , }; - *l3 = (struct cpuinfo_cache) { + *l3 = (struct cpuinfo_cache){ .size = cluster_cores * 1024 * 1024, .associativity = 16 /* assumption */, .line_size = 128 /* assumption */, @@ -1555,38 +1619,18 @@ void cpuinfo_arm_decode_cache( cpuinfo_log_warning("target uarch not recognized; using generic cache parameters"); /* Follow OpenBLAS */ if (arch_version >= 8) { - *l1i = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 4, - .line_size = 64 - }; - *l1d = (struct cpuinfo_cache) { - .size = 32 * 1024, - .associativity = 4, - .line_size = 64 - }; - *l2 = (struct cpuinfo_cache) { - .size = cluster_cores * 256 * 1024, - .associativity = 8, - .line_size = 64 - }; + *l1i = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 64}; + *l1d = (struct cpuinfo_cache){.size = 32 * 1024, .associativity = 4, .line_size = 64}; + *l2 = (struct cpuinfo_cache){ + .size = cluster_cores * 256 * 1024, .associativity = 8, .line_size = 64}; } else { - *l1i = (struct cpuinfo_cache) { - .size = 16 * 1024, - .associativity = 4, - .line_size = 32 - }; - *l1d = (struct cpuinfo_cache) { - .size = 16 * 1024, - .associativity = 4, - .line_size = 32 - }; + *l1i = (struct cpuinfo_cache){.size = 16 * 1024, .associativity = 4, .line_size = 32}; + *l1d = (struct cpuinfo_cache){.size = 16 * 1024, .associativity = 4, .line_size = 32}; if (arch_version >= 7) { - *l2 = (struct cpuinfo_cache) { + *l2 = (struct cpuinfo_cache){ .size = cluster_cores * 128 * 1024, .associativity = 8, - .line_size = 32 - }; + .line_size = 32}; } } break; @@ -1607,8 +1651,9 @@ void cpuinfo_arm_decode_cache( uint32_t cpuinfo_arm_compute_max_cache_size(const struct cpuinfo_processor* processor) { /* - * There is no precise way to detect cache size on ARM/ARM64, and cache size reported by cpuinfo - * may underestimate the actual cache size. Thus, we use microarchitecture-specific maximum. + * There is no precise way to detect cache size on ARM/ARM64, and cache + * size reported by cpuinfo may underestimate the actual cache size. + * Thus, we use microarchitecture-specific maximum. */ switch (processor->core->uarch) { case cpuinfo_uarch_xscale: @@ -1630,7 +1675,8 @@ uint32_t cpuinfo_arm_compute_max_cache_size(const struct cpuinfo_processor* proc * 7.1. About the L2 Memory system * The L2 memory system consists of an: * - Optional tightly-coupled L2 cache that includes: - * - Configurable L2 cache size of 128KB, 256KB, 512KB, and 1MB. + * - Configurable L2 cache size of 128KB, 256KB, + * 512KB, and 1MB. */ return 1024 * 1024; case cpuinfo_uarch_cortex_a8: @@ -1638,7 +1684,8 @@ uint32_t cpuinfo_arm_compute_max_cache_size(const struct cpuinfo_processor* proc * Cortex-A8 Technical Reference Manual: * 8.1. About the L2 memory system * The key features of the L2 memory system include: - * - configurable cache size of 0KB, 128KB, 256KB, 512KB, and 1MB + * - configurable cache size of 0KB, 128KB, 256KB, + * 512KB, and 1MB */ return 1024 * 1024; case cpuinfo_uarch_cortex_a9: @@ -1647,19 +1694,21 @@ uint32_t cpuinfo_arm_compute_max_cache_size(const struct cpuinfo_processor* proc case cpuinfo_uarch_cortex_a12: case cpuinfo_uarch_cortex_a17: /* - * ARM Cortex-A17 MPCore Processor Technical Reference Manual: - * 7.1. About the L2 Memory system - * The key features of the L2 memory system include: + * ARM Cortex-A17 MPCore Processor Technical Reference + * Manual: 7.1. About the L2 Memory system The key + * features of the L2 memory system include: * - An integrated L2 cache: - * - The cache size is implemented as either 256KB, 512KB, 1MB, 2MB, 4MB or 8MB. + * - The cache size is implemented as either 256KB, + * 512KB, 1MB, 2MB, 4MB or 8MB. */ return 8 * 1024 * 1024; case cpuinfo_uarch_cortex_a15: /* - * ARM Cortex-A15 MPCore Processor Technical Reference Manual: - * 7.1. About the L2 memory system - * The features of the L2 memory system include: - * - Configurable L2 cache size of 512KB, 1MB, 2MB and 4MB. + * ARM Cortex-A15 MPCore Processor Technical Reference + * Manual: 7.1. About the L2 memory system The features + * of the L2 memory system include: + * - Configurable L2 cache size of 512KB, 1MB, 2MB + * and 4MB. */ return 4 * 1024 * 1024; case cpuinfo_uarch_cortex_a35: @@ -1668,41 +1717,46 @@ uint32_t cpuinfo_arm_compute_max_cache_size(const struct cpuinfo_processor* proc * 7.1 About the L2 memory system * L2 cache * - Further features of the L2 cache are: - * - Configurable size of 128KB, 256KB, 512KB, and 1MB. + * - Configurable size of 128KB, 256KB, 512KB, and + * 1MB. */ return 1024 * 1024; case cpuinfo_uarch_cortex_a53: /* - * ARM Cortex-A53 MPCore Processor Technical Reference Manual: - * 7.1. About the L2 memory system - * The L2 memory system consists of an: + * ARM Cortex-A53 MPCore Processor Technical Reference + * Manual: 7.1. About the L2 memory system The L2 memory + * system consists of an: * - Optional tightly-coupled L2 cache that includes: - * - Configurable L2 cache size of 128KB, 256KB, 512KB, 1MB and 2MB. + * - Configurable L2 cache size of 128KB, 256KB, + * 512KB, 1MB and 2MB. */ return 2 * 1024 * 1024; case cpuinfo_uarch_cortex_a57: /* - * ARM Cortex-A57 MPCore Processor Technical Reference Manual: - * 7.1 About the L2 memory system - * The features of the L2 memory system include: - * - Configurable L2 cache size of 512KB, 1MB, and 2MB. + * ARM Cortex-A57 MPCore Processor Technical Reference + * Manual: 7.1 About the L2 memory system The features + * of the L2 memory system include: + * - Configurable L2 cache size of 512KB, 1MB, and + * 2MB. */ return 2 * 1024 * 1024; case cpuinfo_uarch_cortex_a72: /* - * ARM Cortex-A72 MPCore Processor Technical Reference Manual: - * 7.1 About the L2 memory system - * The features of the L2 memory system include: - * - Configurable L2 cache size of 512KB, 1MB, 2MB and 4MB. + * ARM Cortex-A72 MPCore Processor Technical Reference + * Manual: 7.1 About the L2 memory system The features + * of the L2 memory system include: + * - Configurable L2 cache size of 512KB, 1MB, 2MB + * and 4MB. */ return 4 * 1024 * 1024; case cpuinfo_uarch_cortex_a73: /* - * ARM Cortex‑A73 MPCore Processor Technical Reference Manual - * 7.1 About the L2 memory system - * The L2 memory system consists of: + * ARM Cortex‑A73 MPCore Processor Technical Reference + * Manual 7.1 About the L2 memory system The L2 memory + * system consists of: * - A tightly-integrated L2 cache with: - * - A configurable size of 256KB, 512KB, 1MB, 2MB, 4MB, or 8MB. + * - A configurable size of 256KB, 512KB, 1MB, + * 2MB, 4MB, or 8MB. */ return 8 * 1024 * 1024; case cpuinfo_uarch_cortex_a55: diff --git a/src/arm/linux/aarch32-isa.c b/src/arm/linux/aarch32-isa.c index 65c7826f..bd5020c7 100644 --- a/src/arm/linux/aarch32-isa.c +++ b/src/arm/linux/aarch32-isa.c @@ -1,29 +1,27 @@ #include #if CPUINFO_MOCK - #include +#include #endif #include #include #include #include - #if CPUINFO_MOCK - uint32_t cpuinfo_arm_fpsid = 0; - uint32_t cpuinfo_arm_mvfr0 = 0; - uint32_t cpuinfo_arm_wcid = 0; +uint32_t cpuinfo_arm_fpsid = 0; +uint32_t cpuinfo_arm_mvfr0 = 0; +uint32_t cpuinfo_arm_wcid = 0; - void cpuinfo_set_fpsid(uint32_t fpsid) { - cpuinfo_arm_fpsid = fpsid; - } +void cpuinfo_set_fpsid(uint32_t fpsid) { + cpuinfo_arm_fpsid = fpsid; +} - void cpuinfo_set_wcid(uint32_t wcid) { - cpuinfo_arm_wcid = wcid; - } +void cpuinfo_set_wcid(uint32_t wcid) { + cpuinfo_arm_wcid = wcid; +} #endif - void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( uint32_t features, uint32_t features2, @@ -31,27 +29,27 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( uint32_t architecture_version, uint32_t architecture_flags, const struct cpuinfo_arm_chipset chipset[restrict static 1], - struct cpuinfo_arm_isa isa[restrict static 1]) -{ + struct cpuinfo_arm_isa isa[restrict static 1]) { if (architecture_version < 8) { - const uint32_t armv8_features2_mask = CPUINFO_ARM_LINUX_FEATURE2_AES | CPUINFO_ARM_LINUX_FEATURE2_PMULL | - CPUINFO_ARM_LINUX_FEATURE2_SHA1 | CPUINFO_ARM_LINUX_FEATURE2_SHA2 | CPUINFO_ARM_LINUX_FEATURE2_CRC32; + const uint32_t armv8_features2_mask = CPUINFO_ARM_LINUX_FEATURE2_AES | + CPUINFO_ARM_LINUX_FEATURE2_PMULL | CPUINFO_ARM_LINUX_FEATURE2_SHA1 | + CPUINFO_ARM_LINUX_FEATURE2_SHA2 | CPUINFO_ARM_LINUX_FEATURE2_CRC32; if (features2 & armv8_features2_mask) { architecture_version = 8; } } if (architecture_version >= 8) { /* - * ARMv7 code running on ARMv8: IDIV, VFP, NEON are always supported, - * but may be not reported in /proc/cpuinfo features. + * ARMv7 code running on ARMv8: IDIV, VFP, NEON are always + * supported, but may be not reported in /proc/cpuinfo features. */ - isa->armv5e = true; - isa->armv6 = true; - isa->armv6k = true; - isa->armv7 = true; + isa->armv5e = true; + isa->armv6 = true; + isa->armv6k = true; + isa->armv7 = true; isa->armv7mp = true; - isa->armv8 = true; - isa->thumb = true; + isa->armv8 = true; + isa->thumb = true; isa->thumb2 = true; isa->idiv = true; isa->vfpv3 = true; @@ -61,8 +59,10 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( isa->neon = true; /* - * NEON FP16 compute extension and VQRDMLAH/VQRDMLSH instructions are not indicated in /proc/cpuinfo. - * Use a MIDR-based heuristic to whitelist processors known to support it: + * NEON FP16 compute extension and VQRDMLAH/VQRDMLSH + * instructions are not indicated in /proc/cpuinfo. Use a + * MIDR-based heuristic to whitelist processors known to support + * it: * - Processors with Cortex-A55 cores * - Processors with Cortex-A75 cores * - Processors with Cortex-A76 cores @@ -82,8 +82,10 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( * - Neoverse V2 cores */ if (chipset->series == cpuinfo_arm_chipset_series_samsung_exynos && chipset->model == 9810) { - /* Only little cores of Exynos 9810 support FP16 & RDM */ - cpuinfo_log_warning("FP16 arithmetics and RDM disabled: only little cores in Exynos 9810 support these extensions"); + /* Only little cores of Exynos 9810 support FP16 & RDM + */ + cpuinfo_log_warning( + "FP16 arithmetics and RDM disabled: only little cores in Exynos 9810 support these extensions"); } else { switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) { case UINT32_C(0x4100D050): /* Cortex-A55 */ @@ -102,11 +104,16 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( case UINT32_C(0x4100D4D0): /* Cortex-A715 */ case UINT32_C(0x4100D4E0): /* Cortex-X3 */ case UINT32_C(0x4100D4F0): /* Neoverse V2 */ - case UINT32_C(0x4800D400): /* Cortex-A76 (HiSilicon) */ - case UINT32_C(0x51008020): /* Kryo 385 Gold (Cortex-A75) */ - case UINT32_C(0x51008030): /* Kryo 385 Silver (Cortex-A55) */ - case UINT32_C(0x51008040): /* Kryo 485 Gold (Cortex-A76) */ - case UINT32_C(0x51008050): /* Kryo 485 Silver (Cortex-A55) */ + case UINT32_C(0x4800D400): /* Cortex-A76 + (HiSilicon) */ + case UINT32_C(0x51008020): /* Kryo 385 Gold + (Cortex-A75) */ + case UINT32_C(0x51008030): /* Kryo 385 Silver + (Cortex-A55) */ + case UINT32_C(0x51008040): /* Kryo 485 Gold + (Cortex-A76) */ + case UINT32_C(0x51008050): /* Kryo 485 Silver + (Cortex-A55) */ case UINT32_C(0x53000030): /* Exynos M4 */ case UINT32_C(0x53000040): /* Exynos M5 */ isa->fp16arith = true; @@ -117,7 +124,8 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( /* * NEON VDOT instructions are not indicated in /proc/cpuinfo. - * Use a MIDR-based heuristic to whitelist processors known to support it: + * Use a MIDR-based heuristic to whitelist processors known to + * support it: * - Processors with Cortex-A76 cores * - Processors with Cortex-A77 cores * - Processors with Cortex-A78 cores @@ -135,7 +143,8 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( * - Neoverse V2 cores */ if (chipset->series == cpuinfo_arm_chipset_series_spreadtrum_sc && chipset->model == 9863) { - cpuinfo_log_warning("VDOT instructions disabled: cause occasional SIGILL on Spreadtrum SC9863A"); + cpuinfo_log_warning( + "VDOT instructions disabled: cause occasional SIGILL on Spreadtrum SC9863A"); } else if (chipset->series == cpuinfo_arm_chipset_series_unisoc_t && chipset->model == 310) { cpuinfo_log_warning("VDOT instructions disabled: cause occasional SIGILL on Unisoc T310"); } else { @@ -154,41 +163,52 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( case UINT32_C(0x4100D4D0): /* Cortex-A715 */ case UINT32_C(0x4100D4E0): /* Cortex-X3 */ case UINT32_C(0x4100D4F0): /* Neoverse V2 */ - case UINT32_C(0x4800D400): /* Cortex-A76 (HiSilicon) */ - case UINT32_C(0x51008040): /* Kryo 485 Gold (Cortex-A76) */ - case UINT32_C(0x51008050): /* Kryo 485 Silver (Cortex-A55) */ + case UINT32_C(0x4800D400): /* Cortex-A76 + (HiSilicon) */ + case UINT32_C(0x51008040): /* Kryo 485 Gold + (Cortex-A76) */ + case UINT32_C(0x51008050): /* Kryo 485 Silver + (Cortex-A55) */ case UINT32_C(0x53000030): /* Exynos M4 */ case UINT32_C(0x53000040): /* Exynos M5 */ isa->dot = true; break; - case UINT32_C(0x4100D050): /* Cortex A55: revision 1 or later only */ + case UINT32_C(0x4100D050): /* Cortex A55: revision 1 + or later only */ isa->dot = !!(midr_get_variant(midr) >= 1); break; - case UINT32_C(0x4100D0A0): /* Cortex A75: revision 2 or later only */ + case UINT32_C(0x4100D0A0): /* Cortex A75: revision 2 + or later only */ isa->dot = !!(midr_get_variant(midr) >= 2); break; } } } else { - /* ARMv7 or lower: use feature flags to detect optional features */ + /* ARMv7 or lower: use feature flags to detect optional features + */ /* - * ARM11 (ARM 1136/1156/1176/11 MPCore) processors can report v7 architecture - * even though they support only ARMv6 instruction set. + * ARM11 (ARM 1136/1156/1176/11 MPCore) processors can report v7 + * architecture even though they support only ARMv6 instruction + * set. */ if (architecture_version == 7 && midr_is_arm11(midr)) { - cpuinfo_log_warning("kernel-reported architecture ARMv7 ignored due to mismatch with processor microarchitecture (ARM11)"); + cpuinfo_log_warning( + "kernel-reported architecture ARMv7 ignored due to mismatch with processor microarchitecture (ARM11)"); architecture_version = 6; } if (architecture_version < 7) { - const uint32_t armv7_features_mask = CPUINFO_ARM_LINUX_FEATURE_VFPV3 | CPUINFO_ARM_LINUX_FEATURE_VFPV3D16 | CPUINFO_ARM_LINUX_FEATURE_VFPD32 | - CPUINFO_ARM_LINUX_FEATURE_VFPV4 | CPUINFO_ARM_LINUX_FEATURE_NEON | CPUINFO_ARM_LINUX_FEATURE_IDIVT | CPUINFO_ARM_LINUX_FEATURE_IDIVA; + const uint32_t armv7_features_mask = CPUINFO_ARM_LINUX_FEATURE_VFPV3 | + CPUINFO_ARM_LINUX_FEATURE_VFPV3D16 | CPUINFO_ARM_LINUX_FEATURE_VFPD32 | + CPUINFO_ARM_LINUX_FEATURE_VFPV4 | CPUINFO_ARM_LINUX_FEATURE_NEON | + CPUINFO_ARM_LINUX_FEATURE_IDIVT | CPUINFO_ARM_LINUX_FEATURE_IDIVA; if (features & armv7_features_mask) { architecture_version = 7; } } - if ((architecture_version >= 6) || (features & CPUINFO_ARM_LINUX_FEATURE_EDSP) || (architecture_flags & CPUINFO_ARM_LINUX_ARCH_E)) { + if ((architecture_version >= 6) || (features & CPUINFO_ARM_LINUX_FEATURE_EDSP) || + (architecture_flags & CPUINFO_ARM_LINUX_ARCH_E)) { isa->armv5e = true; } if (architecture_version >= 6) { @@ -199,13 +219,16 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( isa->armv7 = true; /* - * ARMv7 MP extension (PLDW instruction) is not indicated in /proc/cpuinfo. - * Use heuristic list of supporting processors: - * - Processors supporting UDIV/SDIV instructions ("idiva" + "idivt" features in /proc/cpuinfo) + * ARMv7 MP extension (PLDW instruction) is not + * indicated in /proc/cpuinfo. Use heuristic list of + * supporting processors: + * - Processors supporting UDIV/SDIV instructions + * ("idiva" + "idivt" features in /proc/cpuinfo) * - Cortex-A5 * - Cortex-A9 * - Dual-Core Scorpion - * - Krait (supports UDIV/SDIV, but kernels may not report it in /proc/cpuinfo) + * - Krait (supports UDIV/SDIV, but kernels may not + * report it in /proc/cpuinfo) * * TODO: check single-core Qualcomm Scorpion. */ @@ -218,31 +241,35 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( isa->armv7mp = true; break; default: - /* In practice IDIV instruction implies ARMv7+MP ISA */ - isa->armv7mp = (features & CPUINFO_ARM_LINUX_FEATURE_IDIV) == CPUINFO_ARM_LINUX_FEATURE_IDIV; + /* In practice IDIV instruction implies + * ARMv7+MP ISA */ + isa->armv7mp = (features & CPUINFO_ARM_LINUX_FEATURE_IDIV) == + CPUINFO_ARM_LINUX_FEATURE_IDIV; break; } } if (features & CPUINFO_ARM_LINUX_FEATURE_IWMMXT) { - #if !defined(__ARM_ARCH_8A__) && !(defined(__ARM_ARCH) && (__ARM_ARCH >= 8)) - const uint32_t wcid = read_wcid(); - cpuinfo_log_debug("WCID = 0x%08"PRIx32, wcid); - const uint32_t coprocessor_type = (wcid >> 8) & UINT32_C(0xFF); - if (coprocessor_type >= 0x10) { - isa->wmmx = true; - if (coprocessor_type >= 0x20) { - isa->wmmx2 = true; - } - } else { - cpuinfo_log_warning("WMMX ISA disabled: OS reported iwmmxt feature, " - "but WCID coprocessor type 0x%"PRIx32" indicates no WMMX support", - coprocessor_type); +#if !defined(__ARM_ARCH_8A__) && !(defined(__ARM_ARCH) && (__ARM_ARCH >= 8)) + const uint32_t wcid = read_wcid(); + cpuinfo_log_debug("WCID = 0x%08" PRIx32, wcid); + const uint32_t coprocessor_type = (wcid >> 8) & UINT32_C(0xFF); + if (coprocessor_type >= 0x10) { + isa->wmmx = true; + if (coprocessor_type >= 0x20) { + isa->wmmx2 = true; } - #else - cpuinfo_log_warning("WMMX ISA disabled: OS reported iwmmxt feature, " - "but there is no iWMMXt coprocessor"); - #endif + } else { + cpuinfo_log_warning( + "WMMX ISA disabled: OS reported iwmmxt feature, " + "but WCID coprocessor type 0x%" PRIx32 " indicates no WMMX support", + coprocessor_type); + } +#else + cpuinfo_log_warning( + "WMMX ISA disabled: OS reported iwmmxt feature, " + "but there is no iWMMXt coprocessor"); +#endif } if ((features & CPUINFO_ARM_LINUX_FEATURE_THUMB) || (architecture_flags & CPUINFO_ARM_LINUX_ARCH_T)) { @@ -263,35 +290,39 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( isa->jazelle = true; } - /* Qualcomm Krait may have buggy kernel configuration that doesn't report IDIV */ - if ((features & CPUINFO_ARM_LINUX_FEATURE_IDIV) == CPUINFO_ARM_LINUX_FEATURE_IDIV || midr_is_krait(midr)) { + /* Qualcomm Krait may have buggy kernel configuration that + * doesn't report IDIV */ + if ((features & CPUINFO_ARM_LINUX_FEATURE_IDIV) == CPUINFO_ARM_LINUX_FEATURE_IDIV || + midr_is_krait(midr)) { isa->idiv = true; } - const uint32_t vfp_mask = \ - CPUINFO_ARM_LINUX_FEATURE_VFP | CPUINFO_ARM_LINUX_FEATURE_VFPV3 | CPUINFO_ARM_LINUX_FEATURE_VFPV3D16 | \ - CPUINFO_ARM_LINUX_FEATURE_VFPD32 | CPUINFO_ARM_LINUX_FEATURE_VFPV4 | CPUINFO_ARM_LINUX_FEATURE_NEON; + const uint32_t vfp_mask = CPUINFO_ARM_LINUX_FEATURE_VFP | CPUINFO_ARM_LINUX_FEATURE_VFPV3 | + CPUINFO_ARM_LINUX_FEATURE_VFPV3D16 | CPUINFO_ARM_LINUX_FEATURE_VFPD32 | + CPUINFO_ARM_LINUX_FEATURE_VFPV4 | CPUINFO_ARM_LINUX_FEATURE_NEON; if (features & vfp_mask) { - const uint32_t vfpv3_mask = CPUINFO_ARM_LINUX_FEATURE_VFPV3 | CPUINFO_ARM_LINUX_FEATURE_VFPV3D16 | \ - CPUINFO_ARM_LINUX_FEATURE_VFPD32 | CPUINFO_ARM_LINUX_FEATURE_VFPV4 | CPUINFO_ARM_LINUX_FEATURE_NEON; + const uint32_t vfpv3_mask = CPUINFO_ARM_LINUX_FEATURE_VFPV3 | + CPUINFO_ARM_LINUX_FEATURE_VFPV3D16 | CPUINFO_ARM_LINUX_FEATURE_VFPD32 | + CPUINFO_ARM_LINUX_FEATURE_VFPV4 | CPUINFO_ARM_LINUX_FEATURE_NEON; if ((architecture_version >= 7) || (features & vfpv3_mask)) { isa->vfpv3 = true; - const uint32_t d32_mask = CPUINFO_ARM_LINUX_FEATURE_VFPD32 | CPUINFO_ARM_LINUX_FEATURE_NEON; + const uint32_t d32_mask = + CPUINFO_ARM_LINUX_FEATURE_VFPD32 | CPUINFO_ARM_LINUX_FEATURE_NEON; if (features & d32_mask) { isa->d32 = true; } } else { - #if defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_8A__) || defined(__ARM_ARCH) && (__ARM_ARCH >= 7) - isa->vfpv3 = true; - #else - const uint32_t fpsid = read_fpsid(); - cpuinfo_log_debug("FPSID = 0x%08"PRIx32, fpsid); - const uint32_t subarchitecture = (fpsid >> 16) & UINT32_C(0x7F); - if (subarchitecture >= 0x01) { - isa->vfpv2 = true; - } - #endif +#if defined(__ARM_ARCH_7A__) || defined(__ARM_ARCH_8A__) || defined(__ARM_ARCH) && (__ARM_ARCH >= 7) + isa->vfpv3 = true; +#else + const uint32_t fpsid = read_fpsid(); + cpuinfo_log_debug("FPSID = 0x%08" PRIx32, fpsid); + const uint32_t subarchitecture = (fpsid >> 16) & UINT32_C(0x7F); + if (subarchitecture >= 0x01) { + isa->vfpv2 = true; + } +#endif } } if (features & CPUINFO_ARM_LINUX_FEATURE_NEON) { @@ -300,8 +331,9 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( /* * There is no separate feature flag for FP16 support. - * VFPv4 implies VFPv3-FP16 support (and in practice, NEON-HP as well). - * Additionally, ARM Cortex-A9 and Qualcomm Scorpion support FP16. + * VFPv4 implies VFPv3-FP16 support (and in practice, NEON-HP as + * well). Additionally, ARM Cortex-A9 and Qualcomm Scorpion + * support FP16. */ if ((features & CPUINFO_ARM_LINUX_FEATURE_VFPV4) || midr_is_cortex_a9(midr) || midr_is_scorpion(midr)) { isa->fp16 = true; diff --git a/src/arm/linux/aarch64-isa.c b/src/arm/linux/aarch64-isa.c index 5dd4c4d0..db5349ec 100644 --- a/src/arm/linux/aarch64-isa.c +++ b/src/arm/linux/aarch64-isa.c @@ -3,14 +3,12 @@ #include #include - void cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo( uint32_t features, uint32_t features2, uint32_t midr, const struct cpuinfo_arm_chipset chipset[restrict static 1], - struct cpuinfo_arm_isa isa[restrict static 1]) -{ + struct cpuinfo_arm_isa isa[restrict static 1]) { if (features & CPUINFO_ARM_LINUX_FEATURE_AES) { isa->aes = true; } @@ -31,8 +29,10 @@ void cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo( } /* - * Some phones ship with an old kernel configuration that doesn't report NEON FP16 compute extension and SQRDMLAH/SQRDMLSH/UQRDMLAH/UQRDMLSH instructions. - * Use a MIDR-based heuristic to whitelist processors known to support it: + * Some phones ship with an old kernel configuration that doesn't report + * NEON FP16 compute extension and SQRDMLAH/SQRDMLSH/UQRDMLAH/UQRDMLSH + * instructions. Use a MIDR-based heuristic to whitelist processors + * known to support it: * - Processors with Cortex-A55 cores * - Processors with Cortex-A65 cores * - Processors with Cortex-A75 cores @@ -46,8 +46,10 @@ void cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo( * - Neoverse V2 cores */ if (chipset->series == cpuinfo_arm_chipset_series_samsung_exynos && chipset->model == 9810) { - /* Exynos 9810 reports that it supports FP16 compute, but in fact only little cores do */ - cpuinfo_log_warning("FP16 arithmetics and RDM disabled: only little cores in Exynos 9810 support these extensions"); + /* Exynos 9810 reports that it supports FP16 compute, but in + * fact only little cores do */ + cpuinfo_log_warning( + "FP16 arithmetics and RDM disabled: only little cores in Exynos 9810 support these extensions"); } else { const uint32_t fp16arith_mask = CPUINFO_ARM_LINUX_FEATURE_FPHP | CPUINFO_ARM_LINUX_FEATURE_ASIMDHP; switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) { @@ -75,9 +77,11 @@ void cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo( if ((features & fp16arith_mask) == fp16arith_mask) { isa->fp16arith = true; } else if (features & CPUINFO_ARM_LINUX_FEATURE_FPHP) { - cpuinfo_log_warning("FP16 arithmetics disabled: detected support only for scalar operations"); + cpuinfo_log_warning( + "FP16 arithmetics disabled: detected support only for scalar operations"); } else if (features & CPUINFO_ARM_LINUX_FEATURE_ASIMDHP) { - cpuinfo_log_warning("FP16 arithmetics disabled: detected support only for SIMD operations"); + cpuinfo_log_warning( + "FP16 arithmetics disabled: detected support only for SIMD operations"); } if (features & CPUINFO_ARM_LINUX_FEATURE_ASIMDRDM) { isa->rdm = true; @@ -90,8 +94,9 @@ void cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo( } /* - * Many phones ship with an old kernel configuration that doesn't report UDOT/SDOT instructions. - * Use a MIDR-based heuristic to whitelist processors known to support it. + * Many phones ship with an old kernel configuration that doesn't report + * UDOT/SDOT instructions. Use a MIDR-based heuristic to whitelist + * processors known to support it. */ switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) { case UINT32_C(0x4100D060): /* Cortex-A65 */ @@ -137,8 +142,9 @@ void cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo( if (features2 & CPUINFO_ARM_LINUX_FEATURE2_SVE2) { isa->sve2 = true; } - // SVEBF16 is set iff SVE and BF16 are both supported, but the SVEBF16 feature flag - // was added in Linux kernel before the BF16 feature flag, so we check for either. + // SVEBF16 is set iff SVE and BF16 are both supported, but the SVEBF16 + // feature flag was added in Linux kernel before the BF16 feature flag, + // so we check for either. if (features2 & (CPUINFO_ARM_LINUX_FEATURE2_BF16 | CPUINFO_ARM_LINUX_FEATURE2_SVEBF16)) { isa->bf16 = true; } @@ -146,4 +152,3 @@ void cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo( isa->fhm = true; } } - diff --git a/src/arm/linux/api.h b/src/arm/linux/api.h index 2e849431..365fea6c 100644 --- a/src/arm/linux/api.h +++ b/src/arm/linux/api.h @@ -3,38 +3,40 @@ #include #include +#include +#include #include #include -#include -#include #include -/* No hard limit in the kernel, maximum length observed on non-rogue kernels is 64 */ +/* No hard limit in the kernel, maximum length observed on non-rogue kernels is + * 64 */ #define CPUINFO_HARDWARE_VALUE_MAX 64 -/* No hard limit in the kernel, maximum length on Raspberry Pi is 8. Add 1 symbol to detect overly large revision strings */ +/* No hard limit in the kernel, maximum length on Raspberry Pi is 8. Add 1 + * symbol to detect overly large revision strings */ #define CPUINFO_REVISION_VALUE_MAX 9 #ifdef __ANDROID__ - /* As per include/sys/system_properties.h in Android NDK */ - #define CPUINFO_BUILD_PROP_NAME_MAX 32 - #define CPUINFO_BUILD_PROP_VALUE_MAX 92 - - struct cpuinfo_android_properties { - char proc_cpuinfo_hardware[CPUINFO_HARDWARE_VALUE_MAX]; - char ro_product_board[CPUINFO_BUILD_PROP_VALUE_MAX]; - char ro_board_platform[CPUINFO_BUILD_PROP_VALUE_MAX]; - char ro_mediatek_platform[CPUINFO_BUILD_PROP_VALUE_MAX]; - char ro_arch[CPUINFO_BUILD_PROP_VALUE_MAX]; - char ro_chipname[CPUINFO_BUILD_PROP_VALUE_MAX]; - char ro_hardware_chipname[CPUINFO_BUILD_PROP_VALUE_MAX]; - }; +/* As per include/sys/system_properties.h in Android NDK */ +#define CPUINFO_BUILD_PROP_NAME_MAX 32 +#define CPUINFO_BUILD_PROP_VALUE_MAX 92 + +struct cpuinfo_android_properties { + char proc_cpuinfo_hardware[CPUINFO_HARDWARE_VALUE_MAX]; + char ro_product_board[CPUINFO_BUILD_PROP_VALUE_MAX]; + char ro_board_platform[CPUINFO_BUILD_PROP_VALUE_MAX]; + char ro_mediatek_platform[CPUINFO_BUILD_PROP_VALUE_MAX]; + char ro_arch[CPUINFO_BUILD_PROP_VALUE_MAX]; + char ro_chipname[CPUINFO_BUILD_PROP_VALUE_MAX]; + char ro_hardware_chipname[CPUINFO_BUILD_PROP_VALUE_MAX]; +}; #endif -#define CPUINFO_ARM_LINUX_ARCH_T UINT32_C(0x00000001) -#define CPUINFO_ARM_LINUX_ARCH_E UINT32_C(0x00000002) -#define CPUINFO_ARM_LINUX_ARCH_J UINT32_C(0x00000004) +#define CPUINFO_ARM_LINUX_ARCH_T UINT32_C(0x00000001) +#define CPUINFO_ARM_LINUX_ARCH_E UINT32_C(0x00000002) +#define CPUINFO_ARM_LINUX_ARCH_J UINT32_C(0x00000004) -#define CPUINFO_ARM_LINUX_ARCH_TE UINT32_C(0x00000003) +#define CPUINFO_ARM_LINUX_ARCH_TE UINT32_C(0x00000003) #define CPUINFO_ARM_LINUX_ARCH_TEJ UINT32_C(0x00000007) struct cpuinfo_arm_linux_proc_cpuinfo_cache { @@ -49,116 +51,118 @@ struct cpuinfo_arm_linux_proc_cpuinfo_cache { }; #if CPUINFO_ARCH_ARM - /* arch/arm/include/uapi/asm/hwcap.h */ - - #define CPUINFO_ARM_LINUX_FEATURE_SWP UINT32_C(0x00000001) - #define CPUINFO_ARM_LINUX_FEATURE_HALF UINT32_C(0x00000002) - #define CPUINFO_ARM_LINUX_FEATURE_THUMB UINT32_C(0x00000004) - #define CPUINFO_ARM_LINUX_FEATURE_26BIT UINT32_C(0x00000008) - #define CPUINFO_ARM_LINUX_FEATURE_FASTMULT UINT32_C(0x00000010) - #define CPUINFO_ARM_LINUX_FEATURE_FPA UINT32_C(0x00000020) - #define CPUINFO_ARM_LINUX_FEATURE_VFP UINT32_C(0x00000040) - #define CPUINFO_ARM_LINUX_FEATURE_EDSP UINT32_C(0x00000080) - #define CPUINFO_ARM_LINUX_FEATURE_JAVA UINT32_C(0x00000100) - #define CPUINFO_ARM_LINUX_FEATURE_IWMMXT UINT32_C(0x00000200) - #define CPUINFO_ARM_LINUX_FEATURE_CRUNCH UINT32_C(0x00000400) - #define CPUINFO_ARM_LINUX_FEATURE_THUMBEE UINT32_C(0x00000800) - #define CPUINFO_ARM_LINUX_FEATURE_NEON UINT32_C(0x00001000) - #define CPUINFO_ARM_LINUX_FEATURE_VFPV3 UINT32_C(0x00002000) - #define CPUINFO_ARM_LINUX_FEATURE_VFPV3D16 UINT32_C(0x00004000) /* Also set for VFPv4 with 16 double-precision registers */ - #define CPUINFO_ARM_LINUX_FEATURE_TLS UINT32_C(0x00008000) - #define CPUINFO_ARM_LINUX_FEATURE_VFPV4 UINT32_C(0x00010000) - #define CPUINFO_ARM_LINUX_FEATURE_IDIVA UINT32_C(0x00020000) - #define CPUINFO_ARM_LINUX_FEATURE_IDIVT UINT32_C(0x00040000) - #define CPUINFO_ARM_LINUX_FEATURE_IDIV UINT32_C(0x00060000) - #define CPUINFO_ARM_LINUX_FEATURE_VFPD32 UINT32_C(0x00080000) - #define CPUINFO_ARM_LINUX_FEATURE_LPAE UINT32_C(0x00100000) - #define CPUINFO_ARM_LINUX_FEATURE_EVTSTRM UINT32_C(0x00200000) - - #define CPUINFO_ARM_LINUX_FEATURE2_AES UINT32_C(0x00000001) - #define CPUINFO_ARM_LINUX_FEATURE2_PMULL UINT32_C(0x00000002) - #define CPUINFO_ARM_LINUX_FEATURE2_SHA1 UINT32_C(0x00000004) - #define CPUINFO_ARM_LINUX_FEATURE2_SHA2 UINT32_C(0x00000008) - #define CPUINFO_ARM_LINUX_FEATURE2_CRC32 UINT32_C(0x00000010) +/* arch/arm/include/uapi/asm/hwcap.h */ + +#define CPUINFO_ARM_LINUX_FEATURE_SWP UINT32_C(0x00000001) +#define CPUINFO_ARM_LINUX_FEATURE_HALF UINT32_C(0x00000002) +#define CPUINFO_ARM_LINUX_FEATURE_THUMB UINT32_C(0x00000004) +#define CPUINFO_ARM_LINUX_FEATURE_26BIT UINT32_C(0x00000008) +#define CPUINFO_ARM_LINUX_FEATURE_FASTMULT UINT32_C(0x00000010) +#define CPUINFO_ARM_LINUX_FEATURE_FPA UINT32_C(0x00000020) +#define CPUINFO_ARM_LINUX_FEATURE_VFP UINT32_C(0x00000040) +#define CPUINFO_ARM_LINUX_FEATURE_EDSP UINT32_C(0x00000080) +#define CPUINFO_ARM_LINUX_FEATURE_JAVA UINT32_C(0x00000100) +#define CPUINFO_ARM_LINUX_FEATURE_IWMMXT UINT32_C(0x00000200) +#define CPUINFO_ARM_LINUX_FEATURE_CRUNCH UINT32_C(0x00000400) +#define CPUINFO_ARM_LINUX_FEATURE_THUMBEE UINT32_C(0x00000800) +#define CPUINFO_ARM_LINUX_FEATURE_NEON UINT32_C(0x00001000) +#define CPUINFO_ARM_LINUX_FEATURE_VFPV3 UINT32_C(0x00002000) +#define CPUINFO_ARM_LINUX_FEATURE_VFPV3D16 \ + UINT32_C(0x00004000) /* Also set for VFPv4 with 16 double-precision \ + registers */ +#define CPUINFO_ARM_LINUX_FEATURE_TLS UINT32_C(0x00008000) +#define CPUINFO_ARM_LINUX_FEATURE_VFPV4 UINT32_C(0x00010000) +#define CPUINFO_ARM_LINUX_FEATURE_IDIVA UINT32_C(0x00020000) +#define CPUINFO_ARM_LINUX_FEATURE_IDIVT UINT32_C(0x00040000) +#define CPUINFO_ARM_LINUX_FEATURE_IDIV UINT32_C(0x00060000) +#define CPUINFO_ARM_LINUX_FEATURE_VFPD32 UINT32_C(0x00080000) +#define CPUINFO_ARM_LINUX_FEATURE_LPAE UINT32_C(0x00100000) +#define CPUINFO_ARM_LINUX_FEATURE_EVTSTRM UINT32_C(0x00200000) + +#define CPUINFO_ARM_LINUX_FEATURE2_AES UINT32_C(0x00000001) +#define CPUINFO_ARM_LINUX_FEATURE2_PMULL UINT32_C(0x00000002) +#define CPUINFO_ARM_LINUX_FEATURE2_SHA1 UINT32_C(0x00000004) +#define CPUINFO_ARM_LINUX_FEATURE2_SHA2 UINT32_C(0x00000008) +#define CPUINFO_ARM_LINUX_FEATURE2_CRC32 UINT32_C(0x00000010) #elif CPUINFO_ARCH_ARM64 - /* arch/arm64/include/uapi/asm/hwcap.h */ - #define CPUINFO_ARM_LINUX_FEATURE_FP UINT32_C(0x00000001) - #define CPUINFO_ARM_LINUX_FEATURE_ASIMD UINT32_C(0x00000002) - #define CPUINFO_ARM_LINUX_FEATURE_EVTSTRM UINT32_C(0x00000004) - #define CPUINFO_ARM_LINUX_FEATURE_AES UINT32_C(0x00000008) - #define CPUINFO_ARM_LINUX_FEATURE_PMULL UINT32_C(0x00000010) - #define CPUINFO_ARM_LINUX_FEATURE_SHA1 UINT32_C(0x00000020) - #define CPUINFO_ARM_LINUX_FEATURE_SHA2 UINT32_C(0x00000040) - #define CPUINFO_ARM_LINUX_FEATURE_CRC32 UINT32_C(0x00000080) - #define CPUINFO_ARM_LINUX_FEATURE_ATOMICS UINT32_C(0x00000100) - #define CPUINFO_ARM_LINUX_FEATURE_FPHP UINT32_C(0x00000200) - #define CPUINFO_ARM_LINUX_FEATURE_ASIMDHP UINT32_C(0x00000400) - #define CPUINFO_ARM_LINUX_FEATURE_CPUID UINT32_C(0x00000800) - #define CPUINFO_ARM_LINUX_FEATURE_ASIMDRDM UINT32_C(0x00001000) - #define CPUINFO_ARM_LINUX_FEATURE_JSCVT UINT32_C(0x00002000) - #define CPUINFO_ARM_LINUX_FEATURE_FCMA UINT32_C(0x00004000) - #define CPUINFO_ARM_LINUX_FEATURE_LRCPC UINT32_C(0x00008000) - #define CPUINFO_ARM_LINUX_FEATURE_DCPOP UINT32_C(0x00010000) - #define CPUINFO_ARM_LINUX_FEATURE_SHA3 UINT32_C(0x00020000) - #define CPUINFO_ARM_LINUX_FEATURE_SM3 UINT32_C(0x00040000) - #define CPUINFO_ARM_LINUX_FEATURE_SM4 UINT32_C(0x00080000) - #define CPUINFO_ARM_LINUX_FEATURE_ASIMDDP UINT32_C(0x00100000) - #define CPUINFO_ARM_LINUX_FEATURE_SHA512 UINT32_C(0x00200000) - #define CPUINFO_ARM_LINUX_FEATURE_SVE UINT32_C(0x00400000) - #define CPUINFO_ARM_LINUX_FEATURE_ASIMDFHM UINT32_C(0x00800000) - #define CPUINFO_ARM_LINUX_FEATURE_DIT UINT32_C(0x01000000) - #define CPUINFO_ARM_LINUX_FEATURE_USCAT UINT32_C(0x02000000) - #define CPUINFO_ARM_LINUX_FEATURE_ILRCPC UINT32_C(0x04000000) - #define CPUINFO_ARM_LINUX_FEATURE_FLAGM UINT32_C(0x08000000) - #define CPUINFO_ARM_LINUX_FEATURE_SSBS UINT32_C(0x10000000) - #define CPUINFO_ARM_LINUX_FEATURE_SB UINT32_C(0x20000000) - #define CPUINFO_ARM_LINUX_FEATURE_PACA UINT32_C(0x40000000) - #define CPUINFO_ARM_LINUX_FEATURE_PACG UINT32_C(0x80000000) - - #define CPUINFO_ARM_LINUX_FEATURE2_DCPODP UINT32_C(0x00000001) - #define CPUINFO_ARM_LINUX_FEATURE2_SVE2 UINT32_C(0x00000002) - #define CPUINFO_ARM_LINUX_FEATURE2_SVEAES UINT32_C(0x00000004) - #define CPUINFO_ARM_LINUX_FEATURE2_SVEPMULL UINT32_C(0x00000008) - #define CPUINFO_ARM_LINUX_FEATURE2_SVEBITPERM UINT32_C(0x00000010) - #define CPUINFO_ARM_LINUX_FEATURE2_SVESHA3 UINT32_C(0x00000020) - #define CPUINFO_ARM_LINUX_FEATURE2_SVESM4 UINT32_C(0x00000040) - #define CPUINFO_ARM_LINUX_FEATURE2_FLAGM2 UINT32_C(0x00000080) - #define CPUINFO_ARM_LINUX_FEATURE2_FRINT UINT32_C(0x00000100) - #define CPUINFO_ARM_LINUX_FEATURE2_SVEI8MM UINT32_C(0x00000200) - #define CPUINFO_ARM_LINUX_FEATURE2_SVEF32MM UINT32_C(0x00000400) - #define CPUINFO_ARM_LINUX_FEATURE2_SVEF64MM UINT32_C(0x00000800) - #define CPUINFO_ARM_LINUX_FEATURE2_SVEBF16 UINT32_C(0x00001000) - #define CPUINFO_ARM_LINUX_FEATURE2_I8MM UINT32_C(0x00002000) - #define CPUINFO_ARM_LINUX_FEATURE2_BF16 UINT32_C(0x00004000) - #define CPUINFO_ARM_LINUX_FEATURE2_DGH UINT32_C(0x00008000) - #define CPUINFO_ARM_LINUX_FEATURE2_RNG UINT32_C(0x00010000) - #define CPUINFO_ARM_LINUX_FEATURE2_BTI UINT32_C(0x00020000) +/* arch/arm64/include/uapi/asm/hwcap.h */ +#define CPUINFO_ARM_LINUX_FEATURE_FP UINT32_C(0x00000001) +#define CPUINFO_ARM_LINUX_FEATURE_ASIMD UINT32_C(0x00000002) +#define CPUINFO_ARM_LINUX_FEATURE_EVTSTRM UINT32_C(0x00000004) +#define CPUINFO_ARM_LINUX_FEATURE_AES UINT32_C(0x00000008) +#define CPUINFO_ARM_LINUX_FEATURE_PMULL UINT32_C(0x00000010) +#define CPUINFO_ARM_LINUX_FEATURE_SHA1 UINT32_C(0x00000020) +#define CPUINFO_ARM_LINUX_FEATURE_SHA2 UINT32_C(0x00000040) +#define CPUINFO_ARM_LINUX_FEATURE_CRC32 UINT32_C(0x00000080) +#define CPUINFO_ARM_LINUX_FEATURE_ATOMICS UINT32_C(0x00000100) +#define CPUINFO_ARM_LINUX_FEATURE_FPHP UINT32_C(0x00000200) +#define CPUINFO_ARM_LINUX_FEATURE_ASIMDHP UINT32_C(0x00000400) +#define CPUINFO_ARM_LINUX_FEATURE_CPUID UINT32_C(0x00000800) +#define CPUINFO_ARM_LINUX_FEATURE_ASIMDRDM UINT32_C(0x00001000) +#define CPUINFO_ARM_LINUX_FEATURE_JSCVT UINT32_C(0x00002000) +#define CPUINFO_ARM_LINUX_FEATURE_FCMA UINT32_C(0x00004000) +#define CPUINFO_ARM_LINUX_FEATURE_LRCPC UINT32_C(0x00008000) +#define CPUINFO_ARM_LINUX_FEATURE_DCPOP UINT32_C(0x00010000) +#define CPUINFO_ARM_LINUX_FEATURE_SHA3 UINT32_C(0x00020000) +#define CPUINFO_ARM_LINUX_FEATURE_SM3 UINT32_C(0x00040000) +#define CPUINFO_ARM_LINUX_FEATURE_SM4 UINT32_C(0x00080000) +#define CPUINFO_ARM_LINUX_FEATURE_ASIMDDP UINT32_C(0x00100000) +#define CPUINFO_ARM_LINUX_FEATURE_SHA512 UINT32_C(0x00200000) +#define CPUINFO_ARM_LINUX_FEATURE_SVE UINT32_C(0x00400000) +#define CPUINFO_ARM_LINUX_FEATURE_ASIMDFHM UINT32_C(0x00800000) +#define CPUINFO_ARM_LINUX_FEATURE_DIT UINT32_C(0x01000000) +#define CPUINFO_ARM_LINUX_FEATURE_USCAT UINT32_C(0x02000000) +#define CPUINFO_ARM_LINUX_FEATURE_ILRCPC UINT32_C(0x04000000) +#define CPUINFO_ARM_LINUX_FEATURE_FLAGM UINT32_C(0x08000000) +#define CPUINFO_ARM_LINUX_FEATURE_SSBS UINT32_C(0x10000000) +#define CPUINFO_ARM_LINUX_FEATURE_SB UINT32_C(0x20000000) +#define CPUINFO_ARM_LINUX_FEATURE_PACA UINT32_C(0x40000000) +#define CPUINFO_ARM_LINUX_FEATURE_PACG UINT32_C(0x80000000) + +#define CPUINFO_ARM_LINUX_FEATURE2_DCPODP UINT32_C(0x00000001) +#define CPUINFO_ARM_LINUX_FEATURE2_SVE2 UINT32_C(0x00000002) +#define CPUINFO_ARM_LINUX_FEATURE2_SVEAES UINT32_C(0x00000004) +#define CPUINFO_ARM_LINUX_FEATURE2_SVEPMULL UINT32_C(0x00000008) +#define CPUINFO_ARM_LINUX_FEATURE2_SVEBITPERM UINT32_C(0x00000010) +#define CPUINFO_ARM_LINUX_FEATURE2_SVESHA3 UINT32_C(0x00000020) +#define CPUINFO_ARM_LINUX_FEATURE2_SVESM4 UINT32_C(0x00000040) +#define CPUINFO_ARM_LINUX_FEATURE2_FLAGM2 UINT32_C(0x00000080) +#define CPUINFO_ARM_LINUX_FEATURE2_FRINT UINT32_C(0x00000100) +#define CPUINFO_ARM_LINUX_FEATURE2_SVEI8MM UINT32_C(0x00000200) +#define CPUINFO_ARM_LINUX_FEATURE2_SVEF32MM UINT32_C(0x00000400) +#define CPUINFO_ARM_LINUX_FEATURE2_SVEF64MM UINT32_C(0x00000800) +#define CPUINFO_ARM_LINUX_FEATURE2_SVEBF16 UINT32_C(0x00001000) +#define CPUINFO_ARM_LINUX_FEATURE2_I8MM UINT32_C(0x00002000) +#define CPUINFO_ARM_LINUX_FEATURE2_BF16 UINT32_C(0x00004000) +#define CPUINFO_ARM_LINUX_FEATURE2_DGH UINT32_C(0x00008000) +#define CPUINFO_ARM_LINUX_FEATURE2_RNG UINT32_C(0x00010000) +#define CPUINFO_ARM_LINUX_FEATURE2_BTI UINT32_C(0x00020000) #endif #define CPUINFO_ARM_LINUX_VALID_ARCHITECTURE UINT32_C(0x00010000) -#define CPUINFO_ARM_LINUX_VALID_IMPLEMENTER UINT32_C(0x00020000) -#define CPUINFO_ARM_LINUX_VALID_VARIANT UINT32_C(0x00040000) -#define CPUINFO_ARM_LINUX_VALID_PART UINT32_C(0x00080000) -#define CPUINFO_ARM_LINUX_VALID_REVISION UINT32_C(0x00100000) -#define CPUINFO_ARM_LINUX_VALID_PROCESSOR UINT32_C(0x00200000) -#define CPUINFO_ARM_LINUX_VALID_FEATURES UINT32_C(0x00400000) +#define CPUINFO_ARM_LINUX_VALID_IMPLEMENTER UINT32_C(0x00020000) +#define CPUINFO_ARM_LINUX_VALID_VARIANT UINT32_C(0x00040000) +#define CPUINFO_ARM_LINUX_VALID_PART UINT32_C(0x00080000) +#define CPUINFO_ARM_LINUX_VALID_REVISION UINT32_C(0x00100000) +#define CPUINFO_ARM_LINUX_VALID_PROCESSOR UINT32_C(0x00200000) +#define CPUINFO_ARM_LINUX_VALID_FEATURES UINT32_C(0x00400000) #if CPUINFO_ARCH_ARM - #define CPUINFO_ARM_LINUX_VALID_ICACHE_SIZE UINT32_C(0x01000000) - #define CPUINFO_ARM_LINUX_VALID_ICACHE_SETS UINT32_C(0x02000000) - #define CPUINFO_ARM_LINUX_VALID_ICACHE_WAYS UINT32_C(0x04000000) - #define CPUINFO_ARM_LINUX_VALID_ICACHE_LINE UINT32_C(0x08000000) - #define CPUINFO_ARM_LINUX_VALID_DCACHE_SIZE UINT32_C(0x10000000) - #define CPUINFO_ARM_LINUX_VALID_DCACHE_SETS UINT32_C(0x20000000) - #define CPUINFO_ARM_LINUX_VALID_DCACHE_WAYS UINT32_C(0x40000000) - #define CPUINFO_ARM_LINUX_VALID_DCACHE_LINE UINT32_C(0x80000000) +#define CPUINFO_ARM_LINUX_VALID_ICACHE_SIZE UINT32_C(0x01000000) +#define CPUINFO_ARM_LINUX_VALID_ICACHE_SETS UINT32_C(0x02000000) +#define CPUINFO_ARM_LINUX_VALID_ICACHE_WAYS UINT32_C(0x04000000) +#define CPUINFO_ARM_LINUX_VALID_ICACHE_LINE UINT32_C(0x08000000) +#define CPUINFO_ARM_LINUX_VALID_DCACHE_SIZE UINT32_C(0x10000000) +#define CPUINFO_ARM_LINUX_VALID_DCACHE_SETS UINT32_C(0x20000000) +#define CPUINFO_ARM_LINUX_VALID_DCACHE_WAYS UINT32_C(0x40000000) +#define CPUINFO_ARM_LINUX_VALID_DCACHE_LINE UINT32_C(0x80000000) #endif -#define CPUINFO_ARM_LINUX_VALID_INFO UINT32_C(0x007F0000) -#define CPUINFO_ARM_LINUX_VALID_MIDR UINT32_C(0x003F0000) +#define CPUINFO_ARM_LINUX_VALID_INFO UINT32_C(0x007F0000) +#define CPUINFO_ARM_LINUX_VALID_MIDR UINT32_C(0x003F0000) #if CPUINFO_ARCH_ARM - #define CPUINFO_ARM_LINUX_VALID_ICACHE UINT32_C(0x0F000000) - #define CPUINFO_ARM_LINUX_VALID_DCACHE UINT32_C(0xF0000000) - #define CPUINFO_ARM_LINUX_VALID_CACHE_LINE UINT32_C(0x88000000) +#define CPUINFO_ARM_LINUX_VALID_ICACHE UINT32_C(0x0F000000) +#define CPUINFO_ARM_LINUX_VALID_DCACHE UINT32_C(0xF0000000) +#define CPUINFO_ARM_LINUX_VALID_CACHE_LINE UINT32_C(0x88000000) #endif struct cpuinfo_arm_linux_processor { @@ -178,13 +182,15 @@ struct cpuinfo_arm_linux_processor { uint32_t uarch_index; /** * ID of the physical package which includes this logical processor. - * The value is parsed from /sys/devices/system/cpu/cpu/topology/physical_package_id + * The value is parsed from + * /sys/devices/system/cpu/cpu/topology/physical_package_id */ uint32_t package_id; /** - * Minimum processor ID on the package which includes this logical processor. - * This value can serve as an ID for the cluster of logical processors: it is the - * same for all logical processors on the same package. + * Minimum processor ID on the package which includes this logical + * processor. This value can serve as an ID for the cluster of logical + * processors: it is the same for all logical processors on the same + * package. */ uint32_t package_leader_id; /** @@ -193,14 +199,16 @@ struct cpuinfo_arm_linux_processor { uint32_t package_processor_count; /** * Maximum frequency, in kHZ. - * The value is parsed from /sys/devices/system/cpu/cpu/cpufreq/cpuinfo_max_freq - * If failed to read or parse the file, the value is 0. + * The value is parsed from + * /sys/devices/system/cpu/cpu/cpufreq/cpuinfo_max_freq If failed to + * read or parse the file, the value is 0. */ uint32_t max_frequency; /** * Minimum frequency, in kHZ. - * The value is parsed from /sys/devices/system/cpu/cpu/cpufreq/cpuinfo_min_freq - * If failed to read or parse the file, the value is 0. + * The value is parsed from + * /sys/devices/system/cpu/cpu/cpufreq/cpuinfo_min_freq If failed to + * read or parse the file, the value is 0. */ uint32_t min_frequency; /** Linux processor ID */ @@ -216,8 +224,7 @@ struct cpuinfo_arm_linux_cluster { /* Returns true if the two processors do belong to the same cluster */ static inline bool cpuinfo_arm_linux_processor_equals( struct cpuinfo_arm_linux_processor processor_i[restrict static 1], - struct cpuinfo_arm_linux_processor processor_j[restrict static 1]) -{ + struct cpuinfo_arm_linux_processor processor_j[restrict static 1]) { const uint32_t joint_flags = processor_i->flags & processor_j->flags; bool same_max_frequency = false; @@ -251,11 +258,11 @@ static inline bool cpuinfo_arm_linux_processor_equals( return same_max_frequency && same_min_frequency; } -/* Returns true if the two processors certainly don't belong to the same cluster */ +/* Returns true if the two processors certainly don't belong to the same cluster + */ static inline bool cpuinfo_arm_linux_processor_not_equals( struct cpuinfo_arm_linux_processor processor_i[restrict static 1], - struct cpuinfo_arm_linux_processor processor_j[restrict static 1]) -{ + struct cpuinfo_arm_linux_processor processor_j[restrict static 1]) { const uint32_t joint_flags = processor_i->flags & processor_j->flags; if (joint_flags & CPUINFO_LINUX_FLAG_MAX_FREQUENCY) { @@ -286,79 +293,73 @@ CPUINFO_INTERNAL bool cpuinfo_arm_linux_parse_proc_cpuinfo( struct cpuinfo_arm_linux_processor processors[restrict static max_processors_count]); #if CPUINFO_ARCH_ARM - CPUINFO_INTERNAL bool cpuinfo_arm_linux_hwcap_from_getauxval( - uint32_t hwcap[restrict static 1], - uint32_t hwcap2[restrict static 1]); - CPUINFO_INTERNAL bool cpuinfo_arm_linux_hwcap_from_procfs( - uint32_t hwcap[restrict static 1], - uint32_t hwcap2[restrict static 1]); - - CPUINFO_INTERNAL void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( - uint32_t features, - uint32_t features2, - uint32_t midr, - uint32_t architecture_version, - uint32_t architecture_flags, - const struct cpuinfo_arm_chipset chipset[restrict static 1], - struct cpuinfo_arm_isa isa[restrict static 1]); +CPUINFO_INTERNAL bool cpuinfo_arm_linux_hwcap_from_getauxval( + uint32_t hwcap[restrict static 1], + uint32_t hwcap2[restrict static 1]); +CPUINFO_INTERNAL bool cpuinfo_arm_linux_hwcap_from_procfs( + uint32_t hwcap[restrict static 1], + uint32_t hwcap2[restrict static 1]); + +CPUINFO_INTERNAL void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( + uint32_t features, + uint32_t features2, + uint32_t midr, + uint32_t architecture_version, + uint32_t architecture_flags, + const struct cpuinfo_arm_chipset chipset[restrict static 1], + struct cpuinfo_arm_isa isa[restrict static 1]); #elif CPUINFO_ARCH_ARM64 - CPUINFO_INTERNAL void cpuinfo_arm_linux_hwcap_from_getauxval( - uint32_t hwcap[restrict static 1], - uint32_t hwcap2[restrict static 1]); - - CPUINFO_INTERNAL void cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo( - uint32_t features, - uint32_t features2, - uint32_t midr, - const struct cpuinfo_arm_chipset chipset[restrict static 1], - struct cpuinfo_arm_isa isa[restrict static 1]); +CPUINFO_INTERNAL void cpuinfo_arm_linux_hwcap_from_getauxval( + uint32_t hwcap[restrict static 1], + uint32_t hwcap2[restrict static 1]); + +CPUINFO_INTERNAL void cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo( + uint32_t features, + uint32_t features2, + uint32_t midr, + const struct cpuinfo_arm_chipset chipset[restrict static 1], + struct cpuinfo_arm_isa isa[restrict static 1]); #endif #if defined(__ANDROID__) - CPUINFO_INTERNAL struct cpuinfo_arm_chipset - cpuinfo_arm_android_decode_chipset( - const struct cpuinfo_android_properties properties[restrict static 1], - uint32_t cores, - uint32_t max_cpu_freq_max); +CPUINFO_INTERNAL struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset( + const struct cpuinfo_android_properties properties[restrict static 1], + uint32_t cores, + uint32_t max_cpu_freq_max); #else - CPUINFO_INTERNAL struct cpuinfo_arm_chipset - cpuinfo_arm_linux_decode_chipset( - const char hardware[restrict static CPUINFO_HARDWARE_VALUE_MAX], - const char revision[restrict static CPUINFO_REVISION_VALUE_MAX], - uint32_t cores, - uint32_t max_cpu_freq_max); +CPUINFO_INTERNAL struct cpuinfo_arm_chipset cpuinfo_arm_linux_decode_chipset( + const char hardware[restrict static CPUINFO_HARDWARE_VALUE_MAX], + const char revision[restrict static CPUINFO_REVISION_VALUE_MAX], + uint32_t cores, + uint32_t max_cpu_freq_max); #endif -CPUINFO_INTERNAL struct cpuinfo_arm_chipset - cpuinfo_arm_linux_decode_chipset_from_proc_cpuinfo_hardware( - const char proc_cpuinfo_hardware[restrict static CPUINFO_HARDWARE_VALUE_MAX], - uint32_t cores, uint32_t max_cpu_freq_max, bool is_tegra); +CPUINFO_INTERNAL struct cpuinfo_arm_chipset cpuinfo_arm_linux_decode_chipset_from_proc_cpuinfo_hardware( + const char proc_cpuinfo_hardware[restrict static CPUINFO_HARDWARE_VALUE_MAX], + uint32_t cores, + uint32_t max_cpu_freq_max, + bool is_tegra); #ifdef __ANDROID__ - CPUINFO_INTERNAL struct cpuinfo_arm_chipset - cpuinfo_arm_android_decode_chipset_from_ro_product_board( - const char ro_product_board[restrict static CPUINFO_BUILD_PROP_VALUE_MAX], - uint32_t cores, uint32_t max_cpu_freq_max); - CPUINFO_INTERNAL struct cpuinfo_arm_chipset - cpuinfo_arm_android_decode_chipset_from_ro_board_platform( - const char ro_board_platform[restrict static CPUINFO_BUILD_PROP_VALUE_MAX], - uint32_t cores, uint32_t max_cpu_freq_max); - CPUINFO_INTERNAL struct cpuinfo_arm_chipset - cpuinfo_arm_android_decode_chipset_from_ro_mediatek_platform( - const char ro_mediatek_platform[restrict static CPUINFO_BUILD_PROP_VALUE_MAX]); - CPUINFO_INTERNAL struct cpuinfo_arm_chipset - cpuinfo_arm_android_decode_chipset_from_ro_arch( - const char ro_arch[restrict static CPUINFO_BUILD_PROP_VALUE_MAX]); - CPUINFO_INTERNAL struct cpuinfo_arm_chipset - cpuinfo_arm_android_decode_chipset_from_ro_chipname( - const char ro_chipname[restrict static CPUINFO_BUILD_PROP_VALUE_MAX]); - CPUINFO_INTERNAL struct cpuinfo_arm_chipset - cpuinfo_arm_android_decode_chipset_from_ro_hardware_chipname( - const char ro_hardware_chipname[restrict static CPUINFO_BUILD_PROP_VALUE_MAX]); +CPUINFO_INTERNAL struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_product_board( + const char ro_product_board[restrict static CPUINFO_BUILD_PROP_VALUE_MAX], + uint32_t cores, + uint32_t max_cpu_freq_max); +CPUINFO_INTERNAL struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_board_platform( + const char ro_board_platform[restrict static CPUINFO_BUILD_PROP_VALUE_MAX], + uint32_t cores, + uint32_t max_cpu_freq_max); +CPUINFO_INTERNAL struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_mediatek_platform( + const char ro_mediatek_platform[restrict static CPUINFO_BUILD_PROP_VALUE_MAX]); +CPUINFO_INTERNAL struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_arch( + const char ro_arch[restrict static CPUINFO_BUILD_PROP_VALUE_MAX]); +CPUINFO_INTERNAL struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_chipname( + const char ro_chipname[restrict static CPUINFO_BUILD_PROP_VALUE_MAX]); +CPUINFO_INTERNAL struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_hardware_chipname( + const char ro_hardware_chipname[restrict static CPUINFO_BUILD_PROP_VALUE_MAX]); #else - CPUINFO_INTERNAL struct cpuinfo_arm_chipset - cpuinfo_arm_linux_decode_chipset_from_proc_cpuinfo_revision( - const char proc_cpuinfo_revision[restrict static CPUINFO_REVISION_VALUE_MAX]); +CPUINFO_INTERNAL struct cpuinfo_arm_chipset cpuinfo_arm_linux_decode_chipset_from_proc_cpuinfo_revision( + const char proc_cpuinfo_revision[restrict static CPUINFO_REVISION_VALUE_MAX]); #endif CPUINFO_INTERNAL bool cpuinfo_arm_linux_detect_core_clusters_by_heuristic( diff --git a/src/arm/linux/chipset.c b/src/arm/linux/chipset.c index 0e9191fd..1f93351d 100644 --- a/src/arm/linux/chipset.c +++ b/src/arm/linux/chipset.c @@ -5,11 +5,10 @@ #include #ifdef __ANDROID__ - #include +#include #endif -#include #include - +#include static inline bool is_ascii_whitespace(char c) { switch (c) { @@ -25,29 +24,30 @@ static inline bool is_ascii_whitespace(char c) { static inline bool is_ascii_alphabetic(char c) { const char lower_c = c | '\x20'; - return (uint8_t) (lower_c - 'a') <= (uint8_t) ('z' - 'a'); + return (uint8_t)(lower_c - 'a') <= (uint8_t)('z' - 'a'); } static inline bool is_ascii_alphabetic_uppercase(char c) { - return (uint8_t) (c - 'A') <= (uint8_t) ('Z' - 'A'); + return (uint8_t)(c - 'A') <= (uint8_t)('Z' - 'A'); } static inline bool is_ascii_numeric(char c) { - return (uint8_t) (c - '0') < 10; + return (uint8_t)(c - '0') < 10; } static inline uint16_t load_u16le(const void* ptr) { - const uint8_t* byte_ptr = (const uint8_t*) ptr; - return ((uint16_t) byte_ptr[1] << 8) | (uint16_t) byte_ptr[0]; + const uint8_t* byte_ptr = (const uint8_t*)ptr; + return ((uint16_t)byte_ptr[1] << 8) | (uint16_t)byte_ptr[0]; } static inline uint32_t load_u24le(const void* ptr) { - return ((uint32_t) ((const uint8_t*) ptr)[2] << 16) | (uint32_t) load_u16le(ptr); + return ((uint32_t)((const uint8_t*)ptr)[2] << 16) | (uint32_t)load_u16le(ptr); } static inline uint32_t load_u32le(const void* ptr) { - const uint8_t* byte_ptr = (const uint8_t*) ptr; - return ((uint32_t) byte_ptr[3] << 24) | ((uint32_t) byte_ptr[2] << 16) | ((uint32_t) byte_ptr[1] << 8) | (uint32_t) byte_ptr[0]; + const uint8_t* byte_ptr = (const uint8_t*)ptr; + return ((uint32_t)byte_ptr[3] << 24) | ((uint32_t)byte_ptr[2] << 16) | ((uint32_t)byte_ptr[1] << 8) | + (uint32_t)byte_ptr[0]; } /* @@ -55,63 +55,63 @@ static inline uint32_t load_u32le(const void* ptr) { * This map is used to avoid storing vendor IDs in tables. */ static enum cpuinfo_arm_chipset_vendor chipset_series_vendor[cpuinfo_arm_chipset_series_max] = { - [cpuinfo_arm_chipset_series_unknown] = cpuinfo_arm_chipset_vendor_unknown, - [cpuinfo_arm_chipset_series_qualcomm_qsd] = cpuinfo_arm_chipset_vendor_qualcomm, - [cpuinfo_arm_chipset_series_qualcomm_msm] = cpuinfo_arm_chipset_vendor_qualcomm, - [cpuinfo_arm_chipset_series_qualcomm_apq] = cpuinfo_arm_chipset_vendor_qualcomm, - [cpuinfo_arm_chipset_series_qualcomm_snapdragon] = cpuinfo_arm_chipset_vendor_qualcomm, - [cpuinfo_arm_chipset_series_mediatek_mt] = cpuinfo_arm_chipset_vendor_mediatek, - [cpuinfo_arm_chipset_series_samsung_exynos] = cpuinfo_arm_chipset_vendor_samsung, - [cpuinfo_arm_chipset_series_hisilicon_k3v] = cpuinfo_arm_chipset_vendor_hisilicon, - [cpuinfo_arm_chipset_series_hisilicon_hi] = cpuinfo_arm_chipset_vendor_hisilicon, - [cpuinfo_arm_chipset_series_hisilicon_kirin] = cpuinfo_arm_chipset_vendor_hisilicon, - [cpuinfo_arm_chipset_series_actions_atm] = cpuinfo_arm_chipset_vendor_actions, - [cpuinfo_arm_chipset_series_allwinner_a] = cpuinfo_arm_chipset_vendor_allwinner, - [cpuinfo_arm_chipset_series_amlogic_aml] = cpuinfo_arm_chipset_vendor_amlogic, - [cpuinfo_arm_chipset_series_amlogic_s] = cpuinfo_arm_chipset_vendor_amlogic, - [cpuinfo_arm_chipset_series_broadcom_bcm] = cpuinfo_arm_chipset_vendor_broadcom, - [cpuinfo_arm_chipset_series_lg_nuclun] = cpuinfo_arm_chipset_vendor_lg, - [cpuinfo_arm_chipset_series_leadcore_lc] = cpuinfo_arm_chipset_vendor_leadcore, - [cpuinfo_arm_chipset_series_marvell_pxa] = cpuinfo_arm_chipset_vendor_marvell, - [cpuinfo_arm_chipset_series_mstar_6a] = cpuinfo_arm_chipset_vendor_mstar, - [cpuinfo_arm_chipset_series_novathor_u] = cpuinfo_arm_chipset_vendor_novathor, - [cpuinfo_arm_chipset_series_nvidia_tegra_t] = cpuinfo_arm_chipset_vendor_nvidia, - [cpuinfo_arm_chipset_series_nvidia_tegra_ap] = cpuinfo_arm_chipset_vendor_nvidia, - [cpuinfo_arm_chipset_series_nvidia_tegra_sl] = cpuinfo_arm_chipset_vendor_nvidia, - [cpuinfo_arm_chipset_series_pinecone_surge_s] = cpuinfo_arm_chipset_vendor_pinecone, - [cpuinfo_arm_chipset_series_renesas_mp] = cpuinfo_arm_chipset_vendor_renesas, - [cpuinfo_arm_chipset_series_rockchip_rk] = cpuinfo_arm_chipset_vendor_rockchip, - [cpuinfo_arm_chipset_series_spreadtrum_sc] = cpuinfo_arm_chipset_vendor_spreadtrum, - [cpuinfo_arm_chipset_series_telechips_tcc] = cpuinfo_arm_chipset_vendor_telechips, + [cpuinfo_arm_chipset_series_unknown] = cpuinfo_arm_chipset_vendor_unknown, + [cpuinfo_arm_chipset_series_qualcomm_qsd] = cpuinfo_arm_chipset_vendor_qualcomm, + [cpuinfo_arm_chipset_series_qualcomm_msm] = cpuinfo_arm_chipset_vendor_qualcomm, + [cpuinfo_arm_chipset_series_qualcomm_apq] = cpuinfo_arm_chipset_vendor_qualcomm, + [cpuinfo_arm_chipset_series_qualcomm_snapdragon] = cpuinfo_arm_chipset_vendor_qualcomm, + [cpuinfo_arm_chipset_series_mediatek_mt] = cpuinfo_arm_chipset_vendor_mediatek, + [cpuinfo_arm_chipset_series_samsung_exynos] = cpuinfo_arm_chipset_vendor_samsung, + [cpuinfo_arm_chipset_series_hisilicon_k3v] = cpuinfo_arm_chipset_vendor_hisilicon, + [cpuinfo_arm_chipset_series_hisilicon_hi] = cpuinfo_arm_chipset_vendor_hisilicon, + [cpuinfo_arm_chipset_series_hisilicon_kirin] = cpuinfo_arm_chipset_vendor_hisilicon, + [cpuinfo_arm_chipset_series_actions_atm] = cpuinfo_arm_chipset_vendor_actions, + [cpuinfo_arm_chipset_series_allwinner_a] = cpuinfo_arm_chipset_vendor_allwinner, + [cpuinfo_arm_chipset_series_amlogic_aml] = cpuinfo_arm_chipset_vendor_amlogic, + [cpuinfo_arm_chipset_series_amlogic_s] = cpuinfo_arm_chipset_vendor_amlogic, + [cpuinfo_arm_chipset_series_broadcom_bcm] = cpuinfo_arm_chipset_vendor_broadcom, + [cpuinfo_arm_chipset_series_lg_nuclun] = cpuinfo_arm_chipset_vendor_lg, + [cpuinfo_arm_chipset_series_leadcore_lc] = cpuinfo_arm_chipset_vendor_leadcore, + [cpuinfo_arm_chipset_series_marvell_pxa] = cpuinfo_arm_chipset_vendor_marvell, + [cpuinfo_arm_chipset_series_mstar_6a] = cpuinfo_arm_chipset_vendor_mstar, + [cpuinfo_arm_chipset_series_novathor_u] = cpuinfo_arm_chipset_vendor_novathor, + [cpuinfo_arm_chipset_series_nvidia_tegra_t] = cpuinfo_arm_chipset_vendor_nvidia, + [cpuinfo_arm_chipset_series_nvidia_tegra_ap] = cpuinfo_arm_chipset_vendor_nvidia, + [cpuinfo_arm_chipset_series_nvidia_tegra_sl] = cpuinfo_arm_chipset_vendor_nvidia, + [cpuinfo_arm_chipset_series_pinecone_surge_s] = cpuinfo_arm_chipset_vendor_pinecone, + [cpuinfo_arm_chipset_series_renesas_mp] = cpuinfo_arm_chipset_vendor_renesas, + [cpuinfo_arm_chipset_series_rockchip_rk] = cpuinfo_arm_chipset_vendor_rockchip, + [cpuinfo_arm_chipset_series_spreadtrum_sc] = cpuinfo_arm_chipset_vendor_spreadtrum, + [cpuinfo_arm_chipset_series_telechips_tcc] = cpuinfo_arm_chipset_vendor_telechips, [cpuinfo_arm_chipset_series_texas_instruments_omap] = cpuinfo_arm_chipset_vendor_texas_instruments, - [cpuinfo_arm_chipset_series_unisoc_t] = cpuinfo_arm_chipset_vendor_unisoc, - [cpuinfo_arm_chipset_series_wondermedia_wm] = cpuinfo_arm_chipset_vendor_wondermedia, + [cpuinfo_arm_chipset_series_unisoc_t] = cpuinfo_arm_chipset_vendor_unisoc, + [cpuinfo_arm_chipset_series_wondermedia_wm] = cpuinfo_arm_chipset_vendor_wondermedia, }; /** - * Tries to match /(MSM|APQ)\d{4}([A-Z\-]*)/ signature (case-insensitive) for Qualcomm MSM and APQ chipsets. - * If match successful, extracts model information into \p chipset argument. + * Tries to match /(MSM|APQ)\d{4}([A-Z\-]*)/ signature (case-insensitive) for + * Qualcomm MSM and APQ chipsets. If match successful, extracts model + * information into \p chipset argument. * - * @param start - start of the platform identifier (/proc/cpuinfo Hardware string, ro.product.board, ro.board.platform - * or ro.chipname) to match. - * @param end - end of the platform identifier (/proc/cpuinfo Hardware string, ro.product.board, ro.board.platform or - * ro.chipname) to match. - * @param[out] chipset - location where chipset information will be stored upon a successful match. + * @param start - start of the platform identifier (/proc/cpuinfo Hardware + * string, ro.product.board, ro.board.platform or ro.chipname) to match. + * @param end - end of the platform identifier (/proc/cpuinfo Hardware string, + * ro.product.board, ro.board.platform or ro.chipname) to match. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match. * * @returns true if signature matched, false otherwise. */ -static bool match_msm_apq( - const char* start, const char* end, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ +static bool match_msm_apq(const char* start, const char* end, struct cpuinfo_arm_chipset chipset[restrict static 1]) { /* Expect at least 7 symbols: 3 symbols "MSM" or "APQ" + 4 digits */ if (start + 7 > end) { return false; } /* Check that string starts with "MSM" or "APQ", case-insensitive. - * The first three characters are loaded as 24-bit little endian word, binary ORed with 0x20 to convert to lower - * case, and compared to "MSM" and "APQ" strings as integers. + * The first three characters are loaded as 24-bit little endian word, + * binary ORed with 0x20 to convert to lower case, and compared to "MSM" + * and "APQ" strings as integers. */ const uint32_t series_signature = UINT32_C(0x00202020) | load_u24le(start); enum cpuinfo_arm_chipset_series series; @@ -140,7 +140,7 @@ static bool match_msm_apq( /* Validate and parse 4-digit model number */ uint32_t model = 0; for (uint32_t i = 0; i < 4; i++) { - const uint32_t digit = (uint32_t) (uint8_t) (*pos++) - '0'; + const uint32_t digit = (uint32_t)(uint8_t)(*pos++) - '0'; if (digit >= 10) { /* Not really a digit */ return false; @@ -148,8 +148,9 @@ static bool match_msm_apq( model = model * 10 + digit; } - /* Suffix is optional, so if we got to this point, parsing is successful. Commit parsed chipset. */ - *chipset = (struct cpuinfo_arm_chipset) { + /* Suffix is optional, so if we got to this point, parsing is + * successful. Commit parsed chipset. */ + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_qualcomm, .series = series, .model = model, @@ -182,21 +183,20 @@ static bool match_msm_apq( * * @param start - start of the /proc/cpuinfo Hardware string to match. * @param end - end of the /proc/cpuinfo Hardware string to match. - * @param[out] chipset - location where chipset information will be stored upon a successful match. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match. * * @returns true if signature matched, false otherwise. */ -static bool match_sdm( - const char* start, const char* end, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ +static bool match_sdm(const char* start, const char* end, struct cpuinfo_arm_chipset chipset[restrict static 1]) { /* Expect exactly 6 symbols: 3 symbols "SDM" + 3 digits */ if (start + 6 != end) { return false; } /* Check that string starts with "SDM". - * The first three characters are loaded and compared as 24-bit little endian word. + * The first three characters are loaded and compared as 24-bit little + * endian word. */ const uint32_t expected_sdm = load_u24le(start); if (expected_sdm != UINT32_C(0x004D4453) /* "MDS" = reverse("SDM") */) { @@ -206,7 +206,7 @@ static bool match_sdm( /* Validate and parse 3-digit model number */ uint32_t model = 0; for (uint32_t i = 3; i < 6; i++) { - const uint32_t digit = (uint32_t) (uint8_t) start[i] - '0'; + const uint32_t digit = (uint32_t)(uint8_t)start[i] - '0'; if (digit >= 10) { /* Not really a digit */ return false; @@ -215,7 +215,7 @@ static bool match_sdm( } /* Return parsed chipset. */ - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_qualcomm, .series = cpuinfo_arm_chipset_series_qualcomm_snapdragon, .model = model, @@ -229,21 +229,20 @@ static bool match_sdm( * * @param start - start of the /proc/cpuinfo Hardware string to match. * @param end - end of the /proc/cpuinfo Hardware string to match. - * @param[out] chipset - location where chipset information will be stored upon a successful match. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match. * * @returns true if signature matched, false otherwise. */ -static bool match_sm( - const char* start, const char* end, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ +static bool match_sm(const char* start, const char* end, struct cpuinfo_arm_chipset chipset[restrict static 1]) { /* Expect exactly 6 symbols: 2 symbols "SM" + 4 digits */ if (start + 6 != end) { return false; } /* Check that string starts with "SM". - * The first three characters are loaded and compared as 16-bit little endian word. + * The first three characters are loaded and compared as 16-bit little + * endian word. */ const uint32_t expected_sm = load_u16le(start); if (expected_sm != UINT16_C(0x4D53) /* "MS" = reverse("SM") */) { @@ -253,7 +252,7 @@ static bool match_sm( /* Validate and parse 4-digit model number */ uint32_t model = 0; for (uint32_t i = 2; i < 6; i++) { - const uint32_t digit = (uint32_t) (uint8_t) start[i] - '0'; + const uint32_t digit = (uint32_t)(uint8_t)start[i] - '0'; if (digit >= 10) { /* Not really a digit */ return false; @@ -262,7 +261,7 @@ static bool match_sm( } /* Return parsed chipset. */ - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_qualcomm, .series = cpuinfo_arm_chipset_series_qualcomm_snapdragon, .model = model, @@ -271,22 +270,25 @@ static bool match_sm( } /** - * Tries to match /Samsung Exynos\d{4}$/ signature (case-insensitive) for Samsung Exynos chipsets. - * If match successful, extracts model information into \p chipset argument. + * Tries to match /Samsung Exynos\d{4}$/ signature (case-insensitive) for + * Samsung Exynos chipsets. If match successful, extracts model information into + * \p chipset argument. * * @param start - start of the /proc/cpuinfo Hardware string to match. * @param end - end of the /proc/cpuinfo Hardware string to match. - * @param[out] chipset - location where chipset information will be stored upon a successful match. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match. * * @returns true if signature matched, false otherwise. */ static bool match_samsung_exynos( - const char* start, const char* end, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ + const char* start, + const char* end, + struct cpuinfo_arm_chipset chipset[restrict static 1]) { /* * Expect at 18-19 symbols: - * - "Samsung" (7 symbols) + space + "Exynos" (6 symbols) + optional space 4-digit model number + * - "Samsung" (7 symbols) + space + "Exynos" (6 symbols) + optional + * space 4-digit model number */ const size_t length = end - start; switch (length) { @@ -299,8 +301,9 @@ static bool match_samsung_exynos( /* * Check that the string starts with "samsung exynos", case-insensitive. - * Blocks of 4 characters are loaded and compared as little-endian 32-bit word. - * Case-insensitive characters are binary ORed with 0x20 to convert them to lowercase. + * Blocks of 4 characters are loaded and compared as little-endian + * 32-bit word. Case-insensitive characters are binary ORed with 0x20 to + * convert them to lowercase. */ const uint32_t expected_sams = UINT32_C(0x20202000) | load_u32le(start); if (expected_sams != UINT32_C(0x736D6153) /* "smaS" = reverse("Sams") */) { @@ -325,7 +328,8 @@ static bool match_samsung_exynos( if (*pos == ' ') { pos++; - /* If optional space if present, we expect exactly 19 characters */ + /* If optional space if present, we expect exactly 19 characters + */ if (length != 19) { return false; } @@ -334,7 +338,7 @@ static bool match_samsung_exynos( /* Validate and parse 4-digit model number */ uint32_t model = 0; for (uint32_t i = 0; i < 4; i++) { - const uint32_t digit = (uint32_t) (uint8_t) (*pos++) - '0'; + const uint32_t digit = (uint32_t)(uint8_t)(*pos++) - '0'; if (digit >= 10) { /* Not really a digit */ return false; @@ -343,7 +347,7 @@ static bool match_samsung_exynos( } /* Return parsed chipset */ - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_samsung, .series = cpuinfo_arm_chipset_series_samsung_exynos, .model = model, @@ -355,37 +359,38 @@ static bool match_samsung_exynos( * Tries to match /exynos\d{4}$/ signature for Samsung Exynos chipsets. * If match successful, extracts model information into \p chipset argument. * - * @param start - start of the platform identifier (ro.board.platform or ro.chipname) to match. - * @param end - end of the platform identifier (ro.board.platform or ro.chipname) to match. - * @param[out] chipset - location where chipset information will be stored upon a successful match. + * @param start - start of the platform identifier (ro.board.platform or + * ro.chipname) to match. + * @param end - end of the platform identifier (ro.board.platform or + * ro.chipname) to match. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match. * * @returns true if signature matched, false otherwise. */ -static bool match_exynos( - const char* start, const char* end, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ - /* Expect exactly 10 symbols: "exynos" (6 symbols) + 4-digit model number */ +static bool match_exynos(const char* start, const char* end, struct cpuinfo_arm_chipset chipset[restrict static 1]) { + /* Expect exactly 10 symbols: "exynos" (6 symbols) + 4-digit model + * number */ if (start + 10 != end) { return false; } /* Load first 4 bytes as little endian 32-bit word */ const uint32_t expected_exyn = load_u32le(start); - if (expected_exyn != UINT32_C(0x6E797865) /* "nyxe" = reverse("exyn") */ ) { + if (expected_exyn != UINT32_C(0x6E797865) /* "nyxe" = reverse("exyn") */) { return false; } /* Load next 2 bytes as little endian 16-bit word */ const uint16_t expected_os = load_u16le(start + 4); - if (expected_os != UINT16_C(0x736F) /* "so" = reverse("os") */ ) { + if (expected_os != UINT16_C(0x736F) /* "so" = reverse("os") */) { return false; } /* Check and parse 4-digit model number */ uint32_t model = 0; for (uint32_t i = 6; i < 10; i++) { - const uint32_t digit = (uint32_t) (uint8_t) start[i] - '0'; + const uint32_t digit = (uint32_t)(uint8_t)start[i] - '0'; if (digit >= 10) { /* Not really a digit */ return false; @@ -394,7 +399,7 @@ static bool match_exynos( } /* Return parsed chipset. */ - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_samsung, .series = cpuinfo_arm_chipset_series_samsung_exynos, .model = model, @@ -406,34 +411,35 @@ static bool match_exynos( * Tries to match /universal\d{4}$/ signature for Samsung Exynos chipsets. * If match successful, extracts model information into \p chipset argument. * - * @param start - start of the platform identifier (/proc/cpuinfo Hardware string, ro.product.board or ro.chipname) - * to match. - * @param end - end of the platform identifier (/proc/cpuinfo Hardware string, ro.product.board or ro.chipname) - * to match. - * @param[out] chipset - location where chipset information will be stored upon a successful match. + * @param start - start of the platform identifier (/proc/cpuinfo Hardware + * string, ro.product.board or ro.chipname) to match. + * @param end - end of the platform identifier (/proc/cpuinfo Hardware string, + * ro.product.board or ro.chipname) to match. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match. * * @returns true if signature matched, false otherwise. */ -static bool match_universal( - const char* start, const char* end, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ - /* Expect exactly 13 symbols: "universal" (9 symbols) + 4-digit model number */ +static bool match_universal(const char* start, const char* end, struct cpuinfo_arm_chipset chipset[restrict static 1]) { + /* Expect exactly 13 symbols: "universal" (9 symbols) + 4-digit model + * number + */ if (start + 13 != end) { return false; } /* * Check that the string starts with "universal". - * Blocks of 4 characters are loaded and compared as little-endian 32-bit word. - * Case-insensitive characters are binary ORed with 0x20 to convert them to lowercase. + * Blocks of 4 characters are loaded and compared as little-endian + * 32-bit word. Case-insensitive characters are binary ORed with 0x20 to + * convert them to lowercase. */ - const uint8_t expected_u = UINT8_C(0x20) | (uint8_t) start[0]; + const uint8_t expected_u = UINT8_C(0x20) | (uint8_t)start[0]; if (expected_u != UINT8_C(0x75) /* "u" */) { return false; } const uint32_t expected_nive = UINT32_C(0x20202020) | load_u32le(start + 1); - if (expected_nive != UINT32_C(0x6576696E) /* "evin" = reverse("nive") */ ) { + if (expected_nive != UINT32_C(0x6576696E) /* "evin" = reverse("nive") */) { return false; } const uint32_t expected_ersa = UINT32_C(0x20202020) | load_u32le(start + 5); @@ -444,7 +450,7 @@ static bool match_universal( /* Validate and parse 4-digit model number */ uint32_t model = 0; for (uint32_t i = 9; i < 13; i++) { - const uint32_t digit = (uint32_t) (uint8_t) start[i] - '0'; + const uint32_t digit = (uint32_t)(uint8_t)start[i] - '0'; if (digit >= 10) { /* Not really a digit */ return false; @@ -453,7 +459,7 @@ static bool match_universal( } /* Return parsed chipset. */ - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_samsung, .series = cpuinfo_arm_chipset_series_samsung_exynos, .model = model, @@ -462,29 +468,36 @@ static bool match_universal( } /** - * Compares, case insensitively, a string to known values "SMDK4210" and "SMDK4x12" for Samsung Exynos chipsets. - * If platform identifier matches one of the SMDK* values, extracts model information into \p chipset argument. - * For "SMDK4x12" match, decodes the chipset name using number of cores. + * Compares, case insensitively, a string to known values "SMDK4210" and + * "SMDK4x12" for Samsung Exynos chipsets. If platform identifier matches one of + * the SMDK* values, extracts model information into \p chipset argument. For + * "SMDK4x12" match, decodes the chipset name using number of cores. * - * @param start - start of the platform identifier (/proc/cpuinfo Hardware string or ro.product.board) to match. - * @param end - end of the platform identifier (/proc/cpuinfo Hardware string or ro.product.board) to match. + * @param start - start of the platform identifier (/proc/cpuinfo Hardware + * string or ro.product.board) to match. + * @param end - end of the platform identifier (/proc/cpuinfo Hardware string or + * ro.product.board) to match. * @param cores - number of cores in the chipset. - * @param[out] chipset - location where chipset information will be stored upon a successful match. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match. * * @returns true if signature matched, false otherwise. */ static bool match_and_parse_smdk( - const char* start, const char* end, uint32_t cores, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ - /* Expect exactly 8 symbols: "SMDK" (4 symbols) + 4-digit model number */ + const char* start, + const char* end, + uint32_t cores, + struct cpuinfo_arm_chipset chipset[restrict static 1]) { + /* Expect exactly 8 symbols: "SMDK" (4 symbols) + 4-digit model number + */ if (start + 8 != end) { return false; } /* * Check that string starts with "MT" (case-insensitive). - * The first four characters are loaded as a 32-bit little endian word and converted to lowercase. + * The first four characters are loaded as a 32-bit little endian word + * and converted to lowercase. */ const uint32_t expected_smdk = UINT32_C(0x20202020) | load_u32le(start); if (expected_smdk != UINT32_C(0x6B646D73) /* "kdms" = reverse("smdk") */) { @@ -493,7 +506,8 @@ static bool match_and_parse_smdk( /* * Check that string ends with "4210" or "4x12". - * The last four characters are loaded and compared as a 32-bit little endian word. + * The last four characters are loaded and compared as a 32-bit little + * endian word. */ uint32_t model = 0; const uint32_t expected_model = load_u32le(start + 4); @@ -510,7 +524,8 @@ static bool match_and_parse_smdk( model = 4412; break; default: - cpuinfo_log_warning("system reported invalid %"PRIu32"-core Exynos 4x12 chipset", cores); + cpuinfo_log_warning( + "system reported invalid %" PRIu32 "-core Exynos 4x12 chipset", cores); } } @@ -518,7 +533,7 @@ static bool match_and_parse_smdk( return false; } - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_samsung, .series = cpuinfo_arm_chipset_series_samsung_exynos, .model = model, @@ -530,21 +545,26 @@ static bool match_and_parse_smdk( * Tries to match /MTK?\d{4}[A-Z/]*$/ signature for MediaTek MT chipsets. * If match successful, extracts model information into \p chipset argument. * - * @param start - start of the platform identifier (/proc/cpuinfo Hardware string, ro.product.board, ro.board.platform, - * ro.mediatek.platform, or ro.chipname) to match. - * @param end - end of the platform identifier (/proc/cpuinfo Hardware string, ro.product.board, ro.board.platform, - * ro.mediatek.platform, or ro.chipname) to match. - * @param match_end - indicates if the function should attempt to match through the end of the string and fail if there - * are unparsed characters in the end, or match only MTK signature, model number, and some of the - * suffix characters (the ones that pass validation). - * @param[out] chipset - location where chipset information will be stored upon a successful match. + * @param start - start of the platform identifier (/proc/cpuinfo Hardware + * string, ro.product.board, ro.board.platform, ro.mediatek.platform, or + * ro.chipname) to match. + * @param end - end of the platform identifier (/proc/cpuinfo Hardware string, + * ro.product.board, ro.board.platform, ro.mediatek.platform, or ro.chipname) to + * match. + * @param match_end - indicates if the function should attempt to match through + * the end of the string and fail if there are unparsed characters in the end, + * or match only MTK signature, model number, and some of the suffix characters + * (the ones that pass validation). + * @param[out] chipset - location where chipset information will be stored upon + * a successful match. * * @returns true if signature matched, false otherwise. */ static bool match_mt( - const char* start, const char* end, bool match_end, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ + const char* start, + const char* end, + bool match_end, + struct cpuinfo_arm_chipset chipset[restrict static 1]) { /* Expect at least 6 symbols: "MT" (2 symbols) + 4-digit model number */ if (start + 6 > end) { return false; @@ -552,17 +572,17 @@ static bool match_mt( /* * Check that string starts with "MT" (case-insensitive). - * The first two characters are loaded as 16-bit little endian word and converted to lowercase. + * The first two characters are loaded as 16-bit little endian word and + * converted to lowercase. */ const uint16_t mt = UINT16_C(0x2020) | load_u16le(start); if (mt != UINT16_C(0x746D) /* "tm" */) { return false; } - /* Some images report "MTK" rather than "MT" */ const char* pos = start + 2; - if (((uint8_t) *pos | UINT8_C(0x20)) == (uint8_t) 'k') { + if (((uint8_t)*pos | UINT8_C(0x20)) == (uint8_t)'k') { pos++; /* Expect 4 more symbols after "MTK" (4-digit model number) */ @@ -574,7 +594,7 @@ static bool match_mt( /* Validate and parse 4-digit model number */ uint32_t model = 0; for (uint32_t i = 0; i < 4; i++) { - const uint32_t digit = (uint32_t) (uint8_t) (*pos++) - '0'; + const uint32_t digit = (uint32_t)(uint8_t)(*pos++) - '0'; if (digit >= 10) { /* Not really a digit */ return false; @@ -582,31 +602,36 @@ static bool match_mt( model = model * 10 + digit; } - /* Record parsed chipset. This implicitly zeroes-out suffix, which will be parsed later. */ - *chipset = (struct cpuinfo_arm_chipset) { + /* Record parsed chipset. This implicitly zeroes-out suffix, which will + * be parsed later. */ + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_mediatek, .series = cpuinfo_arm_chipset_series_mediatek_mt, .model = model, }; if (match_end) { - /* Check that the potential suffix does not exceed maximum length */ + /* Check that the potential suffix does not exceed maximum + * length */ const size_t suffix_length = end - pos; if (suffix_length > CPUINFO_ARM_CHIPSET_SUFFIX_MAX) { return false; } - /* Validate suffix characters and copy them to chipset structure */ + /* Validate suffix characters and copy them to chipset structure + */ for (size_t i = 0; i < suffix_length; i++) { const char c = (*pos++); if (is_ascii_alphabetic(c)) { - /* Matched a letter [A-Za-z], convert to uppercase */ + /* Matched a letter [A-Za-z], convert to + * uppercase */ chipset->suffix[i] = c & '\xDF'; } else if (c == '/') { /* Matched a slash '/' */ chipset->suffix[i] = c; } else { - /* Invalid suffix character (neither of [A-Za-z/]) */ + /* Invalid suffix character (neither of + * [A-Za-z/]) */ return false; } } @@ -619,18 +644,22 @@ static bool match_mt( const char c = pos[i]; if (is_ascii_alphabetic(c)) { - /* Matched a letter [A-Za-z], convert to uppercase */ + /* Matched a letter [A-Za-z], convert to + * uppercase */ chipset->suffix[i] = c & '\xDF'; } else if (c == '/') { /* Matched a slash '/' */ chipset->suffix[i] = c; } else { - /* Invalid suffix character (neither of [A-Za-z/]). This marks the end of the suffix. */ + /* Invalid suffix character (neither of + * [A-Za-z/]). This marks the end of the suffix. + */ break; } } } - /* All suffix characters successfully validated and copied to chipset data */ + /* All suffix characters successfully validated and copied to chipset + * data */ return true; } @@ -640,15 +669,14 @@ static bool match_mt( * * @param start - start of the /proc/cpuinfo Hardware string to match. * @param end - end of the /proc/cpuinfo Hardware string to match. - * @param[out] chipset - location where chipset information will be stored upon a successful match. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match. * * @returns true if signature matched, false otherwise. */ -static bool match_kirin( - const char* start, const char* end, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ - /* Expect 8-9 symbols: "Kirin" (5 symbols) + optional whitespace (1 symbol) + 3-digit model number */ +static bool match_kirin(const char* start, const char* end, struct cpuinfo_arm_chipset chipset[restrict static 1]) { + /* Expect 8-9 symbols: "Kirin" (5 symbols) + optional whitespace (1 + * symbol) + 3-digit model number */ const size_t length = end - start; switch (length) { case 8: @@ -659,7 +687,7 @@ static bool match_kirin( } /* Check that the string starts with "Kirin" or "kirin". */ - if (((uint8_t) start[0] | UINT8_C(0x20)) != (uint8_t) 'k') { + if (((uint8_t)start[0] | UINT8_C(0x20)) != (uint8_t)'k') { return false; } /* Symbols 1-5 are loaded and compared as little-endian 32-bit word. */ @@ -670,7 +698,8 @@ static bool match_kirin( /* Check for optional whitespace after "Kirin" */ if (is_ascii_whitespace(start[5])) { - /* When whitespace is present after "Kirin", expect 9 symbols total */ + /* When whitespace is present after "Kirin", expect 9 symbols + * total */ if (length != 9) { return false; } @@ -679,7 +708,7 @@ static bool match_kirin( /* Validate and parse 3-digit model number */ uint32_t model = 0; for (int32_t i = 0; i < 3; i++) { - const uint32_t digit = (uint32_t) (uint8_t) end[i - 3] - '0'; + const uint32_t digit = (uint32_t)(uint8_t)end[i - 3] - '0'; if (digit >= 10) { /* Not really a digit */ return false; @@ -689,10 +718,11 @@ static bool match_kirin( /* * Thats it, return parsed chipset. - * Technically, Kirin 910T has a suffix, but it never appears in the form of "910T" string. - * Instead, Kirin 910T devices report "hi6620oem" string (handled outside of this function). + * Technically, Kirin 910T has a suffix, but it never appears in the + * form of "910T" string. Instead, Kirin 910T devices report "hi6620oem" + * string (handled outside of this function). */ - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_hisilicon, .series = cpuinfo_arm_chipset_series_hisilicon_kirin, .model = model, @@ -704,17 +734,18 @@ static bool match_kirin( * Tries to match /rk\d{4}[a-z]?$/ signature for Rockchip RK chipsets. * If match successful, extracts model information into \p chipset argument. * - * @param start - start of the platform identifier (/proc/cpuinfo Hardware string or ro.board.platform) to match. - * @param end - end of the platform identifier (/proc/cpuinfo Hardware string or ro.board.platform) to match. - * @param[out] chipset - location where chipset information will be stored upon a successful match. + * @param start - start of the platform identifier (/proc/cpuinfo Hardware + * string or ro.board.platform) to match. + * @param end - end of the platform identifier (/proc/cpuinfo Hardware string or + * ro.board.platform) to match. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match. * * @returns true if signature matched, false otherwise. */ -static bool match_rk( - const char* start, const char* end, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ - /* Expect 6-7 symbols: "RK" (2 symbols) + 4-digit model number + optional 1-letter suffix */ +static bool match_rk(const char* start, const char* end, struct cpuinfo_arm_chipset chipset[restrict static 1]) { + /* Expect 6-7 symbols: "RK" (2 symbols) + 4-digit model number + + * optional 1-letter suffix */ const size_t length = end - start; switch (length) { case 6: @@ -726,7 +757,8 @@ static bool match_rk( /* * Check that string starts with "RK" (case-insensitive). - * The first two characters are loaded as 16-bit little endian word and converted to lowercase. + * The first two characters are loaded as 16-bit little endian word and + * converted to lowercase. */ const uint16_t expected_rk = UINT16_C(0x2020) | load_u16le(start); if (expected_rk != UINT16_C(0x6B72) /* "kr" = reverse("rk") */) { @@ -736,7 +768,7 @@ static bool match_rk( /* Validate and parse 4-digit model number */ uint32_t model = 0; for (uint32_t i = 2; i < 6; i++) { - const uint32_t digit = (uint32_t) (uint8_t) start[i] - '0'; + const uint32_t digit = (uint32_t)(uint8_t)start[i] - '0'; if (digit >= 10) { /* Not really a digit */ return false; @@ -759,33 +791,33 @@ static bool match_rk( } /* Return parsed chipset */ - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_rockchip, .series = cpuinfo_arm_chipset_series_rockchip_rk, .model = model, - .suffix = { - [0] = suffix, - }, + .suffix = + { + [0] = suffix, + }, }; return true; } /** - * Tries to match, case-insentitively, /s[cp]\d{4}[a-z]*|scx15$/ signature for Spreadtrum SC chipsets. - * If match successful, extracts model information into \p chipset argument. + * Tries to match, case-insentitively, /s[cp]\d{4}[a-z]*|scx15$/ signature for + * Spreadtrum SC chipsets. If match successful, extracts model information into + * \p chipset argument. * - * @param start - start of the platform identifier (/proc/cpuinfo Hardware string, ro.product.board, - * ro.board.platform, or ro.chipname) to match. - * @param end - end of the platform identifier (/proc/cpuinfo Hardware string, ro.product.board, - * ro.board.platform, or ro.chipname) to match. - * @param[out] chipset - location where chipset information will be stored upon a successful match. + * @param start - start of the platform identifier (/proc/cpuinfo Hardware + * string, ro.product.board, ro.board.platform, or ro.chipname) to match. + * @param end - end of the platform identifier (/proc/cpuinfo Hardware string, + * ro.product.board, ro.board.platform, or ro.chipname) to match. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match. * * @returns true if signature matched, false otherwise. */ -static bool match_sc( - const char* start, const char* end, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ +static bool match_sc(const char* start, const char* end, struct cpuinfo_arm_chipset chipset[restrict static 1]) { /* Expect at least 5 symbols: "scx15" */ if (start + 5 > end) { return false; @@ -793,7 +825,8 @@ static bool match_sc( /* * Check that string starts with "S[CP]" (case-insensitive). - * The first two characters are loaded as 16-bit little endian word and converted to lowercase. + * The first two characters are loaded as 16-bit little endian word and + * converted to lowercase. */ const uint16_t expected_sc_or_sp = UINT16_C(0x2020) | load_u16le(start); switch (expected_sc_or_sp) { @@ -813,11 +846,11 @@ static bool match_sc( /* Check that string ends with "15" */ const uint16_t expected_15 = load_u16le(start + 3); - if (expected_15 != UINT16_C(0x3531) /* "51" = reverse("15") */ ) { + if (expected_15 != UINT16_C(0x3531) /* "51" = reverse("15") */) { return false; } - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_spreadtrum, .series = cpuinfo_arm_chipset_series_spreadtrum_sc, .model = 7715, @@ -825,7 +858,8 @@ static bool match_sc( return true; } - /* Expect at least 6 symbols: "S[CP]" (2 symbols) + 4-digit model number */ + /* Expect at least 6 symbols: "S[CP]" (2 symbols) + 4-digit model number + */ if (start + 6 > end) { return false; } @@ -833,7 +867,7 @@ static bool match_sc( /* Validate and parse 4-digit model number */ uint32_t model = 0; for (uint32_t i = 2; i < 6; i++) { - const uint32_t digit = (uint32_t) (uint8_t) start[i] - '0'; + const uint32_t digit = (uint32_t)(uint8_t)start[i] - '0'; if (digit >= 10) { /* Not really a digit */ return false; @@ -842,13 +876,14 @@ static bool match_sc( } /* Write parsed chipset */ - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_spreadtrum, .series = cpuinfo_arm_chipset_series_spreadtrum_sc, .model = model, }; - /* Validate and copy suffix letters. If suffix is too long, truncate at CPUINFO_ARM_CHIPSET_SUFFIX_MAX letters. */ + /* Validate and copy suffix letters. If suffix is too long, truncate at + * CPUINFO_ARM_CHIPSET_SUFFIX_MAX letters. */ const char* suffix = start + 6; for (size_t i = 0; i < CPUINFO_ARM_CHIPSET_SUFFIX_MAX; i++) { if (suffix + i == end) { @@ -867,22 +902,22 @@ static bool match_sc( } /** - * Tries to match, case-sentitively, /Unisoc T\d{3,4}/ signature for Unisoc T chipset. - * If match successful, extracts model information into \p chipset argument. + * Tries to match, case-sentitively, /Unisoc T\d{3,4}/ signature for Unisoc T + * chipset. If match successful, extracts model information into \p chipset + * argument. * - * @param start - start of the platform identifier (/proc/cpuinfo Hardware string, ro.product.board, - * ro.board.platform, or ro.chipname) to match. - * @param end - end of the platform identifier (/proc/cpuinfo Hardware string, ro.product.board, - * ro.board.platform, or ro.chipname) to match. - * @param[out] chipset - location where chipset information will be stored upon a successful match. + * @param start - start of the platform identifier (/proc/cpuinfo Hardware + * string, ro.product.board, ro.board.platform, or ro.chipname) to match. + * @param end - end of the platform identifier (/proc/cpuinfo Hardware string, + * ro.product.board, ro.board.platform, or ro.chipname) to match. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match. * * @returns true if signature matched, false otherwise. */ -static bool match_t( - const char* start, const char* end, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ - /* Expect 11-12 symbols: "Unisoc T" (8 symbols) + 3-4-digit model number */ +static bool match_t(const char* start, const char* end, struct cpuinfo_arm_chipset chipset[restrict static 1]) { + /* Expect 11-12 symbols: "Unisoc T" (8 symbols) + 3-4-digit model number + */ const size_t length = end - start; switch (length) { case 11: @@ -892,7 +927,8 @@ static bool match_t( return false; } - /* Check that string starts with "Unisoc T". The first four characters are loaded as 32-bit little endian word */ + /* Check that string starts with "Unisoc T". The first four characters + * are loaded as 32-bit little endian word */ const uint32_t expected_unis = load_u32le(start); if (expected_unis != UINT32_C(0x73696E55) /* "sinU" = reverse("Unis") */) { return false; @@ -907,7 +943,7 @@ static bool match_t( /* Validate and parse 3-4 digit model number */ uint32_t model = 0; for (uint32_t i = 8; i < length; i++) { - const uint32_t digit = (uint32_t) (uint8_t) start[i] - '0'; + const uint32_t digit = (uint32_t)(uint8_t)start[i] - '0'; if (digit >= 10) { /* Not really a digit */ return false; @@ -915,7 +951,7 @@ static bool match_t( model = model * 10 + digit; } - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_unisoc, .series = cpuinfo_arm_chipset_series_unisoc_t, .model = model, @@ -927,17 +963,18 @@ static bool match_t( * Tries to match /lc\d{4}[a-z]?$/ signature for Leadcore LC chipsets. * If match successful, extracts model information into \p chipset argument. * - * @param start - start of the platform identifier (ro.product.board or ro.board.platform) to match. - * @param end - end of the platform identifier (ro.product.board or ro.board.platform) to match. - * @param[out] chipset - location where chipset information will be stored upon a successful match. + * @param start - start of the platform identifier (ro.product.board or + * ro.board.platform) to match. + * @param end - end of the platform identifier (ro.product.board or + * ro.board.platform) to match. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match. * * @returns true if signature matched, false otherwise. */ -static bool match_lc( - const char* start, const char* end, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ - /* Expect 6-7 symbols: "lc" (2 symbols) + 4-digit model number + optional 1-letter suffix */ +static bool match_lc(const char* start, const char* end, struct cpuinfo_arm_chipset chipset[restrict static 1]) { + /* Expect 6-7 symbols: "lc" (2 symbols) + 4-digit model number + + * optional 1-letter suffix */ const size_t length = end - start; switch (length) { case 6: @@ -947,7 +984,8 @@ static bool match_lc( return false; } - /* Check that string starts with "lc". The first two characters are loaded as 16-bit little endian word */ + /* Check that string starts with "lc". The first two characters are + * loaded as 16-bit little endian word */ const uint16_t expected_lc = load_u16le(start); if (expected_lc != UINT16_C(0x636C) /* "cl" = reverse("lc") */) { return false; @@ -956,7 +994,7 @@ static bool match_lc( /* Validate and parse 4-digit model number */ uint32_t model = 0; for (uint32_t i = 2; i < 6; i++) { - const uint32_t digit = (uint32_t) (uint8_t) start[i] - '0'; + const uint32_t digit = (uint32_t)(uint8_t)start[i] - '0'; if (digit >= 10) { /* Not really a digit */ return false; @@ -978,13 +1016,14 @@ static bool match_lc( } /* Return parsed chipset */ - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_leadcore, .series = cpuinfo_arm_chipset_series_leadcore_lc, .model = model, - .suffix = { - [0] = suffix, - }, + .suffix = + { + [0] = suffix, + }, }; return true; } @@ -993,18 +1032,16 @@ static bool match_lc( * Tries to match /PXA(\d{3,4}|1L88)$/ signature for Marvell PXA chipsets. * If match successful, extracts model information into \p chipset argument. * - * @param start - start of the platform identifier (/proc/cpuinfo Hardware string, ro.product.board or ro.chipname) - * to match. - * @param end - end of the platform identifier (/proc/cpuinfo Hardaware string, ro.product.board or ro.chipname) to - * match. - * @param[out] chipset - location where chipset information will be stored upon a successful match. + * @param start - start of the platform identifier (/proc/cpuinfo Hardware + * string, ro.product.board or ro.chipname) to match. + * @param end - end of the platform identifier (/proc/cpuinfo Hardaware string, + * ro.product.board or ro.chipname) to match. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match. * * @returns true if signature matched, false otherwise. */ -static bool match_pxa( - const char* start, const char* end, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ +static bool match_pxa(const char* start, const char* end, struct cpuinfo_arm_chipset chipset[restrict static 1]) { /* Expect 6-7 symbols: "PXA" (3 symbols) + 3-4 digit model number */ const size_t length = end - start; switch (length) { @@ -1015,7 +1052,8 @@ static bool match_pxa( return false; } - /* Check that the string starts with "PXA". Symbols 1-3 are loaded and compared as little-endian 16-bit word. */ + /* Check that the string starts with "PXA". Symbols 1-3 are loaded and + * compared as little-endian 16-bit word. */ if (start[0] != 'P') { return false; } @@ -1026,10 +1064,10 @@ static bool match_pxa( uint32_t model = 0; - /* Check for a very common typo: "PXA1L88" for "PXA1088" */ if (length == 7) { - /* Load 4 model "number" symbols as a little endian 32-bit word and compare to "1L88" */ + /* Load 4 model "number" symbols as a little endian 32-bit word + * and compare to "1L88" */ const uint32_t expected_1L88 = load_u32le(start + 3); if (expected_1L88 == UINT32_C(0x38384C31) /* "88L1" = reverse("1L88") */) { model = 1088; @@ -1039,7 +1077,7 @@ static bool match_pxa( /* Check and parse 3-4 digit model number */ for (uint32_t i = 3; i < length; i++) { - const uint32_t digit = (uint32_t) (uint8_t) start[i] - '0'; + const uint32_t digit = (uint32_t)(uint8_t)start[i] - '0'; if (digit >= 10) { /* Not really a digit */ return false; @@ -1049,7 +1087,7 @@ static bool match_pxa( /* Return parsed chipset. */ write_chipset: - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_marvell, .series = cpuinfo_arm_chipset_series_marvell_pxa, .model = model, @@ -1063,21 +1101,20 @@ static bool match_pxa( * * @param start - start of the /proc/cpuinfo Hardware string to match. * @param end - end of the /proc/cpuinfo Hardware string to match. - * @param[out] chipset - location where chipset information will be stored upon a successful match. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match. * * @returns true if signature matched, false otherwise. */ -static bool match_bcm( - const char* start, const char* end, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ +static bool match_bcm(const char* start, const char* end, struct cpuinfo_arm_chipset chipset[restrict static 1]) { /* Expect exactly 7 symbols: "BCM" (3 symbols) + 4-digit model number */ if (start + 7 != end) { return false; } /* Check that the string starts with "BCM". - * The first three characters are loaded and compared as a 24-bit little endian word. + * The first three characters are loaded and compared as a 24-bit little + * endian word. */ const uint32_t expected_bcm = load_u24le(start); if (expected_bcm != UINT32_C(0x004D4342) /* "MCB" = reverse("BCM") */) { @@ -1087,7 +1124,7 @@ static bool match_bcm( /* Validate and parse 4-digit model number */ uint32_t model = 0; for (uint32_t i = 3; i < 7; i++) { - const uint32_t digit = (uint32_t) (uint8_t) start[i] - '0'; + const uint32_t digit = (uint32_t)(uint8_t)start[i] - '0'; if (digit >= 10) { /* Not really a digit */ return false; @@ -1096,7 +1133,7 @@ static bool match_bcm( } /* Return parsed chipset. */ - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_broadcom, .series = cpuinfo_arm_chipset_series_broadcom_bcm, .model = model, @@ -1110,20 +1147,20 @@ static bool match_bcm( * * @param start - start of the /proc/cpuinfo Hardware string to match. * @param end - end of the /proc/cpuinfo Hardware string to match. - * @param[out] chipset - location where chipset information will be stored upon a successful match. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match. * * @returns true if signature matched, false otherwise. */ -static bool match_omap( - const char* start, const char* end, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ - /* Expect exactly 8 symbols: "OMAP" (4 symbols) + 4-digit model number */ +static bool match_omap(const char* start, const char* end, struct cpuinfo_arm_chipset chipset[restrict static 1]) { + /* Expect exactly 8 symbols: "OMAP" (4 symbols) + 4-digit model number + */ if (start + 8 != end) { return false; } - /* Check that the string starts with "OMAP". Symbols 0-4 are loaded and compared as little-endian 32-bit word. */ + /* Check that the string starts with "OMAP". Symbols 0-4 are loaded and + * compared as little-endian 32-bit word. */ const uint32_t expected_omap = load_u32le(start); if (expected_omap != UINT32_C(0x50414D4F) /* "PAMO" = reverse("OMAP") */) { return false; @@ -1132,7 +1169,7 @@ static bool match_omap( /* Validate and parse 4-digit model number */ uint32_t model = 0; for (uint32_t i = 4; i < 8; i++) { - const uint32_t digit = (uint32_t) (uint8_t) start[i] - '0'; + const uint32_t digit = (uint32_t)(uint8_t)start[i] - '0'; if (digit >= 10) { /* Not really a digit */ return false; @@ -1141,7 +1178,7 @@ static bool match_omap( } /* Return parsed chipset. */ - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_texas_instruments, .series = cpuinfo_arm_chipset_series_texas_instruments_omap, .model = model, @@ -1151,22 +1188,30 @@ static bool match_omap( /** * Compares platform identifier string to known values for Broadcom chipsets. - * If the string matches one of the known values, the function decodes Broadcom chipset from frequency and number of - * cores into \p chipset argument. + * If the string matches one of the known values, the function decodes Broadcom + * chipset from frequency and number of cores into \p chipset argument. * - * @param start - start of the platform identifier (ro.product.board or ro.board.platform) to match. - * @param end - end of the platform identifier (ro.product.board or ro.board.platform) to match. + * @param start - start of the platform identifier (ro.product.board or + * ro.board.platform) to match. + * @param end - end of the platform identifier (ro.product.board or + * ro.board.platform) to match. * @param cores - number of cores in the chipset. - * @param max_cpu_freq_max - maximum of /sys/devices/system/cpu/cpu/cpofreq/cpu_freq_max values. - * @param[out] chipset - location where chipset information will be stored upon a successful match and decoding. + * @param max_cpu_freq_max - maximum of + * /sys/devices/system/cpu/cpu/cpofreq/cpu_freq_max values. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match and decoding. * - * @returns true if signature matched (even if exact model can't be decoded), false otherwise. + * @returns true if signature matched (even if exact model can't be decoded), + * false otherwise. */ static bool match_and_parse_broadcom( - const char* start, const char* end, uint32_t cores, uint32_t max_cpu_freq_max, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ - /* Expect 4-6 symbols: "java" (4 symbols), "rhea" (4 symbols), "capri" (5 symbols), or "hawaii" (6 symbols) */ + const char* start, + const char* end, + uint32_t cores, + uint32_t max_cpu_freq_max, + struct cpuinfo_arm_chipset chipset[restrict static 1]) { + /* Expect 4-6 symbols: "java" (4 symbols), "rhea" (4 symbols), "capri" + * (5 symbols), or "hawaii" (6 symbols) */ const size_t length = end - start; switch (length) { case 4: @@ -1178,12 +1223,14 @@ static bool match_and_parse_broadcom( } /* - * Compare the platform identifier to known values for Broadcom chipsets: + * Compare the platform identifier to known values for Broadcom + * chipsets: * - "rhea" * - "java" * - "capri" * - "hawaii" - * Upon a successful match, decode chipset name from frequency and number of cores. + * Upon a successful match, decode chipset name from frequency and + * number of cores. */ uint32_t model = 0; char suffix = 0; @@ -1219,7 +1266,7 @@ static bool match_and_parse_broadcom( if (length == 6) { /* Check that string equals "hawaii" */ const uint16_t expected_ii = load_u16le(start + 4); - if (expected_ii == UINT16_C(0x6969) /* "ii" */ ) { + if (expected_ii == UINT16_C(0x6969) /* "ii" */) { /* * Detected "hawaii" platform: * - 1 core -> BCM21663 @@ -1258,13 +1305,14 @@ static bool match_and_parse_broadcom( if (model != 0) { /* Chipset was successfully decoded */ - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_broadcom, .series = cpuinfo_arm_chipset_series_broadcom_bcm, .model = model, - .suffix = { - [0] = suffix, - }, + .suffix = + { + [0] = suffix, + }, }; } return model != 0; @@ -1339,22 +1387,27 @@ static const struct sunxi_map_entry sunxi_map_entries[] = { }; /** - * Tries to match /proc/cpuinfo Hardware string to Allwinner /sun\d+i/ signature. - * If the string matches signature, the function decodes Allwinner chipset from the number in the signature and the - * number of cores, and stores it in \p chipset argument. + * Tries to match /proc/cpuinfo Hardware string to Allwinner /sun\d+i/ + * signature. If the string matches signature, the function decodes Allwinner + * chipset from the number in the signature and the number of cores, and stores + * it in \p chipset argument. * * @param start - start of the /proc/cpuinfo Hardware string to match. * @param end - end of the /proc/cpuinfo Hardware string to match. * @param cores - number of cores in the chipset. - * @param[out] chipset - location where chipset information will be stored upon a successful match and decoding. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match and decoding. * - * @returns true if signature matched (even if exact model can't be decoded), false otherwise. + * @returns true if signature matched (even if exact model can't be decoded), + * false otherwise. */ static bool match_and_parse_sunxi( - const char* start, const char* end, uint32_t cores, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ - /* Expect at least 5 symbols: "sun" (3 symbols) + platform id (1-2 digits) + "i" (1 symbol) */ + const char* start, + const char* end, + uint32_t cores, + struct cpuinfo_arm_chipset chipset[restrict static 1]) { + /* Expect at least 5 symbols: "sun" (3 symbols) + platform id (1-2 + * digits) + "i" (1 symbol) */ if (start + 5 > end) { return false; } @@ -1368,10 +1421,11 @@ static bool match_and_parse_sunxi( return false; } - /* Check and parse the first (required) digit of the sunXi platform id */ + /* Check and parse the first (required) digit of the sunXi platform id + */ uint32_t sunxi_platform = 0; { - const uint32_t digit = (uint32_t) (uint8_t) start[3] - '0'; + const uint32_t digit = (uint32_t)(uint8_t)start[3] - '0'; if (digit >= 10) { /* Not really a digit */ return false; @@ -1382,11 +1436,12 @@ static bool match_and_parse_sunxi( /* Parse optional second digit of the sunXi platform id */ const char* pos = start + 4; { - const uint32_t digit = (uint32_t) (uint8_t) (*pos) - '0'; + const uint32_t digit = (uint32_t)(uint8_t)(*pos) - '0'; if (digit < 10) { sunxi_platform = sunxi_platform * 10 + digit; if (++pos == end) { - /* Expected one more character, final 'i' letter */ + /* Expected one more character, final 'i' letter + */ return false; } } @@ -1397,7 +1452,8 @@ static bool match_and_parse_sunxi( return false; } - /* Compare sunXi platform id and number of cores to tabulated values to decode chipset name */ + /* Compare sunXi platform id and number of cores to tabulated values to + * decode chipset name */ uint32_t model = 0; char suffix = 0; for (size_t i = 0; i < CPUINFO_COUNT_OF(sunxi_map_entries); i++) { @@ -1409,37 +1465,44 @@ static bool match_and_parse_sunxi( } if (model == 0) { - cpuinfo_log_info("unrecognized %"PRIu32"-core Allwinner sun%"PRIu32" platform", cores, sunxi_platform); + cpuinfo_log_info( + "unrecognized %" PRIu32 "-core Allwinner sun%" PRIu32 " platform", cores, sunxi_platform); } /* Create chipset name from decoded data */ - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_allwinner, .series = cpuinfo_arm_chipset_series_allwinner_a, .model = model, - .suffix = { - [0] = suffix, - }, + .suffix = + { + [0] = suffix, + }, }; return true; } /** * Compares /proc/cpuinfo Hardware string to "WMT" signature. - * If the string matches signature, the function decodes WonderMedia chipset from frequency and number of cores into - * \p chipset argument. + * If the string matches signature, the function decodes WonderMedia chipset + * from frequency and number of cores into \p chipset argument. * * @param start - start of the /proc/cpuinfo Hardware string to match. * @param end - end of the /proc/cpuinfo Hardware string to match. * @param cores - number of cores in the chipset. - * @param max_cpu_freq_max - maximum of /sys/devices/system/cpu/cpu/cpofreq/cpu_freq_max values. - * @param[out] chipset - location where chipset information will be stored upon a successful match and decoding. + * @param max_cpu_freq_max - maximum of + * /sys/devices/system/cpu/cpu/cpofreq/cpu_freq_max values. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match and decoding. * - * @returns true if signature matched (even if exact model can't be decoded), false otherwise. + * @returns true if signature matched (even if exact model can't be decoded), + * false otherwise. */ static bool match_and_parse_wmt( - const char* start, const char* end, uint32_t cores, uint32_t max_cpu_freq_max, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ + const char* start, + const char* end, + uint32_t cores, + uint32_t max_cpu_freq_max, + struct cpuinfo_arm_chipset chipset[restrict static 1]) { /* Expected 3 symbols: "WMT" */ if (start + 3 != end) { return false; @@ -1478,10 +1541,12 @@ static bool match_and_parse_wmt( } if (model == 0) { - cpuinfo_log_info("unrecognized WonderMedia platform with %"PRIu32" cores at %"PRIu32" KHz", - cores, max_cpu_freq_max); + cpuinfo_log_info( + "unrecognized WonderMedia platform with %" PRIu32 " cores at %" PRIu32 " KHz", + cores, + max_cpu_freq_max); } - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_wondermedia, .series = cpuinfo_arm_chipset_series_wondermedia_wm, .model = model, @@ -1633,26 +1698,30 @@ static const struct huawei_map_entry huawei_platform_map[] = { }; /** - * Tries to match ro.product.board string to Huawei /([A-Z]{3})(\-[A-Z]?L\d{2})$/ signature where \1 is one of the - * known values for Huawei devices, which do not report chipset name elsewhere. - * If the string matches signature, the function decodes chipset (always HiSilicon Kirin for matched devices) from - * the Huawei platform ID in the signature and stores it in \p chipset argument. + * Tries to match ro.product.board string to Huawei + * /([A-Z]{3})(\-[A-Z]?L\d{2})$/ signature where \1 is one of the known values + * for Huawei devices, which do not report chipset name elsewhere. If the string + * matches signature, the function decodes chipset (always HiSilicon Kirin for + * matched devices) from the Huawei platform ID in the signature and stores it + * in \p chipset argument. * * @param start - start of the ro.product.board string to match. * @param end - end of the ro.product.board string to match. - * @param[out] chipset - location where chipset information will be stored upon a successful match and decoding. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match and decoding. * * @returns true if signature matched, false otherwise. */ static bool match_and_parse_huawei( - const char* start, const char* end, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ + const char* start, + const char* end, + struct cpuinfo_arm_chipset chipset[restrict static 1]) { /* * Expect length of either 3, 7 or 8, exactly: * - 3-letter platform identifier (see huawei_platform_map) * - 3-letter platform identifier + '-' + 'L' + two digits - * - 3-letter platform identifier + '-' + capital letter + 'L' + two digits + * - 3-letter platform identifier + '-' + capital letter + 'L' + two + * digits */ const size_t length = end - start; switch (length) { @@ -1665,8 +1734,9 @@ static bool match_and_parse_huawei( } /* - * Try to find the first three-letter substring in among the tabulated entries for Huawei devices. - * The first three letters are loaded and compared as a little-endian 24-bit word. + * Try to find the first three-letter substring in among the tabulated + * entries for Huawei devices. The first three letters are loaded and + * compared as a little-endian 24-bit word. */ uint32_t model = 0; const uint32_t target_platform_id = load_u24le(start); @@ -1686,7 +1756,8 @@ static bool match_and_parse_huawei( /* * Check that: * - The symbol after platform id is a dash - * - The symbol after it is an uppercase letter. For 7-symbol strings, the symbol is just 'L'. + * - The symbol after it is an uppercase letter. For 7-symbol + * strings, the symbol is just 'L'. */ if (start[3] != '-' || !is_ascii_alphabetic_uppercase(start[4])) { return false; @@ -1699,7 +1770,7 @@ static bool match_and_parse_huawei( } /* All checks succeeded, commit chipset name */ - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_hisilicon, .series = cpuinfo_arm_chipset_series_hisilicon_kirin, .model = model, @@ -1713,15 +1784,14 @@ static bool match_and_parse_huawei( * * @param start - start of the /proc/cpuinfo Hardware string to match. * @param end - end of the /proc/cpuinfo Hardware string to match. - * @param[out] chipset - location where chipset information will be stored upon a successful match. + * @param[out] chipset - location where chipset information will be stored upon + * a successful match. * * @returns true if signature matched, false otherwise. */ -static bool match_tcc( - const char* start, const char* end, - struct cpuinfo_arm_chipset chipset[restrict static 1]) -{ - /* Expect exactly 7 symbols: "tcc" (3 symbols) + 3-digit model number + fixed "x" suffix */ +static bool match_tcc(const char* start, const char* end, struct cpuinfo_arm_chipset chipset[restrict static 1]) { + /* Expect exactly 7 symbols: "tcc" (3 symbols) + 3-digit model number + + * fixed "x" suffix */ if (start + 7 != end) { return false; } @@ -1733,14 +1803,14 @@ static bool match_tcc( /* Load the next 2 bytes as little endian 16-bit word */ const uint16_t expected_cc = load_u16le(start + 1); - if (expected_cc != UINT16_C(0x6363) /* "cc" */ ) { + if (expected_cc != UINT16_C(0x6363) /* "cc" */) { return false; } /* Check and parse 3-digit model number */ uint32_t model = 0; for (uint32_t i = 3; i < 6; i++) { - const uint32_t digit = (uint32_t) (uint8_t) start[i] - '0'; + const uint32_t digit = (uint32_t)(uint8_t)start[i] - '0'; if (digit >= 10) { /* Not really a digit */ return false; @@ -1754,25 +1824,25 @@ static bool match_tcc( } /* Commit parsed chipset. */ - *chipset = (struct cpuinfo_arm_chipset) { + *chipset = (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_telechips, .series = cpuinfo_arm_chipset_series_telechips_tcc, .model = model, - .suffix = { - [0] = 'X' - }, + .suffix = {[0] = 'X'}, }; return true; } /* - * Compares ro.board.platform string to Nvidia Tegra signatures ("tegra" and "tegra3") - * This check has effect on how /proc/cpuinfo Hardware string is interpreted. + * Compares ro.board.platform string to Nvidia Tegra signatures ("tegra" and + * "tegra3") This check has effect on how /proc/cpuinfo Hardware string is + * interpreted. * * @param start - start of the ro.board.platform string to check. * @param end - end of the ro.board.platform string to check. * - * @returns true if the string matches an Nvidia Tegra signature, and false otherwise + * @returns true if the string matches an Nvidia Tegra signature, and false + * otherwise */ static bool is_tegra(const char* start, const char* end) { /* Expect 5 ("tegra") or 6 ("tegra3") symbols */ @@ -1794,7 +1864,8 @@ static bool is_tegra(const char* start, const char* end) { return false; } - /* Check if the string is either "tegra" (length = 5) or "tegra3" (length != 5) and last character is '3' */ + /* Check if the string is either "tegra" (length = 5) or "tegra3" + * (length != 5) and last character is '3' */ return (length == 5 || start[5] == '3'); } @@ -1813,13 +1884,11 @@ static const struct special_map_entry special_hardware_map_entries[] = { .series = cpuinfo_arm_chipset_series_hisilicon_k3v, .model = 2, }, - { - /* "hi6620oem" -> HiSilicon Kirin 910T */ - .platform = "hi6620oem", - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = 910, - .suffix = 'T' - }, + {/* "hi6620oem" -> HiSilicon Kirin 910T */ + .platform = "hi6620oem", + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = 910, + .suffix = 'T'}, #endif /* CPUINFO_ARCH_ARM */ { /* "hi6250" -> HiSilicon Kirin 650 */ @@ -1906,7 +1975,8 @@ static const struct special_map_entry special_hardware_map_entries[] = { .model = 4470, }, { - /* "Tuna" (Samsung Galaxy Nexus) -> Texas Instruments OMAP4460 */ + /* "Tuna" (Samsung Galaxy Nexus) -> Texas Instruments OMAP4460 + */ .platform = "Tuna", .series = cpuinfo_arm_chipset_series_texas_instruments_omap, .model = 4460, @@ -1954,7 +2024,8 @@ static const struct special_map_entry tegra_hardware_map_entries[] = { .model = 20, }, { - /* "n1" (Samsung Galaxy R / Samsung Captivate Glide) -> Tegra AP20H */ + /* "n1" (Samsung Galaxy R / Samsung Captivate Glide) -> Tegra + AP20H */ .platform = "n1", .series = cpuinfo_arm_chipset_series_nvidia_tegra_ap, .model = 20, @@ -2134,7 +2205,8 @@ static const struct special_map_entry tegra_hardware_map_entries[] = { .model = 20, }, { - /* "tostab12AL" (Toshiba AT300SE "Excite 10 SE") -> Tegra T30L */ + /* "tostab12AL" (Toshiba AT300SE "Excite 10 SE") -> Tegra T30L + */ .platform = "tostab12AL", .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, .model = 30, @@ -2160,7 +2232,8 @@ static const struct special_map_entry tegra_hardware_map_entries[] = { .model = 30, }, { - /* "tostab12BA" (Toshiba AT10-LE-A "Excite Pro") -> Tegra T114 */ + /* "tostab12BA" (Toshiba AT10-LE-A "Excite Pro") -> Tegra T114 + */ .platform = "tostab12BA", .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, .model = 114, @@ -2260,45 +2333,50 @@ static const struct special_map_entry tegra_hardware_map_entries[] = { /* * Decodes chipset name from /proc/cpuinfo Hardware string. - * For some chipsets, the function relies frequency and on number of cores for chipset detection. + * For some chipsets, the function relies frequency and on number of cores for + * chipset detection. * * @param[in] platform - /proc/cpuinfo Hardware string. * @param cores - number of cores in the chipset. - * @param max_cpu_freq_max - maximum of /sys/devices/system/cpu/cpu/cpofreq/cpu_freq_max values. + * @param max_cpu_freq_max - maximum of + * /sys/devices/system/cpu/cpu/cpofreq/cpu_freq_max values. * - * @returns Decoded chipset name. If chipset could not be decoded, the resulting structure would use `unknown` vendor - * and series identifiers. + * @returns Decoded chipset name. If chipset could not be decoded, the resulting + * structure would use `unknown` vendor and series identifiers. */ struct cpuinfo_arm_chipset cpuinfo_arm_linux_decode_chipset_from_proc_cpuinfo_hardware( const char hardware[restrict static CPUINFO_HARDWARE_VALUE_MAX], - uint32_t cores, uint32_t max_cpu_freq_max, bool is_tegra) -{ + uint32_t cores, + uint32_t max_cpu_freq_max, + bool is_tegra) { struct cpuinfo_arm_chipset chipset; const size_t hardware_length = strnlen(hardware, CPUINFO_HARDWARE_VALUE_MAX); const char* hardware_end = hardware + hardware_length; if (is_tegra) { /* - * Nvidia Tegra-specific path: compare /proc/cpuinfo Hardware string to - * tabulated Hardware values for popular chipsets/devices with Tegra chipsets. - * This path is only used when ro.board.platform indicates a Tegra chipset - * (albeit does not indicate which exactly Tegra chipset). + * Nvidia Tegra-specific path: compare /proc/cpuinfo Hardware + * string to tabulated Hardware values for popular + * chipsets/devices with Tegra chipsets. This path is only used + * when ro.board.platform indicates a Tegra chipset (albeit does + * not indicate which exactly Tegra chipset). */ for (size_t i = 0; i < CPUINFO_COUNT_OF(tegra_hardware_map_entries); i++) { if (strncmp(tegra_hardware_map_entries[i].platform, hardware, hardware_length) == 0 && - tegra_hardware_map_entries[i].platform[hardware_length] == 0) - { + tegra_hardware_map_entries[i].platform[hardware_length] == 0) { cpuinfo_log_debug( "found /proc/cpuinfo Hardware string \"%.*s\" in Nvidia Tegra chipset table", - (int) hardware_length, hardware); + (int)hardware_length, + hardware); /* Create chipset name from entry */ - return (struct cpuinfo_arm_chipset) { + return (struct cpuinfo_arm_chipset){ .vendor = chipset_series_vendor[tegra_hardware_map_entries[i].series], - .series = (enum cpuinfo_arm_chipset_series) tegra_hardware_map_entries[i].series, + .series = (enum cpuinfo_arm_chipset_series)tegra_hardware_map_entries[i].series, .model = tegra_hardware_map_entries[i].model, - .suffix = { - [0] = tegra_hardware_map_entries[i].suffix, - }, + .suffix = + { + [0] = tegra_hardware_map_entries[i].suffix, + }, }; } } @@ -2316,51 +2394,63 @@ struct cpuinfo_arm_chipset cpuinfo_arm_linux_decode_chipset_from_proc_cpuinfo_ha break; default: if (word_start && is_ascii_alphabetic(c)) { - /* Check Qualcomm MSM/APQ signature */ + /* Check Qualcomm MSM/APQ + * signature */ if (match_msm_apq(pos, hardware_end, &chipset)) { cpuinfo_log_debug( "matched Qualcomm MSM/APQ signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) hardware_length, hardware); + (int)hardware_length, + hardware); return chipset; } - /* Check SDMxxx (Qualcomm Snapdragon) signature */ + /* Check SDMxxx (Qualcomm + * Snapdragon) signature */ if (match_sdm(pos, hardware_end, &chipset)) { cpuinfo_log_debug( "matched Qualcomm SDM signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) hardware_length, hardware); + (int)hardware_length, + hardware); return chipset; } - /* Check SMxxxx (Qualcomm Snapdragon) signature */ + /* Check SMxxxx (Qualcomm + * Snapdragon) signature */ if (match_sm(pos, hardware_end, &chipset)) { cpuinfo_log_debug( "matched Qualcomm SM signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) hardware_length, hardware); + (int)hardware_length, + hardware); return chipset; } - /* Check MediaTek MT signature */ + /* Check MediaTek MT signature + */ if (match_mt(pos, hardware_end, true, &chipset)) { cpuinfo_log_debug( "matched MediaTek MT signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) hardware_length, hardware); + (int)hardware_length, + hardware); return chipset; } - /* Check HiSilicon Kirin signature */ + /* Check HiSilicon Kirin + * signature */ if (match_kirin(pos, hardware_end, &chipset)) { cpuinfo_log_debug( "matched HiSilicon Kirin signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) hardware_length, hardware); + (int)hardware_length, + hardware); return chipset; } - /* Check Rockchip RK signature */ + /* Check Rockchip RK signature + */ if (match_rk(pos, hardware_end, &chipset)) { cpuinfo_log_debug( "matched Rockchip RK signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) hardware_length, hardware); + (int)hardware_length, + hardware); return chipset; } } @@ -2373,7 +2463,8 @@ struct cpuinfo_arm_chipset cpuinfo_arm_linux_decode_chipset_from_proc_cpuinfo_ha if (match_samsung_exynos(hardware, hardware_end, &chipset)) { cpuinfo_log_debug( "matched Samsung Exynos signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) hardware_length, hardware); + (int)hardware_length, + hardware); return chipset; } @@ -2381,25 +2472,28 @@ struct cpuinfo_arm_chipset cpuinfo_arm_linux_decode_chipset_from_proc_cpuinfo_ha if (match_universal(hardware, hardware_end, &chipset)) { cpuinfo_log_debug( "matched UNIVERSAL (Samsung Exynos) signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) hardware_length, hardware); + (int)hardware_length, + hardware); return chipset; } - #if CPUINFO_ARCH_ARM - /* Match /SMDK(4410|4x12)$/ */ - if (match_and_parse_smdk(hardware, hardware_end, cores, &chipset)) { - cpuinfo_log_debug( - "matched SMDK (Samsung Exynos) signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) hardware_length, hardware); - return chipset; - } - #endif +#if CPUINFO_ARCH_ARM + /* Match /SMDK(4410|4x12)$/ */ + if (match_and_parse_smdk(hardware, hardware_end, cores, &chipset)) { + cpuinfo_log_debug( + "matched SMDK (Samsung Exynos) signature in /proc/cpuinfo Hardware string \"%.*s\"", + (int)hardware_length, + hardware); + return chipset; + } +#endif /* Check Spreadtrum SC signature */ if (match_sc(hardware, hardware_end, &chipset)) { cpuinfo_log_debug( "matched Spreadtrum SC signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) hardware_length, hardware); + (int)hardware_length, + hardware); return chipset; } @@ -2408,26 +2502,30 @@ struct cpuinfo_arm_chipset cpuinfo_arm_linux_decode_chipset_from_proc_cpuinfo_ha if (match_t(hardware, hardware_end, &chipset)) { cpuinfo_log_debug( "matched Unisoc T signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) hardware_length, hardware); + (int)hardware_length, + hardware); return chipset; } - #if CPUINFO_ARCH_ARM - /* Check Marvell PXA signature */ - if (match_pxa(hardware, hardware_end, &chipset)) { - cpuinfo_log_debug( - "matched Marvell PXA signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) hardware_length, hardware); - return chipset; - } - #endif +#if CPUINFO_ARCH_ARM + /* Check Marvell PXA signature */ + if (match_pxa(hardware, hardware_end, &chipset)) { + cpuinfo_log_debug( + "matched Marvell PXA signature in /proc/cpuinfo Hardware string \"%.*s\"", + (int)hardware_length, + hardware); + return chipset; + } +#endif - /* Match /sun\d+i/ signature and map to Allwinner chipset name */ + /* Match /sun\d+i/ signature and map to Allwinner chipset name + */ if (match_and_parse_sunxi(hardware, hardware_end, cores, &chipset)) { cpuinfo_log_debug( "matched sunxi (Allwinner Ax) signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) hardware_length, hardware); + (int)hardware_length, + hardware); return chipset; } @@ -2435,781 +2533,828 @@ struct cpuinfo_arm_chipset cpuinfo_arm_linux_decode_chipset_from_proc_cpuinfo_ha if (match_bcm(hardware, hardware_end, &chipset)) { cpuinfo_log_debug( "matched Broadcom BCM signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) hardware_length, hardware); + (int)hardware_length, + hardware); return chipset; } - #if CPUINFO_ARCH_ARM - /* Check Texas Instruments OMAP signature */ - if (match_omap(hardware, hardware_end, &chipset)) { - cpuinfo_log_debug( - "matched Texas Instruments OMAP signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) hardware_length, hardware); - return chipset; - } +#if CPUINFO_ARCH_ARM + /* Check Texas Instruments OMAP signature */ + if (match_omap(hardware, hardware_end, &chipset)) { + cpuinfo_log_debug( + "matched Texas Instruments OMAP signature in /proc/cpuinfo Hardware string \"%.*s\"", + (int)hardware_length, + hardware); + return chipset; + } - /* Check WonderMedia WMT signature and decode chipset from frequency and number of cores */ - if (match_and_parse_wmt(hardware, hardware_end, cores, max_cpu_freq_max, &chipset)) { - cpuinfo_log_debug( - "matched WonderMedia WMT signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) hardware_length, hardware); - return chipset; - } + /* Check WonderMedia WMT signature and decode chipset from + * frequency and number of cores */ + if (match_and_parse_wmt(hardware, hardware_end, cores, max_cpu_freq_max, &chipset)) { + cpuinfo_log_debug( + "matched WonderMedia WMT signature in /proc/cpuinfo Hardware string \"%.*s\"", + (int)hardware_length, + hardware); + return chipset; + } - #endif +#endif /* Check Telechips TCC signature */ if (match_tcc(hardware, hardware_end, &chipset)) { cpuinfo_log_debug( "matched Telechips TCC signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) hardware_length, hardware); + (int)hardware_length, + hardware); return chipset; } - /* Compare to tabulated Hardware values for popular chipsets/devices which can't be otherwise detected */ + /* Compare to tabulated Hardware values for popular + * chipsets/devices which can't be otherwise detected */ for (size_t i = 0; i < CPUINFO_COUNT_OF(special_hardware_map_entries); i++) { if (strncmp(special_hardware_map_entries[i].platform, hardware, hardware_length) == 0 && - special_hardware_map_entries[i].platform[hardware_length] == 0) - { + special_hardware_map_entries[i].platform[hardware_length] == 0) { cpuinfo_log_debug( "found /proc/cpuinfo Hardware string \"%.*s\" in special chipset table", - (int) hardware_length, hardware); + (int)hardware_length, + hardware); /* Create chipset name from entry */ - return (struct cpuinfo_arm_chipset) { + return (struct cpuinfo_arm_chipset){ .vendor = chipset_series_vendor[special_hardware_map_entries[i].series], - .series = (enum cpuinfo_arm_chipset_series) special_hardware_map_entries[i].series, + .series = + (enum cpuinfo_arm_chipset_series)special_hardware_map_entries[i].series, .model = special_hardware_map_entries[i].model, - .suffix = { - [0] = special_hardware_map_entries[i].suffix, - }, + .suffix = + { + [0] = special_hardware_map_entries[i].suffix, + }, }; } } } - return (struct cpuinfo_arm_chipset) { + return (struct cpuinfo_arm_chipset){ .vendor = cpuinfo_arm_chipset_vendor_unknown, .series = cpuinfo_arm_chipset_series_unknown, }; } #ifdef __ANDROID__ - static const struct special_map_entry special_board_map_entries[] = { - { - /* "hi6250" -> HiSilicon Kirin 650 */ - .platform = "hi6250", - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = 650, - }, - { - /* "hi6210sft" -> HiSilicon Kirin 620 */ - .platform = "hi6210sft", - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = 620, - }, +static const struct special_map_entry special_board_map_entries[] = { + { + /* "hi6250" -> HiSilicon Kirin 650 */ + .platform = "hi6250", + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = 650, + }, + { + /* "hi6210sft" -> HiSilicon Kirin 620 */ + .platform = "hi6210sft", + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = 620, + }, #if CPUINFO_ARCH_ARM - { - /* "hi3630" -> HiSilicon Kirin 920 */ - .platform = "hi3630", - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = 920, - }, + { + /* "hi3630" -> HiSilicon Kirin 920 */ + .platform = "hi3630", + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = 920, + }, #endif /* CPUINFO_ARCH_ARM */ - { - /* "hi3635" -> HiSilicon Kirin 930 */ - .platform = "hi3635", - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = 930, - }, - { - /* "hi3650" -> HiSilicon Kirin 950 */ - .platform = "hi3650", - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = 950, - }, - { - /* "hi3660" -> HiSilicon Kirin 960 */ - .platform = "hi3660", - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = 960, - }, + { + /* "hi3635" -> HiSilicon Kirin 930 */ + .platform = "hi3635", + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = 930, + }, + { + /* "hi3650" -> HiSilicon Kirin 950 */ + .platform = "hi3650", + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = 950, + }, + { + /* "hi3660" -> HiSilicon Kirin 960 */ + .platform = "hi3660", + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = 960, + }, #if CPUINFO_ARCH_ARM - { - /* "mp523x" -> Renesas MP5232 */ - .platform = "mp523x", - .series = cpuinfo_arm_chipset_series_renesas_mp, - .model = 5232, - }, + { + /* "mp523x" -> Renesas MP5232 */ + .platform = "mp523x", + .series = cpuinfo_arm_chipset_series_renesas_mp, + .model = 5232, + }, #endif /* CPUINFO_ARCH_ARM */ - { - /* "BEETHOVEN" (Huawei MadiaPad M3) -> HiSilicon Kirin 950 */ - .platform = "BEETHOVEN", - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = 950, - }, + { + /* "BEETHOVEN" (Huawei MadiaPad M3) -> HiSilicon Kirin 950 */ + .platform = "BEETHOVEN", + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = 950, + }, #if CPUINFO_ARCH_ARM - { - /* "hws7701u" (Huawei MediaPad 7 Youth) -> Rockchip RK3168 */ - .platform = "hws7701u", - .series = cpuinfo_arm_chipset_series_rockchip_rk, - .model = 3168, - }, - { - /* "g2mv" (LG G2 mini LTE) -> Nvidia Tegra SL460N */ - .platform = "g2mv", - .series = cpuinfo_arm_chipset_series_nvidia_tegra_sl, - .model = 460, - .suffix = 'N', - }, - { - /* "K00F" (Asus MeMO Pad 10) -> Rockchip RK3188 */ - .platform = "K00F", - .series = cpuinfo_arm_chipset_series_rockchip_rk, - .model = 3188, - }, - { - /* "T7H" (HP Slate 7) -> Rockchip RK3066 */ - .platform = "T7H", - .series = cpuinfo_arm_chipset_series_rockchip_rk, - .model = 3066, - }, - { - /* "tuna" (Samsung Galaxy Nexus) -> Texas Instruments OMAP4460 */ - .platform = "tuna", - .series = cpuinfo_arm_chipset_series_texas_instruments_omap, - .model = 4460, - }, - { - /* "grouper" (Asus Nexus 7 2012) -> Nvidia Tegra T30L */ - .platform = "grouper", - .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, - .model = 30, - .suffix = 'L', - }, + { + /* "hws7701u" (Huawei MediaPad 7 Youth) -> Rockchip RK3168 */ + .platform = "hws7701u", + .series = cpuinfo_arm_chipset_series_rockchip_rk, + .model = 3168, + }, + { + /* "g2mv" (LG G2 mini LTE) -> Nvidia Tegra SL460N */ + .platform = "g2mv", + .series = cpuinfo_arm_chipset_series_nvidia_tegra_sl, + .model = 460, + .suffix = 'N', + }, + { + /* "K00F" (Asus MeMO Pad 10) -> Rockchip RK3188 */ + .platform = "K00F", + .series = cpuinfo_arm_chipset_series_rockchip_rk, + .model = 3188, + }, + { + /* "T7H" (HP Slate 7) -> Rockchip RK3066 */ + .platform = "T7H", + .series = cpuinfo_arm_chipset_series_rockchip_rk, + .model = 3066, + }, + { + /* "tuna" (Samsung Galaxy Nexus) -> Texas Instruments OMAP4460 + */ + .platform = "tuna", + .series = cpuinfo_arm_chipset_series_texas_instruments_omap, + .model = 4460, + }, + { + /* "grouper" (Asus Nexus 7 2012) -> Nvidia Tegra T30L */ + .platform = "grouper", + .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, + .model = 30, + .suffix = 'L', + }, #endif /* CPUINFO_ARCH_ARM */ - { - /* "flounder" (HTC Nexus 9) -> Nvidia Tegra T132 */ - .platform = "flounder", - .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, - .model = 132, - }, - { - /* "dragon" (Google Pixel C) -> Nvidia Tegra T210 */ - .platform = "dragon", - .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, - .model = 210, - }, - { - /* "sailfish" (Google Pixel) -> Qualcomm MSM8996PRO */ - .platform = "sailfish", - .series = cpuinfo_arm_chipset_series_qualcomm_msm, - .model = 8996, - .suffix = 'P', - }, - { - /* "marlin" (Google Pixel XL) -> Qualcomm MSM8996PRO */ - .platform = "marlin", - .series = cpuinfo_arm_chipset_series_qualcomm_msm, - .model = 8996, - .suffix = 'P', - }, - }; - - /* - * Decodes chipset name from ro.product.board Android system property. - * For some chipsets, the function relies frequency and on number of cores for chipset detection. - * - * @param[in] platform - ro.product.board value. - * @param cores - number of cores in the chipset. - * @param max_cpu_freq_max - maximum of /sys/devices/system/cpu/cpu/cpofreq/cpu_freq_max values. - * - * @returns Decoded chipset name. If chipset could not be decoded, the resulting structure would use `unknown` vendor - * and series identifiers. - */ - struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_product_board( - const char ro_product_board[restrict static CPUINFO_BUILD_PROP_VALUE_MAX], - uint32_t cores, uint32_t max_cpu_freq_max) { - struct cpuinfo_arm_chipset chipset; - const char* board = ro_product_board; - const size_t board_length = strnlen(ro_product_board, CPUINFO_BUILD_PROP_VALUE_MAX); - const char* board_end = ro_product_board + board_length; + /* "flounder" (HTC Nexus 9) -> Nvidia Tegra T132 */ + .platform = "flounder", + .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, + .model = 132, + }, + { + /* "dragon" (Google Pixel C) -> Nvidia Tegra T210 */ + .platform = "dragon", + .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, + .model = 210, + }, + { + /* "sailfish" (Google Pixel) -> Qualcomm MSM8996PRO */ + .platform = "sailfish", + .series = cpuinfo_arm_chipset_series_qualcomm_msm, + .model = 8996, + .suffix = 'P', + }, + { + /* "marlin" (Google Pixel XL) -> Qualcomm MSM8996PRO */ + .platform = "marlin", + .series = cpuinfo_arm_chipset_series_qualcomm_msm, + .model = 8996, + .suffix = 'P', + }, +}; - /* Check Qualcomm MSM/APQ signature */ - if (match_msm_apq(board, board_end, &chipset)) { - cpuinfo_log_debug( - "matched Qualcomm MSM/APQ signature in ro.product.board string \"%.*s\"", (int) board_length, board); - return chipset; - } +/* + * Decodes chipset name from ro.product.board Android system property. + * For some chipsets, the function relies frequency and on number of cores for + * chipset detection. + * + * @param[in] platform - ro.product.board value. + * @param cores - number of cores in the chipset. + * @param max_cpu_freq_max - maximum of + * /sys/devices/system/cpu/cpu/cpofreq/cpu_freq_max values. + * + * @returns Decoded chipset name. If chipset could not be decoded, the resulting + * structure would use `unknown` vendor and series identifiers. + */ +struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_product_board( + const char ro_product_board[restrict static CPUINFO_BUILD_PROP_VALUE_MAX], + uint32_t cores, + uint32_t max_cpu_freq_max) { + struct cpuinfo_arm_chipset chipset; + const char* board = ro_product_board; + const size_t board_length = strnlen(ro_product_board, CPUINFO_BUILD_PROP_VALUE_MAX); + const char* board_end = ro_product_board + board_length; + + /* Check Qualcomm MSM/APQ signature */ + if (match_msm_apq(board, board_end, &chipset)) { + cpuinfo_log_debug( + "matched Qualcomm MSM/APQ signature in ro.product.board string \"%.*s\"", + (int)board_length, + board); + return chipset; + } - /* Check universaXXXX (Samsung Exynos) signature */ - if (match_universal(board, board_end, &chipset)) { - cpuinfo_log_debug( - "matched UNIVERSAL (Samsung Exynos) signature in ro.product.board string \"%.*s\"", - (int) board_length, board); - return chipset; - } + /* Check universaXXXX (Samsung Exynos) signature */ + if (match_universal(board, board_end, &chipset)) { + cpuinfo_log_debug( + "matched UNIVERSAL (Samsung Exynos) signature in ro.product.board string \"%.*s\"", + (int)board_length, + board); + return chipset; + } - #if CPUINFO_ARCH_ARM - /* Check SMDK (Samsung Exynos) signature */ - if (match_and_parse_smdk(board, board_end, cores, &chipset)) { - cpuinfo_log_debug( - "matched SMDK (Samsung Exynos) signature in ro.product.board string \"%.*s\"", - (int) board_length, board); - return chipset; - } - #endif +#if CPUINFO_ARCH_ARM + /* Check SMDK (Samsung Exynos) signature */ + if (match_and_parse_smdk(board, board_end, cores, &chipset)) { + cpuinfo_log_debug( + "matched SMDK (Samsung Exynos) signature in ro.product.board string \"%.*s\"", + (int)board_length, + board); + return chipset; + } +#endif - /* Check MediaTek MT signature */ - if (match_mt(board, board_end, true, &chipset)) { - cpuinfo_log_debug( - "matched MediaTek MT signature in ro.product.board string \"%.*s\"", - (int) board_length, board); - return chipset; - } + /* Check MediaTek MT signature */ + if (match_mt(board, board_end, true, &chipset)) { + cpuinfo_log_debug( + "matched MediaTek MT signature in ro.product.board string \"%.*s\"", (int)board_length, board); + return chipset; + } - /* Check Spreadtrum SC signature */ - if (match_sc(board, board_end, &chipset)) { - cpuinfo_log_debug( - "matched Spreadtrum SC signature in ro.product.board string \"%.*s\"", - (int) board_length, board); - return chipset; - } + /* Check Spreadtrum SC signature */ + if (match_sc(board, board_end, &chipset)) { + cpuinfo_log_debug( + "matched Spreadtrum SC signature in ro.product.board string \"%.*s\"", + (int)board_length, + board); + return chipset; + } - #if CPUINFO_ARCH_ARM - /* Check Marvell PXA signature */ - if (match_pxa(board, board_end, &chipset)) { - cpuinfo_log_debug( - "matched Marvell PXA signature in ro.product.board string \"%.*s\"", - (int) board_length, board); - return chipset; - } +#if CPUINFO_ARCH_ARM + /* Check Marvell PXA signature */ + if (match_pxa(board, board_end, &chipset)) { + cpuinfo_log_debug( + "matched Marvell PXA signature in ro.product.board string \"%.*s\"", (int)board_length, board); + return chipset; + } - /* Check Leadcore LCxxxx signature */ - if (match_lc(board, board_end, &chipset)) { - cpuinfo_log_debug( - "matched Leadcore LC signature in ro.product.board string \"%.*s\"", - (int) board_length, board); - return chipset; - } + /* Check Leadcore LCxxxx signature */ + if (match_lc(board, board_end, &chipset)) { + cpuinfo_log_debug( + "matched Leadcore LC signature in ro.product.board string \"%.*s\"", (int)board_length, board); + return chipset; + } - /* - * Compare to tabulated ro.product.board values for Broadcom chipsets and decode chipset from frequency and - * number of cores. - */ - if (match_and_parse_broadcom(board, board_end, cores, max_cpu_freq_max, &chipset)) { - cpuinfo_log_debug( - "found ro.product.board string \"%.*s\" in Broadcom chipset table", - (int) board_length, board); - return chipset; - } - #endif + /* + * Compare to tabulated ro.product.board values for Broadcom chipsets + * and decode chipset from frequency and number of cores. + */ + if (match_and_parse_broadcom(board, board_end, cores, max_cpu_freq_max, &chipset)) { + cpuinfo_log_debug( + "found ro.product.board string \"%.*s\" in Broadcom chipset table", (int)board_length, board); + return chipset; + } +#endif - /* Compare to tabulated ro.product.board values for Huawei devices which don't report chipset elsewhere */ - if (match_and_parse_huawei(board, board_end, &chipset)) { - cpuinfo_log_debug( - "found ro.product.board string \"%.*s\" in Huawei chipset table", - (int) board_length, board); - return chipset; - } + /* Compare to tabulated ro.product.board values for Huawei devices which + * don't report chipset elsewhere */ + if (match_and_parse_huawei(board, board_end, &chipset)) { + cpuinfo_log_debug( + "found ro.product.board string \"%.*s\" in Huawei chipset table", (int)board_length, board); + return chipset; + } - /* Compare to tabulated ro.product.board values for popular chipsets/devices which can't be otherwise detected */ - for (size_t i = 0; i < CPUINFO_COUNT_OF(special_board_map_entries); i++) { - if (strncmp(special_board_map_entries[i].platform, board, board_length) == 0 && - special_board_map_entries[i].platform[board_length] == 0) - { - cpuinfo_log_debug( - "found ro.product.board string \"%.*s\" in special chipset table", - (int) board_length, board); - /* Create chipset name from entry */ - return (struct cpuinfo_arm_chipset) { - .vendor = chipset_series_vendor[special_board_map_entries[i].series], - .series = (enum cpuinfo_arm_chipset_series) special_board_map_entries[i].series, - .model = special_board_map_entries[i].model, - .suffix = { + /* Compare to tabulated ro.product.board values for popular + * chipsets/devices which can't be otherwise detected */ + for (size_t i = 0; i < CPUINFO_COUNT_OF(special_board_map_entries); i++) { + if (strncmp(special_board_map_entries[i].platform, board, board_length) == 0 && + special_board_map_entries[i].platform[board_length] == 0) { + cpuinfo_log_debug( + "found ro.product.board string \"%.*s\" in special chipset table", + (int)board_length, + board); + /* Create chipset name from entry */ + return (struct cpuinfo_arm_chipset){ + .vendor = chipset_series_vendor[special_board_map_entries[i].series], + .series = (enum cpuinfo_arm_chipset_series)special_board_map_entries[i].series, + .model = special_board_map_entries[i].model, + .suffix = + { [0] = special_board_map_entries[i].suffix, - /* The suffix of MSM8996PRO is truncated at the first letter, reconstruct it here. */ + /* The suffix of MSM8996PRO is + truncated at the first + letter, reconstruct it here. + */ [1] = special_board_map_entries[i].suffix == 'P' ? 'R' : 0, [2] = special_board_map_entries[i].suffix == 'P' ? 'O' : 0, }, - }; - } + }; } - - return (struct cpuinfo_arm_chipset) { - .vendor = cpuinfo_arm_chipset_vendor_unknown, - .series = cpuinfo_arm_chipset_series_unknown, - }; } - struct amlogic_map_entry { - char ro_board_platform[6]; - uint16_t model; - uint8_t series; - char suffix[3]; + return (struct cpuinfo_arm_chipset){ + .vendor = cpuinfo_arm_chipset_vendor_unknown, + .series = cpuinfo_arm_chipset_series_unknown, }; +} - static const struct amlogic_map_entry amlogic_map_entries[] = { -#if CPUINFO_ARCH_ARM - { - /* "meson3" -> Amlogic AML8726-M */ - .ro_board_platform = "meson3", - .series = cpuinfo_arm_chipset_series_amlogic_aml, - .model = 8726, - .suffix = "-M", - }, - { - /* "meson6" -> Amlogic AML8726-MX */ - .ro_board_platform = "meson6", - .series = cpuinfo_arm_chipset_series_amlogic_aml, - .model = 8726, - .suffix = "-MX", - }, - { - /* "meson8" -> Amlogic S805 */ - .ro_board_platform = "meson8", - .series = cpuinfo_arm_chipset_series_amlogic_s, - .model = 805, - }, -#endif /* CPUINFO_ARCH_ARM */ - { - /* "gxbaby" -> Amlogic S905 */ - .ro_board_platform = "gxbaby", - .series = cpuinfo_arm_chipset_series_amlogic_s, - .model = 905, - }, - { - /* "gxl" -> Amlogic S905X */ - .ro_board_platform = "gxl", - .series = cpuinfo_arm_chipset_series_amlogic_s, - .model = 905, - .suffix = "X", - }, - { - /* "gxm" -> Amlogic S912 */ - .ro_board_platform = "gxm", - .series = cpuinfo_arm_chipset_series_amlogic_s, - .model = 912, - }, - }; +struct amlogic_map_entry { + char ro_board_platform[6]; + uint16_t model; + uint8_t series; + char suffix[3]; +}; - static const struct special_map_entry special_platform_map_entries[] = { +static const struct amlogic_map_entry amlogic_map_entries[] = { #if CPUINFO_ARCH_ARM - { - /* "hi6620oem" -> HiSilicon Kirin 910T */ - .platform = "hi6620oem", - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = 910, - .suffix = 'T', - }, + { + /* "meson3" -> Amlogic AML8726-M */ + .ro_board_platform = "meson3", + .series = cpuinfo_arm_chipset_series_amlogic_aml, + .model = 8726, + .suffix = "-M", + }, + { + /* "meson6" -> Amlogic AML8726-MX */ + .ro_board_platform = "meson6", + .series = cpuinfo_arm_chipset_series_amlogic_aml, + .model = 8726, + .suffix = "-MX", + }, + { + /* "meson8" -> Amlogic S805 */ + .ro_board_platform = "meson8", + .series = cpuinfo_arm_chipset_series_amlogic_s, + .model = 805, + }, #endif /* CPUINFO_ARCH_ARM */ - { - /* "hi6250" -> HiSilicon Kirin 650 */ - .platform = "hi6250", - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = 650, - }, - { - /* "hi6210sft" -> HiSilicon Kirin 620 */ - .platform = "hi6210sft", - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = 620, - }, + { + /* "gxbaby" -> Amlogic S905 */ + .ro_board_platform = "gxbaby", + .series = cpuinfo_arm_chipset_series_amlogic_s, + .model = 905, + }, + { + /* "gxl" -> Amlogic S905X */ + .ro_board_platform = "gxl", + .series = cpuinfo_arm_chipset_series_amlogic_s, + .model = 905, + .suffix = "X", + }, + { + /* "gxm" -> Amlogic S912 */ + .ro_board_platform = "gxm", + .series = cpuinfo_arm_chipset_series_amlogic_s, + .model = 912, + }, +}; + +static const struct special_map_entry special_platform_map_entries[] = { #if CPUINFO_ARCH_ARM - { - /* "hi3630" -> HiSilicon Kirin 920 */ - .platform = "hi3630", - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = 920, - }, + { + /* "hi6620oem" -> HiSilicon Kirin 910T */ + .platform = "hi6620oem", + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = 910, + .suffix = 'T', + }, #endif /* CPUINFO_ARCH_ARM */ - { - /* "hi3635" -> HiSilicon Kirin 930 */ - .platform = "hi3635", - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = 930, - }, - { - /* "hi3650" -> HiSilicon Kirin 950 */ - .platform = "hi3650", - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = 950, - }, - { - /* "hi3660" -> HiSilicon Kirin 960 */ - .platform = "hi3660", - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = 960, - }, + { + /* "hi6250" -> HiSilicon Kirin 650 */ + .platform = "hi6250", + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = 650, + }, + { + /* "hi6210sft" -> HiSilicon Kirin 620 */ + .platform = "hi6210sft", + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = 620, + }, #if CPUINFO_ARCH_ARM - { - /* "k3v2oem1" -> HiSilicon K3V2 */ - .platform = "k3v2oem1", - .series = cpuinfo_arm_chipset_series_hisilicon_k3v, - .model = 2, - }, - { - /* "k3v200" -> HiSilicon K3V2 */ - .platform = "k3v200", - .series = cpuinfo_arm_chipset_series_hisilicon_k3v, - .model = 2, - }, - { - /* "montblanc" -> NovaThor U8500 */ - .platform = "montblanc", - .series = cpuinfo_arm_chipset_series_novathor_u, - .model = 8500, - }, + { + /* "hi3630" -> HiSilicon Kirin 920 */ + .platform = "hi3630", + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = 920, + }, #endif /* CPUINFO_ARCH_ARM */ - { - /* "song" -> Pinecone Surge S1 */ - .platform = "song", - .series = cpuinfo_arm_chipset_series_pinecone_surge_s, - .model = 1, - }, + { + /* "hi3635" -> HiSilicon Kirin 930 */ + .platform = "hi3635", + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = 930, + }, + { + /* "hi3650" -> HiSilicon Kirin 950 */ + .platform = "hi3650", + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = 950, + }, + { + /* "hi3660" -> HiSilicon Kirin 960 */ + .platform = "hi3660", + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = 960, + }, #if CPUINFO_ARCH_ARM - { - /* "rk322x" -> RockChip RK3229 */ - .platform = "rk322x", - .series = cpuinfo_arm_chipset_series_rockchip_rk, - .model = 3229, - }, + { + /* "k3v2oem1" -> HiSilicon K3V2 */ + .platform = "k3v2oem1", + .series = cpuinfo_arm_chipset_series_hisilicon_k3v, + .model = 2, + }, + { + /* "k3v200" -> HiSilicon K3V2 */ + .platform = "k3v200", + .series = cpuinfo_arm_chipset_series_hisilicon_k3v, + .model = 2, + }, + { + /* "montblanc" -> NovaThor U8500 */ + .platform = "montblanc", + .series = cpuinfo_arm_chipset_series_novathor_u, + .model = 8500, + }, #endif /* CPUINFO_ARCH_ARM */ - { - /* "tegra132" -> Nvidia Tegra T132 */ - .platform = "tegra132", - .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, - .model = 132, - }, - { - /* "tegra210_dragon" -> Nvidia Tegra T210 */ - .platform = "tegra210_dragon", - .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, - .model = 210, - }, + { + /* "song" -> Pinecone Surge S1 */ + .platform = "song", + .series = cpuinfo_arm_chipset_series_pinecone_surge_s, + .model = 1, + }, #if CPUINFO_ARCH_ARM - { - /* "tegra4" -> Nvidia Tegra T114 */ - .platform = "tegra4", - .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, - .model = 114, - }, - { - /* "s5pc110" -> Samsung Exynos 3110 */ - .platform = "s5pc110", - .series = cpuinfo_arm_chipset_series_samsung_exynos, - .model = 3110, - }, + { + /* "rk322x" -> RockChip RK3229 */ + .platform = "rk322x", + .series = cpuinfo_arm_chipset_series_rockchip_rk, + .model = 3229, + }, #endif /* CPUINFO_ARCH_ARM */ - }; - - /* - * Decodes chipset name from ro.board.platform Android system property. - * For some chipsets, the function relies frequency and on number of cores for chipset detection. - * - * @param[in] platform - ro.board.platform value. - * @param cores - number of cores in the chipset. - * @param max_cpu_freq_max - maximum of /sys/devices/system/cpu/cpu/cpofreq/cpu_freq_max values. - * - * @returns Decoded chipset name. If chipset could not be decoded, the resulting structure would use `unknown` vendor - * and series identifiers. - */ - struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_board_platform( - const char platform[restrict static CPUINFO_BUILD_PROP_VALUE_MAX], - uint32_t cores, uint32_t max_cpu_freq_max) { - struct cpuinfo_arm_chipset chipset; - const size_t platform_length = strnlen(platform, CPUINFO_BUILD_PROP_VALUE_MAX); - const char* platform_end = platform + platform_length; - - /* Check Qualcomm MSM/APQ signature */ - if (match_msm_apq(platform, platform_end, &chipset)) { - cpuinfo_log_debug( - "matched Qualcomm MSM/APQ signature in ro.board.platform string \"%.*s\"", - (int) platform_length, platform); - return chipset; - } + /* "tegra132" -> Nvidia Tegra T132 */ + .platform = "tegra132", + .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, + .model = 132, + }, + { + /* "tegra210_dragon" -> Nvidia Tegra T210 */ + .platform = "tegra210_dragon", + .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, + .model = 210, + }, +#if CPUINFO_ARCH_ARM + { + /* "tegra4" -> Nvidia Tegra T114 */ + .platform = "tegra4", + .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, + .model = 114, + }, + { + /* "s5pc110" -> Samsung Exynos 3110 */ + .platform = "s5pc110", + .series = cpuinfo_arm_chipset_series_samsung_exynos, + .model = 3110, + }, +#endif /* CPUINFO_ARCH_ARM */ +}; - /* Check exynosXXXX (Samsung Exynos) signature */ - if (match_exynos(platform, platform_end, &chipset)) { - cpuinfo_log_debug( - "matched exynosXXXX (Samsung Exynos) signature in ro.board.platform string \"%.*s\"", - (int) platform_length, platform); - return chipset; - } +/* + * Decodes chipset name from ro.board.platform Android system property. + * For some chipsets, the function relies frequency and on number of cores for + * chipset detection. + * + * @param[in] platform - ro.board.platform value. + * @param cores - number of cores in the chipset. + * @param max_cpu_freq_max - maximum of + * /sys/devices/system/cpu/cpu/cpofreq/cpu_freq_max values. + * + * @returns Decoded chipset name. If chipset could not be decoded, the resulting + * structure would use `unknown` vendor and series identifiers. + */ +struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_board_platform( + const char platform[restrict static CPUINFO_BUILD_PROP_VALUE_MAX], + uint32_t cores, + uint32_t max_cpu_freq_max) { + struct cpuinfo_arm_chipset chipset; + const size_t platform_length = strnlen(platform, CPUINFO_BUILD_PROP_VALUE_MAX); + const char* platform_end = platform + platform_length; + + /* Check Qualcomm MSM/APQ signature */ + if (match_msm_apq(platform, platform_end, &chipset)) { + cpuinfo_log_debug( + "matched Qualcomm MSM/APQ signature in ro.board.platform string \"%.*s\"", + (int)platform_length, + platform); + return chipset; + } - /* Check MediaTek MT signature */ - if (match_mt(platform, platform_end, true, &chipset)) { - cpuinfo_log_debug( - "matched MediaTek MT signature in ro.board.platform string \"%.*s\"", (int) platform_length, platform); - return chipset; - } + /* Check exynosXXXX (Samsung Exynos) signature */ + if (match_exynos(platform, platform_end, &chipset)) { + cpuinfo_log_debug( + "matched exynosXXXX (Samsung Exynos) signature in ro.board.platform string \"%.*s\"", + (int)platform_length, + platform); + return chipset; + } - /* Check HiSilicon Kirin signature */ - if (match_kirin(platform, platform_end, &chipset)) { - cpuinfo_log_debug( - "matched HiSilicon Kirin signature in ro.board.platform string \"%.*s\"", (int) platform_length, platform); - return chipset; - } + /* Check MediaTek MT signature */ + if (match_mt(platform, platform_end, true, &chipset)) { + cpuinfo_log_debug( + "matched MediaTek MT signature in ro.board.platform string \"%.*s\"", + (int)platform_length, + platform); + return chipset; + } - /* Check Spreadtrum SC signature */ - if (match_sc(platform, platform_end, &chipset)) { - cpuinfo_log_debug( - "matched Spreadtrum SC signature in ro.board.platform string \"%.*s\"", (int) platform_length, platform); - return chipset; - } + /* Check HiSilicon Kirin signature */ + if (match_kirin(platform, platform_end, &chipset)) { + cpuinfo_log_debug( + "matched HiSilicon Kirin signature in ro.board.platform string \"%.*s\"", + (int)platform_length, + platform); + return chipset; + } - /* Check Rockchip RK signature */ - if (match_rk(platform, platform_end, &chipset)) { - cpuinfo_log_debug( - "matched Rockchip RK signature in ro.board.platform string \"%.*s\"", (int) platform_length, platform); - return chipset; - } + /* Check Spreadtrum SC signature */ + if (match_sc(platform, platform_end, &chipset)) { + cpuinfo_log_debug( + "matched Spreadtrum SC signature in ro.board.platform string \"%.*s\"", + (int)platform_length, + platform); + return chipset; + } - #if CPUINFO_ARCH_ARM - /* Check Leadcore LCxxxx signature */ - if (match_lc(platform, platform_end, &chipset)) { - cpuinfo_log_debug( - "matched Leadcore LC signature in ro.board.platform string \"%.*s\"", (int) platform_length, platform); - return chipset; - } - #endif + /* Check Rockchip RK signature */ + if (match_rk(platform, platform_end, &chipset)) { + cpuinfo_log_debug( + "matched Rockchip RK signature in ro.board.platform string \"%.*s\"", + (int)platform_length, + platform); + return chipset; + } - /* Compare to tabulated ro.board.platform values for Huawei devices which don't report chipset elsewhere */ - if (match_and_parse_huawei(platform, platform_end, &chipset)) { - cpuinfo_log_debug( - "found ro.board.platform string \"%.*s\" in Huawei chipset table", - (int) platform_length, platform); - return chipset; - } +#if CPUINFO_ARCH_ARM + /* Check Leadcore LCxxxx signature */ + if (match_lc(platform, platform_end, &chipset)) { + cpuinfo_log_debug( + "matched Leadcore LC signature in ro.board.platform string \"%.*s\"", + (int)platform_length, + platform); + return chipset; + } +#endif - #if CPUINFO_ARCH_ARM - /* - * Compare to known ro.board.platform values for Broadcom devices and - * detect chipset from frequency and number of cores - */ - if (match_and_parse_broadcom(platform, platform_end, cores, max_cpu_freq_max, &chipset)) { - cpuinfo_log_debug( - "found ro.board.platform string \"%.*s\" in Broadcom chipset table", - (int) platform_length, platform); - return chipset; - } + /* Compare to tabulated ro.board.platform values for Huawei devices + * which don't report chipset elsewhere */ + if (match_and_parse_huawei(platform, platform_end, &chipset)) { + cpuinfo_log_debug( + "found ro.board.platform string \"%.*s\" in Huawei chipset table", + (int)platform_length, + platform); + return chipset; + } - /* - * Compare to ro.board.platform value ("omap4") for OMAP4xxx chipsets. - * Upon successful match, detect OMAP4430 from frequency and number of cores. - */ - if (platform_length == 5 && cores == 2 && max_cpu_freq_max == 1008000 && memcmp(platform, "omap4", 5) == 0) { - cpuinfo_log_debug( - "matched Texas Instruments OMAP4 signature in ro.board.platform string \"%.*s\"", - (int) platform_length, platform); +#if CPUINFO_ARCH_ARM + /* + * Compare to known ro.board.platform values for Broadcom devices and + * detect chipset from frequency and number of cores + */ + if (match_and_parse_broadcom(platform, platform_end, cores, max_cpu_freq_max, &chipset)) { + cpuinfo_log_debug( + "found ro.board.platform string \"%.*s\" in Broadcom chipset table", + (int)platform_length, + platform); + return chipset; + } - return (struct cpuinfo_arm_chipset) { - .vendor = cpuinfo_arm_chipset_vendor_texas_instruments, - .series = cpuinfo_arm_chipset_series_texas_instruments_omap, - .model = 4430, - }; - } - #endif + /* + * Compare to ro.board.platform value ("omap4") for OMAP4xxx chipsets. + * Upon successful match, detect OMAP4430 from frequency and number of + * cores. + */ + if (platform_length == 5 && cores == 2 && max_cpu_freq_max == 1008000 && memcmp(platform, "omap4", 5) == 0) { + cpuinfo_log_debug( + "matched Texas Instruments OMAP4 signature in ro.board.platform string \"%.*s\"", + (int)platform_length, + platform); + + return (struct cpuinfo_arm_chipset){ + .vendor = cpuinfo_arm_chipset_vendor_texas_instruments, + .series = cpuinfo_arm_chipset_series_texas_instruments_omap, + .model = 4430, + }; + } +#endif - /* - * Compare to tabulated ro.board.platform values for Amlogic chipsets/devices which can't be otherwise detected. - * The tabulated Amlogic ro.board.platform values have not more than 6 characters. - */ - if (platform_length <= 6) { - for (size_t i = 0; i < CPUINFO_COUNT_OF(amlogic_map_entries); i++) { - if (strncmp(amlogic_map_entries[i].ro_board_platform, platform, 6) == 0) { - cpuinfo_log_debug( - "found ro.board.platform string \"%.*s\" in Amlogic chipset table", - (int) platform_length, platform); - /* Create chipset name from entry */ - return (struct cpuinfo_arm_chipset) { - .vendor = cpuinfo_arm_chipset_vendor_amlogic, - .series = (enum cpuinfo_arm_chipset_series) amlogic_map_entries[i].series, - .model = amlogic_map_entries[i].model, - .suffix = { + /* + * Compare to tabulated ro.board.platform values for Amlogic + * chipsets/devices which can't be otherwise detected. The tabulated + * Amlogic ro.board.platform values have not more than 6 characters. + */ + if (platform_length <= 6) { + for (size_t i = 0; i < CPUINFO_COUNT_OF(amlogic_map_entries); i++) { + if (strncmp(amlogic_map_entries[i].ro_board_platform, platform, 6) == 0) { + cpuinfo_log_debug( + "found ro.board.platform string \"%.*s\" in Amlogic chipset table", + (int)platform_length, + platform); + /* Create chipset name from entry */ + return (struct cpuinfo_arm_chipset){ + .vendor = cpuinfo_arm_chipset_vendor_amlogic, + .series = (enum cpuinfo_arm_chipset_series)amlogic_map_entries[i].series, + .model = amlogic_map_entries[i].model, + .suffix = + { [0] = amlogic_map_entries[i].suffix[0], [1] = amlogic_map_entries[i].suffix[1], [2] = amlogic_map_entries[i].suffix[2], }, - }; - } + }; } } + } - /* Compare to tabulated ro.board.platform values for popular chipsets/devices which can't be otherwise detected */ - for (size_t i = 0; i < CPUINFO_COUNT_OF(special_platform_map_entries); i++) { - if (strncmp(special_platform_map_entries[i].platform, platform, platform_length) == 0 && - special_platform_map_entries[i].platform[platform_length] == 0) - { - /* Create chipset name from entry */ - cpuinfo_log_debug( - "found ro.board.platform string \"%.*s\" in special chipset table", (int) platform_length, platform); - return (struct cpuinfo_arm_chipset) { - .vendor = chipset_series_vendor[special_platform_map_entries[i].series], - .series = (enum cpuinfo_arm_chipset_series) special_platform_map_entries[i].series, - .model = special_platform_map_entries[i].model, - .suffix = { + /* Compare to tabulated ro.board.platform values for popular + * chipsets/devices which can't be otherwise detected */ + for (size_t i = 0; i < CPUINFO_COUNT_OF(special_platform_map_entries); i++) { + if (strncmp(special_platform_map_entries[i].platform, platform, platform_length) == 0 && + special_platform_map_entries[i].platform[platform_length] == 0) { + /* Create chipset name from entry */ + cpuinfo_log_debug( + "found ro.board.platform string \"%.*s\" in special chipset table", + (int)platform_length, + platform); + return (struct cpuinfo_arm_chipset){ + .vendor = chipset_series_vendor[special_platform_map_entries[i].series], + .series = (enum cpuinfo_arm_chipset_series)special_platform_map_entries[i].series, + .model = special_platform_map_entries[i].model, + .suffix = + { [0] = special_platform_map_entries[i].suffix, }, - }; - } + }; } - - /* None of the ro.board.platform signatures matched, indicate unknown chipset */ - return (struct cpuinfo_arm_chipset) { - .vendor = cpuinfo_arm_chipset_vendor_unknown, - .series = cpuinfo_arm_chipset_series_unknown, - }; } - /* - * Decodes chipset name from ro.mediatek.platform Android system property. - * - * @param[in] platform - ro.mediatek.platform value. - * - * @returns Decoded chipset name. If chipset could not be decoded, the resulting structure would use `unknown` - * vendor and series identifiers. + /* None of the ro.board.platform signatures matched, indicate unknown + * chipset */ - struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_mediatek_platform( - const char platform[restrict static CPUINFO_BUILD_PROP_VALUE_MAX]) - { - struct cpuinfo_arm_chipset chipset; - const char* platform_end = platform + strnlen(platform, CPUINFO_BUILD_PROP_VALUE_MAX); + return (struct cpuinfo_arm_chipset){ + .vendor = cpuinfo_arm_chipset_vendor_unknown, + .series = cpuinfo_arm_chipset_series_unknown, + }; +} - /* Check MediaTek MT signature */ - if (match_mt(platform, platform_end, false, &chipset)) { - return chipset; - } +/* + * Decodes chipset name from ro.mediatek.platform Android system property. + * + * @param[in] platform - ro.mediatek.platform value. + * + * @returns Decoded chipset name. If chipset could not be decoded, the resulting + * structure would use `unknown` vendor and series identifiers. + */ +struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_mediatek_platform( + const char platform[restrict static CPUINFO_BUILD_PROP_VALUE_MAX]) { + struct cpuinfo_arm_chipset chipset; + const char* platform_end = platform + strnlen(platform, CPUINFO_BUILD_PROP_VALUE_MAX); - return (struct cpuinfo_arm_chipset) { - .vendor = cpuinfo_arm_chipset_vendor_unknown, - .series = cpuinfo_arm_chipset_series_unknown, - }; + /* Check MediaTek MT signature */ + if (match_mt(platform, platform_end, false, &chipset)) { + return chipset; } + return (struct cpuinfo_arm_chipset){ + .vendor = cpuinfo_arm_chipset_vendor_unknown, + .series = cpuinfo_arm_chipset_series_unknown, + }; +} - /* - * Decodes chipset name from ro.arch Android system property. - * - * The ro.arch property is matched only against Samsung Exynos signature. Systems with other chipset rarely - * configure ro.arch Android system property, and can be decoded through other properties, but some Exynos - * chipsets are identified only in ro.arch. - * - * @param[in] arch - ro.arch value. - * - * @returns Decoded chipset name. If chipset could not be decoded, the resulting structure would use `unknown` - * vendor and series identifiers. - */ - struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_arch( - const char arch[restrict static CPUINFO_BUILD_PROP_VALUE_MAX]) - { - struct cpuinfo_arm_chipset chipset; - const char* arch_end = arch + strnlen(arch, CPUINFO_BUILD_PROP_VALUE_MAX); - - /* Check Samsung exynosXXXX signature */ - if (match_exynos(arch, arch_end, &chipset)) { - return chipset; - } +/* + * Decodes chipset name from ro.arch Android system property. + * + * The ro.arch property is matched only against Samsung Exynos signature. + * Systems with other chipset rarely configure ro.arch Android system property, + * and can be decoded through other properties, but some Exynos chipsets are + * identified only in ro.arch. + * + * @param[in] arch - ro.arch value. + * + * @returns Decoded chipset name. If chipset could not be decoded, the resulting + * structure would use `unknown` vendor and series identifiers. + */ +struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_arch( + const char arch[restrict static CPUINFO_BUILD_PROP_VALUE_MAX]) { + struct cpuinfo_arm_chipset chipset; + const char* arch_end = arch + strnlen(arch, CPUINFO_BUILD_PROP_VALUE_MAX); - return (struct cpuinfo_arm_chipset) { - .vendor = cpuinfo_arm_chipset_vendor_unknown, - .series = cpuinfo_arm_chipset_series_unknown, - }; + /* Check Samsung exynosXXXX signature */ + if (match_exynos(arch, arch_end, &chipset)) { + return chipset; } - /* - * Decodes chipset name from ro.chipname or ro.hardware.chipname Android system property. - * - * @param[in] chipname - ro.chipname or ro.hardware.chipname value. - * - * @returns Decoded chipset name. If chipset could not be decoded, the resulting structure would use `unknown` vendor - * and series identifiers. - */ - - struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_chipname( - const char chipname[restrict static CPUINFO_BUILD_PROP_VALUE_MAX]) - { - struct cpuinfo_arm_chipset chipset; - const size_t chipname_length = strnlen(chipname, CPUINFO_BUILD_PROP_VALUE_MAX); - const char* chipname_end = chipname + chipname_length; + return (struct cpuinfo_arm_chipset){ + .vendor = cpuinfo_arm_chipset_vendor_unknown, + .series = cpuinfo_arm_chipset_series_unknown, + }; +} - /* Check Qualcomm MSM/APQ signatures */ - if (match_msm_apq(chipname, chipname_end, &chipset)) { - cpuinfo_log_debug( - "matched Qualcomm MSM/APQ signature in ro.chipname string \"%.*s\"", - (int) chipname_length, chipname); - return chipset; - } +/* + * Decodes chipset name from ro.chipname or ro.hardware.chipname Android system + * property. + * + * @param[in] chipname - ro.chipname or ro.hardware.chipname value. + * + * @returns Decoded chipset name. If chipset could not be decoded, the resulting + * structure would use `unknown` vendor and series identifiers. + */ - /* Check SMxxxx (Qualcomm Snapdragon) signature */ - if (match_sm(chipname, chipname_end, &chipset)) { - cpuinfo_log_debug( - "matched Qualcomm SM signature in /proc/cpuinfo Hardware string \"%.*s\"", - (int) chipname_length, chipname); - return chipset; - } +struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset_from_ro_chipname( + const char chipname[restrict static CPUINFO_BUILD_PROP_VALUE_MAX]) { + struct cpuinfo_arm_chipset chipset; + const size_t chipname_length = strnlen(chipname, CPUINFO_BUILD_PROP_VALUE_MAX); + const char* chipname_end = chipname + chipname_length; + + /* Check Qualcomm MSM/APQ signatures */ + if (match_msm_apq(chipname, chipname_end, &chipset)) { + cpuinfo_log_debug( + "matched Qualcomm MSM/APQ signature in ro.chipname string \"%.*s\"", + (int)chipname_length, + chipname); + return chipset; + } - /* Check exynosXXXX (Samsung Exynos) signature */ - if (match_exynos(chipname, chipname_end, &chipset)) { - cpuinfo_log_debug( - "matched exynosXXXX (Samsung Exynos) signature in ro.chipname string \"%.*s\"", - (int) chipname_length, chipname); - return chipset; - } + /* Check SMxxxx (Qualcomm Snapdragon) signature */ + if (match_sm(chipname, chipname_end, &chipset)) { + cpuinfo_log_debug( + "matched Qualcomm SM signature in /proc/cpuinfo Hardware string \"%.*s\"", + (int)chipname_length, + chipname); + return chipset; + } - /* Check universalXXXX (Samsung Exynos) signature */ - if (match_universal(chipname, chipname_end, &chipset)) { - cpuinfo_log_debug( - "matched UNIVERSAL (Samsung Exynos) signature in ro.chipname Hardware string \"%.*s\"", - (int) chipname_length, chipname); - return chipset; - } + /* Check exynosXXXX (Samsung Exynos) signature */ + if (match_exynos(chipname, chipname_end, &chipset)) { + cpuinfo_log_debug( + "matched exynosXXXX (Samsung Exynos) signature in ro.chipname string \"%.*s\"", + (int)chipname_length, + chipname); + return chipset; + } - /* Check MediaTek MT signature */ - if (match_mt(chipname, chipname_end, true, &chipset)) { - cpuinfo_log_debug( - "matched MediaTek MT signature in ro.chipname string \"%.*s\"", - (int) chipname_length, chipname); - return chipset; - } + /* Check universalXXXX (Samsung Exynos) signature */ + if (match_universal(chipname, chipname_end, &chipset)) { + cpuinfo_log_debug( + "matched UNIVERSAL (Samsung Exynos) signature in ro.chipname Hardware string \"%.*s\"", + (int)chipname_length, + chipname); + return chipset; + } - /* Check Spreadtrum SC signature */ - if (match_sc(chipname, chipname_end, &chipset)) { - cpuinfo_log_debug( - "matched Spreadtrum SC signature in ro.chipname string \"%.*s\"", - (int) chipname_length, chipname); - return chipset; - } + /* Check MediaTek MT signature */ + if (match_mt(chipname, chipname_end, true, &chipset)) { + cpuinfo_log_debug( + "matched MediaTek MT signature in ro.chipname string \"%.*s\"", (int)chipname_length, chipname); + return chipset; + } - #if CPUINFO_ARCH_ARM - /* Check Marvell PXA signature */ - if (match_pxa(chipname, chipname_end, &chipset)) { - cpuinfo_log_debug( - "matched Marvell PXA signature in ro.chipname string \"%.*s\"", - (int) chipname_length, chipname); - return chipset; - } + /* Check Spreadtrum SC signature */ + if (match_sc(chipname, chipname_end, &chipset)) { + cpuinfo_log_debug( + "matched Spreadtrum SC signature in ro.chipname string \"%.*s\"", + (int)chipname_length, + chipname); + return chipset; + } - /* Compare to ro.chipname value ("mp523x") for Renesas MP5232 which can't be otherwise detected */ - if (chipname_length == 6 && memcmp(chipname, "mp523x", 6) == 0) { - cpuinfo_log_debug( - "matched Renesas MP5232 signature in ro.chipname string \"%.*s\"", - (int) chipname_length, chipname); +#if CPUINFO_ARCH_ARM + /* Check Marvell PXA signature */ + if (match_pxa(chipname, chipname_end, &chipset)) { + cpuinfo_log_debug( + "matched Marvell PXA signature in ro.chipname string \"%.*s\"", (int)chipname_length, chipname); + return chipset; + } - return (struct cpuinfo_arm_chipset) { - .vendor = cpuinfo_arm_chipset_vendor_renesas, - .series = cpuinfo_arm_chipset_series_renesas_mp, - .model = 5232, - }; - } - #endif + /* Compare to ro.chipname value ("mp523x") for Renesas MP5232 which + * can't be otherwise detected */ + if (chipname_length == 6 && memcmp(chipname, "mp523x", 6) == 0) { + cpuinfo_log_debug( + "matched Renesas MP5232 signature in ro.chipname string \"%.*s\"", + (int)chipname_length, + chipname); - return (struct cpuinfo_arm_chipset) { - .vendor = cpuinfo_arm_chipset_vendor_unknown, - .series = cpuinfo_arm_chipset_series_unknown, + return (struct cpuinfo_arm_chipset){ + .vendor = cpuinfo_arm_chipset_vendor_renesas, + .series = cpuinfo_arm_chipset_series_renesas_mp, + .model = 5232, }; } +#endif + + return (struct cpuinfo_arm_chipset){ + .vendor = cpuinfo_arm_chipset_vendor_unknown, + .series = cpuinfo_arm_chipset_series_unknown, + }; +} #endif /* __ANDROID__ */ /* @@ -3217,96 +3362,136 @@ struct cpuinfo_arm_chipset cpuinfo_arm_linux_decode_chipset_from_proc_cpuinfo_ha * * @param[in,out] chipset - chipset name to fix. * @param cores - number of cores in the chipset. - * @param max_cpu_freq_max - maximum of /sys/devices/system/cpu/cpu/cpofreq/cpu_freq_max values. + * @param max_cpu_freq_max - maximum of + * /sys/devices/system/cpu/cpu/cpofreq/cpu_freq_max values. */ void cpuinfo_arm_fixup_chipset( - struct cpuinfo_arm_chipset chipset[restrict static 1], uint32_t cores, uint32_t max_cpu_freq_max) -{ + struct cpuinfo_arm_chipset chipset[restrict static 1], + uint32_t cores, + uint32_t max_cpu_freq_max) { switch (chipset->series) { case cpuinfo_arm_chipset_series_qualcomm_msm: /* Check if there is suffix */ if (chipset->suffix[0] == 0) { - /* No suffix, but the model may be misreported */ + /* No suffix, but the model may be misreported + */ switch (chipset->model) { case 8216: - /* MSM8216 was renamed to MSM8916 */ + /* MSM8216 was renamed to + * MSM8916 */ cpuinfo_log_info("reinterpreted MSM8216 chipset as MSM8916"); chipset->model = 8916; break; case 8916: - /* Common bug: MSM8939 (Octa-core) reported as MSM8916 (Quad-core) */ + /* Common bug: MSM8939 + * (Octa-core) reported as + * MSM8916 (Quad-core) + */ switch (cores) { case 4: break; case 8: - cpuinfo_log_info("reinterpreted MSM8916 chipset with 8 cores as MSM8939"); + cpuinfo_log_info( + "reinterpreted MSM8916 chipset with 8 cores as MSM8939"); chipset->model = 8939; break; default: - cpuinfo_log_warning("system reported invalid %"PRIu32"-core MSM%"PRIu32" chipset", - cores, chipset->model); + cpuinfo_log_warning( + "system reported invalid %" PRIu32 + "-core MSM%" PRIu32 " chipset", + cores, + chipset->model); chipset->model = 0; } break; case 8937: - /* Common bug: MSM8917 (Quad-core) reported as MSM8937 (Octa-core) */ + /* Common bug: MSM8917 + * (Quad-core) reported as + * MSM8937 (Octa-core) + */ switch (cores) { case 4: - cpuinfo_log_info("reinterpreted MSM8937 chipset with 4 cores as MSM8917"); + cpuinfo_log_info( + "reinterpreted MSM8937 chipset with 4 cores as MSM8917"); chipset->model = 8917; break; case 8: break; default: - cpuinfo_log_warning("system reported invalid %"PRIu32"-core MSM%"PRIu32" chipset", - cores, chipset->model); + cpuinfo_log_warning( + "system reported invalid %" PRIu32 + "-core MSM%" PRIu32 " chipset", + cores, + chipset->model); chipset->model = 0; } break; case 8960: - /* Common bug: APQ8064 (Quad-core) reported as MSM8960 (Dual-core) */ + /* Common bug: APQ8064 + * (Quad-core) reported as + * MSM8960 (Dual-core) + */ switch (cores) { case 2: break; case 4: - cpuinfo_log_info("reinterpreted MSM8960 chipset with 4 cores as APQ8064"); - chipset->series = cpuinfo_arm_chipset_series_qualcomm_apq; + cpuinfo_log_info( + "reinterpreted MSM8960 chipset with 4 cores as APQ8064"); + chipset->series = + cpuinfo_arm_chipset_series_qualcomm_apq; chipset->model = 8064; break; default: - cpuinfo_log_warning("system reported invalid %"PRIu32"-core MSM%"PRIu32" chipset", - cores, chipset->model); + cpuinfo_log_warning( + "system reported invalid %" PRIu32 + "-core MSM%" PRIu32 " chipset", + cores, + chipset->model); chipset->model = 0; } break; case 8996: - /* Common bug: MSM8994 (Octa-core) reported as MSM8996 (Quad-core) */ + /* Common bug: MSM8994 + * (Octa-core) reported as + * MSM8996 (Quad-core) + */ switch (cores) { case 4: break; case 8: - cpuinfo_log_info("reinterpreted MSM8996 chipset with 8 cores as MSM8994"); + cpuinfo_log_info( + "reinterpreted MSM8996 chipset with 8 cores as MSM8994"); chipset->model = 8994; break; default: - cpuinfo_log_warning("system reported invalid %"PRIu32"-core MSM%"PRIu32" chipset", - cores, chipset->model); + cpuinfo_log_warning( + "system reported invalid %" PRIu32 + "-core MSM%" PRIu32 " chipset", + cores, + chipset->model); chipset->model = 0; } break; #if CPUINFO_ARCH_ARM case 8610: - /* Common bug: MSM8612 (Quad-core) reported as MSM8610 (Dual-core) */ + /* Common bug: MSM8612 + * (Quad-core) reported as + * MSM8610 (Dual-core) + */ switch (cores) { case 2: break; case 4: - cpuinfo_log_info("reinterpreted MSM8610 chipset with 4 cores as MSM8612"); + cpuinfo_log_info( + "reinterpreted MSM8610 chipset with 4 cores as MSM8612"); chipset->model = 8612; break; default: - cpuinfo_log_warning("system reported invalid %"PRIu32"-core MSM%"PRIu32" chipset", - cores, chipset->model); + cpuinfo_log_warning( + "system reported invalid %" PRIu32 + "-core MSM%" PRIu32 " chipset", + cores, + chipset->model); chipset->model = 0; } break; @@ -3317,8 +3502,10 @@ void cpuinfo_arm_fixup_chipset( const uint32_t suffix_word = load_u32le(chipset->suffix); if (suffix_word == UINT32_C(0x004D534D) /* "\0MSM" = reverse("MSM\0") */) { /* - * Common bug: model name repeated twice, e.g. "MSM8916MSM8916" - * In this case, model matching code parses the second "MSM" as a suffix + * Common bug: model name repeated + * twice, e.g. "MSM8916MSM8916" In this + * case, model matching code parses the + * second "MSM" as a suffix */ chipset->suffix[0] = 0; chipset->suffix[1] = 0; @@ -3326,33 +3513,39 @@ void cpuinfo_arm_fixup_chipset( } else { switch (chipset->model) { case 8976: - /* MSM8976SG -> MSM8976PRO */ - if (suffix_word == UINT32_C(0x00004753) /* "\0\0GS" = reverse("SG\0\0") */ ) { + /* MSM8976SG -> + * MSM8976PRO */ + if (suffix_word == + UINT32_C(0x00004753) /* "\0\0GS" = reverse("SG\0\0") */) { chipset->suffix[0] = 'P'; chipset->suffix[1] = 'R'; chipset->suffix[2] = 'O'; } break; case 8996: - /* MSM8996PRO -> MSM8996PRO-AB or MSM8996PRO-AC */ - if (suffix_word == UINT32_C(0x004F5250) /* "\0ORP" = reverse("PRO\0") */ ) { + /* MSM8996PRO -> + * MSM8996PRO-AB or + * MSM8996PRO-AC */ + if (suffix_word == + UINT32_C(0x004F5250) /* "\0ORP" = reverse("PRO\0") */) { chipset->suffix[3] = '-'; chipset->suffix[4] = 'A'; - chipset->suffix[5] = 'B' + (char) (max_cpu_freq_max >= 2188800); + chipset->suffix[5] = + 'B' + (char)(max_cpu_freq_max >= 2188800); } break; } } } break; - case cpuinfo_arm_chipset_series_qualcomm_apq: - { + case cpuinfo_arm_chipset_series_qualcomm_apq: { /* Suffix may need correction */ const uint32_t expected_apq = load_u32le(chipset->suffix); if (expected_apq == UINT32_C(0x00515041) /* "\0QPA" = reverse("APQ\0") */) { /* - * Common bug: model name repeated twice, e.g. "APQ8016APQ8016" - * In this case, model matching code parses the second "APQ" as a suffix + * Common bug: model name repeated twice, e.g. + * "APQ8016APQ8016" In this case, model matching + * code parses the second "APQ" as a suffix */ chipset->suffix[0] = 0; chipset->suffix[1] = 0; @@ -3364,35 +3557,48 @@ void cpuinfo_arm_fixup_chipset( switch (chipset->model) { #if CPUINFO_ARCH_ARM case 4410: - /* Exynos 4410 was renamed to Exynos 4412 */ + /* Exynos 4410 was renamed to Exynos + * 4412 */ chipset->model = 4412; break; case 5420: - /* Common bug: Exynos 5260 (Hexa-core) reported as Exynos 5420 (Quad-core) */ + /* Common bug: Exynos 5260 (Hexa-core) + * reported as Exynos 5420 (Quad-core) + */ switch (cores) { case 4: break; case 6: - cpuinfo_log_info("reinterpreted Exynos 5420 chipset with 6 cores as Exynos 5260"); + cpuinfo_log_info( + "reinterpreted Exynos 5420 chipset with 6 cores as Exynos 5260"); chipset->model = 5260; break; default: - cpuinfo_log_warning("system reported invalid %"PRIu32"-core Exynos 5420 chipset", cores); + cpuinfo_log_warning( + "system reported invalid %" PRIu32 + "-core Exynos 5420 chipset", + cores); chipset->model = 0; } break; #endif /* CPUINFO_ARCH_ARM */ case 7580: - /* Common bug: Exynos 7578 (Quad-core) reported as Exynos 7580 (Octa-core) */ + /* Common bug: Exynos 7578 (Quad-core) + * reported as Exynos 7580 (Octa-core) + */ switch (cores) { case 4: - cpuinfo_log_info("reinterpreted Exynos 7580 chipset with 4 cores as Exynos 7578"); + cpuinfo_log_info( + "reinterpreted Exynos 7580 chipset with 4 cores as Exynos 7578"); chipset->model = 7578; break; case 8: break; default: - cpuinfo_log_warning("system reported invalid %"PRIu32"-core Exynos 7580 chipset", cores); + cpuinfo_log_warning( + "system reported invalid %" PRIu32 + "-core Exynos 7580 chipset", + cores); chipset->model = 0; } break; @@ -3400,7 +3606,8 @@ void cpuinfo_arm_fixup_chipset( break; case cpuinfo_arm_chipset_series_mediatek_mt: if (chipset->model == 6752) { - /* Common bug: MT6732 (Quad-core) reported as MT6752 (Octa-core) */ + /* Common bug: MT6732 (Quad-core) reported as + * MT6752 (Octa-core) */ switch (cores) { case 4: cpuinfo_log_info("reinterpreted MT6752 chipset with 4 cores as MT6732"); @@ -3409,16 +3616,23 @@ void cpuinfo_arm_fixup_chipset( case 8: break; default: - cpuinfo_log_warning("system reported invalid %"PRIu32"-core MT6752 chipset", cores); + cpuinfo_log_warning( + "system reported invalid %" PRIu32 "-core MT6752 chipset", + cores); chipset->model = 0; } } if (chipset->suffix[0] == 'T') { - /* Normalization: "TURBO" and "TRUBO" (apparently a typo) -> "T" */ + /* Normalization: "TURBO" and "TRUBO" + * (apparently a typo) -> "T" */ const uint32_t suffix_word = load_u32le(chipset->suffix + 1); switch (suffix_word) { - case UINT32_C(0x4F425255): /* "OBRU" = reverse("URBO") */ - case UINT32_C(0x4F425552): /* "OBUR" = reverse("RUBO") */ + case UINT32_C(0x4F425255): /* "OBRU" = + reverse("URBO") + */ + case UINT32_C(0x4F425552): /* "OBUR" = + reverse("RUBO") + */ if (chipset->suffix[5] == 0) { chipset->suffix[1] = 0; chipset->suffix[2] = 0; @@ -3431,7 +3645,8 @@ void cpuinfo_arm_fixup_chipset( break; case cpuinfo_arm_chipset_series_rockchip_rk: if (chipset->model == 3288) { - /* Common bug: Rockchip RK3399 (Hexa-core) always reported as RK3288 (Quad-core) */ + /* Common bug: Rockchip RK3399 (Hexa-core) + * always reported as RK3288 (Quad-core) */ switch (cores) { case 4: break; @@ -3440,7 +3655,9 @@ void cpuinfo_arm_fixup_chipset( chipset->model = 3399; break; default: - cpuinfo_log_warning("system reported invalid %"PRIu32"-core RK3288 chipset", cores); + cpuinfo_log_warning( + "system reported invalid %" PRIu32 "-core RK3288 chipset", + cores); chipset->model = 0; } } @@ -3452,71 +3669,71 @@ void cpuinfo_arm_fixup_chipset( /* Map from ARM chipset vendor ID to its string representation */ static const char* chipset_vendor_string[cpuinfo_arm_chipset_vendor_max] = { - [cpuinfo_arm_chipset_vendor_unknown] = "Unknown", - [cpuinfo_arm_chipset_vendor_qualcomm] = "Qualcomm", - [cpuinfo_arm_chipset_vendor_mediatek] = "MediaTek", - [cpuinfo_arm_chipset_vendor_samsung] = "Samsung", - [cpuinfo_arm_chipset_vendor_hisilicon] = "HiSilicon", - [cpuinfo_arm_chipset_vendor_actions] = "Actions", - [cpuinfo_arm_chipset_vendor_allwinner] = "Allwinner", - [cpuinfo_arm_chipset_vendor_amlogic] = "Amlogic", - [cpuinfo_arm_chipset_vendor_broadcom] = "Broadcom", - [cpuinfo_arm_chipset_vendor_lg] = "LG", - [cpuinfo_arm_chipset_vendor_leadcore] = "Leadcore", - [cpuinfo_arm_chipset_vendor_marvell] = "Marvell", - [cpuinfo_arm_chipset_vendor_mstar] = "MStar", - [cpuinfo_arm_chipset_vendor_novathor] = "NovaThor", - [cpuinfo_arm_chipset_vendor_nvidia] = "Nvidia", - [cpuinfo_arm_chipset_vendor_pinecone] = "Pinecone", - [cpuinfo_arm_chipset_vendor_renesas] = "Renesas", - [cpuinfo_arm_chipset_vendor_rockchip] = "Rockchip", - [cpuinfo_arm_chipset_vendor_spreadtrum] = "Spreadtrum", - [cpuinfo_arm_chipset_vendor_telechips] = "Telechips", + [cpuinfo_arm_chipset_vendor_unknown] = "Unknown", + [cpuinfo_arm_chipset_vendor_qualcomm] = "Qualcomm", + [cpuinfo_arm_chipset_vendor_mediatek] = "MediaTek", + [cpuinfo_arm_chipset_vendor_samsung] = "Samsung", + [cpuinfo_arm_chipset_vendor_hisilicon] = "HiSilicon", + [cpuinfo_arm_chipset_vendor_actions] = "Actions", + [cpuinfo_arm_chipset_vendor_allwinner] = "Allwinner", + [cpuinfo_arm_chipset_vendor_amlogic] = "Amlogic", + [cpuinfo_arm_chipset_vendor_broadcom] = "Broadcom", + [cpuinfo_arm_chipset_vendor_lg] = "LG", + [cpuinfo_arm_chipset_vendor_leadcore] = "Leadcore", + [cpuinfo_arm_chipset_vendor_marvell] = "Marvell", + [cpuinfo_arm_chipset_vendor_mstar] = "MStar", + [cpuinfo_arm_chipset_vendor_novathor] = "NovaThor", + [cpuinfo_arm_chipset_vendor_nvidia] = "Nvidia", + [cpuinfo_arm_chipset_vendor_pinecone] = "Pinecone", + [cpuinfo_arm_chipset_vendor_renesas] = "Renesas", + [cpuinfo_arm_chipset_vendor_rockchip] = "Rockchip", + [cpuinfo_arm_chipset_vendor_spreadtrum] = "Spreadtrum", + [cpuinfo_arm_chipset_vendor_telechips] = "Telechips", [cpuinfo_arm_chipset_vendor_texas_instruments] = "Texas Instruments", - [cpuinfo_arm_chipset_vendor_unisoc] = "Unisoc", - [cpuinfo_arm_chipset_vendor_wondermedia] = "WonderMedia", + [cpuinfo_arm_chipset_vendor_unisoc] = "Unisoc", + [cpuinfo_arm_chipset_vendor_wondermedia] = "WonderMedia", }; /* Map from ARM chipset series ID to its string representation */ static const char* chipset_series_string[cpuinfo_arm_chipset_series_max] = { - [cpuinfo_arm_chipset_series_unknown] = NULL, - [cpuinfo_arm_chipset_series_qualcomm_qsd] = "QSD", - [cpuinfo_arm_chipset_series_qualcomm_msm] = "MSM", - [cpuinfo_arm_chipset_series_qualcomm_apq] = "APQ", - [cpuinfo_arm_chipset_series_qualcomm_snapdragon] = "Snapdragon ", - [cpuinfo_arm_chipset_series_mediatek_mt] = "MT", - [cpuinfo_arm_chipset_series_samsung_exynos] = "Exynos ", - [cpuinfo_arm_chipset_series_hisilicon_k3v] = "K3V", - [cpuinfo_arm_chipset_series_hisilicon_hi] = "Hi", - [cpuinfo_arm_chipset_series_hisilicon_kirin] = "Kirin ", - [cpuinfo_arm_chipset_series_actions_atm] = "ATM", - [cpuinfo_arm_chipset_series_allwinner_a] = "A", - [cpuinfo_arm_chipset_series_amlogic_aml] = "AML", - [cpuinfo_arm_chipset_series_amlogic_s] = "S", - [cpuinfo_arm_chipset_series_broadcom_bcm] = "BCM", - [cpuinfo_arm_chipset_series_lg_nuclun] = "Nuclun ", - [cpuinfo_arm_chipset_series_leadcore_lc] = "LC", - [cpuinfo_arm_chipset_series_marvell_pxa] = "PXA", - [cpuinfo_arm_chipset_series_mstar_6a] = "6A", - [cpuinfo_arm_chipset_series_novathor_u] = "U", - [cpuinfo_arm_chipset_series_nvidia_tegra_t] = "Tegra T", - [cpuinfo_arm_chipset_series_nvidia_tegra_ap] = "Tegra AP", - [cpuinfo_arm_chipset_series_nvidia_tegra_sl] = "Tegra SL", - [cpuinfo_arm_chipset_series_pinecone_surge_s] = "Surge S", - [cpuinfo_arm_chipset_series_renesas_mp] = "MP", - [cpuinfo_arm_chipset_series_rockchip_rk] = "RK", - [cpuinfo_arm_chipset_series_spreadtrum_sc] = "SC", - [cpuinfo_arm_chipset_series_telechips_tcc] = "TCC", + [cpuinfo_arm_chipset_series_unknown] = NULL, + [cpuinfo_arm_chipset_series_qualcomm_qsd] = "QSD", + [cpuinfo_arm_chipset_series_qualcomm_msm] = "MSM", + [cpuinfo_arm_chipset_series_qualcomm_apq] = "APQ", + [cpuinfo_arm_chipset_series_qualcomm_snapdragon] = "Snapdragon ", + [cpuinfo_arm_chipset_series_mediatek_mt] = "MT", + [cpuinfo_arm_chipset_series_samsung_exynos] = "Exynos ", + [cpuinfo_arm_chipset_series_hisilicon_k3v] = "K3V", + [cpuinfo_arm_chipset_series_hisilicon_hi] = "Hi", + [cpuinfo_arm_chipset_series_hisilicon_kirin] = "Kirin ", + [cpuinfo_arm_chipset_series_actions_atm] = "ATM", + [cpuinfo_arm_chipset_series_allwinner_a] = "A", + [cpuinfo_arm_chipset_series_amlogic_aml] = "AML", + [cpuinfo_arm_chipset_series_amlogic_s] = "S", + [cpuinfo_arm_chipset_series_broadcom_bcm] = "BCM", + [cpuinfo_arm_chipset_series_lg_nuclun] = "Nuclun ", + [cpuinfo_arm_chipset_series_leadcore_lc] = "LC", + [cpuinfo_arm_chipset_series_marvell_pxa] = "PXA", + [cpuinfo_arm_chipset_series_mstar_6a] = "6A", + [cpuinfo_arm_chipset_series_novathor_u] = "U", + [cpuinfo_arm_chipset_series_nvidia_tegra_t] = "Tegra T", + [cpuinfo_arm_chipset_series_nvidia_tegra_ap] = "Tegra AP", + [cpuinfo_arm_chipset_series_nvidia_tegra_sl] = "Tegra SL", + [cpuinfo_arm_chipset_series_pinecone_surge_s] = "Surge S", + [cpuinfo_arm_chipset_series_renesas_mp] = "MP", + [cpuinfo_arm_chipset_series_rockchip_rk] = "RK", + [cpuinfo_arm_chipset_series_spreadtrum_sc] = "SC", + [cpuinfo_arm_chipset_series_telechips_tcc] = "TCC", [cpuinfo_arm_chipset_series_texas_instruments_omap] = "OMAP", - [cpuinfo_arm_chipset_series_unisoc_t] = "T", - [cpuinfo_arm_chipset_series_wondermedia_wm] = "WM", + [cpuinfo_arm_chipset_series_unisoc_t] = "T", + [cpuinfo_arm_chipset_series_wondermedia_wm] = "WM", }; -/* Convert chipset name represented by cpuinfo_arm_chipset structure to a string representation */ +/* Convert chipset name represented by cpuinfo_arm_chipset structure to a string + * representation */ void cpuinfo_arm_chipset_to_string( const struct cpuinfo_arm_chipset chipset[restrict static 1], - char name[restrict static CPUINFO_ARM_CHIPSET_NAME_MAX]) -{ + char name[restrict static CPUINFO_ARM_CHIPSET_NAME_MAX]) { enum cpuinfo_arm_chipset_vendor vendor = chipset->vendor; if (vendor >= cpuinfo_arm_chipset_vendor_max) { vendor = cpuinfo_arm_chipset_vendor_unknown; @@ -3532,387 +3749,411 @@ void cpuinfo_arm_chipset_to_string( if (series == cpuinfo_arm_chipset_series_unknown) { strncpy(name, vendor_string, CPUINFO_ARM_CHIPSET_NAME_MAX); } else { - snprintf(name, CPUINFO_ARM_CHIPSET_NAME_MAX, - "%s %s", vendor_string, series_string); + snprintf(name, CPUINFO_ARM_CHIPSET_NAME_MAX, "%s %s", vendor_string, series_string); } } else { const size_t suffix_length = strnlen(chipset->suffix, CPUINFO_ARM_CHIPSET_SUFFIX_MAX); - snprintf(name, CPUINFO_ARM_CHIPSET_NAME_MAX, - "%s %s%"PRIu32"%.*s", vendor_string, series_string, model, (int) suffix_length, chipset->suffix); + snprintf( + name, + CPUINFO_ARM_CHIPSET_NAME_MAX, + "%s %s%" PRIu32 "%.*s", + vendor_string, + series_string, + model, + (int)suffix_length, + chipset->suffix); } } #if defined(__ANDROID__) - static inline struct cpuinfo_arm_chipset disambiguate_qualcomm_chipset( - const struct cpuinfo_arm_chipset proc_cpuinfo_hardware_chipset[restrict static 1], - const struct cpuinfo_arm_chipset ro_product_board_chipset[restrict static 1], - const struct cpuinfo_arm_chipset ro_board_platform_chipset[restrict static 1], - const struct cpuinfo_arm_chipset ro_chipname_chipset[restrict static 1], - const struct cpuinfo_arm_chipset ro_hardware_chipname_chipset[restrict static 1]) - { - if (ro_hardware_chipname_chipset->series != cpuinfo_arm_chipset_series_unknown) { - return *ro_hardware_chipname_chipset; - } - if (ro_chipname_chipset->series != cpuinfo_arm_chipset_series_unknown) { - return *ro_chipname_chipset; - } - if (proc_cpuinfo_hardware_chipset->series != cpuinfo_arm_chipset_series_unknown) { - return *proc_cpuinfo_hardware_chipset; - } - if (ro_product_board_chipset->series != cpuinfo_arm_chipset_series_unknown) { - return *ro_product_board_chipset; - } - return *ro_board_platform_chipset; +static inline struct cpuinfo_arm_chipset disambiguate_qualcomm_chipset( + const struct cpuinfo_arm_chipset proc_cpuinfo_hardware_chipset[restrict static 1], + const struct cpuinfo_arm_chipset ro_product_board_chipset[restrict static 1], + const struct cpuinfo_arm_chipset ro_board_platform_chipset[restrict static 1], + const struct cpuinfo_arm_chipset ro_chipname_chipset[restrict static 1], + const struct cpuinfo_arm_chipset ro_hardware_chipname_chipset[restrict static 1]) { + if (ro_hardware_chipname_chipset->series != cpuinfo_arm_chipset_series_unknown) { + return *ro_hardware_chipname_chipset; } - - static inline struct cpuinfo_arm_chipset disambiguate_mediatek_chipset( - const struct cpuinfo_arm_chipset proc_cpuinfo_hardware_chipset[restrict static 1], - const struct cpuinfo_arm_chipset ro_product_board_chipset[restrict static 1], - const struct cpuinfo_arm_chipset ro_board_platform_chipset[restrict static 1], - const struct cpuinfo_arm_chipset ro_mediatek_platform_chipset[restrict static 1], - const struct cpuinfo_arm_chipset ro_chipname_chipset[restrict static 1]) - { - if (ro_chipname_chipset->series != cpuinfo_arm_chipset_series_unknown) { - return *ro_chipname_chipset; - } - if (proc_cpuinfo_hardware_chipset->series != cpuinfo_arm_chipset_series_unknown) { - return *proc_cpuinfo_hardware_chipset; - } - if (ro_product_board_chipset->series != cpuinfo_arm_chipset_series_unknown) { - return *ro_product_board_chipset; - } - if (ro_board_platform_chipset->series != cpuinfo_arm_chipset_series_unknown) { - return *ro_board_platform_chipset; - } - return *ro_mediatek_platform_chipset; + if (ro_chipname_chipset->series != cpuinfo_arm_chipset_series_unknown) { + return *ro_chipname_chipset; + } + if (proc_cpuinfo_hardware_chipset->series != cpuinfo_arm_chipset_series_unknown) { + return *proc_cpuinfo_hardware_chipset; } + if (ro_product_board_chipset->series != cpuinfo_arm_chipset_series_unknown) { + return *ro_product_board_chipset; + } + return *ro_board_platform_chipset; +} - static inline struct cpuinfo_arm_chipset disambiguate_hisilicon_chipset( - const struct cpuinfo_arm_chipset proc_cpuinfo_hardware_chipset[restrict static 1], - const struct cpuinfo_arm_chipset ro_product_board_chipset[restrict static 1], - const struct cpuinfo_arm_chipset ro_board_platform_chipset[restrict static 1]) - { - if (proc_cpuinfo_hardware_chipset->series != cpuinfo_arm_chipset_series_unknown) { - return *proc_cpuinfo_hardware_chipset; - } - if (ro_product_board_chipset->series != cpuinfo_arm_chipset_series_unknown) { - return *ro_product_board_chipset; - } +static inline struct cpuinfo_arm_chipset disambiguate_mediatek_chipset( + const struct cpuinfo_arm_chipset proc_cpuinfo_hardware_chipset[restrict static 1], + const struct cpuinfo_arm_chipset ro_product_board_chipset[restrict static 1], + const struct cpuinfo_arm_chipset ro_board_platform_chipset[restrict static 1], + const struct cpuinfo_arm_chipset ro_mediatek_platform_chipset[restrict static 1], + const struct cpuinfo_arm_chipset ro_chipname_chipset[restrict static 1]) { + if (ro_chipname_chipset->series != cpuinfo_arm_chipset_series_unknown) { + return *ro_chipname_chipset; + } + if (proc_cpuinfo_hardware_chipset->series != cpuinfo_arm_chipset_series_unknown) { + return *proc_cpuinfo_hardware_chipset; + } + if (ro_product_board_chipset->series != cpuinfo_arm_chipset_series_unknown) { + return *ro_product_board_chipset; + } + if (ro_board_platform_chipset->series != cpuinfo_arm_chipset_series_unknown) { return *ro_board_platform_chipset; } + return *ro_mediatek_platform_chipset; +} - static inline struct cpuinfo_arm_chipset disambiguate_amlogic_chipset( - const struct cpuinfo_arm_chipset proc_cpuinfo_hardware_chipset[restrict static 1], - const struct cpuinfo_arm_chipset ro_board_platform_chipset[restrict static 1]) - { - if (proc_cpuinfo_hardware_chipset->series != cpuinfo_arm_chipset_series_unknown) { - return *proc_cpuinfo_hardware_chipset; - } - return *ro_board_platform_chipset; +static inline struct cpuinfo_arm_chipset disambiguate_hisilicon_chipset( + const struct cpuinfo_arm_chipset proc_cpuinfo_hardware_chipset[restrict static 1], + const struct cpuinfo_arm_chipset ro_product_board_chipset[restrict static 1], + const struct cpuinfo_arm_chipset ro_board_platform_chipset[restrict static 1]) { + if (proc_cpuinfo_hardware_chipset->series != cpuinfo_arm_chipset_series_unknown) { + return *proc_cpuinfo_hardware_chipset; + } + if (ro_product_board_chipset->series != cpuinfo_arm_chipset_series_unknown) { + return *ro_product_board_chipset; } + return *ro_board_platform_chipset; +} - static inline struct cpuinfo_arm_chipset disambiguate_marvell_chipset( - const struct cpuinfo_arm_chipset proc_cpuinfo_hardware_chipset[restrict static 1], - const struct cpuinfo_arm_chipset ro_product_board_chipset[restrict static 1], - const struct cpuinfo_arm_chipset ro_chipname_chipset[restrict static 1]) - { - if (ro_chipname_chipset->series != cpuinfo_arm_chipset_series_unknown) { - return *ro_chipname_chipset; - } - if (ro_product_board_chipset->series != cpuinfo_arm_chipset_series_unknown) { - return *ro_product_board_chipset; - } +static inline struct cpuinfo_arm_chipset disambiguate_amlogic_chipset( + const struct cpuinfo_arm_chipset proc_cpuinfo_hardware_chipset[restrict static 1], + const struct cpuinfo_arm_chipset ro_board_platform_chipset[restrict static 1]) { + if (proc_cpuinfo_hardware_chipset->series != cpuinfo_arm_chipset_series_unknown) { return *proc_cpuinfo_hardware_chipset; } + return *ro_board_platform_chipset; +} - static inline struct cpuinfo_arm_chipset disambiguate_rockchip_chipset( - const struct cpuinfo_arm_chipset proc_cpuinfo_hardware_chipset[restrict static 1], - const struct cpuinfo_arm_chipset ro_product_board_chipset[restrict static 1], - const struct cpuinfo_arm_chipset ro_board_platform_chipset[restrict static 1]) - { - if (ro_product_board_chipset->series != cpuinfo_arm_chipset_series_unknown) { - return *ro_product_board_chipset; - } - if (proc_cpuinfo_hardware_chipset->series != cpuinfo_arm_chipset_series_unknown) { - return *proc_cpuinfo_hardware_chipset; - } - return *ro_board_platform_chipset; +static inline struct cpuinfo_arm_chipset disambiguate_marvell_chipset( + const struct cpuinfo_arm_chipset proc_cpuinfo_hardware_chipset[restrict static 1], + const struct cpuinfo_arm_chipset ro_product_board_chipset[restrict static 1], + const struct cpuinfo_arm_chipset ro_chipname_chipset[restrict static 1]) { + if (ro_chipname_chipset->series != cpuinfo_arm_chipset_series_unknown) { + return *ro_chipname_chipset; } + if (ro_product_board_chipset->series != cpuinfo_arm_chipset_series_unknown) { + return *ro_product_board_chipset; + } + return *proc_cpuinfo_hardware_chipset; +} - static inline struct cpuinfo_arm_chipset disambiguate_spreadtrum_chipset( - const struct cpuinfo_arm_chipset proc_cpuinfo_hardware_chipset[restrict static 1], - const struct cpuinfo_arm_chipset ro_product_board_chipset[restrict static 1], - const struct cpuinfo_arm_chipset ro_board_platform_chipset[restrict static 1], - const struct cpuinfo_arm_chipset ro_chipname_chipset[restrict static 1]) - { - if (ro_chipname_chipset->series != cpuinfo_arm_chipset_series_unknown) { - return *ro_chipname_chipset; - } - if (ro_product_board_chipset->series != cpuinfo_arm_chipset_series_unknown) { - return *ro_product_board_chipset; - } - if (proc_cpuinfo_hardware_chipset->series != cpuinfo_arm_chipset_series_unknown) { - return *proc_cpuinfo_hardware_chipset; - } - return *ro_board_platform_chipset; +static inline struct cpuinfo_arm_chipset disambiguate_rockchip_chipset( + const struct cpuinfo_arm_chipset proc_cpuinfo_hardware_chipset[restrict static 1], + const struct cpuinfo_arm_chipset ro_product_board_chipset[restrict static 1], + const struct cpuinfo_arm_chipset ro_board_platform_chipset[restrict static 1]) { + if (ro_product_board_chipset->series != cpuinfo_arm_chipset_series_unknown) { + return *ro_product_board_chipset; + } + if (proc_cpuinfo_hardware_chipset->series != cpuinfo_arm_chipset_series_unknown) { + return *proc_cpuinfo_hardware_chipset; } + return *ro_board_platform_chipset; +} - /* - * Decodes chipset name from Android system properties: - * - /proc/cpuinfo Hardware string - * - ro.product.board - * - ro.board.platform - * - ro.mediatek.platform - * - ro.chipname - * For some chipsets, the function relies frequency and on number of cores for chipset detection. - * - * @param[in] properties - structure with the Android system properties described above. - * @param cores - number of cores in the chipset. - * @param max_cpu_freq_max - maximum of /sys/devices/system/cpu/cpu/cpofreq/cpu_freq_max values. - * - * @returns Decoded chipset name. If chipset could not be decoded, the resulting structure would use `unknown` vendor - * and series identifiers. - */ - struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset( - const struct cpuinfo_android_properties properties[restrict static 1], - uint32_t cores, - uint32_t max_cpu_freq_max) - { - struct cpuinfo_arm_chipset chipset = { - .vendor = cpuinfo_arm_chipset_vendor_unknown, - .series = cpuinfo_arm_chipset_series_unknown, - }; +static inline struct cpuinfo_arm_chipset disambiguate_spreadtrum_chipset( + const struct cpuinfo_arm_chipset proc_cpuinfo_hardware_chipset[restrict static 1], + const struct cpuinfo_arm_chipset ro_product_board_chipset[restrict static 1], + const struct cpuinfo_arm_chipset ro_board_platform_chipset[restrict static 1], + const struct cpuinfo_arm_chipset ro_chipname_chipset[restrict static 1]) { + if (ro_chipname_chipset->series != cpuinfo_arm_chipset_series_unknown) { + return *ro_chipname_chipset; + } + if (ro_product_board_chipset->series != cpuinfo_arm_chipset_series_unknown) { + return *ro_product_board_chipset; + } + if (proc_cpuinfo_hardware_chipset->series != cpuinfo_arm_chipset_series_unknown) { + return *proc_cpuinfo_hardware_chipset; + } + return *ro_board_platform_chipset; +} - const bool tegra_platform = is_tegra( - properties->ro_board_platform, - properties->ro_board_platform + strnlen(properties->ro_board_platform, CPUINFO_BUILD_PROP_VALUE_MAX)); - - struct cpuinfo_arm_chipset chipsets[cpuinfo_android_chipset_property_max] = { - [cpuinfo_android_chipset_property_proc_cpuinfo_hardware] = - cpuinfo_arm_linux_decode_chipset_from_proc_cpuinfo_hardware( - properties->proc_cpuinfo_hardware, cores, max_cpu_freq_max, tegra_platform), - [cpuinfo_android_chipset_property_ro_product_board] = - cpuinfo_arm_android_decode_chipset_from_ro_product_board( - properties->ro_product_board, cores, max_cpu_freq_max), - [cpuinfo_android_chipset_property_ro_board_platform] = - cpuinfo_arm_android_decode_chipset_from_ro_board_platform( - properties->ro_board_platform, cores, max_cpu_freq_max), - [cpuinfo_android_chipset_property_ro_mediatek_platform] = - cpuinfo_arm_android_decode_chipset_from_ro_mediatek_platform(properties->ro_mediatek_platform), - [cpuinfo_android_chipset_property_ro_arch] = - cpuinfo_arm_android_decode_chipset_from_ro_arch(properties->ro_arch), - [cpuinfo_android_chipset_property_ro_chipname] = - cpuinfo_arm_android_decode_chipset_from_ro_chipname(properties->ro_chipname), - [cpuinfo_android_chipset_property_ro_hardware_chipname] = - cpuinfo_arm_android_decode_chipset_from_ro_chipname(properties->ro_hardware_chipname), - }; - enum cpuinfo_arm_chipset_vendor vendor = cpuinfo_arm_chipset_vendor_unknown; - for (size_t i = 0; i < cpuinfo_android_chipset_property_max; i++) { - const enum cpuinfo_arm_chipset_vendor decoded_vendor = chipsets[i].vendor; - if (decoded_vendor != cpuinfo_arm_chipset_vendor_unknown) { - if (vendor == cpuinfo_arm_chipset_vendor_unknown) { - vendor = decoded_vendor; - } else if (vendor != decoded_vendor) { - /* Parsing different system properties produces different chipset vendors. This situation is rare. */ - cpuinfo_log_error( - "chipset detection failed: different chipset vendors reported in different system properties"); - goto finish; - } +/* + * Decodes chipset name from Android system properties: + * - /proc/cpuinfo Hardware string + * - ro.product.board + * - ro.board.platform + * - ro.mediatek.platform + * - ro.chipname + * For some chipsets, the function relies frequency and on number of cores for + * chipset detection. + * + * @param[in] properties - structure with the Android system properties + * described above. + * @param cores - number of cores in the chipset. + * @param max_cpu_freq_max - maximum of + * /sys/devices/system/cpu/cpu/cpofreq/cpu_freq_max values. + * + * @returns Decoded chipset name. If chipset could not be decoded, the resulting + * structure would use `unknown` vendor and series identifiers. + */ +struct cpuinfo_arm_chipset cpuinfo_arm_android_decode_chipset( + const struct cpuinfo_android_properties properties[restrict static 1], + uint32_t cores, + uint32_t max_cpu_freq_max) { + struct cpuinfo_arm_chipset chipset = { + .vendor = cpuinfo_arm_chipset_vendor_unknown, + .series = cpuinfo_arm_chipset_series_unknown, + }; + + const bool tegra_platform = is_tegra( + properties->ro_board_platform, + properties->ro_board_platform + strnlen(properties->ro_board_platform, CPUINFO_BUILD_PROP_VALUE_MAX)); + + struct cpuinfo_arm_chipset chipsets[cpuinfo_android_chipset_property_max] = { + [cpuinfo_android_chipset_property_proc_cpuinfo_hardware] = + cpuinfo_arm_linux_decode_chipset_from_proc_cpuinfo_hardware( + properties->proc_cpuinfo_hardware, cores, max_cpu_freq_max, tegra_platform), + [cpuinfo_android_chipset_property_ro_product_board] = + cpuinfo_arm_android_decode_chipset_from_ro_product_board( + properties->ro_product_board, cores, max_cpu_freq_max), + [cpuinfo_android_chipset_property_ro_board_platform] = + cpuinfo_arm_android_decode_chipset_from_ro_board_platform( + properties->ro_board_platform, cores, max_cpu_freq_max), + [cpuinfo_android_chipset_property_ro_mediatek_platform] = + cpuinfo_arm_android_decode_chipset_from_ro_mediatek_platform(properties->ro_mediatek_platform), + [cpuinfo_android_chipset_property_ro_arch] = + cpuinfo_arm_android_decode_chipset_from_ro_arch(properties->ro_arch), + [cpuinfo_android_chipset_property_ro_chipname] = + cpuinfo_arm_android_decode_chipset_from_ro_chipname(properties->ro_chipname), + [cpuinfo_android_chipset_property_ro_hardware_chipname] = + cpuinfo_arm_android_decode_chipset_from_ro_chipname(properties->ro_hardware_chipname), + }; + enum cpuinfo_arm_chipset_vendor vendor = cpuinfo_arm_chipset_vendor_unknown; + for (size_t i = 0; i < cpuinfo_android_chipset_property_max; i++) { + const enum cpuinfo_arm_chipset_vendor decoded_vendor = chipsets[i].vendor; + if (decoded_vendor != cpuinfo_arm_chipset_vendor_unknown) { + if (vendor == cpuinfo_arm_chipset_vendor_unknown) { + vendor = decoded_vendor; + } else if (vendor != decoded_vendor) { + /* Parsing different system properties produces + * different chipset vendors. This situation is + * rare. */ + cpuinfo_log_error( + "chipset detection failed: different chipset vendors reported in different system properties"); + goto finish; } } - if (vendor == cpuinfo_arm_chipset_vendor_unknown) { - cpuinfo_log_warning( - "chipset detection failed: none of the system properties matched known signatures"); - goto finish; - } + } + if (vendor == cpuinfo_arm_chipset_vendor_unknown) { + cpuinfo_log_warning("chipset detection failed: none of the system properties matched known signatures"); + goto finish; + } - /* Fix common bugs in reported chipsets */ - for (size_t i = 0; i < cpuinfo_android_chipset_property_max; i++) { - cpuinfo_arm_fixup_chipset(&chipsets[i], cores, max_cpu_freq_max); - } + /* Fix common bugs in reported chipsets */ + for (size_t i = 0; i < cpuinfo_android_chipset_property_max; i++) { + cpuinfo_arm_fixup_chipset(&chipsets[i], cores, max_cpu_freq_max); + } - /* - * Propagate suffixes: consider all pairs of chipsets, if both chipsets in the pair are from the same series, - * and one's suffix is a prefix of another's chipset suffix, use the longest suffix. - */ - for (size_t i = 0; i < cpuinfo_android_chipset_property_max; i++) { - const size_t chipset_i_suffix_length = strnlen(chipsets[i].suffix, CPUINFO_ARM_CHIPSET_SUFFIX_MAX); - for (size_t j = 0; j < i; j++) { - if (chipsets[i].series == chipsets[j].series) { - const size_t chipset_j_suffix_length = strnlen(chipsets[j].suffix, CPUINFO_ARM_CHIPSET_SUFFIX_MAX); - if (chipset_i_suffix_length != chipset_j_suffix_length) { - const size_t common_prefix_length = (chipset_i_suffix_length < chipset_j_suffix_length) ? - chipset_i_suffix_length : chipset_j_suffix_length; - if (common_prefix_length == 0 || - memcmp(chipsets[i].suffix, chipsets[j].suffix, common_prefix_length) == 0) - { - if (chipset_i_suffix_length > chipset_j_suffix_length) { - memcpy(chipsets[j].suffix, chipsets[i].suffix, chipset_i_suffix_length); - } else { - memcpy(chipsets[i].suffix, chipsets[j].suffix, chipset_j_suffix_length); - } + /* + * Propagate suffixes: consider all pairs of chipsets, if both chipsets + * in the pair are from the same series, and one's suffix is a prefix of + * another's chipset suffix, use the longest suffix. + */ + for (size_t i = 0; i < cpuinfo_android_chipset_property_max; i++) { + const size_t chipset_i_suffix_length = strnlen(chipsets[i].suffix, CPUINFO_ARM_CHIPSET_SUFFIX_MAX); + for (size_t j = 0; j < i; j++) { + if (chipsets[i].series == chipsets[j].series) { + const size_t chipset_j_suffix_length = + strnlen(chipsets[j].suffix, CPUINFO_ARM_CHIPSET_SUFFIX_MAX); + if (chipset_i_suffix_length != chipset_j_suffix_length) { + const size_t common_prefix_length = + (chipset_i_suffix_length < chipset_j_suffix_length) + ? chipset_i_suffix_length + : chipset_j_suffix_length; + if (common_prefix_length == 0 || + memcmp(chipsets[i].suffix, chipsets[j].suffix, common_prefix_length) == 0) { + if (chipset_i_suffix_length > chipset_j_suffix_length) { + memcpy(chipsets[j].suffix, + chipsets[i].suffix, + chipset_i_suffix_length); + } else { + memcpy(chipsets[i].suffix, + chipsets[j].suffix, + chipset_j_suffix_length); } } } } } + } - for (size_t i = 0; i < cpuinfo_android_chipset_property_max; i++) { - if (chipsets[i].series != cpuinfo_arm_chipset_series_unknown) { - if (chipset.series == cpuinfo_arm_chipset_series_unknown) { - chipset = chipsets[i]; - } else if (chipsets[i].series != chipset.series || chipsets[i].model != chipset.model || - strncmp(chipsets[i].suffix, chipset.suffix, CPUINFO_ARM_CHIPSET_SUFFIX_MAX) != 0) - { - cpuinfo_log_info( - "different chipsets reported in different system properties; " - "vendor-specific disambiguation heuristic would be used"); - switch (vendor) { - case cpuinfo_arm_chipset_vendor_qualcomm: - return disambiguate_qualcomm_chipset( - &chipsets[cpuinfo_android_chipset_property_proc_cpuinfo_hardware], - &chipsets[cpuinfo_android_chipset_property_ro_product_board], - &chipsets[cpuinfo_android_chipset_property_ro_board_platform], - &chipsets[cpuinfo_android_chipset_property_ro_chipname], - &chipsets[cpuinfo_android_chipset_property_ro_hardware_chipname]); - case cpuinfo_arm_chipset_vendor_mediatek: - return disambiguate_mediatek_chipset( - &chipsets[cpuinfo_android_chipset_property_proc_cpuinfo_hardware], - &chipsets[cpuinfo_android_chipset_property_ro_product_board], - &chipsets[cpuinfo_android_chipset_property_ro_board_platform], - &chipsets[cpuinfo_android_chipset_property_ro_mediatek_platform], - &chipsets[cpuinfo_android_chipset_property_ro_chipname]); - case cpuinfo_arm_chipset_vendor_hisilicon: - return disambiguate_hisilicon_chipset( - &chipsets[cpuinfo_android_chipset_property_proc_cpuinfo_hardware], - &chipsets[cpuinfo_android_chipset_property_ro_product_board], - &chipsets[cpuinfo_android_chipset_property_ro_board_platform]); - case cpuinfo_arm_chipset_vendor_amlogic: - return disambiguate_amlogic_chipset( - &chipsets[cpuinfo_android_chipset_property_proc_cpuinfo_hardware], - &chipsets[cpuinfo_android_chipset_property_ro_board_platform]); - case cpuinfo_arm_chipset_vendor_marvell: - return disambiguate_marvell_chipset( - &chipsets[cpuinfo_android_chipset_property_proc_cpuinfo_hardware], - &chipsets[cpuinfo_android_chipset_property_ro_product_board], - &chipsets[cpuinfo_android_chipset_property_ro_chipname]); - case cpuinfo_arm_chipset_vendor_rockchip: - return disambiguate_rockchip_chipset( - &chipsets[cpuinfo_android_chipset_property_proc_cpuinfo_hardware], - &chipsets[cpuinfo_android_chipset_property_ro_product_board], - &chipsets[cpuinfo_android_chipset_property_ro_board_platform]); - case cpuinfo_arm_chipset_vendor_spreadtrum: - return disambiguate_spreadtrum_chipset( - &chipsets[cpuinfo_android_chipset_property_proc_cpuinfo_hardware], - &chipsets[cpuinfo_android_chipset_property_ro_product_board], - &chipsets[cpuinfo_android_chipset_property_ro_board_platform], - &chipsets[cpuinfo_android_chipset_property_ro_chipname]); - default: - cpuinfo_log_error( - "chipset detection failed: " - "could not disambiguate different chipsets reported in different system properties"); - /* chipset variable contains valid, but inconsistent chipset information, overwrite it */ - chipset = (struct cpuinfo_arm_chipset) { - .vendor = cpuinfo_arm_chipset_vendor_unknown, - .series = cpuinfo_arm_chipset_series_unknown, - }; - goto finish; - } + for (size_t i = 0; i < cpuinfo_android_chipset_property_max; i++) { + if (chipsets[i].series != cpuinfo_arm_chipset_series_unknown) { + if (chipset.series == cpuinfo_arm_chipset_series_unknown) { + chipset = chipsets[i]; + } else if ( + chipsets[i].series != chipset.series || chipsets[i].model != chipset.model || + strncmp(chipsets[i].suffix, chipset.suffix, CPUINFO_ARM_CHIPSET_SUFFIX_MAX) != 0) { + cpuinfo_log_info( + "different chipsets reported in different system properties; " + "vendor-specific disambiguation heuristic would be used"); + switch (vendor) { + case cpuinfo_arm_chipset_vendor_qualcomm: + return disambiguate_qualcomm_chipset( + &chipsets + [cpuinfo_android_chipset_property_proc_cpuinfo_hardware], + &chipsets[cpuinfo_android_chipset_property_ro_product_board], + &chipsets[cpuinfo_android_chipset_property_ro_board_platform], + &chipsets[cpuinfo_android_chipset_property_ro_chipname], + &chipsets + [cpuinfo_android_chipset_property_ro_hardware_chipname]); + case cpuinfo_arm_chipset_vendor_mediatek: + return disambiguate_mediatek_chipset( + &chipsets + [cpuinfo_android_chipset_property_proc_cpuinfo_hardware], + &chipsets[cpuinfo_android_chipset_property_ro_product_board], + &chipsets[cpuinfo_android_chipset_property_ro_board_platform], + &chipsets + [cpuinfo_android_chipset_property_ro_mediatek_platform], + &chipsets[cpuinfo_android_chipset_property_ro_chipname]); + case cpuinfo_arm_chipset_vendor_hisilicon: + return disambiguate_hisilicon_chipset( + &chipsets + [cpuinfo_android_chipset_property_proc_cpuinfo_hardware], + &chipsets[cpuinfo_android_chipset_property_ro_product_board], + &chipsets[cpuinfo_android_chipset_property_ro_board_platform]); + case cpuinfo_arm_chipset_vendor_amlogic: + return disambiguate_amlogic_chipset( + &chipsets + [cpuinfo_android_chipset_property_proc_cpuinfo_hardware], + &chipsets[cpuinfo_android_chipset_property_ro_board_platform]); + case cpuinfo_arm_chipset_vendor_marvell: + return disambiguate_marvell_chipset( + &chipsets + [cpuinfo_android_chipset_property_proc_cpuinfo_hardware], + &chipsets[cpuinfo_android_chipset_property_ro_product_board], + &chipsets[cpuinfo_android_chipset_property_ro_chipname]); + case cpuinfo_arm_chipset_vendor_rockchip: + return disambiguate_rockchip_chipset( + &chipsets + [cpuinfo_android_chipset_property_proc_cpuinfo_hardware], + &chipsets[cpuinfo_android_chipset_property_ro_product_board], + &chipsets[cpuinfo_android_chipset_property_ro_board_platform]); + case cpuinfo_arm_chipset_vendor_spreadtrum: + return disambiguate_spreadtrum_chipset( + &chipsets + [cpuinfo_android_chipset_property_proc_cpuinfo_hardware], + &chipsets[cpuinfo_android_chipset_property_ro_product_board], + &chipsets[cpuinfo_android_chipset_property_ro_board_platform], + &chipsets[cpuinfo_android_chipset_property_ro_chipname]); + default: + cpuinfo_log_error( + "chipset detection failed: " + "could not disambiguate different chipsets reported in different system properties"); + /* chipset variable contains + * valid, but inconsistent + * chipset information, + * overwrite it */ + chipset = (struct cpuinfo_arm_chipset){ + .vendor = cpuinfo_arm_chipset_vendor_unknown, + .series = cpuinfo_arm_chipset_series_unknown, + }; + goto finish; } } } - - finish: - return chipset; } -#else /* !defined(__ANDROID__) */ - /* - * Fix commonly misreported Broadcom BCM models on Raspberry Pi boards. - * - * @param[in,out] chipset - chipset name to fix. - * @param[in] revision - /proc/cpuinfo Revision string. - */ - void cpuinfo_arm_fixup_raspberry_pi_chipset( - struct cpuinfo_arm_chipset chipset[restrict static 1], - const char revision[restrict static CPUINFO_REVISION_VALUE_MAX]) - { - const size_t revision_length = strnlen(revision, CPUINFO_REVISION_VALUE_MAX); - /* Parse revision codes according to https://www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/README.md */ - #if CPUINFO_ARCH_ARM - if (revision_length == 4) { - /* - * Old-style revision codes. - * All Raspberry Pi models with old-style revision code use Broadcom BCM2835. - */ +finish: + return chipset; +} +#else /* !defined(__ANDROID__) */ +/* + * Fix commonly misreported Broadcom BCM models on Raspberry Pi boards. + * + * @param[in,out] chipset - chipset name to fix. + * @param[in] revision - /proc/cpuinfo Revision string. + */ +void cpuinfo_arm_fixup_raspberry_pi_chipset( + struct cpuinfo_arm_chipset chipset[restrict static 1], + const char revision[restrict static CPUINFO_REVISION_VALUE_MAX]) { + const size_t revision_length = strnlen(revision, CPUINFO_REVISION_VALUE_MAX); - /* BCM2835 often misreported as BCM2708 */ - if (chipset->model == 2708) { - chipset->model = 2835; - } - return; - } - #endif - if ((size_t) (revision_length - 5) <= (size_t) (8 - 5) /* 5 <= length(revision) <= 8 */) { - /* New-style revision codes */ - - uint32_t model = 0; - switch (revision[revision_length - 4]) { - case '0': - /* BCM2835 */ - model = 2835; - break; - case '1': - /* BCM2836 */ - model = 2836; - break; - case '2': - /* BCM2837 */ - model = 2837; - break; - case '3': - /* BCM2711 */ - model = 2711; - break; - } +/* Parse revision codes according to + * https://www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/README.md + */ +#if CPUINFO_ARCH_ARM + if (revision_length == 4) { + /* + * Old-style revision codes. + * All Raspberry Pi models with old-style revision code use + * Broadcom BCM2835. + */ - if (model != 0) { - chipset->model = model; - chipset->suffix[0] = 0; - } + /* BCM2835 often misreported as BCM2708 */ + if (chipset->model == 2708) { + chipset->model = 2835; } + return; } +#endif + if ((size_t)(revision_length - 5) <= (size_t)(8 - 5) /* 5 <= length(revision) <= 8 */) { + /* New-style revision codes */ + + uint32_t model = 0; + switch (revision[revision_length - 4]) { + case '0': + /* BCM2835 */ + model = 2835; + break; + case '1': + /* BCM2836 */ + model = 2836; + break; + case '2': + /* BCM2837 */ + model = 2837; + break; + case '3': + /* BCM2711 */ + model = 2711; + break; + } - /* - * Decodes chipset name from /proc/cpuinfo Hardware string. - * For some chipsets, the function relies frequency and on number of cores for chipset detection. - * - * @param[in] hardware - /proc/cpuinfo Hardware string. - * @param cores - number of cores in the chipset. - * @param max_cpu_freq_max - maximum of /sys/devices/system/cpu/cpu/cpofreq/cpu_freq_max values. - * - * @returns Decoded chipset name. If chipset could not be decoded, the resulting structure would use `unknown` vendor - * and series identifiers. - */ - struct cpuinfo_arm_chipset cpuinfo_arm_linux_decode_chipset( - const char hardware[restrict static CPUINFO_HARDWARE_VALUE_MAX], - const char revision[restrict static CPUINFO_REVISION_VALUE_MAX], - uint32_t cores, - uint32_t max_cpu_freq_max) - { - struct cpuinfo_arm_chipset chipset = - cpuinfo_arm_linux_decode_chipset_from_proc_cpuinfo_hardware( - hardware, cores, max_cpu_freq_max, false); - if (chipset.vendor == cpuinfo_arm_chipset_vendor_unknown) { - cpuinfo_log_warning( - "chipset detection failed: /proc/cpuinfo Hardware string did not match known signatures"); - } else if (chipset.vendor == cpuinfo_arm_chipset_vendor_broadcom) { - /* Raspberry Pi kernel reports bogus chipset models; detect chipset from RPi revision */ - cpuinfo_arm_fixup_raspberry_pi_chipset(&chipset, revision); - } else { - cpuinfo_arm_fixup_chipset(&chipset, cores, max_cpu_freq_max); + if (model != 0) { + chipset->model = model; + chipset->suffix[0] = 0; } - return chipset; } +} + +/* + * Decodes chipset name from /proc/cpuinfo Hardware string. + * For some chipsets, the function relies frequency and on number of cores for + * chipset detection. + * + * @param[in] hardware - /proc/cpuinfo Hardware string. + * @param cores - number of cores in the chipset. + * @param max_cpu_freq_max - maximum of + * /sys/devices/system/cpu/cpu/cpofreq/cpu_freq_max values. + * + * @returns Decoded chipset name. If chipset could not be decoded, the resulting + * structure would use `unknown` vendor and series identifiers. + */ +struct cpuinfo_arm_chipset cpuinfo_arm_linux_decode_chipset( + const char hardware[restrict static CPUINFO_HARDWARE_VALUE_MAX], + const char revision[restrict static CPUINFO_REVISION_VALUE_MAX], + uint32_t cores, + uint32_t max_cpu_freq_max) { + struct cpuinfo_arm_chipset chipset = + cpuinfo_arm_linux_decode_chipset_from_proc_cpuinfo_hardware(hardware, cores, max_cpu_freq_max, false); + if (chipset.vendor == cpuinfo_arm_chipset_vendor_unknown) { + cpuinfo_log_warning( + "chipset detection failed: /proc/cpuinfo Hardware string did not match known signatures"); + } else if (chipset.vendor == cpuinfo_arm_chipset_vendor_broadcom) { + /* Raspberry Pi kernel reports bogus chipset models; detect + * chipset from RPi revision */ + cpuinfo_arm_fixup_raspberry_pi_chipset(&chipset, revision); + } else { + cpuinfo_arm_fixup_chipset(&chipset, cores, max_cpu_freq_max); + } + return chipset; +} #endif diff --git a/src/arm/linux/clusters.c b/src/arm/linux/clusters.c index 430773d1..8dd452a7 100644 --- a/src/arm/linux/clusters.c +++ b/src/arm/linux/clusters.c @@ -1,63 +1,74 @@ -#include #include +#include #include #include -#include #include +#include #if defined(__ANDROID__) - #include +#include #endif #include #include -#include #include #include +#include static inline bool bitmask_all(uint32_t bitfield, uint32_t mask) { return (bitfield & mask) == mask; } /* - * Assigns logical processors to clusters of cores using heuristic based on the typical configuration of clusters for - * 5, 6, 8, and 10 cores: + * Assigns logical processors to clusters of cores using heuristic based on the + * typical configuration of clusters for 5, 6, 8, and 10 cores: * - 5 cores (ARM32 Android only): 2 clusters of 4+1 cores * - 6 cores: 2 clusters of 4+2 cores * - 8 cores: 2 clusters of 4+4 cores * - 10 cores: 3 clusters of 4+4+2 cores * - * The function must be called after parsing OS-provided information on core clusters. - * Its purpose is to detect clusters of cores when OS-provided information is lacking or incomplete, i.e. - * - Linux kernel is not configured to report information in sysfs topology leaf. - * - Linux kernel reports topology information only for online cores, and only cores on one cluster are online, e.g.: - * - Exynos 8890 has 8 cores in 4+4 clusters, but only the first cluster of 4 cores is reported, and cluster - * configuration of logical processors 4-7 is not reported (all remaining processors 4-7 form cluster 1) - * - MT6797 has 10 cores in 4+4+2, but only the first cluster of 4 cores is reported, and cluster configuration - * of logical processors 4-9 is not reported (processors 4-7 form cluster 1, and processors 8-9 form cluster 2). + * The function must be called after parsing OS-provided information on core + * clusters. Its purpose is to detect clusters of cores when OS-provided + * information is lacking or incomplete, i.e. + * - Linux kernel is not configured to report information in sysfs topology + * leaf. + * - Linux kernel reports topology information only for online cores, and only + * cores on one cluster are online, e.g.: + * - Exynos 8890 has 8 cores in 4+4 clusters, but only the first cluster of 4 + * cores is reported, and cluster configuration of logical processors 4-7 is not + * reported (all remaining processors 4-7 form cluster 1) + * - MT6797 has 10 cores in 4+4+2, but only the first cluster of 4 cores is + * reported, and cluster configuration of logical processors 4-9 is not reported + * (processors 4-7 form cluster 1, and processors 8-9 form cluster 2). * - * Heuristic assignment of processors to the above pre-defined clusters fails if such assignment would contradict - * information provided by the operating system: - * - Any of the OS-reported processor clusters is different than the corresponding heuristic cluster. - * - Processors in a heuristic cluster have no OS-provided cluster siblings information, but have known and different - * minimum/maximum frequency. - * - Processors in a heuristic cluster have no OS-provided cluster siblings information, but have known and different - * MIDR components. + * Heuristic assignment of processors to the above pre-defined clusters fails if + * such assignment would contradict information provided by the operating + * system: + * - Any of the OS-reported processor clusters is different than the + * corresponding heuristic cluster. + * - Processors in a heuristic cluster have no OS-provided cluster siblings + * information, but have known and different minimum/maximum frequency. + * - Processors in a heuristic cluster have no OS-provided cluster siblings + * information, but have known and different MIDR components. * - * If the heuristic assignment of processors to clusters of cores fails, all processors' clusters are unchanged. + * If the heuristic assignment of processors to clusters of cores fails, all + * processors' clusters are unchanged. * - * @param usable_processors - number of processors in the @p processors array with CPUINFO_LINUX_FLAG_VALID flags. + * @param usable_processors - number of processors in the @p processors array + * with CPUINFO_LINUX_FLAG_VALID flags. * @param max_processors - number of elements in the @p processors array. - * @param[in,out] processors - processor descriptors with pre-parsed POSSIBLE and PRESENT flags, minimum/maximum - * frequency, MIDR information, and core cluster (package siblings list) information. + * @param[in,out] processors - processor descriptors with pre-parsed POSSIBLE + * and PRESENT flags, minimum/maximum frequency, MIDR information, and core + * cluster (package siblings list) information. * - * @retval true if the heuristic successfully assigned all processors into clusters of cores. - * @retval false if known details about processors contradict the heuristic configuration of core clusters. + * @retval true if the heuristic successfully assigned all processors into + * clusters of cores. + * @retval false if known details about processors contradict the heuristic + * configuration of core clusters. */ bool cpuinfo_arm_linux_detect_core_clusters_by_heuristic( uint32_t usable_processors, uint32_t max_processors, - struct cpuinfo_arm_linux_processor processors[restrict static max_processors]) -{ + struct cpuinfo_arm_linux_processor processors[restrict static max_processors]) { uint32_t cluster_processors[3]; switch (usable_processors) { case 10: @@ -76,8 +87,9 @@ bool cpuinfo_arm_linux_detect_core_clusters_by_heuristic( #if defined(__ANDROID__) && CPUINFO_ARCH_ARM case 5: /* - * The only processor with 5 cores is Leadcore L1860C (ARMv7, mobile), - * but this configuration is not too unreasonable for a virtualized ARM server. + * The only processor with 5 cores is Leadcore L1860C + * (ARMv7, mobile), but this configuration is not too + * unreasonable for a virtualized ARM server. */ cluster_processors[0] = 4; cluster_processors[1] = 1; @@ -89,7 +101,8 @@ bool cpuinfo_arm_linux_detect_core_clusters_by_heuristic( /* * Assignment of processors to core clusters is done in two passes: - * 1. Verify that the clusters proposed by heuristic are compatible with known details about processors. + * 1. Verify that the clusters proposed by heuristic are compatible with + * known details about processors. * 2. If verification passed, update core clusters for the processors. */ @@ -100,16 +113,22 @@ bool cpuinfo_arm_linux_detect_core_clusters_by_heuristic( for (uint32_t i = 0; i < max_processors; i++) { if (bitmask_all(processors[i].flags, CPUINFO_LINUX_FLAG_VALID)) { if (expected_cluster_processors == 0) { - /* Expect this processor to start a new cluster */ + /* Expect this processor to start a new cluster + */ expected_cluster_exists = !!(processors[i].flags & CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER); if (expected_cluster_exists) { if (processors[i].package_leader_id != i) { cpuinfo_log_debug( "heuristic detection of core clusters failed: " - "processor %"PRIu32" is expected to start a new cluster #%"PRIu32" with %"PRIu32" cores, " - "but system siblings lists reported it as a sibling of processor %"PRIu32, - i, cluster, cluster_processors[cluster], processors[i].package_leader_id); + "processor %" PRIu32 + " is expected to start a new cluster #%" PRIu32 " with %" PRIu32 + " cores, " + "but system siblings lists reported it as a sibling of processor %" PRIu32, + i, + cluster, + cluster_processors[cluster], + processors[i].package_leader_id); return false; } } else { @@ -119,48 +138,73 @@ bool cpuinfo_arm_linux_detect_core_clusters_by_heuristic( cluster_start = i; expected_cluster_processors = cluster_processors[cluster++]; } else { - /* Expect this processor to belong to the same cluster as processor */ + /* Expect this processor to belong to the same + * cluster as processor */ if (expected_cluster_exists) { /* - * The cluster suggested by the heuristic was already parsed from system siblings lists. - * For all processors we expect in the cluster, check that: - * - They have pre-assigned cluster from siblings lists (CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER flag). - * - They were assigned to the same cluster based on siblings lists - * (package_leader_id points to the first processor in the cluster). + * The cluster suggested by the + * heuristic was already parsed from + * system siblings lists. For all + * processors we expect in the cluster, + * check that: + * - They have pre-assigned cluster from + * siblings lists + * (CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER + * flag). + * - They were assigned to the same + * cluster based on siblings lists + * (package_leader_id points to the + * first processor in the cluster). */ if ((processors[i].flags & CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER) == 0) { cpuinfo_log_debug( "heuristic detection of core clusters failed: " - "processor %"PRIu32" is expected to belong to the cluster of processor %"PRIu32", " - "but system siblings lists did not report it as a sibling of processor %"PRIu32, - i, cluster_start, cluster_start); + "processor %" PRIu32 + " is expected to belong to the cluster of processor %" PRIu32 + ", " + "but system siblings lists did not report it as a sibling of processor %" PRIu32, + i, + cluster_start, + cluster_start); return false; } if (processors[i].package_leader_id != cluster_start) { cpuinfo_log_debug( "heuristic detection of core clusters failed: " - "processor %"PRIu32" is expected to belong to the cluster of processor %"PRIu32", " - "but system siblings lists reported it to belong to the cluster of processor %"PRIu32, - i, cluster_start, cluster_start); + "processor %" PRIu32 + " is expected to belong to the cluster of processor %" PRIu32 + ", " + "but system siblings lists reported it to belong to the cluster of processor %" PRIu32, + i, + cluster_start, + cluster_start); return false; } } else { /* - * The cluster suggest by the heuristic was not parsed from system siblings lists. - * For all processors we expect in the cluster, check that: - * - They have no pre-assigned cluster from siblings lists. - * - If their min/max CPU frequency is known, it is the same. - * - If any part of their MIDR (Implementer, Variant, Part, Revision) is known, it is the same. + * The cluster suggest by the heuristic + * was not parsed from system siblings + * lists. For all processors we expect + * in the cluster, check that: + * - They have no pre-assigned cluster + * from siblings lists. + * - If their min/max CPU frequency is + * known, it is the same. + * - If any part of their MIDR + * (Implementer, Variant, Part, + * Revision) is known, it is the same. */ if (processors[i].flags & CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER) { cpuinfo_log_debug( "heuristic detection of core clusters failed: " - "processor %"PRIu32" is expected to be unassigned to any cluster, " - "but system siblings lists reported it to belong to the cluster of processor %"PRIu32, - i, processors[i].package_leader_id); + "processor %" PRIu32 + " is expected to be unassigned to any cluster, " + "but system siblings lists reported it to belong to the cluster of processor %" PRIu32, + i, + processors[i].package_leader_id); return false; } @@ -169,8 +213,13 @@ bool cpuinfo_arm_linux_detect_core_clusters_by_heuristic( if (cluster_min_frequency != processors[i].min_frequency) { cpuinfo_log_debug( "heuristic detection of core clusters failed: " - "minimum frequency of processor %"PRIu32" (%"PRIu32" KHz) is different than of its expected cluster (%"PRIu32" KHz)", - i, processors[i].min_frequency, cluster_min_frequency); + "minimum frequency of processor %" PRIu32 + " (%" PRIu32 + " KHz) is different than of its expected cluster (%" PRIu32 + " KHz)", + i, + processors[i].min_frequency, + cluster_min_frequency); return false; } } else { @@ -184,8 +233,13 @@ bool cpuinfo_arm_linux_detect_core_clusters_by_heuristic( if (cluster_max_frequency != processors[i].max_frequency) { cpuinfo_log_debug( "heuristic detection of core clusters failed: " - "maximum frequency of processor %"PRIu32" (%"PRIu32" KHz) is different than of its expected cluster (%"PRIu32" KHz)", - i, processors[i].max_frequency, cluster_max_frequency); + "maximum frequency of processor %" PRIu32 + " (%" PRIu32 + " KHz) is different than of its expected cluster (%" PRIu32 + " KHz)", + i, + processors[i].max_frequency, + cluster_max_frequency); return false; } } else { @@ -196,41 +250,61 @@ bool cpuinfo_arm_linux_detect_core_clusters_by_heuristic( if (processors[i].flags & CPUINFO_ARM_LINUX_VALID_IMPLEMENTER) { if (cluster_flags & CPUINFO_ARM_LINUX_VALID_IMPLEMENTER) { - if ((cluster_midr & CPUINFO_ARM_MIDR_IMPLEMENTER_MASK) != (processors[i].midr & CPUINFO_ARM_MIDR_IMPLEMENTER_MASK)) { + if ((cluster_midr & CPUINFO_ARM_MIDR_IMPLEMENTER_MASK) != + (processors[i].midr & CPUINFO_ARM_MIDR_IMPLEMENTER_MASK)) { cpuinfo_log_debug( "heuristic detection of core clusters failed: " - "CPU Implementer of processor %"PRIu32" (0x%02"PRIx32") is different than of its expected cluster (0x%02"PRIx32")", - i, midr_get_implementer(processors[i].midr), midr_get_implementer(cluster_midr)); + "CPU Implementer of processor %" PRIu32 + " (0x%02" PRIx32 + ") is different than of its expected cluster (0x%02" PRIx32 + ")", + i, + midr_get_implementer(processors[i].midr), + midr_get_implementer(cluster_midr)); return false; } } else { - cluster_midr = midr_copy_implementer(cluster_midr, processors[i].midr); + cluster_midr = + midr_copy_implementer(cluster_midr, processors[i].midr); cluster_flags |= CPUINFO_ARM_LINUX_VALID_IMPLEMENTER; } } if (processors[i].flags & CPUINFO_ARM_LINUX_VALID_VARIANT) { if (cluster_flags & CPUINFO_ARM_LINUX_VALID_VARIANT) { - if ((cluster_midr & CPUINFO_ARM_MIDR_VARIANT_MASK) != (processors[i].midr & CPUINFO_ARM_MIDR_VARIANT_MASK)) { + if ((cluster_midr & CPUINFO_ARM_MIDR_VARIANT_MASK) != + (processors[i].midr & CPUINFO_ARM_MIDR_VARIANT_MASK)) { cpuinfo_log_debug( "heuristic detection of core clusters failed: " - "CPU Variant of processor %"PRIu32" (0x%"PRIx32") is different than of its expected cluster (0x%"PRIx32")", - i, midr_get_variant(processors[i].midr), midr_get_variant(cluster_midr)); + "CPU Variant of processor %" PRIu32 + " (0x%" PRIx32 + ") is different than of its expected cluster (0x%" PRIx32 + ")", + i, + midr_get_variant(processors[i].midr), + midr_get_variant(cluster_midr)); return false; } } else { - cluster_midr = midr_copy_variant(cluster_midr, processors[i].midr); + cluster_midr = + midr_copy_variant(cluster_midr, processors[i].midr); cluster_flags |= CPUINFO_ARM_LINUX_VALID_VARIANT; } } if (processors[i].flags & CPUINFO_ARM_LINUX_VALID_PART) { if (cluster_flags & CPUINFO_ARM_LINUX_VALID_PART) { - if ((cluster_midr & CPUINFO_ARM_MIDR_PART_MASK) != (processors[i].midr & CPUINFO_ARM_MIDR_PART_MASK)) { + if ((cluster_midr & CPUINFO_ARM_MIDR_PART_MASK) != + (processors[i].midr & CPUINFO_ARM_MIDR_PART_MASK)) { cpuinfo_log_debug( "heuristic detection of core clusters failed: " - "CPU Part of processor %"PRIu32" (0x%03"PRIx32") is different than of its expected cluster (0x%03"PRIx32")", - i, midr_get_part(processors[i].midr), midr_get_part(cluster_midr)); + "CPU Part of processor %" PRIu32 + " (0x%03" PRIx32 + ") is different than of its expected cluster (0x%03" PRIx32 + ")", + i, + midr_get_part(processors[i].midr), + midr_get_part(cluster_midr)); return false; } } else { @@ -241,15 +315,22 @@ bool cpuinfo_arm_linux_detect_core_clusters_by_heuristic( if (processors[i].flags & CPUINFO_ARM_LINUX_VALID_REVISION) { if (cluster_flags & CPUINFO_ARM_LINUX_VALID_REVISION) { - if ((cluster_midr & CPUINFO_ARM_MIDR_REVISION_MASK) != (processors[i].midr & CPUINFO_ARM_MIDR_REVISION_MASK)) { + if ((cluster_midr & CPUINFO_ARM_MIDR_REVISION_MASK) != + (processors[i].midr & CPUINFO_ARM_MIDR_REVISION_MASK)) { cpuinfo_log_debug( "heuristic detection of core clusters failed: " - "CPU Revision of processor %"PRIu32" (0x%"PRIx32") is different than of its expected cluster (0x%"PRIx32")", - i, midr_get_revision(cluster_midr), midr_get_revision(processors[i].midr)); + "CPU Revision of processor %" PRIu32 + " (0x%" PRIx32 + ") is different than of its expected cluster (0x%" PRIx32 + ")", + i, + midr_get_revision(cluster_midr), + midr_get_revision(processors[i].midr)); return false; } } else { - cluster_midr = midr_copy_revision(cluster_midr, processors[i].midr); + cluster_midr = + midr_copy_revision(cluster_midr, processors[i].midr); cluster_flags |= CPUINFO_ARM_LINUX_VALID_REVISION; } } @@ -265,16 +346,21 @@ bool cpuinfo_arm_linux_detect_core_clusters_by_heuristic( for (uint32_t i = 0; i < max_processors; i++) { if (bitmask_all(processors[i].flags, CPUINFO_LINUX_FLAG_VALID)) { if (expected_cluster_processors == 0) { - /* Expect this processor to start a new cluster */ + /* Expect this processor to start a new cluster + */ cluster_start = i; expected_cluster_processors = cluster_processors[cluster++]; } else { - /* Expect this processor to belong to the same cluster as processor */ + /* Expect this processor to belong to the same + * cluster as processor */ if (!(processors[i].flags & CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER)) { - cpuinfo_log_debug("assigned processor %"PRIu32" to cluster of processor %"PRIu32" based on heuristic", - i, cluster_start); + cpuinfo_log_debug( + "assigned processor %" PRIu32 " to cluster of processor %" PRIu32 + " based on heuristic", + i, + cluster_start); } processors[i].package_leader_id = cluster_start; @@ -291,38 +377,49 @@ bool cpuinfo_arm_linux_detect_core_clusters_by_heuristic( * - Clusters detected from OS-provided information are unchanged: * - Processors assigned to these clusters stay assigned to the same clusters * - No new processors are added to these clusters - * - Processors without pre-assigned cluster are clustered in one sequential scan: - * - If known details (min/max frequency, MIDR components) of a processor are compatible with a preceding - * processor, without pre-assigned cluster, the processor is assigned to the cluster of the preceding processor. - * - If known details (min/max frequency, MIDR components) of a processor are not compatible with a preceding - * processor, the processor is assigned to a newly created cluster. + * - Processors without pre-assigned cluster are clustered in one sequential + * scan: + * - If known details (min/max frequency, MIDR components) of a processor are + * compatible with a preceding processor, without pre-assigned cluster, the + * processor is assigned to the cluster of the preceding processor. + * - If known details (min/max frequency, MIDR components) of a processor are + * not compatible with a preceding processor, the processor is assigned to a + * newly created cluster. * - * The function must be called after parsing OS-provided information on core clusters, and usually is called only - * if heuristic assignment of processors to clusters (cpuinfo_arm_linux_cluster_processors_by_heuristic) failed. + * The function must be called after parsing OS-provided information on core + * clusters, and usually is called only if heuristic assignment of processors to + * clusters (cpuinfo_arm_linux_cluster_processors_by_heuristic) failed. * - * Its purpose is to detect clusters of cores when OS-provided information is lacking or incomplete, i.e. - * - Linux kernel is not configured to report information in sysfs topology leaf. - * - Linux kernel reports topology information only for online cores, and all cores on some of the clusters are offline. + * Its purpose is to detect clusters of cores when OS-provided information is + * lacking or incomplete, i.e. + * - Linux kernel is not configured to report information in sysfs topology + * leaf. + * - Linux kernel reports topology information only for online cores, and all + * cores on some of the clusters are offline. * - * Sequential assignment of processors to clusters always succeeds, and upon exit, all usable processors in the + * Sequential assignment of processors to clusters always succeeds, and upon + * exit, all usable processors in the * @p processors array have cluster information. * * @param max_processors - number of elements in the @p processors array. - * @param[in,out] processors - processor descriptors with pre-parsed POSSIBLE and PRESENT flags, minimum/maximum - * frequency, MIDR information, and core cluster (package siblings list) information. + * @param[in,out] processors - processor descriptors with pre-parsed POSSIBLE + * and PRESENT flags, minimum/maximum frequency, MIDR information, and core + * cluster (package siblings list) information. * - * @retval true if the heuristic successfully assigned all processors into clusters of cores. - * @retval false if known details about processors contradict the heuristic configuration of core clusters. + * @retval true if the heuristic successfully assigned all processors into + * clusters of cores. + * @retval false if known details about processors contradict the heuristic + * configuration of core clusters. */ void cpuinfo_arm_linux_detect_core_clusters_by_sequential_scan( uint32_t max_processors, - struct cpuinfo_arm_linux_processor processors[restrict static max_processors]) -{ + struct cpuinfo_arm_linux_processor processors[restrict static max_processors]) { uint32_t cluster_flags = 0; uint32_t cluster_processors = 0; uint32_t cluster_start, cluster_midr, cluster_max_frequency, cluster_min_frequency; for (uint32_t i = 0; i < max_processors; i++) { - if ((processors[i].flags & (CPUINFO_LINUX_FLAG_VALID | CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER)) == CPUINFO_LINUX_FLAG_VALID) { + if ((processors[i].flags & (CPUINFO_LINUX_FLAG_VALID | CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER)) == + CPUINFO_LINUX_FLAG_VALID) { if (cluster_processors == 0) { goto new_cluster; } @@ -331,9 +428,14 @@ void cpuinfo_arm_linux_detect_core_clusters_by_sequential_scan( if (cluster_flags & CPUINFO_LINUX_FLAG_MIN_FREQUENCY) { if (cluster_min_frequency != processors[i].min_frequency) { cpuinfo_log_info( - "minimum frequency of processor %"PRIu32" (%"PRIu32" KHz) is different than of preceding cluster (%"PRIu32" KHz); " - "processor %"PRIu32" starts to a new cluster", - i, processors[i].min_frequency, cluster_min_frequency, i); + "minimum frequency of processor %" PRIu32 " (%" PRIu32 + " KHz) is different than of preceding cluster (%" PRIu32 + " KHz); " + "processor %" PRIu32 " starts to a new cluster", + i, + processors[i].min_frequency, + cluster_min_frequency, + i); goto new_cluster; } } else { @@ -346,9 +448,14 @@ void cpuinfo_arm_linux_detect_core_clusters_by_sequential_scan( if (cluster_flags & CPUINFO_LINUX_FLAG_MAX_FREQUENCY) { if (cluster_max_frequency != processors[i].max_frequency) { cpuinfo_log_debug( - "maximum frequency of processor %"PRIu32" (%"PRIu32" KHz) is different than of preceding cluster (%"PRIu32" KHz); " - "processor %"PRIu32" starts a new cluster", - i, processors[i].max_frequency, cluster_max_frequency, i); + "maximum frequency of processor %" PRIu32 " (%" PRIu32 + " KHz) is different than of preceding cluster (%" PRIu32 + " KHz); " + "processor %" PRIu32 " starts a new cluster", + i, + processors[i].max_frequency, + cluster_max_frequency, + i); goto new_cluster; } } else { @@ -359,11 +466,17 @@ void cpuinfo_arm_linux_detect_core_clusters_by_sequential_scan( if (processors[i].flags & CPUINFO_ARM_LINUX_VALID_IMPLEMENTER) { if (cluster_flags & CPUINFO_ARM_LINUX_VALID_IMPLEMENTER) { - if ((cluster_midr & CPUINFO_ARM_MIDR_IMPLEMENTER_MASK) != (processors[i].midr & CPUINFO_ARM_MIDR_IMPLEMENTER_MASK)) { + if ((cluster_midr & CPUINFO_ARM_MIDR_IMPLEMENTER_MASK) != + (processors[i].midr & CPUINFO_ARM_MIDR_IMPLEMENTER_MASK)) { cpuinfo_log_debug( - "CPU Implementer of processor %"PRIu32" (0x%02"PRIx32") is different than of preceding cluster (0x%02"PRIx32"); " - "processor %"PRIu32" starts to a new cluster", - i, midr_get_implementer(processors[i].midr), midr_get_implementer(cluster_midr), i); + "CPU Implementer of processor %" PRIu32 " (0x%02" PRIx32 + ") is different than of preceding cluster (0x%02" PRIx32 + "); " + "processor %" PRIu32 " starts to a new cluster", + i, + midr_get_implementer(processors[i].midr), + midr_get_implementer(cluster_midr), + i); goto new_cluster; } } else { @@ -374,11 +487,17 @@ void cpuinfo_arm_linux_detect_core_clusters_by_sequential_scan( if (processors[i].flags & CPUINFO_ARM_LINUX_VALID_VARIANT) { if (cluster_flags & CPUINFO_ARM_LINUX_VALID_VARIANT) { - if ((cluster_midr & CPUINFO_ARM_MIDR_VARIANT_MASK) != (processors[i].midr & CPUINFO_ARM_MIDR_VARIANT_MASK)) { + if ((cluster_midr & CPUINFO_ARM_MIDR_VARIANT_MASK) != + (processors[i].midr & CPUINFO_ARM_MIDR_VARIANT_MASK)) { cpuinfo_log_debug( - "CPU Variant of processor %"PRIu32" (0x%"PRIx32") is different than of its expected cluster (0x%"PRIx32")" - "processor %"PRIu32" starts to a new cluster", - i, midr_get_variant(processors[i].midr), midr_get_variant(cluster_midr), i); + "CPU Variant of processor %" PRIu32 " (0x%" PRIx32 + ") is different than of its expected cluster (0x%" PRIx32 + ")" + "processor %" PRIu32 " starts to a new cluster", + i, + midr_get_variant(processors[i].midr), + midr_get_variant(cluster_midr), + i); goto new_cluster; } } else { @@ -389,11 +508,17 @@ void cpuinfo_arm_linux_detect_core_clusters_by_sequential_scan( if (processors[i].flags & CPUINFO_ARM_LINUX_VALID_PART) { if (cluster_flags & CPUINFO_ARM_LINUX_VALID_PART) { - if ((cluster_midr & CPUINFO_ARM_MIDR_PART_MASK) != (processors[i].midr & CPUINFO_ARM_MIDR_PART_MASK)) { + if ((cluster_midr & CPUINFO_ARM_MIDR_PART_MASK) != + (processors[i].midr & CPUINFO_ARM_MIDR_PART_MASK)) { cpuinfo_log_debug( - "CPU Part of processor %"PRIu32" (0x%03"PRIx32") is different than of its expected cluster (0x%03"PRIx32")" - "processor %"PRIu32" starts to a new cluster", - i, midr_get_part(processors[i].midr), midr_get_part(cluster_midr), i); + "CPU Part of processor %" PRIu32 " (0x%03" PRIx32 + ") is different than of its expected cluster (0x%03" PRIx32 + ")" + "processor %" PRIu32 " starts to a new cluster", + i, + midr_get_part(processors[i].midr), + midr_get_part(cluster_midr), + i); goto new_cluster; } } else { @@ -404,11 +529,17 @@ void cpuinfo_arm_linux_detect_core_clusters_by_sequential_scan( if (processors[i].flags & CPUINFO_ARM_LINUX_VALID_REVISION) { if (cluster_flags & CPUINFO_ARM_LINUX_VALID_REVISION) { - if ((cluster_midr & CPUINFO_ARM_MIDR_REVISION_MASK) != (processors[i].midr & CPUINFO_ARM_MIDR_REVISION_MASK)) { + if ((cluster_midr & CPUINFO_ARM_MIDR_REVISION_MASK) != + (processors[i].midr & CPUINFO_ARM_MIDR_REVISION_MASK)) { cpuinfo_log_debug( - "CPU Revision of processor %"PRIu32" (0x%"PRIx32") is different than of its expected cluster (0x%"PRIx32")" - "processor %"PRIu32" starts to a new cluster", - i, midr_get_revision(cluster_midr), midr_get_revision(processors[i].midr), i); + "CPU Revision of processor %" PRIu32 " (0x%" PRIx32 + ") is different than of its expected cluster (0x%" PRIx32 + ")" + "processor %" PRIu32 " starts to a new cluster", + i, + midr_get_revision(cluster_midr), + midr_get_revision(processors[i].midr), + i); goto new_cluster; } } else { @@ -417,21 +548,26 @@ void cpuinfo_arm_linux_detect_core_clusters_by_sequential_scan( } } - /* All checks passed, attach processor to the preceding cluster */ + /* All checks passed, attach processor to the preceding + * cluster */ cluster_processors++; processors[i].package_leader_id = cluster_start; processors[i].flags |= CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER; - cpuinfo_log_debug("assigned processor %"PRIu32" to preceding cluster of processor %"PRIu32, i, cluster_start); + cpuinfo_log_debug( + "assigned processor %" PRIu32 " to preceding cluster of processor %" PRIu32, + i, + cluster_start); continue; -new_cluster: + new_cluster: /* Create a new cluster starting with processor i */ cluster_start = i; processors[i].package_leader_id = i; processors[i].flags |= CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER; cluster_processors = 1; - /* Copy known information from processor to cluster, and set the flags accordingly */ + /* Copy known information from processor to cluster, and + * set the flags accordingly */ cluster_flags = 0; if (processors[i].flags & CPUINFO_LINUX_FLAG_MIN_FREQUENCY) { cluster_min_frequency = processors[i].min_frequency; @@ -463,27 +599,30 @@ void cpuinfo_arm_linux_detect_core_clusters_by_sequential_scan( /* * Counts the number of logical processors in each core cluster. - * This function should be called after all processors are assigned to core clusters. + * This function should be called after all processors are assigned to core + * clusters. * * @param max_processors - number of elements in the @p processors array. - * @param[in,out] processors - processor descriptors with pre-parsed POSSIBLE and PRESENT flags, - * and decoded core cluster (package_leader_id) information. - * The function expects the value of processors[i].package_processor_count to be zero. - * Upon return, processors[i].package_processor_count will contain the number of logical + * @param[in,out] processors - processor descriptors with pre-parsed POSSIBLE + * and PRESENT flags, and decoded core cluster (package_leader_id) information. + * The function expects the value of + * processors[i].package_processor_count to be zero. Upon return, + * processors[i].package_processor_count will contain the number of logical * processors in the respective core cluster. */ void cpuinfo_arm_linux_count_cluster_processors( uint32_t max_processors, - struct cpuinfo_arm_linux_processor processors[restrict static max_processors]) -{ - /* First pass: accumulate the number of processors at the group leader's package_processor_count */ + struct cpuinfo_arm_linux_processor processors[restrict static max_processors]) { + /* First pass: accumulate the number of processors at the group leader's + * package_processor_count */ for (uint32_t i = 0; i < max_processors; i++) { if (bitmask_all(processors[i].flags, CPUINFO_LINUX_FLAG_VALID)) { const uint32_t package_leader_id = processors[i].package_leader_id; processors[package_leader_id].package_processor_count += 1; } } - /* Second pass: copy the package_processor_count from the group leader processor */ + /* Second pass: copy the package_processor_count from the group leader + * processor */ for (uint32_t i = 0; i < max_processors; i++) { if (bitmask_all(processors[i].flags, CPUINFO_LINUX_FLAG_VALID)) { const uint32_t package_leader_id = processors[i].package_leader_id; diff --git a/src/arm/linux/cp.h b/src/arm/linux/cp.h index 0abd7d61..3f084d66 100644 --- a/src/arm/linux/cp.h +++ b/src/arm/linux/cp.h @@ -1,50 +1,49 @@ #include - #if CPUINFO_MOCK - extern uint32_t cpuinfo_arm_fpsid; - extern uint32_t cpuinfo_arm_mvfr0; - extern uint32_t cpuinfo_arm_wcid; +extern uint32_t cpuinfo_arm_fpsid; +extern uint32_t cpuinfo_arm_mvfr0; +extern uint32_t cpuinfo_arm_wcid; - static inline uint32_t read_fpsid(void) { - return cpuinfo_arm_fpsid; - } +static inline uint32_t read_fpsid(void) { + return cpuinfo_arm_fpsid; +} - static inline uint32_t read_mvfr0(void) { - return cpuinfo_arm_mvfr0; - } +static inline uint32_t read_mvfr0(void) { + return cpuinfo_arm_mvfr0; +} - static inline uint32_t read_wcid(void) { - return cpuinfo_arm_wcid; - } +static inline uint32_t read_wcid(void) { + return cpuinfo_arm_wcid; +} #else - #if !defined(__ARM_ARCH_7A__) && !defined(__ARM_ARCH_8A__) && !(defined(__ARM_ARCH) && (__ARM_ARCH >= 7)) - /* - * CoProcessor 10 is inaccessible from user mode since ARMv7, - * and clang refuses to compile inline assembly when targeting ARMv7+ - */ - static inline uint32_t read_fpsid(void) { - uint32_t fpsid; - __asm__ __volatile__("MRC p10, 0x7, %[fpsid], cr0, cr0, 0" : [fpsid] "=r" (fpsid)); - return fpsid; - } +#if !defined(__ARM_ARCH_7A__) && !defined(__ARM_ARCH_8A__) && !(defined(__ARM_ARCH) && (__ARM_ARCH >= 7)) +/* + * CoProcessor 10 is inaccessible from user mode since ARMv7, + * and clang refuses to compile inline assembly when targeting ARMv7+ + */ +static inline uint32_t read_fpsid(void) { + uint32_t fpsid; + __asm__ __volatile__("MRC p10, 0x7, %[fpsid], cr0, cr0, 0" : [fpsid] "=r"(fpsid)); + return fpsid; +} - static inline uint32_t read_mvfr0(void) { - uint32_t mvfr0; - __asm__ __volatile__("MRC p10, 0x7, %[mvfr0], cr7, cr0, 0" : [mvfr0] "=r" (mvfr0)); - return mvfr0; - } - #endif - #if !defined(__ARM_ARCH_8A__) && !(defined(__ARM_ARCH) && (__ARM_ARCH >= 8)) - /* - * In ARMv8, AArch32 state supports only conceptual coprocessors CP10, CP11, CP14, and CP15. - * AArch64 does not support the concept of coprocessors. - * and clang refuses to compile inline assembly when targeting ARMv8+ - */ - static inline uint32_t read_wcid(void) { - uint32_t wcid; - __asm__ __volatile__("MRC p1, 0, %[wcid], c0, c0" : [wcid] "=r" (wcid)); - return wcid; - } - #endif +static inline uint32_t read_mvfr0(void) { + uint32_t mvfr0; + __asm__ __volatile__("MRC p10, 0x7, %[mvfr0], cr7, cr0, 0" : [mvfr0] "=r"(mvfr0)); + return mvfr0; +} +#endif +#if !defined(__ARM_ARCH_8A__) && !(defined(__ARM_ARCH) && (__ARM_ARCH >= 8)) +/* + * In ARMv8, AArch32 state supports only conceptual coprocessors CP10, CP11, + * CP14, and CP15. AArch64 does not support the concept of coprocessors. and + * clang refuses to compile inline assembly when targeting ARMv8+ + */ +static inline uint32_t read_wcid(void) { + uint32_t wcid; + __asm__ __volatile__("MRC p1, 0, %[wcid], c0, c0" : [wcid] "=r"(wcid)); + return wcid; +} +#endif #endif diff --git a/src/arm/linux/cpuinfo.c b/src/arm/linux/cpuinfo.c index b7805b5e..3f477e77 100644 --- a/src/arm/linux/cpuinfo.c +++ b/src/arm/linux/cpuinfo.c @@ -1,26 +1,22 @@ #include +#include #include #include -#include #include -#include #include #include #include +#include /* - * Size, in chars, of the on-stack buffer used for parsing lines of /proc/cpuinfo. - * This is also the limit on the length of a single line. + * Size, in chars, of the on-stack buffer used for parsing lines of + * /proc/cpuinfo. This is also the limit on the length of a single line. */ #define BUFFER_SIZE 1024 - -static uint32_t parse_processor_number( - const char* processor_start, - const char* processor_end) -{ - const size_t processor_length = (size_t) (processor_end - processor_start); +static uint32_t parse_processor_number(const char* processor_start, const char* processor_end) { + const size_t processor_length = (size_t)(processor_end - processor_start); if (processor_length == 0) { cpuinfo_log_warning("Processor number in /proc/cpuinfo is ignored: string is empty"); @@ -29,10 +25,12 @@ static uint32_t parse_processor_number( uint32_t processor_number = 0; for (const char* digit_ptr = processor_start; digit_ptr != processor_end; digit_ptr++) { - const uint32_t digit = (uint32_t) (*digit_ptr - '0'); + const uint32_t digit = (uint32_t)(*digit_ptr - '0'); if (digit > 10) { - cpuinfo_log_warning("non-decimal suffix %.*s in /proc/cpuinfo processor number is ignored", - (int) (processor_end - digit_ptr), digit_ptr); + cpuinfo_log_warning( + "non-decimal suffix %.*s in /proc/cpuinfo processor number is ignored", + (int)(processor_end - digit_ptr), + digit_ptr); break; } @@ -45,42 +43,48 @@ static uint32_t parse_processor_number( /* * Full list of ARM features reported in /proc/cpuinfo: * - * * swp - support for SWP instruction (deprecated in ARMv7, can be removed in future) - * * half - support for half-word loads and stores. These instruction are part of ARMv4, - * so no need to check it on supported CPUs. - * * thumb - support for 16-bit Thumb instruction set. Note that BX instruction is detected - * by ARMv4T architecture, not by this flag. - * * 26bit - old CPUs merged 26-bit PC and program status register (flags) into 32-bit PC - * and had special instructions for working with packed PC. Now it is all deprecated. - * * fastmult - most old ARM CPUs could only compute 2 bits of multiplication result per clock - * cycle, but CPUs with M suffix (e.g. ARM7TDMI) could compute 4 bits per cycle. - * Of course, now it makes no sense. - * * fpa - floating point accelerator available. On original ARM ABI all floating-point operations - * generated FPA instructions. If FPA was not available, these instructions generated - * "illegal operation" interrupts, and the OS processed them by emulating the FPA instructions. - * Debian used this ABI before it switched to EABI. Now FPA is deprecated. - * * vfp - vector floating point instructions. Available on most modern CPUs (as part of VFPv3). - * Required by Android ARMv7A ABI and by Ubuntu on ARM. + * * swp - support for SWP instruction (deprecated in ARMv7, can be removed + *in future) + * * half - support for half-word loads and stores. These instruction are + *part of ARMv4, so no need to check it on supported CPUs. + * * thumb - support for 16-bit Thumb instruction set. Note that BX + *instruction is detected by ARMv4T architecture, not by this flag. + * * 26bit - old CPUs merged 26-bit PC and program status register (flags) + *into 32-bit PC and had special instructions for working with packed PC. Now it + *is all deprecated. + * * fastmult - most old ARM CPUs could only compute 2 bits of + *multiplication result per clock cycle, but CPUs with M suffix (e.g. ARM7TDMI) + *could compute 4 bits per cycle. Of course, now it makes no sense. + * * fpa - floating point accelerator available. On original ARM ABI all + *floating-point operations generated FPA instructions. If FPA was not + *available, these instructions generated "illegal operation" interrupts, and + *the OS processed them by emulating the FPA instructions. Debian used this ABI + *before it switched to EABI. Now FPA is deprecated. + * * vfp - vector floating point instructions. Available on most modern + *CPUs (as part of VFPv3). Required by Android ARMv7A ABI and by Ubuntu on ARM. * Note: there is no flag for VFPv2. - * * edsp - V5E instructions: saturating add/sub and 16-bit x 16-bit -> 32/64-bit multiplications. - * Required on Android, supported by all CPUs in production. + * * edsp - V5E instructions: saturating add/sub and 16-bit x 16-bit -> + *32/64-bit multiplications. Required on Android, supported by all CPUs in + *production. * * java - Jazelle extension. Supported on most CPUs. * * iwmmxt - Intel/Marvell Wireless MMX instructions. 64-bit integer SIMD. - * Supported on XScale (Since PXA270) and Sheeva (PJ1, PJ4) architectures. - * Note that there is no flag for WMMX2 instructions. + * Supported on XScale (Since PXA270) and Sheeva (PJ1, PJ4) + *architectures. Note that there is no flag for WMMX2 instructions. * * crunch - Maverick Crunch instructions. Junk. * * thumbee - ThumbEE instructions. Almost no documentation is available. - * * neon - NEON instructions (aka Advanced SIMD). MVFR1 register gives more - * fine-grained information on particular supported features, but - * the Linux kernel exports only a single flag for all of them. - * According to ARMv7A docs it also implies the availability of VFPv3 - * (with 32 double-precision registers d0-d31). - * * vfpv3 - VFPv3 instructions. Available on most modern CPUs. Augment VFPv2 by - * conversion to/from integers and load constant instructions. - * Required by Android ARMv7A ABI and by Ubuntu on ARM. - * * vfpv3d16 - VFPv3 instructions with only 16 double-precision registers (d0-d15). + * * neon - NEON instructions (aka Advanced SIMD). MVFR1 register gives + *more fine-grained information on particular supported features, but the Linux + *kernel exports only a single flag for all of them. According to ARMv7A docs it + *also implies the availability of VFPv3 (with 32 double-precision registers + *d0-d31). + * * vfpv3 - VFPv3 instructions. Available on most modern CPUs. Augment + *VFPv2 by conversion to/from integers and load constant instructions. Required + *by Android ARMv7A ABI and by Ubuntu on ARM. + * * vfpv3d16 - VFPv3 instructions with only 16 double-precision registers + *(d0-d15). * * tls - software thread ID registers. - * Used by kernel (and likely libc) for efficient implementation of TLS. + * Used by kernel (and likely libc) for efficient implementation of + *TLS. * * vfpv4 - fused multiply-add instructions. * * idiva - DIV instructions available in ARM mode. * * idivt - DIV instructions available in Thumb mode. @@ -93,15 +97,15 @@ static uint32_t parse_processor_number( * * sha2 - SHA2 instructions. * * crc32 - CRC32 instructions. * - * /proc/cpuinfo on ARM is populated in file arch/arm/kernel/setup.c in Linux kernel - * Note that some devices may use patched Linux kernels with different feature names. - * However, the names above were checked on a large number of /proc/cpuinfo listings. + * /proc/cpuinfo on ARM is populated in file arch/arm/kernel/setup.c in + *Linux kernel Note that some devices may use patched Linux kernels with + *different feature names. However, the names above were checked on a large + *number of /proc/cpuinfo listings. */ static void parse_features( const char* features_start, const char* features_end, - struct cpuinfo_arm_linux_processor processor[restrict static 1]) -{ + struct cpuinfo_arm_linux_processor processor[restrict static 1]) { const char* feature_start = features_start; const char* feature_end; @@ -115,7 +119,7 @@ static void parse_features( break; } } - const size_t feature_length = (size_t) (feature_end - feature_start); + const size_t feature_length = (size_t)(feature_end - feature_start); switch (feature_length) { case 2: @@ -126,8 +130,9 @@ static void parse_features( #if CPUINFO_ARCH_ARM } else if (memcmp(feature_start, "wp", feature_length) == 0) { /* - * Some AArch64 kernels, including the one on Nexus 5X, - * erroneously report "swp" as "wp" to AArch32 programs + * Some AArch64 kernels, including the + * one on Nexus 5X, erroneously report + * "swp" as "wp" to AArch32 programs */ processor->features |= CPUINFO_ARM_LINUX_FEATURE_SWP; #endif @@ -137,11 +142,11 @@ static void parse_features( break; case 3: if (memcmp(feature_start, "aes", feature_length) == 0) { - #if CPUINFO_ARCH_ARM - processor->features2 |= CPUINFO_ARM_LINUX_FEATURE2_AES; - #elif CPUINFO_ARCH_ARM64 - processor->features |= CPUINFO_ARM_LINUX_FEATURE_AES; - #endif +#if CPUINFO_ARCH_ARM + processor->features2 |= CPUINFO_ARM_LINUX_FEATURE2_AES; +#elif CPUINFO_ARCH_ARM64 + processor->features |= CPUINFO_ARM_LINUX_FEATURE_AES; +#endif #if CPUINFO_ARCH_ARM } else if (memcmp(feature_start, "swp", feature_length) == 0) { processor->features |= CPUINFO_ARM_LINUX_FEATURE_SWP; @@ -158,29 +163,29 @@ static void parse_features( break; case 4: if (memcmp(feature_start, "sha1", feature_length) == 0) { - #if CPUINFO_ARCH_ARM - processor->features2 |= CPUINFO_ARM_LINUX_FEATURE2_SHA1; - #elif CPUINFO_ARCH_ARM64 - processor->features |= CPUINFO_ARM_LINUX_FEATURE_SHA1; - #endif +#if CPUINFO_ARCH_ARM + processor->features2 |= CPUINFO_ARM_LINUX_FEATURE2_SHA1; +#elif CPUINFO_ARCH_ARM64 + processor->features |= CPUINFO_ARM_LINUX_FEATURE_SHA1; +#endif } else if (memcmp(feature_start, "sha2", feature_length) == 0) { - #if CPUINFO_ARCH_ARM - processor->features2 |= CPUINFO_ARM_LINUX_FEATURE2_SHA2; - #elif CPUINFO_ARCH_ARM64 - processor->features |= CPUINFO_ARM_LINUX_FEATURE_SHA2; - #endif +#if CPUINFO_ARCH_ARM + processor->features2 |= CPUINFO_ARM_LINUX_FEATURE2_SHA2; +#elif CPUINFO_ARCH_ARM64 + processor->features |= CPUINFO_ARM_LINUX_FEATURE_SHA2; +#endif } else if (memcmp(feature_start, "fphp", feature_length) == 0) { - #if CPUINFO_ARCH_ARM64 - processor->features |= CPUINFO_ARM_LINUX_FEATURE_FPHP; - #endif +#if CPUINFO_ARCH_ARM64 + processor->features |= CPUINFO_ARM_LINUX_FEATURE_FPHP; +#endif } else if (memcmp(feature_start, "fcma", feature_length) == 0) { - #if CPUINFO_ARCH_ARM64 - processor->features |= CPUINFO_ARM_LINUX_FEATURE_FCMA; - #endif +#if CPUINFO_ARCH_ARM64 + processor->features |= CPUINFO_ARM_LINUX_FEATURE_FCMA; +#endif } else if (memcmp(feature_start, "i8mm", feature_length) == 0) { - #if CPUINFO_ARCH_ARM64 - processor->features2 |= CPUINFO_ARM_LINUX_FEATURE2_I8MM; - #endif +#if CPUINFO_ARCH_ARM64 + processor->features2 |= CPUINFO_ARM_LINUX_FEATURE2_I8MM; +#endif #if CPUINFO_ARCH_ARM } else if (memcmp(feature_start, "half", feature_length) == 0) { processor->features |= CPUINFO_ARM_LINUX_FEATURE_HALF; @@ -194,8 +199,9 @@ static void parse_features( processor->features |= CPUINFO_ARM_LINUX_FEATURE_LPAE; } else if (memcmp(feature_start, "tlsi", feature_length) == 0) { /* - * Some AArch64 kernels, including the one on Nexus 5X, - * erroneously report "tls" as "tlsi" to AArch32 programs + * Some AArch64 kernels, including the + * one on Nexus 5X, erroneously report + * "tls" as "tlsi" to AArch32 programs */ processor->features |= CPUINFO_ARM_LINUX_FEATURE_TLS; #endif /* CPUINFO_ARCH_ARM */ @@ -205,33 +211,33 @@ static void parse_features( break; case 5: if (memcmp(feature_start, "pmull", feature_length) == 0) { - #if CPUINFO_ARCH_ARM - processor->features2 |= CPUINFO_ARM_LINUX_FEATURE2_PMULL; - #elif CPUINFO_ARCH_ARM64 - processor->features |= CPUINFO_ARM_LINUX_FEATURE_PMULL; - #endif +#if CPUINFO_ARCH_ARM + processor->features2 |= CPUINFO_ARM_LINUX_FEATURE2_PMULL; +#elif CPUINFO_ARCH_ARM64 + processor->features |= CPUINFO_ARM_LINUX_FEATURE_PMULL; +#endif } else if (memcmp(feature_start, "crc32", feature_length) == 0) { - #if CPUINFO_ARCH_ARM - processor->features2 |= CPUINFO_ARM_LINUX_FEATURE2_CRC32; - #elif CPUINFO_ARCH_ARM64 - processor->features |= CPUINFO_ARM_LINUX_FEATURE_CRC32; - #endif +#if CPUINFO_ARCH_ARM + processor->features2 |= CPUINFO_ARM_LINUX_FEATURE2_CRC32; +#elif CPUINFO_ARCH_ARM64 + processor->features |= CPUINFO_ARM_LINUX_FEATURE_CRC32; +#endif } else if (memcmp(feature_start, "asimd", feature_length) == 0) { - #if CPUINFO_ARCH_ARM64 - processor->features |= CPUINFO_ARM_LINUX_FEATURE_ASIMD; - #endif +#if CPUINFO_ARCH_ARM64 + processor->features |= CPUINFO_ARM_LINUX_FEATURE_ASIMD; +#endif } else if (memcmp(feature_start, "cpuid", feature_length) == 0) { - #if CPUINFO_ARCH_ARM64 - processor->features |= CPUINFO_ARM_LINUX_FEATURE_CPUID; - #endif +#if CPUINFO_ARCH_ARM64 + processor->features |= CPUINFO_ARM_LINUX_FEATURE_CPUID; +#endif } else if (memcmp(feature_start, "jscvt", feature_length) == 0) { - #if CPUINFO_ARCH_ARM64 - processor->features |= CPUINFO_ARM_LINUX_FEATURE_JSCVT; - #endif +#if CPUINFO_ARCH_ARM64 + processor->features |= CPUINFO_ARM_LINUX_FEATURE_JSCVT; +#endif } else if (memcmp(feature_start, "lrcpc", feature_length) == 0) { - #if CPUINFO_ARCH_ARM64 - processor->features |= CPUINFO_ARM_LINUX_FEATURE_LRCPC; - #endif +#if CPUINFO_ARCH_ARM64 + processor->features |= CPUINFO_ARM_LINUX_FEATURE_LRCPC; +#endif #if CPUINFO_ARCH_ARM } else if (memcmp(feature_start, "thumb", feature_length) == 0) { processor->features |= CPUINFO_ARM_LINUX_FEATURE_THUMB; @@ -249,7 +255,7 @@ static void parse_features( } else { goto unexpected; } - break; + break; #if CPUINFO_ARCH_ARM case 6: if (memcmp(feature_start, "iwmmxt", feature_length) == 0) { @@ -267,13 +273,13 @@ static void parse_features( if (memcmp(feature_start, "evtstrm", feature_length) == 0) { processor->features |= CPUINFO_ARM_LINUX_FEATURE_EVTSTRM; } else if (memcmp(feature_start, "atomics", feature_length) == 0) { - #if CPUINFO_ARCH_ARM64 - processor->features |= CPUINFO_ARM_LINUX_FEATURE_ATOMICS; - #endif +#if CPUINFO_ARCH_ARM64 + processor->features |= CPUINFO_ARM_LINUX_FEATURE_ATOMICS; +#endif } else if (memcmp(feature_start, "asimdhp", feature_length) == 0) { - #if CPUINFO_ARCH_ARM64 - processor->features |= CPUINFO_ARM_LINUX_FEATURE_ASIMDHP; - #endif +#if CPUINFO_ARCH_ARM64 + processor->features |= CPUINFO_ARM_LINUX_FEATURE_ASIMDHP; +#endif #if CPUINFO_ARCH_ARM } else if (memcmp(feature_start, "thumbee", feature_length) == 0) { processor->features |= CPUINFO_ARM_LINUX_FEATURE_THUMBEE; @@ -284,13 +290,13 @@ static void parse_features( break; case 8: if (memcmp(feature_start, "asimdrdm", feature_length) == 0) { - #if CPUINFO_ARCH_ARM64 - processor->features |= CPUINFO_ARM_LINUX_FEATURE_ASIMDRDM; - #endif +#if CPUINFO_ARCH_ARM64 + processor->features |= CPUINFO_ARM_LINUX_FEATURE_ASIMDRDM; +#endif } else if (memcmp(feature_start, "asimdfhm", feature_length) == 0) { - #if CPUINFO_ARCH_ARM64 - processor->features |= CPUINFO_ARM_LINUX_FEATURE_ASIMDFHM; - #endif +#if CPUINFO_ARCH_ARM64 + processor->features |= CPUINFO_ARM_LINUX_FEATURE_ASIMDFHM; +#endif #if CPUINFO_ARCH_ARM } else if (memcmp(feature_start, "fastmult", feature_length) == 0) { processor->features |= CPUINFO_ARM_LINUX_FEATURE_FASTMULT; @@ -303,8 +309,10 @@ static void parse_features( break; default: unexpected: - cpuinfo_log_warning("unexpected /proc/cpuinfo feature \"%.*s\" is ignored", - (int) feature_length, feature_start); + cpuinfo_log_warning( + "unexpected /proc/cpuinfo feature \"%.*s\" is ignored", + (int)feature_length, + feature_start); break; } feature_start = feature_end; @@ -319,10 +327,10 @@ static void parse_features( static void parse_cpu_architecture( const char* cpu_architecture_start, const char* cpu_architecture_end, - struct cpuinfo_arm_linux_processor processor[restrict static 1]) -{ - const size_t cpu_architecture_length = (size_t) (cpu_architecture_end - cpu_architecture_start); - /* Early AArch64 kernels report "CPU architecture: AArch64" instead of a numeric value 8 */ + struct cpuinfo_arm_linux_processor processor[restrict static 1]) { + const size_t cpu_architecture_length = (size_t)(cpu_architecture_end - cpu_architecture_start); + /* Early AArch64 kernels report "CPU architecture: AArch64" instead of a + * numeric value 8 */ if (cpu_architecture_length == 7) { if (memcmp(cpu_architecture_start, "AArch64", cpu_architecture_length) == 0) { processor->midr = midr_set_architecture(processor->midr, UINT32_C(0xF)); @@ -332,7 +340,6 @@ static void parse_cpu_architecture( } } - uint32_t architecture = 0; const char* cpu_architecture_ptr = cpu_architecture_start; for (; cpu_architecture_ptr != cpu_architecture_end; cpu_architecture_ptr++) { @@ -347,8 +354,10 @@ static void parse_cpu_architecture( } if (cpu_architecture_ptr == cpu_architecture_start) { - cpuinfo_log_warning("CPU architecture %.*s in /proc/cpuinfo is ignored due to non-digit at the beginning of the string", - (int) cpu_architecture_length, cpu_architecture_start); + cpuinfo_log_warning( + "CPU architecture %.*s in /proc/cpuinfo is ignored due to non-digit at the beginning of the string", + (int)cpu_architecture_length, + cpu_architecture_start); } else { if (architecture != 0) { processor->architecture_version = architecture; @@ -370,17 +379,22 @@ static void parse_cpu_architecture( #endif /* CPUINFO_ARCH_ARM */ case ' ': case '\t': - /* Ignore whitespace at the end */ + /* Ignore whitespace at the end + */ break; default: - cpuinfo_log_warning("skipped unknown architectural feature '%c' for ARMv%"PRIu32, - feature, architecture); + cpuinfo_log_warning( + "skipped unknown architectural feature '%c' for ARMv%" PRIu32, + feature, + architecture); break; } } } else { - cpuinfo_log_warning("CPU architecture %.*s in /proc/cpuinfo is ignored due to invalid value (0)", - (int) cpu_architecture_length, cpu_architecture_start); + cpuinfo_log_warning( + "CPU architecture %.*s in /proc/cpuinfo is ignored due to invalid value (0)", + (int)cpu_architecture_length, + cpu_architecture_start); } } @@ -391,9 +405,12 @@ static void parse_cpu_architecture( midr_architecture = UINT32_C(0x7); /* ARMv6 */ break; case 5: - if ((processor->architecture_flags & CPUINFO_ARM_LINUX_ARCH_TEJ) == CPUINFO_ARM_LINUX_ARCH_TEJ) { + if ((processor->architecture_flags & CPUINFO_ARM_LINUX_ARCH_TEJ) == + CPUINFO_ARM_LINUX_ARCH_TEJ) { midr_architecture = UINT32_C(0x6); /* ARMv5TEJ */ - } else if ((processor->architecture_flags & CPUINFO_ARM_LINUX_ARCH_TE) == CPUINFO_ARM_LINUX_ARCH_TE) { + } else if ( + (processor->architecture_flags & CPUINFO_ARM_LINUX_ARCH_TE) == + CPUINFO_ARM_LINUX_ARCH_TE) { midr_architecture = UINT32_C(0x5); /* ARMv5TE */ } else { midr_architecture = UINT32_C(0x4); /* ARMv5T */ @@ -407,9 +424,8 @@ static void parse_cpu_architecture( static void parse_cpu_part( const char* cpu_part_start, const char* cpu_part_end, - struct cpuinfo_arm_linux_processor processor[restrict static 1]) -{ - const size_t cpu_part_length = (size_t) (cpu_part_end - cpu_part_start); + struct cpuinfo_arm_linux_processor processor[restrict static 1]) { + const size_t cpu_part_length = (size_t)(cpu_part_end - cpu_part_start); /* * CPU part should contain hex prefix (0x) and one to three hex digits. @@ -419,32 +435,42 @@ static void parse_cpu_part( * Main ID Register (MIDR) assigns only a 12-bit value for CPU part. */ if (cpu_part_length < 3 || cpu_part_length > 5) { - cpuinfo_log_warning("CPU part %.*s in /proc/cpuinfo is ignored due to unexpected length (%zu)", - (int) cpu_part_length, cpu_part_start, cpu_part_length); + cpuinfo_log_warning( + "CPU part %.*s in /proc/cpuinfo is ignored due to unexpected length (%zu)", + (int)cpu_part_length, + cpu_part_start, + cpu_part_length); return; } /* Verify the presence of hex prefix */ if (cpu_part_start[0] != '0' || cpu_part_start[1] != 'x') { - cpuinfo_log_warning("CPU part %.*s in /proc/cpuinfo is ignored due to lack of 0x prefix", - (int) cpu_part_length, cpu_part_start); + cpuinfo_log_warning( + "CPU part %.*s in /proc/cpuinfo is ignored due to lack of 0x prefix", + (int)cpu_part_length, + cpu_part_start); return; } - /* Verify that characters after hex prefix are hexadecimal digits and decode them */ + /* Verify that characters after hex prefix are hexadecimal digits and + * decode them */ uint32_t cpu_part = 0; for (const char* digit_ptr = cpu_part_start + 2; digit_ptr != cpu_part_end; digit_ptr++) { const char digit_char = *digit_ptr; uint32_t digit; if (digit_char >= '0' && digit_char <= '9') { digit = digit_char - '0'; - } else if ((uint32_t) (digit_char - 'A') < 6) { + } else if ((uint32_t)(digit_char - 'A') < 6) { digit = 10 + (digit_char - 'A'); - } else if ((uint32_t) (digit_char - 'a') < 6) { + } else if ((uint32_t)(digit_char - 'a') < 6) { digit = 10 + (digit_char - 'a'); } else { - cpuinfo_log_warning("CPU part %.*s in /proc/cpuinfo is ignored due to unexpected non-hex character %c at offset %zu", - (int) cpu_part_length, cpu_part_start, digit_char, (size_t) (digit_ptr - cpu_part_start)); + cpuinfo_log_warning( + "CPU part %.*s in /proc/cpuinfo is ignored due to unexpected non-hex character %c at offset %zu", + (int)cpu_part_length, + cpu_part_start, + digit_char, + (size_t)(digit_ptr - cpu_part_start)); return; } cpu_part = cpu_part * 16 + digit; @@ -457,8 +483,7 @@ static void parse_cpu_part( static void parse_cpu_implementer( const char* cpu_implementer_start, const char* cpu_implementer_end, - struct cpuinfo_arm_linux_processor processor[restrict static 1]) -{ + struct cpuinfo_arm_linux_processor processor[restrict static 1]) { const size_t cpu_implementer_length = cpu_implementer_end - cpu_implementer_start; /* @@ -466,39 +491,50 @@ static void parse_cpu_implementer( * I have never seen single hex digit as a value of this field, * but I don't think it is impossible in future. * Value can not contain more than two hex digits since - * Main ID Register (MIDR) assigns only an 8-bit value for CPU implementer. + * Main ID Register (MIDR) assigns only an 8-bit value for CPU + * implementer. */ switch (cpu_implementer_length) { case 3: case 4: break; default: - cpuinfo_log_warning("CPU implementer %.*s in /proc/cpuinfo is ignored due to unexpected length (%zu)", - (int) cpu_implementer_length, cpu_implementer_start, cpu_implementer_length); - return; + cpuinfo_log_warning( + "CPU implementer %.*s in /proc/cpuinfo is ignored due to unexpected length (%zu)", + (int)cpu_implementer_length, + cpu_implementer_start, + cpu_implementer_length); + return; } /* Verify the presence of hex prefix */ if (cpu_implementer_start[0] != '0' || cpu_implementer_start[1] != 'x') { - cpuinfo_log_warning("CPU implementer %.*s in /proc/cpuinfo is ignored due to lack of 0x prefix", - (int) cpu_implementer_length, cpu_implementer_start); + cpuinfo_log_warning( + "CPU implementer %.*s in /proc/cpuinfo is ignored due to lack of 0x prefix", + (int)cpu_implementer_length, + cpu_implementer_start); return; } - /* Verify that characters after hex prefix are hexadecimal digits and decode them */ + /* Verify that characters after hex prefix are hexadecimal digits and + * decode them */ uint32_t cpu_implementer = 0; for (const char* digit_ptr = cpu_implementer_start + 2; digit_ptr != cpu_implementer_end; digit_ptr++) { const char digit_char = *digit_ptr; uint32_t digit; if (digit_char >= '0' && digit_char <= '9') { digit = digit_char - '0'; - } else if ((uint32_t) (digit_char - 'A') < 6) { + } else if ((uint32_t)(digit_char - 'A') < 6) { digit = 10 + (digit_char - 'A'); - } else if ((uint32_t) (digit_char - 'a') < 6) { + } else if ((uint32_t)(digit_char - 'a') < 6) { digit = 10 + (digit_char - 'a'); } else { - cpuinfo_log_warning("CPU implementer %.*s in /proc/cpuinfo is ignored due to unexpected non-hex character '%c' at offset %zu", - (int) cpu_implementer_length, cpu_implementer_start, digit_char, (size_t) (digit_ptr - cpu_implementer_start)); + cpuinfo_log_warning( + "CPU implementer %.*s in /proc/cpuinfo is ignored due to unexpected non-hex character '%c' at offset %zu", + (int)cpu_implementer_length, + cpu_implementer_start, + digit_char, + (size_t)(digit_ptr - cpu_implementer_start)); return; } cpu_implementer = cpu_implementer * 16 + digit; @@ -511,8 +547,7 @@ static void parse_cpu_implementer( static void parse_cpu_variant( const char* cpu_variant_start, const char* cpu_variant_end, - struct cpuinfo_arm_linux_processor processor[restrict static 1]) -{ + struct cpuinfo_arm_linux_processor processor[restrict static 1]) { const size_t cpu_variant_length = cpu_variant_end - cpu_variant_start; /* @@ -521,30 +556,39 @@ static void parse_cpu_variant( * Main ID Register (MIDR) assigns only a 4-bit value for CPU variant. */ if (cpu_variant_length != 3) { - cpuinfo_log_warning("CPU variant %.*s in /proc/cpuinfo is ignored due to unexpected length (%zu)", - (int) cpu_variant_length, cpu_variant_start, cpu_variant_length); + cpuinfo_log_warning( + "CPU variant %.*s in /proc/cpuinfo is ignored due to unexpected length (%zu)", + (int)cpu_variant_length, + cpu_variant_start, + cpu_variant_length); return; } /* Skip if there is no hex prefix (0x) */ if (cpu_variant_start[0] != '0' || cpu_variant_start[1] != 'x') { - cpuinfo_log_warning("CPU variant %.*s in /proc/cpuinfo is ignored due to lack of 0x prefix", - (int) cpu_variant_length, cpu_variant_start); + cpuinfo_log_warning( + "CPU variant %.*s in /proc/cpuinfo is ignored due to lack of 0x prefix", + (int)cpu_variant_length, + cpu_variant_start); return; } - /* Check if the value after hex prefix is indeed a hex digit and decode it. */ + /* Check if the value after hex prefix is indeed a hex digit and decode + * it. */ const char digit_char = cpu_variant_start[2]; uint32_t cpu_variant; - if ((uint32_t) (digit_char - '0') < 10) { - cpu_variant = (uint32_t) (digit_char - '0'); - } else if ((uint32_t) (digit_char - 'A') < 6) { - cpu_variant = 10 + (uint32_t) (digit_char - 'A'); - } else if ((uint32_t) (digit_char - 'a') < 6) { - cpu_variant = 10 + (uint32_t) (digit_char - 'a'); + if ((uint32_t)(digit_char - '0') < 10) { + cpu_variant = (uint32_t)(digit_char - '0'); + } else if ((uint32_t)(digit_char - 'A') < 6) { + cpu_variant = 10 + (uint32_t)(digit_char - 'A'); + } else if ((uint32_t)(digit_char - 'a') < 6) { + cpu_variant = 10 + (uint32_t)(digit_char - 'a'); } else { - cpuinfo_log_warning("CPU variant %.*s in /proc/cpuinfo is ignored due to unexpected non-hex character '%c'", - (int) cpu_variant_length, cpu_variant_start, digit_char); + cpuinfo_log_warning( + "CPU variant %.*s in /proc/cpuinfo is ignored due to unexpected non-hex character '%c'", + (int)cpu_variant_length, + cpu_variant_start, + digit_char); return; } @@ -555,17 +599,20 @@ static void parse_cpu_variant( static void parse_cpu_revision( const char* cpu_revision_start, const char* cpu_revision_end, - struct cpuinfo_arm_linux_processor processor[restrict static 1]) -{ + struct cpuinfo_arm_linux_processor processor[restrict static 1]) { uint32_t cpu_revision = 0; for (const char* digit_ptr = cpu_revision_start; digit_ptr != cpu_revision_end; digit_ptr++) { - const uint32_t digit = (uint32_t) (*digit_ptr - '0'); + const uint32_t digit = (uint32_t)(*digit_ptr - '0'); - /* Verify that the character in CPU revision is a decimal digit */ + /* Verify that the character in CPU revision is a decimal digit + */ if (digit >= 10) { - cpuinfo_log_warning("CPU revision %.*s in /proc/cpuinfo is ignored due to unexpected non-digit character '%c' at offset %zu", - (int) (cpu_revision_end - cpu_revision_start), cpu_revision_start, - *digit_ptr, (size_t) (digit_ptr - cpu_revision_start)); + cpuinfo_log_warning( + "CPU revision %.*s in /proc/cpuinfo is ignored due to unexpected non-digit character '%c' at offset %zu", + (int)(cpu_revision_end - cpu_revision_start), + cpu_revision_start, + *digit_ptr, + (size_t)(digit_ptr - cpu_revision_start)); return; } @@ -598,15 +645,18 @@ static void parse_cache_number( const char* number_name, uint32_t number_ptr[restrict static 1], uint32_t flags[restrict static 1], - uint32_t number_mask) -{ + uint32_t number_mask) { uint32_t number = 0; for (const char* digit_ptr = number_start; digit_ptr != number_end; digit_ptr++) { const uint32_t digit = *digit_ptr - '0'; if (digit >= 10) { - cpuinfo_log_warning("%s %.*s in /proc/cpuinfo is ignored due to unexpected non-digit character '%c' at offset %zu", - number_name, (int) (number_end - number_start), number_start, - *digit_ptr, (size_t) (digit_ptr - number_start)); + cpuinfo_log_warning( + "%s %.*s in /proc/cpuinfo is ignored due to unexpected non-digit character '%c' at offset %zu", + number_name, + (int)(number_end - number_start), + number_start, + *digit_ptr, + (size_t)(digit_ptr - number_start)); return; } @@ -614,11 +664,15 @@ static void parse_cache_number( } if (number == 0) { - cpuinfo_log_warning("%s %.*s in /proc/cpuinfo is ignored due to invalid value of zero reported by the kernel", - number_name, (int) (number_end - number_start), number_start); + cpuinfo_log_warning( + "%s %.*s in /proc/cpuinfo is ignored due to invalid value of zero reported by the kernel", + number_name, + (int)(number_end - number_start), + number_start); } - /* If the number specifies a cache line size, verify that is a reasonable power of 2 */ + /* If the number specifies a cache line size, verify that is a + * reasonable power of 2 */ if (number_mask & CPUINFO_ARM_LINUX_VALID_CACHE_LINE) { switch (number) { case 16: @@ -627,8 +681,11 @@ static void parse_cache_number( case 128: break; default: - cpuinfo_log_warning("invalid %s %.*s is ignored: a value of 16, 32, 64, or 128 expected", - number_name, (int) (number_end - number_start), number_start); + cpuinfo_log_warning( + "invalid %s %.*s is ignored: a value of 16, 32, 64, or 128 expected", + number_name, + (int)(number_end - number_start), + number_start); } } @@ -658,12 +715,9 @@ struct proc_cpuinfo_parser_state { * processor : 1 * BogoMIPS : 1363.33 * - * Features : swp half thumb fastmult vfp edsp thumbee neon vfpv3 - * CPU implementer : 0x41 - * CPU architecture: 7 - * CPU variant : 0x2 - * CPU part : 0xc09 - * CPU revision : 10 + * Features : swp half thumb fastmult vfp edsp thumbee neon + *vfpv3 CPU implementer : 0x41 CPU architecture: 7 CPU variant : 0x2 CPU + *part : 0xc09 CPU revision : 10 * * Hardware : OMAP4 Panda board * Revision : 0020 @@ -673,8 +727,7 @@ static bool parse_line( const char* line_start, const char* line_end, struct proc_cpuinfo_parser_state state[restrict static 1], - uint64_t line_number) -{ + uint64_t line_number) { /* Empty line. Skip. */ if (line_start == line_end) { return true; @@ -689,8 +742,10 @@ static bool parse_line( } /* Skip line if no ':' separator was found. */ if (separator == line_end) { - cpuinfo_log_info("Line %.*s in /proc/cpuinfo is ignored: key/value separator ':' not found", - (int) (line_end - line_start), line_start); + cpuinfo_log_info( + "Line %.*s in /proc/cpuinfo is ignored: key/value separator ':' not found", + (int)(line_end - line_start), + line_start); return true; } @@ -703,8 +758,10 @@ static bool parse_line( } /* Skip line if key contains nothing but spaces. */ if (key_end == line_start) { - cpuinfo_log_info("Line %.*s in /proc/cpuinfo is ignored: key contains only spaces", - (int) (line_end - line_start), line_start); + cpuinfo_log_info( + "Line %.*s in /proc/cpuinfo is ignored: key contains only spaces", + (int)(line_end - line_start), + line_start); return true; } @@ -717,8 +774,10 @@ static bool parse_line( } /* Value part contains nothing but spaces. Skip line. */ if (value_start == line_end) { - cpuinfo_log_info("Line %.*s in /proc/cpuinfo is ignored: value contains only spaces", - (int) (line_end - line_start), line_start); + cpuinfo_log_info( + "Line %.*s in /proc/cpuinfo is ignored: value contains only spaces", + (int)(line_end - line_start), + line_start); return true; } @@ -730,10 +789,10 @@ static bool parse_line( } } - const uint32_t processor_index = state->processor_index; + const uint32_t processor_index = state->processor_index; const uint32_t max_processors_count = state->max_processors_count; struct cpuinfo_arm_linux_processor* processors = state->processors; - struct cpuinfo_arm_linux_processor* processor = &state->dummy_processor; + struct cpuinfo_arm_linux_processor* processor = &state->dummy_processor; if (processor_index < max_processors_count) { processor = &processors[processor_index]; } @@ -745,21 +804,37 @@ static bool parse_line( /* Usually contains just zeros, useless */ #if CPUINFO_ARCH_ARM } else if (memcmp(line_start, "I size", key_length) == 0) { - parse_cache_number(value_start, value_end, - "instruction cache size", &processor->proc_cpuinfo_cache.i_size, - &processor->flags, CPUINFO_ARM_LINUX_VALID_ICACHE_SIZE); + parse_cache_number( + value_start, + value_end, + "instruction cache size", + &processor->proc_cpuinfo_cache.i_size, + &processor->flags, + CPUINFO_ARM_LINUX_VALID_ICACHE_SIZE); } else if (memcmp(line_start, "I sets", key_length) == 0) { - parse_cache_number(value_start, value_end, - "instruction cache sets", &processor->proc_cpuinfo_cache.i_sets, - &processor->flags, CPUINFO_ARM_LINUX_VALID_ICACHE_SETS); + parse_cache_number( + value_start, + value_end, + "instruction cache sets", + &processor->proc_cpuinfo_cache.i_sets, + &processor->flags, + CPUINFO_ARM_LINUX_VALID_ICACHE_SETS); } else if (memcmp(line_start, "D size", key_length) == 0) { - parse_cache_number(value_start, value_end, - "data cache size", &processor->proc_cpuinfo_cache.d_size, - &processor->flags, CPUINFO_ARM_LINUX_VALID_DCACHE_SIZE); + parse_cache_number( + value_start, + value_end, + "data cache size", + &processor->proc_cpuinfo_cache.d_size, + &processor->flags, + CPUINFO_ARM_LINUX_VALID_DCACHE_SIZE); } else if (memcmp(line_start, "D sets", key_length) == 0) { - parse_cache_number(value_start, value_end, - "data cache sets", &processor->proc_cpuinfo_cache.d_sets, - &processor->flags, CPUINFO_ARM_LINUX_VALID_DCACHE_SETS); + parse_cache_number( + value_start, + value_end, + "data cache sets", + &processor->proc_cpuinfo_cache.d_sets, + &processor->flags, + CPUINFO_ARM_LINUX_VALID_DCACHE_SETS); #endif /* CPUINFO_ARCH_ARM */ } else { goto unknown; @@ -768,13 +843,21 @@ static bool parse_line( #if CPUINFO_ARCH_ARM case 7: if (memcmp(line_start, "I assoc", key_length) == 0) { - parse_cache_number(value_start, value_end, - "instruction cache associativity", &processor->proc_cpuinfo_cache.i_assoc, - &processor->flags, CPUINFO_ARM_LINUX_VALID_ICACHE_WAYS); + parse_cache_number( + value_start, + value_end, + "instruction cache associativity", + &processor->proc_cpuinfo_cache.i_assoc, + &processor->flags, + CPUINFO_ARM_LINUX_VALID_ICACHE_WAYS); } else if (memcmp(line_start, "D assoc", key_length) == 0) { - parse_cache_number(value_start, value_end, - "data cache associativity", &processor->proc_cpuinfo_cache.d_assoc, - &processor->flags, CPUINFO_ARM_LINUX_VALID_DCACHE_WAYS); + parse_cache_number( + value_start, + value_end, + "data cache associativity", + &processor->proc_cpuinfo_cache.d_assoc, + &processor->flags, + CPUINFO_ARM_LINUX_VALID_DCACHE_WAYS); } else { goto unknown; } @@ -792,25 +875,31 @@ static bool parse_line( if (value_length > CPUINFO_HARDWARE_VALUE_MAX) { cpuinfo_log_info( "length of Hardware value \"%.*s\" in /proc/cpuinfo exceeds limit (%d): truncating to the limit", - (int) value_length, value_start, CPUINFO_HARDWARE_VALUE_MAX); + (int)value_length, + value_start, + CPUINFO_HARDWARE_VALUE_MAX); value_length = CPUINFO_HARDWARE_VALUE_MAX; } else { state->hardware[value_length] = '\0'; } memcpy(state->hardware, value_start, value_length); - cpuinfo_log_debug("parsed /proc/cpuinfo Hardware = \"%.*s\"", (int) value_length, value_start); + cpuinfo_log_debug( + "parsed /proc/cpuinfo Hardware = \"%.*s\"", (int)value_length, value_start); } else if (memcmp(line_start, "Revision", key_length) == 0) { size_t value_length = value_end - value_start; if (value_length > CPUINFO_REVISION_VALUE_MAX) { cpuinfo_log_info( "length of Revision value \"%.*s\" in /proc/cpuinfo exceeds limit (%d): truncating to the limit", - (int) value_length, value_start, CPUINFO_REVISION_VALUE_MAX); + (int)value_length, + value_start, + CPUINFO_REVISION_VALUE_MAX); value_length = CPUINFO_REVISION_VALUE_MAX; } else { state->revision[value_length] = '\0'; } memcpy(state->revision, value_start, value_length); - cpuinfo_log_debug("parsed /proc/cpuinfo Revision = \"%.*s\"", (int) value_length, value_start); + cpuinfo_log_debug( + "parsed /proc/cpuinfo Revision = \"%.*s\"", (int)value_length, value_start); } else { goto unknown; } @@ -819,28 +908,39 @@ static bool parse_line( if (memcmp(line_start, "processor", key_length) == 0) { const uint32_t new_processor_index = parse_processor_number(value_start, value_end); if (new_processor_index < processor_index) { - /* Strange: decreasing processor number */ + /* Strange: decreasing processor number + */ cpuinfo_log_warning( - "unexpectedly low processor number %"PRIu32" following processor %"PRIu32" in /proc/cpuinfo", - new_processor_index, processor_index); + "unexpectedly low processor number %" PRIu32 + " following processor %" PRIu32 " in /proc/cpuinfo", + new_processor_index, + processor_index); } else if (new_processor_index > processor_index + 1) { - /* Strange, but common: skipped processor $(processor_index + 1) */ + /* Strange, but common: skipped + * processor $(processor_index + 1) */ cpuinfo_log_info( - "unexpectedly high processor number %"PRIu32" following processor %"PRIu32" in /proc/cpuinfo", - new_processor_index, processor_index); + "unexpectedly high processor number %" PRIu32 + " following processor %" PRIu32 " in /proc/cpuinfo", + new_processor_index, + processor_index); } if (new_processor_index < max_processors_count) { - /* Record that the processor was mentioned in /proc/cpuinfo */ + /* Record that the processor was + * mentioned in /proc/cpuinfo */ processors[new_processor_index].flags |= CPUINFO_ARM_LINUX_VALID_PROCESSOR; } else { /* Log and ignore processor */ - cpuinfo_log_warning("processor %"PRIu32" in /proc/cpuinfo is ignored: index exceeds system limit %"PRIu32, - new_processor_index, max_processors_count - 1); + cpuinfo_log_warning( + "processor %" PRIu32 + " in /proc/cpuinfo is ignored: index exceeds system limit %" PRIu32, + new_processor_index, + max_processors_count - 1); } state->processor_index = new_processor_index; return true; } else if (memcmp(line_start, "Processor", key_length) == 0) { - /* TODO: parse to fix misreported architecture, similar to Android's cpufeatures */ + /* TODO: parse to fix misreported architecture, + * similar to Android's cpufeatures */ } else { goto unknown; } @@ -862,13 +962,21 @@ static bool parse_line( #if CPUINFO_ARCH_ARM case 13: if (memcmp(line_start, "I line length", key_length) == 0) { - parse_cache_number(value_start, value_end, - "instruction cache line size", &processor->proc_cpuinfo_cache.i_line_length, - &processor->flags, CPUINFO_ARM_LINUX_VALID_ICACHE_LINE); + parse_cache_number( + value_start, + value_end, + "instruction cache line size", + &processor->proc_cpuinfo_cache.i_line_length, + &processor->flags, + CPUINFO_ARM_LINUX_VALID_ICACHE_LINE); } else if (memcmp(line_start, "D line length", key_length) == 0) { - parse_cache_number(value_start, value_end, - "data cache line size", &processor->proc_cpuinfo_cache.d_line_length, - &processor->flags, CPUINFO_ARM_LINUX_VALID_DCACHE_LINE); + parse_cache_number( + value_start, + value_end, + "data cache line size", + &processor->proc_cpuinfo_cache.d_line_length, + &processor->flags, + CPUINFO_ARM_LINUX_VALID_DCACHE_LINE); } else { goto unknown; } @@ -892,8 +1000,7 @@ static bool parse_line( break; default: unknown: - cpuinfo_log_debug("unknown /proc/cpuinfo key: %.*s", (int) key_length, line_start); - + cpuinfo_log_debug("unknown /proc/cpuinfo key: %.*s", (int)key_length, line_start); } return true; } @@ -902,8 +1009,7 @@ bool cpuinfo_arm_linux_parse_proc_cpuinfo( char hardware[restrict static CPUINFO_HARDWARE_VALUE_MAX], char revision[restrict static CPUINFO_REVISION_VALUE_MAX], uint32_t max_processors_count, - struct cpuinfo_arm_linux_processor processors[restrict static max_processors_count]) -{ + struct cpuinfo_arm_linux_processor processors[restrict static max_processors_count]) { hardware[0] = '\0'; struct proc_cpuinfo_parser_state state = { .hardware = hardware, @@ -912,6 +1018,6 @@ bool cpuinfo_arm_linux_parse_proc_cpuinfo( .max_processors_count = max_processors_count, .processors = processors, }; - return cpuinfo_linux_parse_multiline_file("/proc/cpuinfo", BUFFER_SIZE, - (cpuinfo_line_callback) parse_line, &state); + return cpuinfo_linux_parse_multiline_file( + "/proc/cpuinfo", BUFFER_SIZE, (cpuinfo_line_callback)parse_line, &state); } diff --git a/src/arm/linux/hwcap.c b/src/arm/linux/hwcap.c index 984ab43c..e836548d 100644 --- a/src/arm/linux/hwcap.c +++ b/src/arm/linux/hwcap.c @@ -1,163 +1,154 @@ #include #include -#include -#include -#include -#include -#include #include #include +#include +#include +#include +#include +#include #if CPUINFO_MOCK - #include +#include #endif -#include #include +#include #include -#if CPUINFO_ARCH_ARM64 || CPUINFO_ARCH_ARM && \ - defined(__GLIBC__) && defined(__GLIBC_MINOR__) && (__GLIBC__ > 2 || __GLIBC__ == 2 && __GLIBC_MINOR__ >= 16) - #include +#if CPUINFO_ARCH_ARM64 || \ + CPUINFO_ARCH_ARM && defined(__GLIBC__) && defined(__GLIBC_MINOR__) && \ + (__GLIBC__ > 2 || __GLIBC__ == 2 && __GLIBC_MINOR__ >= 16) +#include #else - #define AT_HWCAP 16 - #define AT_HWCAP2 26 +#define AT_HWCAP 16 +#define AT_HWCAP2 26 +#endif + +#if CPUINFO_MOCK +static uint32_t mock_hwcap = 0; +void cpuinfo_set_hwcap(uint32_t hwcap) { + mock_hwcap = hwcap; +} + +static uint32_t mock_hwcap2 = 0; +void cpuinfo_set_hwcap2(uint32_t hwcap2) { + mock_hwcap2 = hwcap2; +} #endif +#if CPUINFO_ARCH_ARM +typedef unsigned long (*getauxval_function_t)(unsigned long); +bool cpuinfo_arm_linux_hwcap_from_getauxval(uint32_t hwcap[restrict static 1], uint32_t hwcap2[restrict static 1]) { #if CPUINFO_MOCK - static uint32_t mock_hwcap = 0; - void cpuinfo_set_hwcap(uint32_t hwcap) { - mock_hwcap = hwcap; + *hwcap = mock_hwcap; + *hwcap2 = mock_hwcap2; + return true; +#elif defined(__ANDROID__) + /* Android: dynamically check if getauxval is supported */ + void* libc = NULL; + getauxval_function_t getauxval = NULL; + + dlerror(); + libc = dlopen("libc.so", RTLD_LAZY); + if (libc == NULL) { + cpuinfo_log_warning("failed to load libc.so: %s", dlerror()); + goto cleanup; } - static uint32_t mock_hwcap2 = 0; - void cpuinfo_set_hwcap2(uint32_t hwcap2) { - mock_hwcap2 = hwcap2; + getauxval = (getauxval_function_t)dlsym(libc, "getauxval"); + if (getauxval == NULL) { + cpuinfo_log_info("failed to locate getauxval in libc.so: %s", dlerror()); + goto cleanup; } -#endif + *hwcap = getauxval(AT_HWCAP); + *hwcap2 = getauxval(AT_HWCAP2); -#if CPUINFO_ARCH_ARM - typedef unsigned long (*getauxval_function_t)(unsigned long); - - bool cpuinfo_arm_linux_hwcap_from_getauxval( - uint32_t hwcap[restrict static 1], - uint32_t hwcap2[restrict static 1]) - { - #if CPUINFO_MOCK - *hwcap = mock_hwcap; - *hwcap2 = mock_hwcap2; - return true; - #elif defined(__ANDROID__) - /* Android: dynamically check if getauxval is supported */ - void* libc = NULL; - getauxval_function_t getauxval = NULL; - - dlerror(); - libc = dlopen("libc.so", RTLD_LAZY); - if (libc == NULL) { - cpuinfo_log_warning("failed to load libc.so: %s", dlerror()); - goto cleanup; - } +cleanup: + if (libc != NULL) { + dlclose(libc); + libc = NULL; + } + return getauxval != NULL; +#elif defined(__GLIBC__) && defined(__GLIBC_MINOR__) && (__GLIBC__ > 2 || __GLIBC__ == 2 && __GLIBC_MINOR__ >= 16) + /* GNU/Linux: getauxval is supported since glibc-2.16 */ + *hwcap = getauxval(AT_HWCAP); + *hwcap2 = getauxval(AT_HWCAP2); + return true; +#else + return false; +#endif +} + +#ifdef __ANDROID__ +bool cpuinfo_arm_linux_hwcap_from_procfs(uint32_t hwcap[restrict static 1], uint32_t hwcap2[restrict static 1]) { +#if CPUINFO_MOCK + *hwcap = mock_hwcap; + *hwcap2 = mock_hwcap2; + return true; +#else + uint32_t hwcaps[2] = {0, 0}; + bool result = false; + int file = -1; + + file = open("/proc/self/auxv", O_RDONLY); + if (file == -1) { + cpuinfo_log_warning("failed to open /proc/self/auxv: %s", strerror(errno)); + goto cleanup; + } - getauxval = (getauxval_function_t) dlsym(libc, "getauxval"); - if (getauxval == NULL) { - cpuinfo_log_info("failed to locate getauxval in libc.so: %s", dlerror()); + ssize_t bytes_read; + do { + Elf32_auxv_t elf_auxv; + bytes_read = read(file, &elf_auxv, sizeof(Elf32_auxv_t)); + if (bytes_read < 0) { + cpuinfo_log_warning("failed to read /proc/self/auxv: %s", strerror(errno)); + goto cleanup; + } else if (bytes_read > 0) { + if (bytes_read == sizeof(elf_auxv)) { + switch (elf_auxv.a_type) { + case AT_HWCAP: + hwcaps[0] = (uint32_t)elf_auxv.a_un.a_val; + break; + case AT_HWCAP2: + hwcaps[1] = (uint32_t)elf_auxv.a_un.a_val; + break; + } + } else { + cpuinfo_log_warning( + "failed to read %zu bytes from /proc/self/auxv: %zu bytes available", + sizeof(elf_auxv), + (size_t)bytes_read); goto cleanup; } + } + } while (bytes_read == sizeof(Elf32_auxv_t)); - *hwcap = getauxval(AT_HWCAP); - *hwcap2 = getauxval(AT_HWCAP2); + /* Success, commit results */ + *hwcap = hwcaps[0]; + *hwcap2 = hwcaps[1]; + result = true; - cleanup: - if (libc != NULL) { - dlclose(libc); - libc = NULL; - } - return getauxval != NULL; - #elif defined(__GLIBC__) && defined(__GLIBC_MINOR__) && (__GLIBC__ > 2 || __GLIBC__ == 2 && __GLIBC_MINOR__ >= 16) - /* GNU/Linux: getauxval is supported since glibc-2.16 */ - *hwcap = getauxval(AT_HWCAP); - *hwcap2 = getauxval(AT_HWCAP2); - return true; - #else - return false; - #endif +cleanup: + if (file != -1) { + close(file); + file = -1; } - - #ifdef __ANDROID__ - bool cpuinfo_arm_linux_hwcap_from_procfs( - uint32_t hwcap[restrict static 1], - uint32_t hwcap2[restrict static 1]) - { - #if CPUINFO_MOCK - *hwcap = mock_hwcap; - *hwcap2 = mock_hwcap2; - return true; - #else - uint32_t hwcaps[2] = { 0, 0 }; - bool result = false; - int file = -1; - - file = open("/proc/self/auxv", O_RDONLY); - if (file == -1) { - cpuinfo_log_warning("failed to open /proc/self/auxv: %s", strerror(errno)); - goto cleanup; - } - - ssize_t bytes_read; - do { - Elf32_auxv_t elf_auxv; - bytes_read = read(file, &elf_auxv, sizeof(Elf32_auxv_t)); - if (bytes_read < 0) { - cpuinfo_log_warning("failed to read /proc/self/auxv: %s", strerror(errno)); - goto cleanup; - } else if (bytes_read > 0) { - if (bytes_read == sizeof(elf_auxv)) { - switch (elf_auxv.a_type) { - case AT_HWCAP: - hwcaps[0] = (uint32_t) elf_auxv.a_un.a_val; - break; - case AT_HWCAP2: - hwcaps[1] = (uint32_t) elf_auxv.a_un.a_val; - break; - } - } else { - cpuinfo_log_warning( - "failed to read %zu bytes from /proc/self/auxv: %zu bytes available", - sizeof(elf_auxv), (size_t) bytes_read); - goto cleanup; - } - } - } while (bytes_read == sizeof(Elf32_auxv_t)); - - /* Success, commit results */ - *hwcap = hwcaps[0]; - *hwcap2 = hwcaps[1]; - result = true; - - cleanup: - if (file != -1) { - close(file); - file = -1; - } - return result; - #endif - } - #endif /* __ANDROID__ */ + return result; +#endif +} +#endif /* __ANDROID__ */ #elif CPUINFO_ARCH_ARM64 - void cpuinfo_arm_linux_hwcap_from_getauxval( - uint32_t hwcap[restrict static 1], - uint32_t hwcap2[restrict static 1]) - { - #if CPUINFO_MOCK - *hwcap = mock_hwcap; - *hwcap2 = mock_hwcap2; - #else - *hwcap = (uint32_t) getauxval(AT_HWCAP); - *hwcap2 = (uint32_t) getauxval(AT_HWCAP2); - return ; - #endif - } +void cpuinfo_arm_linux_hwcap_from_getauxval(uint32_t hwcap[restrict static 1], uint32_t hwcap2[restrict static 1]) { +#if CPUINFO_MOCK + *hwcap = mock_hwcap; + *hwcap2 = mock_hwcap2; +#else + *hwcap = (uint32_t)getauxval(AT_HWCAP); + *hwcap2 = (uint32_t)getauxval(AT_HWCAP2); + return; +#endif +} #endif diff --git a/src/arm/linux/init.c b/src/arm/linux/init.c index 2501f39c..988f05aa 100644 --- a/src/arm/linux/init.c +++ b/src/arm/linux/init.c @@ -1,23 +1,22 @@ -#include #include +#include #include #include -#include #include +#include #if defined(__ANDROID__) - #include +#include #endif #include #include -#include #include #include +#include +struct cpuinfo_arm_isa cpuinfo_isa = {0}; -struct cpuinfo_arm_isa cpuinfo_isa = { 0 }; - -static struct cpuinfo_package package = { { 0 } }; +static struct cpuinfo_package package = {{0}}; static inline bool bitmask_all(uint32_t bitfield, uint32_t mask) { return (bitfield & mask) == mask; @@ -32,16 +31,19 @@ static inline int cmp(uint32_t a, uint32_t b) { } static bool cluster_siblings_parser( - uint32_t processor, uint32_t siblings_start, uint32_t siblings_end, - struct cpuinfo_arm_linux_processor* processors) -{ + uint32_t processor, + uint32_t siblings_start, + uint32_t siblings_end, + struct cpuinfo_arm_linux_processor* processors) { processors[processor].flags |= CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER; uint32_t package_leader_id = processors[processor].package_leader_id; for (uint32_t sibling = siblings_start; sibling < siblings_end; sibling++) { if (!bitmask_all(processors[sibling].flags, CPUINFO_LINUX_FLAG_VALID)) { - cpuinfo_log_info("invalid processor %"PRIu32" reported as a sibling for processor %"PRIu32, - sibling, processor); + cpuinfo_log_info( + "invalid processor %" PRIu32 " reported as a sibling for processor %" PRIu32, + sibling, + processor); continue; } @@ -60,14 +62,14 @@ static bool cluster_siblings_parser( } static int cmp_arm_linux_processor(const void* ptr_a, const void* ptr_b) { - const struct cpuinfo_arm_linux_processor* processor_a = (const struct cpuinfo_arm_linux_processor*) ptr_a; - const struct cpuinfo_arm_linux_processor* processor_b = (const struct cpuinfo_arm_linux_processor*) ptr_b; + const struct cpuinfo_arm_linux_processor* processor_a = (const struct cpuinfo_arm_linux_processor*)ptr_a; + const struct cpuinfo_arm_linux_processor* processor_b = (const struct cpuinfo_arm_linux_processor*)ptr_b; /* Move usable processors towards the start of the array */ const bool usable_a = bitmask_all(processor_a->flags, CPUINFO_LINUX_FLAG_VALID); const bool usable_b = bitmask_all(processor_b->flags, CPUINFO_LINUX_FLAG_VALID); if (usable_a != usable_b) { - return (int) usable_b - (int) usable_a; + return (int)usable_b - (int)usable_a; } /* Compare based on core type (e.g. Cortex-A57 < Cortex-A53) */ @@ -95,7 +97,8 @@ static int cmp_arm_linux_processor(const void* ptr_a, const void* ptr_b) { return cluster_a > cluster_b ? -1 : 1; } - /* Compare based on system processor id (i.e. processor 0 < processor 1) */ + /* Compare based on system processor id (i.e. processor 0 < processor 1) + */ const uint32_t id_a = processor_a->system_processor_id; const uint32_t id_b = processor_b->system_processor_id; return cmp(id_a, id_b); @@ -116,14 +119,13 @@ void cpuinfo_arm_linux_init(void) { uint32_t* linux_cpu_to_uarch_index_map = NULL; const uint32_t max_processors_count = cpuinfo_linux_get_max_processors_count(); - cpuinfo_log_debug("system maximum processors count: %"PRIu32, max_processors_count); + cpuinfo_log_debug("system maximum processors count: %" PRIu32, max_processors_count); - const uint32_t max_possible_processors_count = 1 + - cpuinfo_linux_get_max_possible_processor(max_processors_count); - cpuinfo_log_debug("maximum possible processors count: %"PRIu32, max_possible_processors_count); - const uint32_t max_present_processors_count = 1 + - cpuinfo_linux_get_max_present_processor(max_processors_count); - cpuinfo_log_debug("maximum present processors count: %"PRIu32, max_present_processors_count); + const uint32_t max_possible_processors_count = + 1 + cpuinfo_linux_get_max_possible_processor(max_processors_count); + cpuinfo_log_debug("maximum possible processors count: %" PRIu32, max_possible_processors_count); + const uint32_t max_present_processors_count = 1 + cpuinfo_linux_get_max_present_processor(max_processors_count); + cpuinfo_log_debug("maximum present processors count: %" PRIu32, max_present_processors_count); uint32_t valid_processor_mask = 0; uint32_t arm_linux_processors_count = max_processors_count; @@ -143,7 +145,7 @@ void cpuinfo_arm_linux_init(void) { arm_linux_processors = calloc(arm_linux_processors_count, sizeof(struct cpuinfo_arm_linux_processor)); if (arm_linux_processors == NULL) { cpuinfo_log_error( - "failed to allocate %zu bytes for descriptions of %"PRIu32" ARM logical processors", + "failed to allocate %zu bytes for descriptions of %" PRIu32 " ARM logical processors", arm_linux_processors_count * sizeof(struct cpuinfo_arm_linux_processor), arm_linux_processors_count); return; @@ -151,14 +153,16 @@ void cpuinfo_arm_linux_init(void) { if (max_possible_processors_count) { cpuinfo_linux_detect_possible_processors( - arm_linux_processors_count, &arm_linux_processors->flags, + arm_linux_processors_count, + &arm_linux_processors->flags, sizeof(struct cpuinfo_arm_linux_processor), CPUINFO_LINUX_FLAG_POSSIBLE); } if (max_present_processors_count) { cpuinfo_linux_detect_present_processors( - arm_linux_processors_count, &arm_linux_processors->flags, + arm_linux_processors_count, + &arm_linux_processors->flags, sizeof(struct cpuinfo_arm_linux_processor), CPUINFO_LINUX_FLAG_PRESENT); } @@ -173,13 +177,13 @@ void cpuinfo_arm_linux_init(void) { if (!cpuinfo_arm_linux_parse_proc_cpuinfo( #if defined(__ANDROID__) - android_properties.proc_cpuinfo_hardware, + android_properties.proc_cpuinfo_hardware, #else - proc_cpuinfo_hardware, + proc_cpuinfo_hardware, #endif - proc_cpuinfo_revision, - arm_linux_processors_count, - arm_linux_processors)) { + proc_cpuinfo_revision, + arm_linux_processors_count, + arm_linux_processors)) { cpuinfo_log_error("failed to parse processor information from /proc/cpuinfo"); return; } @@ -187,45 +191,49 @@ void cpuinfo_arm_linux_init(void) { for (uint32_t i = 0; i < arm_linux_processors_count; i++) { if (bitmask_all(arm_linux_processors[i].flags, valid_processor_mask)) { arm_linux_processors[i].flags |= CPUINFO_LINUX_FLAG_VALID; - cpuinfo_log_debug("parsed processor %"PRIu32" MIDR 0x%08"PRIx32, - i, arm_linux_processors[i].midr); + cpuinfo_log_debug( + "parsed processor %" PRIu32 " MIDR 0x%08" PRIx32, i, arm_linux_processors[i].midr); } } uint32_t valid_processors = 0, last_midr = 0; - #if CPUINFO_ARCH_ARM +#if CPUINFO_ARCH_ARM uint32_t last_architecture_version = 0, last_architecture_flags = 0; - #endif +#endif for (uint32_t i = 0; i < arm_linux_processors_count; i++) { arm_linux_processors[i].system_processor_id = i; if (bitmask_all(arm_linux_processors[i].flags, CPUINFO_LINUX_FLAG_VALID)) { if (arm_linux_processors[i].flags & CPUINFO_ARM_LINUX_VALID_PROCESSOR) { /* - * Processor is in possible and present lists, and also reported in /proc/cpuinfo. - * This processor is availble for compute. + * Processor is in possible and present lists, + * and also reported in /proc/cpuinfo. This + * processor is availble for compute. */ valid_processors += 1; } else { /* - * Processor is in possible and present lists, but not reported in /proc/cpuinfo. - * This is fairly common: high-index processors can be not reported if they are offline. + * Processor is in possible and present lists, + * but not reported in /proc/cpuinfo. This is + * fairly common: high-index processors can be + * not reported if they are offline. */ - cpuinfo_log_info("processor %"PRIu32" is not listed in /proc/cpuinfo", i); + cpuinfo_log_info("processor %" PRIu32 " is not listed in /proc/cpuinfo", i); } if (bitmask_all(arm_linux_processors[i].flags, CPUINFO_ARM_LINUX_VALID_MIDR)) { last_midr = arm_linux_processors[i].midr; } - #if CPUINFO_ARCH_ARM - if (bitmask_all(arm_linux_processors[i].flags, CPUINFO_ARM_LINUX_VALID_ARCHITECTURE)) { - last_architecture_version = arm_linux_processors[i].architecture_version; - last_architecture_flags = arm_linux_processors[i].architecture_flags; - } - #endif +#if CPUINFO_ARCH_ARM + if (bitmask_all(arm_linux_processors[i].flags, CPUINFO_ARM_LINUX_VALID_ARCHITECTURE)) { + last_architecture_version = arm_linux_processors[i].architecture_version; + last_architecture_flags = arm_linux_processors[i].architecture_flags; + } +#endif } else { - /* Processor reported in /proc/cpuinfo, but not in possible and/or present lists: log and ignore */ + /* Processor reported in /proc/cpuinfo, but not in + * possible and/or present lists: log and ignore */ if (!(arm_linux_processors[i].flags & CPUINFO_ARM_LINUX_VALID_PROCESSOR)) { - cpuinfo_log_warning("invalid processor %"PRIu32" reported in /proc/cpuinfo", i); + cpuinfo_log_warning("invalid processor %" PRIu32 " reported in /proc/cpuinfo", i); } } } @@ -238,55 +246,65 @@ void cpuinfo_arm_linux_init(void) { cpuinfo_arm_linux_decode_chipset(proc_cpuinfo_hardware, proc_cpuinfo_revision, valid_processors, 0); #endif - #if CPUINFO_ARCH_ARM - uint32_t isa_features = 0, isa_features2 = 0; - #ifdef __ANDROID__ +#if CPUINFO_ARCH_ARM + uint32_t isa_features = 0, isa_features2 = 0; +#ifdef __ANDROID__ + /* + * On Android before API 20, libc.so does not provide getauxval + * function. Thus, we try to dynamically find it, or use two fallback + * mechanisms: + * 1. dlopen libc.so, and try to find getauxval + * 2. Parse /proc/self/auxv procfs file + * 3. Use features reported in /proc/cpuinfo + */ + if (!cpuinfo_arm_linux_hwcap_from_getauxval(&isa_features, &isa_features2)) { + /* getauxval can't be used, fall back to parsing /proc/self/auxv + */ + if (!cpuinfo_arm_linux_hwcap_from_procfs(&isa_features, &isa_features2)) { /* - * On Android before API 20, libc.so does not provide getauxval function. - * Thus, we try to dynamically find it, or use two fallback mechanisms: - * 1. dlopen libc.so, and try to find getauxval - * 2. Parse /proc/self/auxv procfs file - * 3. Use features reported in /proc/cpuinfo + * Reading /proc/self/auxv failed, probably due to file + * permissions. Use information from /proc/cpuinfo to + * detect ISA. + * + * If different processors report different ISA + * features, take the intersection. */ - if (!cpuinfo_arm_linux_hwcap_from_getauxval(&isa_features, &isa_features2)) { - /* getauxval can't be used, fall back to parsing /proc/self/auxv */ - if (!cpuinfo_arm_linux_hwcap_from_procfs(&isa_features, &isa_features2)) { - /* - * Reading /proc/self/auxv failed, probably due to file permissions. - * Use information from /proc/cpuinfo to detect ISA. - * - * If different processors report different ISA features, take the intersection. - */ - uint32_t processors_with_features = 0; - for (uint32_t i = 0; i < arm_linux_processors_count; i++) { - if (bitmask_all(arm_linux_processors[i].flags, CPUINFO_LINUX_FLAG_VALID | CPUINFO_ARM_LINUX_VALID_FEATURES)) { - if (processors_with_features == 0) { - isa_features = arm_linux_processors[i].features; - isa_features2 = arm_linux_processors[i].features2; - } else { - isa_features &= arm_linux_processors[i].features; - isa_features2 &= arm_linux_processors[i].features2; - } - processors_with_features += 1; - } + uint32_t processors_with_features = 0; + for (uint32_t i = 0; i < arm_linux_processors_count; i++) { + if (bitmask_all( + arm_linux_processors[i].flags, + CPUINFO_LINUX_FLAG_VALID | CPUINFO_ARM_LINUX_VALID_FEATURES)) { + if (processors_with_features == 0) { + isa_features = arm_linux_processors[i].features; + isa_features2 = arm_linux_processors[i].features2; + } else { + isa_features &= arm_linux_processors[i].features; + isa_features2 &= arm_linux_processors[i].features2; } + processors_with_features += 1; } } - #else - /* On GNU/Linux getauxval is always available */ - cpuinfo_arm_linux_hwcap_from_getauxval(&isa_features, &isa_features2); - #endif - cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( - isa_features, isa_features2, - last_midr, last_architecture_version, last_architecture_flags, - &chipset, &cpuinfo_isa); - #elif CPUINFO_ARCH_ARM64 - uint32_t isa_features = 0, isa_features2 = 0; - /* getauxval is always available on ARM64 Android */ - cpuinfo_arm_linux_hwcap_from_getauxval(&isa_features, &isa_features2); - cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo( - isa_features, isa_features2, last_midr, &chipset, &cpuinfo_isa); - #endif + } + } +#else + /* On GNU/Linux getauxval is always available */ + cpuinfo_arm_linux_hwcap_from_getauxval(&isa_features, &isa_features2); +#endif + cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( + isa_features, + isa_features2, + last_midr, + last_architecture_version, + last_architecture_flags, + &chipset, + &cpuinfo_isa); +#elif CPUINFO_ARCH_ARM64 + uint32_t isa_features = 0, isa_features2 = 0; + /* getauxval is always available on ARM64 Android */ + cpuinfo_arm_linux_hwcap_from_getauxval(&isa_features, &isa_features2); + cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo( + isa_features, isa_features2, last_midr, &chipset, &cpuinfo_isa); +#endif /* Detect min/max frequency and package ID */ for (uint32_t i = 0; i < arm_linux_processors_count; i++) { @@ -322,8 +340,9 @@ void cpuinfo_arm_linux_init(void) { if (arm_linux_processors[i].flags & CPUINFO_LINUX_FLAG_PACKAGE_ID) { cpuinfo_linux_detect_core_siblings( - arm_linux_processors_count, i, - (cpuinfo_siblings_callback) cluster_siblings_parser, + arm_linux_processors_count, + i, + (cpuinfo_siblings_callback)cluster_siblings_parser, arm_linux_processors); } } @@ -331,79 +350,107 @@ void cpuinfo_arm_linux_init(void) { /* Propagate all cluster IDs */ uint32_t clustered_processors = 0; for (uint32_t i = 0; i < arm_linux_processors_count; i++) { - if (bitmask_all(arm_linux_processors[i].flags, CPUINFO_LINUX_FLAG_VALID | CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER)) { + if (bitmask_all( + arm_linux_processors[i].flags, + CPUINFO_LINUX_FLAG_VALID | CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER)) { clustered_processors += 1; const uint32_t package_leader_id = arm_linux_processors[i].package_leader_id; if (package_leader_id < i) { - arm_linux_processors[i].package_leader_id = arm_linux_processors[package_leader_id].package_leader_id; + arm_linux_processors[i].package_leader_id = + arm_linux_processors[package_leader_id].package_leader_id; } - cpuinfo_log_debug("processor %"PRIu32" clustered with processor %"PRIu32" as inferred from system siblings lists", - i, arm_linux_processors[i].package_leader_id); + cpuinfo_log_debug( + "processor %" PRIu32 " clustered with processor %" PRIu32 + " as inferred from system siblings lists", + i, + arm_linux_processors[i].package_leader_id); } } if (clustered_processors != valid_processors) { /* - * Topology information about some or all logical processors may be unavailable, for the following reasons: - * - Linux kernel is too old, or configured without support for topology information in sysfs. - * - Core is offline, and Linux kernel is configured to not report topology for offline cores. + * Topology information about some or all logical processors may + * be unavailable, for the following reasons: + * - Linux kernel is too old, or configured without support for + * topology information in sysfs. + * - Core is offline, and Linux kernel is configured to not + * report topology for offline cores. * - * In this case, we assign processors to clusters using two methods: - * - Try heuristic cluster configurations (e.g. 6-core SoC usually has 4+2 big.LITTLE configuration). - * - If heuristic failed, assign processors to core clusters in a sequential scan. + * In this case, we assign processors to clusters using two + * methods: + * - Try heuristic cluster configurations (e.g. 6-core SoC + * usually has 4+2 big.LITTLE configuration). + * - If heuristic failed, assign processors to core clusters in + * a sequential scan. */ - if (!cpuinfo_arm_linux_detect_core_clusters_by_heuristic(valid_processors, arm_linux_processors_count, arm_linux_processors)) { - cpuinfo_arm_linux_detect_core_clusters_by_sequential_scan(arm_linux_processors_count, arm_linux_processors); + if (!cpuinfo_arm_linux_detect_core_clusters_by_heuristic( + valid_processors, arm_linux_processors_count, arm_linux_processors)) { + cpuinfo_arm_linux_detect_core_clusters_by_sequential_scan( + arm_linux_processors_count, arm_linux_processors); } } cpuinfo_arm_linux_count_cluster_processors(arm_linux_processors_count, arm_linux_processors); const uint32_t cluster_count = cpuinfo_arm_linux_detect_cluster_midr( - &chipset, - arm_linux_processors_count, valid_processors, arm_linux_processors); + &chipset, arm_linux_processors_count, valid_processors, arm_linux_processors); - /* Initialize core vendor, uarch, MIDR, and frequency for every logical processor */ + /* Initialize core vendor, uarch, MIDR, and frequency for every logical + * processor */ for (uint32_t i = 0; i < arm_linux_processors_count; i++) { if (bitmask_all(arm_linux_processors[i].flags, CPUINFO_LINUX_FLAG_VALID)) { const uint32_t cluster_leader = arm_linux_processors[i].package_leader_id; if (cluster_leader == i) { - /* Cluster leader: decode core vendor and uarch */ + /* Cluster leader: decode core vendor and uarch + */ cpuinfo_arm_decode_vendor_uarch( - arm_linux_processors[cluster_leader].midr, + arm_linux_processors[cluster_leader].midr, #if CPUINFO_ARCH_ARM - !!(arm_linux_processors[cluster_leader].features & CPUINFO_ARM_LINUX_FEATURE_VFPV4), + !!(arm_linux_processors[cluster_leader].features & + CPUINFO_ARM_LINUX_FEATURE_VFPV4), #endif - &arm_linux_processors[cluster_leader].vendor, - &arm_linux_processors[cluster_leader].uarch); + &arm_linux_processors[cluster_leader].vendor, + &arm_linux_processors[cluster_leader].uarch); } else { - /* Cluster non-leader: copy vendor, uarch, MIDR, and frequency from cluster leader */ + /* Cluster non-leader: copy vendor, uarch, MIDR, + * and frequency from cluster leader */ arm_linux_processors[i].flags |= arm_linux_processors[cluster_leader].flags & (CPUINFO_ARM_LINUX_VALID_MIDR | CPUINFO_LINUX_FLAG_MAX_FREQUENCY); arm_linux_processors[i].midr = arm_linux_processors[cluster_leader].midr; arm_linux_processors[i].vendor = arm_linux_processors[cluster_leader].vendor; arm_linux_processors[i].uarch = arm_linux_processors[cluster_leader].uarch; - arm_linux_processors[i].max_frequency = arm_linux_processors[cluster_leader].max_frequency; + arm_linux_processors[i].max_frequency = + arm_linux_processors[cluster_leader].max_frequency; } } } for (uint32_t i = 0; i < arm_linux_processors_count; i++) { if (bitmask_all(arm_linux_processors[i].flags, CPUINFO_LINUX_FLAG_VALID)) { - cpuinfo_log_debug("post-analysis processor %"PRIu32": MIDR %08"PRIx32" frequency %"PRIu32, - i, arm_linux_processors[i].midr, arm_linux_processors[i].max_frequency); + cpuinfo_log_debug( + "post-analysis processor %" PRIu32 ": MIDR %08" PRIx32 " frequency %" PRIu32, + i, + arm_linux_processors[i].midr, + arm_linux_processors[i].max_frequency); } } - qsort(arm_linux_processors, arm_linux_processors_count, - sizeof(struct cpuinfo_arm_linux_processor), cmp_arm_linux_processor); + qsort(arm_linux_processors, + arm_linux_processors_count, + sizeof(struct cpuinfo_arm_linux_processor), + cmp_arm_linux_processor); for (uint32_t i = 0; i < arm_linux_processors_count; i++) { if (bitmask_all(arm_linux_processors[i].flags, CPUINFO_LINUX_FLAG_VALID)) { - cpuinfo_log_debug("post-sort processor %"PRIu32": system id %"PRIu32" MIDR %08"PRIx32" frequency %"PRIu32, - i, arm_linux_processors[i].system_processor_id, arm_linux_processors[i].midr, arm_linux_processors[i].max_frequency); + cpuinfo_log_debug( + "post-sort processor %" PRIu32 ": system id %" PRIu32 " MIDR %08" PRIx32 + " frequency %" PRIu32, + i, + arm_linux_processors[i].system_processor_id, + arm_linux_processors[i].midr, + arm_linux_processors[i].max_frequency); } } @@ -422,8 +469,10 @@ void cpuinfo_arm_linux_init(void) { /* * Assumptions: * - No SMP (i.e. each core supports only one hardware thread). - * - Level 1 instruction and data caches are private to the core clusters. - * - Level 2 and level 3 cache is shared between cores in the same cluster. + * - Level 1 instruction and data caches are private to the core + * clusters. + * - Level 2 and level 3 cache is shared between cores in the same + * cluster. */ cpuinfo_arm_chipset_to_string(&chipset, package.name); package.processor_count = valid_processors; @@ -432,66 +481,84 @@ void cpuinfo_arm_linux_init(void) { processors = calloc(valid_processors, sizeof(struct cpuinfo_processor)); if (processors == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" logical processors", - valid_processors * sizeof(struct cpuinfo_processor), valid_processors); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " logical processors", + valid_processors * sizeof(struct cpuinfo_processor), + valid_processors); goto cleanup; } cores = calloc(valid_processors, sizeof(struct cpuinfo_core)); if (cores == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" cores", - valid_processors * sizeof(struct cpuinfo_core), valid_processors); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " cores", + valid_processors * sizeof(struct cpuinfo_core), + valid_processors); goto cleanup; } clusters = calloc(cluster_count, sizeof(struct cpuinfo_cluster)); if (clusters == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" core clusters", - cluster_count * sizeof(struct cpuinfo_cluster), cluster_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " core clusters", + cluster_count * sizeof(struct cpuinfo_cluster), + cluster_count); goto cleanup; } uarchs = calloc(uarchs_count, sizeof(struct cpuinfo_uarch_info)); if (uarchs == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" microarchitectures", - uarchs_count * sizeof(struct cpuinfo_uarch_info), uarchs_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " microarchitectures", + uarchs_count * sizeof(struct cpuinfo_uarch_info), + uarchs_count); goto cleanup; } linux_cpu_to_processor_map = calloc(arm_linux_processors_count, sizeof(struct cpuinfo_processor*)); if (linux_cpu_to_processor_map == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for %"PRIu32" logical processor mapping entries", - arm_linux_processors_count * sizeof(struct cpuinfo_processor*), arm_linux_processors_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for %" PRIu32 " logical processor mapping entries", + arm_linux_processors_count * sizeof(struct cpuinfo_processor*), + arm_linux_processors_count); goto cleanup; } linux_cpu_to_core_map = calloc(arm_linux_processors_count, sizeof(struct cpuinfo_core*)); if (linux_cpu_to_core_map == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for %"PRIu32" core mapping entries", - arm_linux_processors_count * sizeof(struct cpuinfo_core*), arm_linux_processors_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for %" PRIu32 " core mapping entries", + arm_linux_processors_count * sizeof(struct cpuinfo_core*), + arm_linux_processors_count); goto cleanup; } if (uarchs_count > 1) { linux_cpu_to_uarch_index_map = calloc(arm_linux_processors_count, sizeof(uint32_t)); if (linux_cpu_to_uarch_index_map == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for %"PRIu32" uarch index mapping entries", - arm_linux_processors_count * sizeof(uint32_t), arm_linux_processors_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for %" PRIu32 " uarch index mapping entries", + arm_linux_processors_count * sizeof(uint32_t), + arm_linux_processors_count); goto cleanup; } } l1i = calloc(valid_processors, sizeof(struct cpuinfo_cache)); if (l1i == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L1I caches", - valid_processors * sizeof(struct cpuinfo_cache), valid_processors); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L1I caches", + valid_processors * sizeof(struct cpuinfo_cache), + valid_processors); goto cleanup; } l1d = calloc(valid_processors, sizeof(struct cpuinfo_cache)); if (l1d == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L1D caches", - valid_processors * sizeof(struct cpuinfo_cache), valid_processors); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L1D caches", + valid_processors * sizeof(struct cpuinfo_cache), + valid_processors); goto cleanup; } @@ -500,7 +567,7 @@ void cpuinfo_arm_linux_init(void) { if (bitmask_all(arm_linux_processors[i].flags, CPUINFO_LINUX_FLAG_VALID)) { if (uarchs_index == 0 || arm_linux_processors[i].uarch != last_uarch) { last_uarch = arm_linux_processors[i].uarch; - uarchs[uarchs_index] = (struct cpuinfo_uarch_info) { + uarchs[uarchs_index] = (struct cpuinfo_uarch_info){ .uarch = arm_linux_processors[i].uarch, .midr = arm_linux_processors[i].midr, }; @@ -518,7 +585,7 @@ void cpuinfo_arm_linux_init(void) { for (uint32_t i = 0; i < valid_processors; i++) { if (arm_linux_processors[i].package_leader_id == arm_linux_processors[i].system_processor_id) { cluster_id += 1; - clusters[cluster_id] = (struct cpuinfo_cluster) { + clusters[cluster_id] = (struct cpuinfo_cluster){ .processor_start = i, .processor_count = arm_linux_processors[i].package_processor_count, .core_start = i, @@ -535,7 +602,7 @@ void cpuinfo_arm_linux_init(void) { processors[i].core = cores + i; processors[i].cluster = clusters + cluster_id; processors[i].package = &package; - processors[i].linux_id = (int) arm_linux_processors[i].system_processor_id; + processors[i].linux_id = (int)arm_linux_processors[i].system_processor_id; processors[i].cache.l1i = l1i + i; processors[i].cache.l1d = l1d + i; linux_cpu_to_processor_map[arm_linux_processors[i].system_processor_id] = &processors[i]; @@ -555,7 +622,7 @@ void cpuinfo_arm_linux_init(void) { arm_linux_processors[i].uarch_index; } - struct cpuinfo_cache temp_l2 = { 0 }, temp_l3 = { 0 }; + struct cpuinfo_cache temp_l2 = {0}, temp_l3 = {0}; cpuinfo_arm_decode_cache( arm_linux_processors[i].uarch, arm_linux_processors[i].package_processor_count, @@ -563,38 +630,40 @@ void cpuinfo_arm_linux_init(void) { &chipset, cluster_id, arm_linux_processors[i].architecture_version, - &l1i[i], &l1d[i], &temp_l2, &temp_l3); + &l1i[i], + &l1d[i], + &temp_l2, + &temp_l3); l1i[i].processor_start = l1d[i].processor_start = i; l1i[i].processor_count = l1d[i].processor_count = 1; - #if CPUINFO_ARCH_ARM - /* L1I reported in /proc/cpuinfo overrides defaults */ - if (bitmask_all(arm_linux_processors[i].flags, CPUINFO_ARM_LINUX_VALID_ICACHE)) { - l1i[i] = (struct cpuinfo_cache) { - .size = arm_linux_processors[i].proc_cpuinfo_cache.i_size, - .associativity = arm_linux_processors[i].proc_cpuinfo_cache.i_assoc, - .sets = arm_linux_processors[i].proc_cpuinfo_cache.i_sets, - .partitions = 1, - .line_size = arm_linux_processors[i].proc_cpuinfo_cache.i_line_length - }; - } - /* L1D reported in /proc/cpuinfo overrides defaults */ - if (bitmask_all(arm_linux_processors[i].flags, CPUINFO_ARM_LINUX_VALID_DCACHE)) { - l1d[i] = (struct cpuinfo_cache) { - .size = arm_linux_processors[i].proc_cpuinfo_cache.d_size, - .associativity = arm_linux_processors[i].proc_cpuinfo_cache.d_assoc, - .sets = arm_linux_processors[i].proc_cpuinfo_cache.d_sets, - .partitions = 1, - .line_size = arm_linux_processors[i].proc_cpuinfo_cache.d_line_length - }; - } - #endif +#if CPUINFO_ARCH_ARM + /* L1I reported in /proc/cpuinfo overrides defaults */ + if (bitmask_all(arm_linux_processors[i].flags, CPUINFO_ARM_LINUX_VALID_ICACHE)) { + l1i[i] = (struct cpuinfo_cache){ + .size = arm_linux_processors[i].proc_cpuinfo_cache.i_size, + .associativity = arm_linux_processors[i].proc_cpuinfo_cache.i_assoc, + .sets = arm_linux_processors[i].proc_cpuinfo_cache.i_sets, + .partitions = 1, + .line_size = arm_linux_processors[i].proc_cpuinfo_cache.i_line_length}; + } + /* L1D reported in /proc/cpuinfo overrides defaults */ + if (bitmask_all(arm_linux_processors[i].flags, CPUINFO_ARM_LINUX_VALID_DCACHE)) { + l1d[i] = (struct cpuinfo_cache){ + .size = arm_linux_processors[i].proc_cpuinfo_cache.d_size, + .associativity = arm_linux_processors[i].proc_cpuinfo_cache.d_assoc, + .sets = arm_linux_processors[i].proc_cpuinfo_cache.d_sets, + .partitions = 1, + .line_size = arm_linux_processors[i].proc_cpuinfo_cache.d_line_length}; + } +#endif if (temp_l3.size != 0) { /* * Assumptions: * - L2 is private to each core * - L3 is shared by cores in the same cluster - * - If cores in different clusters report the same L3, it is shared between all cores. + * - If cores in different clusters report the same L3, + * it is shared between all cores. */ l2_count += 1; if (arm_linux_processors[i].package_leader_id == arm_linux_processors[i].system_processor_id) { @@ -602,17 +671,22 @@ void cpuinfo_arm_linux_init(void) { big_l3_size = temp_l3.size; l3_count = 1; } else if (temp_l3.size != big_l3_size) { - /* If some cores have different L3 size, L3 is not shared between all cores */ + /* If some cores have different L3 size, + * L3 is not shared between all cores */ shared_l3 = false; l3_count += 1; } } } else { - /* If some cores don't have L3 cache, L3 is not shared between all cores */ + /* If some cores don't have L3 cache, L3 is not shared + * between all cores + */ shared_l3 = false; if (temp_l2.size != 0) { - /* Assume L2 is shared by cores in the same cluster */ - if (arm_linux_processors[i].package_leader_id == arm_linux_processors[i].system_processor_id) { + /* Assume L2 is shared by cores in the same + * cluster */ + if (arm_linux_processors[i].package_leader_id == + arm_linux_processors[i].system_processor_id) { l2_count += 1; } } @@ -622,16 +696,20 @@ void cpuinfo_arm_linux_init(void) { if (l2_count != 0) { l2 = calloc(l2_count, sizeof(struct cpuinfo_cache)); if (l2 == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L2 caches", - l2_count * sizeof(struct cpuinfo_cache), l2_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L2 caches", + l2_count * sizeof(struct cpuinfo_cache), + l2_count); goto cleanup; } if (l3_count != 0) { l3 = calloc(l3_count, sizeof(struct cpuinfo_cache)); if (l3 == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L3 caches", - l3_count * sizeof(struct cpuinfo_cache), l3_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L3 caches", + l3_count * sizeof(struct cpuinfo_cache), + l3_count); goto cleanup; } } @@ -644,7 +722,7 @@ void cpuinfo_arm_linux_init(void) { cluster_id++; } - struct cpuinfo_cache dummy_l1i, dummy_l1d, temp_l2 = { 0 }, temp_l3 = { 0 }; + struct cpuinfo_cache dummy_l1i, dummy_l1d, temp_l2 = {0}, temp_l3 = {0}; cpuinfo_arm_decode_cache( arm_linux_processors[i].uarch, arm_linux_processors[i].package_processor_count, @@ -652,23 +730,27 @@ void cpuinfo_arm_linux_init(void) { &chipset, cluster_id, arm_linux_processors[i].architecture_version, - &dummy_l1i, &dummy_l1d, &temp_l2, &temp_l3); + &dummy_l1i, + &dummy_l1d, + &temp_l2, + &temp_l3); if (temp_l3.size != 0) { /* * Assumptions: * - L2 is private to each core * - L3 is shared by cores in the same cluster - * - If cores in different clusters report the same L3, it is shared between all cores. + * - If cores in different clusters report the same L3, + * it is shared between all cores. */ l2_index += 1; - l2[l2_index] = (struct cpuinfo_cache) { - .size = temp_l2.size, - .associativity = temp_l2.associativity, - .sets = temp_l2.sets, - .partitions = 1, - .line_size = temp_l2.line_size, - .flags = temp_l2.flags, + l2[l2_index] = (struct cpuinfo_cache){ + .size = temp_l2.size, + .associativity = temp_l2.associativity, + .sets = temp_l2.sets, + .partitions = 1, + .line_size = temp_l2.line_size, + .flags = temp_l2.flags, .processor_start = i, .processor_count = 1, }; @@ -676,16 +758,17 @@ void cpuinfo_arm_linux_init(void) { if (arm_linux_processors[i].package_leader_id == arm_linux_processors[i].system_processor_id) { l3_index += 1; if (l3_index < l3_count) { - l3[l3_index] = (struct cpuinfo_cache) { - .size = temp_l3.size, - .associativity = temp_l3.associativity, - .sets = temp_l3.sets, - .partitions = 1, - .line_size = temp_l3.line_size, - .flags = temp_l3.flags, + l3[l3_index] = (struct cpuinfo_cache){ + .size = temp_l3.size, + .associativity = temp_l3.associativity, + .sets = temp_l3.sets, + .partitions = 1, + .line_size = temp_l3.line_size, + .flags = temp_l3.flags, .processor_start = i, - .processor_count = - shared_l3 ? valid_processors : arm_linux_processors[i].package_processor_count, + .processor_count = shared_l3 + ? valid_processors + : arm_linux_processors[i].package_processor_count, }; } } @@ -698,13 +781,13 @@ void cpuinfo_arm_linux_init(void) { /* Assume L2 is shared by cores in the same cluster */ if (arm_linux_processors[i].package_leader_id == arm_linux_processors[i].system_processor_id) { l2_index += 1; - l2[l2_index] = (struct cpuinfo_cache) { - .size = temp_l2.size, - .associativity = temp_l2.associativity, - .sets = temp_l2.sets, - .partitions = 1, - .line_size = temp_l2.line_size, - .flags = temp_l2.flags, + l2[l2_index] = (struct cpuinfo_cache){ + .size = temp_l2.size, + .associativity = temp_l2.associativity, + .sets = temp_l2.sets, + .partitions = 1, + .line_size = temp_l2.line_size, + .flags = temp_l2.flags, .processor_start = i, .processor_count = arm_linux_processors[i].package_processor_count, }; @@ -721,8 +804,8 @@ void cpuinfo_arm_linux_init(void) { cpuinfo_uarchs = uarchs; cpuinfo_cache[cpuinfo_cache_level_1i] = l1i; cpuinfo_cache[cpuinfo_cache_level_1d] = l1d; - cpuinfo_cache[cpuinfo_cache_level_2] = l2; - cpuinfo_cache[cpuinfo_cache_level_3] = l3; + cpuinfo_cache[cpuinfo_cache_level_2] = l2; + cpuinfo_cache[cpuinfo_cache_level_3] = l3; cpuinfo_processors_count = valid_processors; cpuinfo_cores_count = valid_processors; @@ -731,8 +814,8 @@ void cpuinfo_arm_linux_init(void) { cpuinfo_uarchs_count = uarchs_count; cpuinfo_cache_count[cpuinfo_cache_level_1i] = valid_processors; cpuinfo_cache_count[cpuinfo_cache_level_1d] = valid_processors; - cpuinfo_cache_count[cpuinfo_cache_level_2] = l2_count; - cpuinfo_cache_count[cpuinfo_cache_level_3] = l3_count; + cpuinfo_cache_count[cpuinfo_cache_level_2] = l2_count; + cpuinfo_cache_count[cpuinfo_cache_level_3] = l3_count; cpuinfo_max_cache_size = cpuinfo_arm_compute_max_cache_size(&processors[0]); cpuinfo_linux_cpu_max = arm_linux_processors_count; diff --git a/src/arm/linux/midr.c b/src/arm/linux/midr.c index 0d8f03fa..10db2788 100644 --- a/src/arm/linux/midr.c +++ b/src/arm/linux/midr.c @@ -1,20 +1,19 @@ -#include #include +#include #include #include -#include #include +#include #if defined(__ANDROID__) - #include +#include #endif #include #include -#include +#include #include #include -#include - +#include #define CLUSTERS_MAX 3 @@ -22,7 +21,8 @@ static inline bool bitmask_all(uint32_t bitfield, uint32_t mask) { return (bitfield & mask) == mask; } -/* Description of core clusters configuration in a chipset (identified by series and model number) */ +/* Description of core clusters configuration in a chipset (identified by series + * and model number) */ struct cluster_config { /* Number of cores (logical processors) */ uint8_t cores; @@ -36,29 +36,36 @@ struct cluster_config { * Number of cores in each cluster: # - Symmetric configurations: [0] = # cores * - big.LITTLE configurations: [0] = # LITTLE cores, [1] = # big cores - * - Max.Med.Min configurations: [0] = # Min cores, [1] = # Med cores, [2] = # Max cores + * - Max.Med.Min configurations: [0] = # Min cores, [1] = # Med cores, + [2] = # Max cores */ uint8_t cluster_cores[CLUSTERS_MAX]; /* * MIDR of cores in each cluster: * - Symmetric configurations: [0] = core MIDR - * - big.LITTLE configurations: [0] = LITTLE core MIDR, [1] = big core MIDR - * - Max.Med.Min configurations: [0] = Min core MIDR, [1] = Med core MIDR, [2] = Max core MIDR + * - big.LITTLE configurations: [0] = LITTLE core MIDR, [1] = big core + * MIDR + * - Max.Med.Min configurations: [0] = Min core MIDR, [1] = Med core + * MIDR, [2] = Max core MIDR */ uint32_t cluster_midr[CLUSTERS_MAX]; }; /* - * The list of chipsets where MIDR may not be unambigiously decoded at least on some devices. - * The typical reasons for impossibility to decoded MIDRs are buggy kernels, which either do not report all MIDR - * information (e.g. on ATM7029 kernel doesn't report CPU Part), or chipsets have more than one type of cores - * (i.e. 4x Cortex-A53 + 4x Cortex-A53 is out) and buggy kernels report MIDR information only about some cores - * in /proc/cpuinfo (either only online cores, or only the core that reads /proc/cpuinfo). On these kernels/chipsets, - * it is not possible to detect all core types by just parsing /proc/cpuinfo, so we use chipset name and this table to - * find their MIDR (and thus microarchitecture, cache, etc). + * The list of chipsets where MIDR may not be unambigiously decoded at least on + * some devices. The typical reasons for impossibility to decoded MIDRs are + * buggy kernels, which either do not report all MIDR information (e.g. on + * ATM7029 kernel doesn't report CPU Part), or chipsets have more than one type + * of cores (i.e. 4x Cortex-A53 + 4x Cortex-A53 is out) and buggy kernels report + * MIDR information only about some cores in /proc/cpuinfo (either only online + * cores, or only the core that reads /proc/cpuinfo). On these kernels/chipsets, + * it is not possible to detect all core types by just parsing /proc/cpuinfo, so + * we use chipset name and this table to find their MIDR (and thus + * microarchitecture, cache, etc). * - * Note: not all chipsets with heterogeneous multiprocessing need an entry in this table. The following HMP - * chipsets always list information about all cores in /proc/cpuinfo: + * Note: not all chipsets with heterogeneous multiprocessing need an entry in + * this table. The following HMP chipsets always list information about all + * cores in /proc/cpuinfo: * * - Snapdragon 660 * - Snapdragon 820 (MSM8996) @@ -67,446 +74,510 @@ struct cluster_config { * - Exynos 8895 * - Kirin 960 * - * As these are all new processors, there is hope that this table won't uncontrollably grow over time. + * As these are all new processors, there is hope that this table won't + * uncontrollably grow over time. */ -static const struct cluster_config cluster_configs[] = { +static const struct cluster_config + cluster_configs[] = + { #if CPUINFO_ARCH_ARM - { - /* - * MSM8916 (Snapdragon 410): 4x Cortex-A53 - * Some AArch32 phones use non-standard /proc/cpuinfo format. - */ - .cores = 4, - .series = cpuinfo_arm_chipset_series_qualcomm_msm, - .model = UINT16_C(8916), - .clusters = 1, - .cluster_cores = { - [0] = 4, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FD030), - }, - }, - { - /* - * MSM8939 (Snapdragon 615): 4x Cortex-A53 + 4x Cortex-A53 - * Some AArch32 phones use non-standard /proc/cpuinfo format. - */ - .cores = 8, - .series = cpuinfo_arm_chipset_series_qualcomm_msm, - .model = UINT16_C(8939), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 4, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FD034), - [1] = UINT32_C(0x410FD034), - }, - }, + { + /* + * MSM8916 (Snapdragon 410): 4x Cortex-A53 + * Some AArch32 phones use non-standard /proc/cpuinfo format. + */ + .cores = 4, + .series = cpuinfo_arm_chipset_series_qualcomm_msm, + .model = UINT16_C(8916), + .clusters = 1, + .cluster_cores = + { + [0] = 4, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FD030), + }, + }, + { + /* + * MSM8939 (Snapdragon 615): 4x Cortex-A53 + 4x Cortex-A53 + * Some AArch32 phones use non-standard /proc/cpuinfo format. + */ + .cores = 8, + .series = cpuinfo_arm_chipset_series_qualcomm_msm, + .model = UINT16_C(8939), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 4, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FD034), + [1] = UINT32_C(0x410FD034), + }, + }, #endif - { - /* MSM8956 (Snapdragon 650): 2x Cortex-A72 + 4x Cortex-A53 */ - .cores = 6, - .series = cpuinfo_arm_chipset_series_qualcomm_msm, - .model = UINT16_C(8956), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 2, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FD034), - [1] = UINT32_C(0x410FD080), - }, - }, - { - /* MSM8976/MSM8976PRO (Snapdragon 652/653): 4x Cortex-A72 + 4x Cortex-A53 */ - .cores = 8, - .series = cpuinfo_arm_chipset_series_qualcomm_msm, - .model = UINT16_C(8976), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 4, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FD034), - [1] = UINT32_C(0x410FD080), - }, - }, - { - /* MSM8992 (Snapdragon 808): 2x Cortex-A57 + 4x Cortex-A53 */ - .cores = 6, - .series = cpuinfo_arm_chipset_series_qualcomm_msm, - .model = UINT16_C(8992), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 2, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FD033), - [1] = UINT32_C(0x411FD072), - }, - }, - { - /* MSM8994/MSM8994V (Snapdragon 810): 4x Cortex-A57 + 4x Cortex-A53 */ - .cores = 8, - .series = cpuinfo_arm_chipset_series_qualcomm_msm, - .model = UINT16_C(8994), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 4, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FD032), - [1] = UINT32_C(0x411FD071), - }, - }, + { + /* MSM8956 (Snapdragon 650): 2x Cortex-A72 + 4x Cortex-A53 */ + .cores = 6, + .series = cpuinfo_arm_chipset_series_qualcomm_msm, + .model = UINT16_C(8956), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 2, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FD034), + [1] = UINT32_C(0x410FD080), + }, + }, + { + /* MSM8976/MSM8976PRO (Snapdragon 652/653): 4x Cortex-A72 + 4x + Cortex-A53 */ + .cores = 8, + .series = cpuinfo_arm_chipset_series_qualcomm_msm, + .model = UINT16_C(8976), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 4, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FD034), + [1] = UINT32_C(0x410FD080), + }, + }, + { + /* MSM8992 (Snapdragon 808): 2x Cortex-A57 + 4x Cortex-A53 */ + .cores = 6, + .series = cpuinfo_arm_chipset_series_qualcomm_msm, + .model = UINT16_C(8992), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 2, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FD033), + [1] = UINT32_C(0x411FD072), + }, + }, + { + /* MSM8994/MSM8994V (Snapdragon 810): 4x Cortex-A57 + 4x + Cortex-A53 */ + .cores = 8, + .series = cpuinfo_arm_chipset_series_qualcomm_msm, + .model = UINT16_C(8994), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 4, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FD032), + [1] = UINT32_C(0x411FD071), + }, + }, #if CPUINFO_ARCH_ARM - { - /* Exynos 5422: 4x Cortex-A15 + 4x Cortex-A7 */ - .cores = 8, - .series = cpuinfo_arm_chipset_series_samsung_exynos, - .model = UINT16_C(5422), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 4, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FC073), - [1] = UINT32_C(0x412FC0F3), - }, - }, - { - /* Exynos 5430: 4x Cortex-A15 + 4x Cortex-A7 */ - .cores = 8, - .series = cpuinfo_arm_chipset_series_samsung_exynos, - .model = UINT16_C(5430), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 4, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FC074), - [1] = UINT32_C(0x413FC0F3), - }, - }, + { + /* Exynos 5422: 4x Cortex-A15 + 4x Cortex-A7 */ + .cores = 8, + .series = cpuinfo_arm_chipset_series_samsung_exynos, + .model = UINT16_C(5422), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 4, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FC073), + [1] = UINT32_C(0x412FC0F3), + }, + }, + { + /* Exynos 5430: 4x Cortex-A15 + 4x Cortex-A7 */ + .cores = 8, + .series = cpuinfo_arm_chipset_series_samsung_exynos, + .model = UINT16_C(5430), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 4, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FC074), + [1] = UINT32_C(0x413FC0F3), + }, + }, #endif /* CPUINFO_ARCH_ARM */ - { - /* Exynos 5433: 4x Cortex-A57 + 4x Cortex-A53 */ - .cores = 8, - .series = cpuinfo_arm_chipset_series_samsung_exynos, - .model = UINT16_C(5433), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 4, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FD031), - [1] = UINT32_C(0x411FD070), - }, - }, - { - /* Exynos 7420: 4x Cortex-A57 + 4x Cortex-A53 */ - .cores = 8, - .series = cpuinfo_arm_chipset_series_samsung_exynos, - .model = UINT16_C(7420), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 4, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FD032), - [1] = UINT32_C(0x411FD070), - }, - }, - { - /* Exynos 8890: 4x Exynos M1 + 4x Cortex-A53 */ - .cores = 8, - .series = cpuinfo_arm_chipset_series_samsung_exynos, - .model = UINT16_C(8890), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 4, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FD034), - [1] = UINT32_C(0x531F0011), - }, - }, + { + /* Exynos 5433: 4x Cortex-A57 + 4x Cortex-A53 */ + .cores = 8, + .series = cpuinfo_arm_chipset_series_samsung_exynos, + .model = UINT16_C(5433), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 4, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FD031), + [1] = UINT32_C(0x411FD070), + }, + }, + { + /* Exynos 7420: 4x Cortex-A57 + 4x Cortex-A53 */ + .cores = 8, + .series = cpuinfo_arm_chipset_series_samsung_exynos, + .model = UINT16_C(7420), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 4, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FD032), + [1] = UINT32_C(0x411FD070), + }, + }, + { + /* Exynos 8890: 4x Exynos M1 + 4x Cortex-A53 */ + .cores = 8, + .series = cpuinfo_arm_chipset_series_samsung_exynos, + .model = UINT16_C(8890), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 4, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FD034), + [1] = UINT32_C(0x531F0011), + }, + }, #if CPUINFO_ARCH_ARM - { - /* Kirin 920: 4x Cortex-A15 + 4x Cortex-A7 */ - .cores = 8, - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = UINT16_C(920), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 4, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FC075), - [1] = UINT32_C(0x413FC0F3), - }, - }, - { - /* Kirin 925: 4x Cortex-A15 + 4x Cortex-A7 */ - .cores = 8, - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = UINT16_C(925), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 4, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FC075), - [1] = UINT32_C(0x413FC0F3), - }, - }, - { - /* Kirin 928: 4x Cortex-A15 + 4x Cortex-A7 */ - .cores = 8, - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = UINT16_C(928), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 4, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FC075), - [1] = UINT32_C(0x413FC0F3), - }, - }, + { + /* Kirin 920: 4x Cortex-A15 + 4x Cortex-A7 */ + .cores = 8, + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = UINT16_C(920), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 4, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FC075), + [1] = UINT32_C(0x413FC0F3), + }, + }, + { + /* Kirin 925: 4x Cortex-A15 + 4x Cortex-A7 */ + .cores = 8, + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = UINT16_C(925), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 4, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FC075), + [1] = UINT32_C(0x413FC0F3), + }, + }, + { + /* Kirin 928: 4x Cortex-A15 + 4x Cortex-A7 */ + .cores = 8, + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = UINT16_C(928), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 4, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FC075), + [1] = UINT32_C(0x413FC0F3), + }, + }, #endif /* CPUINFO_ARCH_ARM */ - { - /* Kirin 950: 4x Cortex-A72 + 4x Cortex-A53 */ - .cores = 8, - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = UINT16_C(950), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 4, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FD034), - [1] = UINT32_C(0x410FD080), - }, - }, - { - /* Kirin 955: 4x Cortex-A72 + 4x Cortex-A53 */ - .cores = 8, - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = UINT16_C(955), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 4, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FD034), - [1] = UINT32_C(0x410FD080), - }, - }, + { + /* Kirin 950: 4x Cortex-A72 + 4x Cortex-A53 */ + .cores = 8, + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = UINT16_C(950), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 4, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FD034), + [1] = UINT32_C(0x410FD080), + }, + }, + { + /* Kirin 955: 4x Cortex-A72 + 4x Cortex-A53 */ + .cores = 8, + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = UINT16_C(955), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 4, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FD034), + [1] = UINT32_C(0x410FD080), + }, + }, #if CPUINFO_ARCH_ARM - { - /* MediaTek MT8135: 2x Cortex-A7 + 2x Cortex-A15 */ - .cores = 4, - .series = cpuinfo_arm_chipset_series_mediatek_mt, - .model = UINT16_C(8135), - .clusters = 2, - .cluster_cores = { - [0] = 2, - [1] = 2, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FC073), - [1] = UINT32_C(0x413FC0F2), - }, - }, + { + /* MediaTek MT8135: 2x Cortex-A7 + 2x Cortex-A15 */ + .cores = 4, + .series = cpuinfo_arm_chipset_series_mediatek_mt, + .model = UINT16_C(8135), + .clusters = 2, + .cluster_cores = + { + [0] = 2, + [1] = 2, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FC073), + [1] = UINT32_C(0x413FC0F2), + }, + }, #endif - { - /* MediaTek MT8173: 2x Cortex-A72 + 2x Cortex-A53 */ - .cores = 4, - .series = cpuinfo_arm_chipset_series_mediatek_mt, - .model = UINT16_C(8173), - .clusters = 2, - .cluster_cores = { - [0] = 2, - [1] = 2, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FD032), - [1] = UINT32_C(0x410FD080), - }, - }, - { - /* MediaTek MT8176: 2x Cortex-A72 + 4x Cortex-A53 */ - .cores = 6, - .series = cpuinfo_arm_chipset_series_mediatek_mt, - .model = UINT16_C(8176), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 2, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FD032), - [1] = UINT32_C(0x410FD080), - }, - }, + { + /* MediaTek MT8173: 2x Cortex-A72 + 2x Cortex-A53 */ + .cores = 4, + .series = cpuinfo_arm_chipset_series_mediatek_mt, + .model = UINT16_C(8173), + .clusters = 2, + .cluster_cores = + { + [0] = 2, + [1] = 2, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FD032), + [1] = UINT32_C(0x410FD080), + }, + }, + { + /* MediaTek MT8176: 2x Cortex-A72 + 4x Cortex-A53 */ + .cores = 6, + .series = cpuinfo_arm_chipset_series_mediatek_mt, + .model = UINT16_C(8176), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 2, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FD032), + [1] = UINT32_C(0x410FD080), + }, + }, #if CPUINFO_ARCH_ARM64 - { - /* - * MediaTek MT8735: 4x Cortex-A53 - * Some AArch64 phones use non-standard /proc/cpuinfo format. - */ - .cores = 4, - .series = cpuinfo_arm_chipset_series_mediatek_mt, - .model = UINT16_C(8735), - .clusters = 1, - .cluster_cores = { - [0] = 4, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FD034), - }, - }, + { + /* + * MediaTek MT8735: 4x Cortex-A53 + * Some AArch64 phones use non-standard /proc/cpuinfo format. + */ + .cores = 4, + .series = cpuinfo_arm_chipset_series_mediatek_mt, + .model = UINT16_C(8735), + .clusters = 1, + .cluster_cores = + { + [0] = 4, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FD034), + }, + }, #endif #if CPUINFO_ARCH_ARM - { - /* - * MediaTek MT6592: 4x Cortex-A7 + 4x Cortex-A7 - * Some phones use non-standard /proc/cpuinfo format. - */ - .cores = 4, - .series = cpuinfo_arm_chipset_series_mediatek_mt, - .model = UINT16_C(6592), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 4, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FC074), - [1] = UINT32_C(0x410FC074), - }, - }, - { - /* MediaTek MT6595: 4x Cortex-A17 + 4x Cortex-A7 */ - .cores = 8, - .series = cpuinfo_arm_chipset_series_mediatek_mt, - .model = UINT16_C(6595), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 4, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FC075), - [1] = UINT32_C(0x410FC0E0), - }, - }, + { + /* + * MediaTek MT6592: 4x Cortex-A7 + 4x Cortex-A7 + * Some phones use non-standard /proc/cpuinfo format. + */ + .cores = 4, + .series = cpuinfo_arm_chipset_series_mediatek_mt, + .model = UINT16_C(6592), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 4, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FC074), + [1] = UINT32_C(0x410FC074), + }, + }, + { + /* MediaTek MT6595: 4x Cortex-A17 + 4x Cortex-A7 */ + .cores = 8, + .series = cpuinfo_arm_chipset_series_mediatek_mt, + .model = UINT16_C(6595), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 4, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FC075), + [1] = UINT32_C(0x410FC0E0), + }, + }, #endif - { - /* MediaTek MT6797: 2x Cortex-A72 + 4x Cortex-A53 + 4x Cortex-A53 */ - .cores = 10, - .series = cpuinfo_arm_chipset_series_mediatek_mt, - .model = UINT16_C(6797), - .clusters = 3, - .cluster_cores = { - [0] = 4, - [1] = 4, - [2] = 2, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FD034), - [1] = UINT32_C(0x410FD034), - [2] = UINT32_C(0x410FD081), - }, - }, - { - /* MediaTek MT6799: 2x Cortex-A73 + 4x Cortex-A53 + 4x Cortex-A35 */ - .cores = 10, - .series = cpuinfo_arm_chipset_series_mediatek_mt, - .model = UINT16_C(6799), - .clusters = 3, - .cluster_cores = { - [0] = 4, - [1] = 4, - [2] = 2, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FD041), - [1] = UINT32_C(0x410FD034), - [2] = UINT32_C(0x410FD092), - }, - }, - { - /* Rockchip RK3399: 2x Cortex-A72 + 4x Cortex-A53 */ - .cores = 6, - .series = cpuinfo_arm_chipset_series_rockchip_rk, - .model = UINT16_C(3399), - .clusters = 2, - .cluster_cores = { - [0] = 4, - [1] = 2, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FD034), - [1] = UINT32_C(0x410FD082), - }, - }, + { + /* MediaTek MT6797: 2x Cortex-A72 + 4x Cortex-A53 + 4x + Cortex-A53 */ + .cores = 10, + .series = cpuinfo_arm_chipset_series_mediatek_mt, + .model = UINT16_C(6797), + .clusters = 3, + .cluster_cores = + { + [0] = 4, + [1] = 4, + [2] = 2, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FD034), + [1] = UINT32_C(0x410FD034), + [2] = UINT32_C(0x410FD081), + }, + }, + { + /* MediaTek MT6799: 2x Cortex-A73 + 4x Cortex-A53 + 4x + Cortex-A35 */ + .cores = 10, + .series = cpuinfo_arm_chipset_series_mediatek_mt, + .model = UINT16_C(6799), + .clusters = 3, + .cluster_cores = + { + [0] = 4, + [1] = 4, + [2] = 2, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FD041), + [1] = UINT32_C(0x410FD034), + [2] = UINT32_C(0x410FD092), + }, + }, + { + /* Rockchip RK3399: 2x Cortex-A72 + 4x Cortex-A53 */ + .cores = 6, + .series = cpuinfo_arm_chipset_series_rockchip_rk, + .model = UINT16_C(3399), + .clusters = 2, + .cluster_cores = + { + [0] = 4, + [1] = 2, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FD034), + [1] = UINT32_C(0x410FD082), + }, + }, #if CPUINFO_ARCH_ARM - { - /* Actions ATM8029: 4x Cortex-A5 - * Most devices use non-standard /proc/cpuinfo format. - */ - .cores = 4, - .series = cpuinfo_arm_chipset_series_actions_atm, - .model = UINT16_C(7029), - .clusters = 1, - .cluster_cores = { - [0] = 4, - }, - .cluster_midr = { - [0] = UINT32_C(0x410FC051), - }, - }, + { + /* Actions ATM8029: 4x Cortex-A5 + * Most devices use non-standard /proc/cpuinfo format. + */ + .cores = 4, + .series = cpuinfo_arm_chipset_series_actions_atm, + .model = UINT16_C(7029), + .clusters = 1, + .cluster_cores = + { + [0] = 4, + }, + .cluster_midr = + { + [0] = UINT32_C(0x410FC051), + }, + }, #endif }; /* - * Searches chipset name in mapping of chipset name to cores' MIDR values. If match is successful, initializes MIDR - * for all clusters' leaders with tabulated values. + * Searches chipset name in mapping of chipset name to cores' MIDR values. If + * match is successful, initializes MIDR for all clusters' leaders with + * tabulated values. * * @param[in] chipset - chipset (SoC) name information. * @param clusters_count - number of CPU core clusters detected in the SoC. - * @param cluster_leaders - indices of core clusters' leaders in the @p processors array. + * @param cluster_leaders - indices of core clusters' leaders in the @p + * processors array. * @param processors_count - number of usable logical processors in the system. - * @param[in,out] processors - array of logical processor descriptions with pre-parsed MIDR, maximum frequency, - * and decoded core cluster (package_leader_id) information. - * Upon successful return, processors[i].midr for all clusters' leaders contains the - * tabulated MIDR values. - * @param verify_midr - indicated whether the function should check that the MIDR values to be assigned to leaders of - * core clusters are consistent with known parts of their parsed values. - * Set if to false if the only MIDR value parsed from /proc/cpuinfo is for the last processor - * reported in /proc/cpuinfo and thus can't be unambiguously attributed to that processor. + * @param[in,out] processors - array of logical processor descriptions with + * pre-parsed MIDR, maximum frequency, and decoded core cluster + * (package_leader_id) information. Upon successful return, processors[i].midr + * for all clusters' leaders contains the tabulated MIDR values. + * @param verify_midr - indicated whether the function should check that the + * MIDR values to be assigned to leaders of core clusters are consistent with + * known parts of their parsed values. Set if to false if the only MIDR value + * parsed from /proc/cpuinfo is for the last processor reported in /proc/cpuinfo + * and thus can't be unambiguously attributed to that processor. * - * @retval true if the chipset was found in the mapping and core clusters' leaders initialized with MIDR values. - * @retval false if the chipset was not found in the mapping, or any consistency check failed. + * @retval true if the chipset was found in the mapping and core clusters' + * leaders initialized with MIDR values. + * @retval false if the chipset was not found in the mapping, or any consistency + * check failed. */ static bool cpuinfo_arm_linux_detect_cluster_midr_by_chipset( const struct cpuinfo_arm_chipset chipset[restrict static 1], @@ -514,20 +585,24 @@ static bool cpuinfo_arm_linux_detect_cluster_midr_by_chipset( const uint32_t cluster_leaders[restrict static CLUSTERS_MAX], uint32_t processors_count, struct cpuinfo_arm_linux_processor processors[restrict static processors_count], - bool verify_midr) -{ + bool verify_midr) { if (clusters_count <= CLUSTERS_MAX) { for (uint32_t c = 0; c < CPUINFO_COUNT_OF(cluster_configs); c++) { - if (cluster_configs[c].model == chipset->model && cluster_configs[c].series == chipset->series) { - /* Verify that the total number of cores and clusters of cores matches expectation */ - if (cluster_configs[c].cores != processors_count || cluster_configs[c].clusters != clusters_count) { + if (cluster_configs[c].model == chipset->model && + cluster_configs[c].series == chipset->series) { + /* Verify that the total number of cores and + * clusters of cores matches expectation */ + if (cluster_configs[c].cores != processors_count || + cluster_configs[c].clusters != clusters_count) { return false; } - /* Verify that core cluster configuration matches expectation */ + /* Verify that core cluster configuration + * matches expectation */ for (uint32_t cluster = 0; cluster < clusters_count; cluster++) { const uint32_t cluster_leader = cluster_leaders[cluster]; - if (cluster_configs[c].cluster_cores[cluster] != processors[cluster_leader].package_processor_count) { + if (cluster_configs[c].cluster_cores[cluster] != + processors[cluster_leader].package_processor_count) { return false; } } @@ -537,36 +612,50 @@ static bool cpuinfo_arm_linux_detect_cluster_midr_by_chipset( for (uint32_t cluster = 0; cluster < clusters_count; cluster++) { const uint32_t cluster_leader = cluster_leaders[cluster]; - /* Create a mask of known midr bits */ + /* Create a mask of known midr + * bits */ uint32_t midr_mask = 0; - if (processors[cluster_leader].flags & CPUINFO_ARM_LINUX_VALID_IMPLEMENTER) { + if (processors[cluster_leader].flags & + CPUINFO_ARM_LINUX_VALID_IMPLEMENTER) { midr_mask |= CPUINFO_ARM_MIDR_IMPLEMENTER_MASK; } - if (processors[cluster_leader].flags & CPUINFO_ARM_LINUX_VALID_VARIANT) { + if (processors[cluster_leader].flags & + CPUINFO_ARM_LINUX_VALID_VARIANT) { midr_mask |= CPUINFO_ARM_MIDR_VARIANT_MASK; } if (processors[cluster_leader].flags & CPUINFO_ARM_LINUX_VALID_PART) { midr_mask |= CPUINFO_ARM_MIDR_PART_MASK; } - if (processors[cluster_leader].flags & CPUINFO_ARM_LINUX_VALID_REVISION) { + if (processors[cluster_leader].flags & + CPUINFO_ARM_LINUX_VALID_REVISION) { midr_mask |= CPUINFO_ARM_MIDR_REVISION_MASK; } - /* Verify the bits under the mask */ - if ((processors[cluster_leader].midr ^ cluster_configs[c].cluster_midr[cluster]) & midr_mask) { - cpuinfo_log_debug("parsed MIDR of cluster %08"PRIu32" does not match tabulated value %08"PRIu32, - processors[cluster_leader].midr, cluster_configs[c].cluster_midr[cluster]); + /* Verify the bits under the + * mask */ + if ((processors[cluster_leader].midr ^ + cluster_configs[c].cluster_midr[cluster]) & + midr_mask) { + cpuinfo_log_debug( + "parsed MIDR of cluster %08" PRIu32 + " does not match tabulated value %08" PRIu32, + processors[cluster_leader].midr, + cluster_configs[c].cluster_midr[cluster]); return false; } } } - /* Assign MIDRs according to tabulated configurations */ + /* Assign MIDRs according to tabulated + * configurations */ for (uint32_t cluster = 0; cluster < clusters_count; cluster++) { const uint32_t cluster_leader = cluster_leaders[cluster]; processors[cluster_leader].midr = cluster_configs[c].cluster_midr[cluster]; processors[cluster_leader].flags |= CPUINFO_ARM_LINUX_VALID_MIDR; - cpuinfo_log_debug("cluster %"PRIu32" MIDR = 0x%08"PRIx32, cluster, cluster_configs[c].cluster_midr[cluster]); + cpuinfo_log_debug( + "cluster %" PRIu32 " MIDR = 0x%08" PRIx32, + cluster, + cluster_configs[c].cluster_midr[cluster]); } return true; } @@ -576,26 +665,35 @@ static bool cpuinfo_arm_linux_detect_cluster_midr_by_chipset( } /* - * Initializes MIDR for leaders of core clusters using a heuristic for big.LITTLE systems: - * - If the only known MIDR is for the big core cluster, guess the matching MIDR for the LITTLE cluster. - * - Estimate which of the clusters is big using maximum frequency, if known, otherwise using system processor ID. - * - Initialize the MIDR for big and LITTLE core clusters using the guesstimates values. + * Initializes MIDR for leaders of core clusters using a heuristic for + * big.LITTLE systems: + * - If the only known MIDR is for the big core cluster, guess the matching MIDR + * for the LITTLE cluster. + * - Estimate which of the clusters is big using maximum frequency, if known, + * otherwise using system processor ID. + * - Initialize the MIDR for big and LITTLE core clusters using the guesstimates + * values. * * @param clusters_count - number of CPU core clusters detected in the SoC. - * @param cluster_with_midr_count - number of CPU core clusters in the SoC with known MIDR values. - * @param last_processor_with_midr - index of the last logical processor with known MIDR in the @p processors array. - * @param cluster_leaders - indices of core clusters' leaders in the @p processors array. - * @param[in,out] processors - array of logical processor descriptions with pre-parsed MIDR, maximum frequency, - * and decoded core cluster (package_leader_id) information. - * Upon successful return, processors[i].midr for all core clusters' leaders contains - * the heuristically detected MIDR value. - * @param verify_midr - indicated whether the function should check that the MIDR values to be assigned to leaders of - * core clusters are consistent with known parts of their parsed values. - * Set if to false if the only MIDR value parsed from /proc/cpuinfo is for the last processor - * reported in /proc/cpuinfo and thus can't be unambiguously attributed to that processor. + * @param cluster_with_midr_count - number of CPU core clusters in the SoC with + * known MIDR values. + * @param last_processor_with_midr - index of the last logical processor with + * known MIDR in the @p processors array. + * @param cluster_leaders - indices of core clusters' leaders in the @p + * processors array. + * @param[in,out] processors - array of logical processor descriptions with + * pre-parsed MIDR, maximum frequency, and decoded core cluster + * (package_leader_id) information. Upon successful return, processors[i].midr + * for all core clusters' leaders contains the heuristically detected MIDR + * value. + * @param verify_midr - indicated whether the function should check that the + * MIDR values to be assigned to leaders of core clusters are consistent with + * known parts of their parsed values. Set if to false if the only MIDR value + * parsed from /proc/cpuinfo is for the last processor reported in /proc/cpuinfo + * and thus can't be unambiguously attributed to that processor. * - * @retval true if this is a big.LITTLE system with only one known MIDR and the CPU core clusters' leaders were - * initialized with MIDR values. + * @retval true if this is a big.LITTLE system with only one known MIDR and the + * CPU core clusters' leaders were initialized with MIDR values. * @retval false if this is not a big.LITTLE system. */ static bool cpuinfo_arm_linux_detect_cluster_midr_by_big_little_heuristic( @@ -604,23 +702,27 @@ static bool cpuinfo_arm_linux_detect_cluster_midr_by_big_little_heuristic( uint32_t last_processor_with_midr, const uint32_t cluster_leaders[restrict static CLUSTERS_MAX], struct cpuinfo_arm_linux_processor processors[restrict static last_processor_with_midr], - bool verify_midr) -{ + bool verify_midr) { if (clusters_count != 2 || cluster_with_midr_count != 1) { - /* Not a big.LITTLE system, or MIDR is known for both/neither clusters */ + /* Not a big.LITTLE system, or MIDR is known for both/neither + * clusters */ return false; } const uint32_t midr_flags = - (processors[processors[last_processor_with_midr].package_leader_id].flags & CPUINFO_ARM_LINUX_VALID_MIDR); + (processors[processors[last_processor_with_midr].package_leader_id].flags & + CPUINFO_ARM_LINUX_VALID_MIDR); const uint32_t big_midr = processors[processors[last_processor_with_midr].package_leader_id].midr; const uint32_t little_midr = midr_little_core_for_big(big_midr); - /* Default assumption: the first reported cluster is LITTLE cluster (this holds on most Linux kernels) */ + /* Default assumption: the first reported cluster is LITTLE cluster + * (this holds on most Linux kernels) */ uint32_t little_cluster_leader = cluster_leaders[0]; const uint32_t other_cluster_leader = cluster_leaders[1]; - /* If maximum frequency is known for both clusters, assume LITTLE cluster is the one with lower frequency */ - if (processors[little_cluster_leader].flags & processors[other_cluster_leader].flags & CPUINFO_LINUX_FLAG_MAX_FREQUENCY) { + /* If maximum frequency is known for both clusters, assume LITTLE + * cluster is the one with lower frequency */ + if (processors[little_cluster_leader].flags & processors[other_cluster_leader].flags & + CPUINFO_LINUX_FLAG_MAX_FREQUENCY) { if (processors[little_cluster_leader].max_frequency > processors[other_cluster_leader].max_frequency) { little_cluster_leader = other_cluster_leader; } @@ -650,8 +752,11 @@ static bool cpuinfo_arm_linux_detect_cluster_midr_by_big_little_heuristic( const uint32_t midr = (cluster_leader == little_cluster_leader) ? little_midr : big_midr; if ((processors[cluster_leader].midr ^ midr) & midr_mask) { cpuinfo_log_debug( - "parsed MIDR %08"PRIu32" of cluster leader %"PRIu32" is inconsistent with expected value %08"PRIu32, - processors[cluster_leader].midr, cluster_leader, midr); + "parsed MIDR %08" PRIu32 " of cluster leader %" PRIu32 + " is inconsistent with expected value %08" PRIu32, + processors[cluster_leader].midr, + cluster_leader, + midr); return false; } } @@ -665,8 +770,9 @@ static bool cpuinfo_arm_linux_detect_cluster_midr_by_big_little_heuristic( } const uint32_t midr = (cluster_leader == little_cluster_leader) ? little_midr : big_midr; - cpuinfo_log_info("assume processor %"PRIu32" to have MIDR %08"PRIx32, cluster_leader, midr); - /* To be consistent, we copy the MIDR entirely, rather than by parts */ + cpuinfo_log_info("assume processor %" PRIu32 " to have MIDR %08" PRIx32, cluster_leader, midr); + /* To be consistent, we copy the MIDR entirely, rather than by + * parts */ processors[cluster_leader].midr = midr; processors[cluster_leader].flags |= midr_flags; } @@ -675,21 +781,23 @@ static bool cpuinfo_arm_linux_detect_cluster_midr_by_big_little_heuristic( /* * Initializes MIDR for leaders of core clusters in a single sequential scan: - * - Clusters preceding the first reported MIDR value are assumed to have default MIDR value. + * - Clusters preceding the first reported MIDR value are assumed to have + * default MIDR value. * - Clusters following any reported MIDR value to have that MIDR value. * - * @param default_midr - MIDR value that will be assigned to cluster leaders preceding any reported MIDR value. - * @param processors_count - number of logical processor descriptions in the @p processors array. - * @param[in,out] processors - array of logical processor descriptions with pre-parsed MIDR, maximum frequency, - * and decoded core cluster (package_leader_id) information. - * Upon successful return, processors[i].midr for all core clusters' leaders contains - * the assigned MIDR value. + * @param default_midr - MIDR value that will be assigned to cluster leaders + * preceding any reported MIDR value. + * @param processors_count - number of logical processor descriptions in the @p + * processors array. + * @param[in,out] processors - array of logical processor descriptions with + * pre-parsed MIDR, maximum frequency, and decoded core cluster + * (package_leader_id) information. Upon successful return, processors[i].midr + * for all core clusters' leaders contains the assigned MIDR value. */ static void cpuinfo_arm_linux_detect_cluster_midr_by_sequential_scan( uint32_t default_midr, uint32_t processors_count, - struct cpuinfo_arm_linux_processor processors[restrict static processors_count]) -{ + struct cpuinfo_arm_linux_processor processors[restrict static processors_count]) { uint32_t midr = default_midr; for (uint32_t i = 0; i < processors_count; i++) { if (bitmask_all(processors[i].flags, CPUINFO_LINUX_FLAG_VALID)) { @@ -697,8 +805,11 @@ static void cpuinfo_arm_linux_detect_cluster_midr_by_sequential_scan( if (bitmask_all(processors[i].flags, CPUINFO_ARM_LINUX_VALID_MIDR)) { midr = processors[i].midr; } else { - cpuinfo_log_info("assume processor %"PRIu32" to have MIDR %08"PRIx32, i, midr); - /* To be consistent, we copy the MIDR entirely, rather than by parts */ + cpuinfo_log_info( + "assume processor %" PRIu32 " to have MIDR %08" PRIx32, i, midr); + /* To be consistent, we copy the MIDR + * entirely, rather than by parts + */ processors[i].midr = midr; processors[i].flags |= CPUINFO_ARM_LINUX_VALID_MIDR; } @@ -711,12 +822,14 @@ static void cpuinfo_arm_linux_detect_cluster_midr_by_sequential_scan( * Detects MIDR of each CPU core clusters' leader. * * @param[in] chipset - chipset (SoC) name information. - * @param max_processors - number of processor descriptions in the @p processors array. - * @param usable_processors - number of processor descriptions in the @p processors array with both POSSIBLE and - * PRESENT flags. - * @param[in,out] processors - array of logical processor descriptions with pre-parsed MIDR, maximum frequency, - * and decoded core cluster (package_leader_id) information. - * Upon return, processors[i].midr for all clusters' leaders contains the MIDR value. + * @param max_processors - number of processor descriptions in the @p processors + * array. + * @param usable_processors - number of processor descriptions in the @p + * processors array with both POSSIBLE and PRESENT flags. + * @param[in,out] processors - array of logical processor descriptions with + * pre-parsed MIDR, maximum frequency, and decoded core cluster + * (package_leader_id) information. Upon return, processors[i].midr for all + * clusters' leaders contains the MIDR value. * * @returns The number of core clusters */ @@ -724,8 +837,7 @@ uint32_t cpuinfo_arm_linux_detect_cluster_midr( const struct cpuinfo_arm_chipset chipset[restrict static 1], uint32_t max_processors, uint32_t usable_processors, - struct cpuinfo_arm_linux_processor processors[restrict static max_processors]) -{ + struct cpuinfo_arm_linux_processor processors[restrict static max_processors]) { uint32_t clusters_count = 0; uint32_t cluster_leaders[CLUSTERS_MAX]; uint32_t last_processor_in_cpuinfo = max_processors; @@ -736,7 +848,9 @@ uint32_t cpuinfo_arm_linux_detect_cluster_midr( if (processors[i].flags & CPUINFO_ARM_LINUX_VALID_PROCESSOR) { last_processor_in_cpuinfo = i; } - if (bitmask_all(processors[i].flags, CPUINFO_ARM_LINUX_VALID_IMPLEMENTER | CPUINFO_ARM_LINUX_VALID_PART)) { + if (bitmask_all( + processors[i].flags, + CPUINFO_ARM_LINUX_VALID_IMPLEMENTER | CPUINFO_ARM_LINUX_VALID_PART)) { last_processor_with_midr = i; processors_with_midr_count += 1; } @@ -747,73 +861,86 @@ uint32_t cpuinfo_arm_linux_detect_cluster_midr( } clusters_count += 1; } else { - /* Copy known bits of information to cluster leader */ + /* Copy known bits of information to cluster + * leader */ - if ((processors[i].flags & ~processors[group_leader].flags) & CPUINFO_LINUX_FLAG_MAX_FREQUENCY) { + if ((processors[i].flags & ~processors[group_leader].flags) & + CPUINFO_LINUX_FLAG_MAX_FREQUENCY) { processors[group_leader].max_frequency = processors[i].max_frequency; processors[group_leader].flags |= CPUINFO_LINUX_FLAG_MAX_FREQUENCY; } if (!bitmask_all(processors[group_leader].flags, CPUINFO_ARM_LINUX_VALID_MIDR) && - bitmask_all(processors[i].flags, CPUINFO_ARM_LINUX_VALID_MIDR)) - { + bitmask_all(processors[i].flags, CPUINFO_ARM_LINUX_VALID_MIDR)) { processors[group_leader].midr = processors[i].midr; processors[group_leader].flags |= CPUINFO_ARM_LINUX_VALID_MIDR; } } } } - cpuinfo_log_debug("detected %"PRIu32" core clusters", clusters_count); + cpuinfo_log_debug("detected %" PRIu32 " core clusters", clusters_count); /* - * Two relations between reported /proc/cpuinfo information, and cores is possible: - * - /proc/cpuinfo reports information for all or some of the cores below the corresponding - * "processor : " lines. Information on offline cores may be missing. - * - /proc/cpuinfo reports information only once, after all "processor : " lines. - * The reported information may relate to processor #0 or to the processor which - * executed the system calls to read /proc/cpuinfo. It is also indistinguishable - * from /proc/cpuinfo reporting information only for the last core (e.g. if all other - * cores are offline). + * Two relations between reported /proc/cpuinfo information, and cores + * is possible: + * - /proc/cpuinfo reports information for all or some of the cores + * below the corresponding "processor : " lines. Information on + * offline cores may be missing. + * - /proc/cpuinfo reports information only once, after all "processor : + * " lines. The reported information may relate to processor #0 + * or to the processor which executed the system calls to read + * /proc/cpuinfo. It is also indistinguishable from /proc/cpuinfo + * reporting information only for the last core (e.g. if all other cores + * are offline). * - * We detect the second case by checking if /proc/cpuinfo contains valid MIDR only for one, - * last reported, processor. Note, that the last reported core may be not the last - * present & possible processor, as /proc/cpuinfo may non-report high-index offline cores. + * We detect the second case by checking if /proc/cpuinfo contains valid + * MIDR only for one, last reported, processor. Note, that the last + * reported core may be not the last present & possible processor, as + * /proc/cpuinfo may non-report high-index offline cores. */ - if (processors_with_midr_count == 1 && last_processor_in_cpuinfo == last_processor_with_midr && clusters_count > 1) { + if (processors_with_midr_count == 1 && last_processor_in_cpuinfo == last_processor_with_midr && + clusters_count > 1) { /* - * There are multiple core clusters, but /proc/cpuinfo reported MIDR only for one - * processor, and we don't even know which logical processor this information refers to. + * There are multiple core clusters, but /proc/cpuinfo reported + * MIDR only for one processor, and we don't even know which + * logical processor this information refers to. * * We make three attempts to detect MIDR for all clusters: - * 1. Search tabulated MIDR values for chipsets which have heterogeneous clusters and ship with Linux - * kernels which do not always report all cores in /proc/cpuinfo. If found, use the tabulated values. - * 2. For systems with 2 clusters and MIDR known for one cluster, assume big.LITTLE configuration, - * and estimate MIDR for the other cluster under assumption that MIDR for the big cluster is known. - * 3. Initialize MIDRs for all core clusters to the only parsed MIDR value. + * 1. Search tabulated MIDR values for chipsets which have + * heterogeneous clusters and ship with Linux kernels which do + * not always report all cores in /proc/cpuinfo. If found, use + * the tabulated values. + * 2. For systems with 2 clusters and MIDR known for one + * cluster, assume big.LITTLE configuration, and estimate MIDR + * for the other cluster under assumption that MIDR for the big + * cluster is known. + * 3. Initialize MIDRs for all core clusters to the only parsed + * MIDR value. */ cpuinfo_log_debug("the only reported MIDR can not be attributed to a particular processor"); if (cpuinfo_arm_linux_detect_cluster_midr_by_chipset( - chipset, clusters_count, cluster_leaders, usable_processors, processors, false)) - { + chipset, clusters_count, cluster_leaders, usable_processors, processors, false)) { return clusters_count; } /* Try big.LITTLE heuristic */ if (cpuinfo_arm_linux_detect_cluster_midr_by_big_little_heuristic( - clusters_count, 1, last_processor_with_midr, - cluster_leaders, processors, false)) - { + clusters_count, 1, last_processor_with_midr, cluster_leaders, processors, false)) { return clusters_count; } - /* Fall back to sequential initialization of MIDR values for core clusters */ + /* Fall back to sequential initialization of MIDR values for + * core clusters + */ cpuinfo_arm_linux_detect_cluster_midr_by_sequential_scan( processors[processors[last_processor_with_midr].package_leader_id].midr, - max_processors, processors); + max_processors, + processors); } else if (processors_with_midr_count < usable_processors) { /* - * /proc/cpuinfo reported MIDR only for some processors, and probably some core clusters do not have MIDR - * for any of the cores. Check if this is the case. + * /proc/cpuinfo reported MIDR only for some processors, and + * probably some core clusters do not have MIDR for any of the + * cores. Check if this is the case. */ uint32_t clusters_with_midr_count = 0; for (uint32_t i = 0; i < max_processors; i++) { @@ -826,36 +953,48 @@ uint32_t cpuinfo_arm_linux_detect_cluster_midr( if (clusters_with_midr_count < clusters_count) { /* - * /proc/cpuinfo reported MIDR only for some clusters, need to reconstruct others. - * We make three attempts to detect MIDR for clusters without it: - * 1. Search tabulated MIDR values for chipsets which have heterogeneous clusters and ship with Linux - * kernels which do not always report all cores in /proc/cpuinfo. If found, use the tabulated values. - * 2. For systems with 2 clusters and MIDR known for one cluster, assume big.LITTLE configuration, - * and estimate MIDR for the other cluster under assumption that MIDR for the big cluster is known. - * 3. Initialize MIDRs for core clusters in a single sequential scan: - * - Clusters preceding the first reported MIDR value are assumed to have the last reported MIDR value. - * - Clusters following any reported MIDR value to have that MIDR value. + * /proc/cpuinfo reported MIDR only for some clusters, + * need to reconstruct others. We make three attempts to + * detect MIDR for clusters without it: + * 1. Search tabulated MIDR values for chipsets which + * have heterogeneous clusters and ship with Linux + * kernels which do not always report all cores in + * /proc/cpuinfo. If found, use the tabulated values. + * 2. For systems with 2 clusters and MIDR known for one + * cluster, assume big.LITTLE configuration, and + * estimate MIDR for the other cluster under assumption + * that MIDR for the big cluster is known. + * 3. Initialize MIDRs for core clusters in a single + * sequential scan: + * - Clusters preceding the first reported MIDR value + * are assumed to have the last reported MIDR value. + * - Clusters following any reported MIDR value to + * have that MIDR value. */ if (cpuinfo_arm_linux_detect_cluster_midr_by_chipset( - chipset, clusters_count, cluster_leaders, usable_processors, processors, true)) - { + chipset, clusters_count, cluster_leaders, usable_processors, processors, true)) { return clusters_count; } if (last_processor_with_midr != max_processors) { /* Try big.LITTLE heuristic */ if (cpuinfo_arm_linux_detect_cluster_midr_by_big_little_heuristic( - clusters_count, processors_with_midr_count, last_processor_with_midr, - cluster_leaders, processors, true)) - { + clusters_count, + processors_with_midr_count, + last_processor_with_midr, + cluster_leaders, + processors, + true)) { return clusters_count; } - /* Fall back to sequential initialization of MIDR values for core clusters */ + /* Fall back to sequential initialization of + * MIDR values for core clusters */ cpuinfo_arm_linux_detect_cluster_midr_by_sequential_scan( processors[processors[last_processor_with_midr].package_leader_id].midr, - max_processors, processors); + max_processors, + processors); } } } diff --git a/src/arm/mach/init.c b/src/arm/mach/init.c index 6a28b2db..9d83c05a 100644 --- a/src/arm/mach/init.c +++ b/src/arm/mach/init.c @@ -1,31 +1,31 @@ -#include +#include #include +#include #include #include -#include #include -#include -#include #include +#include +#include #include -#include #include #include +#include /* Polyfill recent CPUFAMILY_ARM_* values for older SDKs */ #ifndef CPUFAMILY_ARM_VORTEX_TEMPEST - #define CPUFAMILY_ARM_VORTEX_TEMPEST 0x07D34B9F +#define CPUFAMILY_ARM_VORTEX_TEMPEST 0x07D34B9F #endif #ifndef CPUFAMILY_ARM_LIGHTNING_THUNDER - #define CPUFAMILY_ARM_LIGHTNING_THUNDER 0x462504D2 +#define CPUFAMILY_ARM_LIGHTNING_THUNDER 0x462504D2 #endif #ifndef CPUFAMILY_ARM_FIRESTORM_ICESTORM - #define CPUFAMILY_ARM_FIRESTORM_ICESTORM 0x1B588BB3 +#define CPUFAMILY_ARM_FIRESTORM_ICESTORM 0x1B588BB3 #endif #ifndef CPUFAMILY_ARM_AVALANCHE_BLIZZARD - #define CPUFAMILY_ARM_AVALANCHE_BLIZZARD 0xDA33D83D +#define CPUFAMILY_ARM_AVALANCHE_BLIZZARD 0xDA33D83D #endif struct cpuinfo_arm_isa cpuinfo_isa = { @@ -39,12 +39,12 @@ struct cpuinfo_arm_isa cpuinfo_isa = { static uint32_t get_sys_info(int type_specifier, const char* name) { size_t size = 0; uint32_t result = 0; - int mib[2] = { CTL_HW, type_specifier }; + int mib[2] = {CTL_HW, type_specifier}; if (sysctl(mib, 2, NULL, &size, NULL, 0) != 0) { cpuinfo_log_info("sysctl(\"%s\") failed: %s", name, strerror(errno)); } else if (size == sizeof(uint32_t)) { sysctl(mib, 2, &result, &size, NULL, 0); - cpuinfo_log_debug("%s: %"PRIu32 ", size = %lu", name, result, size); + cpuinfo_log_debug("%s: %" PRIu32 ", size = %lu", name, result, size); } else { cpuinfo_log_info("sysctl does not support non-integer lookup for (\"%s\")", name); } @@ -58,7 +58,7 @@ static uint32_t get_sys_info_by_name(const char* type_specifier) { cpuinfo_log_info("sysctlbyname(\"%s\") failed: %s", type_specifier, strerror(errno)); } else if (size == sizeof(uint32_t)) { sysctlbyname(type_specifier, &result, &size, NULL, 0); - cpuinfo_log_debug("%s: %"PRIu32 ", size = %lu", type_specifier, result, size); + cpuinfo_log_debug("%s: %" PRIu32 ", size = %lu", type_specifier, result, size); } else { cpuinfo_log_info("sysctl does not support non-integer lookup for (\"%s\")", type_specifier); } @@ -79,13 +79,16 @@ static enum cpuinfo_uarch decode_uarch(uint32_t cpu_family, uint32_t core_index, /* 2x Monsoon + 4x Mistral cores */ return core_index < 2 ? cpuinfo_uarch_monsoon : cpuinfo_uarch_mistral; case CPUFAMILY_ARM_VORTEX_TEMPEST: - /* Hexa-core: 2x Vortex + 4x Tempest; Octa-core: 4x Cortex + 4x Tempest */ + /* Hexa-core: 2x Vortex + 4x Tempest; Octa-core: 4x + * Cortex + 4x Tempest */ return core_index + 4 < core_count ? cpuinfo_uarch_vortex : cpuinfo_uarch_tempest; case CPUFAMILY_ARM_LIGHTNING_THUNDER: - /* Hexa-core: 2x Lightning + 4x Thunder; Octa-core (presumed): 4x Lightning + 4x Thunder */ + /* Hexa-core: 2x Lightning + 4x Thunder; Octa-core + * (presumed): 4x Lightning + 4x Thunder */ return core_index + 4 < core_count ? cpuinfo_uarch_lightning : cpuinfo_uarch_thunder; case CPUFAMILY_ARM_FIRESTORM_ICESTORM: - /* Hexa-core: 2x Firestorm + 4x Icestorm; Octa-core: 4x Firestorm + 4x Icestorm */ + /* Hexa-core: 2x Firestorm + 4x Icestorm; Octa-core: 4x + * Firestorm + 4x Icestorm */ return core_index + 4 < core_count ? cpuinfo_uarch_firestorm : cpuinfo_uarch_icestorm; case CPUFAMILY_ARM_AVALANCHE_BLIZZARD: /* Hexa-core: 2x Avalanche + 4x Blizzard */ @@ -105,7 +108,7 @@ static void decode_package_name(char* package_name) { return; } - char *machine_name = alloca(size); + char* machine_name = alloca(size); if (sysctlbyname("hw.machine", machine_name, &size, NULL, 0) != 0) { cpuinfo_log_warning("sysctlbyname(\"hw.machine\") failed: %s", strerror(errno)); return; @@ -114,7 +117,7 @@ static void decode_package_name(char* package_name) { char name[10]; uint32_t major = 0, minor = 0; - if (sscanf(machine_name, "%9[^,0123456789]%"SCNu32",%"SCNu32, name, &major, &minor) != 3) { + if (sscanf(machine_name, "%9[^,0123456789]%" SCNu32 ",%" SCNu32, name, &major, &minor) != 3) { cpuinfo_log_warning("parsing \"hw.machine\" failed: %s", strerror(errno)); return; } @@ -149,8 +152,9 @@ static void decode_package_name(char* package_name) { /* iPad 2 and up are supported */ case 2: /* - * iPad 2 [A5]: iPad2,1, iPad2,2, iPad2,3, iPad2,4 - * iPad mini [A5]: iPad2,5, iPad2,6, iPad2,7 + * iPad 2 [A5]: iPad2,1, iPad2,2, iPad2,3, + * iPad2,4 iPad mini [A5]: iPad2,5, iPad2,6, + * iPad2,7 */ chip_model = major + 3; break; @@ -164,9 +168,10 @@ static void decode_package_name(char* package_name) { break; case 4: /* - * iPad Air [A7]: iPad4,1, iPad4,2, iPad4,3 - * iPad mini Retina [A7]: iPad4,4, iPad4,5, iPad4,6 - * iPad mini 3 [A7]: iPad4,7, iPad4,8, iPad4,9 + * iPad Air [A7]: iPad4,1, iPad4,2, + * iPad4,3 iPad mini Retina [A7]: iPad4,4, + * iPad4,5, iPad4,6 iPad mini 3 [A7]: + * iPad4,7, iPad4,8, iPad4,9 */ chip_model = major + 3; break; @@ -218,7 +223,7 @@ static void decode_package_name(char* package_name) { cpuinfo_log_info("unknown device: %s", machine_name); } if (chip_model != 0) { - snprintf(package_name, CPUINFO_PACKAGE_NAME_MAX, "Apple A%"PRIu32"%c", chip_model, suffix); + snprintf(package_name, CPUINFO_PACKAGE_NAME_MAX, "Apple A%" PRIu32 "%c", chip_model, suffix); } } @@ -236,20 +241,26 @@ void cpuinfo_arm_mach_init(void) { struct cpuinfo_mach_topology mach_topology = cpuinfo_mach_detect_topology(); processors = calloc(mach_topology.threads, sizeof(struct cpuinfo_processor)); if (processors == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" logical processors", - mach_topology.threads * sizeof(struct cpuinfo_processor), mach_topology.threads); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " logical processors", + mach_topology.threads * sizeof(struct cpuinfo_processor), + mach_topology.threads); goto cleanup; } cores = calloc(mach_topology.cores, sizeof(struct cpuinfo_core)); if (cores == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" cores", - mach_topology.cores * sizeof(struct cpuinfo_core), mach_topology.cores); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " cores", + mach_topology.cores * sizeof(struct cpuinfo_core), + mach_topology.cores); goto cleanup; } packages = calloc(mach_topology.packages, sizeof(struct cpuinfo_package)); if (packages == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" packages", - mach_topology.packages * sizeof(struct cpuinfo_package), mach_topology.packages); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " packages", + mach_topology.packages * sizeof(struct cpuinfo_package), + mach_topology.packages); goto cleanup; } @@ -258,7 +269,7 @@ void cpuinfo_arm_mach_init(void) { const uint32_t cores_per_package = mach_topology.cores / mach_topology.packages; for (uint32_t i = 0; i < mach_topology.packages; i++) { - packages[i] = (struct cpuinfo_package) { + packages[i] = (struct cpuinfo_package){ .processor_start = i * threads_per_package, .processor_count = threads_per_package, .core_start = i * cores_per_package, @@ -267,18 +278,19 @@ void cpuinfo_arm_mach_init(void) { decode_package_name(packages[i].name); } - const uint32_t cpu_family = get_sys_info_by_name("hw.cpufamily"); /* - * iOS 15 and macOS 12 added sysctls for ARM features, use them where possible. - * Otherwise, fallback to hardcoded set of CPUs with known support. + * iOS 15 and macOS 12 added sysctls for ARM features, use them where + * possible. Otherwise, fallback to hardcoded set of CPUs with known + * support. */ const uint32_t has_feat_lse = get_sys_info_by_name("hw.optional.arm.FEAT_LSE"); if (has_feat_lse != 0) { cpuinfo_isa.atomics = true; } else { - // Mandatory in ARMv8.1-A, list only cores released before iOS 15 / macOS 12 + // Mandatory in ARMv8.1-A, list only cores released before iOS + // 15 / macOS 12 switch (cpu_family) { case CPUFAMILY_ARM_MONSOON_MISTRAL: case CPUFAMILY_ARM_VORTEX_TEMPEST: @@ -327,8 +339,9 @@ void cpuinfo_arm_mach_init(void) { if (has_feat_fhm_legacy != 0) { cpuinfo_isa.fhm = true; } else { - // Mandatory in ARMv8.4-A when FP16 arithmetics is implemented, - // list only cores released before iOS 15 / macOS 12 + // Mandatory in ARMv8.4-A when FP16 arithmetics is + // implemented, list only cores released before iOS 15 / + // macOS 12 switch (cpu_family) { case CPUFAMILY_ARM_LIGHTNING_THUNDER: case CPUFAMILY_ARM_FIRESTORM_ICESTORM: @@ -346,7 +359,8 @@ void cpuinfo_arm_mach_init(void) { if (has_feat_fcma != 0) { cpuinfo_isa.fcma = true; } else { - // Mandatory in ARMv8.3-A, list only cores released before iOS 15 / macOS 12 + // Mandatory in ARMv8.3-A, list only cores released before iOS + // 15 / macOS 12 switch (cpu_family) { case CPUFAMILY_ARM_LIGHTNING_THUNDER: case CPUFAMILY_ARM_FIRESTORM_ICESTORM: @@ -358,7 +372,8 @@ void cpuinfo_arm_mach_init(void) { if (has_feat_jscvt != 0) { cpuinfo_isa.jscvt = true; } else { - // Mandatory in ARMv8.3-A, list only cores released before iOS 15 / macOS 12 + // Mandatory in ARMv8.3-A, list only cores released before iOS + // 15 / macOS 12 switch (cpu_family) { case CPUFAMILY_ARM_LIGHTNING_THUNDER: case CPUFAMILY_ARM_FIRESTORM_ICESTORM: @@ -370,7 +385,8 @@ void cpuinfo_arm_mach_init(void) { if (has_feat_dotprod != 0) { cpuinfo_isa.dot = true; } else { - // Mandatory in ARMv8.4-A, list only cores released before iOS 15 / macOS 12 + // Mandatory in ARMv8.4-A, list only cores released before iOS + // 15 / macOS 12 switch (cpu_family) { case CPUFAMILY_ARM_LIGHTNING_THUNDER: case CPUFAMILY_ARM_FIRESTORM_ICESTORM: @@ -385,7 +401,7 @@ void cpuinfo_arm_mach_init(void) { uint32_t num_clusters = 1; for (uint32_t i = 0; i < mach_topology.cores; i++) { - cores[i] = (struct cpuinfo_core) { + cores[i] = (struct cpuinfo_core){ .processor_start = i * threads_per_core, .processor_count = threads_per_core, .core_id = i % cores_per_package, @@ -410,27 +426,29 @@ void cpuinfo_arm_mach_init(void) { clusters = calloc(num_clusters, sizeof(struct cpuinfo_cluster)); if (clusters == NULL) { cpuinfo_log_error( - "failed to allocate %zu bytes for descriptions of %"PRIu32" clusters", - num_clusters * sizeof(struct cpuinfo_cluster), num_clusters); + "failed to allocate %zu bytes for descriptions of %" PRIu32 " clusters", + num_clusters * sizeof(struct cpuinfo_cluster), + num_clusters); goto cleanup; } uarchs = calloc(num_clusters, sizeof(struct cpuinfo_uarch_info)); if (uarchs == NULL) { cpuinfo_log_error( - "failed to allocate %zu bytes for descriptions of %"PRIu32" uarchs", - num_clusters * sizeof(enum cpuinfo_uarch), num_clusters); + "failed to allocate %zu bytes for descriptions of %" PRIu32 " uarchs", + num_clusters * sizeof(enum cpuinfo_uarch), + num_clusters); goto cleanup; } uint32_t cluster_idx = UINT32_MAX; for (uint32_t i = 0; i < mach_topology.cores; i++) { if (i == 0 || cores[i].uarch != cores[i - 1].uarch) { cluster_idx++; - uarchs[cluster_idx] = (struct cpuinfo_uarch_info) { + uarchs[cluster_idx] = (struct cpuinfo_uarch_info){ .uarch = cores[i].uarch, .processor_count = 1, .core_count = 1, }; - clusters[cluster_idx] = (struct cpuinfo_cluster) { + clusters[cluster_idx] = (struct cpuinfo_cluster){ .processor_start = i * threads_per_core, .processor_count = 1, .core_start = i, @@ -475,7 +493,7 @@ void cpuinfo_arm_mach_init(void) { /* Assume L1 caches are private to each core */ threads_per_l1 = 1; l1_count = mach_topology.threads / threads_per_l1; - cpuinfo_log_debug("detected %"PRIu32" L1 caches", l1_count); + cpuinfo_log_debug("detected %" PRIu32 " L1 caches", l1_count); } uint32_t threads_per_l2 = 0, l2_count = 0; @@ -483,7 +501,7 @@ void cpuinfo_arm_mach_init(void) { /* Assume L2 cache is shared between all cores */ threads_per_l2 = mach_topology.cores; l2_count = 1; - cpuinfo_log_debug("detected %"PRIu32" L2 caches", l2_count); + cpuinfo_log_debug("detected %" PRIu32 " L2 caches", l2_count); } uint32_t threads_per_l3 = 0, l3_count = 0; @@ -491,24 +509,26 @@ void cpuinfo_arm_mach_init(void) { /* Assume L3 cache is shared between all cores */ threads_per_l3 = mach_topology.cores; l3_count = 1; - cpuinfo_log_debug("detected %"PRIu32" L3 caches", l3_count); + cpuinfo_log_debug("detected %" PRIu32 " L3 caches", l3_count); } if (l1i_cache_size != 0) { l1i = calloc(l1_count, sizeof(struct cpuinfo_cache)); if (l1i == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L1I caches", - l1_count * sizeof(struct cpuinfo_cache), l1_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L1I caches", + l1_count * sizeof(struct cpuinfo_cache), + l1_count); goto cleanup; } for (uint32_t c = 0; c < l1_count; c++) { - l1i[c] = (struct cpuinfo_cache) { - .size = l1i_cache_size, - .associativity = l1_cache_associativity, - .sets = l1i_cache_size / (l1_cache_associativity * cacheline_size), - .partitions = cache_partitions, - .line_size = cacheline_size, - .flags = cache_flags, + l1i[c] = (struct cpuinfo_cache){ + .size = l1i_cache_size, + .associativity = l1_cache_associativity, + .sets = l1i_cache_size / (l1_cache_associativity * cacheline_size), + .partitions = cache_partitions, + .line_size = cacheline_size, + .flags = cache_flags, .processor_start = c * threads_per_l1, .processor_count = threads_per_l1, }; @@ -521,18 +541,20 @@ void cpuinfo_arm_mach_init(void) { if (l1d_cache_size != 0) { l1d = calloc(l1_count, sizeof(struct cpuinfo_cache)); if (l1d == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L1D caches", - l1_count * sizeof(struct cpuinfo_cache), l1_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L1D caches", + l1_count * sizeof(struct cpuinfo_cache), + l1_count); goto cleanup; } for (uint32_t c = 0; c < l1_count; c++) { - l1d[c] = (struct cpuinfo_cache) { - .size = l1d_cache_size, - .associativity = l1_cache_associativity, - .sets = l1d_cache_size / (l1_cache_associativity * cacheline_size), - .partitions = cache_partitions, - .line_size = cacheline_size, - .flags = cache_flags, + l1d[c] = (struct cpuinfo_cache){ + .size = l1d_cache_size, + .associativity = l1_cache_associativity, + .sets = l1d_cache_size / (l1_cache_associativity * cacheline_size), + .partitions = cache_partitions, + .line_size = cacheline_size, + .flags = cache_flags, .processor_start = c * threads_per_l1, .processor_count = threads_per_l1, }; @@ -545,18 +567,20 @@ void cpuinfo_arm_mach_init(void) { if (l2_count != 0) { l2 = calloc(l2_count, sizeof(struct cpuinfo_cache)); if (l2 == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L2 caches", - l2_count * sizeof(struct cpuinfo_cache), l2_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L2 caches", + l2_count * sizeof(struct cpuinfo_cache), + l2_count); goto cleanup; } for (uint32_t c = 0; c < l2_count; c++) { - l2[c] = (struct cpuinfo_cache) { - .size = l2_cache_size, - .associativity = l2_cache_associativity, - .sets = l2_cache_size / (l2_cache_associativity * cacheline_size), - .partitions = cache_partitions, - .line_size = cacheline_size, - .flags = cache_flags, + l2[c] = (struct cpuinfo_cache){ + .size = l2_cache_size, + .associativity = l2_cache_associativity, + .sets = l2_cache_size / (l2_cache_associativity * cacheline_size), + .partitions = cache_partitions, + .line_size = cacheline_size, + .flags = cache_flags, .processor_start = c * threads_per_l2, .processor_count = threads_per_l2, }; @@ -569,18 +593,20 @@ void cpuinfo_arm_mach_init(void) { if (l3_count != 0) { l3 = calloc(l3_count, sizeof(struct cpuinfo_cache)); if (l3 == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L3 caches", - l3_count * sizeof(struct cpuinfo_cache), l3_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L3 caches", + l3_count * sizeof(struct cpuinfo_cache), + l3_count); goto cleanup; } for (uint32_t c = 0; c < l3_count; c++) { - l3[c] = (struct cpuinfo_cache) { - .size = l3_cache_size, - .associativity = l3_cache_associativity, - .sets = l3_cache_size / (l3_cache_associativity * cacheline_size), - .partitions = cache_partitions, - .line_size = cacheline_size, - .flags = cache_flags, + l3[c] = (struct cpuinfo_cache){ + .size = l3_cache_size, + .associativity = l3_cache_associativity, + .sets = l3_cache_size / (l3_cache_associativity * cacheline_size), + .partitions = cache_partitions, + .line_size = cacheline_size, + .flags = cache_flags, .processor_start = c * threads_per_l3, .processor_count = threads_per_l3, }; @@ -598,8 +624,8 @@ void cpuinfo_arm_mach_init(void) { cpuinfo_uarchs = uarchs; cpuinfo_cache[cpuinfo_cache_level_1i] = l1i; cpuinfo_cache[cpuinfo_cache_level_1d] = l1d; - cpuinfo_cache[cpuinfo_cache_level_2] = l2; - cpuinfo_cache[cpuinfo_cache_level_3] = l3; + cpuinfo_cache[cpuinfo_cache_level_2] = l2; + cpuinfo_cache[cpuinfo_cache_level_3] = l3; cpuinfo_processors_count = mach_topology.threads; cpuinfo_cores_count = mach_topology.cores; @@ -608,8 +634,8 @@ void cpuinfo_arm_mach_init(void) { cpuinfo_uarchs_count = num_clusters; cpuinfo_cache_count[cpuinfo_cache_level_1i] = l1_count; cpuinfo_cache_count[cpuinfo_cache_level_1d] = l1_count; - cpuinfo_cache_count[cpuinfo_cache_level_2] = l2_count; - cpuinfo_cache_count[cpuinfo_cache_level_3] = l3_count; + cpuinfo_cache_count[cpuinfo_cache_level_2] = l2_count; + cpuinfo_cache_count[cpuinfo_cache_level_3] = l3_count; cpuinfo_max_cache_size = cpuinfo_compute_max_cache_size(&processors[0]); __sync_synchronize(); diff --git a/src/arm/midr.h b/src/arm/midr.h index 7255cfcf..89ebbb58 100644 --- a/src/arm/midr.h +++ b/src/arm/midr.h @@ -1,40 +1,39 @@ #pragma once #include - -#define CPUINFO_ARM_MIDR_IMPLEMENTER_MASK UINT32_C(0xFF000000) -#define CPUINFO_ARM_MIDR_VARIANT_MASK UINT32_C(0x00F00000) +#define CPUINFO_ARM_MIDR_IMPLEMENTER_MASK UINT32_C(0xFF000000) +#define CPUINFO_ARM_MIDR_VARIANT_MASK UINT32_C(0x00F00000) #define CPUINFO_ARM_MIDR_ARCHITECTURE_MASK UINT32_C(0x000F0000) -#define CPUINFO_ARM_MIDR_PART_MASK UINT32_C(0x0000FFF0) -#define CPUINFO_ARM_MIDR_REVISION_MASK UINT32_C(0x0000000F) +#define CPUINFO_ARM_MIDR_PART_MASK UINT32_C(0x0000FFF0) +#define CPUINFO_ARM_MIDR_REVISION_MASK UINT32_C(0x0000000F) -#define CPUINFO_ARM_MIDR_IMPLEMENTER_OFFSET 24 -#define CPUINFO_ARM_MIDR_VARIANT_OFFSET 20 +#define CPUINFO_ARM_MIDR_IMPLEMENTER_OFFSET 24 +#define CPUINFO_ARM_MIDR_VARIANT_OFFSET 20 #define CPUINFO_ARM_MIDR_ARCHITECTURE_OFFSET 16 -#define CPUINFO_ARM_MIDR_PART_OFFSET 4 -#define CPUINFO_ARM_MIDR_REVISION_OFFSET 0 +#define CPUINFO_ARM_MIDR_PART_OFFSET 4 +#define CPUINFO_ARM_MIDR_REVISION_OFFSET 0 -#define CPUINFO_ARM_MIDR_ARM1156 UINT32_C(0x410FB560) -#define CPUINFO_ARM_MIDR_CORTEX_A7 UINT32_C(0x410FC070) -#define CPUINFO_ARM_MIDR_CORTEX_A9 UINT32_C(0x410FC090) -#define CPUINFO_ARM_MIDR_CORTEX_A15 UINT32_C(0x410FC0F0) -#define CPUINFO_ARM_MIDR_CORTEX_A17 UINT32_C(0x410FC0E0) -#define CPUINFO_ARM_MIDR_CORTEX_A35 UINT32_C(0x410FD040) -#define CPUINFO_ARM_MIDR_CORTEX_A53 UINT32_C(0x410FD030) -#define CPUINFO_ARM_MIDR_CORTEX_A55 UINT32_C(0x410FD050) -#define CPUINFO_ARM_MIDR_CORTEX_A57 UINT32_C(0x410FD070) -#define CPUINFO_ARM_MIDR_CORTEX_A72 UINT32_C(0x410FD080) -#define CPUINFO_ARM_MIDR_CORTEX_A73 UINT32_C(0x410FD090) -#define CPUINFO_ARM_MIDR_CORTEX_A75 UINT32_C(0x410FD0A0) -#define CPUINFO_ARM_MIDR_KRYO280_GOLD UINT32_C(0x51AF8001) -#define CPUINFO_ARM_MIDR_KRYO280_SILVER UINT32_C(0x51AF8014) -#define CPUINFO_ARM_MIDR_KRYO385_GOLD UINT32_C(0x518F802D) -#define CPUINFO_ARM_MIDR_KRYO385_SILVER UINT32_C(0x518F803C) +#define CPUINFO_ARM_MIDR_ARM1156 UINT32_C(0x410FB560) +#define CPUINFO_ARM_MIDR_CORTEX_A7 UINT32_C(0x410FC070) +#define CPUINFO_ARM_MIDR_CORTEX_A9 UINT32_C(0x410FC090) +#define CPUINFO_ARM_MIDR_CORTEX_A15 UINT32_C(0x410FC0F0) +#define CPUINFO_ARM_MIDR_CORTEX_A17 UINT32_C(0x410FC0E0) +#define CPUINFO_ARM_MIDR_CORTEX_A35 UINT32_C(0x410FD040) +#define CPUINFO_ARM_MIDR_CORTEX_A53 UINT32_C(0x410FD030) +#define CPUINFO_ARM_MIDR_CORTEX_A55 UINT32_C(0x410FD050) +#define CPUINFO_ARM_MIDR_CORTEX_A57 UINT32_C(0x410FD070) +#define CPUINFO_ARM_MIDR_CORTEX_A72 UINT32_C(0x410FD080) +#define CPUINFO_ARM_MIDR_CORTEX_A73 UINT32_C(0x410FD090) +#define CPUINFO_ARM_MIDR_CORTEX_A75 UINT32_C(0x410FD0A0) +#define CPUINFO_ARM_MIDR_KRYO280_GOLD UINT32_C(0x51AF8001) +#define CPUINFO_ARM_MIDR_KRYO280_SILVER UINT32_C(0x51AF8014) +#define CPUINFO_ARM_MIDR_KRYO385_GOLD UINT32_C(0x518F802D) +#define CPUINFO_ARM_MIDR_KRYO385_SILVER UINT32_C(0x518F803C) #define CPUINFO_ARM_MIDR_KRYO_SILVER_821 UINT32_C(0x510F2010) -#define CPUINFO_ARM_MIDR_KRYO_GOLD UINT32_C(0x510F2050) +#define CPUINFO_ARM_MIDR_KRYO_GOLD UINT32_C(0x510F2050) #define CPUINFO_ARM_MIDR_KRYO_SILVER_820 UINT32_C(0x510F2110) -#define CPUINFO_ARM_MIDR_EXYNOS_M1_M2 UINT32_C(0x530F0010) -#define CPUINFO_ARM_MIDR_DENVER2 UINT32_C(0x4E0F0030) +#define CPUINFO_ARM_MIDR_EXYNOS_M1_M2 UINT32_C(0x530F0010) +#define CPUINFO_ARM_MIDR_DENVER2 UINT32_C(0x4E0F0030) inline static uint32_t midr_set_implementer(uint32_t midr, uint32_t implementer) { return (midr & ~CPUINFO_ARM_MIDR_IMPLEMENTER_MASK) | @@ -176,7 +175,9 @@ inline static uint32_t midr_score_core(uint32_t midr) { case UINT32_C(0x4100D440): /* Cortex-X1 */ case UINT32_C(0x4100D480): /* Cortex-X2 */ case UINT32_C(0x4100D4E0): /* Cortex-X3 */ - /* These cores are in big role w.r.t Cortex-A75/-A76/-A77/-A78/-A710/-A715 */ + /* These cores are in big role w.r.t + * Cortex-A75/-A76/-A77/-A78/-A710/-A715 + */ return 6; case UINT32_C(0x4100D080): /* Cortex-A72 */ case UINT32_C(0x4100D090): /* Cortex-A73 */ @@ -204,7 +205,8 @@ inline static uint32_t midr_score_core(uint32_t midr) { /* These cores are always in big role */ return 5; case UINT32_C(0x4100D070): /* Cortex-A57 */ - /* Cortex-A57 can be in LITTLE role w.r.t. Denver 2, or in big role w.r.t. Cortex-A53 */ + /* Cortex-A57 can be in LITTLE role w.r.t. Denver 2, or + * in big role w.r.t. Cortex-A53 */ return 4; #if CPUINFO_ARCH_ARM64 case UINT32_C(0x4100D060): /* Cortex-A65 */ @@ -212,7 +214,8 @@ inline static uint32_t midr_score_core(uint32_t midr) { case UINT32_C(0x4100D030): /* Cortex-A53 */ case UINT32_C(0x4100D050): /* Cortex-A55 */ case UINT32_C(0x4100D460): /* Cortex-A510 */ - /* Cortex-A53 is usually in LITTLE role, but can be in big role w.r.t. Cortex-A35 */ + /* Cortex-A53 is usually in LITTLE role, but can be in + * big role w.r.t. Cortex-A35 */ return 2; case UINT32_C(0x4100D040): /* Cortex-A35 */ #if CPUINFO_ARCH_ARM @@ -227,10 +230,12 @@ inline static uint32_t midr_score_core(uint32_t midr) { return 1; default: /* - * Unknown cores, or cores which do not have big/LITTLE roles. - * To be future-proof w.r.t. cores not yet recognized in cpuinfo, assume position between - * Cortex-A57/A72/A73/A75 and Cortex-A53/A55. Then at least future cores paired with - * one of these known cores will be properly scored. + * Unknown cores, or cores which do not have big/LITTLE + * roles. To be future-proof w.r.t. cores not yet + * recognized in cpuinfo, assume position between + * Cortex-A57/A72/A73/A75 and Cortex-A53/A55. Then at + * least future cores paired with one of these known + * cores will be properly scored. */ return 3; } diff --git a/src/arm/tlb.c b/src/arm/tlb.c index 9beb8327..ba39e6bc 100644 --- a/src/arm/tlb.c +++ b/src/arm/tlb.c @@ -5,23 +5,24 @@ switch (uarch) { /* * Cortex-A5 Technical Reference Manual: * 6.3.1. Micro TLB - * The first level of caching for the page table information is a micro TLB of - * 10 entries that is implemented on each of the instruction and data sides. - * 6.3.2. Main TLB - * Misses from the instruction and data micro TLBs are handled by a unified main TLB. - * The main TLB is 128-entry two-way set-associative. + * The first level of caching for the page table information + * is a micro TLB of 10 entries that is implemented on each of + * the instruction and data sides. 6.3.2. Main TLB Misses from + * the instruction and data micro TLBs are handled by a unified + * main TLB. The main TLB is 128-entry two-way set-associative. */ break; case cpuinfo_uarch_cortex_a7: /* * Cortex-A7 MPCore Technical Reference Manual: * 5.3.1. Micro TLB - * The first level of caching for the page table information is a micro TLB of - * 10 entries that is implemented on each of the instruction and data sides. - * 5.3.2. Main TLB - * Misses from the micro TLBs are handled by a unified main TLB. This is a 256-entry 2-way - * set-associative structure. The main TLB supports all the VMSAv7 page sizes of - * 4KB, 64KB, 1MB and 16MB in addition to the LPAE page sizes of 2MB and 1G. + * The first level of caching for the page table information + * is a micro TLB of 10 entries that is implemented on each of + * the instruction and data sides. 5.3.2. Main TLB Misses from + * the micro TLBs are handled by a unified main TLB. This is a + * 256-entry 2-way set-associative structure. The main TLB + * supports all the VMSAv7 page sizes of 4KB, 64KB, 1MB and 16MB + * in addition to the LPAE page sizes of 2MB and 1G. */ break; case cpuinfo_uarch_cortex_a8: @@ -29,7 +30,8 @@ switch (uarch) { * Cortex-A8 Technical Reference Manual: * 6.1. About the MMU * The MMU features include the following: - * - separate, fully-associative, 32-entry data and instruction TLBs + * - separate, fully-associative, 32-entry data and + * instruction TLBs * - TLB entries that support 4KB, 64KB, 1MB, and 16MB pages */ break; @@ -37,51 +39,63 @@ switch (uarch) { /* * ARM Cortex‑A9 Technical Reference Manual: * 6.2.1 Micro TLB - * The first level of caching for the page table information is a micro TLB of 32 entries on the data side, - * and configurable 32 or 64 entries on the instruction side. - * 6.2.2 Main TLB - * The main TLB is implemented as a combination of: + * The first level of caching for the page table information + * is a micro TLB of 32 entries on the data side, and + * configurable 32 or 64 entries on the instruction side. 6.2.2 + * Main TLB The main TLB is implemented as a combination of: * - A fully-associative, lockable array of four elements. - * - A 2-way associative structure of 2x32, 2x64, 2x128 or 2x256 entries. + * - A 2-way associative structure of 2x32, 2x64, 2x128 or + * 2x256 entries. */ break; case cpuinfo_uarch_cortex_a15: /* * ARM Cortex-A15 MPCore Processor Technical Reference Manual: * 5.2.1. L1 instruction TLB - * The L1 instruction TLB is a 32-entry fully-associative structure. This TLB caches entries at the 4KB - * granularity of Virtual Address (VA) to Physical Address (PA) mapping only. If the page tables map the - * memory region to a larger granularity than 4K, it only allocates one mapping for the particular 4K region - * to which the current access corresponds. - * 5.2.2. L1 data TLB - * There are two separate 32-entry fully-associative TLBs that are used for data loads and stores, - * respectively. Similar to the L1 instruction TLB, both of these cache entries at the 4KB granularity of - * VA to PA mappings only. At implementation time, the Cortex-A15 MPCore processor can be configured with - * the -l1tlb_1m option, to have the L1 data TLB cache entries at both the 4KB and 1MB granularity. - * With this configuration, any translation that results in a 1MB or larger page is cached in the L1 data - * TLB as a 1MB entry. Any translation that results in a page smaller than 1MB is cached in the L1 data TLB - * as a 4KB entry. By default, all translations are cached in the L1 data TLB as a 4KB entry. - * 5.2.3. L2 TLB - * Misses from the L1 instruction and data TLBs are handled by a unified L2 TLB. This is a 512-entry 4-way - * set-associative structure. The L2 TLB supports all the VMSAv7 page sizes of 4K, 64K, 1MB and 16MB in - * addition to the LPAE page sizes of 2MB and 1GB. + * The L1 instruction TLB is a 32-entry fully-associative + * structure. This TLB caches entries at the 4KB granularity of + * Virtual Address (VA) to Physical Address (PA) mapping only. + * If the page tables map the memory region to a larger + * granularity than 4K, it only allocates one mapping for the + * particular 4K region to which the current access + * corresponds. 5.2.2. L1 data TLB There are two separate + * 32-entry fully-associative TLBs that are used for data loads + * and stores, respectively. Similar to the L1 instruction TLB, + * both of these cache entries at the 4KB granularity of VA to + * PA mappings only. At implementation time, the Cortex-A15 + * MPCore processor can be configured with the -l1tlb_1m option, + * to have the L1 data TLB cache entries at both the 4KB and 1MB + * granularity. With this configuration, any translation that + * results in a 1MB or larger page is cached in the L1 data TLB + * as a 1MB entry. Any translation that results in a page + * smaller than 1MB is cached in the L1 data TLB as a 4KB entry. + * By default, all translations are cached in the L1 data TLB as + * a 4KB entry. 5.2.3. L2 TLB Misses from the L1 instruction and + * data TLBs are handled by a unified L2 TLB. This is a + * 512-entry 4-way set-associative structure. The L2 TLB + * supports all the VMSAv7 page sizes of 4K, 64K, 1MB and 16MB + * in addition to the LPAE page sizes of 2MB and 1GB. */ break; case cpuinfo_uarch_cortex_a17: /* * ARM Cortex-A17 MPCore Processor Technical Reference Manual: * 5.2.1. Instruction micro TLB - * The instruction micro TLB is implemented as a 32, 48 or 64 entry, fully-associative structure. This TLB - * caches entries at the 4KB and 1MB granularity of Virtual Address (VA) to Physical Address (PA) mapping - * only. If the translation tables map the memory region to a larger granularity than 4KB or 1MB, it only - * allocates one mapping for the particular 4KB region to which the current access corresponds. - * 5.2.2. Data micro TLB - * The data micro TLB is a 32 entry fully-associative TLB that is used for data loads and stores. The cache - * entries have a 4KB and 1MB granularity of VA to PA mappings only. - * 5.2.3. Unified main TLB - * Misses from the instruction and data micro TLBs are handled by a unified main TLB. This is a 1024 entry - * 4-way set-associative structure. The main TLB supports all the VMSAv7 page sizes of 4K, 64K, 1MB and 16MB - * in addition to the LPAE page sizes of 2MB and 1GB. + * The instruction micro TLB is implemented as a 32, 48 or 64 + * entry, fully-associative structure. This TLB caches entries + * at the 4KB and 1MB granularity of Virtual Address (VA) to + * Physical Address (PA) mapping only. If the translation tables + * map the memory region to a larger granularity than 4KB or + * 1MB, it only allocates one mapping for the particular 4KB + * region to which the current access corresponds. 5.2.2. Data + * micro TLB The data micro TLB is a 32 entry fully-associative + * TLB that is used for data loads and stores. The cache entries + * have a 4KB and 1MB granularity of VA to PA mappings + * only. 5.2.3. Unified main TLB Misses from the instruction and + * data micro TLBs are handled by a unified main TLB. This is a + * 1024 entry 4-way set-associative structure. The main TLB + * supports all the VMSAv7 page sizes of 4K, 64K, 1MB and 16MB + * in addition to the LPAE page sizes of 2MB and 1GB. */ break; case cpuinfo_uarch_cortex_a35: @@ -89,45 +103,52 @@ switch (uarch) { * ARM Cortex‑A35 Processor Technical Reference Manual: * A6.2 TLB Organization * Micro TLB - * The first level of caching for the translation table information is a micro TLB of ten entries that - * is implemented on each of the instruction and data sides. - * Main TLB - * A unified main TLB handles misses from the micro TLBs. It has a 512-entry, 2-way, set-associative - * structure and supports all VMSAv8 block sizes, except 1GB. If it fetches a 1GB block, the TLB splits - * it into 512MB blocks and stores the appropriate block for the lookup. + * The first level of caching for the translation table + * information is a micro TLB of ten entries that is implemented + * on each of the instruction and data sides. Main TLB A unified + * main TLB handles misses from the micro TLBs. It has a + * 512-entry, 2-way, set-associative structure and supports all + * VMSAv8 block sizes, except 1GB. If it fetches a 1GB block, + * the TLB splits it into 512MB blocks and stores the + * appropriate block for the lookup. */ break; case cpuinfo_uarch_cortex_a53: /* * ARM Cortex-A53 MPCore Processor Technical Reference Manual: * 5.2.1. Micro TLB - * The first level of caching for the translation table information is a micro TLB of ten entries that is - * implemented on each of the instruction and data sides. - * 5.2.2. Main TLB - * A unified main TLB handles misses from the micro TLBs. This is a 512-entry, 4-way, set-associative - * structure. The main TLB supports all VMSAv8 block sizes, except 1GB. If a 1GB block is fetched, it is - * split into 512MB blocks and the appropriate block for the lookup stored. + * The first level of caching for the translation table + * information is a micro TLB of ten entries that is implemented + * on each of the instruction and data sides. 5.2.2. Main TLB A + * unified main TLB handles misses from the micro TLBs. This is + * a 512-entry, 4-way, set-associative structure. The main TLB + * supports all VMSAv8 block sizes, except 1GB. If a 1GB block + * is fetched, it is split into 512MB blocks and the appropriate + * block for the lookup stored. */ break; case cpuinfo_uarch_cortex_a57: /* * ARM® Cortex-A57 MPCore Processor Technical Reference Manual: * 5.2.1 L1 instruction TLB - * The L1 instruction TLB is a 48-entry fully-associative structure. This TLB caches entries of three - * different page sizes, natively 4KB, 64KB, and 1MB, of VA to PA mappings. If the page tables map the memory - * region to a larger granularity than 1MB, it only allocates one mapping for the particular 1MB region to - * which the current access corresponds. - * 5.2.2 L1 data TLB - * The L1 data TLB is a 32-entry fully-associative TLB that is used for data loads and stores. This TLB - * caches entries of three different page sizes, natively 4KB, 64KB, and 1MB, of VA to PA mappings. - * 5.2.3 L2 TLB - * Misses from the L1 instruction and data TLBs are handled by a unified L2 TLB. This is a 1024-entry 4-way - * set-associative structure. The L2 TLB supports the page sizes of 4K, 64K, 1MB and 16MB. It also supports - * page sizes of 2MB and 1GB for the long descriptor format translation in AArch32 state and in AArch64 state - * when using the 4KB translation granule. In addition, the L2 TLB supports the 512MB page map size defined - * for the AArch64 translations that use a 64KB translation granule. + * The L1 instruction TLB is a 48-entry fully-associative + * structure. This TLB caches entries of three different page + * sizes, natively 4KB, 64KB, and 1MB, of VA to PA mappings. If + * the page tables map the memory region to a larger granularity + * than 1MB, it only allocates one mapping for the particular + * 1MB region to which the current access corresponds. 5.2.2 L1 + * data TLB The L1 data TLB is a 32-entry fully-associative TLB + * that is used for data loads and stores. This TLB caches + * entries of three different page sizes, natively 4KB, 64KB, + * and 1MB, of VA to PA mappings. 5.2.3 L2 TLB Misses from the + * L1 instruction and data TLBs are handled by a unified L2 TLB. + * This is a 1024-entry 4-way set-associative structure. The L2 + * TLB supports the page sizes of 4K, 64K, 1MB and 16MB. It also + * supports page sizes of 2MB and 1GB for the long descriptor + * format translation in AArch32 state and in AArch64 state when + * using the 4KB translation granule. In addition, the L2 TLB + * supports the 512MB page map size defined for the AArch64 + * translations that use a 64KB translation granule. */ break; } - - diff --git a/src/arm/uarch.c b/src/arm/uarch.c index f1dd4934..68531e4d 100644 --- a/src/arm/uarch.c +++ b/src/arm/uarch.c @@ -4,15 +4,13 @@ #include #include - void cpuinfo_arm_decode_vendor_uarch( uint32_t midr, #if CPUINFO_ARCH_ARM bool has_vfpv4, #endif /* CPUINFO_ARCH_ARM */ enum cpuinfo_vendor vendor[restrict static 1], - enum cpuinfo_uarch uarch[restrict static 1]) -{ + enum cpuinfo_uarch uarch[restrict static 1]) { switch (midr_get_implementer(midr)) { case 'A': *vendor = cpuinfo_vendor_arm; @@ -39,8 +37,9 @@ void cpuinfo_arm_decode_vendor_uarch( case 0xC0D: /* * Rockchip RK3288 only. - * Core information is ambiguous: some sources specify Cortex-A12, others - Cortex-A17. - * Assume it is Cortex-A12. + * Core information is ambiguous: some + * sources specify Cortex-A12, others - + * Cortex-A17. Assume it is Cortex-A12. */ *uarch = cpuinfo_uarch_cortex_a12; break; @@ -58,9 +57,11 @@ void cpuinfo_arm_decode_vendor_uarch( *uarch = cpuinfo_uarch_cortex_a35; break; case 0xD05: - // Note: use Variant, not Revision, field - *uarch = (midr & CPUINFO_ARM_MIDR_VARIANT_MASK) == 0 ? - cpuinfo_uarch_cortex_a55r0 : cpuinfo_uarch_cortex_a55; + // Note: use Variant, not Revision, + // field + *uarch = (midr & CPUINFO_ARM_MIDR_VARIANT_MASK) == 0 + ? cpuinfo_uarch_cortex_a55r0 + : cpuinfo_uarch_cortex_a55; break; case 0xD06: *uarch = cpuinfo_uarch_cortex_a65; @@ -138,7 +139,9 @@ void cpuinfo_arm_decode_vendor_uarch( break; #endif /* CPUINFO_ARCH_ARM */ default: - cpuinfo_log_warning("unknown ARM CPU part 0x%03"PRIx32" ignored", midr_get_part(midr)); + cpuinfo_log_warning( + "unknown ARM CPU part 0x%03" PRIx32 " ignored", + midr_get_part(midr)); } } break; @@ -153,13 +156,17 @@ void cpuinfo_arm_decode_vendor_uarch( break; #if CPUINFO_ARCH_ARM64 case 0x516: - /* Broadcom Vulkan was sold to Cavium before it reached the market, so we identify it as Cavium ThunderX2 */ + /* Broadcom Vulkan was sold to Cavium + * before it reached the market, so we + * identify it as Cavium ThunderX2 */ *vendor = cpuinfo_vendor_cavium; *uarch = cpuinfo_uarch_thunderx2; break; #endif /* CPUINFO_ARCH_ARM64 */ default: - cpuinfo_log_warning("unknown Broadcom CPU part 0x%03"PRIx32" ignored", midr_get_part(midr)); + cpuinfo_log_warning( + "unknown Broadcom CPU part 0x%03" PRIx32 " ignored", + midr_get_part(midr)); } break; #if CPUINFO_ARCH_ARM64 @@ -176,7 +183,8 @@ void cpuinfo_arm_decode_vendor_uarch( *uarch = cpuinfo_uarch_thunderx2; break; default: - cpuinfo_log_warning("unknown Cavium CPU part 0x%03"PRIx32" ignored", midr_get_part(midr)); + cpuinfo_log_warning( + "unknown Cavium CPU part 0x%03" PRIx32 " ignored", midr_get_part(midr)); } break; #endif /* CPUINFO_ARCH_ARM64 */ @@ -188,12 +196,14 @@ void cpuinfo_arm_decode_vendor_uarch( *uarch = cpuinfo_uarch_taishan_v110; break; #endif /* CPUINFO_ARCH_ARM64 */ - case 0xD40: /* Kirin 980 Big/Medium cores -> Cortex-A76 */ + case 0xD40: /* Kirin 980 Big/Medium cores -> + Cortex-A76 */ *vendor = cpuinfo_vendor_arm; *uarch = cpuinfo_uarch_cortex_a76; break; default: - cpuinfo_log_warning("unknown Huawei CPU part 0x%03"PRIx32" ignored", midr_get_part(midr)); + cpuinfo_log_warning( + "unknown Huawei CPU part 0x%03" PRIx32 " ignored", midr_get_part(midr)); } break; #if CPUINFO_ARCH_ARM @@ -206,7 +216,8 @@ void cpuinfo_arm_decode_vendor_uarch( *uarch = cpuinfo_uarch_xscale; break; default: - cpuinfo_log_warning("unknown Intel CPU part 0x%03"PRIx32" ignored", midr_get_part(midr)); + cpuinfo_log_warning( + "unknown Intel CPU part 0x%03" PRIx32 " ignored", midr_get_part(midr)); } break; #endif /* CPUINFO_ARCH_ARM */ @@ -223,7 +234,8 @@ void cpuinfo_arm_decode_vendor_uarch( *uarch = cpuinfo_uarch_carmel; break; default: - cpuinfo_log_warning("unknown Nvidia CPU part 0x%03"PRIx32" ignored", midr_get_part(midr)); + cpuinfo_log_warning( + "unknown Nvidia CPU part 0x%03" PRIx32 " ignored", midr_get_part(midr)); } break; case 'P': @@ -233,7 +245,9 @@ void cpuinfo_arm_decode_vendor_uarch( *uarch = cpuinfo_uarch_xgene; break; default: - cpuinfo_log_warning("unknown Applied Micro CPU part 0x%03"PRIx32" ignored", midr_get_part(midr)); + cpuinfo_log_warning( + "unknown Applied Micro CPU part 0x%03" PRIx32 " ignored", + midr_get_part(midr)); } break; case 'Q': @@ -241,9 +255,12 @@ void cpuinfo_arm_decode_vendor_uarch( switch (midr_get_part(midr)) { #if CPUINFO_ARCH_ARM case 0x00F: - /* Mostly Scorpions, but some Cortex A5 may report this value as well */ + /* Mostly Scorpions, but some Cortex A5 + * may report this value as well + */ if (has_vfpv4) { - /* Unlike Scorpion, Cortex-A5 comes with VFPv4 */ + /* Unlike Scorpion, Cortex-A5 + * comes with VFPv4 */ *vendor = cpuinfo_vendor_arm; *uarch = cpuinfo_uarch_cortex_a5; } else { @@ -266,39 +283,51 @@ void cpuinfo_arm_decode_vendor_uarch( * - r0p1 -> Krait 200 * - r0p2 -> Krait 200 * - r1p0 -> Krait 300 - * - r2p0 -> Krait 400 (Snapdragon 800 MSMxxxx) - * - r2p1 -> Krait 400 (Snapdragon 801 MSMxxxxPRO) + * - r2p0 -> Krait 400 (Snapdragon 800 + * MSMxxxx) + * - r2p1 -> Krait 400 (Snapdragon 801 + * MSMxxxxPRO) * - r3p1 -> Krait 450 */ *uarch = cpuinfo_uarch_krait; break; #endif /* CPUINFO_ARCH_ARM */ - case 0x201: /* Qualcomm Snapdragon 821: Low-power Kryo "Silver" */ - case 0x205: /* Qualcomm Snapdragon 820 & 821: High-performance Kryo "Gold" */ - case 0x211: /* Qualcomm Snapdragon 820: Low-power Kryo "Silver" */ + case 0x201: /* Qualcomm Snapdragon 821: + Low-power Kryo "Silver" */ + case 0x205: /* Qualcomm Snapdragon 820 & 821: + High-performance Kryo "Gold" */ + case 0x211: /* Qualcomm Snapdragon 820: + Low-power Kryo "Silver" */ *uarch = cpuinfo_uarch_kryo; break; - case 0x800: /* High-performance Kryo 260 (r10p2) / Kryo 280 (r10p1) "Gold" -> Cortex-A73 */ + case 0x800: /* High-performance Kryo 260 (r10p2) + / Kryo 280 (r10p1) "Gold" -> + Cortex-A73 */ *vendor = cpuinfo_vendor_arm; *uarch = cpuinfo_uarch_cortex_a73; break; - case 0x801: /* Low-power Kryo 260 / 280 "Silver" -> Cortex-A53 */ + case 0x801: /* Low-power Kryo 260 / 280 "Silver" + -> Cortex-A53 */ *vendor = cpuinfo_vendor_arm; *uarch = cpuinfo_uarch_cortex_a53; break; - case 0x802: /* High-performance Kryo 385 "Gold" -> Cortex-A75 */ + case 0x802: /* High-performance Kryo 385 "Gold" + -> Cortex-A75 */ *vendor = cpuinfo_vendor_arm; *uarch = cpuinfo_uarch_cortex_a75; break; - case 0x803: /* Low-power Kryo 385 "Silver" -> Cortex-A55r0 */ + case 0x803: /* Low-power Kryo 385 "Silver" -> + Cortex-A55r0 */ *vendor = cpuinfo_vendor_arm; *uarch = cpuinfo_uarch_cortex_a55r0; break; - case 0x804: /* High-performance Kryo 485 "Gold" / "Gold Prime" -> Cortex-A76 */ + case 0x804: /* High-performance Kryo 485 "Gold" + / "Gold Prime" -> Cortex-A76 */ *vendor = cpuinfo_vendor_arm; *uarch = cpuinfo_uarch_cortex_a76; break; - case 0x805: /* Low-performance Kryo 485 "Silver" -> Cortex-A55 */ + case 0x805: /* Low-performance Kryo 485 "Silver" + -> Cortex-A55 */ *vendor = cpuinfo_vendor_arm; *uarch = cpuinfo_uarch_cortex_a55; break; @@ -311,7 +340,9 @@ void cpuinfo_arm_decode_vendor_uarch( break; #endif /* CPUINFO_ARCH_ARM64 */ default: - cpuinfo_log_warning("unknown Qualcomm CPU part 0x%03"PRIx32" ignored", midr_get_part(midr)); + cpuinfo_log_warning( + "unknown Qualcomm CPU part 0x%03" PRIx32 " ignored", + midr_get_part(midr)); } break; case 'S': @@ -319,7 +350,8 @@ void cpuinfo_arm_decode_vendor_uarch( switch (midr & (CPUINFO_ARM_MIDR_VARIANT_MASK | CPUINFO_ARM_MIDR_PART_MASK)) { case 0x00100010: /* - * Exynos 8890 MIDR = 0x531F0011, assume Exynos M1 has: + * Exynos 8890 MIDR = 0x531F0011, assume + * Exynos M1 has: * - CPU variant 0x1 * - CPU part 0x001 */ @@ -327,7 +359,8 @@ void cpuinfo_arm_decode_vendor_uarch( break; case 0x00400010: /* - * Exynos 8895 MIDR = 0x534F0010, assume Exynos M2 has: + * Exynos 8895 MIDR = 0x534F0010, assume + * Exynos M2 has: * - CPU variant 0x4 * - CPU part 0x001 */ @@ -335,7 +368,8 @@ void cpuinfo_arm_decode_vendor_uarch( break; case 0x00100020: /* - * Exynos 9810 MIDR = 0x531F0020, assume Exynos M3 has: + * Exynos 9810 MIDR = 0x531F0020, assume + * Exynos M3 has: * - CPU variant 0x1 * - CPU part 0x002 */ @@ -343,7 +377,8 @@ void cpuinfo_arm_decode_vendor_uarch( break; case 0x00100030: /* - * Exynos 9820 MIDR = 0x531F0030, assume Exynos M4 has: + * Exynos 9820 MIDR = 0x531F0030, assume + * Exynos M4 has: * - CPU variant 0x1 * - CPU part 0x003 */ @@ -351,15 +386,19 @@ void cpuinfo_arm_decode_vendor_uarch( break; case 0x00100040: /* - * Exynos 9820 MIDR = 0x531F0040, assume Exynos M5 has: + * Exynos 9820 MIDR = 0x531F0040, assume + * Exynos M5 has: * - CPU variant 0x1 * - CPU part 0x004 */ *uarch = cpuinfo_uarch_exynos_m5; break; default: - cpuinfo_log_warning("unknown Samsung CPU variant 0x%01"PRIx32" part 0x%03"PRIx32" ignored", - midr_get_variant(midr), midr_get_part(midr)); + cpuinfo_log_warning( + "unknown Samsung CPU variant 0x%01" PRIx32 " part 0x%03" PRIx32 + " ignored", + midr_get_variant(midr), + midr_get_part(midr)); } break; #if CPUINFO_ARCH_ARM @@ -371,12 +410,17 @@ void cpuinfo_arm_decode_vendor_uarch( *uarch = cpuinfo_uarch_pj4; break; default: - cpuinfo_log_warning("unknown Marvell CPU part 0x%03"PRIx32" ignored", midr_get_part(midr)); + cpuinfo_log_warning( + "unknown Marvell CPU part 0x%03" PRIx32 " ignored", + midr_get_part(midr)); } break; #endif /* CPUINFO_ARCH_ARM */ default: - cpuinfo_log_warning("unknown CPU implementer '%c' (0x%02"PRIx32") with CPU part 0x%03"PRIx32" ignored", - (char) midr_get_implementer(midr), midr_get_implementer(midr), midr_get_part(midr)); + cpuinfo_log_warning( + "unknown CPU implementer '%c' (0x%02" PRIx32 ") with CPU part 0x%03" PRIx32 " ignored", + (char)midr_get_implementer(midr), + midr_get_implementer(midr), + midr_get_part(midr)); } } diff --git a/src/arm/windows/init-by-logical-sys-info.c b/src/arm/windows/init-by-logical-sys-info.c index fe1b328d..6ce6efe8 100644 --- a/src/arm/windows/init-by-logical-sys-info.c +++ b/src/arm/windows/init-by-logical-sys-info.c @@ -1,9 +1,9 @@ -#include +#include +#include #include +#include #include #include -#include -#include #include #include @@ -12,7 +12,7 @@ #include "windows-arm-init.h" -#define MAX_NR_OF_CACHES (cpuinfo_cache_level_max - 1) +#define MAX_NR_OF_CACHES (cpuinfo_cache_level_max - 1) /* Call chain: * cpu_info_init_by_logical_sys_info @@ -27,30 +27,28 @@ * store_cache_info_per_processor */ -static uint32_t count_logical_processors( - const uint32_t max_group_count, - uint32_t* global_proc_index_per_group); +static uint32_t count_logical_processors(const uint32_t max_group_count, uint32_t* global_proc_index_per_group); static uint32_t read_packages_for_processors( struct cpuinfo_processor* processors, const uint32_t number_of_processors, const uint32_t* global_proc_index_per_group, - const struct woa_chip_info *chip_info); + const struct woa_chip_info* chip_info); static uint32_t read_cores_for_processors( struct cpuinfo_processor* processors, const uint32_t number_of_processors, const uint32_t* global_proc_index_per_group, struct cpuinfo_core* cores, - const struct woa_chip_info *chip_info); + const struct woa_chip_info* chip_info); static uint32_t read_caches_for_processors( - struct cpuinfo_processor *processors, + struct cpuinfo_processor* processors, const uint32_t number_of_processors, - struct cpuinfo_cache *caches, + struct cpuinfo_cache* caches, uint32_t* numbers_of_caches, const uint32_t* global_proc_index_per_group, - const struct woa_chip_info *chip_info); + const struct woa_chip_info* chip_info); static uint32_t read_all_logical_processor_info_of_relation( LOGICAL_PROCESSOR_RELATIONSHIP info_type, @@ -60,7 +58,7 @@ static uint32_t read_all_logical_processor_info_of_relation( uint32_t* numbers_of_caches, struct cpuinfo_core* cores, const uint32_t* global_proc_index_per_group, - const struct woa_chip_info *chip_info); + const struct woa_chip_info* chip_info); static bool parse_relation_processor_info( struct cpuinfo_processor* processors, @@ -69,7 +67,7 @@ static bool parse_relation_processor_info( PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX info, const uint32_t info_id, struct cpuinfo_core* cores, - const struct woa_chip_info *chip_info); + const struct woa_chip_info* chip_info); static bool parse_relation_cache_info( struct cpuinfo_processor* processors, @@ -91,7 +89,7 @@ static void store_core_info_per_processor( const uint32_t core_id, PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX core_info, struct cpuinfo_core* cores, - const struct woa_chip_info *chip_info); + const struct woa_chip_info* chip_info); static void store_cache_info_per_processor( struct cpuinfo_processor* processors, @@ -112,11 +110,7 @@ static bool connect_packages_cores_clusters_by_processors( static inline uint32_t low_index_from_kaffinity(KAFFINITY kaffinity); - -bool cpu_info_init_by_logical_sys_info( - const struct woa_chip_info *chip_info, - const enum cpuinfo_vendor vendor) -{ +bool cpu_info_init_by_logical_sys_info(const struct woa_chip_info* chip_info, const enum cpuinfo_vendor vendor) { struct cpuinfo_processor* processors = NULL; struct cpuinfo_package* packages = NULL; struct cpuinfo_cluster* clusters = NULL; @@ -128,147 +122,156 @@ bool cpu_info_init_by_logical_sys_info( uint32_t nr_of_cores = 0; uint32_t nr_of_all_caches = 0; uint32_t numbers_of_caches[MAX_NR_OF_CACHES] = {0}; - + uint32_t nr_of_uarchs = 0; bool result = false; - + HANDLE heap = GetProcessHeap(); /* 1. Count available logical processor groups and processors */ - const uint32_t max_group_count = (uint32_t) GetMaximumProcessorGroupCount(); - cpuinfo_log_debug("detected %"PRIu32" processor group(s)", max_group_count); - /* We need to store the absolute processor ID offsets for every groups, because + const uint32_t max_group_count = (uint32_t)GetMaximumProcessorGroupCount(); + cpuinfo_log_debug("detected %" PRIu32 " processor group(s)", max_group_count); + /* We need to store the absolute processor ID offsets for every groups, + * because * 1. We can't assume every processor groups include the same number of * logical processors. - * 2. Every processor groups know its group number and processor IDs within - * the group, but not the global processor IDs. + * 2. Every processor groups know its group number and processor IDs + * within the group, but not the global processor IDs. * 3. We need to list every logical processors by global IDs. - */ - uint32_t* global_proc_index_per_group = - (uint32_t*) HeapAlloc(heap, 0, max_group_count * sizeof(uint32_t)); + */ + uint32_t* global_proc_index_per_group = (uint32_t*)HeapAlloc(heap, 0, max_group_count * sizeof(uint32_t)); if (global_proc_index_per_group == NULL) { cpuinfo_log_error( - "failed to allocate %zu bytes for descriptions of %"PRIu32" processor groups", - max_group_count * sizeof(struct cpuinfo_processor), max_group_count); + "failed to allocate %zu bytes for descriptions of %" PRIu32 " processor groups", + max_group_count * sizeof(struct cpuinfo_processor), + max_group_count); goto clean_up; } - - uint32_t nr_of_processors = - count_logical_processors(max_group_count, global_proc_index_per_group); + + uint32_t nr_of_processors = count_logical_processors(max_group_count, global_proc_index_per_group); processors = HeapAlloc(heap, HEAP_ZERO_MEMORY, nr_of_processors * sizeof(struct cpuinfo_processor)); if (processors == NULL) { cpuinfo_log_error( - "failed to allocate %zu bytes for descriptions of %"PRIu32" logical processors", - nr_of_processors * sizeof(struct cpuinfo_processor), nr_of_processors); + "failed to allocate %zu bytes for descriptions of %" PRIu32 " logical processors", + nr_of_processors * sizeof(struct cpuinfo_processor), + nr_of_processors); goto clean_up; } - /* 2. Read topology information via MSDN API: packages, cores and caches*/ - nr_of_packages = read_packages_for_processors( - processors, nr_of_processors, - global_proc_index_per_group, - chip_info); + /* 2. Read topology information via MSDN API: packages, cores and + * caches*/ + nr_of_packages = + read_packages_for_processors(processors, nr_of_processors, global_proc_index_per_group, chip_info); if (!nr_of_packages) { cpuinfo_log_error("error in reading package information"); goto clean_up; } - cpuinfo_log_debug("detected %"PRIu32" processor package(s)", nr_of_packages); + cpuinfo_log_debug("detected %" PRIu32 " processor package(s)", nr_of_packages); /* We need the EfficiencyClass to parse uarch from the core information, * but we need to iterate first to count cores and allocate memory then - * we will iterate again to read and store data to cpuinfo_core structures. + * we will iterate again to read and store data to cpuinfo_core + * structures. */ - nr_of_cores = read_cores_for_processors( - processors, nr_of_processors, - global_proc_index_per_group, NULL, - chip_info); + nr_of_cores = + read_cores_for_processors(processors, nr_of_processors, global_proc_index_per_group, NULL, chip_info); if (!nr_of_cores) { cpuinfo_log_error("error in reading core information"); goto clean_up; } - cpuinfo_log_debug("detected %"PRIu32" processor core(s)", nr_of_cores); + cpuinfo_log_debug("detected %" PRIu32 " processor core(s)", nr_of_cores); - /* There is no API to read number of caches, so we need to iterate twice on caches: + /* There is no API to read number of caches, so we need to iterate twice + on caches: 1. Count all type of caches -> allocate memory 2. Read out cache data and store to allocated memory */ nr_of_all_caches = read_caches_for_processors( - processors, nr_of_processors, - caches, numbers_of_caches, - global_proc_index_per_group, chip_info); + processors, nr_of_processors, caches, numbers_of_caches, global_proc_index_per_group, chip_info); if (!nr_of_all_caches) { cpuinfo_log_error("error in reading cache information"); goto clean_up; } - cpuinfo_log_debug("detected %"PRIu32" processor cache(s)", nr_of_all_caches); + cpuinfo_log_debug("detected %" PRIu32 " processor cache(s)", nr_of_all_caches); /* 3. Allocate memory for package, cluster, core and cache structures */ packages = HeapAlloc(heap, HEAP_ZERO_MEMORY, nr_of_packages * sizeof(struct cpuinfo_package)); if (packages == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" physical packages", - nr_of_packages * sizeof(struct cpuinfo_package), nr_of_packages); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " physical packages", + nr_of_packages * sizeof(struct cpuinfo_package), + nr_of_packages); goto clean_up; } - /* We don't have cluster information so we explicitly set clusters to equal to cores. */ + /* We don't have cluster information so we explicitly set clusters to + * equal to cores. */ clusters = HeapAlloc(heap, HEAP_ZERO_MEMORY, nr_of_cores * sizeof(struct cpuinfo_cluster)); if (clusters == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" core clusters", - nr_of_cores * sizeof(struct cpuinfo_cluster), nr_of_cores); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " core clusters", + nr_of_cores * sizeof(struct cpuinfo_cluster), + nr_of_cores); goto clean_up; } cores = HeapAlloc(heap, HEAP_ZERO_MEMORY, nr_of_cores * sizeof(struct cpuinfo_core)); if (cores == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" cores", - nr_of_cores * sizeof(struct cpuinfo_core), nr_of_cores); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " cores", + nr_of_cores * sizeof(struct cpuinfo_core), + nr_of_cores); goto clean_up; } - /* We allocate one contiguous cache array for all caches, then use offsets per cache type. */ + /* We allocate one contiguous cache array for all caches, then use + * offsets per cache type. */ caches = HeapAlloc(heap, HEAP_ZERO_MEMORY, nr_of_all_caches * sizeof(struct cpuinfo_cache)); if (caches == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" caches", - nr_of_all_caches * sizeof(struct cpuinfo_cache), nr_of_all_caches); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " caches", + nr_of_all_caches * sizeof(struct cpuinfo_cache), + nr_of_all_caches); goto clean_up; } - /* 4.Read missing topology information that can't be saved without counted - * allocate structures in the first round. + /* 4.Read missing topology information that can't be saved without + * counted allocate structures in the first round. */ nr_of_all_caches = read_caches_for_processors( - processors, nr_of_processors, - caches, numbers_of_caches, global_proc_index_per_group, chip_info); + processors, nr_of_processors, caches, numbers_of_caches, global_proc_index_per_group, chip_info); if (!nr_of_all_caches) { cpuinfo_log_error("error in reading cache information"); goto clean_up; } - nr_of_cores = read_cores_for_processors( - processors, nr_of_processors, - global_proc_index_per_group, cores, - chip_info); + nr_of_cores = + read_cores_for_processors(processors, nr_of_processors, global_proc_index_per_group, cores, chip_info); if (!nr_of_cores) { cpuinfo_log_error("error in reading core information"); goto clean_up; } - /* 5. Now that we read out everything from the system we can, fill the package, cluster - * and core structures respectively. + /* 5. Now that we read out everything from the system we can, fill the + * package, cluster and core structures respectively. */ result = connect_packages_cores_clusters_by_processors( - processors, nr_of_processors, - packages, nr_of_packages, - clusters, - cores, nr_of_cores, - chip_info, - vendor); - if(!result) { + processors, + nr_of_processors, + packages, + nr_of_packages, + clusters, + cores, + nr_of_cores, + chip_info, + vendor); + if (!result) { cpuinfo_log_error("error in connecting information"); goto clean_up; } - /* 6. Count and store uarchs of cores, assuming same uarchs are neighbors */ + /* 6. Count and store uarchs of cores, assuming same uarchs are + * neighbors */ enum cpuinfo_uarch prev_uarch = cpuinfo_uarch_unknown; for (uint32_t i = 0; i < nr_of_cores; i++) { if (prev_uarch != cores[i].uarch) { @@ -278,8 +281,10 @@ bool cpu_info_init_by_logical_sys_info( } uarchs = HeapAlloc(heap, HEAP_ZERO_MEMORY, nr_of_uarchs * sizeof(struct cpuinfo_uarch_info)); if (uarchs == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" uarchs", - nr_of_uarchs * sizeof(struct cpuinfo_uarch_info), nr_of_uarchs); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " uarchs", + nr_of_uarchs * sizeof(struct cpuinfo_uarch_info), + nr_of_uarchs); goto clean_up; } prev_uarch = cpuinfo_uarch_unknown; @@ -318,10 +323,14 @@ bool cpu_info_init_by_logical_sys_info( cpuinfo_cache_count[i] = numbers_of_caches[i]; } cpuinfo_cache[cpuinfo_cache_level_1i] = caches; - cpuinfo_cache[cpuinfo_cache_level_1d] = cpuinfo_cache[cpuinfo_cache_level_1i] + cpuinfo_cache_count[cpuinfo_cache_level_1i]; - cpuinfo_cache[cpuinfo_cache_level_2] = cpuinfo_cache[cpuinfo_cache_level_1d] + cpuinfo_cache_count[cpuinfo_cache_level_1d]; - cpuinfo_cache[cpuinfo_cache_level_3] = cpuinfo_cache[cpuinfo_cache_level_2] + cpuinfo_cache_count[cpuinfo_cache_level_2]; - cpuinfo_cache[cpuinfo_cache_level_4] = cpuinfo_cache[cpuinfo_cache_level_3] + cpuinfo_cache_count[cpuinfo_cache_level_3]; + cpuinfo_cache[cpuinfo_cache_level_1d] = + cpuinfo_cache[cpuinfo_cache_level_1i] + cpuinfo_cache_count[cpuinfo_cache_level_1i]; + cpuinfo_cache[cpuinfo_cache_level_2] = + cpuinfo_cache[cpuinfo_cache_level_1d] + cpuinfo_cache_count[cpuinfo_cache_level_1d]; + cpuinfo_cache[cpuinfo_cache_level_3] = + cpuinfo_cache[cpuinfo_cache_level_2] + cpuinfo_cache_count[cpuinfo_cache_level_2]; + cpuinfo_cache[cpuinfo_cache_level_4] = + cpuinfo_cache[cpuinfo_cache_level_3] + cpuinfo_cache_count[cpuinfo_cache_level_3]; cpuinfo_max_cache_size = cpuinfo_compute_max_cache_size(&processors[0]); result = true; @@ -363,16 +372,13 @@ bool cpu_info_init_by_logical_sys_info( return result; } -static uint32_t count_logical_processors( - const uint32_t max_group_count, - uint32_t* global_proc_index_per_group) -{ +static uint32_t count_logical_processors(const uint32_t max_group_count, uint32_t* global_proc_index_per_group) { uint32_t nr_of_processors = 0; for (uint32_t i = 0; i < max_group_count; i++) { - uint32_t nr_of_processors_per_group = GetMaximumProcessorCount((WORD) i); - cpuinfo_log_debug("detected %"PRIu32" processor(s) in group %"PRIu32"", - nr_of_processors_per_group, i); + uint32_t nr_of_processors_per_group = GetMaximumProcessorCount((WORD)i); + cpuinfo_log_debug( + "detected %" PRIu32 " processor(s) in group %" PRIu32 "", nr_of_processors_per_group, i); global_proc_index_per_group[i] = nr_of_processors; nr_of_processors += nr_of_processors_per_group; } @@ -383,8 +389,7 @@ static uint32_t read_packages_for_processors( struct cpuinfo_processor* processors, const uint32_t number_of_processors, const uint32_t* global_proc_index_per_group, - const struct woa_chip_info *chip_info) -{ + const struct woa_chip_info* chip_info) { return read_all_logical_processor_info_of_relation( RelationProcessorPackage, processors, @@ -401,8 +406,7 @@ uint32_t read_cores_for_processors( const uint32_t number_of_processors, const uint32_t* global_proc_index_per_group, struct cpuinfo_core* cores, - const struct woa_chip_info *chip_info) -{ + const struct woa_chip_info* chip_info) { return read_all_logical_processor_info_of_relation( RelationProcessorCore, processors, @@ -420,8 +424,7 @@ static uint32_t read_caches_for_processors( struct cpuinfo_cache* caches, uint32_t* numbers_of_caches, const uint32_t* global_proc_index_per_group, - const struct woa_chip_info *chip_info) -{ + const struct woa_chip_info* chip_info) { /* Reset processor start indexes */ if (caches) { uint32_t cache_offset = 0; @@ -452,8 +455,7 @@ static uint32_t read_all_logical_processor_info_of_relation( uint32_t* numbers_of_caches, struct cpuinfo_core* cores, const uint32_t* global_proc_index_per_group, - const struct woa_chip_info* chip_info) -{ + const struct woa_chip_info* chip_info) { PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX infos = NULL; uint32_t nr_of_structs = 0; DWORD info_size = 0; @@ -465,76 +467,74 @@ static uint32_t read_all_logical_processor_info_of_relation( const DWORD last_error = GetLastError(); if (last_error != ERROR_INSUFFICIENT_BUFFER) { cpuinfo_log_error( - "failed to query size of processor %"PRIu32" information information: error %"PRIu32"", - (uint32_t)info_type, (uint32_t) last_error); + "failed to query size of processor %" PRIu32 " information information: error %" PRIu32 + "", + (uint32_t)info_type, + (uint32_t)last_error); goto clean_up; } } /* 2. Allocate memory for the information structure */ infos = HeapAlloc(heap, 0, info_size); if (infos == NULL) { - cpuinfo_log_error("failed to allocate %"PRIu32" bytes for logical processor information", - (uint32_t) info_size); + cpuinfo_log_error( + "failed to allocate %" PRIu32 " bytes for logical processor information", (uint32_t)info_size); goto clean_up; } /* 3. Read the information structure */ if (GetLogicalProcessorInformationEx(info_type, infos, &info_size) == FALSE) { - cpuinfo_log_error("failed to query processor %"PRIu32" information: error %"PRIu32"", - (uint32_t)info_type, (uint32_t) GetLastError()); + cpuinfo_log_error( + "failed to query processor %" PRIu32 " information: error %" PRIu32 "", + (uint32_t)info_type, + (uint32_t)GetLastError()); goto clean_up; } /* 4. Parse the structure and store relevant data */ PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX info_end = - (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX) ((uintptr_t) infos + info_size); - for (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX info = infos; - info < info_end; - info = (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX) ((uintptr_t) info + info->Size)) - { + (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX)((uintptr_t)infos + info_size); + for (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX info = infos; info < info_end; + info = (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX)((uintptr_t)info + info->Size)) { if (info->Relationship != info_type) { cpuinfo_log_warning( - "unexpected processor info type (%"PRIu32") for processor information", - (uint32_t) info->Relationship); + "unexpected processor info type (%" PRIu32 ") for processor information", + (uint32_t)info->Relationship); continue; } const uint32_t info_id = nr_of_structs++; - switch(info_type) { + switch (info_type) { case RelationProcessorPackage: result = parse_relation_processor_info( - processors, - number_of_processors, - global_proc_index_per_group, - info, - info_id, - cores, - chip_info); - break; + processors, + number_of_processors, + global_proc_index_per_group, + info, + info_id, + cores, + chip_info); + break; case RelationProcessorCore: result = parse_relation_processor_info( - processors, - number_of_processors, - global_proc_index_per_group, - info, - info_id, - cores, - chip_info); - break; + processors, + number_of_processors, + global_proc_index_per_group, + info, + info_id, + cores, + chip_info); + break; case RelationCache: result = parse_relation_cache_info( - processors, - caches, - numbers_of_caches, - global_proc_index_per_group, - info); - break; + processors, caches, numbers_of_caches, global_proc_index_per_group, info); + break; default: cpuinfo_log_error( - "unexpected processor info type (%"PRIu32") for processor information", - (uint32_t) info->Relationship); + "unexpected processor info type (%" PRIu32 ") for processor information", + (uint32_t)info->Relationship); result = false; - break; + break; } if (!result) { nr_of_structs = 0; @@ -555,43 +555,45 @@ static bool parse_relation_processor_info( PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX info, const uint32_t info_id, struct cpuinfo_core* cores, - const struct woa_chip_info *chip_info) -{ + const struct woa_chip_info* chip_info) { for (uint32_t i = 0; i < info->Processor.GroupCount; i++) { const uint32_t group_id = info->Processor.GroupMask[i].Group; - /* Bitmask representing processors in this group belonging to this package */ + /* Bitmask representing processors in this group belonging to + * this package + */ KAFFINITY group_processors_mask = info->Processor.GroupMask[i].Mask; while (group_processors_mask != 0) { - const uint32_t processor_id_in_group = - low_index_from_kaffinity(group_processors_mask); + const uint32_t processor_id_in_group = low_index_from_kaffinity(group_processors_mask); const uint32_t processor_global_index = global_proc_index_per_group[group_id] + processor_id_in_group; - if(processor_global_index >= nr_of_processors) { - cpuinfo_log_error("unexpected processor index %"PRIu32"", - processor_global_index); + if (processor_global_index >= nr_of_processors) { + cpuinfo_log_error("unexpected processor index %" PRIu32 "", processor_global_index); return false; } - switch(info->Relationship) { + switch (info->Relationship) { case RelationProcessorPackage: store_package_info_per_processor( - processors, processor_global_index, info_id, - group_id, processor_id_in_group); - break; + processors, + processor_global_index, + info_id, + group_id, + processor_id_in_group); + break; case RelationProcessorCore: store_core_info_per_processor( - processors, processor_global_index, - info_id, info, - cores, chip_info); - break; + processors, processor_global_index, info_id, info, cores, chip_info); + break; default: cpuinfo_log_error( - "unexpected processor info type (%"PRIu32") for processor information", - (uint32_t) info->Relationship); - break; + "unexpected processor info type (%" PRIu32 + ") for processor information", + (uint32_t)info->Relationship); + break; } - /* Clear the bits in affinity mask, lower the least set bit. */ + /* Clear the bits in affinity mask, lower the least set + * bit. */ group_processors_mask &= (group_processors_mask - 1); } } @@ -603,8 +605,7 @@ static bool parse_relation_cache_info( struct cpuinfo_cache* caches, uint32_t* numbers_of_caches, const uint32_t* global_proc_index_per_group, - PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX info) -{ + PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX info) { static uint32_t l1i_counter = 0; static uint32_t l1d_counter = 0; static uint32_t l2_counter = 0; @@ -612,45 +613,52 @@ static bool parse_relation_cache_info( /* Count cache types for allocation at first. */ if (caches == NULL) { - switch(info->Cache.Level) { + switch (info->Cache.Level) { case 1: switch (info->Cache.Type) { case CacheInstruction: numbers_of_caches[cpuinfo_cache_level_1i]++; - break; + break; case CacheData: numbers_of_caches[cpuinfo_cache_level_1d]++; - break; + break; case CacheUnified: - break; + break; case CacheTrace: - break; + break; default: - break; + break; } - break; + break; case 2: numbers_of_caches[cpuinfo_cache_level_2]++; - break; + break; case 3: numbers_of_caches[cpuinfo_cache_level_3]++; - break; + break; } return true; } struct cpuinfo_cache* l1i_base = caches; struct cpuinfo_cache* l1d_base = l1i_base + numbers_of_caches[cpuinfo_cache_level_1i]; - struct cpuinfo_cache* l2_base = l1d_base + numbers_of_caches[cpuinfo_cache_level_1d]; - struct cpuinfo_cache* l3_base = l2_base + numbers_of_caches[cpuinfo_cache_level_2]; + struct cpuinfo_cache* l2_base = l1d_base + numbers_of_caches[cpuinfo_cache_level_1d]; + struct cpuinfo_cache* l3_base = l2_base + numbers_of_caches[cpuinfo_cache_level_2]; cpuinfo_log_debug( - "info->Cache.GroupCount:%"PRIu32", info->Cache.GroupMask:%"PRIu32"," - "info->Cache.Level:%"PRIu32", info->Cache.Associativity:%"PRIu32"," - "info->Cache.LineSize:%"PRIu32"," - "info->Cache.CacheSize:%"PRIu32", info->Cache.Type:%"PRIu32"", - info->Cache.GroupCount, (unsigned int)info->Cache.GroupMask.Mask, - info->Cache.Level, info->Cache.Associativity, info->Cache.LineSize, - info->Cache.CacheSize, info->Cache.Type); + "info->Cache.GroupCount:%" PRIu32 ", info->Cache.GroupMask:%" PRIu32 + "," + "info->Cache.Level:%" PRIu32 ", info->Cache.Associativity:%" PRIu32 + "," + "info->Cache.LineSize:%" PRIu32 + "," + "info->Cache.CacheSize:%" PRIu32 ", info->Cache.Type:%" PRIu32 "", + info->Cache.GroupCount, + (unsigned int)info->Cache.GroupMask.Mask, + info->Cache.Level, + info->Cache.Associativity, + info->Cache.LineSize, + info->Cache.CacheSize, + info->Cache.Type); struct cpuinfo_cache* current_cache = NULL; switch (info->Cache.Level) { @@ -659,27 +667,27 @@ static bool parse_relation_cache_info( case CacheInstruction: current_cache = l1i_base + l1i_counter; l1i_counter++; - break; + break; case CacheData: current_cache = l1d_base + l1d_counter; l1d_counter++; - break; + break; case CacheUnified: - break; + break; case CacheTrace: - break; + break; default: - break; + break; } - break; + break; case 2: current_cache = l2_base + l2_counter; l2_counter++; - break; + break; case 3: current_cache = l3_base + l3_counter; l3_counter++; - break; + break; } current_cache->size = info->Cache.CacheSize; current_cache->line_size = info->Cache.LineSize; @@ -688,28 +696,28 @@ static bool parse_relation_cache_info( * so we set partitions to 1 and calculate the expected sets. */ current_cache->partitions = 1; - current_cache->sets = - current_cache->size / current_cache->line_size / current_cache->associativity; + current_cache->sets = current_cache->size / current_cache->line_size / current_cache->associativity; if (info->Cache.Type == CacheUnified) { current_cache->flags = CPUINFO_CACHE_UNIFIED; } for (uint32_t i = 0; i < info->Cache.GroupCount; i++) { - /* Zero GroupCount is valid, GroupMask still can store bits set. */ + /* Zero GroupCount is valid, GroupMask still can store bits set. + */ const uint32_t group_id = info->Cache.GroupMasks[i].Group; - /* Bitmask representing processors in this group belonging to this package */ + /* Bitmask representing processors in this group belonging to + * this package + */ KAFFINITY group_processors_mask = info->Cache.GroupMasks[i].Mask; while (group_processors_mask != 0) { - const uint32_t processor_id_in_group = - low_index_from_kaffinity(group_processors_mask); + const uint32_t processor_id_in_group = low_index_from_kaffinity(group_processors_mask); const uint32_t processor_global_index = global_proc_index_per_group[group_id] + processor_id_in_group; - store_cache_info_per_processor( - processors, processor_global_index, - info, current_cache); + store_cache_info_per_processor(processors, processor_global_index, info, current_cache); - /* Clear the bits in affinity mask, lower the least set bit. */ + /* Clear the bits in affinity mask, lower the least set + * bit. */ group_processors_mask &= (group_processors_mask - 1); } } @@ -721,18 +729,15 @@ static void store_package_info_per_processor( const uint32_t processor_global_index, const uint32_t package_id, const uint32_t group_id, - const uint32_t processor_id_in_group) -{ - processors[processor_global_index].windows_group_id = - (uint16_t) group_id; - processors[processor_global_index].windows_processor_id = - (uint16_t) processor_id_in_group; - - /* As we're counting the number of packages now, we haven't allocated memory for - * cpuinfo_packages yet, so we only set the package pointer's offset now. + const uint32_t processor_id_in_group) { + processors[processor_global_index].windows_group_id = (uint16_t)group_id; + processors[processor_global_index].windows_processor_id = (uint16_t)processor_id_in_group; + + /* As we're counting the number of packages now, we haven't allocated + * memory for cpuinfo_packages yet, so we only set the package pointer's + * offset now. */ - processors[processor_global_index].package = - (const struct cpuinfo_package*) NULL + package_id; + processors[processor_global_index].package = (const struct cpuinfo_package*)NULL + package_id; } void store_core_info_per_processor( @@ -741,22 +746,22 @@ void store_core_info_per_processor( const uint32_t core_id, PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX core_info, struct cpuinfo_core* cores, - const struct woa_chip_info *chip_info) -{ + const struct woa_chip_info* chip_info) { if (cores) { processors[processor_global_index].core = cores + core_id; cores[core_id].core_id = core_id; get_core_uarch_for_efficiency( - chip_info->chip_name, core_info->Processor.EfficiencyClass, - &(cores[core_id].uarch), &(cores[core_id].frequency)); + chip_info->chip_name, + core_info->Processor.EfficiencyClass, + &(cores[core_id].uarch), + &(cores[core_id].frequency)); /* We don't have cluster information, so we handle it as * fixed 1 to (cluster / cores). * Set the cluster offset ID now, as soon as we have the * cluster base address, we'll set the absolute address. */ - processors[processor_global_index].cluster = - (const struct cpuinfo_cluster*) NULL + core_id; + processors[processor_global_index].cluster = (const struct cpuinfo_cluster*)NULL + core_id; } } @@ -764,36 +769,35 @@ static void store_cache_info_per_processor( struct cpuinfo_processor* processors, const uint32_t processor_global_index, PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX info, - struct cpuinfo_cache* current_cache) -{ + struct cpuinfo_cache* current_cache) { if (current_cache->processor_start > processor_global_index) { current_cache->processor_start = processor_global_index; } current_cache->processor_count++; - switch(info->Cache.Level) { + switch (info->Cache.Level) { case 1: switch (info->Cache.Type) { case CacheInstruction: processors[processor_global_index].cache.l1i = current_cache; - break; + break; case CacheData: processors[processor_global_index].cache.l1d = current_cache; - break; + break; case CacheUnified: - break; + break; case CacheTrace: - break; + break; default: - break; + break; } - break; + break; case 2: processors[processor_global_index].cache.l2 = current_cache; - break; + break; case 3: processors[processor_global_index].cache.l3 = current_cache; - break; + break; } } @@ -806,8 +810,7 @@ static bool connect_packages_cores_clusters_by_processors( struct cpuinfo_core* cores, const uint32_t nr_of_cores, const struct woa_chip_info* chip_info, - enum cpuinfo_vendor vendor) -{ + enum cpuinfo_vendor vendor) { /* Adjust core and package pointers for all logical processors. */ for (uint32_t i = nr_of_processors; i != 0; i--) { const uint32_t processor_id = i - 1; @@ -815,22 +818,21 @@ static bool connect_packages_cores_clusters_by_processors( struct cpuinfo_core* core = (struct cpuinfo_core*)processor->core; - /* We stored the offset of pointers when we haven't allocated memory - * for packages and clusters, so now add offsets to base addresses. + /* We stored the offset of pointers when we haven't allocated + * memory for packages and clusters, so now add offsets to base + * addresses. */ struct cpuinfo_package* package = - (struct cpuinfo_package*) ((uintptr_t) packages + (uintptr_t) processor->package); - if (package < packages || - package >= (packages + nr_of_packages)) { + (struct cpuinfo_package*)((uintptr_t)packages + (uintptr_t)processor->package); + if (package < packages || package >= (packages + nr_of_packages)) { cpuinfo_log_error("invalid package indexing"); return false; } processor->package = package; struct cpuinfo_cluster* cluster = - (struct cpuinfo_cluster*) ((uintptr_t) clusters + (uintptr_t) processor->cluster); - if (cluster < clusters || - cluster >= (clusters + nr_of_cores)) { + (struct cpuinfo_cluster*)((uintptr_t)clusters + (uintptr_t)processor->cluster); + if (cluster < clusters || cluster >= (clusters + nr_of_cores)) { cpuinfo_log_error("invalid cluster indexing"); return false; } @@ -839,30 +841,34 @@ static bool connect_packages_cores_clusters_by_processors( if (chip_info) { size_t converted_chars = 0; if (!WideCharToMultiByte( - CP_UTF8, - WC_ERR_INVALID_CHARS, - chip_info->chip_name_string, - -1, - package->name, - CPUINFO_PACKAGE_NAME_MAX, - NULL, - NULL)) { + CP_UTF8, + WC_ERR_INVALID_CHARS, + chip_info->chip_name_string, + -1, + package->name, + CPUINFO_PACKAGE_NAME_MAX, + NULL, + NULL)) { cpuinfo_log_error("cpu name character conversion error"); return false; }; } - /* Set start indexes and counts per packages / clusters / cores - going backwards */ + /* Set start indexes and counts per packages / clusters / cores + * - going backwards */ - /* This can be overwritten by lower-index processors on the same package. */ + /* This can be overwritten by lower-index processors on the same + * package. */ package->processor_start = processor_id; package->processor_count++; - /* This can be overwritten by lower-index processors on the same cluster. */ + /* This can be overwritten by lower-index processors on the same + * cluster. */ cluster->processor_start = processor_id; cluster->processor_count++; - /* This can be overwritten by lower-index processors on the same core. */ + /* This can be overwritten by lower-index processors on the same + * core. */ core->processor_start = processor_id; core->processor_count++; } @@ -871,14 +877,16 @@ static bool connect_packages_cores_clusters_by_processors( const uint32_t global_core_id = i - 1; struct cpuinfo_core* core = cores + global_core_id; const struct cpuinfo_processor* processor = processors + core->processor_start; - struct cpuinfo_package* package = (struct cpuinfo_package*) processor->package; - struct cpuinfo_cluster* cluster = (struct cpuinfo_cluster*) processor->cluster; + struct cpuinfo_package* package = (struct cpuinfo_package*)processor->package; + struct cpuinfo_cluster* cluster = (struct cpuinfo_cluster*)processor->cluster; core->package = package; core->cluster = cluster; core->vendor = vendor; - /* This can be overwritten by lower-index cores on the same cluster/package. */ + /* This can be overwritten by lower-index cores on the same + * cluster/package. + */ cluster->core_start = global_core_id; cluster->core_count++; package->core_start = global_core_id; @@ -896,6 +904,6 @@ static bool connect_packages_cores_clusters_by_processors( static inline uint32_t low_index_from_kaffinity(KAFFINITY kaffinity) { unsigned long index; - _BitScanForward64(&index, (unsigned __int64) kaffinity); - return (uint32_t) index; + _BitScanForward64(&index, (unsigned __int64)kaffinity); + return (uint32_t)index; } diff --git a/src/arm/windows/init.c b/src/arm/windows/init.c index ec835560..79828e6e 100644 --- a/src/arm/windows/init.c +++ b/src/arm/windows/init.c @@ -1,7 +1,7 @@ -#include +#include #include +#include #include -#include #include #include @@ -17,88 +17,50 @@ static struct woa_chip_info* get_system_info_from_registry(void); static struct woa_chip_info woa_chip_unknown = { L"Unknown", woa_chip_name_unknown, - { - { - cpuinfo_vendor_unknown, - cpuinfo_uarch_unknown, - 0 - } - } -}; + {{cpuinfo_vendor_unknown, cpuinfo_uarch_unknown, 0}}}; /* Please add new SoC/chip info here! */ static struct woa_chip_info woa_chips[] = { /* Microsoft SQ1 Kryo 495 4 + 4 cores (3 GHz + 1.80 GHz) */ - { - L"Microsoft SQ1", - woa_chip_name_microsoft_sq_1, - { - { - cpuinfo_vendor_arm, - cpuinfo_uarch_cortex_a55, - 1800000000, - }, - { - cpuinfo_vendor_arm, - cpuinfo_uarch_cortex_a76, - 3000000000, - } - } - }, + {L"Microsoft SQ1", + woa_chip_name_microsoft_sq_1, + {{ + cpuinfo_vendor_arm, + cpuinfo_uarch_cortex_a55, + 1800000000, + }, + { + cpuinfo_vendor_arm, + cpuinfo_uarch_cortex_a76, + 3000000000, + }}}, /* Microsoft SQ2 Kryo 495 4 + 4 cores (3.15 GHz + 2.42 GHz) */ - { - L"Microsoft SQ2", - woa_chip_name_microsoft_sq_2, - { - { - cpuinfo_vendor_arm, - cpuinfo_uarch_cortex_a55, - 2420000000, - }, - { - cpuinfo_vendor_arm, - cpuinfo_uarch_cortex_a76, - 3150000000 - } - } - }, + {L"Microsoft SQ2", + woa_chip_name_microsoft_sq_2, + {{ + cpuinfo_vendor_arm, + cpuinfo_uarch_cortex_a55, + 2420000000, + }, + {cpuinfo_vendor_arm, cpuinfo_uarch_cortex_a76, 3150000000}}}, /* Microsoft Windows Dev Kit 2023 */ - { - L"Snapdragon Compute Platform", - woa_chip_name_microsoft_sq_3, - { - { - cpuinfo_vendor_arm, - cpuinfo_uarch_cortex_a78, - 2420000000, - }, - { - cpuinfo_vendor_arm, - cpuinfo_uarch_cortex_x1, - 3000000000 - } - } - }, + {L"Snapdragon Compute Platform", + woa_chip_name_microsoft_sq_3, + {{ + cpuinfo_vendor_arm, + cpuinfo_uarch_cortex_a78, + 2420000000, + }, + {cpuinfo_vendor_arm, cpuinfo_uarch_cortex_x1, 3000000000}}}, /* Ampere Altra */ - { - L"Ampere(R) Altra(R) Processor", - woa_chip_name_ampere_altra, - { - { - cpuinfo_vendor_arm, - cpuinfo_uarch_neoverse_n1, - 3000000000 - } - } - } -}; + {L"Ampere(R) Altra(R) Processor", + woa_chip_name_ampere_altra, + {{cpuinfo_vendor_arm, cpuinfo_uarch_neoverse_n1, 3000000000}}}}; -BOOL CALLBACK cpuinfo_arm_windows_init( - PINIT_ONCE init_once, PVOID parameter, PVOID* context) -{ - struct woa_chip_info *chip_info = NULL; +BOOL CALLBACK cpuinfo_arm_windows_init(PINIT_ONCE init_once, PVOID parameter, PVOID* context) { + struct woa_chip_info* chip_info = NULL; enum cpuinfo_vendor vendor = cpuinfo_vendor_unknown; - + set_cpuinfo_isa_fields(); chip_info = get_system_info_from_registry(); @@ -112,15 +74,15 @@ BOOL CALLBACK cpuinfo_arm_windows_init( } bool get_core_uarch_for_efficiency( - enum woa_chip_name chip, BYTE EfficiencyClass, - enum cpuinfo_uarch* uarch, uint64_t* frequency) -{ + enum woa_chip_name chip, + BYTE EfficiencyClass, + enum cpuinfo_uarch* uarch, + uint64_t* frequency) { /* For currently supported WoA chips, the Efficiency class selects * the pre-defined little and big core. * Any further supported SoC's logic should be implemented here. */ - if (uarch && frequency && chip < woa_chip_name_last && - EfficiencyClass < MAX_WOA_VALID_EFFICIENCY_CLASSES) { + if (uarch && frequency && chip < woa_chip_name_last && EfficiencyClass < MAX_WOA_VALID_EFFICIENCY_CLASSES) { *uarch = woa_chips[chip].uarchs[EfficiencyClass].uarch; *frequency = woa_chips[chip].uarchs[EfficiencyClass].frequency; return true; @@ -130,14 +92,11 @@ bool get_core_uarch_for_efficiency( /* Static helper functions */ -static wchar_t* read_registry( - LPCWSTR subkey, - LPCWSTR value) -{ +static wchar_t* read_registry(LPCWSTR subkey, LPCWSTR value) { DWORD key_type = 0; DWORD data_size = 0; const DWORD flags = RRF_RT_REG_SZ; /* Only read strings (REG_SZ) */ - wchar_t *text_buffer = NULL; + wchar_t* text_buffer = NULL; LSTATUS result = 0; HANDLE heap = GetProcessHeap(); @@ -176,8 +135,7 @@ static wchar_t* read_registry( return text_buffer; } -static struct woa_chip_info* get_system_info_from_registry(void) -{ +static struct woa_chip_info* get_system_info_from_registry(void) { wchar_t* text_buffer = NULL; LPCWSTR cpu0_subkey = L"HARDWARE\\DESCRIPTION\\System\\CentralProcessor\\0"; LPCWSTR chip_name_value = L"ProcessorNameString"; @@ -185,23 +143,27 @@ static struct woa_chip_info* get_system_info_from_registry(void) HANDLE heap = GetProcessHeap(); - /* Read processor model name from registry and find in the hard-coded list. */ + /* Read processor model name from registry and find in the hard-coded + * list. */ text_buffer = read_registry(cpu0_subkey, chip_name_value); if (text_buffer == NULL) { cpuinfo_log_error("Registry read error"); return NULL; } - for (uint32_t i = 0; i < (uint32_t) woa_chip_name_last; i++) { + for (uint32_t i = 0; i < (uint32_t)woa_chip_name_last; i++) { size_t compare_length = wcsnlen(woa_chips[i].chip_name_string, CPUINFO_PACKAGE_NAME_MAX); int compare_result = wcsncmp(text_buffer, woa_chips[i].chip_name_string, compare_length); if (compare_result == 0) { - chip_info = woa_chips+i; + chip_info = woa_chips + i; break; } } if (chip_info == NULL) { - /* No match was found, so print a warning and assign the unknown case. */ - cpuinfo_log_error("Unknown chip model name '%ls'.\nPlease add new Windows on Arm SoC/chip support to arm/windows/init.c!", text_buffer); + /* No match was found, so print a warning and assign the unknown + * case. */ + cpuinfo_log_error( + "Unknown chip model name '%ls'.\nPlease add new Windows on Arm SoC/chip support to arm/windows/init.c!", + text_buffer); } else { cpuinfo_log_debug("detected chip model name: %s", chip_info->chip_name_string); } @@ -210,8 +172,7 @@ static struct woa_chip_info* get_system_info_from_registry(void) return chip_info; } -static void set_cpuinfo_isa_fields(void) -{ +static void set_cpuinfo_isa_fields(void) { cpuinfo_isa.atomics = IsProcessorFeaturePresent(PF_ARM_V81_ATOMIC_INSTRUCTIONS_AVAILABLE) != 0; const bool dotprod = IsProcessorFeaturePresent(PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE) != 0; @@ -220,13 +181,14 @@ static void set_cpuinfo_isa_fields(void) SYSTEM_INFO system_info; GetSystemInfo(&system_info); switch (system_info.wProcessorLevel) { - case 0x803: // Kryo 385 Silver (Snapdragon 850) + case 0x803: // Kryo 385 Silver (Snapdragon 850) cpuinfo_isa.fp16arith = dotprod; cpuinfo_isa.rdm = dotprod; break; default: - // Assume that Dot Product support implies FP16 arithmetics and RDM support. - // ARM manuals don't guarantee that, but it holds in practice. + // Assume that Dot Product support implies FP16 + // arithmetics and RDM support. ARM manuals don't + // guarantee that, but it holds in practice. cpuinfo_isa.fp16arith = dotprod; cpuinfo_isa.rdm = dotprod; break; diff --git a/src/arm/windows/windows-arm-init.h b/src/arm/windows/windows-arm-init.h index 31181c03..36fa061a 100644 --- a/src/arm/windows/windows-arm-init.h +++ b/src/arm/windows/windows-arm-init.h @@ -1,7 +1,7 @@ #pragma once /* Efficiency class = 0 means little core, while 1 means big core for now. */ -#define MAX_WOA_VALID_EFFICIENCY_CLASSES 2 +#define MAX_WOA_VALID_EFFICIENCY_CLASSES 2 /* List of known and supported Windows on Arm SoCs/chips. */ enum woa_chip_name { @@ -30,9 +30,9 @@ struct woa_chip_info { }; bool get_core_uarch_for_efficiency( - enum woa_chip_name chip, BYTE EfficiencyClass, - enum cpuinfo_uarch* uarch, uint64_t* frequency); + enum woa_chip_name chip, + BYTE EfficiencyClass, + enum cpuinfo_uarch* uarch, + uint64_t* frequency); -bool cpu_info_init_by_logical_sys_info( - const struct woa_chip_info *chip_info, - enum cpuinfo_vendor vendor); +bool cpu_info_init_by_logical_sys_info(const struct woa_chip_info* chip_info, enum cpuinfo_vendor vendor); diff --git a/src/cache.c b/src/cache.c index b976b879..2eb4b16d 100644 --- a/src/cache.c +++ b/src/cache.c @@ -3,16 +3,15 @@ #include #include - uint32_t cpuinfo_compute_max_cache_size(const struct cpuinfo_processor* processor) { - if (processor->cache.l4 != NULL) { - return processor->cache.l4->size; - } else if (processor->cache.l3 != NULL) { - return processor->cache.l3->size; - } else if (processor->cache.l2 != NULL) { - return processor->cache.l2->size; - } else if (processor->cache.l1d != NULL) { - return processor->cache.l1d->size; - } - return 0; + if (processor->cache.l4 != NULL) { + return processor->cache.l4->size; + } else if (processor->cache.l3 != NULL) { + return processor->cache.l3->size; + } else if (processor->cache.l2 != NULL) { + return processor->cache.l2->size; + } else if (processor->cache.l1d != NULL) { + return processor->cache.l1d->size; + } + return 0; } diff --git a/src/cpuinfo/common.h b/src/cpuinfo/common.h index b2b404d7..5aa7c839 100644 --- a/src/cpuinfo/common.h +++ b/src/cpuinfo/common.h @@ -8,33 +8,32 @@ #pragma once - -#define CPUINFO_COUNT_OF(array) (sizeof(array) / sizeof(0[array])) +#define CPUINFO_COUNT_OF(array) (sizeof(array) / sizeof(0 [array])) #if defined(__GNUC__) - #define CPUINFO_LIKELY(condition) (__builtin_expect(!!(condition), 1)) - #define CPUINFO_UNLIKELY(condition) (__builtin_expect(!!(condition), 0)) +#define CPUINFO_LIKELY(condition) (__builtin_expect(!!(condition), 1)) +#define CPUINFO_UNLIKELY(condition) (__builtin_expect(!!(condition), 0)) #else - #define CPUINFO_LIKELY(condition) (!!(condition)) - #define CPUINFO_UNLIKELY(condition) (!!(condition)) +#define CPUINFO_LIKELY(condition) (!!(condition)) +#define CPUINFO_UNLIKELY(condition) (!!(condition)) #endif #ifndef CPUINFO_INTERNAL - #if defined(__ELF__) - #define CPUINFO_INTERNAL __attribute__((__visibility__("internal"))) - #elif defined(__MACH__) - #define CPUINFO_INTERNAL __attribute__((__visibility__("hidden"))) - #else - #define CPUINFO_INTERNAL - #endif +#if defined(__ELF__) +#define CPUINFO_INTERNAL __attribute__((__visibility__("internal"))) +#elif defined(__MACH__) +#define CPUINFO_INTERNAL __attribute__((__visibility__("hidden"))) +#else +#define CPUINFO_INTERNAL +#endif #endif #ifndef CPUINFO_PRIVATE - #if defined(__ELF__) - #define CPUINFO_PRIVATE __attribute__((__visibility__("hidden"))) - #elif defined(__MACH__) - #define CPUINFO_PRIVATE __attribute__((__visibility__("hidden"))) - #else - #define CPUINFO_PRIVATE - #endif +#if defined(__ELF__) +#define CPUINFO_PRIVATE __attribute__((__visibility__("hidden"))) +#elif defined(__MACH__) +#define CPUINFO_PRIVATE __attribute__((__visibility__("hidden"))) +#else +#define CPUINFO_PRIVATE +#endif #endif diff --git a/src/cpuinfo/internal-api.h b/src/cpuinfo/internal-api.h index 69a9ec98..d566034e 100644 --- a/src/cpuinfo/internal-api.h +++ b/src/cpuinfo/internal-api.h @@ -1,22 +1,21 @@ #pragma once -#include #include +#include #if defined(_WIN32) || defined(__CYGWIN__) - #include +#include #endif #include #include - enum cpuinfo_cache_level { - cpuinfo_cache_level_1i = 0, - cpuinfo_cache_level_1d = 1, - cpuinfo_cache_level_2 = 2, - cpuinfo_cache_level_3 = 3, - cpuinfo_cache_level_4 = 4, + cpuinfo_cache_level_1i = 0, + cpuinfo_cache_level_1d = 1, + cpuinfo_cache_level_2 = 2, + cpuinfo_cache_level_3 = 3, + cpuinfo_cache_level_4 = 4, cpuinfo_cache_level_max = 5, }; @@ -36,26 +35,26 @@ extern CPUINFO_INTERNAL uint32_t cpuinfo_cache_count[cpuinfo_cache_level_max]; extern CPUINFO_INTERNAL uint32_t cpuinfo_max_cache_size; #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 || CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 - extern CPUINFO_INTERNAL struct cpuinfo_uarch_info* cpuinfo_uarchs; - extern CPUINFO_INTERNAL uint32_t cpuinfo_uarchs_count; +extern CPUINFO_INTERNAL struct cpuinfo_uarch_info* cpuinfo_uarchs; +extern CPUINFO_INTERNAL uint32_t cpuinfo_uarchs_count; #else - extern CPUINFO_INTERNAL struct cpuinfo_uarch_info cpuinfo_global_uarch; +extern CPUINFO_INTERNAL struct cpuinfo_uarch_info cpuinfo_global_uarch; #endif #ifdef __linux__ - extern CPUINFO_INTERNAL uint32_t cpuinfo_linux_cpu_max; - extern CPUINFO_INTERNAL const struct cpuinfo_processor** cpuinfo_linux_cpu_to_processor_map; - extern CPUINFO_INTERNAL const struct cpuinfo_core** cpuinfo_linux_cpu_to_core_map; +extern CPUINFO_INTERNAL uint32_t cpuinfo_linux_cpu_max; +extern CPUINFO_INTERNAL const struct cpuinfo_processor** cpuinfo_linux_cpu_to_processor_map; +extern CPUINFO_INTERNAL const struct cpuinfo_core** cpuinfo_linux_cpu_to_core_map; #endif CPUINFO_PRIVATE void cpuinfo_x86_mach_init(void); CPUINFO_PRIVATE void cpuinfo_x86_linux_init(void); #if defined(_WIN32) || defined(__CYGWIN__) - #if CPUINFO_ARCH_ARM64 - CPUINFO_PRIVATE BOOL CALLBACK cpuinfo_arm_windows_init(PINIT_ONCE init_once, PVOID parameter, PVOID* context); - #else - CPUINFO_PRIVATE BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PVOID* context); - #endif +#if CPUINFO_ARCH_ARM64 +CPUINFO_PRIVATE BOOL CALLBACK cpuinfo_arm_windows_init(PINIT_ONCE init_once, PVOID parameter, PVOID* context); +#else +CPUINFO_PRIVATE BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PVOID* context); +#endif #endif CPUINFO_PRIVATE void cpuinfo_arm_mach_init(void); CPUINFO_PRIVATE void cpuinfo_arm_linux_init(void); diff --git a/src/cpuinfo/log.h b/src/cpuinfo/log.h index 5bd43055..52e3475f 100644 --- a/src/cpuinfo/log.h +++ b/src/cpuinfo/log.h @@ -5,7 +5,7 @@ #include #ifndef CPUINFO_LOG_LEVEL - #error "Undefined CPUINFO_LOG_LEVEL" +#error "Undefined CPUINFO_LOG_LEVEL" #endif #define CPUINFO_LOG_NONE 0 @@ -16,88 +16,87 @@ #define CPUINFO_LOG_DEBUG 5 #ifndef CPUINFO_LOG_DEBUG_PARSERS - #define CPUINFO_LOG_DEBUG_PARSERS 0 +#define CPUINFO_LOG_DEBUG_PARSERS 0 #endif - #ifdef __cplusplus extern "C" { #endif #if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_DEBUG - void cpuinfo_vlog_debug(const char* format, va_list args); +void cpuinfo_vlog_debug(const char* format, va_list args); #endif #if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_INFO - void cpuinfo_vlog_info(const char* format, va_list args); +void cpuinfo_vlog_info(const char* format, va_list args); #endif #if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_WARNING - void cpuinfo_vlog_warning(const char* format, va_list args); +void cpuinfo_vlog_warning(const char* format, va_list args); #endif #if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_ERROR - void cpuinfo_vlog_error(const char* format, va_list args); +void cpuinfo_vlog_error(const char* format, va_list args); #endif #if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_FATAL - void cpuinfo_vlog_fatal(const char* format, va_list args); +void cpuinfo_vlog_fatal(const char* format, va_list args); #endif #ifdef __cplusplus -} // extern "C" +} // extern "C" #endif #ifndef CPUINFO_LOG_ARGUMENTS_FORMAT - #ifdef __GNUC__ - #define CPUINFO_LOG_ARGUMENTS_FORMAT __attribute__((__format__(__printf__, 1, 2))) - #else - #define CPUINFO_LOG_ARGUMENTS_FORMAT - #endif +#ifdef __GNUC__ +#define CPUINFO_LOG_ARGUMENTS_FORMAT __attribute__((__format__(__printf__, 1, 2))) +#else +#define CPUINFO_LOG_ARGUMENTS_FORMAT +#endif #endif CPUINFO_LOG_ARGUMENTS_FORMAT inline static void cpuinfo_log_debug(const char* format, ...) { - #if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_DEBUG - va_list args; - va_start(args, format); - cpuinfo_vlog_debug(format, args); - va_end(args); - #endif +#if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_DEBUG + va_list args; + va_start(args, format); + cpuinfo_vlog_debug(format, args); + va_end(args); +#endif } CPUINFO_LOG_ARGUMENTS_FORMAT inline static void cpuinfo_log_info(const char* format, ...) { - #if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_INFO - va_list args; - va_start(args, format); - cpuinfo_vlog_info(format, args); - va_end(args); - #endif +#if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_INFO + va_list args; + va_start(args, format); + cpuinfo_vlog_info(format, args); + va_end(args); +#endif } CPUINFO_LOG_ARGUMENTS_FORMAT inline static void cpuinfo_log_warning(const char* format, ...) { - #if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_WARNING - va_list args; - va_start(args, format); - cpuinfo_vlog_warning(format, args); - va_end(args); - #endif +#if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_WARNING + va_list args; + va_start(args, format); + cpuinfo_vlog_warning(format, args); + va_end(args); +#endif } CPUINFO_LOG_ARGUMENTS_FORMAT inline static void cpuinfo_log_error(const char* format, ...) { - #if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_ERROR - va_list args; - va_start(args, format); - cpuinfo_vlog_error(format, args); - va_end(args); - #endif +#if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_ERROR + va_list args; + va_start(args, format); + cpuinfo_vlog_error(format, args); + va_end(args); +#endif } CPUINFO_LOG_ARGUMENTS_FORMAT inline static void cpuinfo_log_fatal(const char* format, ...) { - #if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_FATAL - va_list args; - va_start(args, format); - cpuinfo_vlog_fatal(format, args); - va_end(args); - #endif +#if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_FATAL + va_list args; + va_start(args, format); + cpuinfo_vlog_fatal(format, args); + va_end(args); +#endif abort(); } \ No newline at end of file diff --git a/src/cpuinfo/utils.h b/src/cpuinfo/utils.h index 6cfaca7b..6556a660 100644 --- a/src/cpuinfo/utils.h +++ b/src/cpuinfo/utils.h @@ -5,18 +5,17 @@ #endif #include - inline static uint32_t bit_length(uint32_t n) { const uint32_t n_minus_1 = n - 1; if (n_minus_1 == 0) { return 0; } else { - #ifdef _MSC_VER - unsigned long bsr; - _BitScanReverse(&bsr, n_minus_1); - return bsr + 1; - #else - return 32 - __builtin_clz(n_minus_1); - #endif +#ifdef _MSC_VER + unsigned long bsr; + _BitScanReverse(&bsr, n_minus_1); + return bsr + 1; +#else + return 32 - __builtin_clz(n_minus_1); +#endif } } diff --git a/src/emscripten/init.c b/src/emscripten/init.c index ce4bdea2..c2393243 100644 --- a/src/emscripten/init.c +++ b/src/emscripten/init.c @@ -1,8 +1,8 @@ +#include #include #include #include #include -#include #include @@ -10,10 +10,9 @@ #include #include - static const volatile float infinity = INFINITY; -static struct cpuinfo_package static_package = { }; +static struct cpuinfo_package static_package = {}; static struct cpuinfo_cache static_x86_l3 = { .size = 2 * 1024 * 1024, @@ -37,7 +36,7 @@ void cpuinfo_emscripten_init(void) { if (logical_cores_count <= 0) { logical_cores_count = 1; } - uint32_t processor_count = (uint32_t) logical_cores_count; + uint32_t processor_count = (uint32_t)logical_cores_count; uint32_t core_count = processor_count; uint32_t cluster_count = 1; uint32_t big_cluster_core_count = core_count; @@ -60,41 +59,53 @@ void cpuinfo_emscripten_init(void) { processors = calloc(processor_count, sizeof(struct cpuinfo_processor)); if (processors == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" logical processors", - processor_count * sizeof(struct cpuinfo_processor), processor_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " logical processors", + processor_count * sizeof(struct cpuinfo_processor), + processor_count); goto cleanup; } cores = calloc(processor_count, sizeof(struct cpuinfo_core)); if (cores == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" cores", - processor_count * sizeof(struct cpuinfo_core), processor_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " cores", + processor_count * sizeof(struct cpuinfo_core), + processor_count); goto cleanup; } clusters = calloc(cluster_count, sizeof(struct cpuinfo_cluster)); if (clusters == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" clusters", - cluster_count * sizeof(struct cpuinfo_cluster), cluster_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " clusters", + cluster_count * sizeof(struct cpuinfo_cluster), + cluster_count); goto cleanup; } l1i = calloc(core_count, sizeof(struct cpuinfo_cache)); if (l1i == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L1I caches", - core_count * sizeof(struct cpuinfo_cache), core_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L1I caches", + core_count * sizeof(struct cpuinfo_cache), + core_count); goto cleanup; } l1d = calloc(core_count, sizeof(struct cpuinfo_cache)); if (l1d == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L1D caches", - core_count * sizeof(struct cpuinfo_cache), core_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L1D caches", + core_count * sizeof(struct cpuinfo_cache), + core_count); goto cleanup; } l2 = calloc(l2_count, sizeof(struct cpuinfo_cache)); if (l2 == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L2 caches", - l2_count * sizeof(struct cpuinfo_cache), l2_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L2 caches", + l2_count * sizeof(struct cpuinfo_cache), + l2_count); goto cleanup; } @@ -109,30 +120,30 @@ void cpuinfo_emscripten_init(void) { for (uint32_t i = 0; i < core_count; i++) { for (uint32_t j = 0; j < processors_per_core; j++) { - processors[i * processors_per_core + j] = (struct cpuinfo_processor) { + processors[i * processors_per_core + j] = (struct cpuinfo_processor){ .smt_id = j, .core = cores + i, - .cluster = clusters + (uint32_t) (i >= big_cluster_core_count), + .cluster = clusters + (uint32_t)(i >= big_cluster_core_count), .package = &static_package, .cache.l1i = l1i + i, .cache.l1d = l1d + i, - .cache.l2 = is_x86 ? l2 + i : l2 + (uint32_t) (i >= big_cluster_core_count), + .cache.l2 = is_x86 ? l2 + i : l2 + (uint32_t)(i >= big_cluster_core_count), .cache.l3 = is_x86 ? &static_x86_l3 : NULL, }; } - cores[i] = (struct cpuinfo_core) { + cores[i] = (struct cpuinfo_core){ .processor_start = i * processors_per_core, .processor_count = processors_per_core, .core_id = i, - .cluster = clusters + (uint32_t) (i >= big_cluster_core_count), + .cluster = clusters + (uint32_t)(i >= big_cluster_core_count), .package = &static_package, .vendor = cpuinfo_vendor_unknown, .uarch = cpuinfo_uarch_unknown, .frequency = 0, }; - l1i[i] = (struct cpuinfo_cache) { + l1i[i] = (struct cpuinfo_cache){ .size = 32 * 1024, .associativity = 4, .sets = 128, @@ -142,7 +153,7 @@ void cpuinfo_emscripten_init(void) { .processor_count = processors_per_core, }; - l1d[i] = (struct cpuinfo_cache) { + l1d[i] = (struct cpuinfo_cache){ .size = 32 * 1024, .associativity = 4, .sets = 128, @@ -153,7 +164,7 @@ void cpuinfo_emscripten_init(void) { }; if (is_x86) { - l2[i] = (struct cpuinfo_cache) { + l2[i] = (struct cpuinfo_cache){ .size = 256 * 1024, .associativity = 8, .sets = 512, @@ -166,7 +177,7 @@ void cpuinfo_emscripten_init(void) { } if (is_x86) { - clusters[0] = (struct cpuinfo_cluster) { + clusters[0] = (struct cpuinfo_cluster){ .processor_start = 0, .processor_count = processor_count, .core_start = 0, @@ -180,7 +191,7 @@ void cpuinfo_emscripten_init(void) { static_x86_l3.processor_count = processor_count; } else { - clusters[0] = (struct cpuinfo_cluster) { + clusters[0] = (struct cpuinfo_cluster){ .processor_start = 0, .processor_count = big_cluster_core_count, .core_start = 0, @@ -192,7 +203,7 @@ void cpuinfo_emscripten_init(void) { .frequency = 0, }; - l2[0] = (struct cpuinfo_cache) { + l2[0] = (struct cpuinfo_cache){ .size = 1024 * 1024, .associativity = 8, .sets = 2048, @@ -203,7 +214,7 @@ void cpuinfo_emscripten_init(void) { }; if (cluster_count > 1) { - l2[1] = (struct cpuinfo_cache) { + l2[1] = (struct cpuinfo_cache){ .size = 256 * 1024, .associativity = 8, .sets = 512, @@ -213,7 +224,7 @@ void cpuinfo_emscripten_init(void) { .processor_count = processor_count - big_cluster_core_count, }; - clusters[1] = (struct cpuinfo_cluster) { + clusters[1] = (struct cpuinfo_cluster){ .processor_start = big_cluster_core_count, .processor_count = processor_count - big_cluster_core_count, .core_start = big_cluster_core_count, @@ -230,9 +241,9 @@ void cpuinfo_emscripten_init(void) { /* Commit changes */ cpuinfo_cache[cpuinfo_cache_level_1i] = l1i; cpuinfo_cache[cpuinfo_cache_level_1d] = l1d; - cpuinfo_cache[cpuinfo_cache_level_2] = l2; + cpuinfo_cache[cpuinfo_cache_level_2] = l2; if (is_x86) { - cpuinfo_cache[cpuinfo_cache_level_3] = &static_x86_l3; + cpuinfo_cache[cpuinfo_cache_level_3] = &static_x86_l3; } cpuinfo_processors = processors; @@ -242,12 +253,12 @@ void cpuinfo_emscripten_init(void) { cpuinfo_cache_count[cpuinfo_cache_level_1i] = processor_count; cpuinfo_cache_count[cpuinfo_cache_level_1d] = processor_count; - cpuinfo_cache_count[cpuinfo_cache_level_2] = l2_count; + cpuinfo_cache_count[cpuinfo_cache_level_2] = l2_count; if (is_x86) { - cpuinfo_cache_count[cpuinfo_cache_level_3] = 1; + cpuinfo_cache_count[cpuinfo_cache_level_3] = 1; } - cpuinfo_global_uarch = (struct cpuinfo_uarch_info) { + cpuinfo_global_uarch = (struct cpuinfo_uarch_info){ .uarch = cpuinfo_uarch_unknown, .processor_count = processor_count, .core_count = core_count, diff --git a/src/init.c b/src/init.c index 57482715..1ab9b5ac 100644 --- a/src/init.c +++ b/src/init.c @@ -1,7 +1,7 @@ #if defined(_WIN32) || defined(__CYGWIN__) - #include +#include #elif !defined(__EMSCRIPTEN__) || defined(__EMSCRIPTEN_PTHREADS__) - #include +#include #endif #include @@ -9,59 +9,57 @@ #include #ifdef __APPLE__ - #include "TargetConditionals.h" +#include "TargetConditionals.h" #endif - #if defined(_WIN32) || defined(__CYGWIN__) - static INIT_ONCE init_guard = INIT_ONCE_STATIC_INIT; +static INIT_ONCE init_guard = INIT_ONCE_STATIC_INIT; #elif !defined(__EMSCRIPTEN__) || defined(__EMSCRIPTEN_PTHREADS__) - static pthread_once_t init_guard = PTHREAD_ONCE_INIT; +static pthread_once_t init_guard = PTHREAD_ONCE_INIT; #else - static bool init_guard = false; +static bool init_guard = false; #endif bool CPUINFO_ABI cpuinfo_initialize(void) { #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - #if defined(__MACH__) && defined(__APPLE__) - pthread_once(&init_guard, &cpuinfo_x86_mach_init); - #elif defined(__linux__) - pthread_once(&init_guard, &cpuinfo_x86_linux_init); - #elif defined(_WIN32) || defined(__CYGWIN__) - InitOnceExecuteOnce(&init_guard, &cpuinfo_x86_windows_init, NULL, NULL); - #else - cpuinfo_log_error("operating system is not supported in cpuinfo"); - #endif +#if defined(__MACH__) && defined(__APPLE__) + pthread_once(&init_guard, &cpuinfo_x86_mach_init); +#elif defined(__linux__) + pthread_once(&init_guard, &cpuinfo_x86_linux_init); +#elif defined(_WIN32) || defined(__CYGWIN__) + InitOnceExecuteOnce(&init_guard, &cpuinfo_x86_windows_init, NULL, NULL); +#else + cpuinfo_log_error("operating system is not supported in cpuinfo"); +#endif #elif CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 - #if defined(__linux__) - pthread_once(&init_guard, &cpuinfo_arm_linux_init); - #elif defined(__MACH__) && defined(__APPLE__) - pthread_once(&init_guard, &cpuinfo_arm_mach_init); - #elif defined(_WIN32) - InitOnceExecuteOnce(&init_guard, &cpuinfo_arm_windows_init, NULL, NULL); - #else - cpuinfo_log_error("operating system is not supported in cpuinfo"); - #endif +#if defined(__linux__) + pthread_once(&init_guard, &cpuinfo_arm_linux_init); +#elif defined(__MACH__) && defined(__APPLE__) + pthread_once(&init_guard, &cpuinfo_arm_mach_init); +#elif defined(_WIN32) + InitOnceExecuteOnce(&init_guard, &cpuinfo_arm_windows_init, NULL, NULL); +#else + cpuinfo_log_error("operating system is not supported in cpuinfo"); +#endif #elif CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 - #if defined(__linux__) - pthread_once(&init_guard, &cpuinfo_riscv_linux_init); - #else - cpuinfo_log_error("operating system is not supported in cpuinfo"); - #endif +#if defined(__linux__) + pthread_once(&init_guard, &cpuinfo_riscv_linux_init); +#else + cpuinfo_log_error("operating system is not supported in cpuinfo"); +#endif #elif CPUINFO_ARCH_ASMJS || CPUINFO_ARCH_WASM || CPUINFO_ARCH_WASMSIMD - #if defined(__EMSCRIPTEN_PTHREADS__) - pthread_once(&init_guard, &cpuinfo_emscripten_init); - #else - if (!init_guard) { - cpuinfo_emscripten_init(); - } - init_guard = true; - #endif +#if defined(__EMSCRIPTEN_PTHREADS__) + pthread_once(&init_guard, &cpuinfo_emscripten_init); +#else + if (!init_guard) { + cpuinfo_emscripten_init(); + } + init_guard = true; +#endif #else cpuinfo_log_error("processor architecture is not supported in cpuinfo"); #endif return cpuinfo_is_initialized; } -void CPUINFO_ABI cpuinfo_deinitialize(void) { -} +void CPUINFO_ABI cpuinfo_deinitialize(void) {} diff --git a/src/linux/api.h b/src/linux/api.h index df02802c..0966bd57 100644 --- a/src/linux/api.h +++ b/src/linux/api.h @@ -1,35 +1,45 @@ #pragma once #include -#include #include +#include #include #include - -#define CPUINFO_LINUX_FLAG_PRESENT UINT32_C(0x00000001) -#define CPUINFO_LINUX_FLAG_POSSIBLE UINT32_C(0x00000002) -#define CPUINFO_LINUX_FLAG_MAX_FREQUENCY UINT32_C(0x00000004) -#define CPUINFO_LINUX_FLAG_MIN_FREQUENCY UINT32_C(0x00000008) -#define CPUINFO_LINUX_FLAG_SMT_ID UINT32_C(0x00000010) -#define CPUINFO_LINUX_FLAG_CORE_ID UINT32_C(0x00000020) -#define CPUINFO_LINUX_FLAG_PACKAGE_ID UINT32_C(0x00000040) -#define CPUINFO_LINUX_FLAG_APIC_ID UINT32_C(0x00000080) -#define CPUINFO_LINUX_FLAG_SMT_CLUSTER UINT32_C(0x00000100) -#define CPUINFO_LINUX_FLAG_CORE_CLUSTER UINT32_C(0x00000200) -#define CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER UINT32_C(0x00000400) -#define CPUINFO_LINUX_FLAG_PROC_CPUINFO UINT32_C(0x00000800) -#define CPUINFO_LINUX_FLAG_VALID UINT32_C(0x00001000) -#define CPUINFO_LINUX_FLAG_CUR_FREQUENCY UINT32_C(0x00002000) -#define CPUINFO_LINUX_FLAG_CLUSTER_CLUSTER UINT32_C(0x00004000) +#define CPUINFO_LINUX_FLAG_PRESENT UINT32_C(0x00000001) +#define CPUINFO_LINUX_FLAG_POSSIBLE UINT32_C(0x00000002) +#define CPUINFO_LINUX_FLAG_MAX_FREQUENCY UINT32_C(0x00000004) +#define CPUINFO_LINUX_FLAG_MIN_FREQUENCY UINT32_C(0x00000008) +#define CPUINFO_LINUX_FLAG_SMT_ID UINT32_C(0x00000010) +#define CPUINFO_LINUX_FLAG_CORE_ID UINT32_C(0x00000020) +#define CPUINFO_LINUX_FLAG_PACKAGE_ID UINT32_C(0x00000040) +#define CPUINFO_LINUX_FLAG_APIC_ID UINT32_C(0x00000080) +#define CPUINFO_LINUX_FLAG_SMT_CLUSTER UINT32_C(0x00000100) +#define CPUINFO_LINUX_FLAG_CORE_CLUSTER UINT32_C(0x00000200) +#define CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER UINT32_C(0x00000400) +#define CPUINFO_LINUX_FLAG_PROC_CPUINFO UINT32_C(0x00000800) +#define CPUINFO_LINUX_FLAG_VALID UINT32_C(0x00001000) +#define CPUINFO_LINUX_FLAG_CUR_FREQUENCY UINT32_C(0x00002000) +#define CPUINFO_LINUX_FLAG_CLUSTER_CLUSTER UINT32_C(0x00004000) typedef bool (*cpuinfo_cpulist_callback)(uint32_t, uint32_t, void*); -CPUINFO_INTERNAL bool cpuinfo_linux_parse_cpulist(const char* filename, cpuinfo_cpulist_callback callback, void* context); +CPUINFO_INTERNAL bool cpuinfo_linux_parse_cpulist( + const char* filename, + cpuinfo_cpulist_callback callback, + void* context); typedef bool (*cpuinfo_smallfile_callback)(const char*, const char*, const char*, void*); -CPUINFO_INTERNAL bool cpuinfo_linux_parse_small_file(const char* filename, size_t buffer_size, cpuinfo_smallfile_callback, void* context); +CPUINFO_INTERNAL bool cpuinfo_linux_parse_small_file( + const char* filename, + size_t buffer_size, + cpuinfo_smallfile_callback, + void* context); typedef bool (*cpuinfo_line_callback)(const char*, const char*, void*, uint64_t); -CPUINFO_INTERNAL bool cpuinfo_linux_parse_multiline_file(const char* filename, size_t buffer_size, cpuinfo_line_callback, void* context); +CPUINFO_INTERNAL bool cpuinfo_linux_parse_multiline_file( + const char* filename, + size_t buffer_size, + cpuinfo_line_callback, + void* context); CPUINFO_INTERNAL uint32_t cpuinfo_linux_get_max_processors_count(void); CPUINFO_INTERNAL uint32_t cpuinfo_linux_get_max_possible_processor(uint32_t max_processors_count); @@ -37,13 +47,21 @@ CPUINFO_INTERNAL uint32_t cpuinfo_linux_get_max_present_processor(uint32_t max_p CPUINFO_INTERNAL uint32_t cpuinfo_linux_get_processor_cur_frequency(uint32_t processor); CPUINFO_INTERNAL uint32_t cpuinfo_linux_get_processor_min_frequency(uint32_t processor); CPUINFO_INTERNAL uint32_t cpuinfo_linux_get_processor_max_frequency(uint32_t processor); -CPUINFO_INTERNAL bool cpuinfo_linux_get_processor_package_id(uint32_t processor, uint32_t package_id[restrict static 1]); +CPUINFO_INTERNAL bool cpuinfo_linux_get_processor_package_id( + uint32_t processor, + uint32_t package_id[restrict static 1]); CPUINFO_INTERNAL bool cpuinfo_linux_get_processor_core_id(uint32_t processor, uint32_t core_id[restrict static 1]); -CPUINFO_INTERNAL bool cpuinfo_linux_detect_possible_processors(uint32_t max_processors_count, - uint32_t* processor0_flags, uint32_t processor_struct_size, uint32_t possible_flag); -CPUINFO_INTERNAL bool cpuinfo_linux_detect_present_processors(uint32_t max_processors_count, - uint32_t* processor0_flags, uint32_t processor_struct_size, uint32_t present_flag); +CPUINFO_INTERNAL bool cpuinfo_linux_detect_possible_processors( + uint32_t max_processors_count, + uint32_t* processor0_flags, + uint32_t processor_struct_size, + uint32_t possible_flag); +CPUINFO_INTERNAL bool cpuinfo_linux_detect_present_processors( + uint32_t max_processors_count, + uint32_t* processor0_flags, + uint32_t processor_struct_size, + uint32_t present_flag); typedef bool (*cpuinfo_siblings_callback)(uint32_t, uint32_t, uint32_t, void*); CPUINFO_INTERNAL bool cpuinfo_linux_detect_core_siblings( diff --git a/src/linux/cpulist.c b/src/linux/cpulist.c index 28719863..f6c4c291 100644 --- a/src/linux/cpulist.c +++ b/src/linux/cpulist.c @@ -1,21 +1,20 @@ +#include #include #include #include #include -#include -#include -#include -#include #include #include +#include +#include +#include #if CPUINFO_MOCK - #include +#include #endif -#include #include - +#include /* * Size, in chars, of the on-stack buffer used for parsing cpu lists. @@ -25,7 +24,6 @@ */ #define BUFFER_SIZE 256 - /* Locale-independent */ inline static bool is_whitespace(char c) { switch (c) { @@ -42,7 +40,7 @@ inline static bool is_whitespace(char c) { inline static const char* parse_number(const char* string, const char* end, uint32_t number_ptr[restrict static 1]) { uint32_t number = 0; while (string != end) { - const uint32_t digit = (uint32_t) (*string) - (uint32_t) '0'; + const uint32_t digit = (uint32_t)(*string) - (uint32_t)'0'; if (digit >= 10) { break; } @@ -53,7 +51,11 @@ inline static const char* parse_number(const char* string, const char* end, uint return string; } -inline static bool parse_entry(const char* entry_start, const char* entry_end, cpuinfo_cpulist_callback callback, void* context) { +inline static bool parse_entry( + const char* entry_start, + const char* entry_end, + cpuinfo_cpulist_callback callback, + void* context) { /* Skip whitespace at the beginning of an entry */ for (; entry_start != entry_end; entry_start++) { if (!is_whitespace(*entry_start)) { @@ -67,36 +69,44 @@ inline static bool parse_entry(const char* entry_start, const char* entry_end, c } } - const size_t entry_length = (size_t) (entry_end - entry_start); + const size_t entry_length = (size_t)(entry_end - entry_start); if (entry_length == 0) { cpuinfo_log_warning("unexpected zero-length cpu list entry ignored"); return false; } - #if CPUINFO_LOG_DEBUG_PARSERS - cpuinfo_log_debug("parse cpu list entry \"%.*s\" (%zu chars)", (int) entry_length, entry_start, entry_length); - #endif +#if CPUINFO_LOG_DEBUG_PARSERS + cpuinfo_log_debug("parse cpu list entry \"%.*s\" (%zu chars)", (int)entry_length, entry_start, entry_length); +#endif uint32_t first_cpu, last_cpu; const char* number_end = parse_number(entry_start, entry_end, &first_cpu); if (number_end == entry_start) { /* Failed to parse the number; ignore the entry */ - cpuinfo_log_warning("invalid character '%c' in the cpu list entry \"%.*s\": entry is ignored", - entry_start[0], (int) entry_length, entry_start); + cpuinfo_log_warning( + "invalid character '%c' in the cpu list entry \"%.*s\": entry is ignored", + entry_start[0], + (int)entry_length, + entry_start); return false; } else if (number_end == entry_end) { - /* Completely parsed the entry */ - #if CPUINFO_LOG_DEBUG_PARSERS - cpuinfo_log_debug("cpulist: call callback with list_start = %"PRIu32", list_end = %"PRIu32, - first_cpu, first_cpu + 1); - #endif +/* Completely parsed the entry */ +#if CPUINFO_LOG_DEBUG_PARSERS + cpuinfo_log_debug( + "cpulist: call callback with list_start = %" PRIu32 ", list_end = %" PRIu32, + first_cpu, + first_cpu + 1); +#endif return callback(first_cpu, first_cpu + 1, context); } /* Parse the second part of the entry */ if (*number_end != '-') { - cpuinfo_log_warning("invalid character '%c' in the cpu list entry \"%.*s\": entry is ignored", - *number_end, (int) entry_length, entry_start); + cpuinfo_log_warning( + "invalid character '%c' in the cpu list entry \"%.*s\": entry is ignored", + *number_end, + (int)entry_length, + entry_start); return false; } @@ -104,28 +114,40 @@ inline static bool parse_entry(const char* entry_start, const char* entry_end, c number_end = parse_number(number_start, entry_end, &last_cpu); if (number_end == number_start) { /* Failed to parse the second number; ignore the entry */ - cpuinfo_log_warning("invalid character '%c' in the cpu list entry \"%.*s\": entry is ignored", - *number_start, (int) entry_length, entry_start); + cpuinfo_log_warning( + "invalid character '%c' in the cpu list entry \"%.*s\": entry is ignored", + *number_start, + (int)entry_length, + entry_start); return false; } if (number_end != entry_end) { - /* Partially parsed the entry; ignore unparsed characters and continue with the parsed part */ - cpuinfo_log_warning("ignored invalid characters \"%.*s\" at the end of cpu list entry \"%.*s\"", - (int) (entry_end - number_end), number_start, (int) entry_length, entry_start); + /* Partially parsed the entry; ignore unparsed characters and + * continue with the parsed part */ + cpuinfo_log_warning( + "ignored invalid characters \"%.*s\" at the end of cpu list entry \"%.*s\"", + (int)(entry_end - number_end), + number_start, + (int)entry_length, + entry_start); } if (last_cpu < first_cpu) { - cpuinfo_log_warning("ignored cpu list entry \"%.*s\": invalid range %"PRIu32"-%"PRIu32, - (int) entry_length, entry_start, first_cpu, last_cpu); + cpuinfo_log_warning( + "ignored cpu list entry \"%.*s\": invalid range %" PRIu32 "-%" PRIu32, + (int)entry_length, + entry_start, + first_cpu, + last_cpu); return false; } - /* Parsed both parts of the entry; update CPU set */ - #if CPUINFO_LOG_DEBUG_PARSERS - cpuinfo_log_debug("cpulist: call callback with list_start = %"PRIu32", list_end = %"PRIu32, - first_cpu, last_cpu + 1); - #endif +/* Parsed both parts of the entry; update CPU set */ +#if CPUINFO_LOG_DEBUG_PARSERS + cpuinfo_log_debug( + "cpulist: call callback with list_start = %" PRIu32 ", list_end = %" PRIu32, first_cpu, last_cpu + 1); +#endif return callback(first_cpu, last_cpu + 1, context); } @@ -133,9 +155,9 @@ bool cpuinfo_linux_parse_cpulist(const char* filename, cpuinfo_cpulist_callback bool status = true; int file = -1; char buffer[BUFFER_SIZE]; - #if CPUINFO_LOG_DEBUG_PARSERS - cpuinfo_log_debug("parsing cpu list from file %s", filename); - #endif +#if CPUINFO_LOG_DEBUG_PARSERS + cpuinfo_log_debug("parsing cpu list from file %s", filename); +#endif #if CPUINFO_MOCK file = cpuinfo_mock_open(filename, O_RDONLY); @@ -154,29 +176,32 @@ bool cpuinfo_linux_parse_cpulist(const char* filename, cpuinfo_cpulist_callback ssize_t bytes_read; do { #if CPUINFO_MOCK - bytes_read = cpuinfo_mock_read(file, data_start, (size_t) (buffer_end - data_start)); + bytes_read = cpuinfo_mock_read(file, data_start, (size_t)(buffer_end - data_start)); #else - bytes_read = read(file, data_start, (size_t) (buffer_end - data_start)); + bytes_read = read(file, data_start, (size_t)(buffer_end - data_start)); #endif if (bytes_read < 0) { - cpuinfo_log_info("failed to read file %s at position %zu: %s", filename, position, strerror(errno)); + cpuinfo_log_info( + "failed to read file %s at position %zu: %s", filename, position, strerror(errno)); status = false; goto cleanup; } - position += (size_t) bytes_read; - const char* data_end = data_start + (size_t) bytes_read; + position += (size_t)bytes_read; + const char* data_end = data_start + (size_t)bytes_read; const char* entry_start = buffer; if (bytes_read == 0) { - /* No more data in the file: process the remaining text in the buffer as a single entry */ + /* No more data in the file: process the remaining text + * in the buffer as a single entry */ const char* entry_end = data_end; const bool entry_status = parse_entry(entry_start, entry_end, callback, context); status &= entry_status; } else { const char* entry_end; do { - /* Find the end of the entry, as indicated by a comma (',') */ + /* Find the end of the entry, as indicated by a + * comma (',') */ for (entry_end = entry_start; entry_end != data_end; entry_end++) { if (*entry_end == ',') { break; @@ -184,18 +209,21 @@ bool cpuinfo_linux_parse_cpulist(const char* filename, cpuinfo_cpulist_callback } /* - * If we located separator at the end of the entry, parse it. - * Otherwise, there may be more data at the end; read the file once again. + * If we located separator at the end of the + * entry, parse it. Otherwise, there may be more + * data at the end; read the file once again. */ if (entry_end != data_end) { - const bool entry_status = parse_entry(entry_start, entry_end, callback, context); + const bool entry_status = + parse_entry(entry_start, entry_end, callback, context); status &= entry_status; entry_start = entry_end + 1; } } while (entry_end != data_end); - /* Move remaining partial entry data at the end to the beginning of the buffer */ - const size_t entry_length = (size_t) (entry_end - entry_start); + /* Move remaining partial entry data at the end to the + * beginning of the buffer */ + const size_t entry_length = (size_t)(entry_end - entry_start); memmove(buffer, entry_start, entry_length); data_start = &buffer[entry_length]; } diff --git a/src/linux/mockfile.c b/src/linux/mockfile.c index 138acfeb..dd6ec339 100644 --- a/src/linux/mockfile.c +++ b/src/linux/mockfile.c @@ -1,30 +1,28 @@ +#include #include +#include #include #include -#include #include -#include -#include -#include -#include #include #include +#include +#include +#include #if !CPUINFO_MOCK - #error This file should be built only in mock mode +#error This file should be built only in mock mode #endif -#include #include #include +#include #include - static struct cpuinfo_mock_file* cpuinfo_mock_files = NULL; static uint32_t cpuinfo_mock_file_count = 0; - void CPUINFO_ABI cpuinfo_mock_filesystem(struct cpuinfo_mock_file* files) { cpuinfo_log_info("filesystem mocking enabled"); uint32_t file_count = 0; @@ -54,7 +52,7 @@ int CPUINFO_ABI cpuinfo_mock_open(const char* path, int oflag) { return -1; } cpuinfo_mock_files[i].offset = 0; - return (int) i; + return (int)i; } } errno = ENOENT; @@ -67,7 +65,7 @@ int CPUINFO_ABI cpuinfo_mock_close(int fd) { return close(fd); } - if ((unsigned int) fd >= cpuinfo_mock_file_count) { + if ((unsigned int)fd >= cpuinfo_mock_file_count) { errno = EBADF; return -1; } @@ -85,7 +83,7 @@ ssize_t CPUINFO_ABI cpuinfo_mock_read(int fd, void* buffer, size_t capacity) { return read(fd, buffer, capacity); } - if ((unsigned int) fd >= cpuinfo_mock_file_count) { + if ((unsigned int)fd >= cpuinfo_mock_file_count) { errno = EBADF; return -1; } @@ -99,7 +97,7 @@ ssize_t CPUINFO_ABI cpuinfo_mock_read(int fd, void* buffer, size_t capacity) { if (count > capacity) { count = capacity; } - memcpy(buffer, (void*) cpuinfo_mock_files[fd].content + offset, count); + memcpy(buffer, (void*)cpuinfo_mock_files[fd].content + offset, count); cpuinfo_mock_files[fd].offset += count; - return (ssize_t) count; + return (ssize_t)count; } diff --git a/src/linux/multiline.c b/src/linux/multiline.c index 1feeb9b1..00f4583d 100644 --- a/src/linux/multiline.c +++ b/src/linux/multiline.c @@ -1,27 +1,29 @@ +#include +#include #include #include #include #include -#include -#include -#include +#include #include +#include #include -#include #if CPUINFO_MOCK - #include +#include #endif -#include #include +#include - -bool cpuinfo_linux_parse_multiline_file(const char* filename, size_t buffer_size, cpuinfo_line_callback callback, void* context) -{ +bool cpuinfo_linux_parse_multiline_file( + const char* filename, + size_t buffer_size, + cpuinfo_line_callback callback, + void* context) { int file = -1; bool status = false; - char* buffer = (char*) alloca(buffer_size); + char* buffer = (char*)alloca(buffer_size); #if CPUINFO_MOCK file = cpuinfo_mock_open(filename, O_RDONLY); @@ -41,22 +43,23 @@ bool cpuinfo_linux_parse_multiline_file(const char* filename, size_t buffer_size ssize_t bytes_read; do { #if CPUINFO_MOCK - bytes_read = cpuinfo_mock_read(file, data_start, (size_t) (buffer_end - data_start)); + bytes_read = cpuinfo_mock_read(file, data_start, (size_t)(buffer_end - data_start)); #else - bytes_read = read(file, data_start, (size_t) (buffer_end - data_start)); + bytes_read = read(file, data_start, (size_t)(buffer_end - data_start)); #endif if (bytes_read < 0) { - cpuinfo_log_info("failed to read file %s at position %zu: %s", - filename, position, strerror(errno)); + cpuinfo_log_info( + "failed to read file %s at position %zu: %s", filename, position, strerror(errno)); goto cleanup; } - position += (size_t) bytes_read; - const char* data_end = data_start + (size_t) bytes_read; + position += (size_t)bytes_read; + const char* data_end = data_start + (size_t)bytes_read; const char* line_start = buffer; if (bytes_read == 0) { - /* No more data in the file: process the remaining text in the buffer as a single entry */ + /* No more data in the file: process the remaining text + * in the buffer as a single entry */ const char* line_end = data_end; if (!callback(line_start, line_end, context, line_number)) { goto cleanup; @@ -64,7 +67,9 @@ bool cpuinfo_linux_parse_multiline_file(const char* filename, size_t buffer_size } else { const char* line_end; do { - /* Find the end of the entry, as indicated by newline character ('\n') */ + /* Find the end of the entry, as indicated by + * newline character ('\n') + */ for (line_end = line_start; line_end != data_end; line_end++) { if (*line_end == '\n') { break; @@ -72,8 +77,9 @@ bool cpuinfo_linux_parse_multiline_file(const char* filename, size_t buffer_size } /* - * If we located separator at the end of the entry, parse it. - * Otherwise, there may be more data at the end; read the file once again. + * If we located separator at the end of the + * entry, parse it. Otherwise, there may be more + * data at the end; read the file once again. */ if (line_end != data_end) { if (!callback(line_start, line_end, context, line_number++)) { @@ -83,8 +89,9 @@ bool cpuinfo_linux_parse_multiline_file(const char* filename, size_t buffer_size } } while (line_end != data_end); - /* Move remaining partial line data at the end to the beginning of the buffer */ - const size_t line_length = (size_t) (line_end - line_start); + /* Move remaining partial line data at the end to the + * beginning of the buffer */ + const size_t line_length = (size_t)(line_end - line_start); memmove(buffer, line_start, line_length); data_start = &buffer[line_length]; } diff --git a/src/linux/processors.c b/src/linux/processors.c index dcdd4e7c..b68cd1cc 100644 --- a/src/linux/processors.c +++ b/src/linux/processors.c @@ -1,31 +1,32 @@ #include #include -#include #include +#include #include #if !defined(__ANDROID__) - /* - * sched.h is only used for CPU_SETSIZE constant. - * Android NDK headers before platform 21 do have this constant in sched.h - */ - #include +/* + * sched.h is only used for CPU_SETSIZE constant. + * Android NDK headers before platform 21 do have this constant in sched.h + */ +#include #endif -#include #include - +#include #define STRINGIFY(token) #token #define KERNEL_MAX_FILENAME "/sys/devices/system/cpu/kernel_max" #define KERNEL_MAX_FILESIZE 32 -#define FREQUENCY_FILENAME_SIZE (sizeof("/sys/devices/system/cpu/cpu" STRINGIFY(UINT32_MAX) "/cpufreq/cpuinfo_max_freq")) +#define FREQUENCY_FILENAME_SIZE \ + (sizeof("/sys/devices/system/cpu/cpu" STRINGIFY(UINT32_MAX) "/cpufreq/cpuinfo_max_freq")) #define CUR_FREQUENCY_FILENAME_FORMAT "/sys/devices/system/cpu/cpu%" PRIu32 "/cpufreq/cpuinfo_cur_freq" #define MAX_FREQUENCY_FILENAME_FORMAT "/sys/devices/system/cpu/cpu%" PRIu32 "/cpufreq/cpuinfo_max_freq" #define MIN_FREQUENCY_FILENAME_FORMAT "/sys/devices/system/cpu/cpu%" PRIu32 "/cpufreq/cpuinfo_min_freq" #define FREQUENCY_FILESIZE 32 -#define PACKAGE_ID_FILENAME_SIZE (sizeof("/sys/devices/system/cpu/cpu" STRINGIFY(UINT32_MAX) "/topology/physical_package_id")) +#define PACKAGE_ID_FILENAME_SIZE \ + (sizeof("/sys/devices/system/cpu/cpu" STRINGIFY(UINT32_MAX) "/topology/physical_package_id")) #define PACKAGE_ID_FILENAME_FORMAT "/sys/devices/system/cpu/cpu%" PRIu32 "/topology/physical_package_id" #define PACKAGE_ID_FILESIZE 32 #define CORE_ID_FILENAME_SIZE (sizeof("/sys/devices/system/cpu/cpu" STRINGIFY(UINT32_MAX) "/topology/core_id")) @@ -34,24 +35,27 @@ #define CORE_CPUS_FILENAME_SIZE (sizeof("/sys/devices/system/cpu/cpu" STRINGIFY(UINT32_MAX) "/topology/core_cpus_list")) #define CORE_CPUS_FILENAME_FORMAT "/sys/devices/system/cpu/cpu%" PRIu32 "/topology/core_cpus_list" -#define CORE_SIBLINGS_FILENAME_SIZE (sizeof("/sys/devices/system/cpu/cpu" STRINGIFY(UINT32_MAX) "/topology/core_siblings_list")) +#define CORE_SIBLINGS_FILENAME_SIZE \ + (sizeof("/sys/devices/system/cpu/cpu" STRINGIFY(UINT32_MAX) "/topology/core_siblings_list")) #define CORE_SIBLINGS_FILENAME_FORMAT "/sys/devices/system/cpu/cpu%" PRIu32 "/topology/core_siblings_list" -#define CLUSTER_CPUS_FILENAME_SIZE (sizeof("/sys/devices/system/cpu/cpu" STRINGIFY(UINT32_MAX) "/topology/cluster_cpus_list")) +#define CLUSTER_CPUS_FILENAME_SIZE \ + (sizeof("/sys/devices/system/cpu/cpu" STRINGIFY(UINT32_MAX) "/topology/cluster_cpus_list")) #define CLUSTER_CPUS_FILENAME_FORMAT "/sys/devices/system/cpu/cpu%" PRIu32 "/topology/cluster_cpus_list" -#define PACKAGE_CPUS_FILENAME_SIZE (sizeof("/sys/devices/system/cpu/cpu" STRINGIFY(UINT32_MAX) "/topology/package_cpus_list")) +#define PACKAGE_CPUS_FILENAME_SIZE \ + (sizeof("/sys/devices/system/cpu/cpu" STRINGIFY(UINT32_MAX) "/topology/package_cpus_list")) #define PACKAGE_CPUS_FILENAME_FORMAT "/sys/devices/system/cpu/cpu%" PRIu32 "/topology/package_cpus_list" -#define THREAD_SIBLINGS_FILENAME_SIZE (sizeof("/sys/devices/system/cpu/cpu" STRINGIFY(UINT32_MAX) "/topology/thread_siblings_list")) +#define THREAD_SIBLINGS_FILENAME_SIZE \ + (sizeof("/sys/devices/system/cpu/cpu" STRINGIFY(UINT32_MAX) "/topology/thread_siblings_list")) #define THREAD_SIBLINGS_FILENAME_FORMAT "/sys/devices/system/cpu/cpu%" PRIu32 "/topology/thread_siblings_list" #define POSSIBLE_CPULIST_FILENAME "/sys/devices/system/cpu/possible" #define PRESENT_CPULIST_FILENAME "/sys/devices/system/cpu/present" - inline static const char* parse_number(const char* start, const char* end, uint32_t number_ptr[restrict static 1]) { uint32_t number = 0; const char* parsed = start; for (; parsed != end; parsed++) { - const uint32_t digit = (uint32_t) (uint8_t) (*parsed) - (uint32_t) '0'; + const uint32_t digit = (uint32_t)(uint8_t)(*parsed) - (uint32_t)'0'; if (digit >= 10) { break; } @@ -75,17 +79,17 @@ inline static bool is_whitespace(char c) { } #if defined(__ANDROID__) && !defined(CPU_SETSIZE) - /* - * Android NDK headers before platform 21 do not define CPU_SETSIZE, - * so we hard-code its value, as defined in platform 21 headers - */ - #if defined(__LP64__) - static const uint32_t default_max_processors_count = 1024; - #else - static const uint32_t default_max_processors_count = 32; - #endif +/* + * Android NDK headers before platform 21 do not define CPU_SETSIZE, + * so we hard-code its value, as defined in platform 21 headers + */ +#if defined(__LP64__) +static const uint32_t default_max_processors_count = 1024; +#else +static const uint32_t default_max_processors_count = 32; +#endif #else - static const uint32_t default_max_processors_count = CPU_SETSIZE; +static const uint32_t default_max_processors_count = CPU_SETSIZE; #endif static bool uint32_parser(const char* filename, const char* text_start, const char* text_end, void* context) { @@ -97,20 +101,26 @@ static bool uint32_parser(const char* filename, const char* text_start, const ch uint32_t kernel_max = 0; const char* parsed_end = parse_number(text_start, text_end, &kernel_max); if (parsed_end == text_start) { - cpuinfo_log_error("failed to parse file %s: \"%.*s\" is not an unsigned number", - filename, (int) (text_end - text_start), text_start); + cpuinfo_log_error( + "failed to parse file %s: \"%.*s\" is not an unsigned number", + filename, + (int)(text_end - text_start), + text_start); return false; } else { for (const char* char_ptr = parsed_end; char_ptr != text_end; char_ptr++) { if (!is_whitespace(*char_ptr)) { - cpuinfo_log_warning("non-whitespace characters \"%.*s\" following number in file %s are ignored", - (int) (text_end - char_ptr), char_ptr, filename); + cpuinfo_log_warning( + "non-whitespace characters \"%.*s\" following number in file %s are ignored", + (int)(text_end - char_ptr), + char_ptr, + filename); break; } } } - uint32_t* kernel_max_ptr = (uint32_t*) context; + uint32_t* kernel_max_ptr = (uint32_t*)context; *kernel_max_ptr = kernel_max; return true; } @@ -118,133 +128,160 @@ static bool uint32_parser(const char* filename, const char* text_start, const ch uint32_t cpuinfo_linux_get_max_processors_count(void) { uint32_t kernel_max; if (cpuinfo_linux_parse_small_file(KERNEL_MAX_FILENAME, KERNEL_MAX_FILESIZE, uint32_parser, &kernel_max)) { - cpuinfo_log_debug("parsed kernel_max value of %"PRIu32" from %s", kernel_max, KERNEL_MAX_FILENAME); + cpuinfo_log_debug("parsed kernel_max value of %" PRIu32 " from %s", kernel_max, KERNEL_MAX_FILENAME); if (kernel_max >= default_max_processors_count) { - cpuinfo_log_warning("kernel_max value of %"PRIu32" parsed from %s exceeds platform-default limit %"PRIu32, - kernel_max, KERNEL_MAX_FILENAME, default_max_processors_count - 1); + cpuinfo_log_warning( + "kernel_max value of %" PRIu32 + " parsed from %s exceeds platform-default limit %" PRIu32, + kernel_max, + KERNEL_MAX_FILENAME, + default_max_processors_count - 1); } return kernel_max + 1; } else { - cpuinfo_log_warning("using platform-default max processors count = %"PRIu32, default_max_processors_count); + cpuinfo_log_warning( + "using platform-default max processors count = %" PRIu32, default_max_processors_count); return default_max_processors_count; } } uint32_t cpuinfo_linux_get_processor_cur_frequency(uint32_t processor) { char cur_frequency_filename[FREQUENCY_FILENAME_SIZE]; - const int chars_formatted = snprintf( - cur_frequency_filename, FREQUENCY_FILENAME_SIZE, CUR_FREQUENCY_FILENAME_FORMAT, processor); - if ((unsigned int) chars_formatted >= FREQUENCY_FILENAME_SIZE) { - cpuinfo_log_warning("failed to format filename for current frequency of processor %"PRIu32, processor); + const int chars_formatted = + snprintf(cur_frequency_filename, FREQUENCY_FILENAME_SIZE, CUR_FREQUENCY_FILENAME_FORMAT, processor); + if ((unsigned int)chars_formatted >= FREQUENCY_FILENAME_SIZE) { + cpuinfo_log_warning("failed to format filename for current frequency of processor %" PRIu32, processor); return 0; } uint32_t cur_frequency; if (cpuinfo_linux_parse_small_file(cur_frequency_filename, FREQUENCY_FILESIZE, uint32_parser, &cur_frequency)) { - cpuinfo_log_debug("parsed currrent frequency value of %"PRIu32" KHz for logical processor %"PRIu32" from %s", - cur_frequency, processor, cur_frequency_filename); + cpuinfo_log_debug( + "parsed currrent frequency value of %" PRIu32 " KHz for logical processor %" PRIu32 " from %s", + cur_frequency, + processor, + cur_frequency_filename); return cur_frequency; } else { - cpuinfo_log_warning("failed to parse current frequency for processor %"PRIu32" from %s", - processor, cur_frequency_filename); + cpuinfo_log_warning( + "failed to parse current frequency for processor %" PRIu32 " from %s", + processor, + cur_frequency_filename); return 0; } } uint32_t cpuinfo_linux_get_processor_max_frequency(uint32_t processor) { char max_frequency_filename[FREQUENCY_FILENAME_SIZE]; - const int chars_formatted = snprintf( - max_frequency_filename, FREQUENCY_FILENAME_SIZE, MAX_FREQUENCY_FILENAME_FORMAT, processor); - if ((unsigned int) chars_formatted >= FREQUENCY_FILENAME_SIZE) { - cpuinfo_log_warning("failed to format filename for max frequency of processor %"PRIu32, processor); + const int chars_formatted = + snprintf(max_frequency_filename, FREQUENCY_FILENAME_SIZE, MAX_FREQUENCY_FILENAME_FORMAT, processor); + if ((unsigned int)chars_formatted >= FREQUENCY_FILENAME_SIZE) { + cpuinfo_log_warning("failed to format filename for max frequency of processor %" PRIu32, processor); return 0; } uint32_t max_frequency; if (cpuinfo_linux_parse_small_file(max_frequency_filename, FREQUENCY_FILESIZE, uint32_parser, &max_frequency)) { - cpuinfo_log_debug("parsed max frequency value of %"PRIu32" KHz for logical processor %"PRIu32" from %s", - max_frequency, processor, max_frequency_filename); + cpuinfo_log_debug( + "parsed max frequency value of %" PRIu32 " KHz for logical processor %" PRIu32 " from %s", + max_frequency, + processor, + max_frequency_filename); return max_frequency; } else { - cpuinfo_log_warning("failed to parse max frequency for processor %"PRIu32" from %s", - processor, max_frequency_filename); + cpuinfo_log_warning( + "failed to parse max frequency for processor %" PRIu32 " from %s", + processor, + max_frequency_filename); return 0; } } uint32_t cpuinfo_linux_get_processor_min_frequency(uint32_t processor) { char min_frequency_filename[FREQUENCY_FILENAME_SIZE]; - const int chars_formatted = snprintf( - min_frequency_filename, FREQUENCY_FILENAME_SIZE, MIN_FREQUENCY_FILENAME_FORMAT, processor); - if ((unsigned int) chars_formatted >= FREQUENCY_FILENAME_SIZE) { - cpuinfo_log_warning("failed to format filename for min frequency of processor %"PRIu32, processor); + const int chars_formatted = + snprintf(min_frequency_filename, FREQUENCY_FILENAME_SIZE, MIN_FREQUENCY_FILENAME_FORMAT, processor); + if ((unsigned int)chars_formatted >= FREQUENCY_FILENAME_SIZE) { + cpuinfo_log_warning("failed to format filename for min frequency of processor %" PRIu32, processor); return 0; } uint32_t min_frequency; if (cpuinfo_linux_parse_small_file(min_frequency_filename, FREQUENCY_FILESIZE, uint32_parser, &min_frequency)) { - cpuinfo_log_debug("parsed min frequency value of %"PRIu32" KHz for logical processor %"PRIu32" from %s", - min_frequency, processor, min_frequency_filename); + cpuinfo_log_debug( + "parsed min frequency value of %" PRIu32 " KHz for logical processor %" PRIu32 " from %s", + min_frequency, + processor, + min_frequency_filename); return min_frequency; } else { /* - * This error is less severe than parsing max frequency, because min frequency is only useful for clustering, - * while max frequency is also needed for peak FLOPS calculation. + * This error is less severe than parsing max frequency, because + * min frequency is only useful for clustering, while max + * frequency is also needed for peak FLOPS calculation. */ - cpuinfo_log_info("failed to parse min frequency for processor %"PRIu32" from %s", - processor, min_frequency_filename); + cpuinfo_log_info( + "failed to parse min frequency for processor %" PRIu32 " from %s", + processor, + min_frequency_filename); return 0; } } bool cpuinfo_linux_get_processor_core_id(uint32_t processor, uint32_t core_id_ptr[restrict static 1]) { char core_id_filename[PACKAGE_ID_FILENAME_SIZE]; - const int chars_formatted = snprintf( - core_id_filename, CORE_ID_FILENAME_SIZE, CORE_ID_FILENAME_FORMAT, processor); - if ((unsigned int) chars_formatted >= CORE_ID_FILENAME_SIZE) { - cpuinfo_log_warning("failed to format filename for core id of processor %"PRIu32, processor); + const int chars_formatted = + snprintf(core_id_filename, CORE_ID_FILENAME_SIZE, CORE_ID_FILENAME_FORMAT, processor); + if ((unsigned int)chars_formatted >= CORE_ID_FILENAME_SIZE) { + cpuinfo_log_warning("failed to format filename for core id of processor %" PRIu32, processor); return 0; } uint32_t core_id; if (cpuinfo_linux_parse_small_file(core_id_filename, CORE_ID_FILESIZE, uint32_parser, &core_id)) { - cpuinfo_log_debug("parsed core id value of %"PRIu32" for logical processor %"PRIu32" from %s", - core_id, processor, core_id_filename); + cpuinfo_log_debug( + "parsed core id value of %" PRIu32 " for logical processor %" PRIu32 " from %s", + core_id, + processor, + core_id_filename); *core_id_ptr = core_id; return true; } else { - cpuinfo_log_info("failed to parse core id for processor %"PRIu32" from %s", - processor, core_id_filename); + cpuinfo_log_info( + "failed to parse core id for processor %" PRIu32 " from %s", processor, core_id_filename); return false; } } bool cpuinfo_linux_get_processor_package_id(uint32_t processor, uint32_t package_id_ptr[restrict static 1]) { char package_id_filename[PACKAGE_ID_FILENAME_SIZE]; - const int chars_formatted = snprintf( - package_id_filename, PACKAGE_ID_FILENAME_SIZE, PACKAGE_ID_FILENAME_FORMAT, processor); - if ((unsigned int) chars_formatted >= PACKAGE_ID_FILENAME_SIZE) { - cpuinfo_log_warning("failed to format filename for package id of processor %"PRIu32, processor); + const int chars_formatted = + snprintf(package_id_filename, PACKAGE_ID_FILENAME_SIZE, PACKAGE_ID_FILENAME_FORMAT, processor); + if ((unsigned int)chars_formatted >= PACKAGE_ID_FILENAME_SIZE) { + cpuinfo_log_warning("failed to format filename for package id of processor %" PRIu32, processor); return 0; } uint32_t package_id; if (cpuinfo_linux_parse_small_file(package_id_filename, PACKAGE_ID_FILESIZE, uint32_parser, &package_id)) { - cpuinfo_log_debug("parsed package id value of %"PRIu32" for logical processor %"PRIu32" from %s", - package_id, processor, package_id_filename); + cpuinfo_log_debug( + "parsed package id value of %" PRIu32 " for logical processor %" PRIu32 " from %s", + package_id, + processor, + package_id_filename); *package_id_ptr = package_id; return true; } else { - cpuinfo_log_info("failed to parse package id for processor %"PRIu32" from %s", - processor, package_id_filename); + cpuinfo_log_info( + "failed to parse package id for processor %" PRIu32 " from %s", processor, package_id_filename); return false; } } static bool max_processor_number_parser(uint32_t processor_list_start, uint32_t processor_list_end, void* context) { - uint32_t* processor_number_ptr = (uint32_t*) context; + uint32_t* processor_number_ptr = (uint32_t*)context; const uint32_t processor_list_last = processor_list_end - 1; if (*processor_number_ptr < processor_list_last) { *processor_number_ptr = processor_list_last; @@ -254,18 +291,21 @@ static bool max_processor_number_parser(uint32_t processor_list_start, uint32_t uint32_t cpuinfo_linux_get_max_possible_processor(uint32_t max_processors_count) { uint32_t max_possible_processor = 0; - if (!cpuinfo_linux_parse_cpulist(POSSIBLE_CPULIST_FILENAME, max_processor_number_parser, &max_possible_processor)) { - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 - cpuinfo_log_error("failed to parse the list of possible processors in %s", POSSIBLE_CPULIST_FILENAME); - #else - cpuinfo_log_warning("failed to parse the list of possible processors in %s", POSSIBLE_CPULIST_FILENAME); - #endif + if (!cpuinfo_linux_parse_cpulist( + POSSIBLE_CPULIST_FILENAME, max_processor_number_parser, &max_possible_processor)) { +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 + cpuinfo_log_error("failed to parse the list of possible processors in %s", POSSIBLE_CPULIST_FILENAME); +#else + cpuinfo_log_warning("failed to parse the list of possible processors in %s", POSSIBLE_CPULIST_FILENAME); +#endif return UINT32_MAX; } if (max_possible_processor >= max_processors_count) { cpuinfo_log_warning( - "maximum possible processor number %"PRIu32" exceeds system limit %"PRIu32": truncating to the latter", - max_possible_processor, max_processors_count - 1); + "maximum possible processor number %" PRIu32 " exceeds system limit %" PRIu32 + ": truncating to the latter", + max_possible_processor, + max_processors_count - 1); max_possible_processor = max_processors_count - 1; } return max_possible_processor; @@ -273,18 +313,21 @@ uint32_t cpuinfo_linux_get_max_possible_processor(uint32_t max_processors_count) uint32_t cpuinfo_linux_get_max_present_processor(uint32_t max_processors_count) { uint32_t max_present_processor = 0; - if (!cpuinfo_linux_parse_cpulist(PRESENT_CPULIST_FILENAME, max_processor_number_parser, &max_present_processor)) { - #if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 - cpuinfo_log_error("failed to parse the list of present processors in %s", PRESENT_CPULIST_FILENAME); - #else - cpuinfo_log_warning("failed to parse the list of present processors in %s", PRESENT_CPULIST_FILENAME); - #endif + if (!cpuinfo_linux_parse_cpulist( + PRESENT_CPULIST_FILENAME, max_processor_number_parser, &max_present_processor)) { +#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64 + cpuinfo_log_error("failed to parse the list of present processors in %s", PRESENT_CPULIST_FILENAME); +#else + cpuinfo_log_warning("failed to parse the list of present processors in %s", PRESENT_CPULIST_FILENAME); +#endif return UINT32_MAX; } if (max_present_processor >= max_processors_count) { cpuinfo_log_warning( - "maximum present processor number %"PRIu32" exceeds system limit %"PRIu32": truncating to the latter", - max_present_processor, max_processors_count - 1); + "maximum present processor number %" PRIu32 " exceeds system limit %" PRIu32 + ": truncating to the latter", + max_present_processor, + max_processors_count - 1); max_present_processor = max_processors_count - 1; } return max_present_processor; @@ -298,22 +341,25 @@ struct detect_processors_context { }; static bool detect_processor_parser(uint32_t processor_list_start, uint32_t processor_list_end, void* context) { - const uint32_t max_processors_count = ((struct detect_processors_context*) context)->max_processors_count; - const uint32_t* processor0_flags = ((struct detect_processors_context*) context)->processor0_flags; - const uint32_t processor_struct_size = ((struct detect_processors_context*) context)->processor_struct_size; - const uint32_t detected_flag = ((struct detect_processors_context*) context)->detected_flag; + const uint32_t max_processors_count = ((struct detect_processors_context*)context)->max_processors_count; + const uint32_t* processor0_flags = ((struct detect_processors_context*)context)->processor0_flags; + const uint32_t processor_struct_size = ((struct detect_processors_context*)context)->processor_struct_size; + const uint32_t detected_flag = ((struct detect_processors_context*)context)->detected_flag; for (uint32_t processor = processor_list_start; processor < processor_list_end; processor++) { if (processor >= max_processors_count) { break; } - *((uint32_t*) ((uintptr_t) processor0_flags + processor_struct_size * processor)) |= detected_flag; + *((uint32_t*)((uintptr_t)processor0_flags + processor_struct_size * processor)) |= detected_flag; } return true; } -bool cpuinfo_linux_detect_possible_processors(uint32_t max_processors_count, - uint32_t* processor0_flags, uint32_t processor_struct_size, uint32_t possible_flag) { +bool cpuinfo_linux_detect_possible_processors( + uint32_t max_processors_count, + uint32_t* processor0_flags, + uint32_t processor_struct_size, + uint32_t possible_flag) { struct detect_processors_context context = { .max_processors_count = max_processors_count, .processor0_flags = processor0_flags, @@ -328,8 +374,11 @@ bool cpuinfo_linux_detect_possible_processors(uint32_t max_processors_count, } } -bool cpuinfo_linux_detect_present_processors(uint32_t max_processors_count, - uint32_t* processor0_flags, uint32_t processor_struct_size, uint32_t present_flag) { +bool cpuinfo_linux_detect_present_processors( + uint32_t max_processors_count, + uint32_t* processor0_flags, + uint32_t processor_struct_size, + uint32_t present_flag) { struct detect_processors_context context = { .max_processors_count = max_processors_count, .processor0_flags = processor0_flags, @@ -353,13 +402,17 @@ struct siblings_context { }; static bool siblings_parser(uint32_t sibling_list_start, uint32_t sibling_list_end, struct siblings_context* context) { - const char* group_name = context->group_name; - const uint32_t max_processors_count = context->max_processors_count; - const uint32_t processor = context->processor; + const char* group_name = context->group_name; + const uint32_t max_processors_count = context->max_processors_count; + const uint32_t processor = context->processor; if (sibling_list_end > max_processors_count) { - cpuinfo_log_warning("ignore %s siblings %"PRIu32"-%"PRIu32" of processor %"PRIu32, - group_name, max_processors_count, sibling_list_end - 1, processor); + cpuinfo_log_warning( + "ignore %s siblings %" PRIu32 "-%" PRIu32 " of processor %" PRIu32, + group_name, + max_processors_count, + sibling_list_end - 1, + processor); sibling_list_end = max_processors_count; } @@ -372,10 +425,10 @@ bool cpuinfo_linux_detect_core_cpus( cpuinfo_siblings_callback callback, void* context) { char core_cpus_filename[CORE_CPUS_FILENAME_SIZE]; - const int chars_formatted = snprintf( - core_cpus_filename, CORE_CPUS_FILENAME_SIZE, CORE_CPUS_FILENAME_FORMAT, processor); - if ((unsigned int) chars_formatted >= CORE_CPUS_FILENAME_SIZE) { - cpuinfo_log_warning("failed to format filename for core cpus of processor %"PRIu32, processor); + const int chars_formatted = + snprintf(core_cpus_filename, CORE_CPUS_FILENAME_SIZE, CORE_CPUS_FILENAME_FORMAT, processor); + if ((unsigned int)chars_formatted >= CORE_CPUS_FILENAME_SIZE) { + cpuinfo_log_warning("failed to format filename for core cpus of processor %" PRIu32, processor); return false; } @@ -386,12 +439,14 @@ bool cpuinfo_linux_detect_core_cpus( .callback = callback, .callback_context = context, }; - if (cpuinfo_linux_parse_cpulist(core_cpus_filename, - (cpuinfo_cpulist_callback) siblings_parser, &siblings_context)) { + if (cpuinfo_linux_parse_cpulist( + core_cpus_filename, (cpuinfo_cpulist_callback)siblings_parser, &siblings_context)) { return true; } else { - cpuinfo_log_info("failed to parse the list of core cpus for processor %"PRIu32" from %s", - processor, core_cpus_filename); + cpuinfo_log_info( + "failed to parse the list of core cpus for processor %" PRIu32 " from %s", + processor, + core_cpus_filename); return false; } } @@ -402,10 +457,10 @@ bool cpuinfo_linux_detect_core_siblings( cpuinfo_siblings_callback callback, void* context) { char core_siblings_filename[CORE_SIBLINGS_FILENAME_SIZE]; - const int chars_formatted = snprintf( - core_siblings_filename, CORE_SIBLINGS_FILENAME_SIZE, CORE_SIBLINGS_FILENAME_FORMAT, processor); - if ((unsigned int) chars_formatted >= CORE_SIBLINGS_FILENAME_SIZE) { - cpuinfo_log_warning("failed to format filename for core siblings of processor %"PRIu32, processor); + const int chars_formatted = + snprintf(core_siblings_filename, CORE_SIBLINGS_FILENAME_SIZE, CORE_SIBLINGS_FILENAME_FORMAT, processor); + if ((unsigned int)chars_formatted >= CORE_SIBLINGS_FILENAME_SIZE) { + cpuinfo_log_warning("failed to format filename for core siblings of processor %" PRIu32, processor); return false; } @@ -416,12 +471,14 @@ bool cpuinfo_linux_detect_core_siblings( .callback = callback, .callback_context = context, }; - if (cpuinfo_linux_parse_cpulist(core_siblings_filename, - (cpuinfo_cpulist_callback) siblings_parser, &siblings_context)) { + if (cpuinfo_linux_parse_cpulist( + core_siblings_filename, (cpuinfo_cpulist_callback)siblings_parser, &siblings_context)) { return true; } else { - cpuinfo_log_info("failed to parse the list of core siblings for processor %"PRIu32" from %s", - processor, core_siblings_filename); + cpuinfo_log_info( + "failed to parse the list of core siblings for processor %" PRIu32 " from %s", + processor, + core_siblings_filename); return false; } } @@ -434,8 +491,8 @@ bool cpuinfo_linux_detect_thread_siblings( char thread_siblings_filename[THREAD_SIBLINGS_FILENAME_SIZE]; const int chars_formatted = snprintf( thread_siblings_filename, THREAD_SIBLINGS_FILENAME_SIZE, THREAD_SIBLINGS_FILENAME_FORMAT, processor); - if ((unsigned int) chars_formatted >= THREAD_SIBLINGS_FILENAME_SIZE) { - cpuinfo_log_warning("failed to format filename for thread siblings of processor %"PRIu32, processor); + if ((unsigned int)chars_formatted >= THREAD_SIBLINGS_FILENAME_SIZE) { + cpuinfo_log_warning("failed to format filename for thread siblings of processor %" PRIu32, processor); return false; } @@ -446,12 +503,14 @@ bool cpuinfo_linux_detect_thread_siblings( .callback = callback, .callback_context = context, }; - if (cpuinfo_linux_parse_cpulist(thread_siblings_filename, - (cpuinfo_cpulist_callback) siblings_parser, &siblings_context)) { + if (cpuinfo_linux_parse_cpulist( + thread_siblings_filename, (cpuinfo_cpulist_callback)siblings_parser, &siblings_context)) { return true; } else { - cpuinfo_log_info("failed to parse the list of thread siblings for processor %"PRIu32" from %s", - processor, thread_siblings_filename); + cpuinfo_log_info( + "failed to parse the list of thread siblings for processor %" PRIu32 " from %s", + processor, + thread_siblings_filename); return false; } } @@ -462,10 +521,10 @@ bool cpuinfo_linux_detect_cluster_cpus( cpuinfo_siblings_callback callback, void* context) { char cluster_cpus_filename[CLUSTER_CPUS_FILENAME_SIZE]; - const int chars_formatted = snprintf( - cluster_cpus_filename, CLUSTER_CPUS_FILENAME_SIZE, CLUSTER_CPUS_FILENAME_FORMAT, processor); - if ((unsigned int) chars_formatted >= CLUSTER_CPUS_FILENAME_SIZE) { - cpuinfo_log_warning("failed to format filename for cluster cpus of processor %"PRIu32, processor); + const int chars_formatted = + snprintf(cluster_cpus_filename, CLUSTER_CPUS_FILENAME_SIZE, CLUSTER_CPUS_FILENAME_FORMAT, processor); + if ((unsigned int)chars_formatted >= CLUSTER_CPUS_FILENAME_SIZE) { + cpuinfo_log_warning("failed to format filename for cluster cpus of processor %" PRIu32, processor); return false; } @@ -476,12 +535,14 @@ bool cpuinfo_linux_detect_cluster_cpus( .callback = callback, .callback_context = context, }; - if (cpuinfo_linux_parse_cpulist(cluster_cpus_filename, - (cpuinfo_cpulist_callback) siblings_parser, &siblings_context)) { + if (cpuinfo_linux_parse_cpulist( + cluster_cpus_filename, (cpuinfo_cpulist_callback)siblings_parser, &siblings_context)) { return true; } else { - cpuinfo_log_info("failed to parse the list of cluster cpus for processor %"PRIu32" from %s", - processor, cluster_cpus_filename); + cpuinfo_log_info( + "failed to parse the list of cluster cpus for processor %" PRIu32 " from %s", + processor, + cluster_cpus_filename); return false; } } @@ -492,10 +553,10 @@ bool cpuinfo_linux_detect_package_cpus( cpuinfo_siblings_callback callback, void* context) { char package_cpus_filename[PACKAGE_CPUS_FILENAME_SIZE]; - const int chars_formatted = snprintf( - package_cpus_filename, PACKAGE_CPUS_FILENAME_SIZE, PACKAGE_CPUS_FILENAME_FORMAT, processor); - if ((unsigned int) chars_formatted >= PACKAGE_CPUS_FILENAME_SIZE) { - cpuinfo_log_warning("failed to format filename for package cpus of processor %"PRIu32, processor); + const int chars_formatted = + snprintf(package_cpus_filename, PACKAGE_CPUS_FILENAME_SIZE, PACKAGE_CPUS_FILENAME_FORMAT, processor); + if ((unsigned int)chars_formatted >= PACKAGE_CPUS_FILENAME_SIZE) { + cpuinfo_log_warning("failed to format filename for package cpus of processor %" PRIu32, processor); return false; } @@ -506,12 +567,14 @@ bool cpuinfo_linux_detect_package_cpus( .callback = callback, .callback_context = context, }; - if (cpuinfo_linux_parse_cpulist(package_cpus_filename, - (cpuinfo_cpulist_callback) siblings_parser, &siblings_context)) { + if (cpuinfo_linux_parse_cpulist( + package_cpus_filename, (cpuinfo_cpulist_callback)siblings_parser, &siblings_context)) { return true; } else { - cpuinfo_log_info("failed to parse the list of package cpus for processor %"PRIu32" from %s", - processor, package_cpus_filename); + cpuinfo_log_info( + "failed to parse the list of package cpus for processor %" PRIu32 " from %s", + processor, + package_cpus_filename); return false; } } diff --git a/src/linux/smallfile.c b/src/linux/smallfile.c index dbe023bb..6127c4e1 100644 --- a/src/linux/smallfile.c +++ b/src/linux/smallfile.c @@ -1,30 +1,33 @@ +#include +#include #include #include #include #include -#include -#include -#include +#include #include +#include #include -#include #if CPUINFO_MOCK - #include +#include #endif -#include #include +#include - -bool cpuinfo_linux_parse_small_file(const char* filename, size_t buffer_size, cpuinfo_smallfile_callback callback, void* context) { +bool cpuinfo_linux_parse_small_file( + const char* filename, + size_t buffer_size, + cpuinfo_smallfile_callback callback, + void* context) { int file = -1; bool status = false; - char* buffer = (char*) alloca(buffer_size); + char* buffer = (char*)alloca(buffer_size); - #if CPUINFO_LOG_DEBUG_PARSERS - cpuinfo_log_debug("parsing small file %s", filename); - #endif +#if CPUINFO_LOG_DEBUG_PARSERS + cpuinfo_log_debug("parsing small file %s", filename); +#endif #if CPUINFO_MOCK file = cpuinfo_mock_open(filename, O_RDONLY); @@ -45,12 +48,17 @@ bool cpuinfo_linux_parse_small_file(const char* filename, size_t buffer_size, cp bytes_read = read(file, &buffer[buffer_position], buffer_size - buffer_position); #endif if (bytes_read < 0) { - cpuinfo_log_info("failed to read file %s at position %zu: %s", filename, buffer_position, strerror(errno)); + cpuinfo_log_info( + "failed to read file %s at position %zu: %s", + filename, + buffer_position, + strerror(errno)); goto cleanup; } - buffer_position += (size_t) bytes_read; + buffer_position += (size_t)bytes_read; if (buffer_position >= buffer_size) { - cpuinfo_log_error("failed to read file %s: insufficient buffer of size %zu", filename, buffer_size); + cpuinfo_log_error( + "failed to read file %s: insufficient buffer of size %zu", filename, buffer_size); goto cleanup; } } while (bytes_read != 0); diff --git a/src/log.c b/src/log.c index bec604ee..2f85128d 100644 --- a/src/log.c +++ b/src/log.c @@ -1,192 +1,203 @@ #include #include -#include -#include #include +#include +#include #ifdef _WIN32 - #include +#include #else - #include +#include #endif #if defined(__ANDROID__) - #include +#include #endif #if defined(__hexagon__) - #include +#include #endif #ifndef CPUINFO_LOG_TO_STDIO - #if defined(__ANDROID__) - #define CPUINFO_LOG_TO_STDIO 0 - #else - #define CPUINFO_LOG_TO_STDIO 1 - #endif +#if defined(__ANDROID__) +#define CPUINFO_LOG_TO_STDIO 0 +#else +#define CPUINFO_LOG_TO_STDIO 1 +#endif #endif #include - -/* Messages up to this size are formatted entirely on-stack, and don't allocate heap memory */ +/* Messages up to this size are formatted entirely on-stack, and don't allocate + * heap memory */ #define CPUINFO_LOG_STACK_BUFFER_SIZE 1024 #ifdef _WIN32 - #define CPUINFO_LOG_NEWLINE_LENGTH 2 +#define CPUINFO_LOG_NEWLINE_LENGTH 2 - #define CPUINFO_LOG_STDERR STD_ERROR_HANDLE - #define CPUINFO_LOG_STDOUT STD_OUTPUT_HANDLE +#define CPUINFO_LOG_STDERR STD_ERROR_HANDLE +#define CPUINFO_LOG_STDOUT STD_OUTPUT_HANDLE #elif defined(__hexagon__) - #define CPUINFO_LOG_NEWLINE_LENGTH 1 +#define CPUINFO_LOG_NEWLINE_LENGTH 1 - #define CPUINFO_LOG_STDERR 0 - #define CPUINFO_LOG_STDOUT 0 +#define CPUINFO_LOG_STDERR 0 +#define CPUINFO_LOG_STDOUT 0 #else - #define CPUINFO_LOG_NEWLINE_LENGTH 1 +#define CPUINFO_LOG_NEWLINE_LENGTH 1 - #define CPUINFO_LOG_STDERR STDERR_FILENO - #define CPUINFO_LOG_STDOUT STDOUT_FILENO +#define CPUINFO_LOG_STDERR STDERR_FILENO +#define CPUINFO_LOG_STDOUT STDOUT_FILENO #endif #if CPUINFO_LOG_TO_STDIO -static void cpuinfo_vlog(int output_handle, const char* prefix, size_t prefix_length, const char* format, va_list args) { - char stack_buffer[CPUINFO_LOG_STACK_BUFFER_SIZE]; - char* heap_buffer = NULL; - char* out_buffer = &stack_buffer[0]; - - /* The first call to vsnprintf will clobber args, thus need a copy in case a second vsnprintf call is needed */ - va_list args_copy; - va_copy(args_copy, args); - - memcpy(stack_buffer, prefix, prefix_length * sizeof(char)); - assert((prefix_length + CPUINFO_LOG_NEWLINE_LENGTH) * sizeof(char) <= CPUINFO_LOG_STACK_BUFFER_SIZE); - - const int format_chars = vsnprintf( - &stack_buffer[prefix_length], - CPUINFO_LOG_STACK_BUFFER_SIZE - (prefix_length + CPUINFO_LOG_NEWLINE_LENGTH) * sizeof(char), - format, - args); - if (format_chars < 0) { - /* Format error in the message: silently ignore this particular message. */ - goto cleanup; - } - const size_t format_length = (size_t) format_chars; - if ((prefix_length + format_length + CPUINFO_LOG_NEWLINE_LENGTH) * sizeof(char) > CPUINFO_LOG_STACK_BUFFER_SIZE) { - /* Allocate a buffer on heap, and vsnprintf to this buffer */ - const size_t heap_buffer_size = (prefix_length + format_length + CPUINFO_LOG_NEWLINE_LENGTH) * sizeof(char); - #if _WIN32 - heap_buffer = HeapAlloc(GetProcessHeap(), 0, heap_buffer_size); - #else - heap_buffer = malloc(heap_buffer_size); - #endif - if (heap_buffer == NULL) { - goto cleanup; - } - - /* Copy pre-formatted prefix into the on-heap buffer */ - memcpy(heap_buffer, prefix, prefix_length * sizeof(char)); - vsnprintf(&heap_buffer[prefix_length], (format_length + CPUINFO_LOG_NEWLINE_LENGTH) * sizeof(char), format, args_copy); - out_buffer = heap_buffer; - } - #ifdef _WIN32 - out_buffer[prefix_length + format_length] = '\r'; - out_buffer[prefix_length + format_length + 1] = '\n'; - - DWORD bytes_written; - WriteFile( - GetStdHandle((DWORD) output_handle), - out_buffer, (prefix_length + format_length + CPUINFO_LOG_NEWLINE_LENGTH) * sizeof(char), - &bytes_written, NULL); - #elif defined(__hexagon__) - qurt_printf("%s", out_buffer); - #else - out_buffer[prefix_length + format_length] = '\n'; - - ssize_t bytes_written = write(output_handle, out_buffer, (prefix_length + format_length + CPUINFO_LOG_NEWLINE_LENGTH) * sizeof(char)); - (void) bytes_written; - #endif +static void cpuinfo_vlog( + int output_handle, + const char* prefix, + size_t prefix_length, + const char* format, + va_list args) { + char stack_buffer[CPUINFO_LOG_STACK_BUFFER_SIZE]; + char* heap_buffer = NULL; + char* out_buffer = &stack_buffer[0]; + + /* The first call to vsnprintf will clobber args, thus need a copy in + * case a second vsnprintf call is needed */ + va_list args_copy; + va_copy(args_copy, args); + + memcpy(stack_buffer, prefix, prefix_length * sizeof(char)); + assert((prefix_length + CPUINFO_LOG_NEWLINE_LENGTH) * sizeof(char) <= CPUINFO_LOG_STACK_BUFFER_SIZE); + + const int format_chars = vsnprintf( + &stack_buffer[prefix_length], + CPUINFO_LOG_STACK_BUFFER_SIZE - (prefix_length + CPUINFO_LOG_NEWLINE_LENGTH) * sizeof(char), + format, + args); + if (format_chars < 0) { + /* Format error in the message: silently ignore this particular + * message. */ + goto cleanup; + } + const size_t format_length = (size_t)format_chars; + if ((prefix_length + format_length + CPUINFO_LOG_NEWLINE_LENGTH) * sizeof(char) > + CPUINFO_LOG_STACK_BUFFER_SIZE) { + /* Allocate a buffer on heap, and vsnprintf to this buffer */ + const size_t heap_buffer_size = + (prefix_length + format_length + CPUINFO_LOG_NEWLINE_LENGTH) * sizeof(char); +#if _WIN32 + heap_buffer = HeapAlloc(GetProcessHeap(), 0, heap_buffer_size); +#else + heap_buffer = malloc(heap_buffer_size); +#endif + if (heap_buffer == NULL) { + goto cleanup; + } + + /* Copy pre-formatted prefix into the on-heap buffer */ + memcpy(heap_buffer, prefix, prefix_length * sizeof(char)); + vsnprintf( + &heap_buffer[prefix_length], + (format_length + CPUINFO_LOG_NEWLINE_LENGTH) * sizeof(char), + format, + args_copy); + out_buffer = heap_buffer; + } +#ifdef _WIN32 + out_buffer[prefix_length + format_length] = '\r'; + out_buffer[prefix_length + format_length + 1] = '\n'; + + DWORD bytes_written; + WriteFile( + GetStdHandle((DWORD)output_handle), + out_buffer, + (prefix_length + format_length + CPUINFO_LOG_NEWLINE_LENGTH) * sizeof(char), + &bytes_written, + NULL); +#elif defined(__hexagon__) + qurt_printf("%s", out_buffer); +#else + out_buffer[prefix_length + format_length] = '\n'; + + ssize_t bytes_written = write( + output_handle, out_buffer, (prefix_length + format_length + CPUINFO_LOG_NEWLINE_LENGTH) * sizeof(char)); + (void)bytes_written; +#endif cleanup: - #ifdef _WIN32 - HeapFree(GetProcessHeap(), 0, heap_buffer); - #else - free(heap_buffer); - #endif - va_end(args_copy); +#ifdef _WIN32 + HeapFree(GetProcessHeap(), 0, heap_buffer); +#else + free(heap_buffer); +#endif + va_end(args_copy); } #elif defined(__ANDROID__) && CPUINFO_LOG_LEVEL > CPUINFO_LOG_NONE - static const char cpuinfo_module[] = "XNNPACK"; +static const char cpuinfo_module[] = "XNNPACK"; #endif #if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_DEBUG - void cpuinfo_vlog_debug(const char* format, va_list args) { - #if CPUINFO_LOG_TO_STDIO - static const char debug_prefix[17] = { - 'D', 'e', 'b', 'u', 'g', ' ', '(', 'c', 'p', 'u', 'i', 'n', 'f', 'o', ')', ':', ' ' - }; - cpuinfo_vlog(CPUINFO_LOG_STDOUT, debug_prefix, 17, format, args); - #elif defined(__ANDROID__) - __android_log_vprint(ANDROID_LOG_DEBUG, cpuinfo_module, format, args); - #else - #error "Platform-specific implementation required" - #endif - } +void cpuinfo_vlog_debug(const char* format, va_list args) { +#if CPUINFO_LOG_TO_STDIO + static const char debug_prefix[17] = { + 'D', 'e', 'b', 'u', 'g', ' ', '(', 'c', 'p', 'u', 'i', 'n', 'f', 'o', ')', ':', ' '}; + cpuinfo_vlog(CPUINFO_LOG_STDOUT, debug_prefix, 17, format, args); +#elif defined(__ANDROID__) + __android_log_vprint(ANDROID_LOG_DEBUG, cpuinfo_module, format, args); +#else +#error "Platform-specific implementation required" +#endif +} #endif #if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_INFO - void cpuinfo_vlog_info(const char* format, va_list args) { - #if CPUINFO_LOG_TO_STDIO - static const char info_prefix[16] = { - 'N', 'o', 't', 'e', ' ', '(', 'c', 'p', 'u', 'i', 'n', 'f', 'o', ')', ':', ' ' - }; - cpuinfo_vlog(CPUINFO_LOG_STDOUT, info_prefix, 16, format, args); - #elif defined(__ANDROID__) - __android_log_vprint(ANDROID_LOG_INFO, cpuinfo_module, format, args); - #else - #error "Platform-specific implementation required" - #endif - } +void cpuinfo_vlog_info(const char* format, va_list args) { +#if CPUINFO_LOG_TO_STDIO + static const char info_prefix[16] = { + 'N', 'o', 't', 'e', ' ', '(', 'c', 'p', 'u', 'i', 'n', 'f', 'o', ')', ':', ' '}; + cpuinfo_vlog(CPUINFO_LOG_STDOUT, info_prefix, 16, format, args); +#elif defined(__ANDROID__) + __android_log_vprint(ANDROID_LOG_INFO, cpuinfo_module, format, args); +#else +#error "Platform-specific implementation required" +#endif +} #endif #if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_WARNING - void cpuinfo_vlog_warning(const char* format, va_list args) { - #if CPUINFO_LOG_TO_STDIO - static const char warning_prefix[20] = { - 'W', 'a', 'r', 'n', 'i', 'n', 'g', ' ', 'i', 'n', ' ', 'c', 'p', 'u', 'i', 'n', 'f', 'o', ':', ' ' - }; - cpuinfo_vlog(CPUINFO_LOG_STDERR, warning_prefix, 20, format, args); - #elif defined(__ANDROID__) - __android_log_vprint(ANDROID_LOG_WARN, cpuinfo_module, format, args); - #else - #error "Platform-specific implementation required" - #endif - } +void cpuinfo_vlog_warning(const char* format, va_list args) { +#if CPUINFO_LOG_TO_STDIO + static const char warning_prefix[20] = {'W', 'a', 'r', 'n', 'i', 'n', 'g', ' ', 'i', 'n', + ' ', 'c', 'p', 'u', 'i', 'n', 'f', 'o', ':', ' '}; + cpuinfo_vlog(CPUINFO_LOG_STDERR, warning_prefix, 20, format, args); +#elif defined(__ANDROID__) + __android_log_vprint(ANDROID_LOG_WARN, cpuinfo_module, format, args); +#else +#error "Platform-specific implementation required" +#endif +} #endif #if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_ERROR - void cpuinfo_vlog_error(const char* format, va_list args) { - #if CPUINFO_LOG_TO_STDIO - static const char error_prefix[18] = { - 'E', 'r', 'r', 'o', 'r', ' ', 'i', 'n', ' ', 'c', 'p', 'u', 'i', 'n', 'f', 'o', ':', ' ' - }; - cpuinfo_vlog(CPUINFO_LOG_STDERR, error_prefix, 18, format, args); - #elif defined(__ANDROID__) - __android_log_vprint(ANDROID_LOG_ERROR, cpuinfo_module, format, args); - #else - #error "Platform-specific implementation required" - #endif - } +void cpuinfo_vlog_error(const char* format, va_list args) { +#if CPUINFO_LOG_TO_STDIO + static const char error_prefix[18] = { + 'E', 'r', 'r', 'o', 'r', ' ', 'i', 'n', ' ', 'c', 'p', 'u', 'i', 'n', 'f', 'o', ':', ' '}; + cpuinfo_vlog(CPUINFO_LOG_STDERR, error_prefix, 18, format, args); +#elif defined(__ANDROID__) + __android_log_vprint(ANDROID_LOG_ERROR, cpuinfo_module, format, args); +#else +#error "Platform-specific implementation required" +#endif +} #endif #if CPUINFO_LOG_LEVEL >= CPUINFO_LOG_FATAL - void cpuinfo_vlog_fatal(const char* format, va_list args) { - #if CPUINFO_LOG_TO_STDIO - static const char fatal_prefix[24] = { - 'F', 'a', 't', 'a', 'l', ' ', 'e', 'r', 'r', 'o', 'r', ' ', 'i', 'n', ' ', 'c', 'p', 'u', 'i', 'n', 'f', 'o', ':', ' ' - }; - cpuinfo_vlog(CPUINFO_LOG_STDERR, fatal_prefix, 24, format, args); - #elif defined(__ANDROID__) - __android_log_vprint(ANDROID_LOG_FATAL, cpuinfo_module, format, args); - #else - #error "Platform-specific implementation required" - #endif - } +void cpuinfo_vlog_fatal(const char* format, va_list args) { +#if CPUINFO_LOG_TO_STDIO + static const char fatal_prefix[24] = {'F', 'a', 't', 'a', 'l', ' ', 'e', 'r', 'r', 'o', 'r', ' ', + 'i', 'n', ' ', 'c', 'p', 'u', 'i', 'n', 'f', 'o', ':', ' '}; + cpuinfo_vlog(CPUINFO_LOG_STDERR, fatal_prefix, 24, format, args); +#elif defined(__ANDROID__) + __android_log_vprint(ANDROID_LOG_FATAL, cpuinfo_module, format, args); +#else +#error "Platform-specific implementation required" +#endif +} #endif diff --git a/src/mach/api.h b/src/mach/api.h index fdef5bdf..339aeff4 100644 --- a/src/mach/api.h +++ b/src/mach/api.h @@ -4,7 +4,6 @@ #define CPUINFO_MACH_MAX_CACHE_LEVELS 8 - struct cpuinfo_mach_topology { uint32_t packages; uint32_t cores; @@ -12,5 +11,4 @@ struct cpuinfo_mach_topology { uint32_t threads_per_cache[CPUINFO_MACH_MAX_CACHE_LEVELS]; }; - struct cpuinfo_mach_topology cpuinfo_mach_detect_topology(void); diff --git a/src/mach/topology.c b/src/mach/topology.c index b56343bb..53160ce1 100644 --- a/src/mach/topology.c +++ b/src/mach/topology.c @@ -1,16 +1,15 @@ -#include #include #include +#include -#include #include +#include #include #include #include - struct cpuinfo_mach_topology cpuinfo_mach_detect_topology(void) { int cores = 1; size_t sizeof_cores = sizeof(cores); @@ -41,12 +40,9 @@ struct cpuinfo_mach_topology cpuinfo_mach_detect_topology(void) { } #endif - cpuinfo_log_debug("mach topology: packages = %d, cores = %d, threads = %d", packages, (int) cores, (int) threads); + cpuinfo_log_debug("mach topology: packages = %d, cores = %d, threads = %d", packages, (int)cores, (int)threads); struct cpuinfo_mach_topology topology = { - .packages = (uint32_t) packages, - .cores = (uint32_t) cores, - .threads = (uint32_t) threads - }; + .packages = (uint32_t)packages, .cores = (uint32_t)cores, .threads = (uint32_t)threads}; #if !TARGET_OS_IPHONE size_t cacheconfig_size = 0; @@ -63,7 +59,7 @@ struct cpuinfo_mach_topology cpuinfo_mach_detect_topology(void) { cache_configs = CPUINFO_MACH_MAX_CACHE_LEVELS; } for (size_t i = 0; i < cache_configs; i++) { - cpuinfo_log_debug("mach hw.cacheconfig[%zu]: %"PRIu64, i, cacheconfig[i]); + cpuinfo_log_debug("mach hw.cacheconfig[%zu]: %" PRIu64, i, cacheconfig[i]); topology.threads_per_cache[i] = cacheconfig[i]; } } diff --git a/src/riscv/api.h b/src/riscv/api.h index fc2220cb..d4f507b4 100644 --- a/src/riscv/api.h +++ b/src/riscv/api.h @@ -35,8 +35,8 @@ enum cpuinfo_riscv_chipset_impl { * @param[uarch] - Reference to the cpuinfo_uarch to populate. */ CPUINFO_INTERNAL void cpuinfo_riscv_decode_vendor_uarch( - uint32_t vendor_id, - uint32_t arch_id, - uint32_t imp_id, - enum cpuinfo_vendor vendor[restrict static 1], - enum cpuinfo_uarch uarch[restrict static 1]); + uint32_t vendor_id, + uint32_t arch_id, + uint32_t imp_id, + enum cpuinfo_vendor vendor[restrict static 1], + enum cpuinfo_uarch uarch[restrict static 1]); diff --git a/src/riscv/linux/api.h b/src/riscv/linux/api.h index 5f1a8cf3..829de84b 100644 --- a/src/riscv/linux/api.h +++ b/src/riscv/linux/api.h @@ -22,23 +22,26 @@ struct cpuinfo_riscv_linux_processor { uint32_t flags; /** - * Minimum processor ID on the cluster which includes this logical processor. - * This value can serve as an ID for the cluster of logical processors: it is the - * same for all logical processors on the same package. + * Minimum processor ID on the cluster which includes this logical + * processor. This value can serve as an ID for the cluster of logical + * processors: it is the same for all logical processors on the same + * package. */ uint32_t cluster_leader_id; /** - * Minimum processor ID on the core which includes this logical processor. - * This value can serve as an ID for the core of logical processors: it - * is the same for all logical processors on the same core. + * Minimum processor ID on the core which includes this logical + * processor. This value can serve as an ID for the core of logical + * processors: it is the same for all logical processors on the same + * core. */ uint32_t core_leader_id; /** - * Minimum processor ID on the package which includes this logical processor. - * This value can serve as an ID for the package of logical processors: it - * is the same for all logical processors on the same package. + * Minimum processor ID on the package which includes this logical + * processor. This value can serve as an ID for the package of logical + * processors: it is the same for all logical processors on the same + * package. */ uint32_t package_leader_id; }; @@ -49,8 +52,7 @@ struct cpuinfo_riscv_linux_processor { * * @param[isa] - Reference to cpuinfo_riscv_isa structure to populate. */ -CPUINFO_INTERNAL void cpuinfo_riscv_linux_decode_isa_from_hwcap( - struct cpuinfo_riscv_isa isa[restrict static 1]); +CPUINFO_INTERNAL void cpuinfo_riscv_linux_decode_isa_from_hwcap(struct cpuinfo_riscv_isa isa[restrict static 1]); /** * Reads `sys_riscv_hwprobe` and determines the processor vendor and diff --git a/src/riscv/linux/init.c b/src/riscv/linux/init.c index d1c43c54..9ab3d6e6 100644 --- a/src/riscv/linux/init.c +++ b/src/riscv/linux/init.c @@ -10,7 +10,7 @@ struct cpuinfo_riscv_isa cpuinfo_isa; /* Helper function to bitmask flags and ensure operator precedence. */ static inline bool bitmask_all(uint32_t flags, uint32_t mask) { - return (flags & mask) == mask; + return (flags & mask) == mask; } static int compare_riscv_linux_processors(const void* a, const void* b) { @@ -18,8 +18,8 @@ static int compare_riscv_linux_processors(const void* a, const void* b) { * For our purposes, it is only relevant that the list is sorted by * micro-architecture, so the nature of ordering is irrelevant. */ - return ((const struct cpuinfo_riscv_linux_processor*)a)->core.uarch - - ((const struct cpuinfo_riscv_linux_processor*)b)->core.uarch; + return ((const struct cpuinfo_riscv_linux_processor*)a)->core.uarch - + ((const struct cpuinfo_riscv_linux_processor*)b)->core.uarch; } /** @@ -37,10 +37,11 @@ static int compare_riscv_linux_processors(const void* a, const void* b) { * E.g. processors[0].core_leader_id = 0. */ -static bool core_cpus_parser(uint32_t processor, - uint32_t core_cpus_start, - uint32_t core_cpus_end, - struct cpuinfo_riscv_linux_processor* processors) { +static bool core_cpus_parser( + uint32_t processor, + uint32_t core_cpus_start, + uint32_t core_cpus_end, + struct cpuinfo_riscv_linux_processor* processors) { uint32_t processor_start = UINT32_MAX; uint32_t processor_count = 0; @@ -70,8 +71,8 @@ static bool core_cpus_parser(uint32_t processor, * * e.g. core_cpu_list=1,10-12 */ - if (!bitmask_all(processors[processor].flags, CPUINFO_LINUX_FLAG_CORE_CLUSTER) - || processors[processor].core.processor_start > processor_start) { + if (!bitmask_all(processors[processor].flags, CPUINFO_LINUX_FLAG_CORE_CLUSTER) || + processors[processor].core.processor_start > processor_start) { processors[processor].core.processor_start = processor_start; processors[processor].core_leader_id = processor_start; } @@ -92,10 +93,11 @@ static bool core_cpus_parser(uint32_t processor, * their 'cluster_leader_id' to their index in the list. * E.g. processors[0].cluster_leader_id = 0. */ -static bool cluster_cpus_parser(uint32_t processor, - uint32_t cluster_cpus_start, - uint32_t cluster_cpus_end, - struct cpuinfo_riscv_linux_processor* processors) { +static bool cluster_cpus_parser( + uint32_t processor, + uint32_t cluster_cpus_start, + uint32_t cluster_cpus_end, + struct cpuinfo_riscv_linux_processor* processors) { uint32_t processor_start = UINT32_MAX; uint32_t processor_count = 0; uint32_t core_count = 0; @@ -133,8 +135,8 @@ static bool cluster_cpus_parser(uint32_t processor, * * e.g. cluster_cpus_list=1,10-12 */ - if (!bitmask_all(processors[processor].flags, CPUINFO_LINUX_FLAG_CLUSTER_CLUSTER) - || processors[processor].cluster.processor_start > processor_start) { + if (!bitmask_all(processors[processor].flags, CPUINFO_LINUX_FLAG_CLUSTER_CLUSTER) || + processors[processor].cluster.processor_start > processor_start) { processors[processor].cluster.processor_start = processor_start; processors[processor].cluster.core_start = processor_start; processors[processor].cluster.cluster_id = processor_start; @@ -160,10 +162,11 @@ static bool cluster_cpus_parser(uint32_t processor, * their 'package_leader_id' to their index in the list. * E.g. processors[0].package_leader_id = 0. */ -static bool package_cpus_parser(uint32_t processor, - uint32_t package_cpus_start, - uint32_t package_cpus_end, - struct cpuinfo_riscv_linux_processor* processors) { +static bool package_cpus_parser( + uint32_t processor, + uint32_t package_cpus_start, + uint32_t package_cpus_end, + struct cpuinfo_riscv_linux_processor* processors) { uint32_t processor_start = UINT32_MAX; uint32_t processor_count = 0; uint32_t cluster_count = 0; @@ -205,8 +208,8 @@ static bool package_cpus_parser(uint32_t processor, * * e.g. package_cpus_list=1,10-12 */ - if (!bitmask_all(processors[processor].flags, CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER) - || processors[processor].package.processor_start > processor_start) { + if (!bitmask_all(processors[processor].flags, CPUINFO_LINUX_FLAG_PACKAGE_CLUSTER) || + processors[processor].package.processor_start > processor_start) { processors[processor].package.processor_start = processor_start; processors[processor].package.cluster_start = processor_start; processors[processor].package.core_start = processor_start; @@ -233,8 +236,9 @@ void cpuinfo_riscv_linux_init(void) { /** * The interesting set of processors are the number of 'present' - * processors on the system. There may be more 'possible' processors, but - * processor information cannot be gathered on non-present processors. + * processors on the system. There may be more 'possible' processors, + * but processor information cannot be gathered on non-present + * processors. * * Note: For SoCs, it is largely the case that all processors are known * at boot and no processors are hotplugged at runtime, so the @@ -244,9 +248,8 @@ void cpuinfo_riscv_linux_init(void) { * processors. It is not a count of the number of processors on the * system. */ - const uint32_t max_processor_id = 1 + - cpuinfo_linux_get_max_present_processor( - cpuinfo_linux_get_max_processors_count()); + const uint32_t max_processor_id = + 1 + cpuinfo_linux_get_max_present_processor(cpuinfo_linux_get_max_processors_count()); if (max_processor_id == 0) { cpuinfo_log_error("failed to discover any processors"); return; @@ -257,35 +260,36 @@ void cpuinfo_riscv_linux_init(void) { * sized to the max processor ID as opposed to the number of 'present' * processors, to leverage pointer math in the common utility functions. */ - riscv_linux_processors = calloc(max_processor_id, - sizeof(struct cpuinfo_riscv_linux_processor)); + riscv_linux_processors = calloc(max_processor_id, sizeof(struct cpuinfo_riscv_linux_processor)); if (riscv_linux_processors == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for %"PRIu32" processors.", + cpuinfo_log_error( + "failed to allocate %zu bytes for %" PRIu32 " processors.", max_processor_id * sizeof(struct cpuinfo_riscv_linux_processor), max_processor_id); goto cleanup; - } + } /** * Attempt to detect all processors and apply the corresponding flag to * each processor struct that we find. */ - if (!cpuinfo_linux_detect_present_processors(max_processor_id, - &riscv_linux_processors->flags, - sizeof(struct cpuinfo_riscv_linux_processor), - CPUINFO_LINUX_FLAG_PRESENT | CPUINFO_LINUX_FLAG_VALID)) { + if (!cpuinfo_linux_detect_present_processors( + max_processor_id, + &riscv_linux_processors->flags, + sizeof(struct cpuinfo_riscv_linux_processor), + CPUINFO_LINUX_FLAG_PRESENT | CPUINFO_LINUX_FLAG_VALID)) { cpuinfo_log_error("failed to detect present processors"); goto cleanup; } - /* Populate processor information. */ - for (size_t processor = 0; processor < max_processor_id; processor++) { + /* Populate processor information. */ + for (size_t processor = 0; processor < max_processor_id; processor++) { if (!bitmask_all(riscv_linux_processors[processor].flags, CPUINFO_LINUX_FLAG_VALID)) { continue; - } - /* TODO: Determine if an 'smt_id' is available. */ - riscv_linux_processors[processor].processor.linux_id = processor; - } + } + /* TODO: Determine if an 'smt_id' is available. */ + riscv_linux_processors[processor].processor.linux_id = processor; + } /* Populate core information. */ for (size_t processor = 0; processor < max_processor_id; processor++) { @@ -295,18 +299,16 @@ void cpuinfo_riscv_linux_init(void) { /* Populate processor start and count information. */ if (!cpuinfo_linux_detect_core_cpus( - max_processor_id, - processor, - (cpuinfo_siblings_callback) core_cpus_parser, - riscv_linux_processors)) { + max_processor_id, + processor, + (cpuinfo_siblings_callback)core_cpus_parser, + riscv_linux_processors)) { cpuinfo_log_error("failed to detect core cpus for processor %zu.", processor); goto cleanup; } /* Populate core ID information. */ - if (cpuinfo_linux_get_processor_core_id( - processor, - &riscv_linux_processors[processor].core.core_id)) { + if (cpuinfo_linux_get_processor_core_id(processor, &riscv_linux_processors[processor].core.core_id)) { riscv_linux_processors[processor].flags |= CPUINFO_LINUX_FLAG_CORE_ID; } @@ -316,9 +318,9 @@ void cpuinfo_riscv_linux_init(void) { * the values from the core leader will be honored. */ cpuinfo_riscv_linux_decode_vendor_uarch_from_hwprobe( - processor, - &riscv_linux_processors[processor].core.vendor, - &riscv_linux_processors[processor].core.uarch); + processor, + &riscv_linux_processors[processor].core.vendor, + &riscv_linux_processors[processor].core.uarch); /* Populate frequency information of this core. */ uint32_t frequency = cpuinfo_linux_get_processor_cur_frequency(processor); @@ -334,25 +336,23 @@ void cpuinfo_riscv_linux_init(void) { continue; } if (!cpuinfo_linux_detect_cluster_cpus( - max_processor_id, - processor, - (cpuinfo_siblings_callback) cluster_cpus_parser, - riscv_linux_processors)) { + max_processor_id, + processor, + (cpuinfo_siblings_callback)cluster_cpus_parser, + riscv_linux_processors)) { cpuinfo_log_warning("failed to detect cluster cpus for processor %zu.", processor); goto cleanup; } /** * Populate the vendor, uarch and frequency of this cluster from - * this logical processor. When the 'clusters' list is constructed, - * only the values from the cluster leader will be honored. + * this logical processor. When the 'clusters' list is + * constructed, only the values from the cluster leader will be + * honored. */ - riscv_linux_processors[processor].cluster.vendor = - riscv_linux_processors[processor].core.vendor; - riscv_linux_processors[processor].cluster.uarch = - riscv_linux_processors[processor].core.uarch; - riscv_linux_processors[processor].cluster.frequency = - riscv_linux_processors[processor].core.frequency; + riscv_linux_processors[processor].cluster.vendor = riscv_linux_processors[processor].core.vendor; + riscv_linux_processors[processor].cluster.uarch = riscv_linux_processors[processor].core.uarch; + riscv_linux_processors[processor].cluster.frequency = riscv_linux_processors[processor].core.frequency; } /* Populate package information. */ @@ -361,10 +361,10 @@ void cpuinfo_riscv_linux_init(void) { continue; } if (!cpuinfo_linux_detect_package_cpus( - max_processor_id, - processor, - (cpuinfo_siblings_callback) package_cpus_parser, - riscv_linux_processors)) { + max_processor_id, + processor, + (cpuinfo_siblings_callback)package_cpus_parser, + riscv_linux_processors)) { cpuinfo_log_warning("failed to detect package cpus for processor %zu.", processor); goto cleanup; } @@ -424,45 +424,44 @@ void cpuinfo_riscv_linux_init(void) { * As we've sorted by micro-architecture, when the uarch differs * between two entries, a unique uarch has been observed. */ - if (last_uarch != riscv_linux_processors[processor].core.uarch - || valid_uarchs_count == 0) { + if (last_uarch != riscv_linux_processors[processor].core.uarch || valid_uarchs_count == 0) { valid_uarchs_count++; last_uarch = riscv_linux_processors[processor].core.uarch; } } /* Allocate and populate final public ABI structures. */ - processors = calloc(valid_processors_count, - sizeof(struct cpuinfo_processor)); + processors = calloc(valid_processors_count, sizeof(struct cpuinfo_processor)); if (processors == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for %zu processors.", + cpuinfo_log_error( + "failed to allocate %zu bytes for %zu processors.", valid_processors_count * sizeof(struct cpuinfo_processor), valid_processors_count); goto cleanup; } - cores = calloc(valid_cores_count, - sizeof(struct cpuinfo_core)); + cores = calloc(valid_cores_count, sizeof(struct cpuinfo_core)); if (cores == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for %zu cores.", + cpuinfo_log_error( + "failed to allocate %zu bytes for %zu cores.", valid_cores_count * sizeof(struct cpuinfo_core), valid_cores_count); goto cleanup; } - clusters = calloc(valid_clusters_count, - sizeof(struct cpuinfo_cluster)); + clusters = calloc(valid_clusters_count, sizeof(struct cpuinfo_cluster)); if (clusters == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for %zu clusters.", + cpuinfo_log_error( + "failed to allocate %zu bytes for %zu clusters.", valid_clusters_count * sizeof(struct cpuinfo_cluster), valid_clusters_count); goto cleanup; } - packages = calloc(valid_packages_count, - sizeof(struct cpuinfo_package)); + packages = calloc(valid_packages_count, sizeof(struct cpuinfo_package)); if (packages == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for %zu packages.", + cpuinfo_log_error( + "failed to allocate %zu bytes for %zu packages.", valid_packages_count * sizeof(struct cpuinfo_package), valid_packages_count); goto cleanup; @@ -470,36 +469,37 @@ void cpuinfo_riscv_linux_init(void) { uarchs = calloc(valid_uarchs_count, sizeof(struct cpuinfo_uarch_info)); if (uarchs == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for %zu packages.", + cpuinfo_log_error( + "failed to allocate %zu bytes for %zu packages.", valid_uarchs_count * sizeof(struct cpuinfo_uarch_info), valid_uarchs_count); goto cleanup; } - linux_cpu_to_processor_map = calloc(max_processor_id, - sizeof(struct cpuinfo_processor*)); + linux_cpu_to_processor_map = calloc(max_processor_id, sizeof(struct cpuinfo_processor*)); if (linux_cpu_to_processor_map == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for %"PRIu32" processor map.", - max_processor_id * sizeof(struct cpuinfo_processor*), - max_processor_id); + cpuinfo_log_error( + "failed to allocate %zu bytes for %" PRIu32 " processor map.", + max_processor_id * sizeof(struct cpuinfo_processor*), + max_processor_id); goto cleanup; } - linux_cpu_to_core_map = calloc(max_processor_id, - sizeof(struct cpuinfo_core*)); + linux_cpu_to_core_map = calloc(max_processor_id, sizeof(struct cpuinfo_core*)); if (linux_cpu_to_core_map == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for %"PRIu32" core map.", - max_processor_id * sizeof(struct cpuinfo_core*), - max_processor_id); + cpuinfo_log_error( + "failed to allocate %zu bytes for %" PRIu32 " core map.", + max_processor_id * sizeof(struct cpuinfo_core*), + max_processor_id); goto cleanup; } - linux_cpu_to_uarch_index_map = calloc(max_processor_id, - sizeof(struct cpuinfo_uarch_info*)); + linux_cpu_to_uarch_index_map = calloc(max_processor_id, sizeof(struct cpuinfo_uarch_info*)); if (linux_cpu_to_uarch_index_map == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for %"PRIu32" uarch map.", - max_processor_id * sizeof(struct cpuinfo_uarch_info*), - max_processor_id); + cpuinfo_log_error( + "failed to allocate %zu bytes for %" PRIu32 " uarch map.", + max_processor_id * sizeof(struct cpuinfo_uarch_info*), + max_processor_id); goto cleanup; } @@ -524,17 +524,15 @@ void cpuinfo_riscv_linux_init(void) { uint32_t linux_id = riscv_linux_processors[processor].processor.linux_id; /* Create uarch entry if this uarch has not been seen before. */ - if (last_uarch != riscv_linux_processors[processor].core.uarch - || valid_uarchs_index == 0) { - uarchs[valid_uarchs_index++].uarch = - riscv_linux_processors[processor].core.uarch; + if (last_uarch != riscv_linux_processors[processor].core.uarch || valid_uarchs_index == 0) { + uarchs[valid_uarchs_index++].uarch = riscv_linux_processors[processor].core.uarch; last_uarch = riscv_linux_processors[processor].core.uarch; } /* Copy cpuinfo_processor information. */ memcpy(&processors[valid_processors_index++], &riscv_linux_processors[processor].processor, - sizeof(struct cpuinfo_processor)); + sizeof(struct cpuinfo_processor)); /* Update uarch processor count. */ uarchs[valid_uarchs_index - 1].processor_count++; @@ -598,7 +596,8 @@ void cpuinfo_riscv_linux_init(void) { cpuinfo_is_initialized = true; - /* Mark all public structures NULL to prevent cleanup from erasing them. */ + /* Mark all public structures NULL to prevent cleanup from erasing them. + */ processors = NULL; cores = NULL; clusters = NULL; diff --git a/src/riscv/linux/riscv-hw.c b/src/riscv/linux/riscv-hw.c index f589b3fc..243ca870 100644 --- a/src/riscv/linux/riscv-hw.c +++ b/src/riscv/linux/riscv-hw.c @@ -5,15 +5,16 @@ * #ifdef __ANDROID__ check will be removed in the future. */ #ifdef __ANDROID__ - #ifdef __has_include - #if __has_include () - #define CPUINFO_RISCV_LINUX_HAVE_C_HWPROBE - #include - #endif - #endif +#ifdef __has_include +#if __has_include() +#define CPUINFO_RISCV_LINUX_HAVE_C_HWPROBE +#include +#endif +#endif #endif #include +#include #include #include @@ -21,62 +22,68 @@ #ifndef CPUINFO_RISCV_LINUX_HAVE_C_HWPROBE - #include - #include - #include +#include +#include +#include - struct riscv_hwprobe { - int64_t key; - uint64_t value; - }; +struct riscv_hwprobe { + int64_t key; + uint64_t value; +}; - /* - * The standard C library our binary was compiled with does not support - * hwprobe but the kernel on which we are running might do. The - * constants below are copied from - * /usr/include/riscv64-linux-gnu/asm/hwprobe.h. They allow us to - * invoke the hwprobe syscall directly. We duplicate the constants - * rather than including the kernel hwprobe.h header, as this header - * will only be present if we're building Linux 6.4 or greater. - */ +/* + * The standard C library our binary was compiled with does not support + * hwprobe but the kernel on which we are running might do. The + * constants below are copied from + * /usr/include/riscv64-linux-gnu/asm/hwprobe.h. They allow us to + * invoke the hwprobe syscall directly. We duplicate the constants + * rather than including the kernel hwprobe.h header, as this header + * will only be present if we're building Linux 6.4 or greater. + */ - #define RISCV_HWPROBE_KEY_MVENDORID 0 - #define RISCV_HWPROBE_KEY_MARCHID 1 - #define RISCV_HWPROBE_KEY_MIMPID 2 - #define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3 - #define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0) - #define RISCV_HWPROBE_KEY_IMA_EXT_0 4 - #define RISCV_HWPROBE_IMA_FD (1 << 0) - #define RISCV_HWPROBE_IMA_C (1 << 1) - #define RISCV_HWPROBE_IMA_V (1 << 2) - #define RISCV_HWPROBE_EXT_ZBA (1 << 3) - #define RISCV_HWPROBE_EXT_ZBB (1 << 4) - #define RISCV_HWPROBE_EXT_ZBS (1 << 5) - #define RISCV_HWPROBE_EXT_ZICBOZ (1 << 6) - #define RISCV_HWPROBE_KEY_CPUPERF_0 5 - #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) - #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) - #define RISCV_HWPROBE_MISALIGNED_SLOW (2 << 0) - #define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0) - #define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0) - #define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0) +#define RISCV_HWPROBE_KEY_MVENDORID 0 +#define RISCV_HWPROBE_KEY_MARCHID 1 +#define RISCV_HWPROBE_KEY_MIMPID 2 +#define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3 +#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0) +#define RISCV_HWPROBE_KEY_IMA_EXT_0 4 +#define RISCV_HWPROBE_IMA_FD (1 << 0) +#define RISCV_HWPROBE_IMA_C (1 << 1) +#define RISCV_HWPROBE_IMA_V (1 << 2) +#define RISCV_HWPROBE_EXT_ZBA (1 << 3) +#define RISCV_HWPROBE_EXT_ZBB (1 << 4) +#define RISCV_HWPROBE_EXT_ZBS (1 << 5) +#define RISCV_HWPROBE_EXT_ZICBOZ (1 << 6) +#define RISCV_HWPROBE_KEY_CPUPERF_0 5 +#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) +#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) +#define RISCV_HWPROBE_MISALIGNED_SLOW (2 << 0) +#define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0) +#define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0) +#define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0) - #ifndef NR_riscv_hwprobe - #ifndef NR_arch_specific_syscall - #define NR_arch_specific_syscall 244 - #endif - #define NR_riscv_hwprobe (NR_arch_specific_syscall + 14) - #endif +#ifndef NR_riscv_hwprobe +#ifndef NR_arch_specific_syscall +#define NR_arch_specific_syscall 244 +#endif +#define NR_riscv_hwprobe (NR_arch_specific_syscall + 14) +#endif #endif void cpuinfo_riscv_linux_decode_vendor_uarch_from_hwprobe( - uint32_t processor, - enum cpuinfo_vendor vendor[restrict static 1], - enum cpuinfo_uarch uarch[restrict static 1]) { + uint32_t processor, + enum cpuinfo_vendor vendor[restrict static 1], + enum cpuinfo_uarch uarch[restrict static 1]) { struct riscv_hwprobe pairs[] = { - { .key = RISCV_HWPROBE_KEY_MVENDORID, }, - { .key = RISCV_HWPROBE_KEY_MARCHID, }, - { .key = RISCV_HWPROBE_KEY_MIMPID, }, + { + .key = RISCV_HWPROBE_KEY_MVENDORID, + }, + { + .key = RISCV_HWPROBE_KEY_MARCHID, + }, + { + .key = RISCV_HWPROBE_KEY_MIMPID, + }, }; const size_t pairs_count = sizeof(pairs) / sizeof(struct riscv_hwprobe); @@ -106,13 +113,9 @@ void cpuinfo_riscv_linux_decode_vendor_uarch_from_hwprobe( * * for more details. */ - int ret = syscall(NR_riscv_hwprobe, pairs, pairs_count, - cpu_set_size, (unsigned long*)cpu_set, - 0 /* flags */); + int ret = syscall(NR_riscv_hwprobe, pairs, pairs_count, cpu_set_size, (unsigned long*)cpu_set, 0 /* flags */); #else - int ret = __riscv_hwprobe(pairs, pairs_count, - cpu_set_size, (unsigned long*)cpu_set, - 0 /* flags */); + int ret = __riscv_hwprobe(pairs, pairs_count, cpu_set_size, (unsigned long*)cpu_set, 0 /* flags */); #endif if (ret < 0) { cpuinfo_log_warning("failed to get hwprobe information, err: %d", ret); @@ -142,8 +145,7 @@ void cpuinfo_riscv_linux_decode_vendor_uarch_from_hwprobe( break; } } - cpuinfo_riscv_decode_vendor_uarch(vendor_id, arch_id, imp_id, - vendor, uarch); + cpuinfo_riscv_decode_vendor_uarch(vendor_id, arch_id, imp_id, vendor, uarch); cleanup: CPU_FREE(cpu_set); diff --git a/src/riscv/linux/riscv-isa.c b/src/riscv/linux/riscv-isa.c index ace451b8..c133965f 100644 --- a/src/riscv/linux/riscv-isa.c +++ b/src/riscv/linux/riscv-isa.c @@ -8,16 +8,15 @@ * * This must be kept in sync with the upstream kernel header. */ -#define COMPAT_HWCAP_ISA_I (1 << ('I' - 'A')) -#define COMPAT_HWCAP_ISA_M (1 << ('M' - 'A')) -#define COMPAT_HWCAP_ISA_A (1 << ('A' - 'A')) -#define COMPAT_HWCAP_ISA_F (1 << ('F' - 'A')) -#define COMPAT_HWCAP_ISA_D (1 << ('D' - 'A')) -#define COMPAT_HWCAP_ISA_C (1 << ('C' - 'A')) -#define COMPAT_HWCAP_ISA_V (1 << ('V' - 'A')) +#define COMPAT_HWCAP_ISA_I (1 << ('I' - 'A')) +#define COMPAT_HWCAP_ISA_M (1 << ('M' - 'A')) +#define COMPAT_HWCAP_ISA_A (1 << ('A' - 'A')) +#define COMPAT_HWCAP_ISA_F (1 << ('F' - 'A')) +#define COMPAT_HWCAP_ISA_D (1 << ('D' - 'A')) +#define COMPAT_HWCAP_ISA_C (1 << ('C' - 'A')) +#define COMPAT_HWCAP_ISA_V (1 << ('V' - 'A')) -void cpuinfo_riscv_linux_decode_isa_from_hwcap( - struct cpuinfo_riscv_isa isa[restrict static 1]) { +void cpuinfo_riscv_linux_decode_isa_from_hwcap(struct cpuinfo_riscv_isa isa[restrict static 1]) { const unsigned long hwcap = getauxval(AT_HWCAP); if (hwcap & COMPAT_HWCAP_ISA_I) { diff --git a/src/riscv/uarch.c b/src/riscv/uarch.c index 6f4ff57d..83b03c30 100644 --- a/src/riscv/uarch.c +++ b/src/riscv/uarch.c @@ -10,13 +10,13 @@ void cpuinfo_riscv_decode_vendor_uarch( enum cpuinfo_vendor vendor[restrict static 1], enum cpuinfo_uarch uarch[restrict static 1]) { /* The vendor ID is sufficient to determine the cpuinfo_vendor. */ - switch(vendor_id) { + switch (vendor_id) { case cpuinfo_riscv_chipset_vendor_sifive: *vendor = cpuinfo_vendor_sifive; break; default: *vendor = cpuinfo_vendor_unknown; - cpuinfo_log_warning("unknown vendor ID: %"PRIu32, vendor_id); + cpuinfo_log_warning("unknown vendor ID: %" PRIu32, vendor_id); break; } /** diff --git a/src/x86/api.h b/src/x86/api.h index 213c2d88..1331ed04 100644 --- a/src/x86/api.h +++ b/src/x86/api.h @@ -6,7 +6,6 @@ #include #include - struct cpuid_regs { uint32_t eax; uint32_t ebx; @@ -90,9 +89,12 @@ CPUINFO_INTERNAL enum cpuinfo_uarch cpuinfo_x86_decode_uarch( const struct cpuinfo_x86_model_info* model_info); CPUINFO_INTERNAL struct cpuinfo_x86_isa cpuinfo_x86_detect_isa( - const struct cpuid_regs basic_info, const struct cpuid_regs extended_info, - uint32_t max_base_index, uint32_t max_extended_index, - enum cpuinfo_vendor vendor, enum cpuinfo_uarch uarch); + const struct cpuid_regs basic_info, + const struct cpuid_regs extended_info, + uint32_t max_base_index, + uint32_t max_extended_index, + enum cpuinfo_vendor vendor, + enum cpuinfo_uarch uarch); CPUINFO_INTERNAL void cpuinfo_x86_detect_topology( uint32_t max_base_index, @@ -101,7 +103,8 @@ CPUINFO_INTERNAL void cpuinfo_x86_detect_topology( struct cpuinfo_x86_topology* topology); CPUINFO_INTERNAL void cpuinfo_x86_detect_cache( - uint32_t max_base_index, uint32_t max_extended_index, + uint32_t max_base_index, + uint32_t max_extended_index, bool amd_topology_extensions, enum cpuinfo_vendor vendor, const struct cpuinfo_x86_model_info* model_info, @@ -122,7 +125,8 @@ CPUINFO_INTERNAL void cpuinfo_x86_detect_cache( uint32_t* log2_package_cores_max); CPUINFO_INTERNAL void cpuinfo_x86_decode_cache_descriptor( - uint8_t descriptor, enum cpuinfo_vendor vendor, + uint8_t descriptor, + enum cpuinfo_vendor vendor, const struct cpuinfo_x86_model_info* model_info, struct cpuinfo_x86_caches* cache, struct cpuinfo_tlb* itlb_4KB, @@ -145,13 +149,9 @@ CPUINFO_INTERNAL bool cpuinfo_x86_decode_deterministic_cache_parameters( struct cpuinfo_x86_caches* cache, uint32_t* package_cores_max); -CPUINFO_INTERNAL bool cpuinfo_x86_decode_cache_properties( - struct cpuid_regs regs, - struct cpuinfo_x86_caches* cache); +CPUINFO_INTERNAL bool cpuinfo_x86_decode_cache_properties(struct cpuid_regs regs, struct cpuinfo_x86_caches* cache); -CPUINFO_INTERNAL uint32_t cpuinfo_x86_normalize_brand_string( - const char raw_name[48], - char normalized_name[48]); +CPUINFO_INTERNAL uint32_t cpuinfo_x86_normalize_brand_string(const char raw_name[48], char normalized_name[48]); CPUINFO_INTERNAL uint32_t cpuinfo_x86_format_package_name( enum cpuinfo_vendor vendor, diff --git a/src/x86/cache/descriptor.c b/src/x86/cache/descriptor.c index 69d38cc3..8dc71ddc 100644 --- a/src/x86/cache/descriptor.c +++ b/src/x86/cache/descriptor.c @@ -3,9 +3,9 @@ #include #include - void cpuinfo_x86_decode_cache_descriptor( - uint8_t descriptor, enum cpuinfo_vendor vendor, + uint8_t descriptor, + enum cpuinfo_vendor vendor, const struct cpuinfo_x86_model_info* model_info, struct cpuinfo_x86_caches* cache, struct cpuinfo_tlb* itlb_4KB, @@ -21,13 +21,14 @@ void cpuinfo_x86_decode_cache_descriptor( struct cpuinfo_tlb* stlb2_4KB, struct cpuinfo_tlb* stlb2_2MB, struct cpuinfo_tlb* stlb2_1GB, - uint32_t* prefetch_size) -{ + uint32_t* prefetch_size) { /* * Descriptors are parsed according to: - * - Application Note 485: Intel Processor Indentification and CPUID Instruction, May 2012, Order Number 241618-039 - * - Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 2 (2A, 2B, 2C & 2D): Instruction Set - * Reference, A-Z, December 2016. Order Number: 325383-061US + * - Application Note 485: Intel Processor Indentification and CPUID + * Instruction, May 2012, Order Number 241618-039 + * - Intel 64 and IA-32 Architectures Software Developer’s Manual, + * Volume 2 (2A, 2B, 2C & 2D): Instruction Set Reference, A-Z, December + * 2016. Order Number: 325383-061US * - Cyrix CPU Detection Guide, Preliminary Revision 1.01 * - Geode(TM) GX1 Processor Series: Low Power Integrated x86 Solution */ @@ -35,11 +36,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x01: /* * Intel ISA Reference: - * "Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries" - * Application Note 485: - * "Instruction TLB: 4-KB Pages, 4-way set associative, 32 entries" + * "Instruction TLB: 4 KByte pages, 4-way set + * associative, 32 entries" Application Note 485: + * "Instruction TLB: 4-KB Pages, 4-way set + * associative, 32 entries" */ - *itlb_4KB = (struct cpuinfo_tlb) { + *itlb_4KB = (struct cpuinfo_tlb){ .entries = 32, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_4KB, @@ -48,11 +50,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x02: /* * Intel ISA Reference: - * "Instruction TLB: 4 MByte pages, fully associative, 2 entries" - * Application Note 485: - * "Instruction TLB: 4-MB Pages, fully associative, 2 entries" + * "Instruction TLB: 4 MByte pages, fully + * associative, 2 entries" Application Note 485: + * "Instruction TLB: 4-MB Pages, fully associative, + * 2 entries" */ - *itlb_4MB = (struct cpuinfo_tlb) { + *itlb_4MB = (struct cpuinfo_tlb){ .entries = 2, .associativity = 2, .pages = CPUINFO_PAGE_SIZE_4MB, @@ -61,11 +64,11 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x03: /* * Intel ISA Reference: - * "Data TLB: 4 KByte pages, 4-way set associative, 64 entries" - * Application Note 485: - * "Data TLB: 4-KB Pages, 4-way set associative, 64 entries" + * "Data TLB: 4 KByte pages, 4-way set associative, + * 64 entries" Application Note 485: "Data TLB: 4-KB + * Pages, 4-way set associative, 64 entries" */ - *dtlb_4KB = (struct cpuinfo_tlb) { + *dtlb_4KB = (struct cpuinfo_tlb){ .entries = 64, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_4KB, @@ -74,11 +77,11 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x04: /* * Intel ISA Reference: - * "Data TLB: 4 MByte pages, 4-way set associative, 8 entries" - * Application Note 485: - * "Data TLB: 4-MB Pages, 4-way set associative, 8 entries" + * "Data TLB: 4 MByte pages, 4-way set associative, + * 8 entries" Application Note 485: "Data TLB: 4-MB + * Pages, 4-way set associative, 8 entries" */ - *dtlb_4MB = (struct cpuinfo_tlb) { + *dtlb_4MB = (struct cpuinfo_tlb){ .entries = 8, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_4MB, @@ -87,11 +90,11 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x05: /* * Intel ISA Reference: - * "Data TLB1: 4 MByte pages, 4-way set associative, 32 entries" - * Application Note 485: - * "Data TLB: 4-MB Pages, 4-way set associative, 32 entries" + * "Data TLB1: 4 MByte pages, 4-way set associative, + * 32 entries" Application Note 485: "Data TLB: 4-MB + * Pages, 4-way set associative, 32 entries" */ - *dtlb_4MB = (struct cpuinfo_tlb) { + *dtlb_4MB = (struct cpuinfo_tlb){ .entries = 32, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_4MB, @@ -100,11 +103,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x06: /* * Intel ISA Reference: - * "1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size" - * Application Note 485: - * "1st-level instruction cache: 8-KB, 4-way set associative, 32-byte line size" + * "1st-level instruction cache: 8 KBytes, 4-way set + * associative, 32 byte line size" Application Note 485: + * "1st-level instruction cache: 8-KB, 4-way set + * associative, 32-byte line size" */ - cache->l1i = (struct cpuinfo_x86_cache) { + cache->l1i = (struct cpuinfo_x86_cache){ .size = 8 * 1024, .associativity = 4, .sets = 64, @@ -115,11 +119,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x08: /* * Intel ISA Reference: - * "1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size" - * Application Note 485: - * "1st-level instruction cache: 16-KB, 4-way set associative, 32-byte line size" + * "1st-level instruction cache: 16 KBytes, 4-way + * set associative, 32 byte line size" Application Note + * 485: "1st-level instruction cache: 16-KB, 4-way set + * associative, 32-byte line size" */ - cache->l1i = (struct cpuinfo_x86_cache) { + cache->l1i = (struct cpuinfo_x86_cache){ .size = 16 * 1024, .associativity = 4, .sets = 128, @@ -130,11 +135,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x09: /* * Intel ISA Reference: - * "1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size" - * Application Note 485: - * "1st-level Instruction Cache: 32-KB, 4-way set associative, 64-byte line size" + * "1st-level instruction cache: 32KBytes, 4-way set + * associative, 64 byte line size" Application Note 485: + * "1st-level Instruction Cache: 32-KB, 4-way set + * associative, 64-byte line size" */ - cache->l1i = (struct cpuinfo_x86_cache) { + cache->l1i = (struct cpuinfo_x86_cache){ .size = 32 * 1024, .associativity = 4, .sets = 128, @@ -145,11 +151,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x0A: /* * Intel ISA Reference: - * "1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size" - * Application Note 485: - * "1st-level data cache: 8-KB, 2-way set associative, 32-byte line size" + * "1st-level data cache: 8 KBytes, 2-way set + * associative, 32 byte line size" Application Note 485: + * "1st-level data cache: 8-KB, 2-way set associative, + * 32-byte line size" */ - cache->l1d = (struct cpuinfo_x86_cache) { + cache->l1d = (struct cpuinfo_x86_cache){ .size = 8 * 1024, .associativity = 2, .sets = 128, @@ -160,11 +167,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x0B: /* * Intel ISA Reference: - * "Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries" - * Application Note 485: - * "Instruction TLB: 4-MB pages, 4-way set associative, 4 entries" + * "Instruction TLB: 4 MByte pages, 4-way set + * associative, 4 entries" Application Note 485: + * "Instruction TLB: 4-MB pages, 4-way set + * associative, 4 entries" */ - *itlb_4MB = (struct cpuinfo_tlb) { + *itlb_4MB = (struct cpuinfo_tlb){ .entries = 4, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_4MB, @@ -173,11 +181,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x0C: /* * Intel ISA Reference: - * "1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size" - * Application Note 485: - * "1st-level data cache: 16-KB, 4-way set associative, 32-byte line size" + * "1st-level data cache: 16 KBytes, 4-way set + * associative, 32 byte line size" Application Note 485: + * "1st-level data cache: 16-KB, 4-way set associative, + * 32-byte line size" */ - cache->l1d = (struct cpuinfo_x86_cache) { + cache->l1d = (struct cpuinfo_x86_cache){ .size = 16 * 1024, .associativity = 4, .sets = 128, @@ -188,11 +197,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x0D: /* * Intel ISA Reference: - * "1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size" - * Application Note 485: - * "1st-level Data Cache: 16-KB, 4-way set associative, 64-byte line size" + * "1st-level data cache: 16 KBytes, 4-way set + * associative, 64 byte line size" Application Note 485: + * "1st-level Data Cache: 16-KB, 4-way set associative, + * 64-byte line size" */ - cache->l1d = (struct cpuinfo_x86_cache) { + cache->l1d = (struct cpuinfo_x86_cache){ .size = 16 * 1024, .associativity = 4, .sets = 64, @@ -203,11 +213,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x0E: /* * Intel ISA Reference: - * "1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size" - * Application Note 485: - * "1st-level Data Cache: 24-KB, 6-way set associative, 64-byte line size" + * "1st-level data cache: 24 KBytes, 6-way set + * associative, 64 byte line size" Application Note 485: + * "1st-level Data Cache: 24-KB, 6-way set associative, + * 64-byte line size" */ - cache->l1d = (struct cpuinfo_x86_cache) { + cache->l1d = (struct cpuinfo_x86_cache){ .size = 24 * 1024, .associativity = 6, .sets = 64, @@ -218,9 +229,10 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x1D: /* * Intel ISA Reference: - * "2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size" + * "2nd-level cache: 128 KBytes, 2-way set + * associative, 64 byte line size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 128 * 1024, .associativity = 2, .sets = 1024, @@ -231,11 +243,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x21: /* * Intel ISA Reference: - * "2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size" - * Application Note 485: - * "2nd-level cache: 256-KB, 8-way set associative, 64-byte line size" + * "2nd-level cache: 256 KBytes, 8-way set + * associative, 64 byte line size" Application Note 485: + * "2nd-level cache: 256-KB, 8-way set associative, + * 64-byte line size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 256 * 1024, .associativity = 8, .sets = 512, @@ -247,11 +260,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x22: /* * Intel ISA Reference: - * "3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector" - * Application Note 485: - * "3rd-level cache: 512-KB, 4-way set associative, sectored cache, 64-byte line size" + * "3rd-level cache: 512 KBytes, 4-way set + * associative, 64 byte line size, 2 lines per sector" + * Application Note 485: "3rd-level cache: 512-KB, 4-way + * set associative, sectored cache, 64-byte line size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 512 * 1024, .associativity = 4, .sets = 2048, @@ -263,11 +277,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x23: /* * Intel ISA Reference: - * "3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" - * Application Note 485: - * "3rd-level cache: 1-MB, 8-way set associative, sectored cache, 64-byte line size" + * "3rd-level cache: 1 MBytes, 8-way set + * associative, 64 byte line size, 2 lines per sector" + * Application Note 485: "3rd-level cache: 1-MB, 8-way + * set associative, sectored cache, 64-byte line size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 1024 * 1024, .associativity = 8, .sets = 2048, @@ -279,9 +294,10 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x24: /* * Intel ISA Reference: - * "2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size" + * "2nd-level cache: 1 MBytes, 16-way set + * associative, 64 byte line size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 1024 * 1024, .associativity = 16, .sets = 1024, @@ -293,11 +309,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x25: /* * Intel ISA Reference: - * "3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" - * Application Note 485: - * "3rd-level cache: 2-MB, 8-way set associative, sectored cache, 64-byte line size" + * "3rd-level cache: 2 MBytes, 8-way set + * associative, 64 byte line size, 2 lines per sector" + * Application Note 485: "3rd-level cache: 2-MB, 8-way + * set associative, sectored cache, 64-byte line size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 2 * 1024 * 1024, .associativity = 8, .sets = 4096, @@ -309,11 +326,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x29: /* * Intel ISA Reference: - * "3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" - * Application Note 485: - * "3rd-level cache: 4-MB, 8-way set associative, sectored cache, 64-byte line size" + * "3rd-level cache: 4 MBytes, 8-way set + * associative, 64 byte line size, 2 lines per sector" + * Application Note 485: "3rd-level cache: 4-MB, 8-way + * set associative, sectored cache, 64-byte line size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 4 * 1024 * 1024, .associativity = 8, .sets = 8192, @@ -325,11 +343,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x2C: /* * Intel ISA Reference: - * "1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size" - * Application Note 485: - * "1st-level data cache: 32-KB, 8-way set associative, 64-byte line size" + * "1st-level data cache: 32 KBytes, 8-way set + * associative, 64 byte line size" Application Note 485: + * "1st-level data cache: 32-KB, 8-way set associative, + * 64-byte line size" */ - cache->l1d = (struct cpuinfo_x86_cache) { + cache->l1d = (struct cpuinfo_x86_cache){ .size = 32 * 1024, .associativity = 8, .sets = 64, @@ -340,11 +359,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x30: /* * Intel ISA Reference: - * "1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size" - * Application Note 485: - * "1st-level instruction cache: 32-KB, 8-way set associative, 64-byte line size" + * "1st-level instruction cache: 32 KBytes, 8-way + * set associative, 64 byte line size" Application Note + * 485: "1st-level instruction cache: 32-KB, 8-way set + * associative, 64-byte line size" */ - cache->l1i = (struct cpuinfo_x86_cache) { + cache->l1i = (struct cpuinfo_x86_cache){ .size = 32 * 1024, .associativity = 8, .sets = 64, @@ -354,7 +374,7 @@ void cpuinfo_x86_decode_cache_descriptor( break; case 0x39: /* Where does this come from? */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 128 * 1024, .associativity = 4, .sets = 512, @@ -365,7 +385,7 @@ void cpuinfo_x86_decode_cache_descriptor( break; case 0x3A: /* Where does this come from? */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 192 * 1024, .associativity = 6, .sets = 512, @@ -376,7 +396,7 @@ void cpuinfo_x86_decode_cache_descriptor( break; case 0x3B: /* Where does this come from? */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 128 * 1024, .associativity = 2, .sets = 1024, @@ -387,7 +407,7 @@ void cpuinfo_x86_decode_cache_descriptor( break; case 0x3C: /* Where does this come from? */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 256 * 1024, .associativity = 4, .sets = 1024, @@ -398,7 +418,7 @@ void cpuinfo_x86_decode_cache_descriptor( break; case 0x3D: /* Where does this come from? */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 384 * 1024, .associativity = 6, .sets = 1024, @@ -409,7 +429,7 @@ void cpuinfo_x86_decode_cache_descriptor( break; case 0x3E: /* Where does this come from? */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 512 * 1024, .associativity = 4, .sets = 2048, @@ -421,19 +441,22 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x40: /* * Intel ISA Reference: - * "No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache" - * Application Note 485: - * "No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache" + * "No 2nd-level cache or, if processor contains a + * valid 2nd-level cache, no 3rd-level cache" + * Application Note 485: "No 2nd-level cache or, if + * processor contains a valid 2nd-level cache, no + * 3rd-level cache" */ break; case 0x41: /* * Intel ISA Reference: - * "2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size" - * Application Note 485: - * "2nd-level cache: 128-KB, 4-way set associative, 32-byte line size" + * "2nd-level cache: 128 KBytes, 4-way set + * associative, 32 byte line size" Application Note 485: + * "2nd-level cache: 128-KB, 4-way set associative, + * 32-byte line size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 128 * 1024, .associativity = 4, .sets = 1024, @@ -445,11 +468,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x42: /* * Intel ISA Reference: - * "2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size" - * Application Note 485: - * "2nd-level cache: 256-KB, 4-way set associative, 32-byte line size" + * "2nd-level cache: 256 KBytes, 4-way set + * associative, 32 byte line size" Application Note 485: + * "2nd-level cache: 256-KB, 4-way set associative, + * 32-byte line size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 256 * 1024, .associativity = 4, .sets = 2048, @@ -461,11 +485,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x43: /* * Intel ISA Reference: - * "2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size" - * Application Note 485: - * "2nd-level cache: 512-KB, 4-way set associative, 32-byte line size" + * "2nd-level cache: 512 KBytes, 4-way set + * associative, 32 byte line size" Application Note 485: + * "2nd-level cache: 512-KB, 4-way set associative, + * 32-byte line size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 512 * 1024, .associativity = 4, .sets = 4096, @@ -477,11 +502,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x44: /* * Intel ISA Reference: - * "2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size" - * Application Note 485: - * "2nd-level cache: 1-MB, 4-way set associative, 32-byte line size" + * "2nd-level cache: 1 MByte, 4-way set associative, + * 32 byte line size" Application Note 485: "2nd-level + * cache: 1-MB, 4-way set associative, 32-byte line + * size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 1024 * 1024, .associativity = 4, .sets = 8192, @@ -493,11 +519,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x45: /* * Intel ISA Reference: - * "2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size" - * Application Note 485: - * "2nd-level cache: 2-MB, 4-way set associative, 32-byte line size" + * "2nd-level cache: 2 MByte, 4-way set associative, + * 32 byte line size" Application Note 485: "2nd-level + * cache: 2-MB, 4-way set associative, 32-byte line + * size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 2 * 1024 * 1024, .associativity = 4, .sets = 16384, @@ -509,11 +536,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x46: /* * Intel ISA Reference: - * "3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 4-MB, 4-way set associative, 64-byte line size" + * "3rd-level cache: 4 MByte, 4-way set associative, + * 64 byte line size" Application Note 485: "3rd-level + * cache: 4-MB, 4-way set associative, 64-byte line + * size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 4 * 1024 * 1024, .associativity = 4, .sets = 16384, @@ -525,11 +553,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x47: /* * Intel ISA Reference: - * "3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 8-MB, 8-way set associative, 64-byte line size" + * "3rd-level cache: 8 MByte, 8-way set associative, + * 64 byte line size" Application Note 485: "3rd-level + * cache: 8-MB, 8-way set associative, 64-byte line + * size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 8 * 1024 * 1024, .associativity = 8, .sets = 16384, @@ -541,11 +570,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x48: /* * Intel ISA Reference: - * "2nd-level cache: 3MByte, 12-way set associative, 64 byte line size" - * Application Note 485: - * "2nd-level cache: 3-MB, 12-way set associative, 64-byte line size, unified on-die" + * "2nd-level cache: 3MByte, 12-way set associative, + * 64 byte line size" Application Note 485: "2nd-level + * cache: 3-MB, 12-way set associative, 64-byte line + * size, unified on-die" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 3 * 1024 * 1024, .associativity = 12, .sets = 4096, @@ -557,15 +587,18 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x49: /* * Intel ISA Reference: - * "3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, - * Family 0FH, Model 06H); 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 4-MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, - * Family 0Fh, Model 06h) - * 2nd-level cache: 4-MB, 16-way set associative, 64-byte line size" + * "3rd-level cache: 4MB, 16-way set associative, + * 64-byte line size (Intel Xeon processor MP, Family + * 0FH, Model 06H); 2nd-level cache: 4 MByte, 16-way set + * associative, 64 byte line size" Application Note 485: + * "3rd-level cache: 4-MB, 16-way set associative, + * 64-byte line size (Intel Xeon processor MP, Family + * 0Fh, Model 06h) 2nd-level cache: 4-MB, 16-way set + * associative, 64-byte line size" */ - if ((vendor == cpuinfo_vendor_intel) && (model_info->model == 0x06) && (model_info->family == 0x0F)) { - cache->l3 = (struct cpuinfo_x86_cache) { + if ((vendor == cpuinfo_vendor_intel) && (model_info->model == 0x06) && + (model_info->family == 0x0F)) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 4 * 1024 * 1024, .associativity = 16, .sets = 4096, @@ -574,7 +607,7 @@ void cpuinfo_x86_decode_cache_descriptor( .flags = CPUINFO_CACHE_INCLUSIVE, }; } else { - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 4 * 1024 * 1024, .associativity = 16, .sets = 4096, @@ -587,11 +620,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x4A: /* * Intel ISA Reference: - * "3rd-level cache: 6MByte, 12-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 6-MB, 12-way set associative, 64-byte line size" + * "3rd-level cache: 6MByte, 12-way set associative, + * 64 byte line size" Application Note 485: "3rd-level + * cache: 6-MB, 12-way set associative, 64-byte line + * size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 6 * 1024 * 1024, .associativity = 12, .sets = 8192, @@ -603,11 +637,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x4B: /* * Intel ISA Reference: - * "3rd-level cache: 8MByte, 16-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 8-MB, 16-way set associative, 64-byte line size" + * "3rd-level cache: 8MByte, 16-way set associative, + * 64 byte line size" Application Note 485: "3rd-level + * cache: 8-MB, 16-way set associative, 64-byte line + * size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 8 * 1024 * 1024, .associativity = 16, .sets = 8192, @@ -619,11 +654,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x4C: /* * Intel ISA Reference: - * "3rd-level cache: 12MByte, 12-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 12-MB, 12-way set associative, 64-byte line size" + * "3rd-level cache: 12MByte, 12-way set + * associative, 64 byte line size" Application Note 485: + * "3rd-level cache: 12-MB, 12-way set associative, + * 64-byte line size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 12 * 1024 * 1024, .associativity = 12, .sets = 16384, @@ -635,11 +671,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x4D: /* * Intel ISA Reference: - * "3rd-level cache: 16MByte, 16-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 16-MB, 16-way set associative, 64-byte line size" + * "3rd-level cache: 16MByte, 16-way set + * associative, 64 byte line size" Application Note 485: + * "3rd-level cache: 16-MB, 16-way set associative, + * 64-byte line size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 16 * 1024 * 1024, .associativity = 16, .sets = 16384, @@ -651,11 +688,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x4E: /* * Intel ISA Reference: - * "2nd-level cache: 6MByte, 24-way set associative, 64 byte line size" - * Application Note 485: - * "2nd-level cache: 6-MB, 24-way set associative, 64-byte line size" + * "2nd-level cache: 6MByte, 24-way set associative, + * 64 byte line size" Application Note 485: "2nd-level + * cache: 6-MB, 24-way set associative, 64-byte line + * size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 6 * 1024 * 1024, .associativity = 24, .sets = 4096, @@ -671,9 +709,11 @@ void cpuinfo_x86_decode_cache_descriptor( * Application Note 485: * "Instruction TLB: 4-KB pages, 32 entries" */ - *itlb_4KB = (struct cpuinfo_tlb) { + *itlb_4KB = (struct cpuinfo_tlb){ .entries = 32, - /* Assume full associativity from nearby entries: manual lacks detail */ + /* Assume full associativity from nearby + * entries: manual lacks detail + */ .associativity = 32, .pages = CPUINFO_PAGE_SIZE_4KB, }; @@ -681,11 +721,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x50: /* * Intel ISA Reference: - * "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries" - * Application Note 485: - * "Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 64 entries" + * "Instruction TLB: 4 KByte and 2-MByte or 4-MByte + * pages, 64 entries" Application Note 485: "Instruction + * TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 64 + * entries" */ - *itlb_4KB = *itlb_2MB = *itlb_4MB = (struct cpuinfo_tlb) { + *itlb_4KB = *itlb_2MB = *itlb_4MB = (struct cpuinfo_tlb){ .entries = 64, .associativity = 64, .pages = CPUINFO_PAGE_SIZE_4KB | CPUINFO_PAGE_SIZE_2MB | CPUINFO_PAGE_SIZE_4MB, @@ -694,11 +735,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x51: /* * Intel ISA Reference: - * "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries" - * Application Note 485: - * "Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 128 entries" + * "Instruction TLB: 4 KByte and 2-MByte or 4-MByte + * pages, 128 entries" Application Note 485: + * "Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully + * associative, 128 entries" */ - *itlb_4KB = *itlb_2MB = *itlb_4MB = (struct cpuinfo_tlb) { + *itlb_4KB = *itlb_2MB = *itlb_4MB = (struct cpuinfo_tlb){ .entries = 128, .associativity = 128, .pages = CPUINFO_PAGE_SIZE_4KB | CPUINFO_PAGE_SIZE_2MB | CPUINFO_PAGE_SIZE_4MB, @@ -707,11 +749,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x52: /* * Intel ISA Reference: - * "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries" - * Application Note 485: - * "Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully associative, 256 entries" + * "Instruction TLB: 4 KByte and 2-MByte or 4-MByte + * pages, 256 entries" Application Note 485: + * "Instruction TLB: 4-KB, 2-MB or 4-MB pages, fully + * associative, 256 entries" */ - *itlb_4KB = *itlb_2MB = *itlb_4MB = (struct cpuinfo_tlb) { + *itlb_4KB = *itlb_2MB = *itlb_4MB = (struct cpuinfo_tlb){ .entries = 256, .associativity = 256, .pages = CPUINFO_PAGE_SIZE_4KB | CPUINFO_PAGE_SIZE_2MB | CPUINFO_PAGE_SIZE_4MB, @@ -720,11 +763,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x55: /* * Intel ISA Reference: - * "Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries" - * Application Note 485: - * "Instruction TLB: 2-MB or 4-MB pages, fully associative, 7 entries" + * "Instruction TLB: 2-MByte or 4-MByte pages, fully + * associative, 7 entries" Application Note 485: + * "Instruction TLB: 2-MB or 4-MB pages, fully + * associative, 7 entries" */ - *itlb_2MB = *itlb_4MB = (struct cpuinfo_tlb) { + *itlb_2MB = *itlb_4MB = (struct cpuinfo_tlb){ .entries = 7, .associativity = 7, .pages = CPUINFO_PAGE_SIZE_2MB | CPUINFO_PAGE_SIZE_4MB, @@ -733,11 +777,11 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x56: /* * Intel ISA Reference: - * "Data TLB0: 4 MByte pages, 4-way set associative, 16 entries" - * Application Note 485: - * "L1 Data TLB: 4-MB pages, 4-way set associative, 16 entries" + * "Data TLB0: 4 MByte pages, 4-way set associative, + * 16 entries" Application Note 485: "L1 Data TLB: 4-MB + * pages, 4-way set associative, 16 entries" */ - *dtlb0_4MB = (struct cpuinfo_tlb) { + *dtlb0_4MB = (struct cpuinfo_tlb){ .entries = 16, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_4MB, @@ -746,11 +790,11 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x57: /* * Intel ISA Reference: - * "Data TLB0: 4 KByte pages, 4-way associative, 16 entries" - * Application Note 485: - * "L1 Data TLB: 4-KB pages, 4-way set associative, 16 entries" + * "Data TLB0: 4 KByte pages, 4-way associative, 16 + * entries" Application Note 485: "L1 Data TLB: 4-KB + * pages, 4-way set associative, 16 entries" */ - *dtlb0_4KB = (struct cpuinfo_tlb) { + *dtlb0_4KB = (struct cpuinfo_tlb){ .entries = 16, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_4KB, @@ -759,11 +803,11 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x59: /* * Intel ISA Reference: - * "Data TLB0: 4 KByte pages, fully associative, 16 entries" - * Application Note 485: - * "Data TLB0: 4-KB pages, fully associative, 16 entries" + * "Data TLB0: 4 KByte pages, fully associative, 16 + * entries" Application Note 485: "Data TLB0: 4-KB + * pages, fully associative, 16 entries" */ - *dtlb0_4KB = (struct cpuinfo_tlb) { + *dtlb0_4KB = (struct cpuinfo_tlb){ .entries = 16, .associativity = 16, .pages = CPUINFO_PAGE_SIZE_4KB, @@ -772,11 +816,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x5A: /* * Intel ISA Reference: - * "Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries" - * Application Note 485: - * "Data TLB0: 2-MB or 4-MB pages, 4-way associative, 32 entries" + * "Data TLB0: 2 MByte or 4 MByte pages, 4-way set + * associative, 32 entries" Application Note 485: "Data + * TLB0: 2-MB or 4-MB pages, 4-way associative, 32 + * entries" */ - *dtlb0_2MB = *dtlb0_4MB = (struct cpuinfo_tlb) { + *dtlb0_2MB = *dtlb0_4MB = (struct cpuinfo_tlb){ .entries = 32, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_2MB | CPUINFO_PAGE_SIZE_4MB, @@ -787,9 +832,10 @@ void cpuinfo_x86_decode_cache_descriptor( * Intel ISA Reference: * "Data TLB: 4 KByte and 4 MByte pages, 64 entries" * Application Note 485: - * "Data TLB: 4-KB or 4-MB pages, fully associative, 64 entries" + * "Data TLB: 4-KB or 4-MB pages, fully associative, + * 64 entries" */ - *dtlb_4KB = *dtlb_4MB = (struct cpuinfo_tlb) { + *dtlb_4KB = *dtlb_4MB = (struct cpuinfo_tlb){ .entries = 64, .associativity = 64, .pages = CPUINFO_PAGE_SIZE_4KB | CPUINFO_PAGE_SIZE_4MB, @@ -798,11 +844,11 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x5C: /* * Intel ISA Reference: - * "Data TLB: 4 KByte and 4 MByte pages, 128 entries" - * Application Note 485: - * "Data TLB: 4-KB or 4-MB pages, fully associative, 128 entries" + * "Data TLB: 4 KByte and 4 MByte pages, 128 + * entries" Application Note 485: "Data TLB: 4-KB or + * 4-MB pages, fully associative, 128 entries" */ - *dtlb_4KB = *dtlb_4MB = (struct cpuinfo_tlb) { + *dtlb_4KB = *dtlb_4MB = (struct cpuinfo_tlb){ .entries = 128, .associativity = 128, .pages = CPUINFO_PAGE_SIZE_4KB | CPUINFO_PAGE_SIZE_4MB, @@ -811,11 +857,11 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x5D: /* * Intel ISA Reference: - * "Data TLB: 4 KByte and 4 MByte pages, 256 entries" - * Application Note 485: - * "Data TLB: 4-KB or 4-MB pages, fully associative, 256 entries" + * "Data TLB: 4 KByte and 4 MByte pages, 256 + * entries" Application Note 485: "Data TLB: 4-KB or + * 4-MB pages, fully associative, 256 entries" */ - *dtlb_4KB = *dtlb_4MB = (struct cpuinfo_tlb) { + *dtlb_4KB = *dtlb_4MB = (struct cpuinfo_tlb){ .entries = 256, .associativity = 256, .pages = CPUINFO_PAGE_SIZE_4KB | CPUINFO_PAGE_SIZE_4MB, @@ -824,9 +870,10 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x60: /* * Application Note 485: - * "1st-level data cache: 16-KB, 8-way set associative, sectored cache, 64-byte line size" + * "1st-level data cache: 16-KB, 8-way set + * associative, sectored cache, 64-byte line size" */ - cache->l1d = (struct cpuinfo_x86_cache) { + cache->l1d = (struct cpuinfo_x86_cache){ .size = 16 * 1024, .associativity = 8, .sets = 32, @@ -837,9 +884,10 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x61: /* * Intel ISA Reference: - * "Instruction TLB: 4 KByte pages, fully associative, 48 entries" + * "Instruction TLB: 4 KByte pages, fully + * associative, 48 entries" */ - *itlb_4KB = (struct cpuinfo_tlb) { + *itlb_4KB = (struct cpuinfo_tlb){ .entries = 48, .associativity = 48, .pages = CPUINFO_PAGE_SIZE_4KB, @@ -848,15 +896,16 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x63: /* * Intel ISA Reference: - * "Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and - * a separate array with 1 GByte pages, 4-way set associative, 4 entries" + * "Data TLB: 2 MByte or 4 MByte pages, 4-way set + * associative, 32 entries and a separate array with 1 + * GByte pages, 4-way set associative, 4 entries" */ - *dtlb_2MB = *dtlb_4MB = (struct cpuinfo_tlb) { + *dtlb_2MB = *dtlb_4MB = (struct cpuinfo_tlb){ .entries = 32, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_2MB | CPUINFO_PAGE_SIZE_4MB, }; - *dtlb_1GB = (struct cpuinfo_tlb) { + *dtlb_1GB = (struct cpuinfo_tlb){ .entries = 4, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_1GB, @@ -865,10 +914,11 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x64: /* * Intel ISA Reference: - * "Data TLB: 4 KByte pages, 4-way set associative, 512 entries" + * "Data TLB: 4 KByte pages, 4-way set associative, + * 512 entries" * */ - *dtlb_4KB = (struct cpuinfo_tlb) { + *dtlb_4KB = (struct cpuinfo_tlb){ .entries = 512, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_4KB, @@ -877,9 +927,10 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x66: /* * Application Note 485: - * "1st-level data cache: 8-KB, 4-way set associative, sectored cache, 64-byte line size" + * "1st-level data cache: 8-KB, 4-way set + * associative, sectored cache, 64-byte line size" */ - cache->l1d = (struct cpuinfo_x86_cache) { + cache->l1d = (struct cpuinfo_x86_cache){ .size = 8 * 1024, .associativity = 4, .sets = 32, @@ -890,9 +941,10 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x67: /* * Application Note 485: - * "1st-level data cache: 16-KB, 4-way set associative, sectored cache, 64-byte line size" + * "1st-level data cache: 16-KB, 4-way set + * associative, sectored cache, 64-byte line size" */ - cache->l1d = (struct cpuinfo_x86_cache) { + cache->l1d = (struct cpuinfo_x86_cache){ .size = 16 * 1024, .associativity = 4, .sets = 64, @@ -903,9 +955,10 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x68: /* * Application Note 485: - * "1st-level data cache: 32-KB, 4 way set associative, sectored cache, 64-byte line size" + * "1st-level data cache: 32-KB, 4 way set + * associative, sectored cache, 64-byte line size" */ - cache->l1d = (struct cpuinfo_x86_cache) { + cache->l1d = (struct cpuinfo_x86_cache){ .size = 32 * 1024, .associativity = 4, .sets = 128, @@ -916,11 +969,14 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x6A: /* * Intel ISA Reference: - * "uTLB: 4 KByte pages, 8-way set associative, 64 entries" + * "uTLB: 4 KByte pages, 8-way set associative, 64 + * entries" */ - /* uTLB is, an fact, a normal 1-level DTLB on Silvermont & Knoghts Landing */ - *dtlb_4KB = (struct cpuinfo_tlb) { + /* uTLB is, an fact, a normal 1-level DTLB on Silvermont + * & Knoghts Landing + */ + *dtlb_4KB = (struct cpuinfo_tlb){ .entries = 64, .associativity = 8, .pages = CPUINFO_PAGE_SIZE_4KB, @@ -929,9 +985,10 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x6B: /* * Intel ISA Reference: - * "DTLB: 4 KByte pages, 8-way set associative, 256 entries" + * "DTLB: 4 KByte pages, 8-way set associative, 256 + * entries" */ - *dtlb_4KB = (struct cpuinfo_tlb) { + *dtlb_4KB = (struct cpuinfo_tlb){ .entries = 256, .associativity = 8, .pages = CPUINFO_PAGE_SIZE_4KB, @@ -940,9 +997,10 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x6C: /* * Intel ISA Reference: - * "DTLB: 2M/4M pages, 8-way set associative, 128 entries" + * "DTLB: 2M/4M pages, 8-way set associative, 128 + * entries" */ - *dtlb_2MB = *dtlb_4MB = (struct cpuinfo_tlb) { + *dtlb_2MB = *dtlb_4MB = (struct cpuinfo_tlb){ .entries = 128, .associativity = 8, .pages = CPUINFO_PAGE_SIZE_2MB | CPUINFO_PAGE_SIZE_4MB, @@ -951,9 +1009,10 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x6D: /* * Intel ISA Reference: - * "DTLB: 1 GByte pages, fully associative, 16 entries" + * "DTLB: 1 GByte pages, fully associative, 16 + * entries" */ - *dtlb_1GB = (struct cpuinfo_tlb) { + *dtlb_1GB = (struct cpuinfo_tlb){ .entries = 16, .associativity = 16, .pages = CPUINFO_PAGE_SIZE_1GB, @@ -965,14 +1024,15 @@ void cpuinfo_x86_decode_cache_descriptor( * "Trace cache: 12 K-uop, 8-way set associative" * Application Note 485: * "Trace cache: 12K-uops, 8-way set associative" - * Cyrix CPU Detection Guide and Geode GX1 Processor Series: - * "TLB, 32 entries, 4-way set associative, 4K-Byte Pages" + * Cyrix CPU Detection Guide and Geode GX1 Processor + * Series: "TLB, 32 entries, 4-way set associative, + * 4K-Byte Pages" */ switch (vendor) { #if CPUINFO_ARCH_X86 case cpuinfo_vendor_cyrix: case cpuinfo_vendor_nsc: - *dtlb_4KB = *itlb_4KB = (struct cpuinfo_tlb) { + *dtlb_4KB = *itlb_4KB = (struct cpuinfo_tlb){ .entries = 32, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_4KB, @@ -980,7 +1040,7 @@ void cpuinfo_x86_decode_cache_descriptor( break; #endif /* CPUINFO_ARCH_X86 */ default: - cache->trace = (struct cpuinfo_trace_cache) { + cache->trace = (struct cpuinfo_trace_cache){ .uops = 12 * 1024, .associativity = 8, }; @@ -993,7 +1053,7 @@ void cpuinfo_x86_decode_cache_descriptor( * Application Note 485: * "Trace cache: 16K-uops, 8-way set associative" */ - cache->trace = (struct cpuinfo_trace_cache) { + cache->trace = (struct cpuinfo_trace_cache){ .uops = 16 * 1024, .associativity = 8, }; @@ -1005,14 +1065,14 @@ void cpuinfo_x86_decode_cache_descriptor( * Application Note 485: * "Trace cache: 32K-uops, 8-way set associative" */ - cache->trace = (struct cpuinfo_trace_cache) { + cache->trace = (struct cpuinfo_trace_cache){ .uops = 32 * 1024, .associativity = 8, }; break; case 0x73: /* Where does this come from? */ - cache->trace = (struct cpuinfo_trace_cache) { + cache->trace = (struct cpuinfo_trace_cache){ .uops = 64 * 1024, .associativity = 8, }; @@ -1020,11 +1080,11 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x76: /* * Intel ISA Reference: - * "Instruction TLB: 2M/4M pages, fully associative, 8 entries" - * Application Note 485: - * "Instruction TLB: 2M/4M pages, fully associative, 8 entries" + * "Instruction TLB: 2M/4M pages, fully associative, + * 8 entries" Application Note 485: "Instruction TLB: + * 2M/4M pages, fully associative, 8 entries" */ - *itlb_2MB = *itlb_4MB = (struct cpuinfo_tlb) { + *itlb_2MB = *itlb_4MB = (struct cpuinfo_tlb){ .entries = 8, .associativity = 8, .pages = CPUINFO_PAGE_SIZE_2MB | CPUINFO_PAGE_SIZE_4MB, @@ -1033,11 +1093,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x78: /* * Intel ISA Reference: - * "2nd-level cache: 1 MByte, 4-way set associative, 64byte line size" - * Application Note 485: - * "2nd-level cache: 1-MB, 4-way set associative, 64-byte line size" + * "2nd-level cache: 1 MByte, 4-way set associative, + * 64byte line size" Application Note 485: "2nd-level + * cache: 1-MB, 4-way set associative, 64-byte line + * size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 1024 * 1024, .associativity = 4, .sets = 4096, @@ -1049,11 +1110,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x79: /* * Intel ISA Reference: - * "2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" - * Application Note 485: - * "2nd-level cache: 128-KB, 8-way set associative, sectored cache, 64-byte line size" + * "2nd-level cache: 128 KByte, 8-way set + * associative, 64 byte line size, 2 lines per sector" + * Application Note 485: "2nd-level cache: 128-KB, 8-way + * set associative, sectored cache, 64-byte line size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 128 * 1024, .associativity = 8, .sets = 256, @@ -1065,11 +1127,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x7A: /* * Intel ISA Reference: - * "2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" - * Application Note 485: - * "2nd-level cache: 256-KB, 8-way set associative, sectored cache, 64-byte line size" + * "2nd-level cache: 256 KByte, 8-way set + * associative, 64 byte line size, 2 lines per sector" + * Application Note 485: "2nd-level cache: 256-KB, 8-way + * set associative, sectored cache, 64-byte line size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 256 * 1024, .associativity = 8, .sets = 512, @@ -1081,11 +1144,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x7B: /* * Intel ISA Reference: - * "2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" - * Application Note 485: - * "2nd-level cache: 512-KB, 8-way set associative, sectored cache, 64-byte line size" + * "2nd-level cache: 512 KByte, 8-way set + * associative, 64 byte line size, 2 lines per sector" + * Application Note 485: "2nd-level cache: 512-KB, 8-way + * set associative, sectored cache, 64-byte line size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 512 * 1024, .associativity = 8, .sets = 1024, @@ -1097,11 +1161,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x7C: /* * Intel ISA Reference: - * "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector" - * Application Note 485: - * "2nd-level cache: 1-MB, 8-way set associative, sectored cache, 64-byte line size" + * "2nd-level cache: 1 MByte, 8-way set associative, + * 64 byte line size, 2 lines per sector" Application + * Note 485: "2nd-level cache: 1-MB, 8-way set + * associative, sectored cache, 64-byte line size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 1024 * 1024, .associativity = 8, .sets = 2048, @@ -1113,11 +1178,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x7D: /* * Intel ISA Reference: - * "2nd-level cache: 2 MByte, 8-way set associative, 64byte line size" - * Application Note 485: - * "2nd-level cache: 2-MB, 8-way set associative, 64-byte line size" + * "2nd-level cache: 2 MByte, 8-way set associative, + * 64byte line size" Application Note 485: "2nd-level + * cache: 2-MB, 8-way set associative, 64-byte line + * size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 2 * 1024 * 1024, .associativity = 8, .sets = 4096, @@ -1129,11 +1195,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x7F: /* * Intel ISA Reference: - * "2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size" - * Application Note 485: - * "2nd-level cache: 512-KB, 2-way set associative, 64-byte line size" + * "2nd-level cache: 512 KByte, 2-way set + * associative, 64-byte line size" Application Note 485: + * "2nd-level cache: 512-KB, 2-way set associative, + * 64-byte line size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 512 * 1024, .associativity = 2, .sets = 4096, @@ -1145,17 +1212,18 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x80: /* * Intel ISA Reference: - * "2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size" - * Application Note 485: - * "2nd-level cache: 512-KB, 8-way set associative, 64-byte line size" - * Cyrix CPU Detection Guide and Geode GX1 Processor Series: - * "Level 1 Cache, 16K, 4-way set associative, 16 Bytes/Line" + * "2nd-level cache: 512 KByte, 8-way set + * associative, 64-byte line size" Application Note 485: + * "2nd-level cache: 512-KB, 8-way set associative, + * 64-byte line size" Cyrix CPU Detection Guide and + * Geode GX1 Processor Series: "Level 1 Cache, 16K, + * 4-way set associative, 16 Bytes/Line" */ switch (vendor) { #if CPUINFO_ARCH_X86 && !defined(__ANDROID__) case cpuinfo_vendor_cyrix: case cpuinfo_vendor_nsc: - cache->l1i = cache->l1d = (struct cpuinfo_x86_cache) { + cache->l1i = cache->l1d = (struct cpuinfo_x86_cache){ .size = 16 * 1024, .associativity = 4, .sets = 256, @@ -1166,7 +1234,7 @@ void cpuinfo_x86_decode_cache_descriptor( break; #endif /* CPUINFO_ARCH_X86 */ default: - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 512 * 1024, .associativity = 8, .sets = 1024, @@ -1179,11 +1247,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x82: /* * Intel ISA Reference: - * "2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size" - * Application Note 485: - * "2nd-level cache: 256-KB, 8-way set associative, 32-byte line size" + * "2nd-level cache: 256 KByte, 8-way set + * associative, 32 byte line size" Application Note 485: + * "2nd-level cache: 256-KB, 8-way set associative, + * 32-byte line size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 256 * 1024, .associativity = 4, .sets = 2048, @@ -1195,11 +1264,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x83: /* * Intel ISA Reference: - * "2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size" - * Application Note 485: - * "2nd-level cache: 512-KB, 8-way set associative, 32-byte line size" + * "2nd-level cache: 512 KByte, 8-way set + * associative, 32 byte line size" Application Note 485: + * "2nd-level cache: 512-KB, 8-way set associative, + * 32-byte line size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 512 * 1024, .associativity = 8, .sets = 2048, @@ -1211,11 +1281,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x84: /* * Intel ISA Reference: - * "2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size" - * Application Note 485: - * "2nd-level cache: 1-MB, 8-way set associative, 32-byte line size" + * "2nd-level cache: 1 MByte, 8-way set associative, + * 32 byte line size" Application Note 485: "2nd-level + * cache: 1-MB, 8-way set associative, 32-byte line + * size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 1024 * 1024, .associativity = 8, .sets = 4096, @@ -1227,11 +1298,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x85: /* * Intel ISA Reference: - * "2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size" - * Application Note 485: - * "2nd-level cache: 2-MB, 8-way set associative, 32-byte line size" + * "2nd-level cache: 2 MByte, 8-way set associative, + * 32 byte line size" Application Note 485: "2nd-level + * cache: 2-MB, 8-way set associative, 32-byte line + * size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 2 * 1024 * 1024, .associativity = 8, .sets = 8192, @@ -1243,11 +1315,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x86: /* * Intel ISA Reference: - * "2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size" - * Application Note 485: - * "2nd-level cache: 512-KB, 4-way set associative, 64-byte line size" + * "2nd-level cache: 512 KByte, 4-way set + * associative, 64 byte line size" Application Note 485: + * "2nd-level cache: 512-KB, 4-way set associative, + * 64-byte line size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 512 * 1024, .associativity = 4, .sets = 2048, @@ -1259,11 +1332,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0x87: /* * Intel ISA Reference: - * "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size" - * Application Note 485: - * "2nd-level cache: 1-MB, 8-way set associative, 64-byte line size" + * "2nd-level cache: 1 MByte, 8-way set associative, + * 64 byte line size" Application Note 485: "2nd-level + * cache: 1-MB, 8-way set associative, 64-byte line + * size" */ - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = 1024 * 1024, .associativity = 8, .sets = 2048, @@ -1277,7 +1351,7 @@ void cpuinfo_x86_decode_cache_descriptor( * Intel ISA Reference: * "DTLB: 4k pages, fully associative, 32 entries" */ - *dtlb_4KB = (struct cpuinfo_tlb) { + *dtlb_4KB = (struct cpuinfo_tlb){ .entries = 32, .associativity = 32, .pages = CPUINFO_PAGE_SIZE_4KB, @@ -1286,11 +1360,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xB0: /* * Intel ISA Reference: - * "Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries" - * Application Note 485: - * "Instruction TLB: 4-KB Pages, 4-way set associative, 128 entries" + * "Instruction TLB: 4 KByte pages, 4-way set + * associative, 128 entries" Application Note 485: + * "Instruction TLB: 4-KB Pages, 4-way set associative, + * 128 entries" */ - *itlb_4KB = (struct cpuinfo_tlb) { + *itlb_4KB = (struct cpuinfo_tlb){ .entries = 128, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_4KB, @@ -1299,16 +1374,17 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xB1: /* * Intel ISA Reference: - * "Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries" - * Application Note 485: - * "Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries" + * "Instruction TLB: 2M pages, 4-way, 8 entries or + * 4M pages, 4-way, 4 entries" Application Note 485: + * "Instruction TLB: 2-MB pages, 4-way, 8 entries or 4M + * pages, 4-way, 4 entries" */ - *itlb_2MB = (struct cpuinfo_tlb) { + *itlb_2MB = (struct cpuinfo_tlb){ .entries = 8, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_2MB | CPUINFO_PAGE_SIZE_4MB, }; - *itlb_4MB = (struct cpuinfo_tlb) { + *itlb_4MB = (struct cpuinfo_tlb){ .entries = 4, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_2MB | CPUINFO_PAGE_SIZE_4MB, @@ -1317,11 +1393,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xB2: /* * Intel ISA Reference: - * "Instruction TLB: 4KByte pages, 4-way set associative, 64 entries" - * Application Note 485: - * "Instruction TLB: 4-KB pages, 4-way set associative, 64 entries" + * "Instruction TLB: 4KByte pages, 4-way set + * associative, 64 entries" Application Note 485: + * "Instruction TLB: 4-KB pages, 4-way set + * associative, 64 entries" */ - *itlb_4KB = (struct cpuinfo_tlb) { + *itlb_4KB = (struct cpuinfo_tlb){ .entries = 64, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_4KB, @@ -1330,11 +1407,11 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xB3: /* * Intel ISA Reference: - * "Data TLB: 4 KByte pages, 4-way set associative, 128 entries" - * Application Note 485: - * "Data TLB: 4-KB Pages, 4-way set associative, 128 entries" + * "Data TLB: 4 KByte pages, 4-way set associative, + * 128 entries" Application Note 485: "Data TLB: 4-KB + * Pages, 4-way set associative, 128 entries" */ - *dtlb_4KB = (struct cpuinfo_tlb) { + *dtlb_4KB = (struct cpuinfo_tlb){ .entries = 128, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_4KB, @@ -1343,11 +1420,11 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xB4: /* * Intel ISA Reference: - * "Data TLB1: 4 KByte pages, 4-way associative, 256 entries" - * Application Note 485: - * "Data TLB: 4-KB Pages, 4-way set associative, 256 entries" + * "Data TLB1: 4 KByte pages, 4-way associative, 256 + * entries" Application Note 485: "Data TLB: 4-KB Pages, + * 4-way set associative, 256 entries" */ - *dtlb_4KB = (struct cpuinfo_tlb) { + *dtlb_4KB = (struct cpuinfo_tlb){ .entries = 256, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_4KB, @@ -1356,9 +1433,10 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xB5: /* * Intel ISA Reference: - * "Instruction TLB: 4KByte pages, 8-way set associative, 64 entries" + * "Instruction TLB: 4KByte pages, 8-way set + * associative, 64 entries" */ - *itlb_4KB = (struct cpuinfo_tlb) { + *itlb_4KB = (struct cpuinfo_tlb){ .entries = 64, .associativity = 8, .pages = CPUINFO_PAGE_SIZE_4KB, @@ -1367,9 +1445,10 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xB6: /* * Intel ISA Reference: - * "Instruction TLB: 4KByte pages, 8-way set associative, 128 entries" + * "Instruction TLB: 4KByte pages, 8-way set + * associative, 128 entries" */ - *itlb_4KB = (struct cpuinfo_tlb) { + *itlb_4KB = (struct cpuinfo_tlb){ .entries = 128, .associativity = 8, .pages = CPUINFO_PAGE_SIZE_4KB, @@ -1378,11 +1457,11 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xBA: /* * Intel ISA Reference: - * "Data TLB1: 4 KByte pages, 4-way associative, 64 entries" - * Application Note 485: - * "Data TLB: 4-KB Pages, 4-way set associative, 64 entries" + * "Data TLB1: 4 KByte pages, 4-way associative, 64 + * entries" Application Note 485: "Data TLB: 4-KB Pages, + * 4-way set associative, 64 entries" */ - *itlb_4KB = (struct cpuinfo_tlb) { + *itlb_4KB = (struct cpuinfo_tlb){ .entries = 64, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_4KB, @@ -1391,11 +1470,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xC0: /* * Intel ISA Reference: - * "Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries" - * Application Note 485: - * "Data TLB: 4-KB or 4-MB Pages, 4-way set associative, 8 entries" + * "Data TLB: 4 KByte and 4 MByte pages, 4-way + * associative, 8 entries" Application Note 485: "Data + * TLB: 4-KB or 4-MB Pages, 4-way set associative, 8 + * entries" */ - *itlb_4KB = *itlb_4MB = (struct cpuinfo_tlb) { + *itlb_4KB = *itlb_4MB = (struct cpuinfo_tlb){ .entries = 8, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_4KB | CPUINFO_PAGE_SIZE_4MB, @@ -1404,9 +1484,10 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xC1: /* * Intel ISA Reference: - * "Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries" + * "Shared 2nd-Level TLB: 4 KByte/2MByte pages, + * 8-way associative, 1024 entries" */ - *stlb2_4KB = *stlb2_2MB = (struct cpuinfo_tlb) { + *stlb2_4KB = *stlb2_2MB = (struct cpuinfo_tlb){ .entries = 1024, .associativity = 8, .pages = CPUINFO_PAGE_SIZE_4KB | CPUINFO_PAGE_SIZE_2MB, @@ -1415,9 +1496,10 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xC2: /* * Intel ISA Reference: - * "DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries" + * "DTLB: 4 KByte/2 MByte pages, 4-way associative, + * 16 entries" */ - *dtlb_4KB = *dtlb_2MB = (struct cpuinfo_tlb) { + *dtlb_4KB = *dtlb_2MB = (struct cpuinfo_tlb){ .entries = 16, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_4KB | CPUINFO_PAGE_SIZE_2MB, @@ -1426,15 +1508,16 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xC3: /* * Intel ISA Reference: - * "Shared 2nd-Level TLB: 4 KByte/2 MByte pages, 6-way associative, 1536 entries. - * Also 1GBbyte pages, 4-way, 16 entries." + * "Shared 2nd-Level TLB: 4 KByte/2 MByte pages, + * 6-way associative, 1536 entries. Also 1GBbyte pages, + * 4-way, 16 entries." */ - *stlb2_4KB = *stlb2_2MB = (struct cpuinfo_tlb) { + *stlb2_4KB = *stlb2_2MB = (struct cpuinfo_tlb){ .entries = 1536, .associativity = 6, .pages = CPUINFO_PAGE_SIZE_4KB | CPUINFO_PAGE_SIZE_2MB, }; - *stlb2_1GB = (struct cpuinfo_tlb) { + *stlb2_1GB = (struct cpuinfo_tlb){ .entries = 16, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_1GB, @@ -1443,9 +1526,10 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xC4: /* * Intel ISA Reference: - * "DTLB: 2M/4M Byte pages, 4-way associative, 32 entries" + * "DTLB: 2M/4M Byte pages, 4-way associative, 32 + * entries" */ - *dtlb_2MB = *dtlb_4MB = (struct cpuinfo_tlb) { + *dtlb_2MB = *dtlb_4MB = (struct cpuinfo_tlb){ .entries = 32, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_2MB | CPUINFO_PAGE_SIZE_4MB, @@ -1454,11 +1538,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xCA: /* * Intel ISA Reference: - * "Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries" - * Application Note 485: - * "Shared 2nd-level TLB: 4 KB pages, 4-way set associative, 512 entries" + * "Shared 2nd-Level TLB: 4 KByte pages, 4-way + * associative, 512 entries" Application Note 485: + * "Shared 2nd-level TLB: 4 KB pages, 4-way set + * associative, 512 entries" */ - *stlb2_4KB = (struct cpuinfo_tlb) { + *stlb2_4KB = (struct cpuinfo_tlb){ .entries = 512, .associativity = 4, .pages = CPUINFO_PAGE_SIZE_4KB, @@ -1467,11 +1552,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xD0: /* * Intel ISA Reference: - * "3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 512-kB, 4-way set associative, 64-byte line size" + * "3rd-level cache: 512 KByte, 4-way set + * associative, 64 byte line size" Application Note 485: + * "3rd-level cache: 512-kB, 4-way set associative, + * 64-byte line size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 512 * 1024, .associativity = 4, .sets = 2048, @@ -1483,11 +1569,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xD1: /* * Intel ISA Reference: - * "3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 1-MB, 4-way set associative, 64-byte line size" + * "3rd-level cache: 1 MByte, 4-way set associative, + * 64 byte line size" Application Note 485: "3rd-level + * cache: 1-MB, 4-way set associative, 64-byte line + * size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 1024 * 1024, .associativity = 4, .sets = 4096, @@ -1499,11 +1586,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xD2: /* * Intel ISA Reference: - * "3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 2-MB, 4-way set associative, 64-byte line size" + * "3rd-level cache: 2 MByte, 4-way set associative, + * 64 byte line size" Application Note 485: "3rd-level + * cache: 2-MB, 4-way set associative, 64-byte line + * size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 2 * 1024 * 2014, .associativity = 4, .sets = 8192, @@ -1515,11 +1603,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xD6: /* * Intel ISA Reference: - * "3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 1-MB, 8-way set associative, 64-byte line size" + * "3rd-level cache: 1 MByte, 8-way set associative, + * 64 byte line size" Application Note 485: "3rd-level + * cache: 1-MB, 8-way set associative, 64-byte line + * size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 1024 * 1024, .associativity = 8, .sets = 2048, @@ -1531,11 +1620,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xD7: /* * Intel ISA Reference: - * "3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 2-MB, 8-way set associative, 64-byte line size" + * "3rd-level cache: 2 MByte, 8-way set associative, + * 64 byte line size" Application Note 485: "3rd-level + * cache: 2-MB, 8-way set associative, 64-byte line + * size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 2 * 1024 * 1024, .associativity = 8, .sets = 4096, @@ -1547,11 +1637,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xD8: /* * Intel ISA Reference: - * "3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 4-MB, 8-way set associative, 64-byte line size" + * "3rd-level cache: 4 MByte, 8-way set associative, + * 64 byte line size" Application Note 485: "3rd-level + * cache: 4-MB, 8-way set associative, 64-byte line + * size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 4 * 1024 * 1024, .associativity = 8, .sets = 8192, @@ -1563,11 +1654,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xDC: /* * Intel ISA Reference: - * "3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 1.5-MB, 12-way set associative, 64-byte line size" + * "3rd-level cache: 1.5 MByte, 12-way set + * associative, 64 byte line size" Application Note 485: + * "3rd-level cache: 1.5-MB, 12-way set associative, + * 64-byte line size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 3 * 512 * 1024, .associativity = 12, .sets = 2048, @@ -1579,11 +1671,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xDD: /* * Intel ISA Reference: - * "3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 3-MB, 12-way set associative, 64-byte line size" + * "3rd-level cache: 3 MByte, 12-way set + * associative, 64 byte line size" Application Note 485: + * "3rd-level cache: 3-MB, 12-way set associative, + * 64-byte line size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 3 * 1024 * 1024, .associativity = 12, .sets = 4096, @@ -1595,11 +1688,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xDE: /* * Intel ISA Reference: - * "3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 6-MB, 12-way set associative, 64-byte line size" + * "3rd-level cache: 6 MByte, 12-way set + * associative, 64 byte line size" Application Note 485: + * "3rd-level cache: 6-MB, 12-way set associative, + * 64-byte line size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 6 * 1024 * 1024, .associativity = 12, .sets = 8192, @@ -1611,11 +1705,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xE2: /* * Intel ISA Reference: - * "3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 2-MB, 16-way set associative, 64-byte line size" + * "3rd-level cache: 2 MByte, 16-way set + * associative, 64 byte line size" Application Note 485: + * "3rd-level cache: 2-MB, 16-way set associative, + * 64-byte line size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 2 * 1024 * 1024, .associativity = 16, .sets = 2048, @@ -1627,11 +1722,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xE3: /* * Intel ISA Reference: - * "3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 4-MB, 16-way set associative, 64-byte line size" + * "3rd-level cache: 4 MByte, 16-way set + * associative, 64 byte line size" Application Note 485: + * "3rd-level cache: 4-MB, 16-way set associative, + * 64-byte line size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 4 * 1024 * 1024, .associativity = 16, .sets = 4096, @@ -1643,11 +1739,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xE4: /* * Intel ISA Reference: - * "3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 8-MB, 16-way set associative, 64-byte line size" + * "3rd-level cache: 8 MByte, 16-way set + * associative, 64 byte line size" Application Note 485: + * "3rd-level cache: 8-MB, 16-way set associative, + * 64-byte line size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 8 * 1024 * 1024, .associativity = 16, .sets = 8192, @@ -1659,11 +1756,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xEA: /* * Intel ISA Reference: - * "3rd-level cache: 12MByte, 24-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 12-MB, 24-way set associative, 64-byte line size" + * "3rd-level cache: 12MByte, 24-way set + * associative, 64 byte line size" Application Note 485: + * "3rd-level cache: 12-MB, 24-way set associative, + * 64-byte line size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 12 * 1024 * 1024, .associativity = 24, .sets = 8192, @@ -1675,11 +1773,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xEB: /* * Intel ISA Reference: - * "3rd-level cache: 18MByte, 24-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 18-MB, 24-way set associative, 64-byte line size" + * "3rd-level cache: 18MByte, 24-way set + * associative, 64 byte line size" Application Note 485: + * "3rd-level cache: 18-MB, 24-way set associative, + * 64-byte line size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 18 * 1024 * 1024, .associativity = 24, .sets = 12288, @@ -1691,11 +1790,12 @@ void cpuinfo_x86_decode_cache_descriptor( case 0xEC: /* * Intel ISA Reference: - * "3rd-level cache: 24MByte, 24-way set associative, 64 byte line size" - * Application Note 485: - * "3rd-level cache: 24-MB, 24-way set associative, 64-byte line size" + * "3rd-level cache: 24MByte, 24-way set + * associative, 64 byte line size" Application Note 485: + * "3rd-level cache: 24-MB, 24-way set associative, + * 64-byte line size" */ - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = 24 * 1024 * 1024, .associativity = 24, .sets = 16384, diff --git a/src/x86/cache/deterministic.c b/src/x86/cache/deterministic.c index befd5029..f40ee713 100644 --- a/src/x86/cache/deterministic.c +++ b/src/x86/cache/deterministic.c @@ -1,10 +1,9 @@ #include #include -#include -#include #include - +#include +#include enum cache_type { cache_type_none = 0, @@ -16,8 +15,7 @@ enum cache_type { bool cpuinfo_x86_decode_deterministic_cache_parameters( struct cpuid_regs regs, struct cpuinfo_x86_caches* cache, - uint32_t* package_cores_max) -{ + uint32_t* package_cores_max) { const uint32_t type = regs.eax & UINT32_C(0x1F); if (type == cache_type_none) { return false; @@ -46,112 +44,106 @@ bool cpuinfo_x86_decode_deterministic_cache_parameters( case 1: switch (type) { case cache_type_unified: - cache->l1d = cache->l1i = (struct cpuinfo_x86_cache) { + cache->l1d = cache->l1i = (struct cpuinfo_x86_cache){ .size = associativity * partitions * line_size * sets, .associativity = associativity, .sets = sets, .partitions = partitions, .line_size = line_size, .flags = flags | CPUINFO_CACHE_UNIFIED, - .apic_bits = apic_bits - }; + .apic_bits = apic_bits}; break; case cache_type_data: - cache->l1d = (struct cpuinfo_x86_cache) { + cache->l1d = (struct cpuinfo_x86_cache){ .size = associativity * partitions * line_size * sets, .associativity = associativity, .sets = sets, .partitions = partitions, .line_size = line_size, .flags = flags, - .apic_bits = apic_bits - }; + .apic_bits = apic_bits}; break; case cache_type_instruction: - cache->l1i = (struct cpuinfo_x86_cache) { + cache->l1i = (struct cpuinfo_x86_cache){ .size = associativity * partitions * line_size * sets, .associativity = associativity, .sets = sets, .partitions = partitions, .line_size = line_size, .flags = flags, - .apic_bits = apic_bits - }; + .apic_bits = apic_bits}; break; } break; case 2: switch (type) { case cache_type_instruction: - cpuinfo_log_warning("unexpected L2 instruction cache reported in leaf 0x00000004 is ignored"); + cpuinfo_log_warning( + "unexpected L2 instruction cache reported in leaf 0x00000004 is ignored"); break; case cache_type_unified: flags |= CPUINFO_CACHE_UNIFIED; case cache_type_data: - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = associativity * partitions * line_size * sets, .associativity = associativity, .sets = sets, .partitions = partitions, .line_size = line_size, .flags = flags, - .apic_bits = apic_bits - }; + .apic_bits = apic_bits}; break; } break; case 3: switch (type) { case cache_type_instruction: - cpuinfo_log_warning("unexpected L3 instruction cache reported in leaf 0x00000004 is ignored"); + cpuinfo_log_warning( + "unexpected L3 instruction cache reported in leaf 0x00000004 is ignored"); break; case cache_type_unified: flags |= CPUINFO_CACHE_UNIFIED; case cache_type_data: - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = associativity * partitions * line_size * sets, .associativity = associativity, .sets = sets, .partitions = partitions, .line_size = line_size, .flags = flags, - .apic_bits = apic_bits - }; + .apic_bits = apic_bits}; break; } break; case 4: switch (type) { case cache_type_instruction: - cpuinfo_log_warning("unexpected L4 instruction cache reported in leaf 0x00000004 is ignored"); + cpuinfo_log_warning( + "unexpected L4 instruction cache reported in leaf 0x00000004 is ignored"); break; case cache_type_unified: flags |= CPUINFO_CACHE_UNIFIED; case cache_type_data: - cache->l4 = (struct cpuinfo_x86_cache) { + cache->l4 = (struct cpuinfo_x86_cache){ .size = associativity * partitions * line_size * sets, .associativity = associativity, .sets = sets, .partitions = partitions, .line_size = line_size, .flags = flags, - .apic_bits = apic_bits - }; + .apic_bits = apic_bits}; break; } break; default: - cpuinfo_log_warning("unexpected L%"PRIu32" cache reported in leaf 0x00000004 is ignored", level); + cpuinfo_log_warning( + "unexpected L%" PRIu32 " cache reported in leaf 0x00000004 is ignored", level); break; } return true; } - -bool cpuinfo_x86_decode_cache_properties( - struct cpuid_regs regs, - struct cpuinfo_x86_caches* cache) -{ +bool cpuinfo_x86_decode_cache_properties(struct cpuid_regs regs, struct cpuinfo_x86_caches* cache) { const uint32_t type = regs.eax & UINT32_C(0x1F); if (type == cache_type_none) { return false; @@ -175,82 +167,80 @@ bool cpuinfo_x86_decode_cache_properties( case 1: switch (type) { case cache_type_unified: - cache->l1d = cache->l1i = (struct cpuinfo_x86_cache) { + cache->l1d = cache->l1i = (struct cpuinfo_x86_cache){ .size = associativity * partitions * line_size * sets, .associativity = associativity, .sets = sets, .partitions = partitions, .line_size = line_size, .flags = flags | CPUINFO_CACHE_UNIFIED, - .apic_bits = apic_bits - }; + .apic_bits = apic_bits}; break; case cache_type_data: - cache->l1d = (struct cpuinfo_x86_cache) { + cache->l1d = (struct cpuinfo_x86_cache){ .size = associativity * partitions * line_size * sets, .associativity = associativity, .sets = sets, .partitions = partitions, .line_size = line_size, .flags = flags, - .apic_bits = apic_bits - }; + .apic_bits = apic_bits}; break; case cache_type_instruction: - cache->l1i = (struct cpuinfo_x86_cache) { + cache->l1i = (struct cpuinfo_x86_cache){ .size = associativity * partitions * line_size * sets, .associativity = associativity, .sets = sets, .partitions = partitions, .line_size = line_size, .flags = flags, - .apic_bits = apic_bits - }; + .apic_bits = apic_bits}; break; } break; case 2: switch (type) { case cache_type_instruction: - cpuinfo_log_warning("unexpected L2 instruction cache reported in leaf 0x8000001D is ignored"); + cpuinfo_log_warning( + "unexpected L2 instruction cache reported in leaf 0x8000001D is ignored"); break; case cache_type_unified: flags |= CPUINFO_CACHE_UNIFIED; case cache_type_data: - cache->l2 = (struct cpuinfo_x86_cache) { + cache->l2 = (struct cpuinfo_x86_cache){ .size = associativity * partitions * line_size * sets, .associativity = associativity, .sets = sets, .partitions = partitions, .line_size = line_size, .flags = flags, - .apic_bits = apic_bits - }; + .apic_bits = apic_bits}; break; } break; case 3: switch (type) { case cache_type_instruction: - cpuinfo_log_warning("unexpected L3 instruction cache reported in leaf 0x8000001D is ignored"); + cpuinfo_log_warning( + "unexpected L3 instruction cache reported in leaf 0x8000001D is ignored"); break; case cache_type_unified: flags |= CPUINFO_CACHE_UNIFIED; case cache_type_data: - cache->l3 = (struct cpuinfo_x86_cache) { + cache->l3 = (struct cpuinfo_x86_cache){ .size = associativity * partitions * line_size * sets, .associativity = associativity, .sets = sets, .partitions = partitions, .line_size = line_size, .flags = flags, - .apic_bits = apic_bits - }; + .apic_bits = apic_bits}; break; } break; default: - cpuinfo_log_warning("unexpected L%"PRIu32" cache reported in leaf 0x8000001D is ignored", level); + cpuinfo_log_warning( + "unexpected L%" PRIu32 " cache reported in leaf 0x8000001D is ignored", level); break; } return true; diff --git a/src/x86/cache/init.c b/src/x86/cache/init.c index dd1f1ea3..34af90e7 100644 --- a/src/x86/cache/init.c +++ b/src/x86/cache/init.c @@ -1,11 +1,10 @@ #include #include -#include #include -#include +#include #include - +#include union cpuinfo_x86_cache_descriptors { struct cpuid_regs regs; @@ -20,7 +19,8 @@ enum cache_type { }; void cpuinfo_x86_detect_cache( - uint32_t max_base_index, uint32_t max_extended_index, + uint32_t max_base_index, + uint32_t max_extended_index, bool amd_topology_extensions, enum cpuinfo_vendor vendor, const struct cpuinfo_x86_model_info* model_info, @@ -38,24 +38,34 @@ void cpuinfo_x86_detect_cache( struct cpuinfo_tlb* stlb2_4KB, struct cpuinfo_tlb* stlb2_2MB, struct cpuinfo_tlb* stlb2_1GB, - uint32_t* log2_package_cores_max) -{ + uint32_t* log2_package_cores_max) { if (max_base_index >= 2) { union cpuinfo_x86_cache_descriptors descriptors; descriptors.regs = cpuid(2); - uint32_t iterations = (uint8_t) descriptors.as_bytes[0]; + uint32_t iterations = (uint8_t)descriptors.as_bytes[0]; if (iterations != 0) { -iterate_descriptors: + iterate_descriptors: for (uint32_t i = 1 /* note: not 0 */; i < 16; i++) { const uint8_t descriptor = descriptors.as_bytes[i]; if (descriptor != 0) { cpuinfo_x86_decode_cache_descriptor( - descriptor, vendor, model_info, + descriptor, + vendor, + model_info, cache, - itlb_4KB, itlb_2MB, itlb_4MB, - dtlb0_4KB, dtlb0_2MB, dtlb0_4MB, - dtlb_4KB, dtlb_2MB, dtlb_4MB, dtlb_1GB, - stlb2_4KB, stlb2_2MB, stlb2_1GB, + itlb_4KB, + itlb_2MB, + itlb_4MB, + dtlb0_4KB, + dtlb0_2MB, + dtlb0_4MB, + dtlb_4KB, + dtlb_2MB, + dtlb_4MB, + dtlb_1GB, + stlb2_4KB, + stlb2_2MB, + stlb2_1GB, &cache->prefetch_size); } } @@ -71,8 +81,7 @@ void cpuinfo_x86_detect_cache( uint32_t package_cores_max = 0; do { leaf4 = cpuidex(4, input_ecx++); - } while (cpuinfo_x86_decode_deterministic_cache_parameters( - leaf4, cache, &package_cores_max)); + } while (cpuinfo_x86_decode_deterministic_cache_parameters(leaf4, cache, &package_cores_max)); if (package_cores_max != 0) { *log2_package_cores_max = bit_length(package_cores_max); } diff --git a/src/x86/cpuid.h b/src/x86/cpuid.h index 9e9e0131..0d7cf5cc 100644 --- a/src/x86/cpuid.h +++ b/src/x86/cpuid.h @@ -2,78 +2,76 @@ #include #if defined(__GNUC__) - #include +#include #elif defined(_MSC_VER) - #include +#include #endif #if CPUINFO_MOCK - #include +#include #endif #include - #if defined(__GNUC__) || defined(_MSC_VER) - static inline struct cpuid_regs cpuid(uint32_t eax) { - #if CPUINFO_MOCK - uint32_t regs_array[4]; - cpuinfo_mock_get_cpuid(eax, regs_array); - return (struct cpuid_regs) { - .eax = regs_array[0], - .ebx = regs_array[1], - .ecx = regs_array[2], - .edx = regs_array[3], - }; - #else - struct cpuid_regs regs; - #if defined(__GNUC__) - __cpuid(eax, regs.eax, regs.ebx, regs.ecx, regs.edx); - #else - int regs_array[4]; - __cpuid(regs_array, (int) eax); - regs.eax = regs_array[0]; - regs.ebx = regs_array[1]; - regs.ecx = regs_array[2]; - regs.edx = regs_array[3]; - #endif - return regs; - #endif - } +static inline struct cpuid_regs cpuid(uint32_t eax) { +#if CPUINFO_MOCK + uint32_t regs_array[4]; + cpuinfo_mock_get_cpuid(eax, regs_array); + return (struct cpuid_regs){ + .eax = regs_array[0], + .ebx = regs_array[1], + .ecx = regs_array[2], + .edx = regs_array[3], + }; +#else + struct cpuid_regs regs; +#if defined(__GNUC__) + __cpuid(eax, regs.eax, regs.ebx, regs.ecx, regs.edx); +#else + int regs_array[4]; + __cpuid(regs_array, (int)eax); + regs.eax = regs_array[0]; + regs.ebx = regs_array[1]; + regs.ecx = regs_array[2]; + regs.edx = regs_array[3]; +#endif + return regs; +#endif +} - static inline struct cpuid_regs cpuidex(uint32_t eax, uint32_t ecx) { - #if CPUINFO_MOCK - uint32_t regs_array[4]; - cpuinfo_mock_get_cpuidex(eax, ecx, regs_array); - return (struct cpuid_regs) { - .eax = regs_array[0], - .ebx = regs_array[1], - .ecx = regs_array[2], - .edx = regs_array[3], - }; - #else - struct cpuid_regs regs; - #if defined(__GNUC__) - __cpuid_count(eax, ecx, regs.eax, regs.ebx, regs.ecx, regs.edx); - #else - int regs_array[4]; - __cpuidex(regs_array, (int) eax, (int) ecx); - regs.eax = regs_array[0]; - regs.ebx = regs_array[1]; - regs.ecx = regs_array[2]; - regs.edx = regs_array[3]; - #endif - return regs; - #endif - } +static inline struct cpuid_regs cpuidex(uint32_t eax, uint32_t ecx) { +#if CPUINFO_MOCK + uint32_t regs_array[4]; + cpuinfo_mock_get_cpuidex(eax, ecx, regs_array); + return (struct cpuid_regs){ + .eax = regs_array[0], + .ebx = regs_array[1], + .ecx = regs_array[2], + .edx = regs_array[3], + }; +#else + struct cpuid_regs regs; +#if defined(__GNUC__) + __cpuid_count(eax, ecx, regs.eax, regs.ebx, regs.ecx, regs.edx); +#else + int regs_array[4]; + __cpuidex(regs_array, (int)eax, (int)ecx); + regs.eax = regs_array[0]; + regs.ebx = regs_array[1]; + regs.ecx = regs_array[2]; + regs.edx = regs_array[3]; +#endif + return regs; +#endif +} #endif static inline uint64_t xgetbv(uint32_t ext_ctrl_reg) { - #ifdef _MSC_VER - return (uint64_t)_xgetbv((unsigned int)ext_ctrl_reg); - #else - uint32_t lo, hi; - __asm__(".byte 0x0F, 0x01, 0xD0" : "=a" (lo), "=d" (hi) : "c" (ext_ctrl_reg)); - return ((uint64_t) hi << 32) | (uint64_t) lo; - #endif +#ifdef _MSC_VER + return (uint64_t)_xgetbv((unsigned int)ext_ctrl_reg); +#else + uint32_t lo, hi; + __asm__(".byte 0x0F, 0x01, 0xD0" : "=a"(lo), "=d"(hi) : "c"(ext_ctrl_reg)); + return ((uint64_t)hi << 32) | (uint64_t)lo; +#endif } - diff --git a/src/x86/info.c b/src/x86/info.c index ceb6b845..bd761cdb 100644 --- a/src/x86/info.c +++ b/src/x86/info.c @@ -3,17 +3,16 @@ #include #include - struct cpuinfo_x86_model_info cpuinfo_x86_decode_model_info(uint32_t eax) { struct cpuinfo_x86_model_info model_info; - model_info.stepping = eax & 0xF; - model_info.base_model = (eax >> 4) & 0xF; - model_info.base_family = (eax >> 8) & 0xF; - model_info.processor_type = (eax >> 12) & 0x3; - model_info.extended_model = (eax >> 16) & 0xF; + model_info.stepping = eax & 0xF; + model_info.base_model = (eax >> 4) & 0xF; + model_info.base_family = (eax >> 8) & 0xF; + model_info.processor_type = (eax >> 12) & 0x3; + model_info.extended_model = (eax >> 16) & 0xF; model_info.extended_family = (eax >> 20) & 0xFF; model_info.family = model_info.base_family + model_info.extended_family; - model_info.model = model_info.base_model + (model_info.extended_model << 4); + model_info.model = model_info.base_model + (model_info.extended_model << 4); return model_info; } diff --git a/src/x86/init.c b/src/x86/init.c index 244359cd..adc5d361 100644 --- a/src/x86/init.c +++ b/src/x86/init.c @@ -2,14 +2,13 @@ #include #include -#include -#include -#include -#include #include +#include +#include +#include +#include - -struct cpuinfo_x86_isa cpuinfo_isa = { 0 }; +struct cpuinfo_x86_isa cpuinfo_isa = {0}; CPUINFO_INTERNAL uint32_t cpuinfo_x86_clflush_size = 0; void cpuinfo_x86_init_processor(struct cpuinfo_x86_processor* processor) { @@ -19,30 +18,34 @@ void cpuinfo_x86_init_processor(struct cpuinfo_x86_processor* processor) { cpuinfo_x86_decode_vendor(leaf0.ebx, leaf0.ecx, leaf0.edx); const struct cpuid_regs leaf0x80000000 = cpuid(UINT32_C(0x80000000)); - const uint32_t max_extended_index = - leaf0x80000000.eax >= UINT32_C(0x80000000) ? leaf0x80000000.eax : 0; + const uint32_t max_extended_index = leaf0x80000000.eax >= UINT32_C(0x80000000) ? leaf0x80000000.eax : 0; - const struct cpuid_regs leaf0x80000001 = max_extended_index >= UINT32_C(0x80000001) ? - cpuid(UINT32_C(0x80000001)) : (struct cpuid_regs) { 0, 0, 0, 0 }; + const struct cpuid_regs leaf0x80000001 = max_extended_index >= UINT32_C(0x80000001) + ? cpuid(UINT32_C(0x80000001)) + : (struct cpuid_regs){0, 0, 0, 0}; if (max_base_index >= 1) { const struct cpuid_regs leaf1 = cpuid(1); processor->cpuid = leaf1.eax; const struct cpuinfo_x86_model_info model_info = cpuinfo_x86_decode_model_info(leaf1.eax); - const enum cpuinfo_uarch uarch = processor->uarch = - cpuinfo_x86_decode_uarch(vendor, &model_info); + const enum cpuinfo_uarch uarch = processor->uarch = cpuinfo_x86_decode_uarch(vendor, &model_info); cpuinfo_x86_clflush_size = ((leaf1.ebx >> 8) & UINT32_C(0x000000FF)) * 8; /* * Topology extensions support: - * - AMD: ecx[bit 22] in extended info (reserved bit on Intel CPUs). + * - AMD: ecx[bit 22] in extended info (reserved bit on Intel + * CPUs). */ const bool amd_topology_extensions = !!(leaf0x80000001.ecx & UINT32_C(0x00400000)); cpuinfo_x86_detect_cache( - max_base_index, max_extended_index, amd_topology_extensions, vendor, &model_info, + max_base_index, + max_extended_index, + amd_topology_extensions, + vendor, + &model_info, &processor->cache, &processor->tlb.itlb_4KB, &processor->tlb.itlb_2MB, @@ -61,8 +64,8 @@ void cpuinfo_x86_init_processor(struct cpuinfo_x86_processor* processor) { cpuinfo_x86_detect_topology(max_base_index, max_extended_index, leaf1, &processor->topology); - cpuinfo_isa = cpuinfo_x86_detect_isa(leaf1, leaf0x80000001, - max_base_index, max_extended_index, vendor, uarch); + cpuinfo_isa = cpuinfo_x86_detect_isa( + leaf1, leaf0x80000001, max_base_index, max_extended_index, vendor, uarch); } if (max_extended_index >= UINT32_C(0x80000004)) { struct cpuid_regs brand_string[3]; diff --git a/src/x86/isa.c b/src/x86/isa.c index 3f36cee1..a28f10f4 100644 --- a/src/x86/isa.c +++ b/src/x86/isa.c @@ -1,77 +1,82 @@ #include -#include #include +#include -#include #include - +#include #if CPUINFO_ARCH_X86 - #ifdef _MSC_VER - #pragma pack(push, 2) - #endif - struct fxsave_region { - uint16_t fpu_control_word; - uint16_t fpu_status_word; - uint16_t fpu_tag_word; - uint16_t fpu_opcode; - uint32_t fpu_instruction_pointer_offset; - uint32_t fpu_instruction_pointer_selector; - uint32_t fpu_operand_pointer_offset; - uint32_t fpu_operand_pointer_selector; - uint32_t mxcsr_state; - uint32_t mxcsr_mask; - uint64_t fpu_registers[8 * 2]; - uint64_t xmm_registers[8 * 2]; - uint64_t padding[28]; - } - #ifndef _MSC_VER - __attribute__((__aligned__(16), __packed__)) - #endif - ; /* end of fxsave_region structure */ - #ifdef _MSC_VER - #pragma pack(pop, 2) - #endif +#ifdef _MSC_VER +#pragma pack(push, 2) +#endif +struct fxsave_region { + uint16_t fpu_control_word; + uint16_t fpu_status_word; + uint16_t fpu_tag_word; + uint16_t fpu_opcode; + uint32_t fpu_instruction_pointer_offset; + uint32_t fpu_instruction_pointer_selector; + uint32_t fpu_operand_pointer_offset; + uint32_t fpu_operand_pointer_selector; + uint32_t mxcsr_state; + uint32_t mxcsr_mask; + uint64_t fpu_registers[8 * 2]; + uint64_t xmm_registers[8 * 2]; + uint64_t padding[28]; +} +#ifndef _MSC_VER +__attribute__((__aligned__(16), __packed__)) +#endif +; /* end of fxsave_region structure */ +#ifdef _MSC_VER +#pragma pack(pop, 2) +#endif #endif - struct cpuinfo_x86_isa cpuinfo_x86_detect_isa( - const struct cpuid_regs basic_info, const struct cpuid_regs extended_info, - uint32_t max_base_index, uint32_t max_extended_index, - enum cpuinfo_vendor vendor, enum cpuinfo_uarch uarch) -{ - struct cpuinfo_x86_isa isa = { 0 }; + const struct cpuid_regs basic_info, + const struct cpuid_regs extended_info, + uint32_t max_base_index, + uint32_t max_extended_index, + enum cpuinfo_vendor vendor, + enum cpuinfo_uarch uarch) { + struct cpuinfo_x86_isa isa = {0}; const struct cpuid_regs structured_feature_info0 = - (max_base_index >= 7) ? cpuidex(7, 0) : (struct cpuid_regs) { 0, 0, 0, 0}; + (max_base_index >= 7) ? cpuidex(7, 0) : (struct cpuid_regs){0, 0, 0, 0}; const struct cpuid_regs structured_feature_info1 = - (max_base_index >= 7) ? cpuidex(7, 1) : (struct cpuid_regs) { 0, 0, 0, 0}; + (max_base_index >= 7) ? cpuidex(7, 1) : (struct cpuid_regs){0, 0, 0, 0}; const uint32_t processor_capacity_info_index = UINT32_C(0x80000008); - const struct cpuid_regs processor_capacity_info = - (max_extended_index >= processor_capacity_info_index) ? - cpuid(processor_capacity_info_index) : (struct cpuid_regs) { 0, 0, 0, 0 }; + const struct cpuid_regs processor_capacity_info = (max_extended_index >= processor_capacity_info_index) + ? cpuid(processor_capacity_info_index) + : (struct cpuid_regs){0, 0, 0, 0}; bool avx_regs = false, avx512_regs = false, mpx_regs = false; /* - * OSXSAVE: Operating system enabled XSAVE instructions for application use: - * - Intel, AMD: ecx[bit 26] in basic info = XSAVE/XRSTOR instructions supported by a chip. - * - Intel, AMD: ecx[bit 27] in basic info = XSAVE/XRSTOR instructions enabled by OS. + * OSXSAVE: Operating system enabled XSAVE instructions for application + * use: + * - Intel, AMD: ecx[bit 26] in basic info = XSAVE/XRSTOR instructions + * supported by a chip. + * - Intel, AMD: ecx[bit 27] in basic info = XSAVE/XRSTOR instructions + * enabled by OS. */ const uint32_t osxsave_mask = UINT32_C(0x0C000000); if ((basic_info.ecx & osxsave_mask) == osxsave_mask) { uint64_t xcr0_valid_bits = 0; if (max_base_index >= 0xD) { const struct cpuid_regs regs = cpuidex(0xD, 0); - xcr0_valid_bits = ((uint64_t) regs.edx << 32) | regs.eax; + xcr0_valid_bits = ((uint64_t)regs.edx << 32) | regs.eax; } const uint64_t xfeature_enabled_mask = xgetbv(0); /* * AVX registers: - * - Intel, AMD: XFEATURE_ENABLED_MASK[bit 1] for low 128 bits of ymm registers - * - Intel, AMD: XFEATURE_ENABLED_MASK[bit 2] for high 128 bits of ymm registers + * - Intel, AMD: XFEATURE_ENABLED_MASK[bit 1] for low 128 bits + * of ymm registers + * - Intel, AMD: XFEATURE_ENABLED_MASK[bit 2] for high 128 bits + * of ymm registers */ const uint64_t avx_regs_mask = UINT64_C(0x0000000000000006); if ((xcr0_valid_bits & avx_regs_mask) == avx_regs_mask) { @@ -80,11 +85,16 @@ struct cpuinfo_x86_isa cpuinfo_x86_detect_isa( /* * AVX512 registers: - * - Intel, AMD: XFEATURE_ENABLED_MASK[bit 1] for low 128 bits of zmm registers - * - Intel, AMD: XFEATURE_ENABLED_MASK[bit 2] for bits 128-255 of zmm registers - * - Intel: XFEATURE_ENABLED_MASK[bit 5] for 8 64-bit OpMask registers (k0-k7) - * - Intel: XFEATURE_ENABLED_MASK[bit 6] for the high 256 bits of the zmm registers zmm0-zmm15 - * - Intel: XFEATURE_ENABLED_MASK[bit 7] for the 512-bit zmm registers zmm16-zmm31 + * - Intel, AMD: XFEATURE_ENABLED_MASK[bit 1] for low 128 bits + * of zmm registers + * - Intel, AMD: XFEATURE_ENABLED_MASK[bit 2] for bits 128-255 + * of zmm registers + * - Intel: XFEATURE_ENABLED_MASK[bit 5] for 8 64-bit OpMask + * registers (k0-k7) + * - Intel: XFEATURE_ENABLED_MASK[bit 6] for the high 256 bits + * of the zmm registers zmm0-zmm15 + * - Intel: XFEATURE_ENABLED_MASK[bit 7] for the 512-bit zmm + * registers zmm16-zmm31 */ const uint64_t avx512_regs_mask = UINT64_C(0x00000000000000E6); if ((xcr0_valid_bits & avx512_regs_mask) == avx512_regs_mask) { @@ -134,7 +144,8 @@ struct cpuinfo_x86_isa cpuinfo_x86_detect_isa( /* * CLZERO instruction: - * - AMD: ebx[bit 0] in processor capacity info (reserved bit on Intel CPUs). + * - AMD: ebx[bit 0] in processor capacity info (reserved bit on Intel + * CPUs). */ isa.clzero = !!(processor_capacity_info.ebx & UINT32_C(0x00000001)); @@ -165,7 +176,8 @@ struct cpuinfo_x86_isa cpuinfo_x86_detect_isa( /* * FXSAVE/FXRSTOR instructions: * - Intel, AMD: edx[bit 24] in basic info. - * - AMD: edx[bit 24] in extended info (zero bit on Intel CPUs, EMMX bit on Cyrix CPUs). + * - AMD: edx[bit 24] in extended info (zero bit on Intel CPUs, EMMX bit + * on Cyrix CPUs). */ switch (vendor) { #if CPUINFO_ARCH_X86 @@ -230,27 +242,35 @@ struct cpuinfo_x86_isa cpuinfo_x86_detect_isa( /* * PREFETCH instruction: - * - AMD: ecx[bit 8] of extended info (one of 3dnow! prefetch instructions). - * On Intel this bit indicates PREFETCHW, but not PREFETCH support. - * - AMD: edx[bit 31] of extended info (implied by 3dnow! support). Reserved bit on Intel CPUs. - * - AMD: edx[bit 30] of extended info (implied by 3dnow!+ support). Reserved bit on Intel CPUs. - * - AMD: edx[bit 29] of extended info (x86-64 support). Does not imply PREFETCH support on non-AMD CPUs!!! + * - AMD: ecx[bit 8] of extended info (one of 3dnow! prefetch + * instructions). On Intel this bit indicates PREFETCHW, but not + * PREFETCH support. + * - AMD: edx[bit 31] of extended info (implied by 3dnow! support). + * Reserved bit on Intel CPUs. + * - AMD: edx[bit 30] of extended info (implied by 3dnow!+ support). + * Reserved bit on Intel CPUs. + * - AMD: edx[bit 29] of extended info (x86-64 support). Does not imply + * PREFETCH support on non-AMD CPUs!!! */ switch (vendor) { case cpuinfo_vendor_intel: /* * Instruction is not documented in the manual, - * and the 3dnow! prefetch CPUID bit indicates PREFETCHW instruction. + * and the 3dnow! prefetch CPUID bit indicates PREFETCHW + * instruction. */ break; case cpuinfo_vendor_amd: case cpuinfo_vendor_hygon: - isa.prefetch = !!((extended_info.ecx & UINT32_C(0x00000100)) | (extended_info.edx & UINT32_C(0xE0000000))); + isa.prefetch = + !!((extended_info.ecx & UINT32_C(0x00000100)) | + (extended_info.edx & UINT32_C(0xE0000000))); break; default: /* - * Conservatively assume, that 3dnow!/3dnow!+ support implies PREFETCH support, but - * 3dnow! prefetch CPUID bit follows Intel spec (PREFETCHW, but not PREFETCH). + * Conservatively assume, that 3dnow!/3dnow!+ support + * implies PREFETCH support, but 3dnow! prefetch CPUID + * bit follows Intel spec (PREFETCHW, but not PREFETCH). */ isa.prefetch = !!(extended_info.edx & UINT32_C(0xC0000000)); break; @@ -258,26 +278,36 @@ struct cpuinfo_x86_isa cpuinfo_x86_detect_isa( /* * PREFETCHW instruction: - * - AMD: ecx[bit 8] of extended info (one of 3dnow! prefetch instructions). + * - AMD: ecx[bit 8] of extended info (one of 3dnow! prefetch + * instructions). * - Intel: ecx[bit 8] of extended info (PREFETCHW instruction only). - * - AMD: edx[bit 31] of extended info (implied by 3dnow! support). Reserved bit on Intel CPUs. - * - AMD: edx[bit 30] of extended info (implied by 3dnow!+ support). Reserved bit on Intel CPUs. - * - AMD: edx[bit 29] of extended info (x86-64 support). Does not imply PREFETCHW support on non-AMD CPUs!!! + * - AMD: edx[bit 31] of extended info (implied by 3dnow! support). + * Reserved bit on Intel CPUs. + * - AMD: edx[bit 30] of extended info (implied by 3dnow!+ support). + * Reserved bit on Intel CPUs. + * - AMD: edx[bit 29] of extended info (x86-64 support). Does not imply + * PREFETCHW support on non-AMD CPUs!!! */ switch (vendor) { case cpuinfo_vendor_amd: case cpuinfo_vendor_hygon: - isa.prefetchw = !!((extended_info.ecx & UINT32_C(0x00000100)) | (extended_info.edx & UINT32_C(0xE0000000))); + isa.prefetchw = + !!((extended_info.ecx & UINT32_C(0x00000100)) | + (extended_info.edx & UINT32_C(0xE0000000))); break; default: - /* Assume, that 3dnow!/3dnow!+ support implies PREFETCHW support, not implications from x86-64 support */ - isa.prefetchw = !!((extended_info.ecx & UINT32_C(0x00000100)) | (extended_info.edx & UINT32_C(0xC0000000))); + /* Assume, that 3dnow!/3dnow!+ support implies PREFETCHW + * support, not implications from x86-64 support */ + isa.prefetchw = + !!((extended_info.ecx & UINT32_C(0x00000100)) | + (extended_info.edx & UINT32_C(0xC0000000))); break; } /* * PREFETCHWT1 instruction: - * - Intel: ecx[bit 0] of structured feature info (ecx = 0). Reserved bit on AMD. + * - Intel: ecx[bit 0] of structured feature info (ecx = 0). Reserved + * bit on AMD. */ isa.prefetchwt1 = !!(structured_feature_info0.ecx & UINT32_C(0x00000001)); @@ -311,12 +341,12 @@ struct cpuinfo_x86_isa cpuinfo_x86_detect_isa( } else { /* Detect DAZ support from masked MXCSR bits */ if (isa.sse && isa.fxsave) { - struct fxsave_region region = { 0 }; - #ifdef _MSC_VER - _fxsave(®ion); - #else - __asm__ __volatile__ ("fxsave %[region];" : [region] "+m" (region)); - #endif + struct fxsave_region region = {0}; +#ifdef _MSC_VER + _fxsave(®ion); +#else + __asm__ __volatile__("fxsave %[region];" : [region] "+m"(region)); +#endif /* * Denormals-as-zero (DAZ) flag: @@ -333,7 +363,6 @@ struct cpuinfo_x86_isa cpuinfo_x86_detect_isa( */ isa.ssse3 = !!(basic_info.ecx & UINT32_C(0x0000200)); - /* * SSE4.1 instructions: * - Intel, AMD: ecx[bit 19] in basic info. @@ -569,7 +598,8 @@ struct cpuinfo_x86_isa cpuinfo_x86_detect_isa( #if CPUINFO_ARCH_X86_64 /* * Some early x86-64 CPUs lack LAHF & SAHF instructions. - * A special CPU feature bit must be checked to ensure their availability: + * A special CPU feature bit must be checked to ensure their + * availability: * - Intel, AMD: ecx[bit 0] in extended info. */ isa.lahf_sahf = !!(extended_info.ecx & UINT32_C(0x00000001)); @@ -674,40 +704,50 @@ struct cpuinfo_x86_isa cpuinfo_x86_detect_isa( /* * Padlock RNG extension: - * - VIA: edx[bit 2] in padlock info = RNG exists on chip flag. - * - VIA: edx[bit 3] in padlock info = RNG enabled by OS. + * - VIA: edx[bit 2] in padlock info = RNG exists on + * chip flag. + * - VIA: edx[bit 3] in padlock info = RNG enabled by + * OS. */ const uint32_t padlock_rng_mask = UINT32_C(0x0000000C); isa.rng = (padlock_info.edx & padlock_rng_mask) == padlock_rng_mask; /* * Padlock ACE extension: - * - VIA: edx[bit 6] in padlock info = ACE exists on chip flag. - * - VIA: edx[bit 7] in padlock info = ACE enabled by OS. + * - VIA: edx[bit 6] in padlock info = ACE exists on + * chip flag. + * - VIA: edx[bit 7] in padlock info = ACE enabled by + * OS. */ const uint32_t padlock_ace_mask = UINT32_C(0x000000C0); isa.ace = (padlock_info.edx & padlock_ace_mask) == padlock_ace_mask; /* * Padlock ACE 2 extension: - * - VIA: edx[bit 8] in padlock info = ACE2 exists on chip flag. - * - VIA: edx[bit 9] in padlock info = ACE 2 enabled by OS. + * - VIA: edx[bit 8] in padlock info = ACE2 exists on + * chip flag. + * - VIA: edx[bit 9] in padlock info = ACE 2 enabled by + * OS. */ const uint32_t padlock_ace2_mask = UINT32_C(0x00000300); isa.ace2 = (padlock_info.edx & padlock_ace2_mask) == padlock_ace2_mask; /* * Padlock PHE extension: - * - VIA: edx[bit 10] in padlock info = PHE exists on chip flag. - * - VIA: edx[bit 11] in padlock info = PHE enabled by OS. + * - VIA: edx[bit 10] in padlock info = PHE exists on + * chip flag. + * - VIA: edx[bit 11] in padlock info = PHE enabled by + * OS. */ const uint32_t padlock_phe_mask = UINT32_C(0x00000C00); isa.phe = (padlock_info.edx & padlock_phe_mask) == padlock_phe_mask; /* * Padlock PMM extension: - * - VIA: edx[bit 12] in padlock info = PMM exists on chip flag. - * - VIA: edx[bit 13] in padlock info = PMM enabled by OS. + * - VIA: edx[bit 12] in padlock info = PMM exists on + * chip flag. + * - VIA: edx[bit 13] in padlock info = PMM enabled by + * OS. */ const uint32_t padlock_pmm_mask = UINT32_C(0x00003000); isa.pmm = (padlock_info.edx & padlock_pmm_mask) == padlock_pmm_mask; diff --git a/src/x86/linux/api.h b/src/x86/linux/api.h index 1c9485b1..26fc5de0 100644 --- a/src/x86/linux/api.h +++ b/src/x86/linux/api.h @@ -5,9 +5,8 @@ #include #include -#include #include - +#include struct cpuinfo_x86_linux_processor { uint32_t apic_id; diff --git a/src/x86/linux/cpuinfo.c b/src/x86/linux/cpuinfo.c index 90ff8143..ff90884e 100644 --- a/src/x86/linux/cpuinfo.c +++ b/src/x86/linux/cpuinfo.c @@ -1,25 +1,21 @@ #include +#include #include #include -#include #include +#include #include #include -#include /* - * Size, in chars, of the on-stack buffer used for parsing lines of /proc/cpuinfo. - * This is also the limit on the length of a single line. + * Size, in chars, of the on-stack buffer used for parsing lines of + * /proc/cpuinfo. This is also the limit on the length of a single line. */ #define BUFFER_SIZE 2048 - -static uint32_t parse_processor_number( - const char* processor_start, - const char* processor_end) -{ - const size_t processor_length = (size_t) (processor_end - processor_start); +static uint32_t parse_processor_number(const char* processor_start, const char* processor_end) { + const size_t processor_length = (size_t)(processor_end - processor_start); if (processor_length == 0) { cpuinfo_log_warning("Processor number in /proc/cpuinfo is ignored: string is empty"); @@ -28,10 +24,12 @@ static uint32_t parse_processor_number( uint32_t processor_number = 0; for (const char* digit_ptr = processor_start; digit_ptr != processor_end; digit_ptr++) { - const uint32_t digit = (uint32_t) (*digit_ptr - '0'); + const uint32_t digit = (uint32_t)(*digit_ptr - '0'); if (digit > 10) { - cpuinfo_log_warning("non-decimal suffix %.*s in /proc/cpuinfo processor number is ignored", - (int) (processor_end - digit_ptr), digit_ptr); + cpuinfo_log_warning( + "non-decimal suffix %.*s in /proc/cpuinfo processor number is ignored", + (int)(processor_end - digit_ptr), + digit_ptr); break; } @@ -50,15 +48,17 @@ static uint32_t parse_processor_number( static void parse_apic_id( const char* apic_start, const char* apic_end, - struct cpuinfo_x86_linux_processor processor[restrict static 1]) -{ + struct cpuinfo_x86_linux_processor processor[restrict static 1]) { uint32_t apic_id = 0; for (const char* digit_ptr = apic_start; digit_ptr != apic_end; digit_ptr++) { const uint32_t digit = *digit_ptr - '0'; if (digit >= 10) { - cpuinfo_log_warning("APIC ID %.*s in /proc/cpuinfo is ignored due to unexpected non-digit character '%c' at offset %zu", - (int) (apic_end - apic_start), apic_start, - *digit_ptr, (size_t) (digit_ptr - apic_start)); + cpuinfo_log_warning( + "APIC ID %.*s in /proc/cpuinfo is ignored due to unexpected non-digit character '%c' at offset %zu", + (int)(apic_end - apic_start), + apic_start, + *digit_ptr, + (size_t)(digit_ptr - apic_start)); return; } @@ -84,8 +84,7 @@ static bool parse_line( const char* line_start, const char* line_end, struct proc_cpuinfo_parser_state state[restrict static 1], - uint64_t line_number) -{ + uint64_t line_number) { /* Empty line. Skip. */ if (line_start == line_end) { return true; @@ -100,8 +99,10 @@ static bool parse_line( } /* Skip line if no ':' separator was found. */ if (separator == line_end) { - cpuinfo_log_info("Line %.*s in /proc/cpuinfo is ignored: key/value separator ':' not found", - (int) (line_end - line_start), line_start); + cpuinfo_log_info( + "Line %.*s in /proc/cpuinfo is ignored: key/value separator ':' not found", + (int)(line_end - line_start), + line_start); return true; } @@ -114,8 +115,10 @@ static bool parse_line( } /* Skip line if key contains nothing but spaces. */ if (key_end == line_start) { - cpuinfo_log_info("Line %.*s in /proc/cpuinfo is ignored: key contains only spaces", - (int) (line_end - line_start), line_start); + cpuinfo_log_info( + "Line %.*s in /proc/cpuinfo is ignored: key contains only spaces", + (int)(line_end - line_start), + line_start); return true; } @@ -128,8 +131,10 @@ static bool parse_line( } /* Value part contains nothing but spaces. Skip line. */ if (value_start == line_end) { - cpuinfo_log_info("Line %.*s in /proc/cpuinfo is ignored: value contains only spaces", - (int) (line_end - line_start), line_start); + cpuinfo_log_info( + "Line %.*s in /proc/cpuinfo is ignored: value contains only spaces", + (int)(line_end - line_start), + line_start); return true; } @@ -141,10 +146,10 @@ static bool parse_line( } } - const uint32_t processor_index = state->processor_index; + const uint32_t processor_index = state->processor_index; const uint32_t max_processors_count = state->max_processors_count; struct cpuinfo_x86_linux_processor* processors = state->processors; - struct cpuinfo_x86_linux_processor* processor = &state->dummy_processor; + struct cpuinfo_x86_linux_processor* processor = &state->dummy_processor; if (processor_index < max_processors_count) { processor = &processors[processor_index]; } @@ -162,20 +167,29 @@ static bool parse_line( if (memcmp(line_start, "processor", key_length) == 0) { const uint32_t new_processor_index = parse_processor_number(value_start, value_end); if (new_processor_index < processor_index) { - /* Strange: decreasing processor number */ + /* Strange: decreasing processor number + */ cpuinfo_log_warning( - "unexpectedly low processor number %"PRIu32" following processor %"PRIu32" in /proc/cpuinfo", - new_processor_index, processor_index); + "unexpectedly low processor number %" PRIu32 + " following processor %" PRIu32 " in /proc/cpuinfo", + new_processor_index, + processor_index); } else if (new_processor_index > processor_index + 1) { - /* Strange, but common: skipped processor $(processor_index + 1) */ + /* Strange, but common: skipped + * processor $(processor_index + 1) */ cpuinfo_log_info( - "unexpectedly high processor number %"PRIu32" following processor %"PRIu32" in /proc/cpuinfo", - new_processor_index, processor_index); + "unexpectedly high processor number %" PRIu32 + " following processor %" PRIu32 " in /proc/cpuinfo", + new_processor_index, + processor_index); } if (new_processor_index >= max_processors_count) { /* Log and ignore processor */ - cpuinfo_log_warning("processor %"PRIu32" in /proc/cpuinfo is ignored: index exceeds system limit %"PRIu32, - new_processor_index, max_processors_count - 1); + cpuinfo_log_warning( + "processor %" PRIu32 + " in /proc/cpuinfo is ignored: index exceeds system limit %" PRIu32, + new_processor_index, + max_processors_count - 1); } else { processors[new_processor_index].flags |= CPUINFO_LINUX_FLAG_PROC_CPUINFO; } @@ -187,21 +201,19 @@ static bool parse_line( break; default: unknown: - cpuinfo_log_debug("unknown /proc/cpuinfo key: %.*s", (int) key_length, line_start); - + cpuinfo_log_debug("unknown /proc/cpuinfo key: %.*s", (int)key_length, line_start); } return true; } bool cpuinfo_x86_linux_parse_proc_cpuinfo( uint32_t max_processors_count, - struct cpuinfo_x86_linux_processor processors[restrict static max_processors_count]) -{ + struct cpuinfo_x86_linux_processor processors[restrict static max_processors_count]) { struct proc_cpuinfo_parser_state state = { .processor_index = 0, .max_processors_count = max_processors_count, .processors = processors, }; - return cpuinfo_linux_parse_multiline_file("/proc/cpuinfo", BUFFER_SIZE, - (cpuinfo_line_callback) parse_line, &state); + return cpuinfo_linux_parse_multiline_file( + "/proc/cpuinfo", BUFFER_SIZE, (cpuinfo_line_callback)parse_line, &state); } diff --git a/src/x86/linux/init.c b/src/x86/linux/init.c index f5657890..d2b2d475 100644 --- a/src/x86/linux/init.c +++ b/src/x86/linux/init.c @@ -1,15 +1,14 @@ -#include #include +#include #include #include #include -#include -#include -#include #include #include - +#include +#include +#include static inline uint32_t bit_mask(uint32_t bits) { return (UINT32_C(1) << bits) - UINT32_C(1); @@ -28,14 +27,14 @@ static inline int cmp(uint32_t a, uint32_t b) { } static int cmp_x86_linux_processor(const void* ptr_a, const void* ptr_b) { - const struct cpuinfo_x86_linux_processor* processor_a = (const struct cpuinfo_x86_linux_processor*) ptr_a; - const struct cpuinfo_x86_linux_processor* processor_b = (const struct cpuinfo_x86_linux_processor*) ptr_b; + const struct cpuinfo_x86_linux_processor* processor_a = (const struct cpuinfo_x86_linux_processor*)ptr_a; + const struct cpuinfo_x86_linux_processor* processor_b = (const struct cpuinfo_x86_linux_processor*)ptr_b; /* Move usable processors towards the start of the array */ const bool usable_a = bitmask_all(processor_a->flags, CPUINFO_LINUX_FLAG_VALID); const bool usable_b = bitmask_all(processor_b->flags, CPUINFO_LINUX_FLAG_VALID); if (usable_a != usable_b) { - return (int) usable_b - (int) usable_a; + return (int)usable_b - (int)usable_a; } /* Compare based on APIC ID (i.e. processor 0 < processor 1) */ @@ -57,12 +56,11 @@ static void cpuinfo_x86_count_objects( uint32_t l1d_count_ptr[restrict static 1], uint32_t l2_count_ptr[restrict static 1], uint32_t l3_count_ptr[restrict static 1], - uint32_t l4_count_ptr[restrict static 1]) -{ + uint32_t l4_count_ptr[restrict static 1]) { const uint32_t core_apic_mask = ~(bit_mask(processor->topology.thread_bits_length) << processor->topology.thread_bits_offset); - const uint32_t package_apic_mask = - core_apic_mask & ~(bit_mask(processor->topology.core_bits_length) << processor->topology.core_bits_offset); + const uint32_t package_apic_mask = core_apic_mask & + ~(bit_mask(processor->topology.core_bits_length) << processor->topology.core_bits_offset); const uint32_t llc_apic_mask = ~bit_mask(llc_apic_bits); const uint32_t cluster_apic_mask = package_apic_mask | llc_apic_mask; @@ -74,7 +72,10 @@ static void cpuinfo_x86_count_objects( for (uint32_t i = 0; i < linux_processors_count; i++) { if (bitmask_all(linux_processors[i].flags, valid_processor_mask)) { const uint32_t apic_id = linux_processors[i].apic_id; - cpuinfo_log_debug("APID ID %"PRIu32": system processor %"PRIu32, apic_id, linux_processors[i].linux_id); + cpuinfo_log_debug( + "APID ID %" PRIu32 ": system processor %" PRIu32, + apic_id, + linux_processors[i].linux_id); /* All bits of APIC ID except thread ID mask */ const uint32_t core_id = apic_id & core_apic_mask; @@ -82,13 +83,15 @@ static void cpuinfo_x86_count_objects( last_core_id = core_id; cores_count++; } - /* All bits of APIC ID except thread ID and core ID masks */ + /* All bits of APIC ID except thread ID and core ID + * masks */ const uint32_t package_id = apic_id & package_apic_mask; if (package_id != last_package_id) { last_package_id = package_id; packages_count++; } - /* Bits of APIC ID which are part of either LLC or package ID mask */ + /* Bits of APIC ID which are part of either LLC or + * package ID mask */ const uint32_t cluster_id = apic_id & cluster_apic_mask; if (cluster_id != last_cluster_id) { last_cluster_id = cluster_id; @@ -136,9 +139,9 @@ static void cpuinfo_x86_count_objects( *packages_count_ptr = packages_count; *l1i_count_ptr = l1i_count; *l1d_count_ptr = l1d_count; - *l2_count_ptr = l2_count; - *l3_count_ptr = l3_count; - *l4_count_ptr = l4_count; + *l2_count_ptr = l2_count; + *l3_count_ptr = l3_count; + *l4_count_ptr = l4_count; } void cpuinfo_x86_linux_init(void) { @@ -156,14 +159,13 @@ void cpuinfo_x86_linux_init(void) { struct cpuinfo_cache* l4 = NULL; const uint32_t max_processors_count = cpuinfo_linux_get_max_processors_count(); - cpuinfo_log_debug("system maximum processors count: %"PRIu32, max_processors_count); + cpuinfo_log_debug("system maximum processors count: %" PRIu32, max_processors_count); - const uint32_t max_possible_processors_count = 1 + - cpuinfo_linux_get_max_possible_processor(max_processors_count); - cpuinfo_log_debug("maximum possible processors count: %"PRIu32, max_possible_processors_count); - const uint32_t max_present_processors_count = 1 + - cpuinfo_linux_get_max_present_processor(max_processors_count); - cpuinfo_log_debug("maximum present processors count: %"PRIu32, max_present_processors_count); + const uint32_t max_possible_processors_count = + 1 + cpuinfo_linux_get_max_possible_processor(max_processors_count); + cpuinfo_log_debug("maximum possible processors count: %" PRIu32, max_possible_processors_count); + const uint32_t max_present_processors_count = 1 + cpuinfo_linux_get_max_present_processor(max_processors_count); + cpuinfo_log_debug("maximum present processors count: %" PRIu32, max_present_processors_count); uint32_t valid_processor_mask = 0; uint32_t x86_linux_processors_count = max_processors_count; @@ -181,7 +183,7 @@ void cpuinfo_x86_linux_init(void) { x86_linux_processors = calloc(x86_linux_processors_count, sizeof(struct cpuinfo_x86_linux_processor)); if (x86_linux_processors == NULL) { cpuinfo_log_error( - "failed to allocate %zu bytes for descriptions of %"PRIu32" x86 logical processors", + "failed to allocate %zu bytes for descriptions of %" PRIu32 " x86 logical processors", x86_linux_processors_count * sizeof(struct cpuinfo_x86_linux_processor), x86_linux_processors_count); return; @@ -189,14 +191,16 @@ void cpuinfo_x86_linux_init(void) { if (max_possible_processors_count != 0) { cpuinfo_linux_detect_possible_processors( - x86_linux_processors_count, &x86_linux_processors->flags, + x86_linux_processors_count, + &x86_linux_processors->flags, sizeof(struct cpuinfo_x86_linux_processor), CPUINFO_LINUX_FLAG_POSSIBLE); } if (max_present_processors_count != 0) { cpuinfo_linux_detect_present_processors( - x86_linux_processors_count, &x86_linux_processors->flags, + x86_linux_processors_count, + &x86_linux_processors->flags, sizeof(struct cpuinfo_x86_linux_processor), CPUINFO_LINUX_FLAG_PRESENT); } @@ -226,13 +230,17 @@ void cpuinfo_x86_linux_init(void) { } } - qsort(x86_linux_processors, x86_linux_processors_count, sizeof(struct cpuinfo_x86_linux_processor), - cmp_x86_linux_processor); + qsort(x86_linux_processors, + x86_linux_processors_count, + sizeof(struct cpuinfo_x86_linux_processor), + cmp_x86_linux_processor); processors = calloc(processors_count, sizeof(struct cpuinfo_processor)); if (processors == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" logical processors", - processors_count * sizeof(struct cpuinfo_processor), processors_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " logical processors", + processors_count * sizeof(struct cpuinfo_processor), + processors_count); goto cleanup; } @@ -249,21 +257,33 @@ void cpuinfo_x86_linux_init(void) { uint32_t packages_count = 0, clusters_count = 0, cores_count = 0; uint32_t l1i_count = 0, l1d_count = 0, l2_count = 0, l3_count = 0, l4_count = 0; cpuinfo_x86_count_objects( - x86_linux_processors_count, x86_linux_processors, &x86_processor, valid_processor_mask, llc_apic_bits, - &cores_count, &clusters_count, &packages_count, &l1i_count, &l1d_count, &l2_count, &l3_count, &l4_count); - - cpuinfo_log_debug("detected %"PRIu32" cores", cores_count); - cpuinfo_log_debug("detected %"PRIu32" clusters", clusters_count); - cpuinfo_log_debug("detected %"PRIu32" packages", packages_count); - cpuinfo_log_debug("detected %"PRIu32" L1I caches", l1i_count); - cpuinfo_log_debug("detected %"PRIu32" L1D caches", l1d_count); - cpuinfo_log_debug("detected %"PRIu32" L2 caches", l2_count); - cpuinfo_log_debug("detected %"PRIu32" L3 caches", l3_count); - cpuinfo_log_debug("detected %"PRIu32" L4 caches", l4_count); + x86_linux_processors_count, + x86_linux_processors, + &x86_processor, + valid_processor_mask, + llc_apic_bits, + &cores_count, + &clusters_count, + &packages_count, + &l1i_count, + &l1d_count, + &l2_count, + &l3_count, + &l4_count); + + cpuinfo_log_debug("detected %" PRIu32 " cores", cores_count); + cpuinfo_log_debug("detected %" PRIu32 " clusters", clusters_count); + cpuinfo_log_debug("detected %" PRIu32 " packages", packages_count); + cpuinfo_log_debug("detected %" PRIu32 " L1I caches", l1i_count); + cpuinfo_log_debug("detected %" PRIu32 " L1D caches", l1d_count); + cpuinfo_log_debug("detected %" PRIu32 " L2 caches", l2_count); + cpuinfo_log_debug("detected %" PRIu32 " L3 caches", l3_count); + cpuinfo_log_debug("detected %" PRIu32 " L4 caches", l4_count); linux_cpu_to_processor_map = calloc(x86_linux_processors_count, sizeof(struct cpuinfo_processor*)); if (linux_cpu_to_processor_map == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for mapping entries of %"PRIu32" logical processors", + cpuinfo_log_error( + "failed to allocate %zu bytes for mapping entries of %" PRIu32 " logical processors", x86_linux_processors_count * sizeof(struct cpuinfo_processor*), x86_linux_processors_count); goto cleanup; @@ -271,7 +291,8 @@ void cpuinfo_x86_linux_init(void) { linux_cpu_to_core_map = calloc(x86_linux_processors_count, sizeof(struct cpuinfo_core*)); if (linux_cpu_to_core_map == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for mapping entries of %"PRIu32" cores", + cpuinfo_log_error( + "failed to allocate %zu bytes for mapping entries of %" PRIu32 " cores", x86_linux_processors_count * sizeof(struct cpuinfo_core*), x86_linux_processors_count); goto cleanup; @@ -279,75 +300,93 @@ void cpuinfo_x86_linux_init(void) { cores = calloc(cores_count, sizeof(struct cpuinfo_core)); if (cores == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" cores", - cores_count * sizeof(struct cpuinfo_core), cores_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " cores", + cores_count * sizeof(struct cpuinfo_core), + cores_count); goto cleanup; } clusters = calloc(clusters_count, sizeof(struct cpuinfo_cluster)); if (clusters == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" core clusters", - clusters_count * sizeof(struct cpuinfo_cluster), clusters_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " core clusters", + clusters_count * sizeof(struct cpuinfo_cluster), + clusters_count); goto cleanup; } packages = calloc(packages_count, sizeof(struct cpuinfo_package)); if (packages == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" physical packages", - packages_count * sizeof(struct cpuinfo_package), packages_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " physical packages", + packages_count * sizeof(struct cpuinfo_package), + packages_count); goto cleanup; } if (l1i_count != 0) { l1i = calloc(l1i_count, sizeof(struct cpuinfo_cache)); if (l1i == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L1I caches", - l1i_count * sizeof(struct cpuinfo_cache), l1i_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L1I caches", + l1i_count * sizeof(struct cpuinfo_cache), + l1i_count); goto cleanup; } } if (l1d_count != 0) { l1d = calloc(l1d_count, sizeof(struct cpuinfo_cache)); if (l1d == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L1D caches", - l1d_count * sizeof(struct cpuinfo_cache), l1d_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L1D caches", + l1d_count * sizeof(struct cpuinfo_cache), + l1d_count); goto cleanup; } } if (l2_count != 0) { l2 = calloc(l2_count, sizeof(struct cpuinfo_cache)); if (l2 == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L2 caches", - l2_count * sizeof(struct cpuinfo_cache), l2_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L2 caches", + l2_count * sizeof(struct cpuinfo_cache), + l2_count); goto cleanup; } } if (l3_count != 0) { l3 = calloc(l3_count, sizeof(struct cpuinfo_cache)); if (l3 == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L3 caches", - l3_count * sizeof(struct cpuinfo_cache), l3_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L3 caches", + l3_count * sizeof(struct cpuinfo_cache), + l3_count); goto cleanup; } } if (l4_count != 0) { l4 = calloc(l4_count, sizeof(struct cpuinfo_cache)); if (l4 == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L4 caches", - l4_count * sizeof(struct cpuinfo_cache), l4_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L4 caches", + l4_count * sizeof(struct cpuinfo_cache), + l4_count); goto cleanup; } } const uint32_t core_apic_mask = ~(bit_mask(x86_processor.topology.thread_bits_length) << x86_processor.topology.thread_bits_offset); - const uint32_t package_apic_mask = - core_apic_mask & ~(bit_mask(x86_processor.topology.core_bits_length) << x86_processor.topology.core_bits_offset); + const uint32_t package_apic_mask = core_apic_mask & + ~(bit_mask(x86_processor.topology.core_bits_length) << x86_processor.topology.core_bits_offset); const uint32_t llc_apic_mask = ~bit_mask(llc_apic_bits); const uint32_t cluster_apic_mask = package_apic_mask | llc_apic_mask; - uint32_t processor_index = UINT32_MAX, core_index = UINT32_MAX, cluster_index = UINT32_MAX, package_index = UINT32_MAX; - uint32_t l1i_index = UINT32_MAX, l1d_index = UINT32_MAX, l2_index = UINT32_MAX, l3_index = UINT32_MAX, l4_index = UINT32_MAX; + uint32_t processor_index = UINT32_MAX, core_index = UINT32_MAX, cluster_index = UINT32_MAX, + package_index = UINT32_MAX; + uint32_t l1i_index = UINT32_MAX, l1d_index = UINT32_MAX, l2_index = UINT32_MAX, l3_index = UINT32_MAX, + l4_index = UINT32_MAX; uint32_t cluster_id = 0, core_id = 0, smt_id = 0; uint32_t last_apic_core_id = UINT32_MAX, last_apic_cluster_id = UINT32_MAX, last_apic_package_id = UINT32_MAX; uint32_t last_l1i_id = UINT32_MAX, last_l1d_id = UINT32_MAX; @@ -365,13 +404,15 @@ void cpuinfo_x86_linux_init(void) { core_id++; smt_id = 0; } - /* Bits of APIC ID which are part of either LLC or package ID mask */ + /* Bits of APIC ID which are part of either LLC or + * package ID mask */ const uint32_t apic_cluster_id = apic_id & cluster_apic_mask; if (apic_cluster_id != last_apic_cluster_id) { cluster_index++; cluster_id++; } - /* All bits of APIC ID except thread ID and core ID masks */ + /* All bits of APIC ID except thread ID and core ID + * masks */ const uint32_t apic_package_id = apic_id & package_apic_mask; if (apic_package_id != last_apic_package_id) { package_index++; @@ -380,16 +421,16 @@ void cpuinfo_x86_linux_init(void) { } /* Initialize logical processor object */ - processors[processor_index].smt_id = smt_id; - processors[processor_index].core = cores + core_index; - processors[processor_index].cluster = clusters + cluster_index; - processors[processor_index].package = packages + package_index; + processors[processor_index].smt_id = smt_id; + processors[processor_index].core = cores + core_index; + processors[processor_index].cluster = clusters + cluster_index; + processors[processor_index].package = packages + package_index; processors[processor_index].linux_id = x86_linux_processors[i].linux_id; - processors[processor_index].apic_id = x86_linux_processors[i].apic_id; + processors[processor_index].apic_id = x86_linux_processors[i].apic_id; if (apid_core_id != last_apic_core_id) { /* new core */ - cores[core_index] = (struct cpuinfo_core) { + cores[core_index] = (struct cpuinfo_core){ .processor_start = processor_index, .processor_count = 1, .core_id = core_id, @@ -420,7 +461,8 @@ void cpuinfo_x86_linux_init(void) { packages[package_index].cluster_count += 1; last_apic_cluster_id = apic_cluster_id; } else { - /* another logical processor on the same cluster */ + /* another logical processor on the same cluster + */ clusters[cluster_index].processor_count++; } @@ -430,10 +472,12 @@ void cpuinfo_x86_linux_init(void) { packages[package_index].processor_count = 1; packages[package_index].core_start = core_index; packages[package_index].cluster_start = cluster_index; - cpuinfo_x86_format_package_name(x86_processor.vendor, brand_string, packages[package_index].name); + cpuinfo_x86_format_package_name( + x86_processor.vendor, brand_string, packages[package_index].name); last_apic_package_id = apic_package_id; } else { - /* another logical processor on the same package */ + /* another logical processor on the same package + */ packages[package_index].processor_count++; } @@ -446,18 +490,19 @@ void cpuinfo_x86_linux_init(void) { if (l1i_id != last_l1i_id) { /* new cache */ last_l1i_id = l1i_id; - l1i[++l1i_index] = (struct cpuinfo_cache) { - .size = x86_processor.cache.l1i.size, - .associativity = x86_processor.cache.l1i.associativity, - .sets = x86_processor.cache.l1i.sets, - .partitions = x86_processor.cache.l1i.partitions, - .line_size = x86_processor.cache.l1i.line_size, - .flags = x86_processor.cache.l1i.flags, + l1i[++l1i_index] = (struct cpuinfo_cache){ + .size = x86_processor.cache.l1i.size, + .associativity = x86_processor.cache.l1i.associativity, + .sets = x86_processor.cache.l1i.sets, + .partitions = x86_processor.cache.l1i.partitions, + .line_size = x86_processor.cache.l1i.line_size, + .flags = x86_processor.cache.l1i.flags, .processor_start = processor_index, .processor_count = 1, }; } else { - /* another processor sharing the same cache */ + /* another processor sharing the same + * cache */ l1i[l1i_index].processor_count += 1; } processors[i].cache.l1i = &l1i[l1i_index]; @@ -471,18 +516,19 @@ void cpuinfo_x86_linux_init(void) { if (l1d_id != last_l1d_id) { /* new cache */ last_l1d_id = l1d_id; - l1d[++l1d_index] = (struct cpuinfo_cache) { - .size = x86_processor.cache.l1d.size, - .associativity = x86_processor.cache.l1d.associativity, - .sets = x86_processor.cache.l1d.sets, - .partitions = x86_processor.cache.l1d.partitions, - .line_size = x86_processor.cache.l1d.line_size, - .flags = x86_processor.cache.l1d.flags, + l1d[++l1d_index] = (struct cpuinfo_cache){ + .size = x86_processor.cache.l1d.size, + .associativity = x86_processor.cache.l1d.associativity, + .sets = x86_processor.cache.l1d.sets, + .partitions = x86_processor.cache.l1d.partitions, + .line_size = x86_processor.cache.l1d.line_size, + .flags = x86_processor.cache.l1d.flags, .processor_start = processor_index, .processor_count = 1, }; } else { - /* another processor sharing the same cache */ + /* another processor sharing the same + * cache */ l1d[l1d_index].processor_count += 1; } processors[i].cache.l1d = &l1d[l1d_index]; @@ -496,18 +542,19 @@ void cpuinfo_x86_linux_init(void) { if (l2_id != last_l2_id) { /* new cache */ last_l2_id = l2_id; - l2[++l2_index] = (struct cpuinfo_cache) { - .size = x86_processor.cache.l2.size, - .associativity = x86_processor.cache.l2.associativity, - .sets = x86_processor.cache.l2.sets, - .partitions = x86_processor.cache.l2.partitions, - .line_size = x86_processor.cache.l2.line_size, - .flags = x86_processor.cache.l2.flags, + l2[++l2_index] = (struct cpuinfo_cache){ + .size = x86_processor.cache.l2.size, + .associativity = x86_processor.cache.l2.associativity, + .sets = x86_processor.cache.l2.sets, + .partitions = x86_processor.cache.l2.partitions, + .line_size = x86_processor.cache.l2.line_size, + .flags = x86_processor.cache.l2.flags, .processor_start = processor_index, .processor_count = 1, }; } else { - /* another processor sharing the same cache */ + /* another processor sharing the same + * cache */ l2[l2_index].processor_count += 1; } processors[i].cache.l2 = &l2[l2_index]; @@ -521,18 +568,19 @@ void cpuinfo_x86_linux_init(void) { if (l3_id != last_l3_id) { /* new cache */ last_l3_id = l3_id; - l3[++l3_index] = (struct cpuinfo_cache) { - .size = x86_processor.cache.l3.size, - .associativity = x86_processor.cache.l3.associativity, - .sets = x86_processor.cache.l3.sets, - .partitions = x86_processor.cache.l3.partitions, - .line_size = x86_processor.cache.l3.line_size, - .flags = x86_processor.cache.l3.flags, + l3[++l3_index] = (struct cpuinfo_cache){ + .size = x86_processor.cache.l3.size, + .associativity = x86_processor.cache.l3.associativity, + .sets = x86_processor.cache.l3.sets, + .partitions = x86_processor.cache.l3.partitions, + .line_size = x86_processor.cache.l3.line_size, + .flags = x86_processor.cache.l3.flags, .processor_start = processor_index, .processor_count = 1, }; } else { - /* another processor sharing the same cache */ + /* another processor sharing the same + * cache */ l3[l3_index].processor_count += 1; } processors[i].cache.l3 = &l3[l3_index]; @@ -546,18 +594,19 @@ void cpuinfo_x86_linux_init(void) { if (l4_id != last_l4_id) { /* new cache */ last_l4_id = l4_id; - l4[++l4_index] = (struct cpuinfo_cache) { - .size = x86_processor.cache.l4.size, - .associativity = x86_processor.cache.l4.associativity, - .sets = x86_processor.cache.l4.sets, - .partitions = x86_processor.cache.l4.partitions, - .line_size = x86_processor.cache.l4.line_size, - .flags = x86_processor.cache.l4.flags, + l4[++l4_index] = (struct cpuinfo_cache){ + .size = x86_processor.cache.l4.size, + .associativity = x86_processor.cache.l4.associativity, + .sets = x86_processor.cache.l4.sets, + .partitions = x86_processor.cache.l4.partitions, + .line_size = x86_processor.cache.l4.line_size, + .flags = x86_processor.cache.l4.flags, .processor_start = processor_index, .processor_count = 1, }; } else { - /* another processor sharing the same cache */ + /* another processor sharing the same + * cache */ l4[l4_index].processor_count += 1; } processors[i].cache.l4 = &l4[l4_index]; @@ -575,9 +624,9 @@ void cpuinfo_x86_linux_init(void) { cpuinfo_packages = packages; cpuinfo_cache[cpuinfo_cache_level_1i] = l1i; cpuinfo_cache[cpuinfo_cache_level_1d] = l1d; - cpuinfo_cache[cpuinfo_cache_level_2] = l2; - cpuinfo_cache[cpuinfo_cache_level_3] = l3; - cpuinfo_cache[cpuinfo_cache_level_4] = l4; + cpuinfo_cache[cpuinfo_cache_level_2] = l2; + cpuinfo_cache[cpuinfo_cache_level_3] = l3; + cpuinfo_cache[cpuinfo_cache_level_4] = l4; cpuinfo_processors_count = processors_count; cpuinfo_cores_count = cores_count; @@ -585,12 +634,12 @@ void cpuinfo_x86_linux_init(void) { cpuinfo_packages_count = packages_count; cpuinfo_cache_count[cpuinfo_cache_level_1i] = l1i_count; cpuinfo_cache_count[cpuinfo_cache_level_1d] = l1d_count; - cpuinfo_cache_count[cpuinfo_cache_level_2] = l2_count; - cpuinfo_cache_count[cpuinfo_cache_level_3] = l3_count; - cpuinfo_cache_count[cpuinfo_cache_level_4] = l4_count; + cpuinfo_cache_count[cpuinfo_cache_level_2] = l2_count; + cpuinfo_cache_count[cpuinfo_cache_level_3] = l3_count; + cpuinfo_cache_count[cpuinfo_cache_level_4] = l4_count; cpuinfo_max_cache_size = cpuinfo_compute_max_cache_size(&processors[0]); - cpuinfo_global_uarch = (struct cpuinfo_uarch_info) { + cpuinfo_global_uarch = (struct cpuinfo_uarch_info){ .uarch = x86_processor.uarch, .cpuid = x86_processor.cpuid, .processor_count = processors_count, diff --git a/src/x86/mach/init.c b/src/x86/mach/init.c index b44d3adf..b8ea6047 100644 --- a/src/x86/mach/init.c +++ b/src/x86/mach/init.c @@ -3,11 +3,10 @@ #include #include -#include -#include #include #include - +#include +#include static inline uint32_t max(uint32_t a, uint32_t b) { return a > b ? a : b; @@ -31,27 +30,35 @@ void cpuinfo_x86_mach_init(void) { struct cpuinfo_mach_topology mach_topology = cpuinfo_mach_detect_topology(); processors = calloc(mach_topology.threads, sizeof(struct cpuinfo_processor)); if (processors == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" logical processors", - mach_topology.threads * sizeof(struct cpuinfo_processor), mach_topology.threads); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " logical processors", + mach_topology.threads * sizeof(struct cpuinfo_processor), + mach_topology.threads); goto cleanup; } cores = calloc(mach_topology.cores, sizeof(struct cpuinfo_core)); if (cores == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" cores", - mach_topology.cores * sizeof(struct cpuinfo_core), mach_topology.cores); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " cores", + mach_topology.cores * sizeof(struct cpuinfo_core), + mach_topology.cores); goto cleanup; } /* On x86 cluster of cores is a physical package */ clusters = calloc(mach_topology.packages, sizeof(struct cpuinfo_cluster)); if (clusters == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" core clusters", - mach_topology.packages * sizeof(struct cpuinfo_cluster), mach_topology.packages); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " core clusters", + mach_topology.packages * sizeof(struct cpuinfo_cluster), + mach_topology.packages); goto cleanup; } packages = calloc(mach_topology.packages, sizeof(struct cpuinfo_package)); if (packages == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" physical packages", - mach_topology.packages * sizeof(struct cpuinfo_package), mach_topology.packages); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " physical packages", + mach_topology.packages * sizeof(struct cpuinfo_package), + mach_topology.packages); goto cleanup; } @@ -65,7 +72,7 @@ void cpuinfo_x86_mach_init(void) { const uint32_t threads_per_package = mach_topology.threads / mach_topology.packages; const uint32_t cores_per_package = mach_topology.cores / mach_topology.packages; for (uint32_t i = 0; i < mach_topology.packages; i++) { - clusters[i] = (struct cpuinfo_cluster) { + clusters[i] = (struct cpuinfo_cluster){ .processor_start = i * threads_per_package, .processor_count = threads_per_package, .core_start = i * cores_per_package, @@ -85,7 +92,7 @@ void cpuinfo_x86_mach_init(void) { cpuinfo_x86_format_package_name(x86_processor.vendor, brand_string, packages[i].name); } for (uint32_t i = 0; i < mach_topology.cores; i++) { - cores[i] = (struct cpuinfo_core) { + cores[i] = (struct cpuinfo_core){ .processor_start = i * threads_per_core, .processor_count = threads_per_core, .core_id = i % cores_per_package, @@ -103,15 +110,14 @@ void cpuinfo_x86_mach_init(void) { /* Reconstruct APIC IDs from topology components */ const uint32_t thread_bits_mask = bit_mask(x86_processor.topology.thread_bits_length); - const uint32_t core_bits_mask = bit_mask(x86_processor.topology.core_bits_length); - const uint32_t package_bits_offset = max( - x86_processor.topology.thread_bits_offset + x86_processor.topology.thread_bits_length, - x86_processor.topology.core_bits_offset + x86_processor.topology.core_bits_length); - const uint32_t apic_id = - ((smt_id & thread_bits_mask) << x86_processor.topology.thread_bits_offset) | + const uint32_t core_bits_mask = bit_mask(x86_processor.topology.core_bits_length); + const uint32_t package_bits_offset = + max(x86_processor.topology.thread_bits_offset + x86_processor.topology.thread_bits_length, + x86_processor.topology.core_bits_offset + x86_processor.topology.core_bits_length); + const uint32_t apic_id = ((smt_id & thread_bits_mask) << x86_processor.topology.thread_bits_offset) | ((core_id & core_bits_mask) << x86_processor.topology.core_bits_offset) | (package_id << package_bits_offset); - cpuinfo_log_debug("reconstructed APIC ID 0x%08"PRIx32" for thread %"PRIu32, apic_id, i); + cpuinfo_log_debug("reconstructed APIC ID 0x%08" PRIx32 " for thread %" PRIu32, apic_id, i); processors[i].smt_id = smt_id; processors[i].core = cores + i / threads_per_core; @@ -126,11 +132,12 @@ void cpuinfo_x86_mach_init(void) { if (threads_per_l1 == 0) { /* Assume that threads on the same core share L1 */ threads_per_l1 = mach_topology.threads / mach_topology.cores; - cpuinfo_log_warning("Mach kernel did not report number of threads sharing L1 cache; assume %"PRIu32, + cpuinfo_log_warning( + "Mach kernel did not report number of threads sharing L1 cache; assume %" PRIu32, threads_per_l1); } l1_count = mach_topology.threads / threads_per_l1; - cpuinfo_log_debug("detected %"PRIu32" L1 caches", l1_count); + cpuinfo_log_debug("detected %" PRIu32 " L1 caches", l1_count); } uint32_t threads_per_l2 = 0, l2_count = 0; @@ -138,17 +145,20 @@ void cpuinfo_x86_mach_init(void) { threads_per_l2 = mach_topology.threads_per_cache[2]; if (threads_per_l2 == 0) { if (x86_processor.cache.l3.size != 0) { - /* This is not a last-level cache; assume that threads on the same core share L2 */ + /* This is not a last-level cache; assume that + * threads on the same core share L2 */ threads_per_l2 = mach_topology.threads / mach_topology.cores; } else { - /* This is a last-level cache; assume that threads on the same package share L2 */ + /* This is a last-level cache; assume that + * threads on the same package share L2 */ threads_per_l2 = mach_topology.threads / mach_topology.packages; } - cpuinfo_log_warning("Mach kernel did not report number of threads sharing L2 cache; assume %"PRIu32, + cpuinfo_log_warning( + "Mach kernel did not report number of threads sharing L2 cache; assume %" PRIu32, threads_per_l2); } l2_count = mach_topology.threads / threads_per_l2; - cpuinfo_log_debug("detected %"PRIu32" L2 caches", l2_count); + cpuinfo_log_debug("detected %" PRIu32 " L2 caches", l2_count); } uint32_t threads_per_l3 = 0, l3_count = 0; @@ -157,14 +167,16 @@ void cpuinfo_x86_mach_init(void) { if (threads_per_l3 == 0) { /* * Assume that threads on the same package share L3. - * However, is it not necessarily the last-level cache (there may be L4 cache as well) + * However, is it not necessarily the last-level cache + * (there may be L4 cache as well) */ threads_per_l3 = mach_topology.threads / mach_topology.packages; - cpuinfo_log_warning("Mach kernel did not report number of threads sharing L3 cache; assume %"PRIu32, + cpuinfo_log_warning( + "Mach kernel did not report number of threads sharing L3 cache; assume %" PRIu32, threads_per_l3); } l3_count = mach_topology.threads / threads_per_l3; - cpuinfo_log_debug("detected %"PRIu32" L3 caches", l3_count); + cpuinfo_log_debug("detected %" PRIu32 " L3 caches", l3_count); } uint32_t threads_per_l4 = 0, l4_count = 0; @@ -173,32 +185,36 @@ void cpuinfo_x86_mach_init(void) { if (threads_per_l4 == 0) { /* * Assume that all threads share this L4. - * As of now, L4 cache exists only on notebook x86 CPUs, which are single-package, - * but multi-socket systems could have shared L4 (like on IBM POWER8). + * As of now, L4 cache exists only on notebook x86 CPUs, + * which are single-package, but multi-socket systems + * could have shared L4 (like on IBM POWER8). */ threads_per_l4 = mach_topology.threads; - cpuinfo_log_warning("Mach kernel did not report number of threads sharing L4 cache; assume %"PRIu32, + cpuinfo_log_warning( + "Mach kernel did not report number of threads sharing L4 cache; assume %" PRIu32, threads_per_l4); } l4_count = mach_topology.threads / threads_per_l4; - cpuinfo_log_debug("detected %"PRIu32" L4 caches", l4_count); + cpuinfo_log_debug("detected %" PRIu32 " L4 caches", l4_count); } if (x86_processor.cache.l1i.size != 0) { l1i = calloc(l1_count, sizeof(struct cpuinfo_cache)); if (l1i == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L1I caches", - l1_count * sizeof(struct cpuinfo_cache), l1_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L1I caches", + l1_count * sizeof(struct cpuinfo_cache), + l1_count); return; } for (uint32_t c = 0; c < l1_count; c++) { - l1i[c] = (struct cpuinfo_cache) { - .size = x86_processor.cache.l1i.size, - .associativity = x86_processor.cache.l1i.associativity, - .sets = x86_processor.cache.l1i.sets, - .partitions = x86_processor.cache.l1i.partitions, - .line_size = x86_processor.cache.l1i.line_size, - .flags = x86_processor.cache.l1i.flags, + l1i[c] = (struct cpuinfo_cache){ + .size = x86_processor.cache.l1i.size, + .associativity = x86_processor.cache.l1i.associativity, + .sets = x86_processor.cache.l1i.sets, + .partitions = x86_processor.cache.l1i.partitions, + .line_size = x86_processor.cache.l1i.line_size, + .flags = x86_processor.cache.l1i.flags, .processor_start = c * threads_per_l1, .processor_count = threads_per_l1, }; @@ -211,18 +227,20 @@ void cpuinfo_x86_mach_init(void) { if (x86_processor.cache.l1d.size != 0) { l1d = calloc(l1_count, sizeof(struct cpuinfo_cache)); if (l1d == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L1D caches", - l1_count * sizeof(struct cpuinfo_cache), l1_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L1D caches", + l1_count * sizeof(struct cpuinfo_cache), + l1_count); return; } for (uint32_t c = 0; c < l1_count; c++) { - l1d[c] = (struct cpuinfo_cache) { - .size = x86_processor.cache.l1d.size, - .associativity = x86_processor.cache.l1d.associativity, - .sets = x86_processor.cache.l1d.sets, - .partitions = x86_processor.cache.l1d.partitions, - .line_size = x86_processor.cache.l1d.line_size, - .flags = x86_processor.cache.l1d.flags, + l1d[c] = (struct cpuinfo_cache){ + .size = x86_processor.cache.l1d.size, + .associativity = x86_processor.cache.l1d.associativity, + .sets = x86_processor.cache.l1d.sets, + .partitions = x86_processor.cache.l1d.partitions, + .line_size = x86_processor.cache.l1d.line_size, + .flags = x86_processor.cache.l1d.flags, .processor_start = c * threads_per_l1, .processor_count = threads_per_l1, }; @@ -235,18 +253,20 @@ void cpuinfo_x86_mach_init(void) { if (l2_count != 0) { l2 = calloc(l2_count, sizeof(struct cpuinfo_cache)); if (l2 == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L2 caches", - l2_count * sizeof(struct cpuinfo_cache), l2_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L2 caches", + l2_count * sizeof(struct cpuinfo_cache), + l2_count); return; } for (uint32_t c = 0; c < l2_count; c++) { - l2[c] = (struct cpuinfo_cache) { - .size = x86_processor.cache.l2.size, - .associativity = x86_processor.cache.l2.associativity, - .sets = x86_processor.cache.l2.sets, - .partitions = x86_processor.cache.l2.partitions, - .line_size = x86_processor.cache.l2.line_size, - .flags = x86_processor.cache.l2.flags, + l2[c] = (struct cpuinfo_cache){ + .size = x86_processor.cache.l2.size, + .associativity = x86_processor.cache.l2.associativity, + .sets = x86_processor.cache.l2.sets, + .partitions = x86_processor.cache.l2.partitions, + .line_size = x86_processor.cache.l2.line_size, + .flags = x86_processor.cache.l2.flags, .processor_start = c * threads_per_l2, .processor_count = threads_per_l2, }; @@ -259,18 +279,20 @@ void cpuinfo_x86_mach_init(void) { if (l3_count != 0) { l3 = calloc(l3_count, sizeof(struct cpuinfo_cache)); if (l3 == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L3 caches", - l3_count * sizeof(struct cpuinfo_cache), l3_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L3 caches", + l3_count * sizeof(struct cpuinfo_cache), + l3_count); return; } for (uint32_t c = 0; c < l3_count; c++) { - l3[c] = (struct cpuinfo_cache) { - .size = x86_processor.cache.l3.size, - .associativity = x86_processor.cache.l3.associativity, - .sets = x86_processor.cache.l3.sets, - .partitions = x86_processor.cache.l3.partitions, - .line_size = x86_processor.cache.l3.line_size, - .flags = x86_processor.cache.l3.flags, + l3[c] = (struct cpuinfo_cache){ + .size = x86_processor.cache.l3.size, + .associativity = x86_processor.cache.l3.associativity, + .sets = x86_processor.cache.l3.sets, + .partitions = x86_processor.cache.l3.partitions, + .line_size = x86_processor.cache.l3.line_size, + .flags = x86_processor.cache.l3.flags, .processor_start = c * threads_per_l3, .processor_count = threads_per_l3, }; @@ -283,18 +305,20 @@ void cpuinfo_x86_mach_init(void) { if (l4_count != 0) { l4 = calloc(l4_count, sizeof(struct cpuinfo_cache)); if (l4 == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L4 caches", - l4_count * sizeof(struct cpuinfo_cache), l4_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L4 caches", + l4_count * sizeof(struct cpuinfo_cache), + l4_count); return; } for (uint32_t c = 0; c < l4_count; c++) { - l4[c] = (struct cpuinfo_cache) { - .size = x86_processor.cache.l4.size, - .associativity = x86_processor.cache.l4.associativity, - .sets = x86_processor.cache.l4.sets, - .partitions = x86_processor.cache.l4.partitions, - .line_size = x86_processor.cache.l4.line_size, - .flags = x86_processor.cache.l4.flags, + l4[c] = (struct cpuinfo_cache){ + .size = x86_processor.cache.l4.size, + .associativity = x86_processor.cache.l4.associativity, + .sets = x86_processor.cache.l4.sets, + .partitions = x86_processor.cache.l4.partitions, + .line_size = x86_processor.cache.l4.line_size, + .flags = x86_processor.cache.l4.flags, .processor_start = c * threads_per_l4, .processor_count = threads_per_l4, }; @@ -311,9 +335,9 @@ void cpuinfo_x86_mach_init(void) { cpuinfo_packages = packages; cpuinfo_cache[cpuinfo_cache_level_1i] = l1i; cpuinfo_cache[cpuinfo_cache_level_1d] = l1d; - cpuinfo_cache[cpuinfo_cache_level_2] = l2; - cpuinfo_cache[cpuinfo_cache_level_3] = l3; - cpuinfo_cache[cpuinfo_cache_level_4] = l4; + cpuinfo_cache[cpuinfo_cache_level_2] = l2; + cpuinfo_cache[cpuinfo_cache_level_3] = l3; + cpuinfo_cache[cpuinfo_cache_level_4] = l4; cpuinfo_processors_count = mach_topology.threads; cpuinfo_cores_count = mach_topology.cores; @@ -321,12 +345,12 @@ void cpuinfo_x86_mach_init(void) { cpuinfo_packages_count = mach_topology.packages; cpuinfo_cache_count[cpuinfo_cache_level_1i] = l1_count; cpuinfo_cache_count[cpuinfo_cache_level_1d] = l1_count; - cpuinfo_cache_count[cpuinfo_cache_level_2] = l2_count; - cpuinfo_cache_count[cpuinfo_cache_level_3] = l3_count; - cpuinfo_cache_count[cpuinfo_cache_level_4] = l4_count; + cpuinfo_cache_count[cpuinfo_cache_level_2] = l2_count; + cpuinfo_cache_count[cpuinfo_cache_level_3] = l3_count; + cpuinfo_cache_count[cpuinfo_cache_level_4] = l4_count; cpuinfo_max_cache_size = cpuinfo_compute_max_cache_size(&processors[0]); - cpuinfo_global_uarch = (struct cpuinfo_uarch_info) { + cpuinfo_global_uarch = (struct cpuinfo_uarch_info){ .uarch = x86_processor.uarch, .cpuid = x86_processor.cpuid, .processor_count = mach_topology.threads, diff --git a/src/x86/mockcpuid.c b/src/x86/mockcpuid.c index 2631f09b..0eacfa0b 100644 --- a/src/x86/mockcpuid.c +++ b/src/x86/mockcpuid.c @@ -1,13 +1,12 @@ -#include #include +#include #if !CPUINFO_MOCK - #error This file should be built only in mock mode +#error This file should be built only in mock mode #endif #include - static struct cpuinfo_mock_cpuid* cpuinfo_mock_cpuid_data = NULL; static uint32_t cpuinfo_mock_cpuid_entries = 0; static uint32_t cpuinfo_mock_cpuid_leaf4_iteration = 0; @@ -56,8 +55,7 @@ void CPUINFO_ABI cpuinfo_mock_get_cpuidex(uint32_t eax, uint32_t ecx, uint32_t r if (cpuinfo_mock_cpuid_data != NULL && cpuinfo_mock_cpuid_entries != 0) { for (uint32_t i = 0; i < cpuinfo_mock_cpuid_entries; i++) { if (eax == cpuinfo_mock_cpuid_data[i].input_eax && - ecx == cpuinfo_mock_cpuid_data[i].input_ecx) - { + ecx == cpuinfo_mock_cpuid_data[i].input_ecx) { regs[0] = cpuinfo_mock_cpuid_data[i].eax; regs[1] = cpuinfo_mock_cpuid_data[i].ebx; regs[2] = cpuinfo_mock_cpuid_data[i].ecx; diff --git a/src/x86/name.c b/src/x86/name.c index 38c47a34..76f61368 100644 --- a/src/x86/name.c +++ b/src/x86/name.c @@ -1,6 +1,6 @@ #include -#include #include +#include #include #include @@ -8,7 +8,6 @@ #include #include - /* The state of the parser to be preserved between parsing different tokens. */ struct parser_state { /* @@ -17,8 +16,9 @@ struct parser_state { */ char* context_model; /* - * Pointer to the start of the previous token if it is a single-uppercase-letter token. - * NULL if previous token is anything different. + * Pointer to the start of the previous token if it is a + * single-uppercase-letter token. NULL if previous token is anything + * different. */ char* context_upper_letter; /* @@ -27,31 +27,36 @@ struct parser_state { */ char* context_dual; /* - * Pointer to the start of the previous token if it is "Core", "Dual-Core", "QuadCore", etc. - * NULL if previous token is anything different. + * Pointer to the start of the previous token if it is "Core", + * "Dual-Core", "QuadCore", etc. NULL if previous token is anything + * different. */ char* context_core; /* - * Pointer to the start of the previous token if it is "Eng" or "Engineering", etc. - * NULL if previous token is anything different. + * Pointer to the start of the previous token if it is "Eng" or + * "Engineering", etc. NULL if previous token is anything different. */ char* context_engineering; /* - * Pointer to the '@' symbol in the brand string (separates frequency specification). - * NULL if there is no '@' symbol. + * Pointer to the '@' symbol in the brand string (separates frequency + * specification). NULL if there is no '@' symbol. */ char* frequency_separator; - /* Indicates whether the brand string (after transformations) contains frequency. */ + /* Indicates whether the brand string (after transformations) contains + * frequency. */ bool frequency_token; - /* Indicates whether the processor is of Xeon family (contains "Xeon" substring). */ + /* Indicates whether the processor is of Xeon family (contains "Xeon" + * substring). */ bool xeon; /* Indicates whether the processor model number was already parsed. */ bool parsed_model_number; - /* Indicates whether the processor is an engineering sample (contains "Engineering Sample" or "Eng Sample" substrings). */ + /* Indicates whether the processor is an engineering sample (contains + * "Engineering Sample" or "Eng Sample" substrings). */ bool engineering_sample; }; -/** @brief Resets information about the previous token. Keeps all other state information. */ +/** @brief Resets information about the previous token. Keeps all other + * state information. */ static void reset_context(struct parser_state* state) { state->context_model = NULL; state->context_upper_letter = NULL; @@ -60,12 +65,17 @@ static void reset_context(struct parser_state* state) { } /** - * @brief Overwrites the supplied string with space characters if it exactly matches the given string. - * @param string The string to be compared against other string, and erased in case of matching. - * @param length The length of the two string to be compared against each other. + * @brief Overwrites the supplied string with space characters if it + * exactly matches the given string. + * @param string The string to be compared against other string, and + * erased in case of matching. + * @param length The length of the two string to be compared against each + * other. * @param target The string to compare against. - * @retval true If the two strings match and the first supplied string was erased (overwritten with space characters). - * @retval false If the two strings are different and the first supplied string remained unchanged. + * @retval true If the two strings match and the first supplied string + * was erased (overwritten with space characters). + * @retval false If the two strings are different and the first supplied + * string remained unchanged. */ static inline bool erase_matching(char* string, size_t length, const char* target) { const bool match = memcmp(string, target, length) == 0; @@ -76,13 +86,15 @@ static inline bool erase_matching(char* string, size_t length, const char* targe } /** - * @brief Checks if the supplied ASCII character is an uppercase latin letter. + * @brief Checks if the supplied ASCII character is an uppercase latin + * letter. * @param character The character to analyse. - * @retval true If the supplied character is an uppercase latin letter ('A' to 'Z'). + * @retval true If the supplied character is an uppercase latin letter + * ('A' to 'Z'). * @retval false If the supplied character is anything different. */ static inline bool is_upper_letter(char character) { - return (uint32_t) (character - 'A') <= (uint32_t)('Z' - 'A'); + return (uint32_t)(character - 'A') <= (uint32_t)('Z' - 'A'); } /** @@ -92,7 +104,7 @@ static inline bool is_upper_letter(char character) { * @retval false If the supplied character is anything different. */ static inline bool is_digit(char character) { - return (uint32_t) (character - '0') < UINT32_C(10); + return (uint32_t)(character - '0') < UINT32_C(10); } static inline bool is_zero_number(const char* token_start, const char* token_end) { @@ -132,7 +144,7 @@ static inline bool is_model_number(const char* token_start, const char* token_en } static inline bool is_frequency(const char* token_start, const char* token_end) { - const size_t token_length = (size_t) (token_end - token_start); + const size_t token_length = (size_t)(token_end - token_start); if (token_length > 3 && token_end[-2] == 'H' && token_end[-1] == 'z') { switch (token_end[-3]) { case 'K': @@ -148,7 +160,7 @@ static inline bool is_frequency(const char* token_start, const char* token_end) * @warning Input and output tokens can overlap */ static inline char* move_token(const char* token_start, const char* token_end, char* output_ptr) { - const size_t token_length = (size_t) (token_end - token_start); + const size_t token_length = (size_t)(token_end - token_start); memmove(output_ptr, token_start, token_length); return output_ptr + token_length; } @@ -157,7 +169,7 @@ static bool transform_token(char* token_start, char* token_end, struct parser_st const struct parser_state previousState = *state; reset_context(state); - size_t token_length = (size_t) (token_end - token_start); + size_t token_length = (size_t)(token_end - token_start); if (state->frequency_separator != NULL) { if (token_start > state->frequency_separator) { @@ -167,7 +179,6 @@ static bool transform_token(char* token_start, char* token_end, struct parser_st } } - /* Early AMD and Cyrix processors have "tm" suffix for trademark, e.g. * "AMD-K6tm w/ multimedia extensions" * "Cyrix MediaGXtm MMXtm Enhanced" @@ -196,11 +207,13 @@ static bool transform_token(char* token_start, char* token_end, struct parser_st switch (token_length) { case 1: /* - * On some Intel processors there is a space between the first letter of - * the name and the number after it, e.g. - * "Intel(R) Core(TM) i7 CPU X 990 @ 3.47GHz" + * On some Intel processors there is a space between the + * first letter of the name and the number after it, + * e.g. "Intel(R) Core(TM) i7 CPU X 990 @ 3.47GHz" * "Intel(R) Core(TM) CPU Q 820 @ 1.73GHz" - * We want to merge these parts together, in reverse order, i.e. "X 990" -> "990X", "820" -> "820Q" + * We want to merge these parts together, in reverse + * order, i.e. "X 990" + * -> "990X", "820" -> "820Q" */ if (is_upper_letter(token_start[0])) { state->context_upper_letter = token_start; @@ -208,15 +221,17 @@ static bool transform_token(char* token_start, char* token_end, struct parser_st } break; case 2: - /* Erase everything after "w/" in "AMD-K6tm w/ multimedia extensions" */ + /* Erase everything after "w/" in "AMD-K6tm w/ + * multimedia extensions" */ if (erase_matching(token_start, token_length, "w/")) { return false; } /* - * Intel Xeon processors since Ivy Bridge use versions, e.g. - * "Intel Xeon E3-1230 v2" - * Some processor branch strings report them as "V", others report as "v". - * Normalize the former (upper-case) to the latter (lower-case) version + * Intel Xeon processors since Ivy Bridge use versions, + * e.g. "Intel Xeon E3-1230 v2" Some processor branch + * strings report them as "V", others report as + * "v". Normalize the former (upper-case) to the + * latter (lower-case) version */ if (token_start[0] == 'V' && is_digit(token_start[1])) { token_start[0] = 'v'; @@ -234,8 +249,9 @@ static bool transform_token(char* token_start, char* token_end, struct parser_st return true; } /* - * Erase everything after "SOC" on AMD System-on-Chips, e.g. - * "AMD GX-212JC SOC with Radeon(TM) R2E Graphics \0" + * Erase everything after "SOC" on AMD System-on-Chips, + * e.g. "AMD GX-212JC SOC with Radeon(TM) R2E Graphics + * \0" */ if (erase_matching(token_start, token_length, "SOC")) { return false; @@ -258,36 +274,41 @@ static bool transform_token(char* token_start, char* token_end, struct parser_st if (erase_matching(token_start, token_length, "VIA")) { return true; } - /* Erase "IDT" in brand string on early Centaur processors, e.g. "IDT WinChip 2-3D" */ + /* Erase "IDT" in brand string on early Centaur + * processors, e.g. "IDT WinChip 2-3D" */ if (erase_matching(token_start, token_length, "IDT")) { return true; } /* * Erase everything starting with "MMX" in - * "Cyrix MediaGXtm MMXtm Enhanced" ("tm" suffix is removed by this point) + * "Cyrix MediaGXtm MMXtm Enhanced" ("tm" suffix is + * removed by this point) */ if (erase_matching(token_start, token_length, "MMX")) { return false; } /* - * Erase everything starting with "APU" on AMD processors, e.g. - * "AMD A10-4600M APU with Radeon(tm) HD Graphics" - * "AMD A10-7850K APU with Radeon(TM) R7 Graphics" - * "AMD A6-6310 APU with AMD Radeon R4 Graphics" + * Erase everything starting with "APU" on AMD + * processors, e.g. "AMD A10-4600M APU with Radeon(tm) + * HD Graphics" "AMD A10-7850K APU with Radeon(TM) R7 + * Graphics" "AMD A6-6310 APU with AMD Radeon R4 + * Graphics" */ if (erase_matching(token_start, token_length, "APU")) { return false; } /* - * Remember to discard string if it contains "Eng Sample", - * e.g. "Eng Sample, ZD302046W4K43_36/30/20_2/8_A" + * Remember to discard string if it contains "Eng + * Sample", e.g. "Eng Sample, + * ZD302046W4K43_36/30/20_2/8_A" */ if (memcmp(token_start, "Eng", token_length) == 0) { state->context_engineering = token_start; } break; case 4: - /* Remember to erase "Dual Core" in "AMD Athlon(tm) 64 X2 Dual Core Processor 3800+" */ + /* Remember to erase "Dual Core" in "AMD Athlon(tm) 64 + * X2 Dual Core Processor 3800+" */ if (memcmp(token_start, "Dual", token_length) == 0) { state->context_dual = token_start; } @@ -295,10 +316,14 @@ static bool transform_token(char* token_start, char* token_end, struct parser_st if (memcmp(token_start, "Xeon", token_length) == 0) { state->xeon = true; } - /* Erase "Dual Core" in "AMD Athlon(tm) 64 X2 Dual Core Processor 3800+" */ + /* Erase "Dual Core" in "AMD Athlon(tm) 64 X2 Dual Core + * Processor 3800+" + */ if (previousState.context_dual != NULL) { if (memcmp(token_start, "Core", token_length) == 0) { - memset(previousState.context_dual, ' ', (size_t) (token_end - previousState.context_dual)); + memset(previousState.context_dual, + ' ', + (size_t)(token_end - previousState.context_dual)); state->context_core = token_end; return true; } @@ -306,30 +331,32 @@ static bool transform_token(char* token_start, char* token_end, struct parser_st break; case 5: /* - * Erase "Intel" in brand string on Intel processors, e.g. - * "Intel(R) Xeon(R) CPU X3210 @ 2.13GHz" - * "Intel(R) Atom(TM) CPU D2700 @ 2.13GHz" - * "Genuine Intel(R) processor 800MHz" + * Erase "Intel" in brand string on Intel processors, + * e.g. "Intel(R) Xeon(R) CPU X3210 @ 2.13GHz" "Intel(R) + * Atom(TM) CPU D2700 @ 2.13GHz" "Genuine Intel(R) + * processor 800MHz" */ if (erase_matching(token_start, token_length, "Intel")) { return true; } /* - * Erase "Cyrix" in brand string on Cyrix processors, e.g. - * "Cyrix MediaGXtm MMXtm Enhanced" + * Erase "Cyrix" in brand string on Cyrix processors, + * e.g. "Cyrix MediaGXtm MMXtm Enhanced" */ if (erase_matching(token_start, token_length, "Cyrix")) { return true; } /* - * Erase everything following "Geode" (but not "Geode" token itself) on Geode processors, e.g. - * "Geode(TM) Integrated Processor by AMD PCS" - * "Geode(TM) Integrated Processor by National Semi" + * Erase everything following "Geode" (but not "Geode" + * token itself) on Geode processors, e.g. "Geode(TM) + * Integrated Processor by AMD PCS" "Geode(TM) + * Integrated Processor by National Semi" */ if (memcmp(token_start, "Geode", token_length) == 0) { return false; } - /* Remember to erase "model unknown" in "AMD Processor model unknown" */ + /* Remember to erase "model unknown" in "AMD Processor + * model unknown" */ if (memcmp(token_start, "model", token_length) == 0) { state->context_model = token_start; return true; @@ -337,29 +364,33 @@ static bool transform_token(char* token_start, char* token_end, struct parser_st break; case 6: /* - * Erase everything starting with "Radeon" or "RADEON" on AMD APUs, e.g. - * "A8-7670K Radeon R7, 10 Compute Cores 4C+6G" - * "FX-8800P Radeon R7, 12 Compute Cores 4C+8G" - * "A12-9800 RADEON R7, 12 COMPUTE CORES 4C+8G" + * Erase everything starting with "Radeon" or "RADEON" + * on AMD APUs, e.g. "A8-7670K Radeon R7, 10 Compute + * Cores 4C+6G" "FX-8800P Radeon R7, 12 Compute Cores + * 4C+8G" "A12-9800 RADEON R7, 12 COMPUTE CORES 4C+8G" * "A9-9410 RADEON R5, 5 COMPUTE CORES 2C+3G" */ - if (erase_matching(token_start, token_length, "Radeon") || erase_matching(token_start, token_length, "RADEON")) { + if (erase_matching(token_start, token_length, "Radeon") || + erase_matching(token_start, token_length, "RADEON")) { return false; } /* - * Erase "Mobile" when it is not part of the processor name, - * e.g. in "AMD Turion(tm) X2 Ultra Dual-Core Mobile ZM-82" + * Erase "Mobile" when it is not part of the processor + * name, e.g. in "AMD Turion(tm) X2 Ultra Dual-Core + * Mobile ZM-82" */ if (previousState.context_core != NULL) { if (erase_matching(token_start, token_length, "Mobile")) { return true; } } - /* Erase "family" in "Intel(R) Pentium(R) III CPU family 1266MHz" */ + /* Erase "family" in "Intel(R) Pentium(R) III CPU family + * 1266MHz" */ if (erase_matching(token_start, token_length, "family")) { return true; } - /* Discard the string if it contains "Engineering Sample" */ + /* Discard the string if it contains "Engineering + * Sample" */ if (previousState.context_engineering != NULL) { if (memcmp(token_start, "Sample", token_length) == 0) { state->engineering_sample = true; @@ -369,8 +400,8 @@ static bool transform_token(char* token_start, char* token_end, struct parser_st break; case 7: /* - * Erase "Geniune" in brand string on Intel engineering samples, e.g. - * "Genuine Intel(R) processor 800MHz" + * Erase "Geniune" in brand string on Intel engineering + * samples, e.g. "Genuine Intel(R) processor 800MHz" * "Genuine Intel(R) CPU @ 2.13GHz" * "Genuine Intel(R) CPU 0000 @ 1.73GHz" */ @@ -378,45 +409,52 @@ static bool transform_token(char* token_start, char* token_end, struct parser_st return true; } /* - * Erase "12-core" in brand string on AMD Threadripper, e.g. - * "AMD Ryzen Threadripper 1920X 12-Core Processor" + * Erase "12-core" in brand string on AMD Threadripper, + * e.g. "AMD Ryzen Threadripper 1920X 12-Core Processor" */ if (erase_matching(token_start, token_length, "12-Core")) { return true; } /* - * Erase "16-core" in brand string on AMD Threadripper, e.g. - * "AMD Ryzen Threadripper 1950X 16-Core Processor" + * Erase "16-core" in brand string on AMD Threadripper, + * e.g. "AMD Ryzen Threadripper 1950X 16-Core Processor" */ if (erase_matching(token_start, token_length, "16-Core")) { return true; } - /* Erase "model unknown" in "AMD Processor model unknown" */ + /* Erase "model unknown" in "AMD Processor model + * unknown" */ if (previousState.context_model != NULL) { if (memcmp(token_start, "unknown", token_length) == 0) { - memset(previousState.context_model, ' ', token_end - previousState.context_model); + memset(previousState.context_model, + ' ', + token_end - previousState.context_model); return true; } } /* - * Discard the string if it contains "Eng Sample:" or "Eng Sample," e.g. - * "AMD Eng Sample, ZD302046W4K43_36/30/20_2/8_A" - * "AMD Eng Sample: 2D3151A2M88E4_35/31_N" + * Discard the string if it contains "Eng Sample:" or + * "Eng Sample," e.g. "AMD Eng Sample, + * ZD302046W4K43_36/30/20_2/8_A" "AMD Eng Sample: + * 2D3151A2M88E4_35/31_N" */ if (previousState.context_engineering != NULL) { - if (memcmp(token_start, "Sample,", token_length) == 0 || memcmp(token_start, "Sample:", token_length) == 0) { + if (memcmp(token_start, "Sample,", token_length) == 0 || + memcmp(token_start, "Sample:", token_length) == 0) { state->engineering_sample = true; return false; } } break; case 8: - /* Erase "QuadCore" in "VIA QuadCore L4700 @ 1.2+ GHz" */ + /* Erase "QuadCore" in "VIA QuadCore L4700 @ 1.2+ GHz" + */ if (erase_matching(token_start, token_length, "QuadCore")) { state->context_core = token_end; return true; } - /* Erase "Six-Core" in "AMD FX(tm)-6100 Six-Core Processor" */ + /* Erase "Six-Core" in "AMD FX(tm)-6100 Six-Core + * Processor" */ if (erase_matching(token_start, token_length, "Six-Core")) { state->context_core = token_end; return true; @@ -429,7 +467,8 @@ static bool transform_token(char* token_start, char* token_end, struct parser_st if (erase_matching(token_start, token_length, "processor")) { return true; } - /* Erase "Dual-Core" in "Pentium(R) Dual-Core CPU T4200 @ 2.00GHz" */ + /* Erase "Dual-Core" in "Pentium(R) Dual-Core CPU T4200 + * @ 2.00GHz" */ if (erase_matching(token_start, token_length, "Dual-Core")) { state->context_core = token_end; return true; @@ -442,9 +481,9 @@ static bool transform_token(char* token_start, char* token_end, struct parser_st state->context_core = token_end; return true; } - /* Erase "Transmeta" in brand string on Transmeta processors, e.g. - * "Transmeta(tm) Crusoe(tm) Processor TM5800" - * "Transmeta Efficeon(tm) Processor TM8000" + /* Erase "Transmeta" in brand string on Transmeta + * processors, e.g. "Transmeta(tm) Crusoe(tm) Processor + * TM5800" "Transmeta Efficeon(tm) Processor TM8000" */ if (erase_matching(token_start, token_length, "Transmeta")) { return true; @@ -471,8 +510,8 @@ static bool transform_token(char* token_start, char* token_end, struct parser_st return true; } /* - * Remember to discard string if it contains "Engineering Sample", - * e.g. "AMD Engineering Sample" + * Remember to discard string if it contains + * "Engineering Sample", e.g. "AMD Engineering Sample" */ if (memcmp(token_start, "Engineering", token_length) == 0) { state->context_engineering = token_start; @@ -484,31 +523,38 @@ static bool transform_token(char* token_start, char* token_end, struct parser_st memset(token_start, ' ', token_length); return true; } - /* On some Intel processors the last letter of the name is put before the number, - * and an additional space it added, e.g. - * "Intel(R) Core(TM) i7 CPU X 990 @ 3.47GHz" - * "Intel(R) Core(TM) CPU Q 820 @ 1.73GHz" - * "Intel(R) Core(TM) i5 CPU M 480 @ 2.67GHz" - * We fix this issue, i.e. "X 990" -> "990X", "Q 820" -> "820Q" + /* On some Intel processors the last letter of the name is put before + * the number, and an additional space it added, e.g. "Intel(R) Core(TM) + * i7 CPU X 990 @ 3.47GHz" "Intel(R) Core(TM) CPU Q 820 @ 1.73GHz" + * "Intel(R) Core(TM) i5 CPU M 480 @ 2.67GHz" We fix this issue, i.e. + * "X 990" -> "990X", "Q 820" + * -> "820Q" */ if (previousState.context_upper_letter != 0) { - /* A single letter token followed by 2-to-5 digit letter is merged together */ + /* A single letter token followed by 2-to-5 digit letter is + * merged together + */ switch (token_length) { case 2: case 3: case 4: case 5: if (is_number(token_start, token_end)) { - /* Load the previous single-letter token */ + /* Load the previous single-letter token + */ const char letter = *previousState.context_upper_letter; - /* Erase the previous single-letter token */ + /* Erase the previous single-letter + * token */ *previousState.context_upper_letter = ' '; - /* Move the current token one position to the left */ + /* Move the current token one position + * to the left */ move_token(token_start, token_end, token_start - 1); token_start -= 1; /* * Add the letter on the end - * Note: accessing token_start[-1] is safe because this is not the first token + * Note: accessing token_start[-1] is + * safe because this is not the first + * token */ token_end[-1] = letter; } @@ -525,23 +571,22 @@ static bool transform_token(char* token_start, char* token_end, struct parser_st return true; } -uint32_t cpuinfo_x86_normalize_brand_string( - const char raw_name[48], - char normalized_name[48]) -{ +uint32_t cpuinfo_x86_normalize_brand_string(const char raw_name[48], char normalized_name[48]) { normalized_name[0] = '\0'; char name[48]; memcpy(name, raw_name, sizeof(name)); /* * First find the end of the string - * Start search from the end because some brand strings contain zeroes in the middle + * Start search from the end because some brand strings contain zeroes + * in the middle */ char* name_end = &name[48]; while (name_end[-1] == '\0') { /* - * Adject name_end by 1 position and check that we didn't reach the start of the brand string. - * This is possible if all characters are zero. + * Adject name_end by 1 position and check that we didn't reach + * the start of the brand string. This is possible if all + * characters are zero. */ if (--name_end == name) { /* All characters are zeros */ @@ -549,9 +594,10 @@ uint32_t cpuinfo_x86_normalize_brand_string( } } - struct parser_state parser_state = { 0 }; + struct parser_state parser_state = {0}; - /* Now unify all whitespace characters: replace tabs and '\0' with spaces */ + /* Now unify all whitespace characters: replace tabs and '\0' with + * spaces */ { bool inside_parentheses = false; for (char* char_ptr = name; char_ptr != name_end; char_ptr++) { @@ -611,7 +657,8 @@ uint32_t cpuinfo_x86_normalize_brand_string( /* Check if there is some string before the frequency separator. */ if (parser_state.frequency_separator != NULL) { if (is_space(name, parser_state.frequency_separator)) { - /* If only frequency is available, return empty string */ + /* If only frequency is available, return empty string + */ return 0; } } @@ -634,7 +681,8 @@ uint32_t cpuinfo_x86_normalize_brand_string( *output_ptr++ = ' '; } output_ptr = move_token(token_start, char_ptr, output_ptr); - /* Note: char_ptr[-1] exists because there is a token before this space */ + /* Note: char_ptr[-1] exists because + * there is a token before this space */ previous_token_ends_with_dash = (char_ptr[-1] == '-'); } } else { @@ -662,7 +710,7 @@ uint32_t cpuinfo_x86_normalize_brand_string( } else { normalized_name[47] = '\0'; } - return (uint32_t) (output_ptr - normalized_name); + return (uint32_t)(output_ptr - normalized_name); } } @@ -685,24 +733,22 @@ static const char* vendor_string_map[] = { uint32_t cpuinfo_x86_format_package_name( enum cpuinfo_vendor vendor, const char normalized_brand_string[48], - char package_name[CPUINFO_PACKAGE_NAME_MAX]) -{ + char package_name[CPUINFO_PACKAGE_NAME_MAX]) { if (normalized_brand_string[0] == '\0') { package_name[0] = '\0'; return 0; } const char* vendor_string = NULL; - if ((uint32_t) vendor < (uint32_t) CPUINFO_COUNT_OF(vendor_string_map)) { - vendor_string = vendor_string_map[(uint32_t) vendor]; + if ((uint32_t)vendor < (uint32_t)CPUINFO_COUNT_OF(vendor_string_map)) { + vendor_string = vendor_string_map[(uint32_t)vendor]; } if (vendor_string == NULL) { strncpy(package_name, normalized_brand_string, CPUINFO_PACKAGE_NAME_MAX); package_name[CPUINFO_PACKAGE_NAME_MAX - 1] = '\0'; return 0; } else { - snprintf(package_name, CPUINFO_PACKAGE_NAME_MAX, - "%s %s", vendor_string, normalized_brand_string); - return (uint32_t) strlen(vendor_string) + 1; + snprintf(package_name, CPUINFO_PACKAGE_NAME_MAX, "%s %s", vendor_string, normalized_brand_string); + return (uint32_t)strlen(vendor_string) + 1; } } diff --git a/src/x86/topology.c b/src/x86/topology.c index 0e83d468..52530892 100644 --- a/src/x86/topology.c +++ b/src/x86/topology.c @@ -1,25 +1,23 @@ -#include #include +#include #include -#include #include +#include #include #include - enum topology_type { topology_type_invalid = 0, - topology_type_smt = 1, - topology_type_core = 2, + topology_type_smt = 1, + topology_type_core = 2, }; void cpuinfo_x86_detect_topology( uint32_t max_base_index, uint32_t max_extended_index, struct cpuid_regs leaf1, - struct cpuinfo_x86_topology* topology) -{ + struct cpuinfo_x86_topology* topology) { /* * HTT: indicates multi-core/hyper-threading support on this core. * - Intel, AMD: edx[bit 28] in basic info. @@ -34,7 +32,8 @@ void cpuinfo_x86_detect_topology( const struct cpuid_regs leaf0x80000001 = cpuid(UINT32_C(0x80000001)); /* * CmpLegacy: core multi-processing legacy mode. - * - AMD: ecx[bit 1] in extended info (reserved bit on Intel CPUs). + * - AMD: ecx[bit 1] in extended info (reserved bit on + * Intel CPUs). */ amd_cmp_legacy = !!(leaf0x80000001.ecx & UINT32_C(0x00000002)); } @@ -42,36 +41,52 @@ void cpuinfo_x86_detect_topology( if (max_extended_index >= UINT32_C(0x80000008)) { const struct cpuid_regs leaf0x80000008 = cpuid(UINT32_C(0x80000008)); /* - * NC: number of physical cores - 1. The number of cores in the processor is NC+1. - * - AMD: ecx[bits 0-7] in leaf 0x80000008 (reserved zero bits on Intel CPUs). + * NC: number of physical cores - 1. The number + * of cores in the processor is NC+1. + * - AMD: ecx[bits 0-7] in leaf 0x80000008 + * (reserved zero bits on Intel CPUs). */ const uint32_t cores_per_processor = 1 + (leaf0x80000008.ecx & UINT32_C(0x000000FF)); topology->core_bits_length = bit_length(cores_per_processor); - cpuinfo_log_debug("HTT: APIC ID = %08"PRIx32", cores per processor = %"PRIu32, apic_id, cores_per_processor); + cpuinfo_log_debug( + "HTT: APIC ID = %08" PRIx32 ", cores per processor = %" PRIu32, + apic_id, + cores_per_processor); } else { /* - * LogicalProcessorCount: the number of cores per processor. - * - AMD: ebx[bits 16-23] in basic info (different interpretation on Intel CPUs). + * LogicalProcessorCount: the number of cores + * per processor. + * - AMD: ebx[bits 16-23] in basic info + * (different interpretation on Intel CPUs). */ const uint32_t cores_per_processor = (leaf1.ebx >> 16) & UINT32_C(0x000000FF); if (cores_per_processor != 0) { topology->core_bits_length = bit_length(cores_per_processor); } - cpuinfo_log_debug("HTT: APIC ID = %08"PRIx32", cores per processor = %"PRIu32, apic_id, cores_per_processor); + cpuinfo_log_debug( + "HTT: APIC ID = %08" PRIx32 ", cores per processor = %" PRIu32, + apic_id, + cores_per_processor); } } else { /* - * Maximum number of addressable IDs for logical processors in this physical package. - * - Intel: ebx[bits 16-23] in basic info (different interpretation on AMD CPUs). + * Maximum number of addressable IDs for logical + * processors in this physical package. + * - Intel: ebx[bits 16-23] in basic info (different + * interpretation on AMD CPUs). */ const uint32_t logical_processors = (leaf1.ebx >> 16) & UINT32_C(0x000000FF); if (logical_processors != 0) { const uint32_t log2_max_logical_processors = bit_length(logical_processors); - const uint32_t log2_max_threads_per_core = log2_max_logical_processors - topology->core_bits_length; + const uint32_t log2_max_threads_per_core = + log2_max_logical_processors - topology->core_bits_length; topology->core_bits_offset = log2_max_threads_per_core; topology->thread_bits_length = log2_max_threads_per_core; } - cpuinfo_log_debug("HTT: APIC ID = %08"PRIx32", logical processors = %"PRIu32, apic_id, logical_processors); + cpuinfo_log_debug( + "HTT: APIC ID = %08" PRIx32 ", logical processors = %" PRIu32, + apic_id, + logical_processors); } } @@ -84,43 +99,64 @@ void cpuinfo_x86_detect_topology( uint32_t level = 0; uint32_t type; uint32_t total_shift = 0; - topology->thread_bits_offset = topology->thread_bits_length = 0; - topology->core_bits_offset = topology->core_bits_length = 0; + topology->thread_bits_offset = topology->thread_bits_length = 0; + topology->core_bits_offset = topology->core_bits_length = 0; do { const struct cpuid_regs leafB = cpuidex(UINT32_C(0xB), level); type = (leafB.ecx >> 8) & UINT32_C(0x000000FF); const uint32_t level_shift = leafB.eax & UINT32_C(0x0000001F); - const uint32_t x2apic_id = leafB.edx; + const uint32_t x2apic_id = leafB.edx; apic_id = x2apic_id; switch (type) { case topology_type_invalid: break; case topology_type_smt: - cpuinfo_log_debug("x2 level %"PRIu32": APIC ID = %08"PRIx32", " - "type SMT, shift %"PRIu32", total shift %"PRIu32, - level, apic_id, level_shift, total_shift); + cpuinfo_log_debug( + "x2 level %" PRIu32 ": APIC ID = %08" PRIx32 + ", " + "type SMT, shift %" PRIu32 ", total shift %" PRIu32, + level, + apic_id, + level_shift, + total_shift); topology->thread_bits_offset = total_shift; topology->thread_bits_length = level_shift; break; case topology_type_core: - cpuinfo_log_debug("x2 level %"PRIu32": APIC ID = %08"PRIx32", " - "type core, shift %"PRIu32", total shift %"PRIu32, - level, apic_id, level_shift, total_shift); + cpuinfo_log_debug( + "x2 level %" PRIu32 ": APIC ID = %08" PRIx32 + ", " + "type core, shift %" PRIu32 ", total shift %" PRIu32, + level, + apic_id, + level_shift, + total_shift); topology->core_bits_offset = total_shift; topology->core_bits_length = level_shift; break; default: - cpuinfo_log_warning("unexpected topology type %"PRIu32" (offset %"PRIu32", length %"PRIu32") " - "reported in leaf 0x0000000B is ignored", type, total_shift, level_shift); + cpuinfo_log_warning( + "unexpected topology type %" PRIu32 " (offset %" PRIu32 + ", length %" PRIu32 + ") " + "reported in leaf 0x0000000B is ignored", + type, + total_shift, + level_shift); break; } total_shift += level_shift; level += 1; } while (type != 0); - cpuinfo_log_debug("x2APIC ID 0x%08"PRIx32", " - "SMT offset %"PRIu32" length %"PRIu32", core offset %"PRIu32" length %"PRIu32, apic_id, - topology->thread_bits_offset, topology->thread_bits_length, - topology->core_bits_offset, topology->core_bits_length); + cpuinfo_log_debug( + "x2APIC ID 0x%08" PRIx32 + ", " + "SMT offset %" PRIu32 " length %" PRIu32 ", core offset %" PRIu32 " length %" PRIu32, + apic_id, + topology->thread_bits_offset, + topology->thread_bits_length, + topology->core_bits_offset, + topology->core_bits_length); } topology->apic_id = apic_id; diff --git a/src/x86/uarch.c b/src/x86/uarch.c index a38d7b05..b291ebcf 100644 --- a/src/x86/uarch.c +++ b/src/x86/uarch.c @@ -3,11 +3,9 @@ #include #include - enum cpuinfo_uarch cpuinfo_x86_decode_uarch( enum cpuinfo_vendor vendor, - const struct cpuinfo_x86_model_info* model_info) -{ + const struct cpuinfo_x86_model_info* model_info) { switch (vendor) { case cpuinfo_vendor_intel: switch (model_info->family) { @@ -15,8 +13,12 @@ enum cpuinfo_uarch cpuinfo_x86_decode_uarch( case 0x05: switch (model_info->model) { case 0x01: // Pentium (60, 66) - case 0x02: // Pentium (75, 90, 100, 120, 133, 150, 166, 200) - case 0x03: // Pentium OverDrive for Intel486-based systems + case 0x02: // Pentium (75, 90, + // 100, 120, 133, + // 150, 166, 200) + case 0x03: // Pentium OverDrive + // for Intel486-based + // systems case 0x04: // Pentium MMX return cpuinfo_uarch_p5; case 0x09: @@ -29,39 +31,109 @@ enum cpuinfo_uarch cpuinfo_x86_decode_uarch( /* Mainstream cores */ #if CPUINFO_ARCH_X86 case 0x01: // Pentium Pro - case 0x03: // Pentium II (Klamath) and Pentium II Overdrive - case 0x05: // Pentium II (Deschutes, Tonga), Pentium II Celeron (Covington), Pentium II Xeon (Drake) - case 0x06: // Pentium II (Dixon), Pentium II Celeron (Mendocino) - case 0x07: // Pentium III (Katmai), Pentium III Xeon (Tanner) - case 0x08: // Pentium III (Coppermine), Pentium II Celeron (Coppermine-128), Pentium III Xeon (Cascades) - case 0x0A: // Pentium III Xeon (Cascades-2MB) - case 0x0B: // Pentium III (Tualatin), Pentium III Celeron (Tualatin-256) + case 0x03: // Pentium II + // (Klamath) and + // Pentium II + // Overdrive + case 0x05: // Pentium II + // (Deschutes, + // Tonga), Pentium II + // Celeron + // (Covington), + // Pentium II Xeon + // (Drake) + case 0x06: // Pentium II + // (Dixon), Pentium + // II Celeron + // (Mendocino) + case 0x07: // Pentium III + // (Katmai), Pentium + // III Xeon (Tanner) + case 0x08: // Pentium III + // (Coppermine), + // Pentium II Celeron + // (Coppermine-128), + // Pentium III Xeon + // (Cascades) + case 0x0A: // Pentium III Xeon + // (Cascades-2MB) + case 0x0B: // Pentium III + // (Tualatin), + // Pentium III + // Celeron + // (Tualatin-256) return cpuinfo_uarch_p6; - case 0x09: // Pentium M (Banias), Pentium M Celeron (Banias-0, Banias-512) - case 0x0D: // Pentium M (Dothan), Pentium M Celeron (Dothan-512, Dothan-1024) - case 0x15: // Intel 80579 (Tolapai) + case 0x09: // Pentium M + // (Banias), Pentium + // M Celeron + // (Banias-0, + // Banias-512) + case 0x0D: // Pentium M + // (Dothan), Pentium + // M Celeron + // (Dothan-512, + // Dothan-1024) + case 0x15: // Intel 80579 + // (Tolapai) return cpuinfo_uarch_dothan; - case 0x0E: // Core Solo/Duo (Yonah), Pentium Dual-Core T2xxx (Yonah), Celeron M (Yonah-512, Yonah-1024), Dual-Core Xeon (Sossaman) + case 0x0E: // Core Solo/Duo + // (Yonah), Pentium + // Dual-Core T2xxx + // (Yonah), Celeron M + // (Yonah-512, + // Yonah-1024), + // Dual-Core Xeon + // (Sossaman) return cpuinfo_uarch_yonah; #endif /* CPUINFO_ARCH_X86 */ - case 0x0F: // Core 2 Duo (Conroe, Conroe-2M, Merom), Core 2 Quad (Tigerton), Xeon (Woodcrest, Clovertown, Kentsfield) - case 0x16: // Celeron (Conroe-L, Merom-L), Core 2 Duo (Merom) + case 0x0F: // Core 2 Duo + // (Conroe, + // Conroe-2M, Merom), + // Core 2 Quad + // (Tigerton), Xeon + // (Woodcrest, + // Clovertown, + // Kentsfield) + case 0x16: // Celeron (Conroe-L, + // Merom-L), Core 2 + // Duo (Merom) return cpuinfo_uarch_conroe; - case 0x17: // Core 2 Duo (Penryn-3M), Core 2 Quad (Yorkfield), Core 2 Extreme (Yorkfield), Xeon (Harpertown), Pentium Dual-Core (Penryn) + case 0x17: // Core 2 Duo + // (Penryn-3M), Core + // 2 Quad + // (Yorkfield), Core + // 2 Extreme + // (Yorkfield), Xeon + // (Harpertown), + // Pentium Dual-Core + // (Penryn) case 0x1D: // Xeon (Dunnington) return cpuinfo_uarch_penryn; - case 0x1A: // Core iX (Bloomfield), Xeon (Gainestown) - case 0x1E: // Core iX (Lynnfield, Clarksfield) - case 0x1F: // Core iX (Havendale) + case 0x1A: // Core iX + // (Bloomfield), Xeon + // (Gainestown) + case 0x1E: // Core iX + // (Lynnfield, + // Clarksfield) + case 0x1F: // Core iX + // (Havendale) case 0x2E: // Xeon (Beckton) - case 0x25: // Core iX (Clarkdale) - case 0x2C: // Core iX (Gulftown), Xeon (Gulftown) + case 0x25: // Core iX + // (Clarkdale) + case 0x2C: // Core iX + // (Gulftown), Xeon + // (Gulftown) case 0x2F: // Xeon (Eagleton) return cpuinfo_uarch_nehalem; - case 0x2A: // Core iX (Sandy Bridge) - case 0x2D: // Core iX (Sandy Bridge-E), Xeon (Sandy Bridge EP/EX) + case 0x2A: // Core iX (Sandy + // Bridge) + case 0x2D: // Core iX (Sandy + // Bridge-E), Xeon + // (Sandy Bridge + // EP/EX) return cpuinfo_uarch_sandy_bridge; - case 0x3A: // Core iX (Ivy Bridge) + case 0x3A: // Core iX (Ivy + // Bridge) case 0x3E: // Ivy Bridge-E return cpuinfo_uarch_ivy_bridge; case 0x3C: @@ -74,15 +146,21 @@ enum cpuinfo_uarch cpuinfo_x86_decode_uarch( case 0x4F: // Broadwell-E case 0x56: // Broadwell-DE return cpuinfo_uarch_broadwell; - case 0x4E: // Sky Lake Client Y/U - case 0x55: // Sky/Cascade/Cooper Lake Server - case 0x5E: // Sky Lake Client DT/H/S - case 0x8E: // Kaby/Whiskey/Amber/Comet Lake Y/U - case 0x9E: // Kaby/Coffee Lake DT/H/S + case 0x4E: // Sky Lake Client + // Y/U + case 0x55: // Sky/Cascade/Cooper + // Lake Server + case 0x5E: // Sky Lake Client + // DT/H/S + case 0x8E: // Kaby/Whiskey/Amber/Comet + // Lake Y/U + case 0x9E: // Kaby/Coffee Lake + // DT/H/S case 0xA5: // Comet Lake H/S case 0xA6: // Comet Lake U/Y return cpuinfo_uarch_sky_lake; - case 0x66: // Cannon Lake (Core i3-8121U) + case 0x66: // Cannon Lake (Core + // i3-8121U) return cpuinfo_uarch_palm_cove; case 0x6A: // Ice Lake-DE case 0x6C: // Ice Lake-SP @@ -91,12 +169,15 @@ enum cpuinfo_uarch cpuinfo_x86_decode_uarch( return cpuinfo_uarch_sunny_cove; /* Low-power cores */ - case 0x1C: // Diamondville, Silverthorne, Pineview + case 0x1C: // Diamondville, + // Silverthorne, + // Pineview case 0x26: // Tunnel Creek return cpuinfo_uarch_bonnell; case 0x27: // Medfield case 0x35: // Cloverview - case 0x36: // Cedarview, Centerton + case 0x36: // Cedarview, + // Centerton return cpuinfo_uarch_saltwell; case 0x37: // Bay Trail case 0x4A: // Merrifield @@ -104,8 +185,10 @@ enum cpuinfo_uarch cpuinfo_x86_decode_uarch( case 0x5A: // Moorefield case 0x5D: // SoFIA return cpuinfo_uarch_silvermont; - case 0x4C: // Braswell, Cherry Trail - case 0x75: // Spreadtrum SC9853I-IA + case 0x4C: // Braswell, Cherry + // Trail + case 0x75: // Spreadtrum + // SC9853I-IA return cpuinfo_uarch_airmont; case 0x5C: // Apollo Lake case 0x5F: // Denverton @@ -122,14 +205,48 @@ enum cpuinfo_uarch cpuinfo_x86_decode_uarch( break; case 0x0F: switch (model_info->model) { - case 0x00: // Pentium 4 Xeon (Foster) - case 0x01: // Pentium 4 Celeron (Willamette-128), Pentium 4 Xeon (Foster, Foster MP) - case 0x02: // Pentium 4 (Northwood), Pentium 4 EE (Gallatin), Pentium 4 Celeron (Northwood-128, Northwood-256), Pentium 4 Xeon (Gallatin DP, Prestonia) + case 0x00: // Pentium 4 Xeon + // (Foster) + case 0x01: // Pentium 4 Celeron + // (Willamette-128), + // Pentium 4 Xeon + // (Foster, Foster + // MP) + case 0x02: // Pentium 4 + // (Northwood), + // Pentium 4 EE + // (Gallatin), + // Pentium 4 Celeron + // (Northwood-128, + // Northwood-256), + // Pentium 4 Xeon + // (Gallatin DP, + // Prestonia) return cpuinfo_uarch_willamette; break; - case 0x03: // Pentium 4 (Prescott), Pentium 4 Xeon (Nocona) - case 0x04: // Pentium 4 (Prescott-2M), Pentium 4 EE (Prescott-2M), Pentium D (Smithfield), Celeron D (Prescott-256), Pentium 4 Xeon (Cranford, Irwindale, Paxville) - case 0x06: // Pentium 4 (Cedar Mill), Pentium D EE (Presler), Celeron D (Cedar Mill), Pentium 4 Xeon (Dempsey, Tulsa) + case 0x03: // Pentium 4 + // (Prescott), + // Pentium 4 Xeon + // (Nocona) + case 0x04: // Pentium 4 + // (Prescott-2M), + // Pentium 4 EE + // (Prescott-2M), + // Pentium D + // (Smithfield), + // Celeron D + // (Prescott-256), + // Pentium 4 Xeon + // (Cranford, + // Irwindale, + // Paxville) + case 0x06: // Pentium 4 (Cedar + // Mill), Pentium D + // EE (Presler), + // Celeron D (Cedar + // Mill), Pentium 4 + // Xeon (Dempsey, + // Tulsa) return cpuinfo_uarch_prescott; } break; @@ -166,8 +283,10 @@ enum cpuinfo_uarch cpuinfo_x86_decode_uarch( return cpuinfo_uarch_bobcat; case 0x15: switch (model_info->model) { - case 0x00: // Engineering samples - case 0x01: // Zambezi, Interlagos + case 0x00: // Engineering + // samples + case 0x01: // Zambezi, + // Interlagos return cpuinfo_uarch_bulldozer; case 0x02: // Vishera case 0x10: // Trinity @@ -184,11 +303,19 @@ enum cpuinfo_uarch cpuinfo_x86_decode_uarch( switch (model_info->extended_model) { case 0x0: return cpuinfo_uarch_bulldozer; - case 0x1: // No L3 cache - case 0x2: // With L3 cache + case 0x1: // No + // L3 + // cache + case 0x2: // With + // L3 + // cache return cpuinfo_uarch_piledriver; - case 0x3: // With L3 cache - case 0x4: // No L3 cache + case 0x3: // With + // L3 + // cache + case 0x4: // No + // L3 + // cache return cpuinfo_uarch_steamroller; } break; @@ -202,29 +329,61 @@ enum cpuinfo_uarch cpuinfo_x86_decode_uarch( } case 0x17: switch (model_info->extended_model) { - case 0x0: // model 01h -> 14 nm Naples/Whitehaven/Summit Ridge/Snowy Owl, model 08h -> 12 nm Colfax/Pinnacle Ridge - case 0x1: // model 11h -> 14 nm Raven Ridge/Great Horned Owl, model 18h -> 14 nm Banded Kestrel / 12 nm Picasso + case 0x0: // model 01h -> 14 nm + // Naples/Whitehaven/Summit + // Ridge/Snowy Owl, + // model 08h -> 12 nm + // Colfax/Pinnacle + // Ridge + case 0x1: // model 11h -> 14 nm + // Raven Ridge/Great + // Horned Owl, model + // 18h -> 14 nm Banded + // Kestrel / 12 nm + // Picasso return cpuinfo_uarch_zen; - case 0x3: // model 31h -> Rome/Castle Peak - case 0x4: // model 47h -> Xbox Series X - case 0x6: // model 60h -> Renoir/Grey Hawk, model 68h -> Lucienne - case 0x7: // model 71h -> Matisse - case 0x9: // model 90h -> Van Gogh, model 98h -> Mero + case 0x3: // model 31h -> + // Rome/Castle Peak + case 0x4: // model 47h -> Xbox + // Series X + case 0x6: // model 60h -> + // Renoir/Grey Hawk, + // model 68h -> + // Lucienne + case 0x7: // model 71h -> + // Matisse + case 0x9: // model 90h -> Van + // Gogh, model 98h -> + // Mero return cpuinfo_uarch_zen2; } break; case 0x19: switch (model_info->extended_model) { - case 0x0: // model 00h -> Genesis, model 01h -> Milan, model 08h -> Chagall - case 0x2: // model 21h -> Vermeer - case 0x3: // model 30h -> Badami, Trento - case 0x4: // model 40h -> Rembrandt - case 0x5: // model 50h -> Cezanne + case 0x0: // model 00h -> + // Genesis, model 01h + // -> Milan, model 08h + // -> Chagall + case 0x2: // model 21h -> + // Vermeer + case 0x3: // model 30h -> + // Badami, Trento + case 0x4: // model 40h -> + // Rembrandt + case 0x5: // model 50h -> + // Cezanne return cpuinfo_uarch_zen3; - case 0x1: // model 10h..1Fh -> Stones - case 0x6: // model 60h..6Fh -> Raphael - case 0x7: // model 70h..77h -> Phoenix/Hawkpoint1, model 78h..7Fh -> Phoenix 2/Hawkpoint2 - case 0xA: // model A0h..AFh -> Stones-Dense + case 0x1: // model 10h..1Fh -> + // Stones + case 0x6: // model 60h..6Fh -> + // Raphael + case 0x7: // model 70h..77h -> + // Phoenix/Hawkpoint1, + // model 78h..7Fh -> + // Phoenix + // 2/Hawkpoint2 + case 0xA: // model A0h..AFh -> + // Stones-Dense return cpuinfo_uarch_zen4; } break; diff --git a/src/x86/vendor.c b/src/x86/vendor.c index bad50fa9..eaccef5c 100644 --- a/src/x86/vendor.c +++ b/src/x86/vendor.c @@ -3,7 +3,6 @@ #include #include - /* Intel vendor string: "GenuineIntel" */ #define Genu UINT32_C(0x756E6547) #define ineI UINT32_C(0x49656E69) @@ -15,8 +14,8 @@ #define cAMD UINT32_C(0x444D4163) #define AMDi UINT32_C(0x69444D41) #define sbet UINT32_C(0x74656273) -#define ter UINT32_C(0x21726574) -#define AMD UINT32_C(0x20444D41) +#define ter UINT32_C(0x21726574) +#define AMD UINT32_C(0x20444D41) #define ISBE UINT32_C(0x45425349) #define TTER UINT32_C(0x52455454) @@ -24,7 +23,7 @@ #define Cent UINT32_C(0x746E6543) #define aurH UINT32_C(0x48727561) #define auls UINT32_C(0x736C7561) -#define VIA UINT32_C(0x20414956) +#define VIA UINT32_C(0x20414956) /* Hygon vendor string: "HygonGenuine" */ #define Hygo UINT32_C(0x6F677948) @@ -49,10 +48,10 @@ /* NSC vendor string: "Geode by NSC" */ #define Geod UINT32_C(0x646F6547) #define e_by UINT32_C(0x79622065) -#define NSC UINT32_C(0x43534E20) +#define NSC UINT32_C(0x43534E20) /* SiS vendor string: "SiS SiS SiS " */ -#define SiS UINT32_C(0x20536953) +#define SiS UINT32_C(0x20536953) /* NexGen vendor string: "NexGenDriven" */ #define NexG UINT32_C(0x4778654E) @@ -60,17 +59,16 @@ #define iven UINT32_C(0x6E657669) /* UMC vendor string: "UMC UMC UMC " */ -#define UMC UINT32_C(0x20434D55) +#define UMC UINT32_C(0x20434D55) /* RDC vendor string: "Genuine RDC" */ -#define ine UINT32_C(0x20656E69) -#define RDC UINT32_C(0x43445220) +#define ine UINT32_C(0x20656E69) +#define RDC UINT32_C(0x43445220) /* D&MP vendor string: "Vortex86 SoC" */ #define Vort UINT32_C(0x74726F56) #define ex86 UINT32_C(0x36387865) -#define SoC UINT32_C(0x436F5320) - +#define SoC UINT32_C(0x436F5320) enum cpuinfo_vendor cpuinfo_x86_decode_vendor(uint32_t ebx, uint32_t ecx, uint32_t edx) { switch (ebx) { diff --git a/src/x86/windows/api.h b/src/x86/windows/api.h index 33d917e0..4f6df0f0 100644 --- a/src/x86/windows/api.h +++ b/src/x86/windows/api.h @@ -9,15 +9,17 @@ struct cpuinfo_arm_linux_processor { /** - * Minimum processor ID on the package which includes this logical processor. - * This value can serve as an ID for the cluster of logical processors: it is the - * same for all logical processors on the same package. + * Minimum processor ID on the package which includes this logical + * processor. This value can serve as an ID for the cluster of logical + * processors: it is the same for all logical processors on the same + * package. */ uint32_t package_leader_id; /** - * Minimum processor ID on the core which includes this logical processor. - * This value can serve as an ID for the cluster of logical processors: it is the - * same for all logical processors on the same package. + * Minimum processor ID on the core which includes this logical + * processor. This value can serve as an ID for the cluster of logical + * processors: it is the same for all logical processors on the same + * package. */ /** * Number of logical processors in the package. @@ -25,14 +27,16 @@ struct cpuinfo_arm_linux_processor { uint32_t package_processor_count; /** * Maximum frequency, in kHZ. - * The value is parsed from /sys/devices/system/cpu/cpu/cpufreq/cpuinfo_max_freq - * If failed to read or parse the file, the value is 0. + * The value is parsed from + * /sys/devices/system/cpu/cpu/cpufreq/cpuinfo_max_freq If failed to + * read or parse the file, the value is 0. */ uint32_t max_frequency; /** * Minimum frequency, in kHZ. - * The value is parsed from /sys/devices/system/cpu/cpu/cpufreq/cpuinfo_min_freq - * If failed to read or parse the file, the value is 0. + * The value is parsed from + * /sys/devices/system/cpu/cpu/cpufreq/cpuinfo_min_freq If failed to + * read or parse the file, the value is 0. */ uint32_t min_frequency; /** Linux processor ID */ diff --git a/src/x86/windows/init.c b/src/x86/windows/init.c index 274075c0..d2332802 100644 --- a/src/x86/windows/init.c +++ b/src/x86/windows/init.c @@ -1,38 +1,37 @@ -#include #include +#include #include #include #include -#include #include #include +#include #include #ifdef __GNUC__ - #define CPUINFO_ALLOCA __builtin_alloca +#define CPUINFO_ALLOCA __builtin_alloca #else - #define CPUINFO_ALLOCA _alloca +#define CPUINFO_ALLOCA _alloca #endif - static inline uint32_t bit_mask(uint32_t bits) { return (UINT32_C(1) << bits) - UINT32_C(1); } static inline uint32_t low_index_from_kaffinity(KAFFINITY kaffinity) { - #if defined(_M_X64) || defined(_M_AMD64) - unsigned long index; - _BitScanForward64(&index, (unsigned __int64) kaffinity); - return (uint32_t) index; - #elif defined(_M_IX86) - unsigned long index; - _BitScanForward(&index, (unsigned long) kaffinity); - return (uint32_t) index; - #else - #error Platform-specific implementation required - #endif +#if defined(_M_X64) || defined(_M_AMD64) + unsigned long index; + _BitScanForward64(&index, (unsigned __int64)kaffinity); + return (uint32_t)index; +#elif defined(_M_IX86) + unsigned long index; + _BitScanForward(&index, (unsigned long)kaffinity); + return (uint32_t)index; +#else +#error Platform-specific implementation required +#endif } static void cpuinfo_x86_count_caches( @@ -43,14 +42,13 @@ static void cpuinfo_x86_count_caches( uint32_t* l1d_count_ptr, uint32_t* l2_count_ptr, uint32_t* l3_count_ptr, - uint32_t* l4_count_ptr) -{ + uint32_t* l4_count_ptr) { uint32_t l1i_count = 0, l1d_count = 0, l2_count = 0, l3_count = 0, l4_count = 0; uint32_t last_l1i_id = UINT32_MAX, last_l1d_id = UINT32_MAX; uint32_t last_l2_id = UINT32_MAX, last_l3_id = UINT32_MAX, last_l4_id = UINT32_MAX; for (uint32_t i = 0; i < processors_count; i++) { const uint32_t apic_id = processors[i].apic_id; - cpuinfo_log_debug("APID ID %"PRIu32": logical processor %"PRIu32, apic_id, i); + cpuinfo_log_debug("APID ID %" PRIu32 ": logical processor %" PRIu32, apic_id, i); if (x86_processor->cache.l1i.size != 0) { const uint32_t l1i_id = apic_id & ~bit_mask(x86_processor->cache.l1i.apic_bits); @@ -90,9 +88,9 @@ static void cpuinfo_x86_count_caches( } *l1i_count_ptr = l1i_count; *l1d_count_ptr = l1d_count; - *l2_count_ptr = l2_count; - *l3_count_ptr = l3_count; - *l4_count_ptr = l4_count; + *l2_count_ptr = l2_count; + *l3_count_ptr = l3_count; + *l4_count_ptr = l4_count; } static bool cpuinfo_x86_windows_is_wine(void) { @@ -126,36 +124,38 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV cpuinfo_x86_normalize_brand_string(x86_processor.brand_string, brand_string); const uint32_t thread_bits_mask = bit_mask(x86_processor.topology.thread_bits_length); - const uint32_t core_bits_mask = bit_mask(x86_processor.topology.core_bits_length); - const uint32_t package_bits_offset = max( - x86_processor.topology.thread_bits_offset + x86_processor.topology.thread_bits_length, - x86_processor.topology.core_bits_offset + x86_processor.topology.core_bits_length); + const uint32_t core_bits_mask = bit_mask(x86_processor.topology.core_bits_length); + const uint32_t package_bits_offset = + max(x86_processor.topology.thread_bits_offset + x86_processor.topology.thread_bits_length, + x86_processor.topology.core_bits_offset + x86_processor.topology.core_bits_length); - /* WINE doesn't implement GetMaximumProcessorGroupCount and aborts when calling it */ - const uint32_t max_group_count = is_wine ? 1 : (uint32_t) GetMaximumProcessorGroupCount(); - cpuinfo_log_debug("detected %"PRIu32" processor groups", max_group_count); + /* WINE doesn't implement GetMaximumProcessorGroupCount and aborts when + * calling it */ + const uint32_t max_group_count = is_wine ? 1 : (uint32_t)GetMaximumProcessorGroupCount(); + cpuinfo_log_debug("detected %" PRIu32 " processor groups", max_group_count); uint32_t processors_count = 0; - uint32_t* processors_per_group = (uint32_t*) CPUINFO_ALLOCA(max_group_count * sizeof(uint32_t)); + uint32_t* processors_per_group = (uint32_t*)CPUINFO_ALLOCA(max_group_count * sizeof(uint32_t)); for (uint32_t i = 0; i < max_group_count; i++) { - processors_per_group[i] = GetMaximumProcessorCount((WORD) i); - cpuinfo_log_debug("detected %"PRIu32" processors in group %"PRIu32, - processors_per_group[i], i); + processors_per_group[i] = GetMaximumProcessorCount((WORD)i); + cpuinfo_log_debug("detected %" PRIu32 " processors in group %" PRIu32, processors_per_group[i], i); processors_count += processors_per_group[i]; } - uint32_t* processors_before_group = (uint32_t*) CPUINFO_ALLOCA(max_group_count * sizeof(uint32_t)); + uint32_t* processors_before_group = (uint32_t*)CPUINFO_ALLOCA(max_group_count * sizeof(uint32_t)); for (uint32_t i = 0, count = 0; i < max_group_count; i++) { processors_before_group[i] = count; - cpuinfo_log_debug("detected %"PRIu32" processors before group %"PRIu32, - processors_before_group[i], i); + cpuinfo_log_debug( + "detected %" PRIu32 " processors before group %" PRIu32, processors_before_group[i], i); count += processors_per_group[i]; } processors = HeapAlloc(heap, HEAP_ZERO_MEMORY, processors_count * sizeof(struct cpuinfo_processor)); if (processors == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" logical processors", - processors_count * sizeof(struct cpuinfo_processor), processors_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " logical processors", + processors_count * sizeof(struct cpuinfo_processor), + processors_count); goto cleanup; } @@ -163,8 +163,9 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV if (GetLogicalProcessorInformationEx(RelationProcessorCore, NULL, &cores_info_size) == FALSE) { const DWORD last_error = GetLastError(); if (last_error != ERROR_INSUFFICIENT_BUFFER) { - cpuinfo_log_error("failed to query size of processor cores information: error %"PRIu32, - (uint32_t) last_error); + cpuinfo_log_error( + "failed to query size of processor cores information: error %" PRIu32, + (uint32_t)last_error); goto cleanup; } } @@ -173,8 +174,9 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV if (GetLogicalProcessorInformationEx(RelationProcessorPackage, NULL, &packages_info_size) == FALSE) { const DWORD last_error = GetLastError(); if (last_error != ERROR_INSUFFICIENT_BUFFER) { - cpuinfo_log_error("failed to query size of processor packages information: error %"PRIu32, - (uint32_t) last_error); + cpuinfo_log_error( + "failed to query size of processor packages information: error %" PRIu32, + (uint32_t)last_error); goto cleanup; } } @@ -183,27 +185,27 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV processor_infos = HeapAlloc(heap, 0, max_info_size); if (processor_infos == NULL) { - cpuinfo_log_error("failed to allocate %"PRIu32" bytes for logical processor information", - (uint32_t) max_info_size); + cpuinfo_log_error( + "failed to allocate %" PRIu32 " bytes for logical processor information", + (uint32_t)max_info_size); goto cleanup; } if (GetLogicalProcessorInformationEx(RelationProcessorPackage, processor_infos, &max_info_size) == FALSE) { - cpuinfo_log_error("failed to query processor packages information: error %"PRIu32, - (uint32_t) GetLastError()); + cpuinfo_log_error( + "failed to query processor packages information: error %" PRIu32, (uint32_t)GetLastError()); goto cleanup; } uint32_t packages_count = 0; PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX packages_info_end = - (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX) ((uintptr_t) processor_infos + packages_info_size); - for (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX package_info = processor_infos; - package_info < packages_info_end; - package_info = (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX) ((uintptr_t) package_info + package_info->Size)) - { + (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX)((uintptr_t)processor_infos + packages_info_size); + for (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX package_info = processor_infos; package_info < packages_info_end; + package_info = (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX)((uintptr_t)package_info + package_info->Size)) { if (package_info->Relationship != RelationProcessorPackage) { - cpuinfo_log_warning("unexpected processor info type (%"PRIu32") for processor package information", - (uint32_t) package_info->Relationship); + cpuinfo_log_warning( + "unexpected processor info type (%" PRIu32 ") for processor package information", + (uint32_t)package_info->Relationship); continue; } @@ -211,19 +213,23 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV const uint32_t package_id = packages_count++; /* Reconstruct package part of APIC ID */ const uint32_t package_apic_id = package_id << package_bits_offset; - /* Iterate processor groups and set the package part of APIC ID */ + /* Iterate processor groups and set the package part of APIC ID + */ for (uint32_t i = 0; i < package_info->Processor.GroupCount; i++) { const uint32_t group_id = package_info->Processor.GroupMask[i].Group; - /* Global index of the first logical processor belonging to this group */ + /* Global index of the first logical processor belonging + * to this group */ const uint32_t group_processors_start = processors_before_group[group_id]; - /* Bitmask representing processors in this group belonging to this package */ + /* Bitmask representing processors in this group + * belonging to this package + */ KAFFINITY group_processors_mask = package_info->Processor.GroupMask[i].Mask; while (group_processors_mask != 0) { const uint32_t group_processor_id = low_index_from_kaffinity(group_processors_mask); const uint32_t processor_id = group_processors_start + group_processor_id; - processors[processor_id].package = (const struct cpuinfo_package*) NULL + package_id; - processors[processor_id].windows_group_id = (uint16_t) group_id; - processors[processor_id].windows_processor_id = (uint16_t) group_processor_id; + processors[processor_id].package = (const struct cpuinfo_package*)NULL + package_id; + processors[processor_id].windows_group_id = (uint16_t)group_id; + processors[processor_id].windows_processor_id = (uint16_t)group_processor_id; processors[processor_id].apic_id = package_apic_id; /* Reset the lowest bit in affinity mask */ @@ -234,44 +240,50 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV max_info_size = max(cores_info_size, packages_info_size); if (GetLogicalProcessorInformationEx(RelationProcessorCore, processor_infos, &max_info_size) == FALSE) { - cpuinfo_log_error("failed to query processor cores information: error %"PRIu32, - (uint32_t) GetLastError()); + cpuinfo_log_error( + "failed to query processor cores information: error %" PRIu32, (uint32_t)GetLastError()); goto cleanup; } uint32_t cores_count = 0; - /* Index (among all cores) of the the first core on the current package */ + /* Index (among all cores) of the the first core on the current package + */ uint32_t package_core_start = 0; uint32_t current_package_apic_id = 0; PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX cores_info_end = - (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX) ((uintptr_t) processor_infos + cores_info_size); - for (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX core_info = processor_infos; - core_info < cores_info_end; - core_info = (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX) ((uintptr_t) core_info + core_info->Size)) - { + (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX)((uintptr_t)processor_infos + cores_info_size); + for (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX core_info = processor_infos; core_info < cores_info_end; + core_info = (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX)((uintptr_t)core_info + core_info->Size)) { if (core_info->Relationship != RelationProcessorCore) { - cpuinfo_log_warning("unexpected processor info type (%"PRIu32") for processor core information", - (uint32_t) core_info->Relationship); + cpuinfo_log_warning( + "unexpected processor info type (%" PRIu32 ") for processor core information", + (uint32_t)core_info->Relationship); continue; } - /* We assume that cores and logical processors are reported in APIC order */ + /* We assume that cores and logical processors are reported in + * APIC order */ const uint32_t core_id = cores_count++; uint32_t smt_id = 0; /* Reconstruct core part of APIC ID */ const uint32_t core_apic_id = (core_id & core_bits_mask) << x86_processor.topology.core_bits_offset; - /* Iterate processor groups and set the core & SMT parts of APIC ID */ + /* Iterate processor groups and set the core & SMT parts of APIC + * ID */ for (uint32_t i = 0; i < core_info->Processor.GroupCount; i++) { const uint32_t group_id = core_info->Processor.GroupMask[i].Group; - /* Global index of the first logical processor belonging to this group */ + /* Global index of the first logical processor belonging + * to this group */ const uint32_t group_processors_start = processors_before_group[group_id]; - /* Bitmask representing processors in this group belonging to this package */ + /* Bitmask representing processors in this group + * belonging to this package + */ KAFFINITY group_processors_mask = core_info->Processor.GroupMask[i].Mask; while (group_processors_mask != 0) { const uint32_t group_processor_id = low_index_from_kaffinity(group_processors_mask); const uint32_t processor_id = group_processors_start + group_processor_id; - /* Check if this is the first core on a new package */ + /* Check if this is the first core on a new + * package */ if (processors[processor_id].apic_id != current_package_apic_id) { package_core_start = core_id; current_package_apic_id = processors[processor_id].apic_id; @@ -283,12 +295,17 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV processors[processor_id].apic_id |= ((smt_id & thread_bits_mask) << x86_processor.topology.thread_bits_offset) | ((package_core_id & core_bits_mask) << x86_processor.topology.core_bits_offset); - cpuinfo_log_debug("reconstructed APIC ID 0x%08"PRIx32" for processor %"PRIu32" in group %"PRIu32, - processors[processor_id].apic_id, group_processor_id, group_id); - - /* Set SMT ID (assume logical processors within the core are reported in APIC order) */ + cpuinfo_log_debug( + "reconstructed APIC ID 0x%08" PRIx32 " for processor %" PRIu32 + " in group %" PRIu32, + processors[processor_id].apic_id, + group_processor_id, + group_id); + + /* Set SMT ID (assume logical processors within + * the core are reported in APIC order) */ processors[processor_id].smt_id = smt_id++; - processors[processor_id].core = (const struct cpuinfo_core*) NULL + core_id; + processors[processor_id].core = (const struct cpuinfo_core*)NULL + core_id; /* Reset the lowest bit in affinity mask */ group_processors_mask &= (group_processors_mask - 1); @@ -298,22 +315,28 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV cores = HeapAlloc(heap, HEAP_ZERO_MEMORY, cores_count * sizeof(struct cpuinfo_core)); if (cores == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" cores", - cores_count * sizeof(struct cpuinfo_core), cores_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " cores", + cores_count * sizeof(struct cpuinfo_core), + cores_count); goto cleanup; } clusters = HeapAlloc(heap, HEAP_ZERO_MEMORY, packages_count * sizeof(struct cpuinfo_cluster)); if (clusters == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" core clusters", - packages_count * sizeof(struct cpuinfo_cluster), packages_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " core clusters", + packages_count * sizeof(struct cpuinfo_cluster), + packages_count); goto cleanup; } packages = HeapAlloc(heap, HEAP_ZERO_MEMORY, packages_count * sizeof(struct cpuinfo_package)); if (packages == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" physical packages", - packages_count * sizeof(struct cpuinfo_package), packages_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " physical packages", + packages_count * sizeof(struct cpuinfo_package), + packages_count); goto cleanup; } @@ -321,26 +344,29 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV const uint32_t processor_id = i - 1; struct cpuinfo_processor* processor = processors + processor_id; - /* Adjust core and package pointers for all logical processors */ - struct cpuinfo_core* core = - (struct cpuinfo_core*) ((uintptr_t) cores + (uintptr_t) processor->core); + /* Adjust core and package pointers for all logical processors + */ + struct cpuinfo_core* core = (struct cpuinfo_core*)((uintptr_t)cores + (uintptr_t)processor->core); processor->core = core; struct cpuinfo_cluster* cluster = - (struct cpuinfo_cluster*) ((uintptr_t) clusters + (uintptr_t) processor->cluster); + (struct cpuinfo_cluster*)((uintptr_t)clusters + (uintptr_t)processor->cluster); processor->cluster = cluster; struct cpuinfo_package* package = - (struct cpuinfo_package*) ((uintptr_t) packages + (uintptr_t) processor->package); + (struct cpuinfo_package*)((uintptr_t)packages + (uintptr_t)processor->package); processor->package = package; - /* This can be overwritten by lower-index processors on the same package */ + /* This can be overwritten by lower-index processors on the same + * package */ package->processor_start = processor_id; package->processor_count += 1; - /* This can be overwritten by lower-index processors on the same cluster */ + /* This can be overwritten by lower-index processors on the same + * cluster */ cluster->processor_start = processor_id; cluster->processor_count += 1; - /* This can be overwritten by lower-index processors on the same core*/ + /* This can be overwritten by lower-index processors on the same + * core*/ core->processor_start = processor_id; core->processor_count += 1; } @@ -350,18 +376,19 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV const uint32_t global_core_id = i - 1; struct cpuinfo_core* core = cores + global_core_id; const struct cpuinfo_processor* processor = processors + core->processor_start; - struct cpuinfo_package* package = (struct cpuinfo_package*) processor->package; - struct cpuinfo_cluster* cluster = (struct cpuinfo_cluster*) processor->cluster; + struct cpuinfo_package* package = (struct cpuinfo_package*)processor->package; + struct cpuinfo_cluster* cluster = (struct cpuinfo_cluster*)processor->cluster; core->cluster = cluster; core->package = package; - core->core_id = core_bits_mask & - (processor->apic_id >> x86_processor.topology.core_bits_offset); + core->core_id = core_bits_mask & (processor->apic_id >> x86_processor.topology.core_bits_offset); core->vendor = x86_processor.vendor; - core->uarch = x86_processor.uarch; - core->cpuid = x86_processor.cpuid; + core->uarch = x86_processor.uarch; + core->cpuid = x86_processor.cpuid; - /* This can be overwritten by lower-index cores on the same cluster/package */ + /* This can be overwritten by lower-index cores on the same + * cluster/package + */ cluster->core_start = global_core_id; cluster->core_count += 1; package->core_start = global_core_id; @@ -383,53 +410,64 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV /* Count caches */ uint32_t l1i_count, l1d_count, l2_count, l3_count, l4_count; - cpuinfo_x86_count_caches(processors_count, processors, &x86_processor, - &l1i_count, &l1d_count, &l2_count, &l3_count, &l4_count); + cpuinfo_x86_count_caches( + processors_count, processors, &x86_processor, &l1i_count, &l1d_count, &l2_count, &l3_count, &l4_count); /* Allocate cache descriptions */ if (l1i_count != 0) { l1i = HeapAlloc(heap, HEAP_ZERO_MEMORY, l1i_count * sizeof(struct cpuinfo_cache)); if (l1i == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L1I caches", - l1i_count * sizeof(struct cpuinfo_cache), l1i_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L1I caches", + l1i_count * sizeof(struct cpuinfo_cache), + l1i_count); goto cleanup; } } if (l1d_count != 0) { l1d = HeapAlloc(heap, HEAP_ZERO_MEMORY, l1d_count * sizeof(struct cpuinfo_cache)); if (l1d == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L1D caches", - l1d_count * sizeof(struct cpuinfo_cache), l1d_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L1D caches", + l1d_count * sizeof(struct cpuinfo_cache), + l1d_count); goto cleanup; } } if (l2_count != 0) { l2 = HeapAlloc(heap, HEAP_ZERO_MEMORY, l2_count * sizeof(struct cpuinfo_cache)); if (l2 == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L2 caches", - l2_count * sizeof(struct cpuinfo_cache), l2_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L2 caches", + l2_count * sizeof(struct cpuinfo_cache), + l2_count); goto cleanup; } } if (l3_count != 0) { l3 = HeapAlloc(heap, HEAP_ZERO_MEMORY, l3_count * sizeof(struct cpuinfo_cache)); if (l3 == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L3 caches", - l3_count * sizeof(struct cpuinfo_cache), l3_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L3 caches", + l3_count * sizeof(struct cpuinfo_cache), + l3_count); goto cleanup; } } if (l4_count != 0) { l4 = HeapAlloc(heap, HEAP_ZERO_MEMORY, l4_count * sizeof(struct cpuinfo_cache)); if (l4 == NULL) { - cpuinfo_log_error("failed to allocate %zu bytes for descriptions of %"PRIu32" L4 caches", - l4_count * sizeof(struct cpuinfo_cache), l4_count); + cpuinfo_log_error( + "failed to allocate %zu bytes for descriptions of %" PRIu32 " L4 caches", + l4_count * sizeof(struct cpuinfo_cache), + l4_count); goto cleanup; } } /* Set cache information */ - uint32_t l1i_index = UINT32_MAX, l1d_index = UINT32_MAX, l2_index = UINT32_MAX, l3_index = UINT32_MAX, l4_index = UINT32_MAX; + uint32_t l1i_index = UINT32_MAX, l1d_index = UINT32_MAX, l2_index = UINT32_MAX, l3_index = UINT32_MAX, + l4_index = UINT32_MAX; uint32_t last_l1i_id = UINT32_MAX, last_l1d_id = UINT32_MAX; uint32_t last_l2_id = UINT32_MAX, last_l3_id = UINT32_MAX, last_l4_id = UINT32_MAX; for (uint32_t i = 0; i < processors_count; i++) { @@ -441,13 +479,13 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV if (l1i_id != last_l1i_id) { /* new cache */ last_l1i_id = l1i_id; - l1i[++l1i_index] = (struct cpuinfo_cache) { - .size = x86_processor.cache.l1i.size, - .associativity = x86_processor.cache.l1i.associativity, - .sets = x86_processor.cache.l1i.sets, - .partitions = x86_processor.cache.l1i.partitions, - .line_size = x86_processor.cache.l1i.line_size, - .flags = x86_processor.cache.l1i.flags, + l1i[++l1i_index] = (struct cpuinfo_cache){ + .size = x86_processor.cache.l1i.size, + .associativity = x86_processor.cache.l1i.associativity, + .sets = x86_processor.cache.l1i.sets, + .partitions = x86_processor.cache.l1i.partitions, + .line_size = x86_processor.cache.l1i.line_size, + .flags = x86_processor.cache.l1i.flags, .processor_start = i, .processor_count = 1, }; @@ -466,13 +504,13 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV if (l1d_id != last_l1d_id) { /* new cache */ last_l1d_id = l1d_id; - l1d[++l1d_index] = (struct cpuinfo_cache) { - .size = x86_processor.cache.l1d.size, - .associativity = x86_processor.cache.l1d.associativity, - .sets = x86_processor.cache.l1d.sets, - .partitions = x86_processor.cache.l1d.partitions, - .line_size = x86_processor.cache.l1d.line_size, - .flags = x86_processor.cache.l1d.flags, + l1d[++l1d_index] = (struct cpuinfo_cache){ + .size = x86_processor.cache.l1d.size, + .associativity = x86_processor.cache.l1d.associativity, + .sets = x86_processor.cache.l1d.sets, + .partitions = x86_processor.cache.l1d.partitions, + .line_size = x86_processor.cache.l1d.line_size, + .flags = x86_processor.cache.l1d.flags, .processor_start = i, .processor_count = 1, }; @@ -491,13 +529,13 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV if (l2_id != last_l2_id) { /* new cache */ last_l2_id = l2_id; - l2[++l2_index] = (struct cpuinfo_cache) { - .size = x86_processor.cache.l2.size, - .associativity = x86_processor.cache.l2.associativity, - .sets = x86_processor.cache.l2.sets, - .partitions = x86_processor.cache.l2.partitions, - .line_size = x86_processor.cache.l2.line_size, - .flags = x86_processor.cache.l2.flags, + l2[++l2_index] = (struct cpuinfo_cache){ + .size = x86_processor.cache.l2.size, + .associativity = x86_processor.cache.l2.associativity, + .sets = x86_processor.cache.l2.sets, + .partitions = x86_processor.cache.l2.partitions, + .line_size = x86_processor.cache.l2.line_size, + .flags = x86_processor.cache.l2.flags, .processor_start = i, .processor_count = 1, }; @@ -516,13 +554,13 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV if (l3_id != last_l3_id) { /* new cache */ last_l3_id = l3_id; - l3[++l3_index] = (struct cpuinfo_cache) { - .size = x86_processor.cache.l3.size, - .associativity = x86_processor.cache.l3.associativity, - .sets = x86_processor.cache.l3.sets, - .partitions = x86_processor.cache.l3.partitions, - .line_size = x86_processor.cache.l3.line_size, - .flags = x86_processor.cache.l3.flags, + l3[++l3_index] = (struct cpuinfo_cache){ + .size = x86_processor.cache.l3.size, + .associativity = x86_processor.cache.l3.associativity, + .sets = x86_processor.cache.l3.sets, + .partitions = x86_processor.cache.l3.partitions, + .line_size = x86_processor.cache.l3.line_size, + .flags = x86_processor.cache.l3.flags, .processor_start = i, .processor_count = 1, }; @@ -541,13 +579,13 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV if (l4_id != last_l4_id) { /* new cache */ last_l4_id = l4_id; - l4[++l4_index] = (struct cpuinfo_cache) { - .size = x86_processor.cache.l4.size, - .associativity = x86_processor.cache.l4.associativity, - .sets = x86_processor.cache.l4.sets, - .partitions = x86_processor.cache.l4.partitions, - .line_size = x86_processor.cache.l4.line_size, - .flags = x86_processor.cache.l4.flags, + l4[++l4_index] = (struct cpuinfo_cache){ + .size = x86_processor.cache.l4.size, + .associativity = x86_processor.cache.l4.associativity, + .sets = x86_processor.cache.l4.sets, + .partitions = x86_processor.cache.l4.partitions, + .line_size = x86_processor.cache.l4.line_size, + .flags = x86_processor.cache.l4.flags, .processor_start = i, .processor_count = 1, }; @@ -562,7 +600,6 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV } } - /* Commit changes */ cpuinfo_processors = processors; cpuinfo_cores = cores; @@ -570,9 +607,9 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV cpuinfo_packages = packages; cpuinfo_cache[cpuinfo_cache_level_1i] = l1i; cpuinfo_cache[cpuinfo_cache_level_1d] = l1d; - cpuinfo_cache[cpuinfo_cache_level_2] = l2; - cpuinfo_cache[cpuinfo_cache_level_3] = l3; - cpuinfo_cache[cpuinfo_cache_level_4] = l4; + cpuinfo_cache[cpuinfo_cache_level_2] = l2; + cpuinfo_cache[cpuinfo_cache_level_3] = l3; + cpuinfo_cache[cpuinfo_cache_level_4] = l4; cpuinfo_processors_count = processors_count; cpuinfo_cores_count = cores_count; @@ -580,12 +617,12 @@ BOOL CALLBACK cpuinfo_x86_windows_init(PINIT_ONCE init_once, PVOID parameter, PV cpuinfo_packages_count = packages_count; cpuinfo_cache_count[cpuinfo_cache_level_1i] = l1i_count; cpuinfo_cache_count[cpuinfo_cache_level_1d] = l1d_count; - cpuinfo_cache_count[cpuinfo_cache_level_2] = l2_count; - cpuinfo_cache_count[cpuinfo_cache_level_3] = l3_count; - cpuinfo_cache_count[cpuinfo_cache_level_4] = l4_count; + cpuinfo_cache_count[cpuinfo_cache_level_2] = l2_count; + cpuinfo_cache_count[cpuinfo_cache_level_3] = l3_count; + cpuinfo_cache_count[cpuinfo_cache_level_4] = l4_count; cpuinfo_max_cache_size = cpuinfo_compute_max_cache_size(&processors[0]); - cpuinfo_global_uarch = (struct cpuinfo_uarch_info) { + cpuinfo_global_uarch = (struct cpuinfo_uarch_info){ .uarch = x86_processor.uarch, .cpuid = x86_processor.cpuid, .processor_count = processors_count, diff --git a/test/arm-cache.cc b/test/arm-cache.cc index 398c099d..c1499c33 100644 --- a/test/arm-cache.cc +++ b/test/arm-cache.cc @@ -4,10 +4,9 @@ #include extern "C" { - #include +#include } - TEST(QUALCOMM, snapdragon_410_msm) { const struct cpuinfo_arm_chipset chipset = { .vendor = cpuinfo_arm_chipset_vendor_qualcomm, @@ -15,14 +14,12 @@ TEST(QUALCOMM, snapdragon_410_msm) { .model = 8916, }; - struct cpuinfo_cache l1i = { 0 }; - struct cpuinfo_cache l1d = { 0 }; - struct cpuinfo_cache l2 = { 0 }; - struct cpuinfo_cache l3 = { 0 }; + struct cpuinfo_cache l1i = {0}; + struct cpuinfo_cache l1d = {0}; + struct cpuinfo_cache l2 = {0}; + struct cpuinfo_cache l3 = {0}; cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD030), - &chipset, 0, 8, - &l1i, &l1d, &l2, &l3); + cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD030), &chipset, 0, 8, &l1i, &l1d, &l2, &l3); EXPECT_EQ(32 * 1024, l1i.size); EXPECT_EQ(32 * 1024, l1d.size); EXPECT_EQ(512 * 1024, l2.size); @@ -36,14 +33,12 @@ TEST(QUALCOMM, snapdragon_410_apq) { .model = 8016, }; - struct cpuinfo_cache l1i = { 0 }; - struct cpuinfo_cache l1d = { 0 }; - struct cpuinfo_cache l2 = { 0 }; - struct cpuinfo_cache l3 = { 0 }; + struct cpuinfo_cache l1i = {0}; + struct cpuinfo_cache l1d = {0}; + struct cpuinfo_cache l2 = {0}; + struct cpuinfo_cache l3 = {0}; cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD030), - &chipset, 0, 8, - &l1i, &l1d, &l2, &l3); + cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD030), &chipset, 0, 8, &l1i, &l1d, &l2, &l3); EXPECT_EQ(32 * 1024, l1i.size); EXPECT_EQ(32 * 1024, l1d.size); EXPECT_EQ(512 * 1024, l2.size); @@ -58,14 +53,12 @@ TEST(QUALCOMM, snapdragon_415) { }; for (uint32_t cluster = 0; cluster < 2; cluster++) { - struct cpuinfo_cache l1i = { 0 }; - struct cpuinfo_cache l1d = { 0 }; - struct cpuinfo_cache l2 = { 0 }; - struct cpuinfo_cache l3 = { 0 }; + struct cpuinfo_cache l1i = {0}; + struct cpuinfo_cache l1d = {0}; + struct cpuinfo_cache l2 = {0}; + struct cpuinfo_cache l3 = {0}; cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD031), - &chipset, cluster, 8, - &l1i, &l1d, &l2, &l3); + cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD031), &chipset, cluster, 8, &l1i, &l1d, &l2, &l3); EXPECT_EQ(32 * 1024, l1i.size); EXPECT_EQ(32 * 1024, l1d.size); EXPECT_EQ(512 * 1024, l2.size); @@ -80,14 +73,12 @@ TEST(QUALCOMM, snapdragon_425) { .model = 8917, }; - struct cpuinfo_cache l1i = { 0 }; - struct cpuinfo_cache l1d = { 0 }; - struct cpuinfo_cache l2 = { 0 }; - struct cpuinfo_cache l3 = { 0 }; + struct cpuinfo_cache l1i = {0}; + struct cpuinfo_cache l1d = {0}; + struct cpuinfo_cache l2 = {0}; + struct cpuinfo_cache l3 = {0}; cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), - &chipset, 0, 8, - &l1i, &l1d, &l2, &l3); + cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), &chipset, 0, 8, &l1i, &l1d, &l2, &l3); EXPECT_EQ(32 * 1024, l1i.size); EXPECT_EQ(32 * 1024, l1d.size); EXPECT_EQ(512 * 1024, l2.size); @@ -101,14 +92,12 @@ TEST(QUALCOMM, snapdragon_427) { .model = 8920, }; - struct cpuinfo_cache l1i = { 0 }; - struct cpuinfo_cache l1d = { 0 }; - struct cpuinfo_cache l2 = { 0 }; - struct cpuinfo_cache l3 = { 0 }; + struct cpuinfo_cache l1i = {0}; + struct cpuinfo_cache l1d = {0}; + struct cpuinfo_cache l2 = {0}; + struct cpuinfo_cache l3 = {0}; cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), - &chipset, 0, 8, - &l1i, &l1d, &l2, &l3); + cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), &chipset, 0, 8, &l1i, &l1d, &l2, &l3); EXPECT_EQ(32 * 1024, l1i.size); EXPECT_EQ(32 * 1024, l1d.size); EXPECT_EQ(512 * 1024, l2.size); @@ -122,23 +111,37 @@ TEST(QUALCOMM, snapdragon_430) { .model = 8937, }; - struct cpuinfo_cache big_l1i = { 0 }; - struct cpuinfo_cache big_l1d = { 0 }; - struct cpuinfo_cache big_l2 = { 0 }; - struct cpuinfo_cache big_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), - &chipset, 0, 8, - &big_l1i, &big_l1d, &big_l2, &big_l3); - - struct cpuinfo_cache little_l1i = { 0 }; - struct cpuinfo_cache little_l1d = { 0 }; - struct cpuinfo_cache little_l2 = { 0 }; - struct cpuinfo_cache little_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), - &chipset, 1, 8, - &little_l1i, &little_l1d, &little_l2, &little_l3); + struct cpuinfo_cache big_l1i = {0}; + struct cpuinfo_cache big_l1d = {0}; + struct cpuinfo_cache big_l2 = {0}; + struct cpuinfo_cache big_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 4, + UINT32_C(0x410FD034), + &chipset, + 0, + 8, + &big_l1i, + &big_l1d, + &big_l2, + &big_l3); + + struct cpuinfo_cache little_l1i = {0}; + struct cpuinfo_cache little_l1d = {0}; + struct cpuinfo_cache little_l2 = {0}; + struct cpuinfo_cache little_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 4, + UINT32_C(0x410FD034), + &chipset, + 1, + 8, + &little_l1i, + &little_l1d, + &little_l2, + &little_l3); EXPECT_EQ(32 * 1024, big_l1i.size); EXPECT_EQ(32 * 1024, big_l1d.size); @@ -158,23 +161,37 @@ TEST(QUALCOMM, snapdragon_435) { .model = 8940, }; - struct cpuinfo_cache big_l1i = { 0 }; - struct cpuinfo_cache big_l1d = { 0 }; - struct cpuinfo_cache big_l2 = { 0 }; - struct cpuinfo_cache big_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), - &chipset, 0, 8, - &big_l1i, &big_l1d, &big_l2, &big_l3); - - struct cpuinfo_cache little_l1i = { 0 }; - struct cpuinfo_cache little_l1d = { 0 }; - struct cpuinfo_cache little_l2 = { 0 }; - struct cpuinfo_cache little_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), - &chipset, 1, 8, - &little_l1i, &little_l1d, &little_l2, &little_l3); + struct cpuinfo_cache big_l1i = {0}; + struct cpuinfo_cache big_l1d = {0}; + struct cpuinfo_cache big_l2 = {0}; + struct cpuinfo_cache big_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 4, + UINT32_C(0x410FD034), + &chipset, + 0, + 8, + &big_l1i, + &big_l1d, + &big_l2, + &big_l3); + + struct cpuinfo_cache little_l1i = {0}; + struct cpuinfo_cache little_l1d = {0}; + struct cpuinfo_cache little_l2 = {0}; + struct cpuinfo_cache little_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 4, + UINT32_C(0x410FD034), + &chipset, + 1, + 8, + &little_l1i, + &little_l1d, + &little_l2, + &little_l3); EXPECT_EQ(32 * 1024, big_l1i.size); EXPECT_EQ(32 * 1024, big_l1d.size); @@ -194,23 +211,37 @@ TEST(QUALCOMM, snapdragon_450) { .model = 450, }; - struct cpuinfo_cache big_l1i = { 0 }; - struct cpuinfo_cache big_l1d = { 0 }; - struct cpuinfo_cache big_l2 = { 0 }; - struct cpuinfo_cache big_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), - &chipset, 0, 8, - &big_l1i, &big_l1d, &big_l2, &big_l3); - - struct cpuinfo_cache little_l1i = { 0 }; - struct cpuinfo_cache little_l1d = { 0 }; - struct cpuinfo_cache little_l2 = { 0 }; - struct cpuinfo_cache little_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), - &chipset, 1, 8, - &little_l1i, &little_l1d, &little_l2, &little_l3); + struct cpuinfo_cache big_l1i = {0}; + struct cpuinfo_cache big_l1d = {0}; + struct cpuinfo_cache big_l2 = {0}; + struct cpuinfo_cache big_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 4, + UINT32_C(0x410FD034), + &chipset, + 0, + 8, + &big_l1i, + &big_l1d, + &big_l2, + &big_l3); + + struct cpuinfo_cache little_l1i = {0}; + struct cpuinfo_cache little_l1d = {0}; + struct cpuinfo_cache little_l2 = {0}; + struct cpuinfo_cache little_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 4, + UINT32_C(0x410FD034), + &chipset, + 1, + 8, + &little_l1i, + &little_l1d, + &little_l2, + &little_l3); EXPECT_EQ(32 * 1024, big_l1i.size); EXPECT_EQ(32 * 1024, big_l1d.size); @@ -230,23 +261,37 @@ TEST(QUALCOMM, snapdragon_617) { .model = 8952, }; - struct cpuinfo_cache big_l1i = { 0 }; - struct cpuinfo_cache big_l1d = { 0 }; - struct cpuinfo_cache big_l2 = { 0 }; - struct cpuinfo_cache big_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), - &chipset, 0, 8, - &big_l1i, &big_l1d, &big_l2, &big_l3); - - struct cpuinfo_cache little_l1i = { 0 }; - struct cpuinfo_cache little_l1d = { 0 }; - struct cpuinfo_cache little_l2 = { 0 }; - struct cpuinfo_cache little_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), - &chipset, 1, 8, - &little_l1i, &little_l1d, &little_l2, &little_l3); + struct cpuinfo_cache big_l1i = {0}; + struct cpuinfo_cache big_l1d = {0}; + struct cpuinfo_cache big_l2 = {0}; + struct cpuinfo_cache big_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 4, + UINT32_C(0x410FD034), + &chipset, + 0, + 8, + &big_l1i, + &big_l1d, + &big_l2, + &big_l3); + + struct cpuinfo_cache little_l1i = {0}; + struct cpuinfo_cache little_l1d = {0}; + struct cpuinfo_cache little_l2 = {0}; + struct cpuinfo_cache little_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 4, + UINT32_C(0x410FD034), + &chipset, + 1, + 8, + &little_l1i, + &little_l1d, + &little_l2, + &little_l3); EXPECT_EQ(32 * 1024, big_l1i.size); EXPECT_EQ(32 * 1024, big_l1d.size); @@ -266,23 +311,37 @@ TEST(QUALCOMM, snapdragon_625) { .model = 8953, }; - struct cpuinfo_cache big_l1i = { 0 }; - struct cpuinfo_cache big_l1d = { 0 }; - struct cpuinfo_cache big_l2 = { 0 }; - struct cpuinfo_cache big_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), - &chipset, 0, 8, - &big_l1i, &big_l1d, &big_l2, &big_l3); - - struct cpuinfo_cache little_l1i = { 0 }; - struct cpuinfo_cache little_l1d = { 0 }; - struct cpuinfo_cache little_l2 = { 0 }; - struct cpuinfo_cache little_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), - &chipset, 1, 8, - &little_l1i, &little_l1d, &little_l2, &little_l3); + struct cpuinfo_cache big_l1i = {0}; + struct cpuinfo_cache big_l1d = {0}; + struct cpuinfo_cache big_l2 = {0}; + struct cpuinfo_cache big_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 4, + UINT32_C(0x410FD034), + &chipset, + 0, + 8, + &big_l1i, + &big_l1d, + &big_l2, + &big_l3); + + struct cpuinfo_cache little_l1i = {0}; + struct cpuinfo_cache little_l1d = {0}; + struct cpuinfo_cache little_l2 = {0}; + struct cpuinfo_cache little_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 4, + UINT32_C(0x410FD034), + &chipset, + 1, + 8, + &little_l1i, + &little_l1d, + &little_l2, + &little_l3); EXPECT_EQ(32 * 1024, big_l1i.size); EXPECT_EQ(32 * 1024, big_l1d.size); @@ -300,30 +359,45 @@ TEST(QUALCOMM, snapdragon_626) { .vendor = cpuinfo_arm_chipset_vendor_qualcomm, .series = cpuinfo_arm_chipset_series_qualcomm_msm, .model = 8953, - .suffix = { - [0] = 'P', - [1] = 'R', - [2] = 'O', - }, + .suffix = + { + [0] = 'P', + [1] = 'R', + [2] = 'O', + }, }; - struct cpuinfo_cache big_l1i = { 0 }; - struct cpuinfo_cache big_l1d = { 0 }; - struct cpuinfo_cache big_l2 = { 0 }; - struct cpuinfo_cache big_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), - &chipset, 0, 8, - &big_l1i, &big_l1d, &big_l2, &big_l3); - - struct cpuinfo_cache little_l1i = { 0 }; - struct cpuinfo_cache little_l1d = { 0 }; - struct cpuinfo_cache little_l2 = { 0 }; - struct cpuinfo_cache little_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), - &chipset, 1, 8, - &little_l1i, &little_l1d, &little_l2, &little_l3); + struct cpuinfo_cache big_l1i = {0}; + struct cpuinfo_cache big_l1d = {0}; + struct cpuinfo_cache big_l2 = {0}; + struct cpuinfo_cache big_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 4, + UINT32_C(0x410FD034), + &chipset, + 0, + 8, + &big_l1i, + &big_l1d, + &big_l2, + &big_l3); + + struct cpuinfo_cache little_l1i = {0}; + struct cpuinfo_cache little_l1d = {0}; + struct cpuinfo_cache little_l2 = {0}; + struct cpuinfo_cache little_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 4, + UINT32_C(0x410FD034), + &chipset, + 1, + 8, + &little_l1i, + &little_l1d, + &little_l2, + &little_l3); EXPECT_EQ(32 * 1024, big_l1i.size); EXPECT_EQ(32 * 1024, big_l1d.size); @@ -343,23 +417,37 @@ TEST(QUALCOMM, snapdragon_630) { .model = 630, }; - struct cpuinfo_cache big_l1i = { 0 }; - struct cpuinfo_cache big_l1d = { 0 }; - struct cpuinfo_cache big_l2 = { 0 }; - struct cpuinfo_cache big_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x51AF8014), - &chipset, 0, 8, - &big_l1i, &big_l1d, &big_l2, &big_l3); - - struct cpuinfo_cache little_l1i = { 0 }; - struct cpuinfo_cache little_l1d = { 0 }; - struct cpuinfo_cache little_l2 = { 0 }; - struct cpuinfo_cache little_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x51AF8014), - &chipset, 1, 8, - &little_l1i, &little_l1d, &little_l2, &little_l3); + struct cpuinfo_cache big_l1i = {0}; + struct cpuinfo_cache big_l1d = {0}; + struct cpuinfo_cache big_l2 = {0}; + struct cpuinfo_cache big_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 4, + UINT32_C(0x51AF8014), + &chipset, + 0, + 8, + &big_l1i, + &big_l1d, + &big_l2, + &big_l3); + + struct cpuinfo_cache little_l1i = {0}; + struct cpuinfo_cache little_l1d = {0}; + struct cpuinfo_cache little_l2 = {0}; + struct cpuinfo_cache little_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 4, + UINT32_C(0x51AF8014), + &chipset, + 1, + 8, + &little_l1i, + &little_l1d, + &little_l2, + &little_l3); EXPECT_EQ(32 * 1024, big_l1i.size); EXPECT_EQ(32 * 1024, big_l1d.size); @@ -379,23 +467,37 @@ TEST(QUALCOMM, snapdragon_636) { .model = 636, }; - struct cpuinfo_cache big_l1i = { 0 }; - struct cpuinfo_cache big_l1d = { 0 }; - struct cpuinfo_cache big_l2 = { 0 }; - struct cpuinfo_cache big_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a73, 4, UINT32_C(0x51AF8002), - &chipset, 0, 8, - &big_l1i, &big_l1d, &big_l2, &big_l3); - - struct cpuinfo_cache little_l1i = { 0 }; - struct cpuinfo_cache little_l1d = { 0 }; - struct cpuinfo_cache little_l2 = { 0 }; - struct cpuinfo_cache little_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x51AF8014), - &chipset, 1, 8, - &little_l1i, &little_l1d, &little_l2, &little_l3); + struct cpuinfo_cache big_l1i = {0}; + struct cpuinfo_cache big_l1d = {0}; + struct cpuinfo_cache big_l2 = {0}; + struct cpuinfo_cache big_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a73, + 4, + UINT32_C(0x51AF8002), + &chipset, + 0, + 8, + &big_l1i, + &big_l1d, + &big_l2, + &big_l3); + + struct cpuinfo_cache little_l1i = {0}; + struct cpuinfo_cache little_l1d = {0}; + struct cpuinfo_cache little_l2 = {0}; + struct cpuinfo_cache little_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 4, + UINT32_C(0x51AF8014), + &chipset, + 1, + 8, + &little_l1i, + &little_l1d, + &little_l2, + &little_l3); EXPECT_EQ(64 * 1024, big_l1i.size); EXPECT_EQ(64 * 1024, big_l1d.size); @@ -415,23 +517,37 @@ TEST(QUALCOMM, snapdragon_650) { .model = 8956, }; - struct cpuinfo_cache big_l1i = { 0 }; - struct cpuinfo_cache big_l1d = { 0 }; - struct cpuinfo_cache big_l2 = { 0 }; - struct cpuinfo_cache big_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a72, 2, UINT32_C(0x410FD080), - &chipset, 0, 8, - &big_l1i, &big_l1d, &big_l2, &big_l3); - - struct cpuinfo_cache little_l1i = { 0 }; - struct cpuinfo_cache little_l1d = { 0 }; - struct cpuinfo_cache little_l2 = { 0 }; - struct cpuinfo_cache little_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), - &chipset, 1, 8, - &little_l1i, &little_l1d, &little_l2, &little_l3); + struct cpuinfo_cache big_l1i = {0}; + struct cpuinfo_cache big_l1d = {0}; + struct cpuinfo_cache big_l2 = {0}; + struct cpuinfo_cache big_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a72, + 2, + UINT32_C(0x410FD080), + &chipset, + 0, + 8, + &big_l1i, + &big_l1d, + &big_l2, + &big_l3); + + struct cpuinfo_cache little_l1i = {0}; + struct cpuinfo_cache little_l1d = {0}; + struct cpuinfo_cache little_l2 = {0}; + struct cpuinfo_cache little_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 4, + UINT32_C(0x410FD034), + &chipset, + 1, + 8, + &little_l1i, + &little_l1d, + &little_l2, + &little_l3); EXPECT_EQ(48 * 1024, big_l1i.size); EXPECT_EQ(32 * 1024, big_l1d.size); @@ -451,23 +567,37 @@ TEST(QUALCOMM, snapdragon_652) { .model = 8976, }; - struct cpuinfo_cache big_l1i = { 0 }; - struct cpuinfo_cache big_l1d = { 0 }; - struct cpuinfo_cache big_l2 = { 0 }; - struct cpuinfo_cache big_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a72, 4, UINT32_C(0x410FD080), - &chipset, 0, 8, - &big_l1i, &big_l1d, &big_l2, &big_l3); - - struct cpuinfo_cache little_l1i = { 0 }; - struct cpuinfo_cache little_l1d = { 0 }; - struct cpuinfo_cache little_l2 = { 0 }; - struct cpuinfo_cache little_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), - &chipset, 1, 8, - &little_l1i, &little_l1d, &little_l2, &little_l3); + struct cpuinfo_cache big_l1i = {0}; + struct cpuinfo_cache big_l1d = {0}; + struct cpuinfo_cache big_l2 = {0}; + struct cpuinfo_cache big_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a72, + 4, + UINT32_C(0x410FD080), + &chipset, + 0, + 8, + &big_l1i, + &big_l1d, + &big_l2, + &big_l3); + + struct cpuinfo_cache little_l1i = {0}; + struct cpuinfo_cache little_l1d = {0}; + struct cpuinfo_cache little_l2 = {0}; + struct cpuinfo_cache little_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 4, + UINT32_C(0x410FD034), + &chipset, + 1, + 8, + &little_l1i, + &little_l1d, + &little_l2, + &little_l3); EXPECT_EQ(48 * 1024, big_l1i.size); EXPECT_EQ(32 * 1024, big_l1d.size); @@ -485,30 +615,45 @@ TEST(QUALCOMM, snapdragon_653) { .vendor = cpuinfo_arm_chipset_vendor_qualcomm, .series = cpuinfo_arm_chipset_series_qualcomm_msm, .model = 8976, - .suffix = { - [0] = 'P', - [1] = 'R', - [2] = 'O', - }, + .suffix = + { + [0] = 'P', + [1] = 'R', + [2] = 'O', + }, }; - struct cpuinfo_cache big_l1i = { 0 }; - struct cpuinfo_cache big_l1d = { 0 }; - struct cpuinfo_cache big_l2 = { 0 }; - struct cpuinfo_cache big_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a72, 4, UINT32_C(0x410FD080), - &chipset, 0, 8, - &big_l1i, &big_l1d, &big_l2, &big_l3); - - struct cpuinfo_cache little_l1i = { 0 }; - struct cpuinfo_cache little_l1d = { 0 }; - struct cpuinfo_cache little_l2 = { 0 }; - struct cpuinfo_cache little_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), - &chipset, 1, 8, - &little_l1i, &little_l1d, &little_l2, &little_l3); + struct cpuinfo_cache big_l1i = {0}; + struct cpuinfo_cache big_l1d = {0}; + struct cpuinfo_cache big_l2 = {0}; + struct cpuinfo_cache big_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a72, + 4, + UINT32_C(0x410FD080), + &chipset, + 0, + 8, + &big_l1i, + &big_l1d, + &big_l2, + &big_l3); + + struct cpuinfo_cache little_l1i = {0}; + struct cpuinfo_cache little_l1d = {0}; + struct cpuinfo_cache little_l2 = {0}; + struct cpuinfo_cache little_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 4, + UINT32_C(0x410FD034), + &chipset, + 1, + 8, + &little_l1i, + &little_l1d, + &little_l2, + &little_l3); EXPECT_EQ(48 * 1024, big_l1i.size); EXPECT_EQ(32 * 1024, big_l1d.size); @@ -528,23 +673,37 @@ TEST(QUALCOMM, snapdragon_660) { .model = 660, }; - struct cpuinfo_cache big_l1i = { 0 }; - struct cpuinfo_cache big_l1d = { 0 }; - struct cpuinfo_cache big_l2 = { 0 }; - struct cpuinfo_cache big_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a73, 4, UINT32_C(0x51AF8002), - &chipset, 0, 8, - &big_l1i, &big_l1d, &big_l2, &big_l3); - - struct cpuinfo_cache little_l1i = { 0 }; - struct cpuinfo_cache little_l1d = { 0 }; - struct cpuinfo_cache little_l2 = { 0 }; - struct cpuinfo_cache little_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x51AF8014), - &chipset, 1, 8, - &little_l1i, &little_l1d, &little_l2, &little_l3); + struct cpuinfo_cache big_l1i = {0}; + struct cpuinfo_cache big_l1d = {0}; + struct cpuinfo_cache big_l2 = {0}; + struct cpuinfo_cache big_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a73, + 4, + UINT32_C(0x51AF8002), + &chipset, + 0, + 8, + &big_l1i, + &big_l1d, + &big_l2, + &big_l3); + + struct cpuinfo_cache little_l1i = {0}; + struct cpuinfo_cache little_l1d = {0}; + struct cpuinfo_cache little_l2 = {0}; + struct cpuinfo_cache little_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 4, + UINT32_C(0x51AF8014), + &chipset, + 1, + 8, + &little_l1i, + &little_l1d, + &little_l2, + &little_l3); EXPECT_EQ(64 * 1024, big_l1i.size); EXPECT_EQ(64 * 1024, big_l1d.size); @@ -564,23 +723,37 @@ TEST(QUALCOMM, snapdragon_808) { .model = 8992, }; - struct cpuinfo_cache big_l1i = { 0 }; - struct cpuinfo_cache big_l1d = { 0 }; - struct cpuinfo_cache big_l2 = { 0 }; - struct cpuinfo_cache big_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a57, 2, UINT32_C(0x410FD033), - &chipset, 0, 8, - &big_l1i, &big_l1d, &big_l2, &big_l3); - - struct cpuinfo_cache little_l1i = { 0 }; - struct cpuinfo_cache little_l1d = { 0 }; - struct cpuinfo_cache little_l2 = { 0 }; - struct cpuinfo_cache little_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD033), - &chipset, 1, 8, - &little_l1i, &little_l1d, &little_l2, &little_l3); + struct cpuinfo_cache big_l1i = {0}; + struct cpuinfo_cache big_l1d = {0}; + struct cpuinfo_cache big_l2 = {0}; + struct cpuinfo_cache big_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a57, + 2, + UINT32_C(0x410FD033), + &chipset, + 0, + 8, + &big_l1i, + &big_l1d, + &big_l2, + &big_l3); + + struct cpuinfo_cache little_l1i = {0}; + struct cpuinfo_cache little_l1d = {0}; + struct cpuinfo_cache little_l2 = {0}; + struct cpuinfo_cache little_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 4, + UINT32_C(0x410FD033), + &chipset, + 1, + 8, + &little_l1i, + &little_l1d, + &little_l2, + &little_l3); EXPECT_EQ(48 * 1024, big_l1i.size); EXPECT_EQ(32 * 1024, big_l1d.size); @@ -600,23 +773,37 @@ TEST(QUALCOMM, snapdragon_810) { .model = 8994, }; - struct cpuinfo_cache big_l1i = { 0 }; - struct cpuinfo_cache big_l1d = { 0 }; - struct cpuinfo_cache big_l2 = { 0 }; - struct cpuinfo_cache big_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a57, 4, UINT32_C(0x410FD033), - &chipset, 0, 8, - &big_l1i, &big_l1d, &big_l2, &big_l3); - - struct cpuinfo_cache little_l1i = { 0 }; - struct cpuinfo_cache little_l1d = { 0 }; - struct cpuinfo_cache little_l2 = { 0 }; - struct cpuinfo_cache little_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD033), - &chipset, 1, 8, - &little_l1i, &little_l1d, &little_l2, &little_l3); + struct cpuinfo_cache big_l1i = {0}; + struct cpuinfo_cache big_l1d = {0}; + struct cpuinfo_cache big_l2 = {0}; + struct cpuinfo_cache big_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a57, + 4, + UINT32_C(0x410FD033), + &chipset, + 0, + 8, + &big_l1i, + &big_l1d, + &big_l2, + &big_l3); + + struct cpuinfo_cache little_l1i = {0}; + struct cpuinfo_cache little_l1d = {0}; + struct cpuinfo_cache little_l2 = {0}; + struct cpuinfo_cache little_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 4, + UINT32_C(0x410FD033), + &chipset, + 1, + 8, + &little_l1i, + &little_l1d, + &little_l2, + &little_l3); EXPECT_EQ(48 * 1024, big_l1i.size); EXPECT_EQ(32 * 1024, big_l1d.size); @@ -636,23 +823,28 @@ TEST(QUALCOMM, snapdragon_820) { .model = 8996, }; - struct cpuinfo_cache big_l1i = { 0 }; - struct cpuinfo_cache big_l1d = { 0 }; - struct cpuinfo_cache big_l2 = { 0 }; - struct cpuinfo_cache big_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_kryo, 4, UINT32_C(0x511F2052), - &chipset, 0, 8, - &big_l1i, &big_l1d, &big_l2, &big_l3); - - struct cpuinfo_cache little_l1i = { 0 }; - struct cpuinfo_cache little_l1d = { 0 }; - struct cpuinfo_cache little_l2 = { 0 }; - struct cpuinfo_cache little_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_kryo, 4, UINT32_C(0x511F2112), - &chipset, 1, 8, - &little_l1i, &little_l1d, &little_l2, &little_l3); + struct cpuinfo_cache big_l1i = {0}; + struct cpuinfo_cache big_l1d = {0}; + struct cpuinfo_cache big_l2 = {0}; + struct cpuinfo_cache big_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_kryo, 4, UINT32_C(0x511F2052), &chipset, 0, 8, &big_l1i, &big_l1d, &big_l2, &big_l3); + + struct cpuinfo_cache little_l1i = {0}; + struct cpuinfo_cache little_l1d = {0}; + struct cpuinfo_cache little_l2 = {0}; + struct cpuinfo_cache little_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_kryo, + 4, + UINT32_C(0x511F2112), + &chipset, + 1, + 8, + &little_l1i, + &little_l1d, + &little_l2, + &little_l3); EXPECT_EQ(32 * 1024, big_l1i.size); EXPECT_EQ(24 * 1024, big_l1d.size); @@ -670,33 +862,39 @@ TEST(QUALCOMM, snapdragon_821) { .vendor = cpuinfo_arm_chipset_vendor_qualcomm, .series = cpuinfo_arm_chipset_series_qualcomm_msm, .model = 8996, - .suffix = { - [0] = 'P', - [1] = 'R', - [2] = 'O', - [3] = '-', - [4] = 'A', - [5] = 'C', - }, + .suffix = + { + [0] = 'P', + [1] = 'R', + [2] = 'O', + [3] = '-', + [4] = 'A', + [5] = 'C', + }, }; - struct cpuinfo_cache big_l1i = { 0 }; - struct cpuinfo_cache big_l1d = { 0 }; - struct cpuinfo_cache big_l2 = { 0 }; - struct cpuinfo_cache big_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_kryo, 4, UINT32_C(0x512F2051), - &chipset, 0, 8, - &big_l1i, &big_l1d, &big_l2, &big_l3); - - struct cpuinfo_cache little_l1i = { 0 }; - struct cpuinfo_cache little_l1d = { 0 }; - struct cpuinfo_cache little_l2 = { 0 }; - struct cpuinfo_cache little_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_kryo, 4, UINT32_C(0x512F2011), - &chipset, 1, 8, - &little_l1i, &little_l1d, &little_l2, &little_l3); + struct cpuinfo_cache big_l1i = {0}; + struct cpuinfo_cache big_l1d = {0}; + struct cpuinfo_cache big_l2 = {0}; + struct cpuinfo_cache big_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_kryo, 4, UINT32_C(0x512F2051), &chipset, 0, 8, &big_l1i, &big_l1d, &big_l2, &big_l3); + + struct cpuinfo_cache little_l1i = {0}; + struct cpuinfo_cache little_l1d = {0}; + struct cpuinfo_cache little_l2 = {0}; + struct cpuinfo_cache little_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_kryo, + 4, + UINT32_C(0x512F2011), + &chipset, + 1, + 8, + &little_l1i, + &little_l1d, + &little_l2, + &little_l3); EXPECT_EQ(32 * 1024, big_l1i.size); EXPECT_EQ(24 * 1024, big_l1d.size); @@ -716,23 +914,37 @@ TEST(QUALCOMM, snapdragon_835) { .model = 8998, }; - struct cpuinfo_cache big_l1i = { 0 }; - struct cpuinfo_cache big_l1d = { 0 }; - struct cpuinfo_cache big_l2 = { 0 }; - struct cpuinfo_cache big_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a73, 4, UINT32_C(0x51AF8001), - &chipset, 0, 8, - &big_l1i, &big_l1d, &big_l2, &big_l3); - - struct cpuinfo_cache little_l1i = { 0 }; - struct cpuinfo_cache little_l1d = { 0 }; - struct cpuinfo_cache little_l2 = { 0 }; - struct cpuinfo_cache little_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x51AF8014), - &chipset, 1, 8, - &little_l1i, &little_l1d, &little_l2, &little_l3); + struct cpuinfo_cache big_l1i = {0}; + struct cpuinfo_cache big_l1d = {0}; + struct cpuinfo_cache big_l2 = {0}; + struct cpuinfo_cache big_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a73, + 4, + UINT32_C(0x51AF8001), + &chipset, + 0, + 8, + &big_l1i, + &big_l1d, + &big_l2, + &big_l3); + + struct cpuinfo_cache little_l1i = {0}; + struct cpuinfo_cache little_l1d = {0}; + struct cpuinfo_cache little_l2 = {0}; + struct cpuinfo_cache little_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 4, + UINT32_C(0x51AF8014), + &chipset, + 1, + 8, + &little_l1i, + &little_l1d, + &little_l2, + &little_l3); EXPECT_EQ(64 * 1024, big_l1i.size); EXPECT_EQ(64 * 1024, big_l1d.size); @@ -752,23 +964,37 @@ TEST(QUALCOMM, snapdragon_845) { .model = 845, }; - struct cpuinfo_cache big_l1i = { 0 }; - struct cpuinfo_cache big_l1d = { 0 }; - struct cpuinfo_cache big_l2 = { 0 }; - struct cpuinfo_cache big_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a75, 4, UINT32_C(0x518F802D), - &chipset, 0, 8, - &big_l1i, &big_l1d, &big_l2, &big_l3); - - struct cpuinfo_cache little_l1i = { 0 }; - struct cpuinfo_cache little_l1d = { 0 }; - struct cpuinfo_cache little_l2 = { 0 }; - struct cpuinfo_cache little_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a55r0, 4, UINT32_C(0x518F803C), - &chipset, 1, 8, - &little_l1i, &little_l1d, &little_l2, &little_l3); + struct cpuinfo_cache big_l1i = {0}; + struct cpuinfo_cache big_l1d = {0}; + struct cpuinfo_cache big_l2 = {0}; + struct cpuinfo_cache big_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a75, + 4, + UINT32_C(0x518F802D), + &chipset, + 0, + 8, + &big_l1i, + &big_l1d, + &big_l2, + &big_l3); + + struct cpuinfo_cache little_l1i = {0}; + struct cpuinfo_cache little_l1d = {0}; + struct cpuinfo_cache little_l2 = {0}; + struct cpuinfo_cache little_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a55r0, + 4, + UINT32_C(0x518F803C), + &chipset, + 1, + 8, + &little_l1i, + &little_l1d, + &little_l2, + &little_l3); EXPECT_EQ(64 * 1024, big_l1i.size); EXPECT_EQ(64 * 1024, big_l1d.size); @@ -788,23 +1014,37 @@ TEST(SAMSUNG, exynos_7885) { .model = 7885, }; - struct cpuinfo_cache big_l1i = { 0 }; - struct cpuinfo_cache big_l1d = { 0 }; - struct cpuinfo_cache big_l2 = { 0 }; - struct cpuinfo_cache big_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a73, 2, UINT32_C(0x410FD092), - &chipset, 0, 8, - &big_l1i, &big_l1d, &big_l2, &big_l3); - - struct cpuinfo_cache little_l1i = { 0 }; - struct cpuinfo_cache little_l1d = { 0 }; - struct cpuinfo_cache little_l2 = { 0 }; - struct cpuinfo_cache little_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 6, UINT32_C(0x410FD034), - &chipset, 1, 8, - &little_l1i, &little_l1d, &little_l2, &little_l3); + struct cpuinfo_cache big_l1i = {0}; + struct cpuinfo_cache big_l1d = {0}; + struct cpuinfo_cache big_l2 = {0}; + struct cpuinfo_cache big_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a73, + 2, + UINT32_C(0x410FD092), + &chipset, + 0, + 8, + &big_l1i, + &big_l1d, + &big_l2, + &big_l3); + + struct cpuinfo_cache little_l1i = {0}; + struct cpuinfo_cache little_l1d = {0}; + struct cpuinfo_cache little_l2 = {0}; + struct cpuinfo_cache little_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 6, + UINT32_C(0x410FD034), + &chipset, + 1, + 8, + &little_l1i, + &little_l1d, + &little_l2, + &little_l3); EXPECT_EQ(64 * 1024, big_l1i.size); EXPECT_EQ(32 * 1024, big_l1d.size); @@ -824,23 +1064,28 @@ TEST(SAMSUNG, exynos_8890) { .model = 8890, }; - struct cpuinfo_cache big_l1i = { 0 }; - struct cpuinfo_cache big_l1d = { 0 }; - struct cpuinfo_cache big_l2 = { 0 }; - struct cpuinfo_cache big_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_exynos_m1, 4, UINT32_C(0x531F0011), - &chipset, 0, 8, - &big_l1i, &big_l1d, &big_l2, &big_l3); - - struct cpuinfo_cache little_l1i = { 0 }; - struct cpuinfo_cache little_l1d = { 0 }; - struct cpuinfo_cache little_l2 = { 0 }; - struct cpuinfo_cache little_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), - &chipset, 1, 8, - &little_l1i, &little_l1d, &little_l2, &little_l3); + struct cpuinfo_cache big_l1i = {0}; + struct cpuinfo_cache big_l1d = {0}; + struct cpuinfo_cache big_l2 = {0}; + struct cpuinfo_cache big_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_exynos_m1, 4, UINT32_C(0x531F0011), &chipset, 0, 8, &big_l1i, &big_l1d, &big_l2, &big_l3); + + struct cpuinfo_cache little_l1i = {0}; + struct cpuinfo_cache little_l1d = {0}; + struct cpuinfo_cache little_l2 = {0}; + struct cpuinfo_cache little_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 4, + UINT32_C(0x410FD034), + &chipset, + 1, + 8, + &little_l1i, + &little_l1d, + &little_l2, + &little_l3); EXPECT_EQ(64 * 1024, big_l1i.size); EXPECT_EQ(32 * 1024, big_l1d.size); @@ -860,23 +1105,28 @@ TEST(SAMSUNG, exynos_8895) { .model = 8890, }; - struct cpuinfo_cache big_l1i = { 0 }; - struct cpuinfo_cache big_l1d = { 0 }; - struct cpuinfo_cache big_l2 = { 0 }; - struct cpuinfo_cache big_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_exynos_m2, 4, UINT32_C(0x534F0010), - &chipset, 0, 8, - &big_l1i, &big_l1d, &big_l2, &big_l3); - - struct cpuinfo_cache little_l1i = { 0 }; - struct cpuinfo_cache little_l1d = { 0 }; - struct cpuinfo_cache little_l2 = { 0 }; - struct cpuinfo_cache little_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), - &chipset, 1, 8, - &little_l1i, &little_l1d, &little_l2, &little_l3); + struct cpuinfo_cache big_l1i = {0}; + struct cpuinfo_cache big_l1d = {0}; + struct cpuinfo_cache big_l2 = {0}; + struct cpuinfo_cache big_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_exynos_m2, 4, UINT32_C(0x534F0010), &chipset, 0, 8, &big_l1i, &big_l1d, &big_l2, &big_l3); + + struct cpuinfo_cache little_l1i = {0}; + struct cpuinfo_cache little_l1d = {0}; + struct cpuinfo_cache little_l2 = {0}; + struct cpuinfo_cache little_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 4, + UINT32_C(0x410FD034), + &chipset, + 1, + 8, + &little_l1i, + &little_l1d, + &little_l2, + &little_l3); EXPECT_EQ(64 * 1024, big_l1i.size); EXPECT_EQ(32 * 1024, big_l1d.size); @@ -896,23 +1146,28 @@ TEST(SAMSUNG, exynos_9810) { .model = 9810, }; - struct cpuinfo_cache big_l1i = { 0 }; - struct cpuinfo_cache big_l1d = { 0 }; - struct cpuinfo_cache big_l2 = { 0 }; - struct cpuinfo_cache big_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_exynos_m3, 4, UINT32_C(0x531F0020), - &chipset, 0, 8, - &big_l1i, &big_l1d, &big_l2, &big_l3); - - struct cpuinfo_cache little_l1i = { 0 }; - struct cpuinfo_cache little_l1d = { 0 }; - struct cpuinfo_cache little_l2 = { 0 }; - struct cpuinfo_cache little_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a55r0, 4, UINT32_C(0x410FD051), - &chipset, 1, 8, - &little_l1i, &little_l1d, &little_l2, &little_l3); + struct cpuinfo_cache big_l1i = {0}; + struct cpuinfo_cache big_l1d = {0}; + struct cpuinfo_cache big_l2 = {0}; + struct cpuinfo_cache big_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_exynos_m3, 4, UINT32_C(0x531F0020), &chipset, 0, 8, &big_l1i, &big_l1d, &big_l2, &big_l3); + + struct cpuinfo_cache little_l1i = {0}; + struct cpuinfo_cache little_l1d = {0}; + struct cpuinfo_cache little_l2 = {0}; + struct cpuinfo_cache little_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a55r0, + 4, + UINT32_C(0x410FD051), + &chipset, + 1, + 8, + &little_l1i, + &little_l1d, + &little_l2, + &little_l3); EXPECT_EQ(64 * 1024, big_l1i.size); EXPECT_EQ(64 * 1024, big_l1d.size); @@ -932,23 +1187,37 @@ TEST(MEDIATEK, mediatek_mt8173) { .model = 8173, }; - struct cpuinfo_cache big_l1i = { 0 }; - struct cpuinfo_cache big_l1d = { 0 }; - struct cpuinfo_cache big_l2 = { 0 }; - struct cpuinfo_cache big_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a72, 2, UINT32_C(0x410FD080), - &chipset, 0, 4, - &big_l1i, &big_l1d, &big_l2, &big_l3); - - struct cpuinfo_cache little_l1i = { 0 }; - struct cpuinfo_cache little_l1d = { 0 }; - struct cpuinfo_cache little_l2 = { 0 }; - struct cpuinfo_cache little_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 2, UINT32_C(0x410FD032), - &chipset, 1, 4, - &little_l1i, &little_l1d, &little_l2, &little_l3); + struct cpuinfo_cache big_l1i = {0}; + struct cpuinfo_cache big_l1d = {0}; + struct cpuinfo_cache big_l2 = {0}; + struct cpuinfo_cache big_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a72, + 2, + UINT32_C(0x410FD080), + &chipset, + 0, + 4, + &big_l1i, + &big_l1d, + &big_l2, + &big_l3); + + struct cpuinfo_cache little_l1i = {0}; + struct cpuinfo_cache little_l1d = {0}; + struct cpuinfo_cache little_l2 = {0}; + struct cpuinfo_cache little_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 2, + UINT32_C(0x410FD032), + &chipset, + 1, + 4, + &little_l1i, + &little_l1d, + &little_l2, + &little_l3); EXPECT_EQ(48 * 1024, big_l1i.size); EXPECT_EQ(32 * 1024, big_l1d.size); @@ -966,28 +1235,43 @@ TEST(MEDIATEK, mediatek_mt8173c) { .vendor = cpuinfo_arm_chipset_vendor_mediatek, .series = cpuinfo_arm_chipset_series_mediatek_mt, .model = 8173, - .suffix = { - [0] = 'C', - }, + .suffix = + { + [0] = 'C', + }, }; - struct cpuinfo_cache big_l1i = { 0 }; - struct cpuinfo_cache big_l1d = { 0 }; - struct cpuinfo_cache big_l2 = { 0 }; - struct cpuinfo_cache big_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a72, 2, UINT32_C(0x410FD080), - &chipset, 0, 4, - &big_l1i, &big_l1d, &big_l2, &big_l3); - - struct cpuinfo_cache little_l1i = { 0 }; - struct cpuinfo_cache little_l1d = { 0 }; - struct cpuinfo_cache little_l2 = { 0 }; - struct cpuinfo_cache little_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 2, UINT32_C(0x410FD032), - &chipset, 1, 4, - &little_l1i, &little_l1d, &little_l2, &little_l3); + struct cpuinfo_cache big_l1i = {0}; + struct cpuinfo_cache big_l1d = {0}; + struct cpuinfo_cache big_l2 = {0}; + struct cpuinfo_cache big_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a72, + 2, + UINT32_C(0x410FD080), + &chipset, + 0, + 4, + &big_l1i, + &big_l1d, + &big_l2, + &big_l3); + + struct cpuinfo_cache little_l1i = {0}; + struct cpuinfo_cache little_l1d = {0}; + struct cpuinfo_cache little_l2 = {0}; + struct cpuinfo_cache little_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 2, + UINT32_C(0x410FD032), + &chipset, + 1, + 4, + &little_l1i, + &little_l1d, + &little_l2, + &little_l3); EXPECT_EQ(48 * 1024, big_l1i.size); EXPECT_EQ(32 * 1024, big_l1d.size); @@ -1007,23 +1291,37 @@ TEST(HISILICON, kirin_650) { .model = 650, }; - struct cpuinfo_cache big_l1i = { 0 }; - struct cpuinfo_cache big_l1d = { 0 }; - struct cpuinfo_cache big_l2 = { 0 }; - struct cpuinfo_cache big_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), - &chipset, 0, 8, - &big_l1i, &big_l1d, &big_l2, &big_l3); - - struct cpuinfo_cache little_l1i = { 0 }; - struct cpuinfo_cache little_l1d = { 0 }; - struct cpuinfo_cache little_l2 = { 0 }; - struct cpuinfo_cache little_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), - &chipset, 1, 8, - &little_l1i, &little_l1d, &little_l2, &little_l3); + struct cpuinfo_cache big_l1i = {0}; + struct cpuinfo_cache big_l1d = {0}; + struct cpuinfo_cache big_l2 = {0}; + struct cpuinfo_cache big_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 4, + UINT32_C(0x410FD034), + &chipset, + 0, + 8, + &big_l1i, + &big_l1d, + &big_l2, + &big_l3); + + struct cpuinfo_cache little_l1i = {0}; + struct cpuinfo_cache little_l1d = {0}; + struct cpuinfo_cache little_l2 = {0}; + struct cpuinfo_cache little_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 4, + UINT32_C(0x410FD034), + &chipset, + 1, + 8, + &little_l1i, + &little_l1d, + &little_l2, + &little_l3); EXPECT_EQ(32 * 1024, big_l1i.size); EXPECT_EQ(32 * 1024, big_l1d.size); @@ -1043,23 +1341,37 @@ TEST(HISILICON, kirin_659) { .model = 659, }; - struct cpuinfo_cache big_l1i = { 0 }; - struct cpuinfo_cache big_l1d = { 0 }; - struct cpuinfo_cache big_l2 = { 0 }; - struct cpuinfo_cache big_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), - &chipset, 0, 8, - &big_l1i, &big_l1d, &big_l2, &big_l3); - - struct cpuinfo_cache little_l1i = { 0 }; - struct cpuinfo_cache little_l1d = { 0 }; - struct cpuinfo_cache little_l2 = { 0 }; - struct cpuinfo_cache little_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), - &chipset, 1, 8, - &little_l1i, &little_l1d, &little_l2, &little_l3); + struct cpuinfo_cache big_l1i = {0}; + struct cpuinfo_cache big_l1d = {0}; + struct cpuinfo_cache big_l2 = {0}; + struct cpuinfo_cache big_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 4, + UINT32_C(0x410FD034), + &chipset, + 0, + 8, + &big_l1i, + &big_l1d, + &big_l2, + &big_l3); + + struct cpuinfo_cache little_l1i = {0}; + struct cpuinfo_cache little_l1d = {0}; + struct cpuinfo_cache little_l2 = {0}; + struct cpuinfo_cache little_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 4, + UINT32_C(0x410FD034), + &chipset, + 1, + 8, + &little_l1i, + &little_l1d, + &little_l2, + &little_l3); EXPECT_EQ(32 * 1024, big_l1i.size); EXPECT_EQ(32 * 1024, big_l1d.size); @@ -1073,113 +1385,155 @@ TEST(HISILICON, kirin_659) { } #if CPUINFO_ARCH_ARM - TEST(HISILICON, kirin_920) { - const struct cpuinfo_arm_chipset chipset = { - .vendor = cpuinfo_arm_chipset_vendor_hisilicon, - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = 920, - }; - - struct cpuinfo_cache big_l1i = { 0 }; - struct cpuinfo_cache big_l1d = { 0 }; - struct cpuinfo_cache big_l2 = { 0 }; - struct cpuinfo_cache big_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a15, 4, UINT32_C(0x413FC0F3), - &chipset, 0, 8, - &big_l1i, &big_l1d, &big_l2, &big_l3); - - struct cpuinfo_cache little_l1i = { 0 }; - struct cpuinfo_cache little_l1d = { 0 }; - struct cpuinfo_cache little_l2 = { 0 }; - struct cpuinfo_cache little_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a7, 4, UINT32_C(0x410FC075), - &chipset, 1, 8, - &little_l1i, &little_l1d, &little_l2, &little_l3); - - EXPECT_EQ(32 * 1024, big_l1i.size); - EXPECT_EQ(32 * 1024, big_l1d.size); - EXPECT_EQ(2 * 1024 * 1024, big_l2.size); - EXPECT_EQ(0, big_l3.size); - - EXPECT_EQ(32 * 1024, little_l1i.size); /* TODO: verify */ - EXPECT_EQ(32 * 1024, little_l1d.size); /* TODO: verify */ - EXPECT_EQ(512 * 1024, little_l2.size); - EXPECT_EQ(0, little_l3.size); - } +TEST(HISILICON, kirin_920) { + const struct cpuinfo_arm_chipset chipset = { + .vendor = cpuinfo_arm_chipset_vendor_hisilicon, + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = 920, + }; - TEST(HISILICON, kirin_925) { - const struct cpuinfo_arm_chipset chipset = { - .vendor = cpuinfo_arm_chipset_vendor_hisilicon, - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = 925, - }; - - struct cpuinfo_cache big_l1i = { 0 }; - struct cpuinfo_cache big_l1d = { 0 }; - struct cpuinfo_cache big_l2 = { 0 }; - struct cpuinfo_cache big_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a15, 4, UINT32_C(0x413FC0F3), - &chipset, 0, 8, - &big_l1i, &big_l1d, &big_l2, &big_l3); - - struct cpuinfo_cache little_l1i = { 0 }; - struct cpuinfo_cache little_l1d = { 0 }; - struct cpuinfo_cache little_l2 = { 0 }; - struct cpuinfo_cache little_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a7, 4, UINT32_C(0x410FC075), - &chipset, 1, 8, - &little_l1i, &little_l1d, &little_l2, &little_l3); - - EXPECT_EQ(32 * 1024, big_l1i.size); - EXPECT_EQ(32 * 1024, big_l1d.size); - EXPECT_EQ(2 * 1024 * 1024, big_l2.size); - EXPECT_EQ(0, big_l3.size); - - EXPECT_EQ(32 * 1024, little_l1i.size); /* TODO: verify */ - EXPECT_EQ(32 * 1024, little_l1d.size); /* TODO: verify */ - EXPECT_EQ(512 * 1024, little_l2.size); - EXPECT_EQ(0, little_l3.size); - } + struct cpuinfo_cache big_l1i = {0}; + struct cpuinfo_cache big_l1d = {0}; + struct cpuinfo_cache big_l2 = {0}; + struct cpuinfo_cache big_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a15, + 4, + UINT32_C(0x413FC0F3), + &chipset, + 0, + 8, + &big_l1i, + &big_l1d, + &big_l2, + &big_l3); + + struct cpuinfo_cache little_l1i = {0}; + struct cpuinfo_cache little_l1d = {0}; + struct cpuinfo_cache little_l2 = {0}; + struct cpuinfo_cache little_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a7, + 4, + UINT32_C(0x410FC075), + &chipset, + 1, + 8, + &little_l1i, + &little_l1d, + &little_l2, + &little_l3); - TEST(HISILICON, kirin_928) { - const struct cpuinfo_arm_chipset chipset = { - .vendor = cpuinfo_arm_chipset_vendor_hisilicon, - .series = cpuinfo_arm_chipset_series_hisilicon_kirin, - .model = 928, - }; - - struct cpuinfo_cache big_l1i = { 0 }; - struct cpuinfo_cache big_l1d = { 0 }; - struct cpuinfo_cache big_l2 = { 0 }; - struct cpuinfo_cache big_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a15, 4, UINT32_C(0x413FC0F3), - &chipset, 0, 8, - &big_l1i, &big_l1d, &big_l2, &big_l3); - - struct cpuinfo_cache little_l1i = { 0 }; - struct cpuinfo_cache little_l1d = { 0 }; - struct cpuinfo_cache little_l2 = { 0 }; - struct cpuinfo_cache little_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a7, 4, UINT32_C(0x410FC075), - &chipset, 1, 8, - &little_l1i, &little_l1d, &little_l2, &little_l3); - - EXPECT_EQ(32 * 1024, big_l1i.size); - EXPECT_EQ(32 * 1024, big_l1d.size); - EXPECT_EQ(2 * 1024 * 1024, big_l2.size); - EXPECT_EQ(0, big_l3.size); - - EXPECT_EQ(32 * 1024, little_l1i.size); /* TODO: verify */ - EXPECT_EQ(32 * 1024, little_l1d.size); /* TODO: verify */ - EXPECT_EQ(512 * 1024, little_l2.size); - EXPECT_EQ(0, little_l3.size); - } + EXPECT_EQ(32 * 1024, big_l1i.size); + EXPECT_EQ(32 * 1024, big_l1d.size); + EXPECT_EQ(2 * 1024 * 1024, big_l2.size); + EXPECT_EQ(0, big_l3.size); + + EXPECT_EQ(32 * 1024, little_l1i.size); /* TODO: verify */ + EXPECT_EQ(32 * 1024, little_l1d.size); /* TODO: verify */ + EXPECT_EQ(512 * 1024, little_l2.size); + EXPECT_EQ(0, little_l3.size); +} + +TEST(HISILICON, kirin_925) { + const struct cpuinfo_arm_chipset chipset = { + .vendor = cpuinfo_arm_chipset_vendor_hisilicon, + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = 925, + }; + + struct cpuinfo_cache big_l1i = {0}; + struct cpuinfo_cache big_l1d = {0}; + struct cpuinfo_cache big_l2 = {0}; + struct cpuinfo_cache big_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a15, + 4, + UINT32_C(0x413FC0F3), + &chipset, + 0, + 8, + &big_l1i, + &big_l1d, + &big_l2, + &big_l3); + + struct cpuinfo_cache little_l1i = {0}; + struct cpuinfo_cache little_l1d = {0}; + struct cpuinfo_cache little_l2 = {0}; + struct cpuinfo_cache little_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a7, + 4, + UINT32_C(0x410FC075), + &chipset, + 1, + 8, + &little_l1i, + &little_l1d, + &little_l2, + &little_l3); + + EXPECT_EQ(32 * 1024, big_l1i.size); + EXPECT_EQ(32 * 1024, big_l1d.size); + EXPECT_EQ(2 * 1024 * 1024, big_l2.size); + EXPECT_EQ(0, big_l3.size); + + EXPECT_EQ(32 * 1024, little_l1i.size); /* TODO: verify */ + EXPECT_EQ(32 * 1024, little_l1d.size); /* TODO: verify */ + EXPECT_EQ(512 * 1024, little_l2.size); + EXPECT_EQ(0, little_l3.size); +} + +TEST(HISILICON, kirin_928) { + const struct cpuinfo_arm_chipset chipset = { + .vendor = cpuinfo_arm_chipset_vendor_hisilicon, + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = 928, + }; + + struct cpuinfo_cache big_l1i = {0}; + struct cpuinfo_cache big_l1d = {0}; + struct cpuinfo_cache big_l2 = {0}; + struct cpuinfo_cache big_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a15, + 4, + UINT32_C(0x413FC0F3), + &chipset, + 0, + 8, + &big_l1i, + &big_l1d, + &big_l2, + &big_l3); + + struct cpuinfo_cache little_l1i = {0}; + struct cpuinfo_cache little_l1d = {0}; + struct cpuinfo_cache little_l2 = {0}; + struct cpuinfo_cache little_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a7, + 4, + UINT32_C(0x410FC075), + &chipset, + 1, + 8, + &little_l1i, + &little_l1d, + &little_l2, + &little_l3); + + EXPECT_EQ(32 * 1024, big_l1i.size); + EXPECT_EQ(32 * 1024, big_l1d.size); + EXPECT_EQ(2 * 1024 * 1024, big_l2.size); + EXPECT_EQ(0, big_l3.size); + + EXPECT_EQ(32 * 1024, little_l1i.size); /* TODO: verify */ + EXPECT_EQ(32 * 1024, little_l1d.size); /* TODO: verify */ + EXPECT_EQ(512 * 1024, little_l2.size); + EXPECT_EQ(0, little_l3.size); +} #endif /* CPUINFO_ARCH_ARM */ TEST(HISILICON, kirin_950) { @@ -1189,23 +1543,37 @@ TEST(HISILICON, kirin_950) { .model = 950, }; - struct cpuinfo_cache big_l1i = { 0 }; - struct cpuinfo_cache big_l1d = { 0 }; - struct cpuinfo_cache big_l2 = { 0 }; - struct cpuinfo_cache big_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a72, 4, UINT32_C(0x410FD080), - &chipset, 0, 8, - &big_l1i, &big_l1d, &big_l2, &big_l3); - - struct cpuinfo_cache little_l1i = { 0 }; - struct cpuinfo_cache little_l1d = { 0 }; - struct cpuinfo_cache little_l2 = { 0 }; - struct cpuinfo_cache little_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), - &chipset, 1, 8, - &little_l1i, &little_l1d, &little_l2, &little_l3); + struct cpuinfo_cache big_l1i = {0}; + struct cpuinfo_cache big_l1d = {0}; + struct cpuinfo_cache big_l2 = {0}; + struct cpuinfo_cache big_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a72, + 4, + UINT32_C(0x410FD080), + &chipset, + 0, + 8, + &big_l1i, + &big_l1d, + &big_l2, + &big_l3); + + struct cpuinfo_cache little_l1i = {0}; + struct cpuinfo_cache little_l1d = {0}; + struct cpuinfo_cache little_l2 = {0}; + struct cpuinfo_cache little_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 4, + UINT32_C(0x410FD034), + &chipset, + 1, + 8, + &little_l1i, + &little_l1d, + &little_l2, + &little_l3); EXPECT_EQ(48 * 1024, big_l1i.size); EXPECT_EQ(32 * 1024, big_l1d.size); @@ -1225,23 +1593,37 @@ TEST(HISILICON, kirin_955) { .model = 955, }; - struct cpuinfo_cache big_l1i = { 0 }; - struct cpuinfo_cache big_l1d = { 0 }; - struct cpuinfo_cache big_l2 = { 0 }; - struct cpuinfo_cache big_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a72, 4, UINT32_C(0x410FD080), - &chipset, 0, 8, - &big_l1i, &big_l1d, &big_l2, &big_l3); - - struct cpuinfo_cache little_l1i = { 0 }; - struct cpuinfo_cache little_l1d = { 0 }; - struct cpuinfo_cache little_l2 = { 0 }; - struct cpuinfo_cache little_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), - &chipset, 1, 8, - &little_l1i, &little_l1d, &little_l2, &little_l3); + struct cpuinfo_cache big_l1i = {0}; + struct cpuinfo_cache big_l1d = {0}; + struct cpuinfo_cache big_l2 = {0}; + struct cpuinfo_cache big_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a72, + 4, + UINT32_C(0x410FD080), + &chipset, + 0, + 8, + &big_l1i, + &big_l1d, + &big_l2, + &big_l3); + + struct cpuinfo_cache little_l1i = {0}; + struct cpuinfo_cache little_l1d = {0}; + struct cpuinfo_cache little_l2 = {0}; + struct cpuinfo_cache little_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 4, + UINT32_C(0x410FD034), + &chipset, + 1, + 8, + &little_l1i, + &little_l1d, + &little_l2, + &little_l3); EXPECT_EQ(48 * 1024, big_l1i.size); EXPECT_EQ(32 * 1024, big_l1d.size); @@ -1261,23 +1643,37 @@ TEST(HISILICON, kirin_960) { .model = 960, }; - struct cpuinfo_cache big_l1i = { 0 }; - struct cpuinfo_cache big_l1d = { 0 }; - struct cpuinfo_cache big_l2 = { 0 }; - struct cpuinfo_cache big_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a73, 4, UINT32_C(0x410FD091), - &chipset, 0, 8, - &big_l1i, &big_l1d, &big_l2, &big_l3); - - struct cpuinfo_cache little_l1i = { 0 }; - struct cpuinfo_cache little_l1d = { 0 }; - struct cpuinfo_cache little_l2 = { 0 }; - struct cpuinfo_cache little_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), - &chipset, 1, 8, - &little_l1i, &little_l1d, &little_l2, &little_l3); + struct cpuinfo_cache big_l1i = {0}; + struct cpuinfo_cache big_l1d = {0}; + struct cpuinfo_cache big_l2 = {0}; + struct cpuinfo_cache big_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a73, + 4, + UINT32_C(0x410FD091), + &chipset, + 0, + 8, + &big_l1i, + &big_l1d, + &big_l2, + &big_l3); + + struct cpuinfo_cache little_l1i = {0}; + struct cpuinfo_cache little_l1d = {0}; + struct cpuinfo_cache little_l2 = {0}; + struct cpuinfo_cache little_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 4, + UINT32_C(0x410FD034), + &chipset, + 1, + 8, + &little_l1i, + &little_l1d, + &little_l2, + &little_l3); EXPECT_EQ(64 * 1024, big_l1i.size); EXPECT_EQ(64 * 1024, big_l1d.size); @@ -1297,23 +1693,37 @@ TEST(HISILICON, kirin_970) { .model = 970, }; - struct cpuinfo_cache big_l1i = { 0 }; - struct cpuinfo_cache big_l1d = { 0 }; - struct cpuinfo_cache big_l2 = { 0 }; - struct cpuinfo_cache big_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a73, 4, UINT32_C(0x410FD092), - &chipset, 0, 8, - &big_l1i, &big_l1d, &big_l2, &big_l3); - - struct cpuinfo_cache little_l1i = { 0 }; - struct cpuinfo_cache little_l1d = { 0 }; - struct cpuinfo_cache little_l2 = { 0 }; - struct cpuinfo_cache little_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), - &chipset, 1, 8, - &little_l1i, &little_l1d, &little_l2, &little_l3); + struct cpuinfo_cache big_l1i = {0}; + struct cpuinfo_cache big_l1d = {0}; + struct cpuinfo_cache big_l2 = {0}; + struct cpuinfo_cache big_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a73, + 4, + UINT32_C(0x410FD092), + &chipset, + 0, + 8, + &big_l1i, + &big_l1d, + &big_l2, + &big_l3); + + struct cpuinfo_cache little_l1i = {0}; + struct cpuinfo_cache little_l1d = {0}; + struct cpuinfo_cache little_l2 = {0}; + struct cpuinfo_cache little_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 4, + UINT32_C(0x410FD034), + &chipset, + 1, + 8, + &little_l1i, + &little_l1d, + &little_l2, + &little_l3); EXPECT_EQ(64 * 1024, big_l1i.size); EXPECT_EQ(64 * 1024, big_l1d.size); @@ -1333,32 +1743,53 @@ TEST(HISILICON, kirin_980) { .model = 980, }; - struct cpuinfo_cache big_l1i = { 0 }; - struct cpuinfo_cache big_l1d = { 0 }; - struct cpuinfo_cache big_l2 = { 0 }; - struct cpuinfo_cache big_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a76, 2, UINT32_C(0x481FD400), - &chipset, 0, 2, - &big_l1i, &big_l1d, &big_l2, &big_l3); - - struct cpuinfo_cache middle_l1i = { 0 }; - struct cpuinfo_cache middle_l1d = { 0 }; - struct cpuinfo_cache middle_l2 = { 0 }; - struct cpuinfo_cache middle_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a76, 2, UINT32_C(0x481FD400), - &chipset, 1, 2, - &middle_l1i, &middle_l1d, &middle_l2, &middle_l3); - - struct cpuinfo_cache little_l1i = { 0 }; - struct cpuinfo_cache little_l1d = { 0 }; - struct cpuinfo_cache little_l2 = { 0 }; - struct cpuinfo_cache little_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a55, 4, UINT32_C(0x411FD050), - &chipset, 2, 4, - &little_l1i, &little_l1d, &little_l2, &little_l3); + struct cpuinfo_cache big_l1i = {0}; + struct cpuinfo_cache big_l1d = {0}; + struct cpuinfo_cache big_l2 = {0}; + struct cpuinfo_cache big_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a76, + 2, + UINT32_C(0x481FD400), + &chipset, + 0, + 2, + &big_l1i, + &big_l1d, + &big_l2, + &big_l3); + + struct cpuinfo_cache middle_l1i = {0}; + struct cpuinfo_cache middle_l1d = {0}; + struct cpuinfo_cache middle_l2 = {0}; + struct cpuinfo_cache middle_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a76, + 2, + UINT32_C(0x481FD400), + &chipset, + 1, + 2, + &middle_l1i, + &middle_l1d, + &middle_l2, + &middle_l3); + + struct cpuinfo_cache little_l1i = {0}; + struct cpuinfo_cache little_l1d = {0}; + struct cpuinfo_cache little_l2 = {0}; + struct cpuinfo_cache little_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a55, + 4, + UINT32_C(0x411FD050), + &chipset, + 2, + 4, + &little_l1i, + &little_l1d, + &little_l2, + &little_l3); EXPECT_EQ(64 * 1024, big_l1i.size); EXPECT_EQ(64 * 1024, big_l1d.size); @@ -1377,212 +1808,197 @@ TEST(HISILICON, kirin_980) { } #if CPUINFO_ARCH_ARM - TEST(NVIDIA, tegra_ap20h) { - const struct cpuinfo_arm_chipset chipset = { - .vendor = cpuinfo_arm_chipset_vendor_nvidia, - .series = cpuinfo_arm_chipset_series_nvidia_tegra_ap, - .model = 20, - .suffix = { +TEST(NVIDIA, tegra_ap20h) { + const struct cpuinfo_arm_chipset chipset = { + .vendor = cpuinfo_arm_chipset_vendor_nvidia, + .series = cpuinfo_arm_chipset_series_nvidia_tegra_ap, + .model = 20, + .suffix = + { [0] = 'H', }, - }; + }; - struct cpuinfo_cache l1i = { 0 }; - struct cpuinfo_cache l1d = { 0 }; - struct cpuinfo_cache l2 = { 0 }; - struct cpuinfo_cache l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a9, 2, UINT32_C(0x411FC090), - &chipset, 0, 7, - &l1i, &l1d, &l2, &l3); + struct cpuinfo_cache l1i = {0}; + struct cpuinfo_cache l1d = {0}; + struct cpuinfo_cache l2 = {0}; + struct cpuinfo_cache l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a9, 2, UINT32_C(0x411FC090), &chipset, 0, 7, &l1i, &l1d, &l2, &l3); - EXPECT_EQ(32 * 1024, l1i.size); - EXPECT_EQ(32 * 1024, l1d.size); - EXPECT_EQ(1024 * 1024, l2.size); - EXPECT_EQ(0, l3.size); - } + EXPECT_EQ(32 * 1024, l1i.size); + EXPECT_EQ(32 * 1024, l1d.size); + EXPECT_EQ(1024 * 1024, l2.size); + EXPECT_EQ(0, l3.size); +} - TEST(NVIDIA, tegra_t20) { - const struct cpuinfo_arm_chipset chipset = { - .vendor = cpuinfo_arm_chipset_vendor_nvidia, - .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, - .model = 20, - }; - - struct cpuinfo_cache l1i = { 0 }; - struct cpuinfo_cache l1d = { 0 }; - struct cpuinfo_cache l2 = { 0 }; - struct cpuinfo_cache l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a9, 2, UINT32_C(0x411FC090), - &chipset, 0, 7, - &l1i, &l1d, &l2, &l3); +TEST(NVIDIA, tegra_t20) { + const struct cpuinfo_arm_chipset chipset = { + .vendor = cpuinfo_arm_chipset_vendor_nvidia, + .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, + .model = 20, + }; - EXPECT_EQ(32 * 1024, l1i.size); - EXPECT_EQ(32 * 1024, l1d.size); - EXPECT_EQ(1024 * 1024, l2.size); - EXPECT_EQ(0, l3.size); - } + struct cpuinfo_cache l1i = {0}; + struct cpuinfo_cache l1d = {0}; + struct cpuinfo_cache l2 = {0}; + struct cpuinfo_cache l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a9, 2, UINT32_C(0x411FC090), &chipset, 0, 7, &l1i, &l1d, &l2, &l3); + + EXPECT_EQ(32 * 1024, l1i.size); + EXPECT_EQ(32 * 1024, l1d.size); + EXPECT_EQ(1024 * 1024, l2.size); + EXPECT_EQ(0, l3.size); +} - TEST(NVIDIA, tegra_t30l) { - const struct cpuinfo_arm_chipset chipset = { - .vendor = cpuinfo_arm_chipset_vendor_nvidia, - .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, - .model = 30, - .suffix = { +TEST(NVIDIA, tegra_t30l) { + const struct cpuinfo_arm_chipset chipset = { + .vendor = cpuinfo_arm_chipset_vendor_nvidia, + .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, + .model = 30, + .suffix = + { [0] = 'L', }, - }; + }; - struct cpuinfo_cache l1i = { 0 }; - struct cpuinfo_cache l1d = { 0 }; - struct cpuinfo_cache l2 = { 0 }; - struct cpuinfo_cache l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a9, 4, UINT32_C(0x412FC099), - &chipset, 0, 7, - &l1i, &l1d, &l2, &l3); + struct cpuinfo_cache l1i = {0}; + struct cpuinfo_cache l1d = {0}; + struct cpuinfo_cache l2 = {0}; + struct cpuinfo_cache l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a9, 4, UINT32_C(0x412FC099), &chipset, 0, 7, &l1i, &l1d, &l2, &l3); - EXPECT_EQ(32 * 1024, l1i.size); - EXPECT_EQ(32 * 1024, l1d.size); - EXPECT_EQ(1024 * 1024, l2.size); - EXPECT_EQ(0, l3.size); - } + EXPECT_EQ(32 * 1024, l1i.size); + EXPECT_EQ(32 * 1024, l1d.size); + EXPECT_EQ(1024 * 1024, l2.size); + EXPECT_EQ(0, l3.size); +} - TEST(NVIDIA, tegra_t30) { - const struct cpuinfo_arm_chipset chipset = { - .vendor = cpuinfo_arm_chipset_vendor_nvidia, - .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, - .model = 30, - }; - - struct cpuinfo_cache l1i = { 0 }; - struct cpuinfo_cache l1d = { 0 }; - struct cpuinfo_cache l2 = { 0 }; - struct cpuinfo_cache l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a9, 4, UINT32_C(0x412FC099), - &chipset, 0, 7, - &l1i, &l1d, &l2, &l3); +TEST(NVIDIA, tegra_t30) { + const struct cpuinfo_arm_chipset chipset = { + .vendor = cpuinfo_arm_chipset_vendor_nvidia, + .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, + .model = 30, + }; - EXPECT_EQ(32 * 1024, l1i.size); - EXPECT_EQ(32 * 1024, l1d.size); - EXPECT_EQ(1024 * 1024, l2.size); - EXPECT_EQ(0, l3.size); - } + struct cpuinfo_cache l1i = {0}; + struct cpuinfo_cache l1d = {0}; + struct cpuinfo_cache l2 = {0}; + struct cpuinfo_cache l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a9, 4, UINT32_C(0x412FC099), &chipset, 0, 7, &l1i, &l1d, &l2, &l3); - TEST(NVIDIA, tegra_t33) { - const struct cpuinfo_arm_chipset chipset = { - .vendor = cpuinfo_arm_chipset_vendor_nvidia, - .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, - .model = 33, - }; - - struct cpuinfo_cache l1i = { 0 }; - struct cpuinfo_cache l1d = { 0 }; - struct cpuinfo_cache l2 = { 0 }; - struct cpuinfo_cache l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a9, 4, UINT32_C(0x412FC099), - &chipset, 0, 7, - &l1i, &l1d, &l2, &l3); + EXPECT_EQ(32 * 1024, l1i.size); + EXPECT_EQ(32 * 1024, l1d.size); + EXPECT_EQ(1024 * 1024, l2.size); + EXPECT_EQ(0, l3.size); +} - EXPECT_EQ(32 * 1024, l1i.size); - EXPECT_EQ(32 * 1024, l1d.size); - EXPECT_EQ(1024 * 1024, l2.size); - EXPECT_EQ(0, l3.size); - } +TEST(NVIDIA, tegra_t33) { + const struct cpuinfo_arm_chipset chipset = { + .vendor = cpuinfo_arm_chipset_vendor_nvidia, + .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, + .model = 33, + }; - TEST(NVIDIA, tegra_ap33) { - const struct cpuinfo_arm_chipset chipset = { - .vendor = cpuinfo_arm_chipset_vendor_nvidia, - .series = cpuinfo_arm_chipset_series_nvidia_tegra_ap, - .model = 33, - }; - - struct cpuinfo_cache l1i = { 0 }; - struct cpuinfo_cache l1d = { 0 }; - struct cpuinfo_cache l2 = { 0 }; - struct cpuinfo_cache l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a9, 4, UINT32_C(0x412FC099), - &chipset, 0, 7, - &l1i, &l1d, &l2, &l3); + struct cpuinfo_cache l1i = {0}; + struct cpuinfo_cache l1d = {0}; + struct cpuinfo_cache l2 = {0}; + struct cpuinfo_cache l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a9, 4, UINT32_C(0x412FC099), &chipset, 0, 7, &l1i, &l1d, &l2, &l3); - EXPECT_EQ(32 * 1024, l1i.size); - EXPECT_EQ(32 * 1024, l1d.size); - EXPECT_EQ(1024 * 1024, l2.size); - EXPECT_EQ(0, l3.size); - } + EXPECT_EQ(32 * 1024, l1i.size); + EXPECT_EQ(32 * 1024, l1d.size); + EXPECT_EQ(1024 * 1024, l2.size); + EXPECT_EQ(0, l3.size); +} - TEST(NVIDIA, tegra_t114) { - const struct cpuinfo_arm_chipset chipset = { - .vendor = cpuinfo_arm_chipset_vendor_nvidia, - .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, - .model = 114, - }; - - struct cpuinfo_cache l1i = { 0 }; - struct cpuinfo_cache l1d = { 0 }; - struct cpuinfo_cache l2 = { 0 }; - struct cpuinfo_cache l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a15, 4, UINT32_C(0x412FC0F2), - &chipset, 0, 7, - &l1i, &l1d, &l2, &l3); +TEST(NVIDIA, tegra_ap33) { + const struct cpuinfo_arm_chipset chipset = { + .vendor = cpuinfo_arm_chipset_vendor_nvidia, + .series = cpuinfo_arm_chipset_series_nvidia_tegra_ap, + .model = 33, + }; - EXPECT_EQ(32 * 1024, l1i.size); - EXPECT_EQ(32 * 1024, l1d.size); - EXPECT_EQ(2 * 1024 * 1024, l2.size); - EXPECT_EQ(0, l3.size); - } + struct cpuinfo_cache l1i = {0}; + struct cpuinfo_cache l1d = {0}; + struct cpuinfo_cache l2 = {0}; + struct cpuinfo_cache l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a9, 4, UINT32_C(0x412FC099), &chipset, 0, 7, &l1i, &l1d, &l2, &l3); + + EXPECT_EQ(32 * 1024, l1i.size); + EXPECT_EQ(32 * 1024, l1d.size); + EXPECT_EQ(1024 * 1024, l2.size); + EXPECT_EQ(0, l3.size); +} + +TEST(NVIDIA, tegra_t114) { + const struct cpuinfo_arm_chipset chipset = { + .vendor = cpuinfo_arm_chipset_vendor_nvidia, + .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, + .model = 114, + }; - TEST(NVIDIA, tegra_sl460n) { - const struct cpuinfo_arm_chipset chipset = { - .vendor = cpuinfo_arm_chipset_vendor_nvidia, - .series = cpuinfo_arm_chipset_series_nvidia_tegra_sl, - .model = 460, - .suffix = { + struct cpuinfo_cache l1i = {0}; + struct cpuinfo_cache l1d = {0}; + struct cpuinfo_cache l2 = {0}; + struct cpuinfo_cache l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a15, 4, UINT32_C(0x412FC0F2), &chipset, 0, 7, &l1i, &l1d, &l2, &l3); + + EXPECT_EQ(32 * 1024, l1i.size); + EXPECT_EQ(32 * 1024, l1d.size); + EXPECT_EQ(2 * 1024 * 1024, l2.size); + EXPECT_EQ(0, l3.size); +} + +TEST(NVIDIA, tegra_sl460n) { + const struct cpuinfo_arm_chipset chipset = { + .vendor = cpuinfo_arm_chipset_vendor_nvidia, + .series = cpuinfo_arm_chipset_series_nvidia_tegra_sl, + .model = 460, + .suffix = + { [0] = 'N', }, - }; + }; - struct cpuinfo_cache l1i = { 0 }; - struct cpuinfo_cache l1d = { 0 }; - struct cpuinfo_cache l2 = { 0 }; - struct cpuinfo_cache l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a9, 4, UINT32_C(0x414FC091), - &chipset, 0, 7, - &l1i, &l1d, &l2, &l3); + struct cpuinfo_cache l1i = {0}; + struct cpuinfo_cache l1d = {0}; + struct cpuinfo_cache l2 = {0}; + struct cpuinfo_cache l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a9, 4, UINT32_C(0x414FC091), &chipset, 0, 7, &l1i, &l1d, &l2, &l3); - EXPECT_EQ(32 * 1024, l1i.size); - EXPECT_EQ(32 * 1024, l1d.size); - EXPECT_EQ(1 * 1024 * 1024, l2.size); - EXPECT_EQ(0, l3.size); - } + EXPECT_EQ(32 * 1024, l1i.size); + EXPECT_EQ(32 * 1024, l1d.size); + EXPECT_EQ(1 * 1024 * 1024, l2.size); + EXPECT_EQ(0, l3.size); +} - TEST(NVIDIA, tegra_t124) { - const struct cpuinfo_arm_chipset chipset = { - .vendor = cpuinfo_arm_chipset_vendor_nvidia, - .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, - .model = 124, - }; - - struct cpuinfo_cache l1i = { 0 }; - struct cpuinfo_cache l1d = { 0 }; - struct cpuinfo_cache l2 = { 0 }; - struct cpuinfo_cache l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a15, 4, UINT32_C(0x413FC0F3), - &chipset, 0, 7, - &l1i, &l1d, &l2, &l3); +TEST(NVIDIA, tegra_t124) { + const struct cpuinfo_arm_chipset chipset = { + .vendor = cpuinfo_arm_chipset_vendor_nvidia, + .series = cpuinfo_arm_chipset_series_nvidia_tegra_t, + .model = 124, + }; - EXPECT_EQ(32 * 1024, l1i.size); - EXPECT_EQ(32 * 1024, l1d.size); - EXPECT_EQ(2 * 1024 * 1024, l2.size); - EXPECT_EQ(0, l3.size); - } + struct cpuinfo_cache l1i = {0}; + struct cpuinfo_cache l1d = {0}; + struct cpuinfo_cache l2 = {0}; + struct cpuinfo_cache l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a15, 4, UINT32_C(0x413FC0F3), &chipset, 0, 7, &l1i, &l1d, &l2, &l3); + + EXPECT_EQ(32 * 1024, l1i.size); + EXPECT_EQ(32 * 1024, l1d.size); + EXPECT_EQ(2 * 1024 * 1024, l2.size); + EXPECT_EQ(0, l3.size); +} #endif /* CPUINFO_ARCH_ARM */ TEST(NVIDIA, tegra_t132) { @@ -1592,14 +2008,11 @@ TEST(NVIDIA, tegra_t132) { .model = 132, }; - struct cpuinfo_cache l1i = { 0 }; - struct cpuinfo_cache l1d = { 0 }; - struct cpuinfo_cache l2 = { 0 }; - struct cpuinfo_cache l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_denver, 2, UINT32_C(0x4E0F0000), - &chipset, 0, 8, - &l1i, &l1d, &l2, &l3); + struct cpuinfo_cache l1i = {0}; + struct cpuinfo_cache l1d = {0}; + struct cpuinfo_cache l2 = {0}; + struct cpuinfo_cache l3 = {0}; + cpuinfo_arm_decode_cache(cpuinfo_uarch_denver, 2, UINT32_C(0x4E0F0000), &chipset, 0, 8, &l1i, &l1d, &l2, &l3); EXPECT_EQ(128 * 1024, l1i.size); EXPECT_EQ(64 * 1024, l1d.size); @@ -1614,14 +2027,12 @@ TEST(NVIDIA, tegra_t210) { .model = 210, }; - struct cpuinfo_cache l1i = { 0 }; - struct cpuinfo_cache l1d = { 0 }; - struct cpuinfo_cache l2 = { 0 }; - struct cpuinfo_cache l3 = { 0 }; + struct cpuinfo_cache l1i = {0}; + struct cpuinfo_cache l1d = {0}; + struct cpuinfo_cache l2 = {0}; + struct cpuinfo_cache l3 = {0}; cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a57, 4, UINT32_C(0x411FD071), - &chipset, 0, 8, - &l1i, &l1d, &l2, &l3); + cpuinfo_uarch_cortex_a57, 4, UINT32_C(0x411FD071), &chipset, 0, 8, &l1i, &l1d, &l2, &l3); EXPECT_EQ(48 * 1024, l1i.size); EXPECT_EQ(32 * 1024, l1d.size); @@ -1636,23 +2047,37 @@ TEST(ROCKCHIP, rk3368) { .model = 3368, }; - struct cpuinfo_cache big_l1i = { 0 }; - struct cpuinfo_cache big_l1d = { 0 }; - struct cpuinfo_cache big_l2 = { 0 }; - struct cpuinfo_cache big_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD033), - &chipset, 0, 8, - &big_l1i, &big_l1d, &big_l2, &big_l3); - - struct cpuinfo_cache little_l1i = { 0 }; - struct cpuinfo_cache little_l1d = { 0 }; - struct cpuinfo_cache little_l2 = { 0 }; - struct cpuinfo_cache little_l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD033), - &chipset, 1, 8, - &little_l1i, &little_l1d, &little_l2, &little_l3); + struct cpuinfo_cache big_l1i = {0}; + struct cpuinfo_cache big_l1d = {0}; + struct cpuinfo_cache big_l2 = {0}; + struct cpuinfo_cache big_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 4, + UINT32_C(0x410FD033), + &chipset, + 0, + 8, + &big_l1i, + &big_l1d, + &big_l2, + &big_l3); + + struct cpuinfo_cache little_l1i = {0}; + struct cpuinfo_cache little_l1d = {0}; + struct cpuinfo_cache little_l2 = {0}; + struct cpuinfo_cache little_l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, + 4, + UINT32_C(0x410FD033), + &chipset, + 1, + 8, + &little_l1i, + &little_l1d, + &little_l2, + &little_l3); EXPECT_EQ(32 * 1024, big_l1i.size); EXPECT_EQ(32 * 1024, big_l1d.size); @@ -1666,49 +2091,44 @@ TEST(ROCKCHIP, rk3368) { } #if CPUINFO_ARCH_ARM - TEST(BROADCOM, bcm2835) { - const struct cpuinfo_arm_chipset chipset = { - .vendor = cpuinfo_arm_chipset_vendor_broadcom, - .series = cpuinfo_arm_chipset_series_broadcom_bcm, - .model = 2835, - }; - - struct cpuinfo_cache l1i = { 0 }; - struct cpuinfo_cache l1d = { 0 }; - struct cpuinfo_cache l2 = { 0 }; - struct cpuinfo_cache l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_arm11, 4, UINT32_C(0x410FB767), - &chipset, 0, 4, - &l1i, &l1d, &l2, &l3); +TEST(BROADCOM, bcm2835) { + const struct cpuinfo_arm_chipset chipset = { + .vendor = cpuinfo_arm_chipset_vendor_broadcom, + .series = cpuinfo_arm_chipset_series_broadcom_bcm, + .model = 2835, + }; - EXPECT_EQ(16 * 1024, l1i.size); - EXPECT_EQ(16 * 1024, l1d.size); - EXPECT_EQ(0, l2.size); - EXPECT_EQ(0, l3.size); - } + struct cpuinfo_cache l1i = {0}; + struct cpuinfo_cache l1d = {0}; + struct cpuinfo_cache l2 = {0}; + struct cpuinfo_cache l3 = {0}; + cpuinfo_arm_decode_cache(cpuinfo_uarch_arm11, 4, UINT32_C(0x410FB767), &chipset, 0, 4, &l1i, &l1d, &l2, &l3); - TEST(BROADCOM, bcm2836) { - const struct cpuinfo_arm_chipset chipset = { - .vendor = cpuinfo_arm_chipset_vendor_broadcom, - .series = cpuinfo_arm_chipset_series_broadcom_bcm, - .model = 2836, - }; - - struct cpuinfo_cache l1i = { 0 }; - struct cpuinfo_cache l1d = { 0 }; - struct cpuinfo_cache l2 = { 0 }; - struct cpuinfo_cache l3 = { 0 }; - cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a7, 4, UINT32_C(0x410FC075), - &chipset, 0, 4, - &l1i, &l1d, &l2, &l3); + EXPECT_EQ(16 * 1024, l1i.size); + EXPECT_EQ(16 * 1024, l1d.size); + EXPECT_EQ(0, l2.size); + EXPECT_EQ(0, l3.size); +} - EXPECT_EQ(32 * 1024, l1i.size); - EXPECT_EQ(32 * 1024, l1d.size); - EXPECT_EQ(512 * 1024, l2.size); - EXPECT_EQ(0, l3.size); - } +TEST(BROADCOM, bcm2836) { + const struct cpuinfo_arm_chipset chipset = { + .vendor = cpuinfo_arm_chipset_vendor_broadcom, + .series = cpuinfo_arm_chipset_series_broadcom_bcm, + .model = 2836, + }; + + struct cpuinfo_cache l1i = {0}; + struct cpuinfo_cache l1d = {0}; + struct cpuinfo_cache l2 = {0}; + struct cpuinfo_cache l3 = {0}; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a7, 4, UINT32_C(0x410FC075), &chipset, 0, 4, &l1i, &l1d, &l2, &l3); + + EXPECT_EQ(32 * 1024, l1i.size); + EXPECT_EQ(32 * 1024, l1d.size); + EXPECT_EQ(512 * 1024, l2.size); + EXPECT_EQ(0, l3.size); +} #endif /* CPUINFO_ARCH_ARM */ TEST(BROADCOM, bcm2837) { @@ -1718,14 +2138,12 @@ TEST(BROADCOM, bcm2837) { .model = 2837, }; - struct cpuinfo_cache l1i = { 0 }; - struct cpuinfo_cache l1d = { 0 }; - struct cpuinfo_cache l2 = { 0 }; - struct cpuinfo_cache l3 = { 0 }; + struct cpuinfo_cache l1i = {0}; + struct cpuinfo_cache l1d = {0}; + struct cpuinfo_cache l2 = {0}; + struct cpuinfo_cache l3 = {0}; cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), - &chipset, 0, 4, - &l1i, &l1d, &l2, &l3); + cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD034), &chipset, 0, 4, &l1i, &l1d, &l2, &l3); EXPECT_EQ(16 * 1024, l1i.size); EXPECT_EQ(16 * 1024, l1d.size); @@ -1740,14 +2158,12 @@ TEST(BROADCOM, bcm2711) { .model = 2711, }; - struct cpuinfo_cache l1i = { 0 }; - struct cpuinfo_cache l1d = { 0 }; - struct cpuinfo_cache l2 = { 0 }; - struct cpuinfo_cache l3 = { 0 }; + struct cpuinfo_cache l1i = {0}; + struct cpuinfo_cache l1d = {0}; + struct cpuinfo_cache l2 = {0}; + struct cpuinfo_cache l3 = {0}; cpuinfo_arm_decode_cache( - cpuinfo_uarch_cortex_a72, 4, UINT32_C(0x410FD083), - &chipset, 0, 4, - &l1i, &l1d, &l2, &l3); + cpuinfo_uarch_cortex_a72, 4, UINT32_C(0x410FD083), &chipset, 0, 4, &l1i, &l1d, &l2, &l3); EXPECT_EQ(48 * 1024, l1i.size); EXPECT_EQ(32 * 1024, l1d.size); diff --git a/test/get-current.cc b/test/get-current.cc index 96b11dc9..1aa4b638 100644 --- a/test/get-current.cc +++ b/test/get-current.cc @@ -2,7 +2,6 @@ #include - TEST(CURRENT_PROCESSOR, within_bounds) { ASSERT_TRUE(cpuinfo_initialize()); diff --git a/test/init.cc b/test/init.cc index 718eb96d..a6128e35 100644 --- a/test/init.cc +++ b/test/init.cc @@ -2,7 +2,6 @@ #include - TEST(PROCESSORS_COUNT, non_zero) { ASSERT_TRUE(cpuinfo_initialize()); EXPECT_NE(0, cpuinfo_get_processors_count()); @@ -782,8 +781,7 @@ TEST(L1I_CACHE, valid_size) { const cpuinfo_cache* cache = cpuinfo_get_l1i_cache(i); ASSERT_TRUE(cache); - EXPECT_EQ(cache->size, - cache->associativity * cache->sets * cache->partitions * cache->line_size); + EXPECT_EQ(cache->size, cache->associativity * cache->sets * cache->partitions * cache->line_size); } cpuinfo_deinitialize(); } @@ -947,8 +945,7 @@ TEST(L1D_CACHE, valid_size) { const cpuinfo_cache* cache = cpuinfo_get_l1d_cache(i); ASSERT_TRUE(cache); - EXPECT_EQ(cache->size, - cache->associativity * cache->sets * cache->partitions * cache->line_size); + EXPECT_EQ(cache->size, cache->associativity * cache->sets * cache->partitions * cache->line_size); } cpuinfo_deinitialize(); } @@ -1114,8 +1111,7 @@ TEST(L2_CACHE, valid_size) { const cpuinfo_cache* cache = cpuinfo_get_l2_cache(i); ASSERT_TRUE(cache); - EXPECT_EQ(cache->size, - cache->associativity * cache->sets * cache->partitions * cache->line_size); + EXPECT_EQ(cache->size, cache->associativity * cache->sets * cache->partitions * cache->line_size); } cpuinfo_deinitialize(); } @@ -1262,8 +1258,7 @@ TEST(L3_CACHE, valid_size) { const cpuinfo_cache* cache = cpuinfo_get_l3_cache(i); ASSERT_TRUE(cache); - EXPECT_EQ(cache->size, - cache->associativity * cache->sets * cache->partitions * cache->line_size); + EXPECT_EQ(cache->size, cache->associativity * cache->sets * cache->partitions * cache->line_size); } cpuinfo_deinitialize(); } @@ -1410,8 +1405,7 @@ TEST(L4_CACHE, valid_size) { const cpuinfo_cache* cache = cpuinfo_get_l4_cache(i); ASSERT_TRUE(cache); - EXPECT_EQ(cache->size, - cache->associativity * cache->sets * cache->partitions * cache->line_size); + EXPECT_EQ(cache->size, cache->associativity * cache->sets * cache->partitions * cache->line_size); } cpuinfo_deinitialize(); } diff --git a/test/mock/alcatel-revvl.cc b/test/mock/alcatel-revvl.cc index d3ed9816..f16356e2 100644 --- a/test/mock/alcatel-revvl.cc +++ b/test/mock/alcatel-revvl.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(5, cpuinfo_get_processors_count()); @@ -273,8 +272,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("MediaTek MT6738", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "MediaTek MT6738", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -316,59 +317,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -493,8 +494,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -545,8 +548,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -597,8 +602,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/alcatel-revvl.h b/test/mock/alcatel-revvl.h index 2d7ecc66..def6ec81 100644 --- a/test/mock/alcatel-revvl.h +++ b/test/mock/alcatel-revvl.h @@ -3,31 +3,30 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 554, - .content = - "Processor\t: AArch64 Processor rev 2 (aarch64)\n" - "processor\t: 4\n" - "model name\t: AArch64 Processor rev 2 (aarch64)\n" - "BogoMIPS\t: 26.00\n" - "BogoMIPS\t: 26.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 2\n" - "\n" - "processor\t: 5\n" - "model name\t: AArch64 Processor rev 2 (aarch64)\n" - "BogoMIPS\t: 26.00\n" - "BogoMIPS\t: 26.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 2\n" - "\n" - "Hardware\t: MT6738\n", + .content = "Processor\t: AArch64 Processor rev 2 (aarch64)\n" + "processor\t: 4\n" + "model name\t: AArch64 Processor rev 2 (aarch64)\n" + "BogoMIPS\t: 26.00\n" + "BogoMIPS\t: 26.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 2\n" + "\n" + "processor\t: 5\n" + "model name\t: AArch64 Processor rev 2 (aarch64)\n" + "BogoMIPS\t: 26.00\n" + "BogoMIPS\t: 26.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 2\n" + "\n" + "Hardware\t: MT6738\n", }, #elif CPUINFO_ARCH_ARM { @@ -52,358 +51,357 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/system/build.prop", .size = 9423, - .content = - "\n" - "# begin build properties\n" - "# autogenerated by buildinfo.sh\n" - "ro.build.id=NRD90M\n" - "ro.build.display.id=Android N\n" - "ro.build.version.incremental=v6H7J-0\n" - "ro.build.version.sdk=24\n" - "ro.build.version.preview_sdk=0\n" - "ro.build.version.codename=REL\n" - "ro.build.version.all_codenames=REL\n" - "ro.build.version.release=7.0\n" - "ro.build.version.security_patch=2017-07-01\n" - "ro.build.version.base_os=\n" - "ro.build.date=Wed Aug 2 13:58:19 CST 2017\n" - "ro.build.date.utc=1501653499\n" - "ro.build.type=user\n" - "ro.build.user=android-bld\n" - "ro.build.host=Perso41\n" - "ro.build.tags=release-keys\n" - "ro.build.flavor=Mickey6TTMO-user\n" - "ro.product.model=5049W\n" - "ro.product.brand=TCL\n" - "ro.product.name=5049W\n" - "ro.product.device=Mickey6TTMO\n" - "ro.product.board=\n" - "# ro.product.cpu.abi and ro.product.cpu.abi2 are obsolete,\n" - "# use ro.product.cpu.abilist instead.\n" - "ro.product.cpu.abi=arm64-v8a\n" - "ro.product.cpu.abilist=arm64-v8a,armeabi-v7a,armeabi\n" - "ro.product.cpu.abilist32=armeabi-v7a,armeabi\n" - "ro.product.cpu.abilist64=arm64-v8a\n" - "ro.product.manufacturer=AlcatelOneTouch\n" - "ro.wifi.channels=\n" - "ro.board.platform=mt6750\n" - "# ro.build.product is obsolete; use ro.product.device\n" - "ro.build.product=Mickey6TTMO\n" - "# Do not try to parse description, fingerprint, or thumbprint\n" - "ro.build.description=Mickey6TTMO-user 7.0 NRD90M v6H7J-0 release-keys\n" - "ro.build.fingerprint=TCL/5049W/Mickey6TTMO:7.0/NRD90M/v6H7J-0:user/release-keys\n" - "ro.build.characteristics=default\n" - "persist.disable.temperature=false\n" - "ro.product.locales=\n" - "ro.product.display.model=5049W\n" - "ro.tct.sys.ver=Y6H7J0J0CM00\n" - "ro.tct.boot.ver=B6H7J0J0CM00\n" - "ro.tct.cust.ver=C6H7UMJ3CM00\n" - "ro.tct.reco.ver=R6H7J0J0CM00\n" - "# end build properties\n" - "#\n" - "#jrd sys properties\n" - "#\n" - "\n" - "Modem.FD.supported.for.perso=true\n" - "ro.product.locale.language=en\n" - "ro.product.locale.region=US\n" - "ro.com.google.clientidbase=android-alcatel\n" - "ro.com.google.clientidbase.am=android-tmobile-us\n" - "ro.com.google.clientidbase.ms=android-hms-tmobile-us\n" - "gsm.version.baseband=c1-00006-8909_GEN_PACK-1.32621.1\n" - "ro.def.software.svn=010 04\n" - "def.israel.on=false\n" - "def.settings.separate.volume=true\n" - "persist.sys.phone.minmatch.len=10\n" - "persist.sys.recovery.showtext=true\n" - "ro.mtk_oma_drm_support=1\n" - "ro.drm_popup_dialog=1\n" - "persist.sys.phone.assistedstat=false\n" - "ro.usb.product=T-Mobile Revvl\n" - "ro.x.wap.profile=http://www-ccpp.tcl-ta.com/files/5049W.xml\n" - "persist.sys.pwringtone.enable=1\n" - "persist.sys.ringtonemode=2\n" - "ro.config.power_on=Jumping_on_default.mp3\n" - "ro.config.power_off=\n" - "ro.config.ringtone=T-Jingle.mp3\n" - "ro.config.alarm_alert=Galactic.mp3\n" - "ro.bluetooth.name=T-Mobile Revvl\n" - "ro.config.notification_sound=Success.mp3\n" - "ro.setupwizard.require_network=\n" - "feature_tctfw_mtp_on=0\n" - "persist.radio.hotspot.support=0\n" - "ro_set_nl_cb_on=false\n" - "persist.sys.ssshot.threePointer=1\n" - "ro.headset.sound.mode=0\n" - "persist.sys.phone.refercountry=United States of America\n" - "persist.sys.phone.countrycode=1\n" - "persist.sys.phone.iddcode=011\n" - "persist.sys.phone.nddcode=1\n" - "persist.sys.phone.areasettings=Washington\n" - "persist.sys.phone.citycode=206\n" - "persist.sys.phone.numberlen=null\n" - "ro.config.number.format=false\n" - "ro.start.nextradio.service=true\n" - "ro.config.videocall.show=true\n" - "ecc.list.for.perso=911,112\n" - "ecc.list.for.perso.no_sim=000,110,118,119,999,112,911\n" - "ro.jrd.wfc.manager.operator=1\n" - "ro.tcl_sar_support=1\n" - "ro.def.software.version=H7JUMJ3\n" - "ro.config.support_softsim=0\n" - "persist.net.wo.keep_timer=300\n" - "persist.net.wo.dpd_timer=300\n" - "#\n" - "# from device/jrdcsz/Mickey6TTMO/system.prop\n" - "#\n" - "#\n" - "# system.prop for generic sdk\n" - "#\n" - "\n" - "rild.libpath=mtk-ril.so\n" - "rild.libargs=-d /dev/ttyC0\n" - "\n" - "\n" - "# MTK, Infinity, 20090720 {\n" - "wifi.interface=wlan0\n" - "# MTK, Infinity, 20090720 }\n" - "\n" - "# MTK, mtk03034, 20101210 {\n" - "ro.mediatek.wlan.wsc=1\n" - "# MTK, mtk03034 20101210}\n" - "# MTK, mtk03034, 20110318 {\n" - "ro.mediatek.wlan.p2p=1\n" - "# MTK, mtk03034 20110318}\n" - "\n" - "# MTK, mtk03034, 20101213 {\n" - "mediatek.wlan.ctia=0\n" - "# MTK, mtk03034 20101213}\n" - "\n" - "\n" - "#\n" - "wifi.tethering.interface=ap0\n" - "#\n" - "\n" - "#Modify by hua.lei@tcl.com for cts Tetst\n" - "#this value should be the same as Opengl Driver (Eg.3.2)\n" - "ro.opengles.version=196610\n" - "#ro.kernel.qemu=1\n" - "#ro.kernel.qemu.gles=0\n" - "\n" - "wifi.direct.interface=p2p0\n" - "dalvik.vm.heapgrowthlimit=256m\n" - "dalvik.vm.heapsize=512m\n" - "\n" - "# USB MTP WHQL\n" - "ro.sys.usb.mtp.whql.enable=0\n" - "\n" - "# Power off opt in IPO\n" - "sys.ipo.pwrdncap=2\n" - "\n" - "ro.sys.usb.storage.type=mtp\n" - "\n" - "# USB BICR function\n" - "ro.sys.usb.bicr=no\n" - "\n" - "# USB Charge only function\n" - "ro.sys.usb.charging.only=yes\n" - "\n" - "# audio\n" - "ro.camera.sound.forced=0\n" - "ro.audio.silent=0\n" - "\n" - "ro.zygote.preload.enable=0\n" - "\n" - "# temporary enables NAV bar (soft keys)\n" - "qemu.hw.mainkeys=0\n" - "\n" - "ro.kernel.zio=38,108,105,16\n" - "#ro.kernel.qemu=1\n" - "#ro.kernel.qemu.gles=0\n" - "#ro.boot.selinux=disable\n" - "\n" - "\n" - "ro.sf.lcd_density=480\n" - "\n" - "# performance\n" - "ro.mtk_perf_simple_start_win=1\n" - "ro.mtk_perf_fast_start_win=1\n" - "ro.mtk_perf_response_time=1\n" - "\n" - "# MAL\n" - "persist.mal.mode=0\n" - "\n" - "#add by kai.yan@tcl.com for Defect 4355270 at 20170315\n" - "persist.mtk_wfc_support=1\n" - "persist.mtk.wfc.enable=1\n" - "persist.dbg.wfc_avail_ovr=1\n" - "\n" - "#custom Dialer show video calling button\n" - "ro.config.videocall.show=false\n" - "\n" - "#\n" - "# ADDITIONAL_BUILD_PROPERTIES\n" - "#\n" - "ro.product.first_api_level=24\n" - "ro.config.ringtone=Ring_Synth_04.ogg\n" - "ro.config.notification_sound=pixiedust.ogg\n" - "ro.carrier=unknown\n" - "ro.config.alarm_alert=Alarm_Classic.ogg\n" - "ro.setupwizard.require_network=ro.setupwizard.mode=OPTIONAL\n" - "ro.com.google.gmsversion=7.0_r7\n" - "dalvik.vm.heapgrowthlimit=256m\n" - "dalvik.vm.heapsize=512m\n" - "ro.mediatek.chip_ver=S01\n" - "ro.mediatek.platform=MT6755\n" - "ro.telephony.sim.count=2\n" - "persist.radio.default.sim=0\n" - "ro.feature_private_mode=true\n" - "ril.specific.sm_cause=0\n" - "bgw.current3gband=0\n" - "ril.external.md=0\n" - "ro.mtk_cam_lomo_support=1\n" - "ro.sf.hwrotation=0\n" - "ro.operator.optr=OP08\n" - "ro.operator.spec=SPEC0200\n" - "ro.operator.seg=SEGDEFAULT\n" - "persist.operator.optr=OP08\n" - "persist.operator.spec=SPEC0200\n" - "persist.operator.seg=SEGDEFAULT\n" - "persist.radio.fd.counter=150\n" - "persist.radio.fd.off.counter=50\n" - "persist.radio.fd.r8.counter=150\n" - "persist.radio.fd.off.r8.counter=50\n" - "drm.service.enabled=true\n" - "fmradio.driver.enable=1\n" - "ro.mtk_rebootmeta_support=0\n" - "mtk.eccci.c2k=enabled\n" - "ril.first.md=1\n" - "ril.flightmode.poweroffMD=0\n" - "ril.telephony.mode=0\n" - "dalvik.vm.mtk-stack-trace-file=/data/anr/mtk_traces.txt\n" - "mediatek.wlan.chip=CONSYS_MT6755\n" - "mediatek.wlan.module.postfix=_consys_mt6755\n" - "ril.radiooff.poweroffMD=0\n" - "ro.frp.pst=/dev/block/platform/mtk-msdc.0/11230000.msdc0/by-name/frp\n" - "ro.mtk_protocol1_rat_config=Lf/W/G\n" - "ro.mediatek.version.branch=alps-mp-n0.mp7\n" - "ro.mediatek.version.release=alps-mp-n0.mp7-V1.92_jrdsz6750.66.tm.n_P140\n" - "ro.mediatek.version.sdk=4\n" - "ro.num_md_protocol=2\n" - "persist.radio.multisim.config=ss\n" - "ro.mtk_besloudness_support=1\n" - "ro.mtk_wapi_support=1\n" - "ro.mtk_bt_support=1\n" - "ro.mtk_wappush_support=1\n" - "ro.mtk_agps_app=1\n" - "ro.mtk_audio_tuning_tool_ver=V2.2\n" - "ro.mtk_matv_analog_support=1\n" - "ro.mtk_wlan_support=1\n" - "ro.mtk_ipo_support=1\n" - "ro.mtk_gps_support=1\n" - "ro.mtk_omacp_support=1\n" - "ro.mtk_search_db_support=1\n" - "ro.mtk_dialer_search_support=1\n" - "ro.mtk_dhcpv6c_wifi=1\n" - "ro.have_aacencode_feature=1\n" - "ro.mtk_fd_support=1\n" - "ro.mtk_widevine_drm_l3_support=1\n" - "ro.mtk_disable_cap_switch=1\n" - "ro.mtk_eap_sim_aka=1\n" - "ro.mtk_fm_recording_support=1\n" - "ro.mtk_send_rr_support=1\n" - "ro.mtk_emmc_support=1\n" - "ro.mtk_tetheringipv6_support=1\n" - "ro.telephony.default_network=9\n" - "ro.mtk_shared_sdcard=1\n" - "ro.mtk_enable_md1=1\n" - "ro.mtk_afw_support=1\n" - "ro.mtk_aal_support=1\n" - "ro.mtk_pq_support=2\n" - "ro.mtk_pq_color_mode=1\n" - "ro.mtk_miravision_support=1\n" - "ro.mtk_blulight_def_support=1\n" - "ro.mtk_wfd_support=1\n" - "ro.mtk_wifi_mcc_support=1\n" - "ro.mtk_sim_hot_swap=1\n" - "ro.mtk_bip_scws=1\n" - "ro.mtk_world_phone_policy=0\n" - "ro.mtk_md_world_mode_support=1\n" - "ro.mtk_perfservice_support=1\n" - "ro.mtk_cam_mfb_support=3\n" - "ro.mtk_slow_motion_support=1\n" - "ro.mtk_lte_support=1\n" - "ro.sim_refresh_reset_by_modem=1\n" - "ro.mtk_external_sim_only_slots=0\n" - "ro.mtk_bg_power_saving_support=1\n" - "ro.mtk_bg_power_saving_ui=1\n" - "ro.have_aee_feature=1\n" - "ro.sim_me_lock_mode=0\n" - "ro.mtk_dual_mic_support=1\n" - "ro.mtk_is_tablet=0\n" - "ro.mtk_pow_perf_support=1\n" - "persist.mtk_nlp_switch_support=1\n" - "persist.mtk_ims_support=1\n" - "ro.mtk_multiple_ims_support=1\n" - "persist.mtk_wfc_support=1\n" - "persist.mtk_vilte_support=1\n" - "ro.mtk_vilte_ut_support=0\n" - "persist.mtk_ussi_support=1\n" - "wfd.dummy.enable=1\n" - "wfd.iframesize.level=0\n" - "ro.mediatek.project.path=device/jrdcsz/Mickey6TTMO\n" - "ro.mtk_trustonic_tee_support=1\n" - "persist.mtk.wcn.combo.chipid=-1\n" - "persist.mtk.wcn.patch.version=-1\n" - "persist.mtk.wcn.dynamic.dump=0\n" - "service.wcn.driver.ready=no\n" - "service.wcn.coredump.mode=0\n" - "persist.mtk.connsys.poweron.ctl=0\n" - "persist.mtk_epdg_support=1\n" - "ro.com.android.mobiledata=true\n" - "persist.radio.mobile.data=0,0\n" - "persist.meta.dumpdata=0\n" - "ro.mtk_deinterlace_support=1\n" - "ro.mtk_md_sbp_custom_value=8\n" - "ro.mtk_modem_monitor_support=1\n" - "persist.radio.mtk_ps2_rat=W/G\n" - "persist.radio.mtk_ps3_rat=G\n" - "ro.boot.opt_c2k_lte_mode=0\n" - "ro.boot.opt_md1_support=14\n" - "ro.boot.opt_lte_support=1\n" - "persist.log.tag.AT=I\n" - "persist.log.tag.RILMUXD=I\n" - "persist.log.tag.RILC-MTK=I\n" - "persist.log.tag.RILC=I\n" - "persist.log.tag.RfxMainThread=I\n" - "persist.log.tag.RfxRoot=I\n" - "persist.log.tag.RfxRilAdapter=I\n" - "persist.log.tag.RfxController=I\n" - "persist.log.tag.RILC-RP=I\n" - "persist.log.tag.RIL-DATA=D\n" - "ro.boot.opt_eccci_c2k=1\n" - "ro.boot.opt_using_default=1\n" - "mtk.vdec.waitkeyframeforplay=1\n" - "ro.sys.sdcardfs=1\n" - "persist.mtk.datashaping.support=1\n" - "persist.datashaping.alarmgroup=1\n" - "ro.media.maxmem=500000000\n" - "ro.feature_amazon_support=0\n" - "persist.mtk_rcs_ua_support=1\n" - "persist.mtk_uce_ua_support=1\n" - "persist.service.rcs.geolocation=1\n" - "persist.mtk_volte_support=1\n" - "persist.mtk.volte.enable=1\n" - "persist.sys.dalvik.vm.lib.2=libart.so\n" - "dalvik.vm.isa.arm64.variant=cortex-a53\n" - "dalvik.vm.isa.arm64.features=default\n" - "dalvik.vm.isa.arm.variant=cortex-a53\n" - "dalvik.vm.isa.arm.features=default\n" - "net.bt.name=Android\n" - "dalvik.vm.stack-trace-file=/data/anr/traces.txt\n" - "persist.sys.usb.config=\n" - "ro.expect.recovery_id=0x2f97b67aa16de7e155850b81d8d0b574e2e580c0000000000000000000000000\n", + .content = "\n" + "# begin build properties\n" + "# autogenerated by buildinfo.sh\n" + "ro.build.id=NRD90M\n" + "ro.build.display.id=Android N\n" + "ro.build.version.incremental=v6H7J-0\n" + "ro.build.version.sdk=24\n" + "ro.build.version.preview_sdk=0\n" + "ro.build.version.codename=REL\n" + "ro.build.version.all_codenames=REL\n" + "ro.build.version.release=7.0\n" + "ro.build.version.security_patch=2017-07-01\n" + "ro.build.version.base_os=\n" + "ro.build.date=Wed Aug 2 13:58:19 CST 2017\n" + "ro.build.date.utc=1501653499\n" + "ro.build.type=user\n" + "ro.build.user=android-bld\n" + "ro.build.host=Perso41\n" + "ro.build.tags=release-keys\n" + "ro.build.flavor=Mickey6TTMO-user\n" + "ro.product.model=5049W\n" + "ro.product.brand=TCL\n" + "ro.product.name=5049W\n" + "ro.product.device=Mickey6TTMO\n" + "ro.product.board=\n" + "# ro.product.cpu.abi and ro.product.cpu.abi2 are obsolete,\n" + "# use ro.product.cpu.abilist instead.\n" + "ro.product.cpu.abi=arm64-v8a\n" + "ro.product.cpu.abilist=arm64-v8a,armeabi-v7a,armeabi\n" + "ro.product.cpu.abilist32=armeabi-v7a,armeabi\n" + "ro.product.cpu.abilist64=arm64-v8a\n" + "ro.product.manufacturer=AlcatelOneTouch\n" + "ro.wifi.channels=\n" + "ro.board.platform=mt6750\n" + "# ro.build.product is obsolete; use ro.product.device\n" + "ro.build.product=Mickey6TTMO\n" + "# Do not try to parse description, fingerprint, or thumbprint\n" + "ro.build.description=Mickey6TTMO-user 7.0 NRD90M v6H7J-0 release-keys\n" + "ro.build.fingerprint=TCL/5049W/Mickey6TTMO:7.0/NRD90M/v6H7J-0:user/release-keys\n" + "ro.build.characteristics=default\n" + "persist.disable.temperature=false\n" + "ro.product.locales=\n" + "ro.product.display.model=5049W\n" + "ro.tct.sys.ver=Y6H7J0J0CM00\n" + "ro.tct.boot.ver=B6H7J0J0CM00\n" + "ro.tct.cust.ver=C6H7UMJ3CM00\n" + "ro.tct.reco.ver=R6H7J0J0CM00\n" + "# end build properties\n" + "#\n" + "#jrd sys properties\n" + "#\n" + "\n" + "Modem.FD.supported.for.perso=true\n" + "ro.product.locale.language=en\n" + "ro.product.locale.region=US\n" + "ro.com.google.clientidbase=android-alcatel\n" + "ro.com.google.clientidbase.am=android-tmobile-us\n" + "ro.com.google.clientidbase.ms=android-hms-tmobile-us\n" + "gsm.version.baseband=c1-00006-8909_GEN_PACK-1.32621.1\n" + "ro.def.software.svn=010 04\n" + "def.israel.on=false\n" + "def.settings.separate.volume=true\n" + "persist.sys.phone.minmatch.len=10\n" + "persist.sys.recovery.showtext=true\n" + "ro.mtk_oma_drm_support=1\n" + "ro.drm_popup_dialog=1\n" + "persist.sys.phone.assistedstat=false\n" + "ro.usb.product=T-Mobile Revvl\n" + "ro.x.wap.profile=http://www-ccpp.tcl-ta.com/files/5049W.xml\n" + "persist.sys.pwringtone.enable=1\n" + "persist.sys.ringtonemode=2\n" + "ro.config.power_on=Jumping_on_default.mp3\n" + "ro.config.power_off=\n" + "ro.config.ringtone=T-Jingle.mp3\n" + "ro.config.alarm_alert=Galactic.mp3\n" + "ro.bluetooth.name=T-Mobile Revvl\n" + "ro.config.notification_sound=Success.mp3\n" + "ro.setupwizard.require_network=\n" + "feature_tctfw_mtp_on=0\n" + "persist.radio.hotspot.support=0\n" + "ro_set_nl_cb_on=false\n" + "persist.sys.ssshot.threePointer=1\n" + "ro.headset.sound.mode=0\n" + "persist.sys.phone.refercountry=United States of America\n" + "persist.sys.phone.countrycode=1\n" + "persist.sys.phone.iddcode=011\n" + "persist.sys.phone.nddcode=1\n" + "persist.sys.phone.areasettings=Washington\n" + "persist.sys.phone.citycode=206\n" + "persist.sys.phone.numberlen=null\n" + "ro.config.number.format=false\n" + "ro.start.nextradio.service=true\n" + "ro.config.videocall.show=true\n" + "ecc.list.for.perso=911,112\n" + "ecc.list.for.perso.no_sim=000,110,118,119,999,112,911\n" + "ro.jrd.wfc.manager.operator=1\n" + "ro.tcl_sar_support=1\n" + "ro.def.software.version=H7JUMJ3\n" + "ro.config.support_softsim=0\n" + "persist.net.wo.keep_timer=300\n" + "persist.net.wo.dpd_timer=300\n" + "#\n" + "# from device/jrdcsz/Mickey6TTMO/system.prop\n" + "#\n" + "#\n" + "# system.prop for generic sdk\n" + "#\n" + "\n" + "rild.libpath=mtk-ril.so\n" + "rild.libargs=-d /dev/ttyC0\n" + "\n" + "\n" + "# MTK, Infinity, 20090720 {\n" + "wifi.interface=wlan0\n" + "# MTK, Infinity, 20090720 }\n" + "\n" + "# MTK, mtk03034, 20101210 {\n" + "ro.mediatek.wlan.wsc=1\n" + "# MTK, mtk03034 20101210}\n" + "# MTK, mtk03034, 20110318 {\n" + "ro.mediatek.wlan.p2p=1\n" + "# MTK, mtk03034 20110318}\n" + "\n" + "# MTK, mtk03034, 20101213 {\n" + "mediatek.wlan.ctia=0\n" + "# MTK, mtk03034 20101213}\n" + "\n" + "\n" + "#\n" + "wifi.tethering.interface=ap0\n" + "#\n" + "\n" + "#Modify by hua.lei@tcl.com for cts Tetst\n" + "#this value should be the same as Opengl Driver (Eg.3.2)\n" + "ro.opengles.version=196610\n" + "#ro.kernel.qemu=1\n" + "#ro.kernel.qemu.gles=0\n" + "\n" + "wifi.direct.interface=p2p0\n" + "dalvik.vm.heapgrowthlimit=256m\n" + "dalvik.vm.heapsize=512m\n" + "\n" + "# USB MTP WHQL\n" + "ro.sys.usb.mtp.whql.enable=0\n" + "\n" + "# Power off opt in IPO\n" + "sys.ipo.pwrdncap=2\n" + "\n" + "ro.sys.usb.storage.type=mtp\n" + "\n" + "# USB BICR function\n" + "ro.sys.usb.bicr=no\n" + "\n" + "# USB Charge only function\n" + "ro.sys.usb.charging.only=yes\n" + "\n" + "# audio\n" + "ro.camera.sound.forced=0\n" + "ro.audio.silent=0\n" + "\n" + "ro.zygote.preload.enable=0\n" + "\n" + "# temporary enables NAV bar (soft keys)\n" + "qemu.hw.mainkeys=0\n" + "\n" + "ro.kernel.zio=38,108,105,16\n" + "#ro.kernel.qemu=1\n" + "#ro.kernel.qemu.gles=0\n" + "#ro.boot.selinux=disable\n" + "\n" + "\n" + "ro.sf.lcd_density=480\n" + "\n" + "# performance\n" + "ro.mtk_perf_simple_start_win=1\n" + "ro.mtk_perf_fast_start_win=1\n" + "ro.mtk_perf_response_time=1\n" + "\n" + "# MAL\n" + "persist.mal.mode=0\n" + "\n" + "#add by kai.yan@tcl.com for Defect 4355270 at 20170315\n" + "persist.mtk_wfc_support=1\n" + "persist.mtk.wfc.enable=1\n" + "persist.dbg.wfc_avail_ovr=1\n" + "\n" + "#custom Dialer show video calling button\n" + "ro.config.videocall.show=false\n" + "\n" + "#\n" + "# ADDITIONAL_BUILD_PROPERTIES\n" + "#\n" + "ro.product.first_api_level=24\n" + "ro.config.ringtone=Ring_Synth_04.ogg\n" + "ro.config.notification_sound=pixiedust.ogg\n" + "ro.carrier=unknown\n" + "ro.config.alarm_alert=Alarm_Classic.ogg\n" + "ro.setupwizard.require_network=ro.setupwizard.mode=OPTIONAL\n" + "ro.com.google.gmsversion=7.0_r7\n" + "dalvik.vm.heapgrowthlimit=256m\n" + "dalvik.vm.heapsize=512m\n" + "ro.mediatek.chip_ver=S01\n" + "ro.mediatek.platform=MT6755\n" + "ro.telephony.sim.count=2\n" + "persist.radio.default.sim=0\n" + "ro.feature_private_mode=true\n" + "ril.specific.sm_cause=0\n" + "bgw.current3gband=0\n" + "ril.external.md=0\n" + "ro.mtk_cam_lomo_support=1\n" + "ro.sf.hwrotation=0\n" + "ro.operator.optr=OP08\n" + "ro.operator.spec=SPEC0200\n" + "ro.operator.seg=SEGDEFAULT\n" + "persist.operator.optr=OP08\n" + "persist.operator.spec=SPEC0200\n" + "persist.operator.seg=SEGDEFAULT\n" + "persist.radio.fd.counter=150\n" + "persist.radio.fd.off.counter=50\n" + "persist.radio.fd.r8.counter=150\n" + "persist.radio.fd.off.r8.counter=50\n" + "drm.service.enabled=true\n" + "fmradio.driver.enable=1\n" + "ro.mtk_rebootmeta_support=0\n" + "mtk.eccci.c2k=enabled\n" + "ril.first.md=1\n" + "ril.flightmode.poweroffMD=0\n" + "ril.telephony.mode=0\n" + "dalvik.vm.mtk-stack-trace-file=/data/anr/mtk_traces.txt\n" + "mediatek.wlan.chip=CONSYS_MT6755\n" + "mediatek.wlan.module.postfix=_consys_mt6755\n" + "ril.radiooff.poweroffMD=0\n" + "ro.frp.pst=/dev/block/platform/mtk-msdc.0/11230000.msdc0/by-name/frp\n" + "ro.mtk_protocol1_rat_config=Lf/W/G\n" + "ro.mediatek.version.branch=alps-mp-n0.mp7\n" + "ro.mediatek.version.release=alps-mp-n0.mp7-V1.92_jrdsz6750.66.tm.n_P140\n" + "ro.mediatek.version.sdk=4\n" + "ro.num_md_protocol=2\n" + "persist.radio.multisim.config=ss\n" + "ro.mtk_besloudness_support=1\n" + "ro.mtk_wapi_support=1\n" + "ro.mtk_bt_support=1\n" + "ro.mtk_wappush_support=1\n" + "ro.mtk_agps_app=1\n" + "ro.mtk_audio_tuning_tool_ver=V2.2\n" + "ro.mtk_matv_analog_support=1\n" + "ro.mtk_wlan_support=1\n" + "ro.mtk_ipo_support=1\n" + "ro.mtk_gps_support=1\n" + "ro.mtk_omacp_support=1\n" + "ro.mtk_search_db_support=1\n" + "ro.mtk_dialer_search_support=1\n" + "ro.mtk_dhcpv6c_wifi=1\n" + "ro.have_aacencode_feature=1\n" + "ro.mtk_fd_support=1\n" + "ro.mtk_widevine_drm_l3_support=1\n" + "ro.mtk_disable_cap_switch=1\n" + "ro.mtk_eap_sim_aka=1\n" + "ro.mtk_fm_recording_support=1\n" + "ro.mtk_send_rr_support=1\n" + "ro.mtk_emmc_support=1\n" + "ro.mtk_tetheringipv6_support=1\n" + "ro.telephony.default_network=9\n" + "ro.mtk_shared_sdcard=1\n" + "ro.mtk_enable_md1=1\n" + "ro.mtk_afw_support=1\n" + "ro.mtk_aal_support=1\n" + "ro.mtk_pq_support=2\n" + "ro.mtk_pq_color_mode=1\n" + "ro.mtk_miravision_support=1\n" + "ro.mtk_blulight_def_support=1\n" + "ro.mtk_wfd_support=1\n" + "ro.mtk_wifi_mcc_support=1\n" + "ro.mtk_sim_hot_swap=1\n" + "ro.mtk_bip_scws=1\n" + "ro.mtk_world_phone_policy=0\n" + "ro.mtk_md_world_mode_support=1\n" + "ro.mtk_perfservice_support=1\n" + "ro.mtk_cam_mfb_support=3\n" + "ro.mtk_slow_motion_support=1\n" + "ro.mtk_lte_support=1\n" + "ro.sim_refresh_reset_by_modem=1\n" + "ro.mtk_external_sim_only_slots=0\n" + "ro.mtk_bg_power_saving_support=1\n" + "ro.mtk_bg_power_saving_ui=1\n" + "ro.have_aee_feature=1\n" + "ro.sim_me_lock_mode=0\n" + "ro.mtk_dual_mic_support=1\n" + "ro.mtk_is_tablet=0\n" + "ro.mtk_pow_perf_support=1\n" + "persist.mtk_nlp_switch_support=1\n" + "persist.mtk_ims_support=1\n" + "ro.mtk_multiple_ims_support=1\n" + "persist.mtk_wfc_support=1\n" + "persist.mtk_vilte_support=1\n" + "ro.mtk_vilte_ut_support=0\n" + "persist.mtk_ussi_support=1\n" + "wfd.dummy.enable=1\n" + "wfd.iframesize.level=0\n" + "ro.mediatek.project.path=device/jrdcsz/Mickey6TTMO\n" + "ro.mtk_trustonic_tee_support=1\n" + "persist.mtk.wcn.combo.chipid=-1\n" + "persist.mtk.wcn.patch.version=-1\n" + "persist.mtk.wcn.dynamic.dump=0\n" + "service.wcn.driver.ready=no\n" + "service.wcn.coredump.mode=0\n" + "persist.mtk.connsys.poweron.ctl=0\n" + "persist.mtk_epdg_support=1\n" + "ro.com.android.mobiledata=true\n" + "persist.radio.mobile.data=0,0\n" + "persist.meta.dumpdata=0\n" + "ro.mtk_deinterlace_support=1\n" + "ro.mtk_md_sbp_custom_value=8\n" + "ro.mtk_modem_monitor_support=1\n" + "persist.radio.mtk_ps2_rat=W/G\n" + "persist.radio.mtk_ps3_rat=G\n" + "ro.boot.opt_c2k_lte_mode=0\n" + "ro.boot.opt_md1_support=14\n" + "ro.boot.opt_lte_support=1\n" + "persist.log.tag.AT=I\n" + "persist.log.tag.RILMUXD=I\n" + "persist.log.tag.RILC-MTK=I\n" + "persist.log.tag.RILC=I\n" + "persist.log.tag.RfxMainThread=I\n" + "persist.log.tag.RfxRoot=I\n" + "persist.log.tag.RfxRilAdapter=I\n" + "persist.log.tag.RfxController=I\n" + "persist.log.tag.RILC-RP=I\n" + "persist.log.tag.RIL-DATA=D\n" + "ro.boot.opt_eccci_c2k=1\n" + "ro.boot.opt_using_default=1\n" + "mtk.vdec.waitkeyframeforplay=1\n" + "ro.sys.sdcardfs=1\n" + "persist.mtk.datashaping.support=1\n" + "persist.datashaping.alarmgroup=1\n" + "ro.media.maxmem=500000000\n" + "ro.feature_amazon_support=0\n" + "persist.mtk_rcs_ua_support=1\n" + "persist.mtk_uce_ua_support=1\n" + "persist.service.rcs.geolocation=1\n" + "persist.mtk_volte_support=1\n" + "persist.mtk.volte.enable=1\n" + "persist.sys.dalvik.vm.lib.2=libart.so\n" + "dalvik.vm.isa.arm64.variant=cortex-a53\n" + "dalvik.vm.isa.arm64.features=default\n" + "dalvik.vm.isa.arm.variant=cortex-a53\n" + "dalvik.vm.isa.arm.features=default\n" + "net.bt.name=Android\n" + "dalvik.vm.stack-trace-file=/data/anr/traces.txt\n" + "persist.sys.usb.config=\n" + "ro.expect.recovery_id=0x2f97b67aa16de7e155850b81d8d0b574e2e580c0000000000000000000000000\n", }, { .path = "/sys/devices/system/cpu/kernel_max", @@ -438,29 +436,27 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpufreq/all_time_in_state", .size = 219, - .content = - "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\t\n" - "286000\t\t7\t\t7\t\t7\t\t\n" - "663000\t\t0\t\t0\t\t0\t\t\n" - "871000\t\t0\t\t0\t\t0\t\t\n" - "1027000\t\t0\t\t0\t\t0\t\t\n" - "1196000\t\t23\t\t23\t\t23\t\t\n" - "1352000\t\t31\t\t31\t\t31\t\t\n" - "1430000\t\t0\t\t0\t\t0\t\t\n" - "1508000\t\t4673\t\t4673\t\t4673\t\t\n", + .content = "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\t\n" + "286000\t\t7\t\t7\t\t7\t\t\n" + "663000\t\t0\t\t0\t\t0\t\t\n" + "871000\t\t0\t\t0\t\t0\t\t\n" + "1027000\t\t0\t\t0\t\t0\t\t\n" + "1196000\t\t23\t\t23\t\t23\t\t\n" + "1352000\t\t31\t\t31\t\t31\t\t\n" + "1430000\t\t0\t\t0\t\t0\t\t\n" + "1508000\t\t4673\t\t4673\t\t4673\t\t\n", }, { .path = "/sys/devices/system/cpu/cpufreq/current_in_state", .size = 664, - .content = - "CPU0:1508000=0 1430000=0 1352000=0 1196000=0 1027000=0 871000=0 663000=0 286000=0 \n" - "CPU1:1508000=0 1430000=0 1352000=0 1196000=0 1027000=0 871000=0 663000=0 286000=0 \n" - "CPU2:1508000=0 1430000=0 1352000=0 1196000=0 1027000=0 871000=0 663000=0 286000=0 \n" - "CPU3:1508000=0 1430000=0 1352000=0 1196000=0 1027000=0 871000=0 663000=0 286000=0 \n" - "CPU4:1508000=0 1430000=0 1352000=0 1196000=0 1027000=0 871000=0 663000=0 286000=0 \n" - "CPU5:1508000=0 1430000=0 1352000=0 1196000=0 1027000=0 871000=0 663000=0 286000=0 \n" - "CPU6:1508000=0 1430000=0 1352000=0 1196000=0 1027000=0 871000=0 663000=0 286000=0 \n" - "CPU7:1508000=0 1430000=0 1352000=0 1196000=0 1027000=0 871000=0 663000=0 286000=0 \n", + .content = "CPU0:1508000=0 1430000=0 1352000=0 1196000=0 1027000=0 871000=0 663000=0 286000=0 \n" + "CPU1:1508000=0 1430000=0 1352000=0 1196000=0 1027000=0 871000=0 663000=0 286000=0 \n" + "CPU2:1508000=0 1430000=0 1352000=0 1196000=0 1027000=0 871000=0 663000=0 286000=0 \n" + "CPU3:1508000=0 1430000=0 1352000=0 1196000=0 1027000=0 871000=0 663000=0 286000=0 \n" + "CPU4:1508000=0 1430000=0 1352000=0 1196000=0 1027000=0 871000=0 663000=0 286000=0 \n" + "CPU5:1508000=0 1430000=0 1352000=0 1196000=0 1027000=0 871000=0 663000=0 286000=0 \n" + "CPU6:1508000=0 1430000=0 1352000=0 1196000=0 1027000=0 871000=0 663000=0 286000=0 \n" + "CPU7:1508000=0 1430000=0 1352000=0 1196000=0 1027000=0 871000=0 663000=0 286000=0 \n", }, { .path = "/sys/devices/system/cpu/cpuidle/current_driver", @@ -475,19 +471,17 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cputopo/cpus_per_cluster", .size = 25, - .content = - "cluster0: f\n" - "cluster1: f0\n", + .content = "cluster0: f\n" + "cluster1: f0\n", }, { .path = "/sys/devices/system/cpu/cputopo/glbinfo", .size = 72, - .content = - "big/little arch: yes\n" - "nr_cups: 8\n" - "nr_clusters: 2\n" - "cluster0: f\n" - "cluster1: f0\n", + .content = "big/little arch: yes\n" + "nr_cups: 8\n" + "nr_clusters: 2\n" + "cluster0: f\n" + "cluster1: f0\n", }, { .path = "/sys/devices/system/cpu/cputopo/is_big_little", @@ -567,15 +561,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/time_in_state", .size = 88, - .content = - "1508000 5013\n" - "1430000 12\n" - "1352000 186\n" - "1196000 25\n" - "1027000 0\n" - "871000 12\n" - "663000 28\n" - "286000 155\n", + .content = "1508000 5013\n" + "1430000 12\n" + "1352000 186\n" + "1196000 25\n" + "1027000 0\n" + "871000 12\n" + "663000 28\n" + "286000 155\n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/total_trans", @@ -677,7 +670,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 54, .content = "ondemand userspace powersave interactive performance \n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -2821,6 +2814,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.wfd.security.image", .value = "1", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/alldocube-iwork8.cc b/test/mock/alldocube-iwork8.cc index aa8f4c51..ab19e6c5 100644 --- a/test/mock/alldocube-iwork8.cc +++ b/test/mock/alldocube-iwork8.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(4, cpuinfo_get_processors_count()); @@ -212,8 +211,10 @@ TEST(PACKAGES, non_null) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Intel Atom x5-Z8350", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Intel Atom x5-Z8350", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -536,8 +537,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -588,8 +591,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -640,8 +645,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/alldocube-iwork8.h b/test/mock/alldocube-iwork8.h index fec63e3a..b6baa774 100644 --- a/test/mock/alldocube-iwork8.h +++ b/test/mock/alldocube-iwork8.h @@ -398,32 +398,32 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/modalias", .size = 446, - .content = "x86cpu:vendor:0000:family:0006:model:004C:feature:,0000,0001,0002,0003,0004,0005,0006,0007,0008,0009,000B,000C,000D,000E,000F,0010,0011,0013,0015,0016,0017,0018,0019,001A,001B,001C,001D,001F,002B,0034,003B,003D,0068,006B,006C,006D,006F,0070,0072,0074,0075,0076,0078,007C,007E,0080,0081,0082,0083,0084,0085,0087,0088,0089,008D,008E,008F,0093,0094,0096,0097,0098,0099,009E,00C0,00C8,00E0,00E1,00E3,00E7,0100,0101,0102,0103,0104,0121,0127,0129,012D\n", + .content = + "x86cpu:vendor:0000:family:0006:model:004C:feature:,0000,0001,0002,0003,0004,0005,0006,0007,0008,0009,000B,000C,000D,000E,000F,0010,0011,0013,0015,0016,0017,0018,0019,001A,001B,001C,001D,001F,002B,0034,003B,003D,0068,006B,006C,006D,006F,0070,0072,0074,0075,0076,0078,007C,007E,0080,0081,0082,0083,0084,0085,0087,0088,0089,008D,008E,008F,0093,0094,0096,0097,0098,0099,009E,00C0,00C8,00E0,00E1,00E3,00E7,0100,0101,0102,0103,0104,0121,0127,0129,012D\n", }, { .path = "/sys/devices/system/cpu/cpufreq/all_time_in_state", .size = 538, - .content = - "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\t\n" - "480000\t\t13328\t\t13328\t\t13328\t\t13328\t\t\n" - "560000\t\t179\t\t179\t\t179\t\t179\t\t\n" - "640000\t\t78\t\t78\t\t78\t\t78\t\t\n" - "720000\t\t69\t\t69\t\t69\t\t69\t\t\n" - "800000\t\t63\t\t63\t\t63\t\t63\t\t\n" - "880000\t\t99\t\t99\t\t99\t\t99\t\t\n" - "960000\t\t30\t\t30\t\t30\t\t30\t\t\n" - "1040000\t\t19\t\t19\t\t19\t\t19\t\t\n" - "1120000\t\t56\t\t56\t\t56\t\t56\t\t\n" - "1200000\t\t26\t\t26\t\t26\t\t26\t\t\n" - "1280000\t\t6\t\t6\t\t6\t\t6\t\t\n" - "1360000\t\t26\t\t26\t\t26\t\t26\t\t\n" - "1440000\t\t13\t\t13\t\t13\t\t13\t\t\n" - "1520000\t\t19\t\t19\t\t19\t\t19\t\t\n" - "1600000\t\t20\t\t20\t\t20\t\t20\t\t\n" - "1680000\t\t20\t\t20\t\t20\t\t20\t\t\n" - "1760000\t\t28\t\t28\t\t28\t\t28\t\t\n" - "1840000\t\t23\t\t23\t\t23\t\t23\t\t\n" - "1920000\t\t4893\t\t4893\t\t4893\t\t4893\t\t\n", + .content = "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\t\n" + "480000\t\t13328\t\t13328\t\t13328\t\t13328\t\t\n" + "560000\t\t179\t\t179\t\t179\t\t179\t\t\n" + "640000\t\t78\t\t78\t\t78\t\t78\t\t\n" + "720000\t\t69\t\t69\t\t69\t\t69\t\t\n" + "800000\t\t63\t\t63\t\t63\t\t63\t\t\n" + "880000\t\t99\t\t99\t\t99\t\t99\t\t\n" + "960000\t\t30\t\t30\t\t30\t\t30\t\t\n" + "1040000\t\t19\t\t19\t\t19\t\t19\t\t\n" + "1120000\t\t56\t\t56\t\t56\t\t56\t\t\n" + "1200000\t\t26\t\t26\t\t26\t\t26\t\t\n" + "1280000\t\t6\t\t6\t\t6\t\t6\t\t\n" + "1360000\t\t26\t\t26\t\t26\t\t26\t\t\n" + "1440000\t\t13\t\t13\t\t13\t\t13\t\t\n" + "1520000\t\t19\t\t19\t\t19\t\t19\t\t\n" + "1600000\t\t20\t\t20\t\t20\t\t20\t\t\n" + "1680000\t\t20\t\t20\t\t20\t\t20\t\t\n" + "1760000\t\t28\t\t28\t\t28\t\t28\t\t\n" + "1840000\t\t23\t\t23\t\t23\t\t23\t\t\n" + "1920000\t\t4893\t\t4893\t\t4893\t\t4893\t\t\n", }, { .path = "/sys/devices/system/cpu/cpuidle/current_driver", @@ -463,7 +463,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies", .size = 146, - .content = "1920000 1840000 1760000 1680000 1600000 1520000 1440000 1360000 1280000 1200000 1120000 1040000 960000 880000 800000 720000 640000 560000 480000 \n", + .content = + "1920000 1840000 1760000 1680000 1600000 1520000 1440000 1360000 1280000 1200000 1120000 1040000 960000 880000 800000 720000 640000 560000 480000 \n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors", @@ -493,26 +494,25 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 207, - .content = - "1920000 4893\n" - "1840000 23\n" - "1760000 28\n" - "1680000 20\n" - "1600000 20\n" - "1520000 19\n" - "1440000 13\n" - "1360000 26\n" - "1280000 6\n" - "1200000 26\n" - "1120000 56\n" - "1040000 19\n" - "960000 30\n" - "880000 99\n" - "800000 63\n" - "720000 69\n" - "640000 78\n" - "560000 179\n" - "480000 13422\n", + .content = "1920000 4893\n" + "1840000 23\n" + "1760000 28\n" + "1680000 20\n" + "1600000 20\n" + "1520000 19\n" + "1440000 13\n" + "1360000 26\n" + "1280000 6\n" + "1200000 26\n" + "1120000 56\n" + "1040000 19\n" + "960000 30\n" + "880000 99\n" + "800000 63\n" + "720000 69\n" + "640000 78\n" + "560000 179\n" + "480000 13422\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -723,7 +723,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_frequencies", .size = 146, - .content = "1920000 1840000 1760000 1680000 1600000 1520000 1440000 1360000 1280000 1200000 1120000 1040000 960000 880000 800000 720000 640000 560000 480000 \n", + .content = + "1920000 1840000 1760000 1680000 1600000 1520000 1440000 1360000 1280000 1200000 1120000 1040000 960000 880000 800000 720000 640000 560000 480000 \n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_governors", @@ -753,26 +754,25 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 207, - .content = - "1920000 4893\n" - "1840000 23\n" - "1760000 28\n" - "1680000 20\n" - "1600000 20\n" - "1520000 19\n" - "1440000 13\n" - "1360000 26\n" - "1280000 6\n" - "1200000 26\n" - "1120000 56\n" - "1040000 19\n" - "960000 30\n" - "880000 99\n" - "800000 63\n" - "720000 69\n" - "640000 78\n" - "560000 179\n" - "480000 13594\n", + .content = "1920000 4893\n" + "1840000 23\n" + "1760000 28\n" + "1680000 20\n" + "1600000 20\n" + "1520000 19\n" + "1440000 13\n" + "1360000 26\n" + "1280000 6\n" + "1200000 26\n" + "1120000 56\n" + "1040000 19\n" + "960000 30\n" + "880000 99\n" + "800000 63\n" + "720000 69\n" + "640000 78\n" + "560000 179\n" + "480000 13594\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -983,7 +983,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_frequencies", .size = 146, - .content = "1920000 1840000 1760000 1680000 1600000 1520000 1440000 1360000 1280000 1200000 1120000 1040000 960000 880000 800000 720000 640000 560000 480000 \n", + .content = + "1920000 1840000 1760000 1680000 1600000 1520000 1440000 1360000 1280000 1200000 1120000 1040000 960000 880000 800000 720000 640000 560000 480000 \n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_governors", @@ -1013,26 +1014,25 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 207, - .content = - "1920000 4893\n" - "1840000 23\n" - "1760000 28\n" - "1680000 20\n" - "1600000 20\n" - "1520000 19\n" - "1440000 13\n" - "1360000 26\n" - "1280000 6\n" - "1200000 26\n" - "1120000 56\n" - "1040000 19\n" - "960000 30\n" - "880000 99\n" - "800000 63\n" - "720000 69\n" - "640000 78\n" - "560000 179\n" - "480000 13767\n", + .content = "1920000 4893\n" + "1840000 23\n" + "1760000 28\n" + "1680000 20\n" + "1600000 20\n" + "1520000 19\n" + "1440000 13\n" + "1360000 26\n" + "1280000 6\n" + "1200000 26\n" + "1120000 56\n" + "1040000 19\n" + "960000 30\n" + "880000 99\n" + "800000 63\n" + "720000 69\n" + "640000 78\n" + "560000 179\n" + "480000 13767\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -1042,28 +1042,27 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/trans_table", .size = 4057, - .content = - " From : To\n" - " : 1920000 1840000 1760000 1680000 1600000 1520000 1440000 1360000 1280000 1200000 1120000 1040000 960000 880000 800000 720000 640000 560000 480000 \n" - " 1920000: 0 6 7 3 4 3 4 5 1 4 8 5 6 7 7 3 5 3 35 \n" - " 1840000: 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 \n" - " 1760000: 2 2 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 \n" - " 1680000: 2 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 \n" - " 1600000: 2 0 0 1 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 \n" - " 1520000: 1 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 2 0 \n" - " 1440000: 4 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 \n" - " 1360000: 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 1 1 \n" - " 1280000: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \n" - " 1200000: 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 \n" - " 1120000: 3 0 0 0 0 0 0 0 0 1 0 1 1 4 0 0 1 0 1 \n" - " 1040000: 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 0 1 \n" - " 960000: 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 2 2 0 1 \n" - " 880000: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 5 1 3 1 6 \n" - " 800000: 1 0 0 0 0 0 0 0 0 0 0 0 0 3 0 2 1 2 6 \n" - " 720000: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 5 3 \n" - " 640000: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 2 10 \n" - " 560000: 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 20 \n" - " 480000: 78 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 0 \n", + .content = " From : To\n" + " : 1920000 1840000 1760000 1680000 1600000 1520000 1440000 1360000 1280000 1200000 1120000 1040000 960000 880000 800000 720000 640000 560000 480000 \n" + " 1920000: 0 6 7 3 4 3 4 5 1 4 8 5 6 7 7 3 5 3 35 \n" + " 1840000: 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 \n" + " 1760000: 2 2 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 \n" + " 1680000: 2 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 \n" + " 1600000: 2 0 0 1 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 \n" + " 1520000: 1 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 2 0 \n" + " 1440000: 4 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 \n" + " 1360000: 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 1 1 \n" + " 1280000: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \n" + " 1200000: 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 \n" + " 1120000: 3 0 0 0 0 0 0 0 0 1 0 1 1 4 0 0 1 0 1 \n" + " 1040000: 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 0 1 \n" + " 960000: 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 2 2 0 1 \n" + " 880000: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 5 1 3 1 6 \n" + " 800000: 1 0 0 0 0 0 0 0 0 0 0 0 0 3 0 2 1 2 6 \n" + " 720000: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 5 3 \n" + " 640000: 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 2 10 \n" + " 560000: 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 20 \n" + " 480000: 78 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 0 \n", }, { .path = "/sys/devices/system/cpu/cpu2/topology/core_id", @@ -1238,7 +1237,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_frequencies", .size = 146, - .content = "1920000 1840000 1760000 1680000 1600000 1520000 1440000 1360000 1280000 1200000 1120000 1040000 960000 880000 800000 720000 640000 560000 480000 \n", + .content = + "1920000 1840000 1760000 1680000 1600000 1520000 1440000 1360000 1280000 1200000 1120000 1040000 960000 880000 800000 720000 640000 560000 480000 \n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_governors", @@ -1268,26 +1268,25 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 207, - .content = - "1920000 4912\n" - "1840000 23\n" - "1760000 28\n" - "1680000 20\n" - "1600000 20\n" - "1520000 19\n" - "1440000 13\n" - "1360000 26\n" - "1280000 6\n" - "1200000 26\n" - "1120000 56\n" - "1040000 19\n" - "960000 30\n" - "880000 99\n" - "800000 63\n" - "720000 69\n" - "640000 78\n" - "560000 187\n" - "480000 16528\n", + .content = "1920000 4912\n" + "1840000 23\n" + "1760000 28\n" + "1680000 20\n" + "1600000 20\n" + "1520000 19\n" + "1440000 13\n" + "1360000 26\n" + "1280000 6\n" + "1200000 26\n" + "1120000 56\n" + "1040000 19\n" + "960000 30\n" + "880000 99\n" + "800000 63\n" + "720000 69\n" + "640000 78\n" + "560000 187\n" + "480000 16528\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -1470,7 +1469,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 3, .content = "16\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -2358,6 +2357,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.driver.status", .value = "unloaded", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/atm7029b-tablet.cc b/test/mock/atm7029b-tablet.cc index 3ae59ce6..904a862f 100644 --- a/test/mock/atm7029b-tablet.cc +++ b/test/mock/atm7029b-tablet.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(4, cpuinfo_get_processors_count()); @@ -208,8 +207,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Actions ATM7029B", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Actions ATM7029B", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -400,8 +401,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -452,8 +455,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -504,8 +509,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/atm7029b-tablet.h b/test/mock/atm7029b-tablet.h index 59b5c664..4ac1962e 100644 --- a/test/mock/atm7029b-tablet.h +++ b/test/mock/atm7029b-tablet.h @@ -2,19 +2,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 263, - .content = - "Processor\t: ARMv7 Processor rev 1 (v7l)\n" - "processor\t: 0\n" - "BogoMIPS\t: 1022.18\n" - "\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x0\n" - "\n" - "Hardware\t: gs702c\n" - "Revision\t: 0000\n" - "Serial\t\t: 0000000000000000\n", + .content = "Processor\t: ARMv7 Processor rev 1 (v7l)\n" + "processor\t: 0\n" + "BogoMIPS\t: 1022.18\n" + "\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x0\n" + "\n" + "Hardware\t: gs702c\n" + "Revision\t: 0000\n" + "Serial\t\t: 0000000000000000\n", }, { .path = "/system/build.prop", @@ -267,14 +266,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 77, - .content = - "288000 147856\n" - "732000 843\n" - "948000 0\n" - "1020000 0\n" - "1104000 7945\n" - "1260000 0\n" - "1320000 0\n", + .content = "288000 147856\n" + "732000 843\n" + "948000 0\n" + "1020000 0\n" + "1104000 7945\n" + "1260000 0\n" + "1320000 0\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -311,7 +309,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "0\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -1271,6 +1269,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.driver.status", .value = "ok", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/blu-r1-hd.cc b/test/mock/blu-r1-hd.cc index 4d6037d6..65da9e2b 100644 --- a/test/mock/blu-r1-hd.cc +++ b/test/mock/blu-r1-hd.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(4, cpuinfo_get_processors_count()); @@ -212,8 +211,10 @@ TEST(PACKAGES, non_null) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("MediaTek MT6735", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "MediaTek MT6735", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -404,8 +405,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -456,8 +459,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -508,8 +513,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/blu-r1-hd.h b/test/mock/blu-r1-hd.h index 743fa1d0..a15ee20c 100644 --- a/test/mock/blu-r1-hd.h +++ b/test/mock/blu-r1-hd.h @@ -352,25 +352,23 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpufreq/all_time_in_state", .size = 223, - .content = - "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\t\n" - "299000\t\t665\t\t665\t\t665\t\t665\t\t\n" - "442000\t\t8\t\t8\t\t8\t\t8\t\t\n" - "598000\t\t0\t\t0\t\t0\t\t0\t\t\n" - "819000\t\t42\t\t42\t\t42\t\t42\t\t\n" - "1040000\t\t0\t\t0\t\t0\t\t0\t\t\n" - "1170000\t\t4\t\t4\t\t4\t\t4\t\t\n" - "1235000\t\t0\t\t0\t\t0\t\t0\t\t\n" - "1300000\t\t362\t\t362\t\t362\t\t362\t\t\n", + .content = "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\t\n" + "299000\t\t665\t\t665\t\t665\t\t665\t\t\n" + "442000\t\t8\t\t8\t\t8\t\t8\t\t\n" + "598000\t\t0\t\t0\t\t0\t\t0\t\t\n" + "819000\t\t42\t\t42\t\t42\t\t42\t\t\n" + "1040000\t\t0\t\t0\t\t0\t\t0\t\t\n" + "1170000\t\t4\t\t4\t\t4\t\t4\t\t\n" + "1235000\t\t0\t\t0\t\t0\t\t0\t\t\n" + "1300000\t\t362\t\t362\t\t362\t\t362\t\t\n", }, { .path = "/sys/devices/system/cpu/cpufreq/current_in_state", .size = 328, - .content = - "CPU0:1300000=0 1235000=0 1170000=0 1040000=0 819000=0 598000=0 442000=0 299000=0 \n" - "CPU1:1300000=0 1235000=0 1170000=0 1040000=0 819000=0 598000=0 442000=0 299000=0 \n" - "CPU2:1300000=0 1235000=0 1170000=0 1040000=0 819000=0 598000=0 442000=0 299000=0 \n" - "CPU3:1300000=0 1235000=0 1170000=0 1040000=0 819000=0 598000=0 442000=0 299000=0 \n", + .content = "CPU0:1300000=0 1235000=0 1170000=0 1040000=0 819000=0 598000=0 442000=0 299000=0 \n" + "CPU1:1300000=0 1235000=0 1170000=0 1040000=0 819000=0 598000=0 442000=0 299000=0 \n" + "CPU2:1300000=0 1235000=0 1170000=0 1040000=0 819000=0 598000=0 442000=0 299000=0 \n" + "CPU3:1300000=0 1235000=0 1170000=0 1040000=0 819000=0 598000=0 442000=0 299000=0 \n", }, { .path = "/sys/devices/system/cpu/cpuidle/current_driver", @@ -390,11 +388,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cputopo/glbinfo", .size = 58, - .content = - "big/little arch: no\n" - "nr_cups: 4\n" - "nr_clusters: 1\n" - "cluster0: f\n", + .content = "big/little arch: no\n" + "nr_cups: 4\n" + "nr_clusters: 1\n" + "cluster0: f\n", }, { .path = "/sys/devices/system/cpu/cputopo/is_big_little", @@ -469,15 +466,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 81, - .content = - "1300000 470\n" - "1235000 0\n" - "1170000 4\n" - "1040000 0\n" - "819000 42\n" - "598000 0\n" - "442000 8\n" - "299000 665\n", + .content = "1300000 470\n" + "1235000 0\n" + "1170000 4\n" + "1040000 0\n" + "819000 42\n" + "598000 0\n" + "442000 8\n" + "299000 665\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -587,15 +583,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 81, - .content = - "1300000 693\n" - "1235000 0\n" - "1170000 4\n" - "1040000 2\n" - "819000 42\n" - "598000 0\n" - "442000 8\n" - "299000 665\n", + .content = "1300000 693\n" + "1235000 0\n" + "1170000 4\n" + "1040000 2\n" + "819000 42\n" + "598000 0\n" + "442000 8\n" + "299000 665\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -647,7 +642,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 3, .content = "02\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ @@ -1992,6 +1987,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wifi.tethering.interface", .value = "ap0", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/galaxy-a3-2016-eu.cc b/test/mock/galaxy-a3-2016-eu.cc index b30f005c..0e630666 100644 --- a/test/mock/galaxy-a3-2016-eu.cc +++ b/test/mock/galaxy-a3-2016-eu.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(4, cpuinfo_get_processors_count()); @@ -208,8 +207,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Samsung Exynos 7578", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Samsung Exynos 7578", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -251,59 +252,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -428,8 +429,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -480,8 +483,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -532,8 +537,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/galaxy-a3-2016-eu.h b/test/mock/galaxy-a3-2016-eu.h index 32922d46..b70416e0 100644 --- a/test/mock/galaxy-a3-2016-eu.h +++ b/test/mock/galaxy-a3-2016-eu.h @@ -227,20 +227,19 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpufreq/all_time_in_state", .size = 301, - .content = - "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\t\n" - "400000\t\t0\t\t0\t\t0\t\t0\t\t\n" - "500000\t\t0\t\t0\t\t0\t\t0\t\t\n" - "600000\t\t0\t\t0\t\t0\t\t0\t\t\n" - "700000\t\t0\t\t0\t\t0\t\t0\t\t\n" - "800000\t\t2\t\t2\t\t2\t\t2\t\t\n" - "900000\t\t0\t\t0\t\t0\t\t0\t\t\n" - "1000000\t\t0\t\t0\t\t0\t\t0\t\t\n" - "1100000\t\t0\t\t0\t\t0\t\t0\t\t\n" - "1200000\t\t0\t\t0\t\t0\t\t0\t\t\n" - "1300000\t\t0\t\t0\t\t0\t\t0\t\t\n" - "1400000\t\t0\t\t0\t\t0\t\t0\t\t\n" - "1500000\t\t3009\t\t3009\t\t3009\t\t3009\t\t\n", + .content = "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\t\n" + "400000\t\t0\t\t0\t\t0\t\t0\t\t\n" + "500000\t\t0\t\t0\t\t0\t\t0\t\t\n" + "600000\t\t0\t\t0\t\t0\t\t0\t\t\n" + "700000\t\t0\t\t0\t\t0\t\t0\t\t\n" + "800000\t\t2\t\t2\t\t2\t\t2\t\t\n" + "900000\t\t0\t\t0\t\t0\t\t0\t\t\n" + "1000000\t\t0\t\t0\t\t0\t\t0\t\t\n" + "1100000\t\t0\t\t0\t\t0\t\t0\t\t\n" + "1200000\t\t0\t\t0\t\t0\t\t0\t\t\n" + "1300000\t\t0\t\t0\t\t0\t\t0\t\t\n" + "1400000\t\t0\t\t0\t\t0\t\t0\t\t\n" + "1500000\t\t3009\t\t3009\t\t3009\t\t3009\t\t\n", }, { .path = "/sys/devices/system/cpu/cpuidle/current_driver", @@ -280,10 +279,9 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/clusterhotplug/time_in_state", .size = 19, - .content = - "H0 32491\n" - "H1 0\n" - "H2 0\n", + .content = "H0 32491\n" + "H1 0\n" + "H2 0\n", }, { .path = "/sys/devices/system/cpu/clusterhotplug/up_freq", @@ -328,7 +326,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies", .size = 91, - .content = "1500000 1400000 1300000 1200000 1100000 1000000 900000 800000 700000 600000 500000 400000 \n", + .content = + "1500000 1400000 1300000 1200000 1100000 1000000 900000 800000 700000 600000 500000 400000 \n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors", @@ -358,19 +357,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 117, - .content = - "1500000 3092\n" - "1400000 0\n" - "1300000 0\n" - "1200000 0\n" - "1100000 0\n" - "1000000 0\n" - "900000 0\n" - "800000 2\n" - "700000 0\n" - "600000 0\n" - "500000 0\n" - "400000 0\n", + .content = "1500000 3092\n" + "1400000 0\n" + "1300000 0\n" + "1200000 0\n" + "1100000 0\n" + "1000000 0\n" + "900000 0\n" + "800000 2\n" + "700000 0\n" + "600000 0\n" + "500000 0\n" + "400000 0\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -435,7 +433,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_frequencies", .size = 91, - .content = "1500000 1400000 1300000 1200000 1100000 1000000 900000 800000 700000 600000 500000 400000 \n", + .content = + "1500000 1400000 1300000 1200000 1100000 1000000 900000 800000 700000 600000 500000 400000 \n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_governors", @@ -465,19 +464,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 119, - .content = - "1500000 3166\n" - "1400000 4\n" - "1300000 0\n" - "1200000 4\n" - "1100000 10\n" - "1000000 2\n" - "900000 53\n" - "800000 2\n" - "700000 0\n" - "600000 4\n" - "500000 1\n" - "400000 5\n", + .content = "1500000 3166\n" + "1400000 4\n" + "1300000 0\n" + "1200000 4\n" + "1100000 10\n" + "1000000 2\n" + "900000 53\n" + "800000 2\n" + "700000 0\n" + "600000 4\n" + "500000 1\n" + "400000 5\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -542,7 +540,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_frequencies", .size = 91, - .content = "1500000 1400000 1300000 1200000 1100000 1000000 900000 800000 700000 600000 500000 400000 \n", + .content = + "1500000 1400000 1300000 1200000 1100000 1000000 900000 800000 700000 600000 500000 400000 \n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_governors", @@ -572,19 +571,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 120, - .content = - "1500000 3237\n" - "1400000 6\n" - "1300000 0\n" - "1200000 19\n" - "1100000 19\n" - "1000000 6\n" - "900000 95\n" - "800000 2\n" - "700000 7\n" - "600000 6\n" - "500000 1\n" - "400000 5\n", + .content = "1500000 3237\n" + "1400000 6\n" + "1300000 0\n" + "1200000 19\n" + "1100000 19\n" + "1000000 6\n" + "900000 95\n" + "800000 2\n" + "700000 7\n" + "600000 6\n" + "500000 1\n" + "400000 5\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -649,7 +647,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_frequencies", .size = 91, - .content = "1500000 1400000 1300000 1200000 1100000 1000000 900000 800000 700000 600000 500000 400000 \n", + .content = + "1500000 1400000 1300000 1200000 1100000 1000000 900000 800000 700000 600000 500000 400000 \n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_governors", @@ -679,19 +678,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 123, - .content = - "1500000 3296\n" - "1400000 17\n" - "1300000 8\n" - "1200000 21\n" - "1100000 23\n" - "1000000 6\n" - "900000 148\n" - "800000 2\n" - "700000 7\n" - "600000 6\n" - "500000 11\n" - "400000 6\n", + .content = "1500000 3296\n" + "1400000 17\n" + "1300000 8\n" + "1200000 21\n" + "1100000 23\n" + "1000000 6\n" + "900000 148\n" + "800000 2\n" + "700000 7\n" + "600000 6\n" + "500000 11\n" + "400000 6\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -728,7 +726,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "3\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -2368,6 +2366,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.driver.status", .value = "ok", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/galaxy-a8-2016-duos.cc b/test/mock/galaxy-a8-2016-duos.cc index 1e546e9b..6c58790f 100644 --- a/test/mock/galaxy-a8-2016-duos.cc +++ b/test/mock/galaxy-a8-2016-duos.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(8, cpuinfo_get_processors_count()); @@ -294,8 +293,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Qualcomm MSM8939", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Qualcomm MSM8939", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -486,8 +487,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -538,8 +541,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -597,8 +602,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/galaxy-a8-2016-duos.h b/test/mock/galaxy-a8-2016-duos.h index 9ebe1a10..084dd2a8 100644 --- a/test/mock/galaxy-a8-2016-duos.h +++ b/test/mock/galaxy-a8-2016-duos.h @@ -375,28 +375,27 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpufreq/all_time_in_state", .size = 905, - .content = - "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\t\n" - "200000\t\t0\t\t0\t\t0\t\t0\t\t2\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "249600\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "345600\t\t0\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "400000\t\t0\t\t0\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "422400\t\t0\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "499200\t\t344\t\t0\t\t0\t\t0\t\t21\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "533333\t\t25\t\t0\t\t0\t\t0\t\t6\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "652800\t\t18\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "729600\t\t11\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "800000\t\t0\t\t0\t\t0\t\t0\t\t134\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "806400\t\t0\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "883200\t\t10\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "960000\t\t68\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "998400\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t119\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1036800\t\t51\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1113600\t\t63\t\t0\t\t0\t\t0\t\t3828\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1209600\t\t19\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1267200\t\t54\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1344000\t\t268\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1459200\t\t3179\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n", + .content = "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\t\n" + "200000\t\t0\t\t0\t\t0\t\t0\t\t2\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "249600\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "345600\t\t0\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "400000\t\t0\t\t0\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "422400\t\t0\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "499200\t\t344\t\t0\t\t0\t\t0\t\t21\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "533333\t\t25\t\t0\t\t0\t\t0\t\t6\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "652800\t\t18\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "729600\t\t11\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "800000\t\t0\t\t0\t\t0\t\t0\t\t134\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "806400\t\t0\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "883200\t\t10\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "960000\t\t68\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "998400\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t119\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "1036800\t\t51\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "1113600\t\t63\t\t0\t\t0\t\t0\t\t3828\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "1209600\t\t19\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "1267200\t\t54\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "1344000\t\t268\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "1459200\t\t3179\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n", }, { .path = "/sys/devices/system/cpu/cpufreq/current_in_state", @@ -446,7 +445,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies", .size = 133, - .content = "200000 345600 400000 422400 499200 533333 652800 729600 800000 806400 883200 960000 1036800 1113600 1209600 1267200 1344000 1459200 \n", + .content = + "200000 345600 400000 422400 499200 533333 652800 729600 800000 806400 883200 960000 1036800 1113600 1209600 1267200 1344000 1459200 \n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors", @@ -481,25 +481,24 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 184, - .content = - "200000 0\n" - "345600 0\n" - "400000 0\n" - "422400 0\n" - "499200 344\n" - "533333 25\n" - "652800 18\n" - "729600 11\n" - "800000 0\n" - "806400 0\n" - "883200 10\n" - "960000 68\n" - "1036800 51\n" - "1113600 63\n" - "1209600 19\n" - "1267200 54\n" - "1344000 268\n" - "1459200 3277\n", + .content = "200000 0\n" + "345600 0\n" + "400000 0\n" + "422400 0\n" + "499200 344\n" + "533333 25\n" + "652800 18\n" + "729600 11\n" + "800000 0\n" + "806400 0\n" + "883200 10\n" + "960000 68\n" + "1036800 51\n" + "1113600 63\n" + "1209600 19\n" + "1267200 54\n" + "1344000 268\n" + "1459200 3277\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -569,7 +568,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_frequencies", .size = 133, - .content = "200000 345600 400000 422400 499200 533333 652800 729600 800000 806400 883200 960000 1036800 1113600 1209600 1267200 1344000 1459200 \n", + .content = + "200000 345600 400000 422400 499200 533333 652800 729600 800000 806400 883200 960000 1036800 1113600 1209600 1267200 1344000 1459200 \n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_governors", @@ -604,25 +604,24 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 184, - .content = - "200000 0\n" - "345600 0\n" - "400000 0\n" - "422400 0\n" - "499200 360\n" - "533333 25\n" - "652800 18\n" - "729600 11\n" - "800000 0\n" - "806400 0\n" - "883200 10\n" - "960000 85\n" - "1036800 59\n" - "1113600 89\n" - "1209600 30\n" - "1267200 54\n" - "1344000 293\n" - "1459200 3341\n", + .content = "200000 0\n" + "345600 0\n" + "400000 0\n" + "422400 0\n" + "499200 360\n" + "533333 25\n" + "652800 18\n" + "729600 11\n" + "800000 0\n" + "806400 0\n" + "883200 10\n" + "960000 85\n" + "1036800 59\n" + "1113600 89\n" + "1209600 30\n" + "1267200 54\n" + "1344000 293\n" + "1459200 3341\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -692,7 +691,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_frequencies", .size = 133, - .content = "200000 345600 400000 422400 499200 533333 652800 729600 800000 806400 883200 960000 1036800 1113600 1209600 1267200 1344000 1459200 \n", + .content = + "200000 345600 400000 422400 499200 533333 652800 729600 800000 806400 883200 960000 1036800 1113600 1209600 1267200 1344000 1459200 \n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_governors", @@ -727,25 +727,24 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 184, - .content = - "200000 0\n" - "345600 0\n" - "400000 0\n" - "422400 0\n" - "499200 360\n" - "533333 25\n" - "652800 18\n" - "729600 11\n" - "800000 0\n" - "806400 0\n" - "883200 10\n" - "960000 85\n" - "1036800 59\n" - "1113600 89\n" - "1209600 30\n" - "1267200 54\n" - "1344000 456\n" - "1459200 3341\n", + .content = "200000 0\n" + "345600 0\n" + "400000 0\n" + "422400 0\n" + "499200 360\n" + "533333 25\n" + "652800 18\n" + "729600 11\n" + "800000 0\n" + "806400 0\n" + "883200 10\n" + "960000 85\n" + "1036800 59\n" + "1113600 89\n" + "1209600 30\n" + "1267200 54\n" + "1344000 456\n" + "1459200 3341\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -855,15 +854,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/time_in_state", .size = 82, - .content = - "200000 2\n" - "249600 0\n" - "400000 0\n" - "499200 21\n" - "533333 23\n" - "800000 207\n" - "998400 171\n" - "1113600 4792\n", + .content = "200000 2\n" + "249600 0\n" + "400000 0\n" + "499200 21\n" + "533333 23\n" + "800000 207\n" + "998400 171\n" + "1113600 4792\n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/total_trans", @@ -968,15 +966,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/time_in_state", .size = 82, - .content = - "200000 2\n" - "249600 0\n" - "400000 0\n" - "499200 21\n" - "533333 29\n" - "800000 213\n" - "998400 176\n" - "1113600 4928\n", + .content = "200000 2\n" + "249600 0\n" + "400000 0\n" + "499200 21\n" + "533333 29\n" + "800000 213\n" + "998400 176\n" + "1113600 4928\n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/total_trans", @@ -1081,15 +1078,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/time_in_state", .size = 82, - .content = - "200000 2\n" - "249600 0\n" - "400000 0\n" - "499200 21\n" - "533333 48\n" - "800000 263\n" - "998400 181\n" - "1113600 5006\n", + .content = "200000 2\n" + "249600 0\n" + "400000 0\n" + "499200 21\n" + "533333 48\n" + "800000 263\n" + "998400 181\n" + "1113600 5006\n", }, { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/total_trans", @@ -1194,15 +1190,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/time_in_state", .size = 83, - .content = - "200000 2\n" - "249600 0\n" - "400000 0\n" - "499200 21\n" - "533333 116\n" - "800000 280\n" - "998400 181\n" - "1113600 5085\n", + .content = "200000 2\n" + "249600 0\n" + "400000 0\n" + "499200 21\n" + "533333 116\n" + "800000 280\n" + "998400 181\n" + "1113600 5085\n", }, { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/total_trans", @@ -1239,7 +1234,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "7\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -3419,6 +3414,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.wfd.status", .value = "disconnected", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/galaxy-a8-2018.cc b/test/mock/galaxy-a8-2018.cc index 560055ac..a29623ee 100644 --- a/test/mock/galaxy-a8-2018.cc +++ b/test/mock/galaxy-a8-2018.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(8, cpuinfo_get_processors_count()); @@ -348,8 +347,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Samsung Exynos 7885", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Samsung Exynos 7885", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -391,59 +392,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -594,8 +595,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -659,8 +662,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -718,8 +723,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/galaxy-a8-2018.h b/test/mock/galaxy-a8-2018.h index b3ba6a20..2f2151e5 100644 --- a/test/mock/galaxy-a8-2018.h +++ b/test/mock/galaxy-a8-2018.h @@ -3,79 +3,78 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 1448, - .content = - "processor\t: 0\n" - "BogoMIPS\t: 52.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 1\n" - "BogoMIPS\t: 52.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 2\n" - "BogoMIPS\t: 52.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 3\n" - "BogoMIPS\t: 52.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 4\n" - "BogoMIPS\t: 52.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 5\n" - "BogoMIPS\t: 52.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 6\n" - "BogoMIPS\t: 52.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd09\n" - "CPU revision\t: 2\n" - "\n" - "processor\t: 7\n" - "BogoMIPS\t: 52.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd09\n" - "CPU revision\t: 2\n" - "\n", + .content = "processor\t: 0\n" + "BogoMIPS\t: 52.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 1\n" + "BogoMIPS\t: 52.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 2\n" + "BogoMIPS\t: 52.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 3\n" + "BogoMIPS\t: 52.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 4\n" + "BogoMIPS\t: 52.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 5\n" + "BogoMIPS\t: 52.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 6\n" + "BogoMIPS\t: 52.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd09\n" + "CPU revision\t: 2\n" + "\n" + "processor\t: 7\n" + "BogoMIPS\t: 52.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd09\n" + "CPU revision\t: 2\n" + "\n", }, #elif CPUINFO_ARCH_ARM { @@ -467,19 +466,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 123, - .content = - "1586000 8312\n" - "1482000 36\n" - "1352000 60\n" - "1248000 38\n" - "1144000 26\n" - "1014000 10\n" - "902000 4\n" - "839000 52\n" - "757000 4\n" - "676000 2\n" - "546000 8\n" - "449000 8\n", + .content = "1586000 8312\n" + "1482000 36\n" + "1352000 60\n" + "1248000 38\n" + "1144000 26\n" + "1014000 10\n" + "902000 4\n" + "839000 52\n" + "757000 4\n" + "676000 2\n" + "546000 8\n" + "449000 8\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -574,19 +572,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 123, - .content = - "1586000 8523\n" - "1482000 36\n" - "1352000 60\n" - "1248000 38\n" - "1144000 26\n" - "1014000 10\n" - "902000 4\n" - "839000 52\n" - "757000 4\n" - "676000 2\n" - "546000 8\n" - "449000 8\n", + .content = "1586000 8523\n" + "1482000 36\n" + "1352000 60\n" + "1248000 38\n" + "1144000 26\n" + "1014000 10\n" + "902000 4\n" + "839000 52\n" + "757000 4\n" + "676000 2\n" + "546000 8\n" + "449000 8\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -681,19 +678,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 123, - .content = - "1586000 8736\n" - "1482000 36\n" - "1352000 60\n" - "1248000 38\n" - "1144000 26\n" - "1014000 10\n" - "902000 4\n" - "839000 52\n" - "757000 4\n" - "676000 2\n" - "546000 8\n" - "449000 8\n", + .content = "1586000 8736\n" + "1482000 36\n" + "1352000 60\n" + "1248000 38\n" + "1144000 26\n" + "1014000 10\n" + "902000 4\n" + "839000 52\n" + "757000 4\n" + "676000 2\n" + "546000 8\n" + "449000 8\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -788,19 +784,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 123, - .content = - "1586000 8977\n" - "1482000 36\n" - "1352000 60\n" - "1248000 38\n" - "1144000 26\n" - "1014000 10\n" - "902000 4\n" - "839000 52\n" - "757000 4\n" - "676000 2\n" - "546000 8\n" - "449000 8\n", + .content = "1586000 8977\n" + "1482000 36\n" + "1352000 60\n" + "1248000 38\n" + "1144000 26\n" + "1014000 10\n" + "902000 4\n" + "839000 52\n" + "757000 4\n" + "676000 2\n" + "546000 8\n" + "449000 8\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -895,19 +890,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/time_in_state", .size = 123, - .content = - "1586000 9233\n" - "1482000 36\n" - "1352000 68\n" - "1248000 38\n" - "1144000 26\n" - "1014000 10\n" - "902000 4\n" - "839000 52\n" - "757000 4\n" - "676000 2\n" - "546000 8\n" - "449000 8\n", + .content = "1586000 9233\n" + "1482000 36\n" + "1352000 68\n" + "1248000 38\n" + "1144000 26\n" + "1014000 10\n" + "902000 4\n" + "839000 52\n" + "757000 4\n" + "676000 2\n" + "546000 8\n" + "449000 8\n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/total_trans", @@ -1002,19 +996,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/time_in_state", .size = 123, - .content = - "1586000 9459\n" - "1482000 36\n" - "1352000 68\n" - "1248000 38\n" - "1144000 26\n" - "1014000 10\n" - "902000 4\n" - "839000 52\n" - "757000 4\n" - "676000 2\n" - "546000 8\n" - "449000 8\n", + .content = "1586000 9459\n" + "1482000 36\n" + "1352000 68\n" + "1248000 38\n" + "1144000 26\n" + "1014000 10\n" + "902000 4\n" + "839000 52\n" + "757000 4\n" + "676000 2\n" + "546000 8\n" + "449000 8\n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/total_trans", @@ -1114,17 +1107,16 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/time_in_state", .size = 119, - .content = - "2184000 5049\n" - "2080000 70\n" - "1976000 93\n" - "1872000 287\n" - "1768000 190\n" - "1664000 195\n" - "1560000 104\n" - "1352000 378\n" - "1144000 164\n" - "936000 3414\n", + .content = "2184000 5049\n" + "2080000 70\n" + "1976000 93\n" + "1872000 287\n" + "1768000 190\n" + "1664000 195\n" + "1560000 104\n" + "1352000 378\n" + "1144000 164\n" + "936000 3414\n", }, { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/total_trans", @@ -1224,17 +1216,16 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/time_in_state", .size = 119, - .content = - "2184000 5049\n" - "2080000 70\n" - "1976000 93\n" - "1872000 293\n" - "1768000 194\n" - "1664000 203\n" - "1560000 104\n" - "1352000 382\n" - "1144000 164\n" - "936000 3646\n", + .content = "2184000 5049\n" + "2080000 70\n" + "1976000 93\n" + "1872000 293\n" + "1768000 194\n" + "1664000 203\n" + "1560000 104\n" + "1352000 382\n" + "1144000 164\n" + "936000 3646\n", }, { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/total_trans", @@ -1271,7 +1262,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "7\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -3467,6 +3458,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.wfd.status", .value = "disconnected", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/galaxy-c9-pro.cc b/test/mock/galaxy-c9-pro.cc index f270284e..8b0943fb 100644 --- a/test/mock/galaxy-c9-pro.cc +++ b/test/mock/galaxy-c9-pro.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(8, cpuinfo_get_processors_count()); @@ -334,8 +333,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Qualcomm MSM8976", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Qualcomm MSM8976", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -377,59 +378,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -580,8 +581,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -645,8 +648,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -704,8 +709,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/galaxy-c9-pro.h b/test/mock/galaxy-c9-pro.h index c2c4be5c..6ba4f5b5 100644 --- a/test/mock/galaxy-c9-pro.h +++ b/test/mock/galaxy-c9-pro.h @@ -3,26 +3,25 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 398, - .content = - "Processor\t: AArch64 Processor rev 0 (aarch64)\n" - "processor\t: 0\n" - "processor\t: 1\n" - "processor\t: 2\n" - "processor\t: 3\n" - "processor\t: 4\n" - "processor\t: 5\n" - "processor\t: 6\n" - "processor\t: 7\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd08\n" - "CPU revision\t: 0\n" - "\n" - "Hardware\t: Qualcomm Technologies, Inc MSM8976\n" - "Revision\t: 0009\n" - "Serial\t\t: 00007fc7000046a9\n", + .content = "Processor\t: AArch64 Processor rev 0 (aarch64)\n" + "processor\t: 0\n" + "processor\t: 1\n" + "processor\t: 2\n" + "processor\t: 3\n" + "processor\t: 4\n" + "processor\t: 5\n" + "processor\t: 6\n" + "processor\t: 7\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd08\n" + "CPU revision\t: 0\n" + "\n" + "Hardware\t: Qualcomm Technologies, Inc MSM8976\n" + "Revision\t: 0009\n" + "Serial\t\t: 00007fc7000046a9\n", }, #elif CPUINFO_ARCH_ARM { @@ -431,12 +430,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/class/kgsl/kgsl-3d0/devfreq/available_frequencies", .size = 101, - .content = "133333333 200000000 266666667 300000000 366670000 432000000 480000000 550000000 600000000 621330000\r\n", + .content = + "133333333 200000000 266666667 300000000 366670000 432000000 480000000 550000000 600000000 621330000\r\n", }, { .path = "/sys/class/kgsl/kgsl-3d0/devfreq/available_governors", .size = 122, - .content = "spdm_bw_hyp cache_hwmon bw_hwmon bw_vbif gpubw_mon msm-adreno-tz cpufreq userspace powersave performance simple_ondemand\r\n", + .content = + "spdm_bw_hyp cache_hwmon bw_hwmon bw_vbif gpubw_mon msm-adreno-tz cpufreq userspace powersave performance simple_ondemand\r\n", }, { .path = "/sys/class/kgsl/kgsl-3d0/devfreq/cur_freq", @@ -471,16 +472,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/class/kgsl/kgsl-3d0/devfreq/trans_stat", .size = 542, - .content = - " From : To\r\n" - " :621330000550000000480000000432000000300000000266666667 time(ms)\r\n" - " 621330000: 0 0 0 0 0 1 330\r\n" - " 550000000: 0 0 0 0 0 0 0\r\n" - " 480000000: 0 0 0 0 0 1 1340\r\n" - " 432000000: 0 0 0 0 0 0 0\r\n" - " 300000000: 0 0 0 0 0 0 0\r\n" - "*266666667: 1 0 1 0 0 0 54400\r\n" - "Total transition : 4\r\n", + .content = " From : To\r\n" + " :621330000550000000480000000432000000300000000266666667 time(ms)\r\n" + " 621330000: 0 0 0 0 0 1 330\r\n" + " 550000000: 0 0 0 0 0 0 0\r\n" + " 480000000: 0 0 0 0 0 1 1340\r\n" + " 432000000: 0 0 0 0 0 0 0\r\n" + " 300000000: 0 0 0 0 0 0 0\r\n" + "*266666667: 1 0 1 0 0 0 54400\r\n" + "Total transition : 4\r\n", }, { .path = "/sys/class/kgsl/kgsl-3d0/ft_fast_hang_detect", @@ -610,23 +610,20 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/soc0/image_crm_version", .size = 5, - .content = - "REL\n" - "\n", + .content = "REL\n" + "\n", }, { .path = "/sys/devices/soc0/image_variant", .size = 14, - .content = - "c9ltezh-user\n" - "\n", + .content = "c9ltezh-user\n" + "\n", }, { .path = "/sys/devices/soc0/image_version", .size = 25, - .content = - "10:MMB29M:C9000ZHU1APC1\n" - "\n", + .content = "10:MMB29M:C9000ZHU1APC1\n" + "\n", }, { .path = "/sys/devices/soc0/machine", @@ -721,26 +718,25 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpufreq/all_time_in_state", .size = 847, - .content = - "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\t\n" - "400000\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\tN/A\t\t\n" - "691200\t\t464\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "806400\t\t683\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "883200\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t236\t\t1717\t\t429\t\tN/A\t\t\n" - "940800\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t1\t\t12\t\t13\t\tN/A\t\t\n" - "998400\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t1\t\t10\t\t4\t\tN/A\t\t\n" - "1017600\t\t409\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1056000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t3\t\t0\t\t2\t\tN/A\t\t\n" - "1113600\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t1\t\t0\t\t9\t\tN/A\t\t\n" - "1190400\t\t360\t\t0\t\t0\t\t0\t\t98\t\t101\t\t180\t\tN/A\t\t\n" - "1248000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t7\t\t2\t\t5\t\tN/A\t\t\n" - "1305600\t\t116\t\t0\t\t0\t\t0\t\t0\t\t0\t\t12\t\tN/A\t\t\n" - "1382400\t\t202\t\t0\t\t0\t\t0\t\t89\t\t35\t\t140\t\tN/A\t\t\n" - "1401600\t\t3561\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1612800\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t20\t\t31\t\t22\t\tN/A\t\t\n" - "1747200\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t3\t\t0\t\t3\t\tN/A\t\t\n" - "1804800\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t147\t\t151\t\t0\t\tN/A\t\t\n" - "1958400\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t1536\t\t88\t\t9\t\tN/A\t\t\n", + .content = "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\t\n" + "400000\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\tN/A\t\t\n" + "691200\t\t464\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "806400\t\t683\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "883200\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t236\t\t1717\t\t429\t\tN/A\t\t\n" + "940800\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t1\t\t12\t\t13\t\tN/A\t\t\n" + "998400\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t1\t\t10\t\t4\t\tN/A\t\t\n" + "1017600\t\t409\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "1056000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t3\t\t0\t\t2\t\tN/A\t\t\n" + "1113600\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t1\t\t0\t\t9\t\tN/A\t\t\n" + "1190400\t\t360\t\t0\t\t0\t\t0\t\t98\t\t101\t\t180\t\tN/A\t\t\n" + "1248000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t7\t\t2\t\t5\t\tN/A\t\t\n" + "1305600\t\t116\t\t0\t\t0\t\t0\t\t0\t\t0\t\t12\t\tN/A\t\t\n" + "1382400\t\t202\t\t0\t\t0\t\t0\t\t89\t\t35\t\t140\t\tN/A\t\t\n" + "1401600\t\t3561\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "1612800\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t20\t\t31\t\t22\t\tN/A\t\t\n" + "1747200\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t3\t\t0\t\t3\t\tN/A\t\t\n" + "1804800\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t147\t\t151\t\t0\t\tN/A\t\t\n" + "1958400\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t1536\t\t88\t\t9\t\tN/A\t\t\n", }, { .path = "/sys/devices/system/cpu/cpufreq/current_in_state", @@ -793,69 +789,68 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/core_ctl/global_state", .size = 678, - .content = - "CPU0\n" - "\tCPU: 0\n" - "\tOnline: 1\n" - "\tRejected: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 88\n" - "\tIs busy: 1\n" - "\tNr running: 5\n" - "\tAvail CPUs: 4\n" - "\tNeed CPUs: 5\n" - "CPU1\n" - "\tCPU: 1\n" - "\tOnline: 1\n" - "\tRejected: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 100\n" - "\tIs busy: 1\n" - "CPU2\n" - "\tCPU: 2\n" - "\tOnline: 1\n" - "\tRejected: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 31\n" - "\tIs busy: 1\n" - "CPU3\n" - "\tCPU: 3\n" - "\tOnline: 1\n" - "\tRejected: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 100\n" - "\tIs busy: 1\n" - "CPU4\n" - "\tCPU: 4\n" - "\tOnline: 0\n" - "\tRejected: 0\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "\tNr running: 0\n" - "\tAvail CPUs: 4\n" - "\tNeed CPUs: 0\n" - "CPU5\n" - "\tCPU: 5\n" - "\tOnline: 1\n" - "\tRejected: 0\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "CPU6\n" - "\tCPU: 6\n" - "\tOnline: 0\n" - "\tRejected: 0\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "CPU7\n" - "\tCPU: 7\n" - "\tOnline: 1\n" - "\tRejected: 0\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n", + .content = "CPU0\n" + "\tCPU: 0\n" + "\tOnline: 1\n" + "\tRejected: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 88\n" + "\tIs busy: 1\n" + "\tNr running: 5\n" + "\tAvail CPUs: 4\n" + "\tNeed CPUs: 5\n" + "CPU1\n" + "\tCPU: 1\n" + "\tOnline: 1\n" + "\tRejected: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 100\n" + "\tIs busy: 1\n" + "CPU2\n" + "\tCPU: 2\n" + "\tOnline: 1\n" + "\tRejected: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 31\n" + "\tIs busy: 1\n" + "CPU3\n" + "\tCPU: 3\n" + "\tOnline: 1\n" + "\tRejected: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 100\n" + "\tIs busy: 1\n" + "CPU4\n" + "\tCPU: 4\n" + "\tOnline: 0\n" + "\tRejected: 0\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "\tNr running: 0\n" + "\tAvail CPUs: 4\n" + "\tNeed CPUs: 0\n" + "CPU5\n" + "\tCPU: 5\n" + "\tOnline: 1\n" + "\tRejected: 0\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "CPU6\n" + "\tCPU: 6\n" + "\tOnline: 0\n" + "\tRejected: 0\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "CPU7\n" + "\tCPU: 7\n" + "\tOnline: 1\n" + "\tRejected: 0\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n", }, { .path = "/sys/devices/system/cpu/cpu0/core_ctl/is_big_cluster", @@ -880,11 +875,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/core_ctl/not_preferred", .size = 36, - .content = - "\tCPU:0 0\n" - "\tCPU:1 0\n" - "\tCPU:2 0\n" - "\tCPU:3 0\n", + .content = "\tCPU:0 0\n" + "\tCPU:1 0\n" + "\tCPU:2 0\n" + "\tCPU:3 0\n", }, { .path = "/sys/devices/system/cpu/cpu0/core_ctl/offline_delay_ms", @@ -959,15 +953,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 92, - .content = - "400000 0\n" - "691200 464\n" - "806400 683\n" - "1017600 409\n" - "1190400 360\n" - "1305600 122\n" - "1382400 206\n" - "1401600 3683\n", + .content = "400000 0\n" + "691200 464\n" + "806400 683\n" + "1017600 409\n" + "1190400 360\n" + "1305600 122\n" + "1382400 206\n" + "1401600 3683\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -1067,15 +1060,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 92, - .content = - "400000 0\n" - "691200 464\n" - "806400 696\n" - "1017600 425\n" - "1190400 376\n" - "1305600 127\n" - "1382400 222\n" - "1401600 3873\n", + .content = "400000 0\n" + "691200 464\n" + "806400 696\n" + "1017600 425\n" + "1190400 376\n" + "1305600 127\n" + "1382400 222\n" + "1401600 3873\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -1175,15 +1167,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 92, - .content = - "400000 0\n" - "691200 476\n" - "806400 714\n" - "1017600 446\n" - "1190400 398\n" - "1305600 132\n" - "1382400 241\n" - "1401600 3996\n", + .content = "400000 0\n" + "691200 476\n" + "806400 714\n" + "1017600 446\n" + "1190400 398\n" + "1305600 132\n" + "1382400 241\n" + "1401600 3996\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -1283,15 +1274,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 92, - .content = - "400000 0\n" - "691200 476\n" - "806400 721\n" - "1017600 459\n" - "1190400 432\n" - "1305600 136\n" - "1382400 258\n" - "1401600 4149\n", + .content = "400000 0\n" + "691200 476\n" + "806400 721\n" + "1017600 459\n" + "1190400 432\n" + "1305600 136\n" + "1382400 258\n" + "1401600 4149\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -1341,69 +1331,68 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/core_ctl/global_state", .size = 674, - .content = - "CPU0\n" - "\tCPU: 0\n" - "\tOnline: 1\n" - "\tRejected: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 2\n" - "\tIs busy: 1\n" - "\tNr running: 2\n" - "\tAvail CPUs: 4\n" - "\tNeed CPUs: 4\n" - "CPU1\n" - "\tCPU: 1\n" - "\tOnline: 1\n" - "\tRejected: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 0\n" - "\tIs busy: 1\n" - "CPU2\n" - "\tCPU: 2\n" - "\tOnline: 1\n" - "\tRejected: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 40\n" - "\tIs busy: 1\n" - "CPU3\n" - "\tCPU: 3\n" - "\tOnline: 1\n" - "\tRejected: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 0\n" - "\tIs busy: 1\n" - "CPU4\n" - "\tCPU: 4\n" - "\tOnline: 0\n" - "\tRejected: 0\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "\tNr running: 1\n" - "\tAvail CPUs: 4\n" - "\tNeed CPUs: 1\n" - "CPU5\n" - "\tCPU: 5\n" - "\tOnline: 1\n" - "\tRejected: 0\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "CPU6\n" - "\tCPU: 6\n" - "\tOnline: 0\n" - "\tRejected: 0\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "CPU7\n" - "\tCPU: 7\n" - "\tOnline: 1\n" - "\tRejected: 0\n" - "\tFirst CPU: 4\n" - "\tBusy%: 70\n" - "\tIs busy: 1\n", + .content = "CPU0\n" + "\tCPU: 0\n" + "\tOnline: 1\n" + "\tRejected: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 2\n" + "\tIs busy: 1\n" + "\tNr running: 2\n" + "\tAvail CPUs: 4\n" + "\tNeed CPUs: 4\n" + "CPU1\n" + "\tCPU: 1\n" + "\tOnline: 1\n" + "\tRejected: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 0\n" + "\tIs busy: 1\n" + "CPU2\n" + "\tCPU: 2\n" + "\tOnline: 1\n" + "\tRejected: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 40\n" + "\tIs busy: 1\n" + "CPU3\n" + "\tCPU: 3\n" + "\tOnline: 1\n" + "\tRejected: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 0\n" + "\tIs busy: 1\n" + "CPU4\n" + "\tCPU: 4\n" + "\tOnline: 0\n" + "\tRejected: 0\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "\tNr running: 1\n" + "\tAvail CPUs: 4\n" + "\tNeed CPUs: 1\n" + "CPU5\n" + "\tCPU: 5\n" + "\tOnline: 1\n" + "\tRejected: 0\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "CPU6\n" + "\tCPU: 6\n" + "\tOnline: 0\n" + "\tRejected: 0\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "CPU7\n" + "\tCPU: 7\n" + "\tOnline: 1\n" + "\tRejected: 0\n" + "\tFirst CPU: 4\n" + "\tBusy%: 70\n" + "\tIs busy: 1\n", }, { .path = "/sys/devices/system/cpu/cpu4/core_ctl/is_big_cluster", @@ -1428,11 +1417,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/core_ctl/not_preferred", .size = 36, - .content = - "\tCPU:4 0\n" - "\tCPU:5 0\n" - "\tCPU:6 0\n" - "\tCPU:7 0\n", + .content = "\tCPU:4 0\n" + "\tCPU:5 0\n" + "\tCPU:6 0\n" + "\tCPU:7 0\n", }, { .path = "/sys/devices/system/cpu/cpu4/core_ctl/offline_delay_ms", @@ -1482,7 +1470,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_available_frequencies", .size = 109, - .content = "400000 883200 940800 998400 1056000 1113600 1190400 1248000 1305600 1382400 1612800 1747200 1804800 1958400 \n", + .content = + "400000 883200 940800 998400 1056000 1113600 1190400 1248000 1305600 1382400 1612800 1747200 1804800 1958400 \n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_available_governors", @@ -1517,21 +1506,20 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/time_in_state", .size = 154, - .content = - "400000 0\n" - "883200 3515\n" - "940800 43\n" - "998400 15\n" - "1056000 5\n" - "1113600 11\n" - "1190400 507\n" - "1248000 15\n" - "1305600 16\n" - "1382400 279\n" - "1612800 81\n" - "1747200 6\n" - "1804800 298\n" - "1958400 2300\n", + .content = "400000 0\n" + "883200 3515\n" + "940800 43\n" + "998400 15\n" + "1056000 5\n" + "1113600 11\n" + "1190400 507\n" + "1248000 15\n" + "1305600 16\n" + "1382400 279\n" + "1612800 81\n" + "1747200 6\n" + "1804800 298\n" + "1958400 2300\n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/total_trans", @@ -1606,7 +1594,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_available_frequencies", .size = 109, - .content = "400000 883200 940800 998400 1056000 1113600 1190400 1248000 1305600 1382400 1612800 1747200 1804800 1958400 \n", + .content = + "400000 883200 940800 998400 1056000 1113600 1190400 1248000 1305600 1382400 1612800 1747200 1804800 1958400 \n", }, { .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_available_governors", @@ -1641,21 +1630,20 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/time_in_state", .size = 154, - .content = - "400000 0\n" - "883200 4006\n" - "940800 43\n" - "998400 15\n" - "1056000 5\n" - "1113600 11\n" - "1190400 511\n" - "1248000 15\n" - "1305600 16\n" - "1382400 279\n" - "1612800 81\n" - "1747200 6\n" - "1804800 298\n" - "1958400 2300\n", + .content = "400000 0\n" + "883200 4006\n" + "940800 43\n" + "998400 15\n" + "1056000 5\n" + "1113600 11\n" + "1190400 511\n" + "1248000 15\n" + "1305600 16\n" + "1382400 279\n" + "1612800 81\n" + "1747200 6\n" + "1804800 298\n" + "1958400 2300\n", }, { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/total_trans", @@ -1692,7 +1680,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "7\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -4292,6 +4280,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.wfd.status", .value = "disconnected", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/galaxy-grand-prime-value-edition.cc b/test/mock/galaxy-grand-prime-value-edition.cc index f7b8793a..8190648c 100644 --- a/test/mock/galaxy-grand-prime-value-edition.cc +++ b/test/mock/galaxy-grand-prime-value-edition.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(4, cpuinfo_get_processors_count()); @@ -208,8 +207,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Spreadtrum SC7730SE", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Spreadtrum SC7730SE", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -400,8 +401,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -452,8 +455,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -504,8 +509,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/galaxy-grand-prime-value-edition.h b/test/mock/galaxy-grand-prime-value-edition.h index c63271e2..840ec7cd 100644 --- a/test/mock/galaxy-grand-prime-value-edition.h +++ b/test/mock/galaxy-grand-prime-value-edition.h @@ -2,51 +2,50 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 1121, - .content = - "Processor\t: ARMv7 Processor rev 5 (v7l)\n" - "processor\t: 0\n" - "model name\t: ARMv7 Processor rev 5 (v7l)\n" - "BogoMIPS\t: 2603.41\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xc07\n" - "CPU revision\t: 5\n" - "\n" - "processor\t: 1\n" - "model name\t: ARMv7 Processor rev 5 (v7l)\n" - "BogoMIPS\t: 2609.97\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xc07\n" - "CPU revision\t: 5\n" - "\n" - "processor\t: 2\n" - "model name\t: ARMv7 Processor rev 5 (v7l)\n" - "BogoMIPS\t: 2609.97\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xc07\n" - "CPU revision\t: 5\n" - "\n" - "processor\t: 3\n" - "model name\t: ARMv7 Processor rev 5 (v7l)\n" - "BogoMIPS\t: 2609.97\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xc07\n" - "CPU revision\t: 5\n" - "\n" - "Hardware\t: sc8830\n" - "Revision\t: 0004\n" - "Serial\t\t: 4200ddccd2da6300\n", + .content = "Processor\t: ARMv7 Processor rev 5 (v7l)\n" + "processor\t: 0\n" + "model name\t: ARMv7 Processor rev 5 (v7l)\n" + "BogoMIPS\t: 2603.41\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xc07\n" + "CPU revision\t: 5\n" + "\n" + "processor\t: 1\n" + "model name\t: ARMv7 Processor rev 5 (v7l)\n" + "BogoMIPS\t: 2609.97\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xc07\n" + "CPU revision\t: 5\n" + "\n" + "processor\t: 2\n" + "model name\t: ARMv7 Processor rev 5 (v7l)\n" + "BogoMIPS\t: 2609.97\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xc07\n" + "CPU revision\t: 5\n" + "\n" + "processor\t: 3\n" + "model name\t: ARMv7 Processor rev 5 (v7l)\n" + "BogoMIPS\t: 2609.97\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xc07\n" + "CPU revision\t: 5\n" + "\n" + "Hardware\t: sc8830\n" + "Revision\t: 0004\n" + "Serial\t\t: 4200ddccd2da6300\n", }, { .path = "/system/build.prop", @@ -279,12 +278,11 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpufreq/all_time_in_state", .size = 130, - .content = - "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\t\n" - "768000\t\t0\t\t0\t\t0\t\t0\t\t\n" - "1000000\t\t0\t\t0\t\t0\t\t0\t\t\n" - "1200000\t\t0\t\t0\t\t0\t\t0\t\t\n" - "1300000\t\t2191\t\t2191\t\t2191\t\t2191\t\t\n", + .content = "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\t\n" + "768000\t\t0\t\t0\t\t0\t\t0\t\t\n" + "1000000\t\t0\t\t0\t\t0\t\t0\t\t\n" + "1200000\t\t0\t\t0\t\t0\t\t0\t\t\n" + "1300000\t\t2191\t\t2191\t\t2191\t\t2191\t\t\n", }, { .path = "/sys/devices/system/cpu/cpuidle/current_driver", @@ -349,11 +347,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 42, - .content = - "1300000 2275\n" - "1200000 0\n" - "1000000 0\n" - "768000 0\n", + .content = "1300000 2275\n" + "1200000 0\n" + "1000000 0\n" + "768000 0\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -443,11 +440,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 42, - .content = - "1300000 2506\n" - "1200000 0\n" - "1000000 0\n" - "768000 0\n", + .content = "1300000 2506\n" + "1200000 0\n" + "1000000 0\n" + "768000 0\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -537,11 +533,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 42, - .content = - "1300000 2707\n" - "1200000 0\n" - "1000000 0\n" - "768000 0\n", + .content = "1300000 2707\n" + "1200000 0\n" + "1000000 0\n" + "768000 0\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -631,11 +626,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 42, - .content = - "1300000 2902\n" - "1200000 0\n" - "1000000 0\n" - "768000 0\n", + .content = "1300000 2902\n" + "1200000 0\n" + "1000000 0\n" + "768000 0\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -672,7 +666,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "8\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ @@ -1989,6 +1983,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.wfd.status", .value = "disconnected", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/galaxy-j1-2016.cc b/test/mock/galaxy-j1-2016.cc index e1f2f030..8a99085b 100644 --- a/test/mock/galaxy-j1-2016.cc +++ b/test/mock/galaxy-j1-2016.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(4, cpuinfo_get_processors_count()); @@ -208,8 +207,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Spreadtrum SC7727SE", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Spreadtrum SC7727SE", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -400,8 +401,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -452,8 +455,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -504,8 +509,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/galaxy-j1-2016.h b/test/mock/galaxy-j1-2016.h index d1bb1cb5..d4169621 100644 --- a/test/mock/galaxy-j1-2016.h +++ b/test/mock/galaxy-j1-2016.h @@ -2,51 +2,50 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 1121, - .content = - "Processor\t: ARMv7 Processor rev 5 (v7l)\n" - "processor\t: 0\n" - "model name\t: ARMv7 Processor rev 5 (v7l)\n" - "BogoMIPS\t: 2413.36\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xc07\n" - "CPU revision\t: 5\n" - "\n" - "processor\t: 1\n" - "model name\t: ARMv7 Processor rev 5 (v7l)\n" - "BogoMIPS\t: 2419.91\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xc07\n" - "CPU revision\t: 5\n" - "\n" - "processor\t: 2\n" - "model name\t: ARMv7 Processor rev 5 (v7l)\n" - "BogoMIPS\t: 2419.91\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xc07\n" - "CPU revision\t: 5\n" - "\n" - "processor\t: 3\n" - "model name\t: ARMv7 Processor rev 5 (v7l)\n" - "BogoMIPS\t: 2419.91\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xc07\n" - "CPU revision\t: 5\n" - "\n" - "Hardware\t: sc8830\n" - "Revision\t: 0005\n" - "Serial\t\t: 4200ff80dc185400\n", + .content = "Processor\t: ARMv7 Processor rev 5 (v7l)\n" + "processor\t: 0\n" + "model name\t: ARMv7 Processor rev 5 (v7l)\n" + "BogoMIPS\t: 2413.36\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xc07\n" + "CPU revision\t: 5\n" + "\n" + "processor\t: 1\n" + "model name\t: ARMv7 Processor rev 5 (v7l)\n" + "BogoMIPS\t: 2419.91\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xc07\n" + "CPU revision\t: 5\n" + "\n" + "processor\t: 2\n" + "model name\t: ARMv7 Processor rev 5 (v7l)\n" + "BogoMIPS\t: 2419.91\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xc07\n" + "CPU revision\t: 5\n" + "\n" + "processor\t: 3\n" + "model name\t: ARMv7 Processor rev 5 (v7l)\n" + "BogoMIPS\t: 2419.91\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xc07\n" + "CPU revision\t: 5\n" + "\n" + "Hardware\t: sc8830\n" + "Revision\t: 0005\n" + "Serial\t\t: 4200ff80dc185400\n", }, { .path = "/system/build.prop", @@ -271,11 +270,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpufreq/all_time_in_state", .size = 108, - .content = - "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\t\n" - "768000\t\t0\t\t0\t\t0\t\t0\t\t\n" - "1000000\t\t0\t\t0\t\t0\t\t0\t\t\n" - "1200000\t\t2301\t\t2301\t\t2301\t\t2301\t\t\n", + .content = "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\t\n" + "768000\t\t0\t\t0\t\t0\t\t0\t\t\n" + "1000000\t\t0\t\t0\t\t0\t\t0\t\t\n" + "1200000\t\t2301\t\t2301\t\t2301\t\t2301\t\t\n", }, { .path = "/sys/devices/system/cpu/cpuidle/current_driver", @@ -330,10 +328,9 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 32, - .content = - "1200000 2395\n" - "1000000 0\n" - "768000 0\n", + .content = "1200000 2395\n" + "1000000 0\n" + "768000 0\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -413,10 +410,9 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 32, - .content = - "1200000 2683\n" - "1000000 0\n" - "768000 0\n", + .content = "1200000 2683\n" + "1000000 0\n" + "768000 0\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -496,10 +492,9 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 32, - .content = - "1200000 2968\n" - "1000000 0\n" - "768000 0\n", + .content = "1200000 2968\n" + "1000000 0\n" + "768000 0\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -579,10 +574,9 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 32, - .content = - "1200000 3254\n" - "1000000 6\n" - "768000 0\n", + .content = "1200000 3254\n" + "1000000 6\n" + "768000 0\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -619,7 +613,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "3\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -2075,6 +2069,6 @@ struct cpuinfo_mock_property properties[] = { .key = "zram.disksize", .value = "600", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/galaxy-j5.cc b/test/mock/galaxy-j5.cc index b2a9c6b4..ba156aed 100644 --- a/test/mock/galaxy-j5.cc +++ b/test/mock/galaxy-j5.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(4, cpuinfo_get_processors_count()); @@ -208,8 +207,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Qualcomm MSM8916", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Qualcomm MSM8916", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -400,8 +401,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -452,8 +455,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -504,8 +509,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/galaxy-j5.h b/test/mock/galaxy-j5.h index 39507b53..abd15265 100644 --- a/test/mock/galaxy-j5.h +++ b/test/mock/galaxy-j5.h @@ -414,15 +414,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpufreq/all_time_in_state", .size = 184, - .content = - "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\t\n" - "200000\t\t0\t\t0\t\t0\t\t0\t\t\n" - "400000\t\t0\t\t0\t\t0\t\t0\t\t\n" - "533333\t\t0\t\t0\t\t0\t\t0\t\t\n" - "800000\t\t6\t\t0\t\t0\t\t0\t\t\n" - "998400\t\t1\t\t0\t\t0\t\t0\t\t\n" - "1094400\t\t13\t\t0\t\t0\t\t0\t\t\n" - "1190400\t\t3342\t\t0\t\t0\t\t0\t\t\n", + .content = "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\t\n" + "200000\t\t0\t\t0\t\t0\t\t0\t\t\n" + "400000\t\t0\t\t0\t\t0\t\t0\t\t\n" + "533333\t\t0\t\t0\t\t0\t\t0\t\t\n" + "800000\t\t6\t\t0\t\t0\t\t0\t\t\n" + "998400\t\t1\t\t0\t\t0\t\t0\t\t\n" + "1094400\t\t13\t\t0\t\t0\t\t0\t\t\n" + "1190400\t\t3342\t\t0\t\t0\t\t0\t\t\n", }, { .path = "/sys/devices/system/cpu/cpufreq/current_in_state", @@ -502,14 +501,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 69, - .content = - "200000 0\n" - "400000 0\n" - "533333 0\n" - "800000 6\n" - "998400 3\n" - "1094400 23\n" - "1190400 3421\n", + .content = "200000 0\n" + "400000 0\n" + "533333 0\n" + "800000 6\n" + "998400 3\n" + "1094400 23\n" + "1190400 3421\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -609,14 +607,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 71, - .content = - "200000 0\n" - "400000 0\n" - "533333 0\n" - "800000 18\n" - "998400 20\n" - "1094400 26\n" - "1190400 3555\n", + .content = "200000 0\n" + "400000 0\n" + "533333 0\n" + "800000 18\n" + "998400 20\n" + "1094400 26\n" + "1190400 3555\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -716,14 +713,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 72, - .content = - "200000 0\n" - "400000 0\n" - "533333 0\n" - "800000 112\n" - "998400 37\n" - "1094400 32\n" - "1190400 3596\n", + .content = "200000 0\n" + "400000 0\n" + "533333 0\n" + "800000 112\n" + "998400 37\n" + "1094400 32\n" + "1190400 3596\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -823,14 +819,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 72, - .content = - "200000 0\n" - "400000 0\n" - "533333 0\n" - "800000 190\n" - "998400 84\n" - "1094400 38\n" - "1190400 3621\n", + .content = "200000 0\n" + "400000 0\n" + "533333 0\n" + "800000 190\n" + "998400 84\n" + "1094400 38\n" + "1190400 3621\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -867,7 +862,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "3\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -2979,6 +2974,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.p2p.chkintent", .value = "8", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/galaxy-j7-prime.cc b/test/mock/galaxy-j7-prime.cc index 597de8bd..6f3b89ec 100644 --- a/test/mock/galaxy-j7-prime.cc +++ b/test/mock/galaxy-j7-prime.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(8, cpuinfo_get_processors_count()); @@ -274,8 +273,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Samsung Exynos 7870", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Samsung Exynos 7870", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -317,59 +318,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -494,8 +495,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -546,8 +549,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -598,8 +603,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/galaxy-j7-prime.h b/test/mock/galaxy-j7-prime.h index a91a15b5..242d342b 100644 --- a/test/mock/galaxy-j7-prime.h +++ b/test/mock/galaxy-j7-prime.h @@ -266,19 +266,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpufreq/all_time_in_state", .size = 508, - .content = - "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\t\n" - "546000\t\t21\t\t21\t\t21\t\t21\t\t30\t\t30\t\t30\t\t30\t\t\n" - "676000\t\t4\t\t4\t\t4\t\t4\t\t28\t\t28\t\t28\t\t28\t\t\n" - "757000\t\t0\t\t0\t\t0\t\t0\t\t6\t\t6\t\t6\t\t6\t\t\n" - "839000\t\t0\t\t0\t\t0\t\t0\t\t22\t\t22\t\t22\t\t22\t\t\n" - "902000\t\t63\t\t63\t\t63\t\t63\t\t48\t\t48\t\t48\t\t48\t\t\n" - "1014000\t\t7\t\t7\t\t7\t\t7\t\t10\t\t10\t\t10\t\t10\t\t\n" - "1144000\t\t12\t\t12\t\t12\t\t12\t\t12\t\t12\t\t12\t\t12\t\t\n" - "1248000\t\t27\t\t27\t\t27\t\t27\t\t13\t\t13\t\t13\t\t13\t\t\n" - "1352000\t\t2\t\t2\t\t2\t\t2\t\t4\t\t4\t\t4\t\t4\t\t\n" - "1482000\t\t4006\t\t4006\t\t4006\t\t4006\t\t3963\t\t3963\t\t3963\t\t3963\t\t\n" - "1586000\t\t210\t\t210\t\t210\t\t210\t\t203\t\t203\t\t203\t\t203\t\t\n", + .content = "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\t\n" + "546000\t\t21\t\t21\t\t21\t\t21\t\t30\t\t30\t\t30\t\t30\t\t\n" + "676000\t\t4\t\t4\t\t4\t\t4\t\t28\t\t28\t\t28\t\t28\t\t\n" + "757000\t\t0\t\t0\t\t0\t\t0\t\t6\t\t6\t\t6\t\t6\t\t\n" + "839000\t\t0\t\t0\t\t0\t\t0\t\t22\t\t22\t\t22\t\t22\t\t\n" + "902000\t\t63\t\t63\t\t63\t\t63\t\t48\t\t48\t\t48\t\t48\t\t\n" + "1014000\t\t7\t\t7\t\t7\t\t7\t\t10\t\t10\t\t10\t\t10\t\t\n" + "1144000\t\t12\t\t12\t\t12\t\t12\t\t12\t\t12\t\t12\t\t12\t\t\n" + "1248000\t\t27\t\t27\t\t27\t\t27\t\t13\t\t13\t\t13\t\t13\t\t\n" + "1352000\t\t2\t\t2\t\t2\t\t2\t\t4\t\t4\t\t4\t\t4\t\t\n" + "1482000\t\t4006\t\t4006\t\t4006\t\t4006\t\t3963\t\t3963\t\t3963\t\t3963\t\t\n" + "1586000\t\t210\t\t210\t\t210\t\t210\t\t203\t\t203\t\t203\t\t203\t\t\n", }, { .path = "/sys/devices/system/cpu/cpuidle/current_driver", @@ -348,18 +347,17 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 114, - .content = - "1586000 270\n" - "1482000 4008\n" - "1352000 4\n" - "1248000 29\n" - "1144000 12\n" - "1014000 7\n" - "902000 67\n" - "839000 0\n" - "757000 0\n" - "676000 8\n" - "546000 25\n", + .content = "1586000 270\n" + "1482000 4008\n" + "1352000 4\n" + "1248000 29\n" + "1144000 12\n" + "1014000 7\n" + "902000 67\n" + "839000 0\n" + "757000 0\n" + "676000 8\n" + "546000 25\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -454,18 +452,17 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 114, - .content = - "1586000 401\n" - "1482000 4010\n" - "1352000 4\n" - "1248000 31\n" - "1144000 16\n" - "1014000 7\n" - "902000 71\n" - "839000 2\n" - "757000 4\n" - "676000 8\n" - "546000 25\n", + .content = "1586000 401\n" + "1482000 4010\n" + "1352000 4\n" + "1248000 31\n" + "1144000 16\n" + "1014000 7\n" + "902000 71\n" + "839000 2\n" + "757000 4\n" + "676000 8\n" + "546000 25\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -560,18 +557,17 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 118, - .content = - "1586000 482\n" - "1482000 4023\n" - "1352000 10\n" - "1248000 43\n" - "1144000 16\n" - "1014000 15\n" - "902000 81\n" - "839000 3\n" - "757000 10\n" - "676000 13\n" - "546000 27\n", + .content = "1586000 482\n" + "1482000 4023\n" + "1352000 10\n" + "1248000 43\n" + "1144000 16\n" + "1014000 15\n" + "902000 81\n" + "839000 3\n" + "757000 10\n" + "676000 13\n" + "546000 27\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -666,18 +662,17 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 118, - .content = - "1586000 627\n" - "1482000 4023\n" - "1352000 10\n" - "1248000 43\n" - "1144000 16\n" - "1014000 15\n" - "902000 81\n" - "839000 3\n" - "757000 10\n" - "676000 13\n" - "546000 27\n", + .content = "1586000 627\n" + "1482000 4023\n" + "1352000 10\n" + "1248000 43\n" + "1144000 16\n" + "1014000 15\n" + "902000 81\n" + "839000 3\n" + "757000 10\n" + "676000 13\n" + "546000 27\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -777,18 +772,17 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/time_in_state", .size = 112, - .content = - "1586000 123\n" - "1482000 2\n" - "1352000 8\n" - "1248000 14\n" - "1144000 10\n" - "1014000 16\n" - "902000 30\n" - "839000 0\n" - "757000 4\n" - "676000 9\n" - "546000 86\n", + .content = "1586000 123\n" + "1482000 2\n" + "1352000 8\n" + "1248000 14\n" + "1144000 10\n" + "1014000 16\n" + "902000 30\n" + "839000 0\n" + "757000 4\n" + "676000 9\n" + "546000 86\n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/total_trans", @@ -825,7 +819,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "4\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -2649,6 +2643,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.wfd.status", .value = "disconnected", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/galaxy-j7-tmobile.cc b/test/mock/galaxy-j7-tmobile.cc index 63b05ba0..40219000 100644 --- a/test/mock/galaxy-j7-tmobile.cc +++ b/test/mock/galaxy-j7-tmobile.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(8, cpuinfo_get_processors_count()); @@ -274,8 +273,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Samsung Exynos 7580", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Samsung Exynos 7580", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -317,59 +318,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -494,8 +495,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -546,8 +549,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -598,8 +603,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/galaxy-j7-tmobile.h b/test/mock/galaxy-j7-tmobile.h index b85cd0d3..50b65ca0 100644 --- a/test/mock/galaxy-j7-tmobile.h +++ b/test/mock/galaxy-j7-tmobile.h @@ -217,20 +217,19 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpufreq/all_time_in_state", .size = 613, - .content = - "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\t\n" - "400000\t\t113\t\t113\t\t113\t\t113\t\t121\t\t121\t\t121\t\t121\t\t\n" - "500000\t\t38\t\t38\t\t38\t\t38\t\t72\t\t72\t\t72\t\t72\t\t\n" - "600000\t\t16\t\t16\t\t16\t\t16\t\t60\t\t60\t\t60\t\t60\t\t\n" - "700000\t\t14\t\t14\t\t14\t\t14\t\t61\t\t61\t\t61\t\t61\t\t\n" - "800000\t\t14\t\t14\t\t14\t\t14\t\t22\t\t22\t\t22\t\t22\t\t\n" - "900000\t\t466\t\t466\t\t466\t\t466\t\t661\t\t661\t\t661\t\t661\t\t\n" - "1000000\t\t91\t\t91\t\t91\t\t91\t\t52\t\t52\t\t52\t\t52\t\t\n" - "1100000\t\t118\t\t118\t\t118\t\t118\t\t104\t\t104\t\t104\t\t104\t\t\n" - "1200000\t\t241\t\t241\t\t241\t\t241\t\t189\t\t189\t\t189\t\t189\t\t\n" - "1300000\t\t126\t\t126\t\t126\t\t126\t\t97\t\t97\t\t97\t\t97\t\t\n" - "1400000\t\t237\t\t237\t\t237\t\t237\t\t161\t\t161\t\t161\t\t161\t\t\n" - "1500000\t\t4492\t\t4492\t\t4492\t\t4492\t\t4012\t\t4012\t\t4012\t\t4012\t\t\n", + .content = "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\t\n" + "400000\t\t113\t\t113\t\t113\t\t113\t\t121\t\t121\t\t121\t\t121\t\t\n" + "500000\t\t38\t\t38\t\t38\t\t38\t\t72\t\t72\t\t72\t\t72\t\t\n" + "600000\t\t16\t\t16\t\t16\t\t16\t\t60\t\t60\t\t60\t\t60\t\t\n" + "700000\t\t14\t\t14\t\t14\t\t14\t\t61\t\t61\t\t61\t\t61\t\t\n" + "800000\t\t14\t\t14\t\t14\t\t14\t\t22\t\t22\t\t22\t\t22\t\t\n" + "900000\t\t466\t\t466\t\t466\t\t466\t\t661\t\t661\t\t661\t\t661\t\t\n" + "1000000\t\t91\t\t91\t\t91\t\t91\t\t52\t\t52\t\t52\t\t52\t\t\n" + "1100000\t\t118\t\t118\t\t118\t\t118\t\t104\t\t104\t\t104\t\t104\t\t\n" + "1200000\t\t241\t\t241\t\t241\t\t241\t\t189\t\t189\t\t189\t\t189\t\t\n" + "1300000\t\t126\t\t126\t\t126\t\t126\t\t97\t\t97\t\t97\t\t97\t\t\n" + "1400000\t\t237\t\t237\t\t237\t\t237\t\t161\t\t161\t\t161\t\t161\t\t\n" + "1500000\t\t4492\t\t4492\t\t4492\t\t4492\t\t4012\t\t4012\t\t4012\t\t4012\t\t\n", }, { .path = "/sys/devices/system/cpu/cpuidle/current_driver", @@ -270,11 +269,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/clusterhotplug/time_in_state", .size = 27, - .content = - "H0 57447\n" - "H1 3553\n" - "H2 0\n" - "H3 0\n", + .content = "H0 57447\n" + "H1 3553\n" + "H2 0\n" + "H3 0\n", }, { .path = "/sys/devices/system/cpu/clusterhotplug/up_freq", @@ -319,7 +317,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies", .size = 91, - .content = "1500000 1400000 1300000 1200000 1100000 1000000 900000 800000 700000 600000 500000 400000 \n", + .content = + "1500000 1400000 1300000 1200000 1100000 1000000 900000 800000 700000 600000 500000 400000 \n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors", @@ -349,19 +348,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 134, - .content = - "1500000 4540\n" - "1400000 237\n" - "1300000 129\n" - "1200000 250\n" - "1100000 118\n" - "1000000 93\n" - "900000 476\n" - "800000 15\n" - "700000 17\n" - "600000 17\n" - "500000 38\n" - "400000 113\n", + .content = "1500000 4540\n" + "1400000 237\n" + "1300000 129\n" + "1200000 250\n" + "1100000 118\n" + "1000000 93\n" + "900000 476\n" + "800000 15\n" + "700000 17\n" + "600000 17\n" + "500000 38\n" + "400000 113\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -426,7 +424,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_frequencies", .size = 91, - .content = "1500000 1400000 1300000 1200000 1100000 1000000 900000 800000 700000 600000 500000 400000 \n", + .content = + "1500000 1400000 1300000 1200000 1100000 1000000 900000 800000 700000 600000 500000 400000 \n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_governors", @@ -456,19 +455,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 134, - .content = - "1500000 4664\n" - "1400000 239\n" - "1300000 131\n" - "1200000 256\n" - "1100000 121\n" - "1000000 99\n" - "900000 547\n" - "800000 15\n" - "700000 17\n" - "600000 27\n" - "500000 41\n" - "400000 124\n", + .content = "1500000 4664\n" + "1400000 239\n" + "1300000 131\n" + "1200000 256\n" + "1100000 121\n" + "1000000 99\n" + "900000 547\n" + "800000 15\n" + "700000 17\n" + "600000 27\n" + "500000 41\n" + "400000 124\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -533,7 +531,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_frequencies", .size = 91, - .content = "1500000 1400000 1300000 1200000 1100000 1000000 900000 800000 700000 600000 500000 400000 \n", + .content = + "1500000 1400000 1300000 1200000 1100000 1000000 900000 800000 700000 600000 500000 400000 \n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_governors", @@ -563,19 +562,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 134, - .content = - "1500000 4836\n" - "1400000 244\n" - "1300000 150\n" - "1200000 283\n" - "1100000 132\n" - "1000000 99\n" - "900000 553\n" - "800000 15\n" - "700000 17\n" - "600000 27\n" - "500000 41\n" - "400000 124\n", + .content = "1500000 4836\n" + "1400000 244\n" + "1300000 150\n" + "1200000 283\n" + "1100000 132\n" + "1000000 99\n" + "900000 553\n" + "800000 15\n" + "700000 17\n" + "600000 27\n" + "500000 41\n" + "400000 124\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -640,7 +638,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_frequencies", .size = 91, - .content = "1500000 1400000 1300000 1200000 1100000 1000000 900000 800000 700000 600000 500000 400000 \n", + .content = + "1500000 1400000 1300000 1200000 1100000 1000000 900000 800000 700000 600000 500000 400000 \n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_governors", @@ -670,19 +669,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 135, - .content = - "1500000 5159\n" - "1400000 262\n" - "1300000 183\n" - "1200000 358\n" - "1100000 166\n" - "1000000 122\n" - "900000 802\n" - "800000 25\n" - "700000 20\n" - "600000 37\n" - "500000 56\n" - "400000 245\n", + .content = "1500000 5159\n" + "1400000 262\n" + "1300000 183\n" + "1200000 358\n" + "1100000 166\n" + "1000000 122\n" + "900000 802\n" + "800000 25\n" + "700000 20\n" + "600000 37\n" + "500000 56\n" + "400000 245\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -737,19 +735,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/time_in_state", .size = 134, - .content = - "1500000 4361\n" - "1400000 170\n" - "1300000 105\n" - "1200000 220\n" - "1100000 118\n" - "1000000 76\n" - "900000 823\n" - "800000 30\n" - "700000 70\n" - "600000 74\n" - "500000 94\n" - "400000 345\n", + .content = "1500000 4361\n" + "1400000 170\n" + "1300000 105\n" + "1200000 220\n" + "1100000 118\n" + "1000000 76\n" + "900000 823\n" + "800000 30\n" + "700000 70\n" + "600000 74\n" + "500000 94\n" + "400000 345\n", }, { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/total_trans", @@ -814,7 +811,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_available_frequencies", .size = 91, - .content = "1500000 1400000 1300000 1200000 1100000 1000000 900000 800000 700000 600000 500000 400000 \n", + .content = + "1500000 1400000 1300000 1200000 1100000 1000000 900000 800000 700000 600000 500000 400000 \n", }, { .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_available_governors", @@ -849,19 +847,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/time_in_state", .size = 135, - .content = - "1500000 4374\n" - "1400000 178\n" - "1300000 105\n" - "1200000 232\n" - "1100000 126\n" - "1000000 86\n" - "900000 962\n" - "800000 37\n" - "700000 73\n" - "600000 78\n" - "500000 106\n" - "400000 373\n", + .content = "1500000 4374\n" + "1400000 178\n" + "1300000 105\n" + "1200000 232\n" + "1100000 126\n" + "1000000 86\n" + "900000 962\n" + "800000 37\n" + "700000 73\n" + "600000 78\n" + "500000 106\n" + "400000 373\n", }, { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/total_trans", @@ -898,7 +895,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 3, .content = "80\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ @@ -2667,6 +2664,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.wfd.status", .value = "disconnected", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/galaxy-j7-uae.cc b/test/mock/galaxy-j7-uae.cc index a15ab66b..285d857d 100644 --- a/test/mock/galaxy-j7-uae.cc +++ b/test/mock/galaxy-j7-uae.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(8, cpuinfo_get_processors_count()); @@ -274,8 +273,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Samsung Exynos 7580", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Samsung Exynos 7580", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -317,59 +318,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -494,8 +495,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -546,8 +549,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -598,8 +603,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/galaxy-j7-uae.h b/test/mock/galaxy-j7-uae.h index 82c83804..ba4bd993 100644 --- a/test/mock/galaxy-j7-uae.h +++ b/test/mock/galaxy-j7-uae.h @@ -24,168 +24,167 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/system/build.prop", .size = 4597, - .content = - "\n" - "# begin build properties\n" - "# autogenerated by buildinfo.sh\n" - "ro.build.id=MMB29K\n" - "ro.build.display.id=MMB29K.J700FXXU4BQC6\n" - "ro.build.version.incremental=J700FXXU4BQC6\n" - "ro.build.version.sdk=23\n" - "ro.build.version.preview_sdk=0\n" - "ro.build.version.codename=REL\n" - "ro.build.version.all_codenames=REL\n" - "ro.build.version.release=6.0.1\n" - "ro.build.version.security_patch=2017-03-01\n" - "ro.build.version.base_os=\n" - "ro.build.date=Wed Mar 22 20:04:05 KST 2017\n" - "ro.build.date.utc=1490180645\n" - "ro.build.type=user\n" - "ro.build.user=dpi\n" - "ro.build.host=SWHC3715\n" - "ro.build.tags=release-keys\n" - "ro.build.flavor=j7eltexx-user\n" - "ro.product.model=SM-J700F\n" - "ro.product.brand=samsung\n" - "ro.product.name=j7eltexx\n" - "ro.product.device=j7elte\n" - "ro.product.board=universal7580\n" - "# ro.product.cpu.abi and ro.product.cpu.abi2 are obsolete,\n" - "# use ro.product.cpu.abilist instead.\n" - "ro.product.cpu.abi=armeabi-v7a\n" - "ro.product.cpu.abi2=armeabi\n" - "ro.product.cpu.abilist=armeabi-v7a,armeabi\n" - "ro.product.cpu.abilist32=armeabi-v7a,armeabi\n" - "ro.product.cpu.abilist64=\n" - "ro.product.manufacturer=samsung\n" - "ro.product.locale=en-GB\n" - "ro.wifi.channels=\n" - "ro.board.platform=exynos5\n" - "# ro.build.product is obsolete; use ro.product.device\n" - "ro.build.product=j7elte\n" - "# Do not try to parse description, fingerprint, or thumbprint\n" - "ro.build.description=j7eltexx-user 6.0.1 MMB29K J700FXXU4BQC6 release-keys\n" - "ro.build.fingerprint=samsung/j7eltexx/j7elte:6.0.1/MMB29K/J700FXXU4BQC6:user/release-keys\n" - "ro.build.characteristics=phone\n" - "# Samsung Specific Properties\n" - "ro.build.PDA=J700FXXU4BQC6\n" - "ro.build.hidden_ver=J700FXXU4BQC6\n" - "ro.config.rm_preload_enabled=0\n" - "ro.build.changelist=10198822\n" - "ro.product_ship=true\n" - "ro.build.official.release=true\n" - "ro.chipname=exynos7580\n" - "# end build properties\n" - "\n" - "#\n" - "# HWUI_BUILD_PROPERTIES\n" - "#\n" - "ro.hwui.texture_cache_size=24\n" - "ro.hwui.layer_cache_size=16\n" - "ro.hwui.path_cache_size=4\n" - "ro.hwui.texture_cache_flushrate=0.4\n" - "ro.hwui.shape_cache_size=1\n" - "ro.hwui.gradient_cache_size=0.5\n" - "ro.hwui.drop_shadow_cache_size=2\n" - "ro.hwui.r_buffer_cache_size=2\n" - "ro.hwui.text_small_cache_width=1024\n" - "ro.hwui.text_small_cache_height=512\n" - "ro.hwui.text_large_cache_width=2048\n" - "ro.hwui.text_large_cache_height=1024\n" - "#\n" - "# from device/samsung/j7elte/system.prop\n" - "#\n" - "#\n" - "# system.prop for universal7580\n" - "#\n" - "\n" - "ro.sf.lcd_density=320\n" - "\n" - "ro.arch=exynos7580\n" - "ro.kernel.qemu=0\n" - "ro.kernel.qemu.gles=1\n" - "persist.demo.hdmirotationlock=false\n" - "ro.zygote.disable_gl_preload=1\n" - "\n" - "# VQG - User Agent Header for Video-Streaming Client\n" - "net.streaming.rtsp.uaprof=http://wap.samsungmobile.com/uaprof/\n" - "\n" - "# SAMP_SPCM\n" - "sys.config.samp_spcm_enable=true\n" - "sys.config.spcm_db_enable=true\n" - "sys.config.spcm_db_launcher=true\n" - "sys.config.spcm_preload_enable=true\n" - "#\n" - "# ADDITIONAL_BUILD_PROPERTIES\n" - "#\n" - "ro.astcenc.astcsupport=1\n" - "ro.mct.compressiontype=ETC1\n" - "ro.config.tima=1\n" - "ro.config.timaversion=3.0\n" - "ro.config.dmverity=true\n" - "ro.config.rkp=true\n" - "ro.config.kap=true\n" - "persist.radio.sib16_support=0\n" - "ro.telephony.default_network=9\n" - "dalvik.vm.image-dex2oat-filter=speed\n" - "dalvik.vm.dex2oat-filter=speed\n" - "ro.config.ringtone=Over_the_Horizon.ogg\n" - "ro.config.notification_sound=Skyline.ogg\n" - "ro.config.alarm_alert=Morning_Flower.ogg\n" - "ro.config.media_sound=Media_preview_Touch_the_light.ogg\n" - "ro.config.ringtone_2=Basic_Bell.ogg\n" - "ro.config.notification_sound_2=S_Charming_Bell.ogg\n" - "ro.opengles.version=196609\n" - "ro.sf.lcd_density=480\n" - "debug.hwc.otf=1\n" - "debug.hwc.winupdate=1\n" - "drm.service.enabled=true\n" - "dalvik.vm.heapstartsize=8m\n" - "dalvik.vm.heapgrowthlimit=128m\n" - "dalvik.vm.heapsize=512m\n" - "dalvik.vm.heaptargetutilization=0.75\n" - "dalvik.vm.heapminfree=2m\n" - "dalvik.vm.heapmaxfree=8m\n" - "ro.security.vpnpp.ver=1.4\n" - "ro.security.vpnpp.release=7.0\n" - "ro.build.scafe.size=short\n" - "ro.build.scafe.shot=single\n" - "ro.build.scafe.cream=white\n" - "ro.build.scafe.version=2016A\n" - "ro.frp.pst=/dev/block/persistent\n" - "security.mdpp.mass=skmm\n" - "ro.sec.fle.encryption=true\n" - "ro.config.dha_cached_min=2\n" - "ro.config.dha_cached_max=5\n" - "ro.config.dha_empty_min=6\n" - "ro.config.dha_empty_max=16\n" - "ro.config.dha_empty_init=12\n" - "ro.config.dha_lmk_scale=0.66\n" - "ro.config.dha_th_rate=2.5\n" - "ro.error.receiver.default=com.samsung.receiver.error\n" - "sys.config.samp_spcm_enable=true\n" - "keyguard.no_require_sim=true\n" - "ro.carrier=unknown\n" - "ro.com.google.clientidbase=android-samsung\n" - "ro.security.icd.flagmode=multi\n" - "security.ASKS.policy_version=000000\n" - "ro.ril.hsxpa=1\n" - "ro.ril.gprsclass=10\n" - "ro.adb.qemud=1\n" - "ro.smps.enable=true\n" - "ro.setupwizard.mode=OPTIONAL\n" - "ro.com.google.gmsversion=6.0_r10\n" - "ro.build.selinux=1\n" - "persist.sys.dalvik.vm.lib.2=libart.so\n" - "dalvik.vm.isa.arm.variant=cortex-a15\n" - "dalvik.vm.isa.arm.features=default\n" - "ro.config.knox=v30\n" - "ro.kernel.qemu=0\n" - "net.bt.name=Android\n" - "dalvik.vm.stack-trace-file=/data/anr/traces.txt\n" - "ro.build.version.sdl=2301\n" - "ro.expect.recovery_id=0xc8326816ea212d9a942ed2888101dea9fa88529d000000000000000000000000\n" - "\n", + .content = "\n" + "# begin build properties\n" + "# autogenerated by buildinfo.sh\n" + "ro.build.id=MMB29K\n" + "ro.build.display.id=MMB29K.J700FXXU4BQC6\n" + "ro.build.version.incremental=J700FXXU4BQC6\n" + "ro.build.version.sdk=23\n" + "ro.build.version.preview_sdk=0\n" + "ro.build.version.codename=REL\n" + "ro.build.version.all_codenames=REL\n" + "ro.build.version.release=6.0.1\n" + "ro.build.version.security_patch=2017-03-01\n" + "ro.build.version.base_os=\n" + "ro.build.date=Wed Mar 22 20:04:05 KST 2017\n" + "ro.build.date.utc=1490180645\n" + "ro.build.type=user\n" + "ro.build.user=dpi\n" + "ro.build.host=SWHC3715\n" + "ro.build.tags=release-keys\n" + "ro.build.flavor=j7eltexx-user\n" + "ro.product.model=SM-J700F\n" + "ro.product.brand=samsung\n" + "ro.product.name=j7eltexx\n" + "ro.product.device=j7elte\n" + "ro.product.board=universal7580\n" + "# ro.product.cpu.abi and ro.product.cpu.abi2 are obsolete,\n" + "# use ro.product.cpu.abilist instead.\n" + "ro.product.cpu.abi=armeabi-v7a\n" + "ro.product.cpu.abi2=armeabi\n" + "ro.product.cpu.abilist=armeabi-v7a,armeabi\n" + "ro.product.cpu.abilist32=armeabi-v7a,armeabi\n" + "ro.product.cpu.abilist64=\n" + "ro.product.manufacturer=samsung\n" + "ro.product.locale=en-GB\n" + "ro.wifi.channels=\n" + "ro.board.platform=exynos5\n" + "# ro.build.product is obsolete; use ro.product.device\n" + "ro.build.product=j7elte\n" + "# Do not try to parse description, fingerprint, or thumbprint\n" + "ro.build.description=j7eltexx-user 6.0.1 MMB29K J700FXXU4BQC6 release-keys\n" + "ro.build.fingerprint=samsung/j7eltexx/j7elte:6.0.1/MMB29K/J700FXXU4BQC6:user/release-keys\n" + "ro.build.characteristics=phone\n" + "# Samsung Specific Properties\n" + "ro.build.PDA=J700FXXU4BQC6\n" + "ro.build.hidden_ver=J700FXXU4BQC6\n" + "ro.config.rm_preload_enabled=0\n" + "ro.build.changelist=10198822\n" + "ro.product_ship=true\n" + "ro.build.official.release=true\n" + "ro.chipname=exynos7580\n" + "# end build properties\n" + "\n" + "#\n" + "# HWUI_BUILD_PROPERTIES\n" + "#\n" + "ro.hwui.texture_cache_size=24\n" + "ro.hwui.layer_cache_size=16\n" + "ro.hwui.path_cache_size=4\n" + "ro.hwui.texture_cache_flushrate=0.4\n" + "ro.hwui.shape_cache_size=1\n" + "ro.hwui.gradient_cache_size=0.5\n" + "ro.hwui.drop_shadow_cache_size=2\n" + "ro.hwui.r_buffer_cache_size=2\n" + "ro.hwui.text_small_cache_width=1024\n" + "ro.hwui.text_small_cache_height=512\n" + "ro.hwui.text_large_cache_width=2048\n" + "ro.hwui.text_large_cache_height=1024\n" + "#\n" + "# from device/samsung/j7elte/system.prop\n" + "#\n" + "#\n" + "# system.prop for universal7580\n" + "#\n" + "\n" + "ro.sf.lcd_density=320\n" + "\n" + "ro.arch=exynos7580\n" + "ro.kernel.qemu=0\n" + "ro.kernel.qemu.gles=1\n" + "persist.demo.hdmirotationlock=false\n" + "ro.zygote.disable_gl_preload=1\n" + "\n" + "# VQG - User Agent Header for Video-Streaming Client\n" + "net.streaming.rtsp.uaprof=http://wap.samsungmobile.com/uaprof/\n" + "\n" + "# SAMP_SPCM\n" + "sys.config.samp_spcm_enable=true\n" + "sys.config.spcm_db_enable=true\n" + "sys.config.spcm_db_launcher=true\n" + "sys.config.spcm_preload_enable=true\n" + "#\n" + "# ADDITIONAL_BUILD_PROPERTIES\n" + "#\n" + "ro.astcenc.astcsupport=1\n" + "ro.mct.compressiontype=ETC1\n" + "ro.config.tima=1\n" + "ro.config.timaversion=3.0\n" + "ro.config.dmverity=true\n" + "ro.config.rkp=true\n" + "ro.config.kap=true\n" + "persist.radio.sib16_support=0\n" + "ro.telephony.default_network=9\n" + "dalvik.vm.image-dex2oat-filter=speed\n" + "dalvik.vm.dex2oat-filter=speed\n" + "ro.config.ringtone=Over_the_Horizon.ogg\n" + "ro.config.notification_sound=Skyline.ogg\n" + "ro.config.alarm_alert=Morning_Flower.ogg\n" + "ro.config.media_sound=Media_preview_Touch_the_light.ogg\n" + "ro.config.ringtone_2=Basic_Bell.ogg\n" + "ro.config.notification_sound_2=S_Charming_Bell.ogg\n" + "ro.opengles.version=196609\n" + "ro.sf.lcd_density=480\n" + "debug.hwc.otf=1\n" + "debug.hwc.winupdate=1\n" + "drm.service.enabled=true\n" + "dalvik.vm.heapstartsize=8m\n" + "dalvik.vm.heapgrowthlimit=128m\n" + "dalvik.vm.heapsize=512m\n" + "dalvik.vm.heaptargetutilization=0.75\n" + "dalvik.vm.heapminfree=2m\n" + "dalvik.vm.heapmaxfree=8m\n" + "ro.security.vpnpp.ver=1.4\n" + "ro.security.vpnpp.release=7.0\n" + "ro.build.scafe.size=short\n" + "ro.build.scafe.shot=single\n" + "ro.build.scafe.cream=white\n" + "ro.build.scafe.version=2016A\n" + "ro.frp.pst=/dev/block/persistent\n" + "security.mdpp.mass=skmm\n" + "ro.sec.fle.encryption=true\n" + "ro.config.dha_cached_min=2\n" + "ro.config.dha_cached_max=5\n" + "ro.config.dha_empty_min=6\n" + "ro.config.dha_empty_max=16\n" + "ro.config.dha_empty_init=12\n" + "ro.config.dha_lmk_scale=0.66\n" + "ro.config.dha_th_rate=2.5\n" + "ro.error.receiver.default=com.samsung.receiver.error\n" + "sys.config.samp_spcm_enable=true\n" + "keyguard.no_require_sim=true\n" + "ro.carrier=unknown\n" + "ro.com.google.clientidbase=android-samsung\n" + "ro.security.icd.flagmode=multi\n" + "security.ASKS.policy_version=000000\n" + "ro.ril.hsxpa=1\n" + "ro.ril.gprsclass=10\n" + "ro.adb.qemud=1\n" + "ro.smps.enable=true\n" + "ro.setupwizard.mode=OPTIONAL\n" + "ro.com.google.gmsversion=6.0_r10\n" + "ro.build.selinux=1\n" + "persist.sys.dalvik.vm.lib.2=libart.so\n" + "dalvik.vm.isa.arm.variant=cortex-a15\n" + "dalvik.vm.isa.arm.features=default\n" + "ro.config.knox=v30\n" + "ro.kernel.qemu=0\n" + "net.bt.name=Android\n" + "dalvik.vm.stack-trace-file=/data/anr/traces.txt\n" + "ro.build.version.sdl=2301\n" + "ro.expect.recovery_id=0xc8326816ea212d9a942ed2888101dea9fa88529d000000000000000000000000\n" + "\n", }, { .path = "/sys/devices/system/cpu/kernel_max", @@ -220,20 +219,19 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpufreq/all_time_in_state", .size = 481, - .content = - "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\t\n" - "400000\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t\n" - "500000\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t\n" - "600000\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t\n" - "700000\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t\n" - "800000\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t\n" - "900000\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t\n" - "1000000\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t\n" - "1100000\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t\n" - "1200000\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t\n" - "1300000\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t\n" - "1400000\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t\n" - "1500000\t\t1998\t\t1998\t\t1998\t\t1998\t\t1998\t\t1998\t\t1998\t\t1998\t\t\n", + .content = "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\t\n" + "400000\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t\n" + "500000\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t\n" + "600000\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t\n" + "700000\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t\n" + "800000\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t\n" + "900000\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t\n" + "1000000\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t\n" + "1100000\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t\n" + "1200000\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t\n" + "1300000\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t\n" + "1400000\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t\n" + "1500000\t\t1998\t\t1998\t\t1998\t\t1998\t\t1998\t\t1998\t\t1998\t\t1998\t\t\n", }, { .path = "/sys/devices/system/cpu/cpuidle/current_driver", @@ -273,11 +271,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/clusterhotplug/time_in_state", .size = 24, - .content = - "H0 21198\n" - "H1 0\n" - "H2 0\n" - "H3 0\n", + .content = "H0 21198\n" + "H1 0\n" + "H2 0\n" + "H3 0\n", }, { .path = "/sys/devices/system/cpu/clusterhotplug/up_freq", @@ -322,7 +319,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies", .size = 91, - .content = "1500000 1400000 1300000 1200000 1100000 1000000 900000 800000 700000 600000 500000 400000 \n", + .content = + "1500000 1400000 1300000 1200000 1100000 1000000 900000 800000 700000 600000 500000 400000 \n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors", @@ -352,19 +350,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 117, - .content = - "1500000 2059\n" - "1400000 0\n" - "1300000 0\n" - "1200000 0\n" - "1100000 0\n" - "1000000 0\n" - "900000 0\n" - "800000 0\n" - "700000 0\n" - "600000 0\n" - "500000 0\n" - "400000 0\n", + .content = "1500000 2059\n" + "1400000 0\n" + "1300000 0\n" + "1200000 0\n" + "1100000 0\n" + "1000000 0\n" + "900000 0\n" + "800000 0\n" + "700000 0\n" + "600000 0\n" + "500000 0\n" + "400000 0\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -429,7 +426,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_frequencies", .size = 91, - .content = "1500000 1400000 1300000 1200000 1100000 1000000 900000 800000 700000 600000 500000 400000 \n", + .content = + "1500000 1400000 1300000 1200000 1100000 1000000 900000 800000 700000 600000 500000 400000 \n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_governors", @@ -459,19 +457,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 117, - .content = - "1500000 2280\n" - "1400000 0\n" - "1300000 0\n" - "1200000 0\n" - "1100000 0\n" - "1000000 0\n" - "900000 0\n" - "800000 0\n" - "700000 0\n" - "600000 0\n" - "500000 0\n" - "400000 0\n", + .content = "1500000 2280\n" + "1400000 0\n" + "1300000 0\n" + "1200000 0\n" + "1100000 0\n" + "1000000 0\n" + "900000 0\n" + "800000 0\n" + "700000 0\n" + "600000 0\n" + "500000 0\n" + "400000 0\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -536,7 +533,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_frequencies", .size = 91, - .content = "1500000 1400000 1300000 1200000 1100000 1000000 900000 800000 700000 600000 500000 400000 \n", + .content = + "1500000 1400000 1300000 1200000 1100000 1000000 900000 800000 700000 600000 500000 400000 \n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_governors", @@ -566,19 +564,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 117, - .content = - "1500000 2520\n" - "1400000 0\n" - "1300000 0\n" - "1200000 0\n" - "1100000 0\n" - "1000000 0\n" - "900000 0\n" - "800000 0\n" - "700000 0\n" - "600000 0\n" - "500000 0\n" - "400000 0\n", + .content = "1500000 2520\n" + "1400000 0\n" + "1300000 0\n" + "1200000 0\n" + "1100000 0\n" + "1000000 0\n" + "900000 0\n" + "800000 0\n" + "700000 0\n" + "600000 0\n" + "500000 0\n" + "400000 0\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -643,7 +640,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_available_frequencies", .size = 91, - .content = "1500000 1400000 1300000 1200000 1100000 1000000 900000 800000 700000 600000 500000 400000 \n", + .content = + "1500000 1400000 1300000 1200000 1100000 1000000 900000 800000 700000 600000 500000 400000 \n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_available_governors", @@ -678,19 +676,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/time_in_state", .size = 117, - .content = - "1500000 2980\n" - "1400000 0\n" - "1300000 0\n" - "1200000 0\n" - "1100000 0\n" - "1000000 0\n" - "900000 0\n" - "800000 0\n" - "700000 0\n" - "600000 0\n" - "500000 0\n" - "400000 0\n", + .content = "1500000 2980\n" + "1400000 0\n" + "1300000 0\n" + "1200000 0\n" + "1100000 0\n" + "1000000 0\n" + "900000 0\n" + "800000 0\n" + "700000 0\n" + "600000 0\n" + "500000 0\n" + "400000 0\n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/total_trans", @@ -755,7 +752,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_available_frequencies", .size = 91, - .content = "1500000 1400000 1300000 1200000 1100000 1000000 900000 800000 700000 600000 500000 400000 \n", + .content = + "1500000 1400000 1300000 1200000 1100000 1000000 900000 800000 700000 600000 500000 400000 \n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_available_governors", @@ -790,19 +788,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/time_in_state", .size = 120, - .content = - "1500000 3105\n" - "1400000 58\n" - "1300000 1\n" - "1200000 14\n" - "1100000 0\n" - "1000000 6\n" - "900000 27\n" - "800000 0\n" - "700000 0\n" - "600000 0\n" - "500000 0\n" - "400000 6\n", + .content = "1500000 3105\n" + "1400000 58\n" + "1300000 1\n" + "1200000 14\n" + "1100000 0\n" + "1000000 6\n" + "900000 27\n" + "800000 0\n" + "700000 0\n" + "600000 0\n" + "500000 0\n" + "400000 6\n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/total_trans", @@ -839,7 +836,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 3, .content = "20\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ @@ -2356,6 +2353,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.wfd.status", .value = "disconnected", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/galaxy-s3-us.cc b/test/mock/galaxy-s3-us.cc index db859180..50ba73cb 100644 --- a/test/mock/galaxy-s3-us.cc +++ b/test/mock/galaxy-s3-us.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(2, cpuinfo_get_processors_count()); @@ -208,8 +207,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Qualcomm MSM8960", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Qualcomm MSM8960", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -400,8 +401,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -452,8 +455,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -492,9 +497,7 @@ TEST(L2, non_null) { TEST(L2, size) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - switch (i) { - ASSERT_EQ(1 * 1024 * 1024, cpuinfo_get_l2_cache(i)->size); - } + switch (i) { ASSERT_EQ(1 * 1024 * 1024, cpuinfo_get_l2_cache(i)->size); } } } @@ -506,8 +509,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/galaxy-s3-us.h b/test/mock/galaxy-s3-us.h index 655b2f71..0cce00b1 100644 --- a/test/mock/galaxy-s3-us.h +++ b/test/mock/galaxy-s3-us.h @@ -2,236 +2,234 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 335, - .content = - "Processor\t: ARMv7 Processor rev 4 (v7l)\n" - "processor\t: 0\n" - "BogoMIPS\t: 13.53\n" - "\n" - "processor\t: 1\n" - "BogoMIPS\t: 13.53\n" - "\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 \n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x1\n" - "CPU part\t: 0x04d\n" - "CPU revision\t: 4\n" - "\n" - "Hardware\t: SAMSUNG M2_ATT\n" - "Revision\t: 0010\n" - "Serial\t\t: 0000eb0d0000f3a2\n", + .content = "Processor\t: ARMv7 Processor rev 4 (v7l)\n" + "processor\t: 0\n" + "BogoMIPS\t: 13.53\n" + "\n" + "processor\t: 1\n" + "BogoMIPS\t: 13.53\n" + "\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 \n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0x04d\n" + "CPU revision\t: 4\n" + "\n" + "Hardware\t: SAMSUNG M2_ATT\n" + "Revision\t: 0010\n" + "Serial\t\t: 0000eb0d0000f3a2\n", }, { .path = "/system/build.prop", .size = 5377, - .content = - "# begin build properties\n" - "# autogenerated by buildinfo.sh\n" - "ro.build.id=JRO03L\n" - "ro.build.display.id=JRO03L.I747UCDLK3\n" - "ro.build.version.incremental=I747UCDLK3\n" - "ro.build.version.sdk=16\n" - "ro.build.version.codename=REL\n" - "ro.build.version.release=4.1.1\n" - "ro.build.date=Thu Nov 15 15:56:47 KST 2012\n" - "ro.build.date.utc=1352962607\n" - "ro.build.type=user\n" - "ro.build.user=se.infra\n" - "ro.build.host=SEP-103\n" - "ro.build.tags=release-keys\n" - "ro.product.model=SAMSUNG-SGH-I747\n" - "ro.product.brand=samsung\n" - "ro.product.name=d2uc\n" - "ro.product.device=d2att\n" - "ro.product.board=MSM8960\n" - "ro.chipname=MSM8960\n" - "ro.product.cpu.abi=armeabi-v7a\n" - "ro.product.cpu.abi2=armeabi\n" - "ro.product_ship=true\n" - "ro.product.manufacturer=samsung\n" - "ro.product.locale.language=en\n" - "ro.product.locale.region=GB\n" - "ro.wifi.channels=\n" - "ro.board.platform=msm8960\n" - "# ro.build.product is obsolete; use ro.product.device\n" - "ro.build.product=d2att\n" - "# Do not try to parse ro.build.description or .fingerprint\n" - "ro.build.description=d2uc-user 4.1.1 JRO03L I747UCDLK3 release-keys\n" - "ro.build.fingerprint=samsung/d2uc/d2att:4.1.1/JRO03L/I747UCDLK3:user/release-keys\n" - "ro.build.characteristics=att\n" - "# Samsung Specific Properties\n" - "ro.build.PDA=I747UCDLK3\n" - "ro.build.hidden_ver=I747UCDLK3\n" - "ro.build.changelist=274808\n" - "# end build properties\n" - "#\n" - "# system.prop for surf\n" - "#\n" - "\n" - "rild.libpath=/system/lib/libril-qc-qmi-1.so\n" - "rild.libargs=-d /dev/smd0\n" - "persist.rild.nitz_plmn=\n" - "persist.rild.nitz_long_ons_0=\n" - "persist.rild.nitz_long_ons_1=\n" - "persist.rild.nitz_long_ons_2=\n" - "persist.rild.nitz_long_ons_3=\n" - "persist.rild.nitz_short_ons_0=\n" - "persist.rild.nitz_short_ons_1=\n" - "persist.rild.nitz_short_ons_2=\n" - "persist.rild.nitz_short_ons_3=\n" - "ril.subscription.types=NV,RUIM\n" - "DEVICE_PROVISIONED=1\n" - "debug.sf.hw=1\n" - "debug.egl.hw=1\n" - "debug.composition.type=dyn\n" - "debug.compbypass.enable=1\n" - "debug.hwui.render_dirty_regions=true\n" - "dalvik.vm.heapsize=36m\n" - "debug.enable.wl_log=1\n" - "debug.mdpcomp.maxlayer=3\n" - "\n" - "#\n" - "# system props for the cne module\n" - "#\n" - "persist.cne.bat.range.low.med=30\n" - "persist.cne.bat.range.med.high=60\n" - "persist.cne.loc.policy.op=/system/etc/OperatorPolicy.xml\n" - "persist.cne.loc.policy.user=/system/etc/UserPolicy.xml\n" - "persist.cne.bwbased.rat.sel=false\n" - "persist.cne.snsr.based.rat.mgt=false\n" - "persist.cne.bat.based.rat.mgt=false\n" - "persist.cne.rat.acq.time.out=30000\n" - "persist.cne.rat.acq.retry.tout=0\n" - "persist.cne.feature=0\n" - "\n" - "ro.hdmi.enable=true\n" - "lpa.decode=true\n" - "lpa.use-stagefright=true\n" - "\n" - "#system props for the MM modules\n" - "\n" - "media.stagefright.enable-player=true\n" - "media.stagefright.enable-http=true\n" - "media.stagefright.enable-aac=true\n" - "media.stagefright.enable-qcp=true\n" - "media.stagefright.enable-fma2dp=true\n" - "media.stagefright.enable-scan=true\n" - "mmp.enable.3g2=true\n" - "\n" - "#\n" - "# system props for the data modules\n" - "#\n" - "ro.use_data_netmgrd=true\n" - "\n" - "#system props for time-services\n" - "persist.timed.enable=true\n" - "\n" - "# System props for audio\n" - "persist.audio.fluence.mode=endfire\n" - "persist.audio.vr.enable=false\n" - "persist.audio.handset.mic=digital\n" - "\n" - "# System prop to select audio resampler quality\n" - "af.resampler.quality=255\n" - "# System prop to select MPQAudioPlayer by default on mpq8064\n" - "mpq.audio.decode=true\n" - "\n" - "#\n" - "# system prop for opengles version\n" - "#\n" - "# 131072 is decimal for 0x20000 to report version 2\n" - "ro.opengles.version=131072\n" - "\n" - "#\n" - "# system property for Bluetooth Handsfree Profile version\n" - "#\n" - "ro.bluetooth.hfp.ver=1.6\n" - "#\n" - "#system prop for Bluetooth hci transport\n" - "ro.qualcomm.bt.hci_transport=smd\n" - "#\n" - "# system prop for requesting Master role in incoming Bluetooth connection.\n" - "#\n" - "ro.bluetooth.request.master=true\n" - "#\n" - "# system prop for Bluetooth Auto connect for remote initated connections\n" - "#\n" - "ro.bluetooth.remote.autoconnect=true\n" - "# system property for Bluetooth discoverability time out in seconds\n" - "# 0: Always discoverable\n" - "#debug.bt.discoverable_time=0\n" - "\n" - "#system prop for switching gps driver to qmi\n" - "persist.gps.qmienabled=true\n" - "\n" - "# System property for cabl\n" - "ro.qualcomm.cabl=1\n" - "\n" - "#\n" - "# System prop for sending transmit power request to RIL during WiFi hotspot on/off\n" - "#\n" - "ro.ril.transmitpower=true\n" - "\n" - "#\n" - "#Simulate sdcard on /data/media\n" - "#\n" - "persist.fuse_sdcard=true\n" - "ro.hwui.text_cache_width=2048\n" - "\n" - "#\n" - "# Supports warmboot capabilities\n" - "#\n" - "ro.warmboot.capability=1\n" - "\n" - "ro.sf.lcd_density=320\n" - "\n" - "# Keep SIM state on LPM mode\n" - "persist.radio.apm_sim_not_pwdn=1\n" - "\n" - "# System property for Default touch key light duration\n" - "ro.button_key_light=6000\n" - "\n" - "# System proverty for sys info indication\n" - "persist.radio.add_power_save=1\n" - "\n" - "# System property for HDMI/WFD\n" - "persist.sys.camera.connect=0\n" - "persist.sys.camera.transform=0\n" - "persist.sys.videomode=0\n" - "#\n" - "# ADDITIONAL_BUILD_PROPERTIES\n" - "#\n" - "ro.vendor.extension_library=/system/lib/libqc-opt.so\n" - "ro.error.receiver.default=com.samsung.receiver.error\n" - "dalvik.vm.heapstartsize=8m\n" - "dalvik.vm.heapgrowthlimit=64m\n" - "dalvik.vm.heapsize=256m\n" - "dalvik.vm.heaputilization=0.25\n" - "dalvik.vm.heapidealfree=8388608\n" - "dalvik.vm.heapconcurrentstart=2097152\n" - "ro.hdcp2.rx=tz\n" - "ro.sec.fle.encryption=true\n" - "ro.config.alarm_alert=Walk_in_the_forest.ogg\n" - "ro.config.ringtone=ATT_Firefly_Default.ogg\n" - "ro.config.notification_sound=S_Whistle.ogg\n" - "ro.monkey=0\n" - "keyguard.no_require_sim=true\n" - "ro.com.android.dateformat=MM-dd-yyyy\n" - "ro.carrier=unknown\n" - "ro.ril.hsxpa=1\n" - "ro.ril.gprsclass=10\n" - "ro.adb.qemud=1\n" - "ro.setupwizard.mode=OPTIONAL\n" - "ro.com.google.apphider=off\n" - "ro.com.google.clientidbase=android-samsung\n" - "ro.com.google.clientidbase.ms=android-att-us\n" - "ro.com.google.clientidbase.am=android-att-us\n" - "ro.com.google.clientidbase.yt=android-samsung\n" - "ro.com.google.clientidbase.gmm=android-samsung\n" - "ro.com.google.gmsversion=4.1_r3\n" - "net.bt.name=Android\n" - "dalvik.vm.stack-trace-file=/data/anr/traces.txt\n" - "\n", + .content = "# begin build properties\n" + "# autogenerated by buildinfo.sh\n" + "ro.build.id=JRO03L\n" + "ro.build.display.id=JRO03L.I747UCDLK3\n" + "ro.build.version.incremental=I747UCDLK3\n" + "ro.build.version.sdk=16\n" + "ro.build.version.codename=REL\n" + "ro.build.version.release=4.1.1\n" + "ro.build.date=Thu Nov 15 15:56:47 KST 2012\n" + "ro.build.date.utc=1352962607\n" + "ro.build.type=user\n" + "ro.build.user=se.infra\n" + "ro.build.host=SEP-103\n" + "ro.build.tags=release-keys\n" + "ro.product.model=SAMSUNG-SGH-I747\n" + "ro.product.brand=samsung\n" + "ro.product.name=d2uc\n" + "ro.product.device=d2att\n" + "ro.product.board=MSM8960\n" + "ro.chipname=MSM8960\n" + "ro.product.cpu.abi=armeabi-v7a\n" + "ro.product.cpu.abi2=armeabi\n" + "ro.product_ship=true\n" + "ro.product.manufacturer=samsung\n" + "ro.product.locale.language=en\n" + "ro.product.locale.region=GB\n" + "ro.wifi.channels=\n" + "ro.board.platform=msm8960\n" + "# ro.build.product is obsolete; use ro.product.device\n" + "ro.build.product=d2att\n" + "# Do not try to parse ro.build.description or .fingerprint\n" + "ro.build.description=d2uc-user 4.1.1 JRO03L I747UCDLK3 release-keys\n" + "ro.build.fingerprint=samsung/d2uc/d2att:4.1.1/JRO03L/I747UCDLK3:user/release-keys\n" + "ro.build.characteristics=att\n" + "# Samsung Specific Properties\n" + "ro.build.PDA=I747UCDLK3\n" + "ro.build.hidden_ver=I747UCDLK3\n" + "ro.build.changelist=274808\n" + "# end build properties\n" + "#\n" + "# system.prop for surf\n" + "#\n" + "\n" + "rild.libpath=/system/lib/libril-qc-qmi-1.so\n" + "rild.libargs=-d /dev/smd0\n" + "persist.rild.nitz_plmn=\n" + "persist.rild.nitz_long_ons_0=\n" + "persist.rild.nitz_long_ons_1=\n" + "persist.rild.nitz_long_ons_2=\n" + "persist.rild.nitz_long_ons_3=\n" + "persist.rild.nitz_short_ons_0=\n" + "persist.rild.nitz_short_ons_1=\n" + "persist.rild.nitz_short_ons_2=\n" + "persist.rild.nitz_short_ons_3=\n" + "ril.subscription.types=NV,RUIM\n" + "DEVICE_PROVISIONED=1\n" + "debug.sf.hw=1\n" + "debug.egl.hw=1\n" + "debug.composition.type=dyn\n" + "debug.compbypass.enable=1\n" + "debug.hwui.render_dirty_regions=true\n" + "dalvik.vm.heapsize=36m\n" + "debug.enable.wl_log=1\n" + "debug.mdpcomp.maxlayer=3\n" + "\n" + "#\n" + "# system props for the cne module\n" + "#\n" + "persist.cne.bat.range.low.med=30\n" + "persist.cne.bat.range.med.high=60\n" + "persist.cne.loc.policy.op=/system/etc/OperatorPolicy.xml\n" + "persist.cne.loc.policy.user=/system/etc/UserPolicy.xml\n" + "persist.cne.bwbased.rat.sel=false\n" + "persist.cne.snsr.based.rat.mgt=false\n" + "persist.cne.bat.based.rat.mgt=false\n" + "persist.cne.rat.acq.time.out=30000\n" + "persist.cne.rat.acq.retry.tout=0\n" + "persist.cne.feature=0\n" + "\n" + "ro.hdmi.enable=true\n" + "lpa.decode=true\n" + "lpa.use-stagefright=true\n" + "\n" + "#system props for the MM modules\n" + "\n" + "media.stagefright.enable-player=true\n" + "media.stagefright.enable-http=true\n" + "media.stagefright.enable-aac=true\n" + "media.stagefright.enable-qcp=true\n" + "media.stagefright.enable-fma2dp=true\n" + "media.stagefright.enable-scan=true\n" + "mmp.enable.3g2=true\n" + "\n" + "#\n" + "# system props for the data modules\n" + "#\n" + "ro.use_data_netmgrd=true\n" + "\n" + "#system props for time-services\n" + "persist.timed.enable=true\n" + "\n" + "# System props for audio\n" + "persist.audio.fluence.mode=endfire\n" + "persist.audio.vr.enable=false\n" + "persist.audio.handset.mic=digital\n" + "\n" + "# System prop to select audio resampler quality\n" + "af.resampler.quality=255\n" + "# System prop to select MPQAudioPlayer by default on mpq8064\n" + "mpq.audio.decode=true\n" + "\n" + "#\n" + "# system prop for opengles version\n" + "#\n" + "# 131072 is decimal for 0x20000 to report version 2\n" + "ro.opengles.version=131072\n" + "\n" + "#\n" + "# system property for Bluetooth Handsfree Profile version\n" + "#\n" + "ro.bluetooth.hfp.ver=1.6\n" + "#\n" + "#system prop for Bluetooth hci transport\n" + "ro.qualcomm.bt.hci_transport=smd\n" + "#\n" + "# system prop for requesting Master role in incoming Bluetooth connection.\n" + "#\n" + "ro.bluetooth.request.master=true\n" + "#\n" + "# system prop for Bluetooth Auto connect for remote initated connections\n" + "#\n" + "ro.bluetooth.remote.autoconnect=true\n" + "# system property for Bluetooth discoverability time out in seconds\n" + "# 0: Always discoverable\n" + "#debug.bt.discoverable_time=0\n" + "\n" + "#system prop for switching gps driver to qmi\n" + "persist.gps.qmienabled=true\n" + "\n" + "# System property for cabl\n" + "ro.qualcomm.cabl=1\n" + "\n" + "#\n" + "# System prop for sending transmit power request to RIL during WiFi hotspot on/off\n" + "#\n" + "ro.ril.transmitpower=true\n" + "\n" + "#\n" + "#Simulate sdcard on /data/media\n" + "#\n" + "persist.fuse_sdcard=true\n" + "ro.hwui.text_cache_width=2048\n" + "\n" + "#\n" + "# Supports warmboot capabilities\n" + "#\n" + "ro.warmboot.capability=1\n" + "\n" + "ro.sf.lcd_density=320\n" + "\n" + "# Keep SIM state on LPM mode\n" + "persist.radio.apm_sim_not_pwdn=1\n" + "\n" + "# System property for Default touch key light duration\n" + "ro.button_key_light=6000\n" + "\n" + "# System proverty for sys info indication\n" + "persist.radio.add_power_save=1\n" + "\n" + "# System property for HDMI/WFD\n" + "persist.sys.camera.connect=0\n" + "persist.sys.camera.transform=0\n" + "persist.sys.videomode=0\n" + "#\n" + "# ADDITIONAL_BUILD_PROPERTIES\n" + "#\n" + "ro.vendor.extension_library=/system/lib/libqc-opt.so\n" + "ro.error.receiver.default=com.samsung.receiver.error\n" + "dalvik.vm.heapstartsize=8m\n" + "dalvik.vm.heapgrowthlimit=64m\n" + "dalvik.vm.heapsize=256m\n" + "dalvik.vm.heaputilization=0.25\n" + "dalvik.vm.heapidealfree=8388608\n" + "dalvik.vm.heapconcurrentstart=2097152\n" + "ro.hdcp2.rx=tz\n" + "ro.sec.fle.encryption=true\n" + "ro.config.alarm_alert=Walk_in_the_forest.ogg\n" + "ro.config.ringtone=ATT_Firefly_Default.ogg\n" + "ro.config.notification_sound=S_Whistle.ogg\n" + "ro.monkey=0\n" + "keyguard.no_require_sim=true\n" + "ro.com.android.dateformat=MM-dd-yyyy\n" + "ro.carrier=unknown\n" + "ro.ril.hsxpa=1\n" + "ro.ril.gprsclass=10\n" + "ro.adb.qemud=1\n" + "ro.setupwizard.mode=OPTIONAL\n" + "ro.com.google.apphider=off\n" + "ro.com.google.clientidbase=android-samsung\n" + "ro.com.google.clientidbase.ms=android-att-us\n" + "ro.com.google.clientidbase.am=android-att-us\n" + "ro.com.google.clientidbase.yt=android-samsung\n" + "ro.com.google.clientidbase.gmm=android-samsung\n" + "ro.com.google.gmsversion=4.1_r3\n" + "net.bt.name=Android\n" + "dalvik.vm.stack-trace-file=/data/anr/traces.txt\n" + "\n", }, { .path = "/sys/devices/system/cpu/kernel_max", @@ -296,7 +294,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies", .size = 91, - .content = "384000 486000 594000 702000 810000 918000 1026000 1134000 1242000 1350000 1458000 1512000 \n", + .content = + "384000 486000 594000 702000 810000 918000 1026000 1134000 1242000 1350000 1458000 1512000 \n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors", @@ -326,19 +325,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 116, - .content = - "384000 0\n" - "486000 0\n" - "594000 0\n" - "702000 0\n" - "810000 0\n" - "918000 0\n" - "1026000 0\n" - "1134000 0\n" - "1242000 0\n" - "1350000 0\n" - "1458000 0\n" - "1512000 818\n", + .content = "384000 0\n" + "486000 0\n" + "594000 0\n" + "702000 0\n" + "810000 0\n" + "918000 0\n" + "1026000 0\n" + "1134000 0\n" + "1242000 0\n" + "1350000 0\n" + "1458000 0\n" + "1512000 818\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -403,7 +401,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_frequencies", .size = 91, - .content = "384000 486000 594000 702000 810000 918000 1026000 1134000 1242000 1350000 1458000 1512000 \n", + .content = + "384000 486000 594000 702000 810000 918000 1026000 1134000 1242000 1350000 1458000 1512000 \n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_governors", @@ -438,19 +437,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 117, - .content = - "384000 0\n" - "486000 0\n" - "594000 0\n" - "702000 0\n" - "810000 0\n" - "918000 0\n" - "1026000 0\n" - "1134000 0\n" - "1242000 0\n" - "1350000 0\n" - "1458000 0\n" - "1512000 1064\n", + .content = "384000 0\n" + "486000 0\n" + "594000 0\n" + "702000 0\n" + "810000 0\n" + "918000 0\n" + "1026000 0\n" + "1134000 0\n" + "1242000 0\n" + "1350000 0\n" + "1458000 0\n" + "1512000 1064\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -487,7 +485,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "2\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ @@ -1612,6 +1610,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.wfd.tcp", .value = "0", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/galaxy-s4-us.cc b/test/mock/galaxy-s4-us.cc index 8da4841b..d9491207 100644 --- a/test/mock/galaxy-s4-us.cc +++ b/test/mock/galaxy-s4-us.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(4, cpuinfo_get_processors_count()); @@ -208,8 +207,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Qualcomm APQ8064", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Qualcomm APQ8064", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -400,8 +401,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -452,8 +455,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -492,9 +497,7 @@ TEST(L2, non_null) { TEST(L2, size) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - switch (i) { - ASSERT_EQ(2 * 1024 * 1024, cpuinfo_get_l2_cache(i)->size); - } + switch (i) { ASSERT_EQ(2 * 1024 * 1024, cpuinfo_get_l2_cache(i)->size); } } } @@ -506,8 +509,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/galaxy-s4-us.h b/test/mock/galaxy-s4-us.h index ec194098..b0ca554b 100644 --- a/test/mock/galaxy-s4-us.h +++ b/test/mock/galaxy-s4-us.h @@ -2,301 +2,299 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 395, - .content = - "Processor\t: ARMv7 Processor rev 0 (v7l)\n" - "processor\t: 0\n" - "BogoMIPS\t: 13.53\n" - "\n" - "processor\t: 1\n" - "BogoMIPS\t: 13.53\n" - "\n" - "processor\t: 2\n" - "BogoMIPS\t: 13.53\n" - "\n" - "processor\t: 3\n" - "BogoMIPS\t: 13.53\n" - "\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 \n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x1\n" - "CPU part\t: 0x06f\n" - "CPU revision\t: 0\n" - "\n" - "Hardware\t: SAMSUNG JF\n" - "Revision\t: 000a\n" - "Serial\t\t: 000012a70000ac49\n", + .content = "Processor\t: ARMv7 Processor rev 0 (v7l)\n" + "processor\t: 0\n" + "BogoMIPS\t: 13.53\n" + "\n" + "processor\t: 1\n" + "BogoMIPS\t: 13.53\n" + "\n" + "processor\t: 2\n" + "BogoMIPS\t: 13.53\n" + "\n" + "processor\t: 3\n" + "BogoMIPS\t: 13.53\n" + "\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 \n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0x06f\n" + "CPU revision\t: 0\n" + "\n" + "Hardware\t: SAMSUNG JF\n" + "Revision\t: 000a\n" + "Serial\t\t: 000012a70000ac49\n", }, { .path = "/system/build.prop", .size = 6846, - .content = - "# begin build properties\n" - "# autogenerated by buildinfo.sh\n" - "ro.build.id=KOT49H\n" - "ro.build.display.id=KOT49H.I337UCUFNC1\n" - "ro.build.version.incremental=I337UCUFNC1\n" - "ro.build.version.sdk=19\n" - "ro.build.version.codename=REL\n" - "ro.build.version.release=4.4.2\n" - "ro.build.date=Tue Mar 25 13:32:47 KST 2014\n" - "ro.build.date.utc=1395721967\n" - "ro.build.type=user\n" - "ro.build.user=dpi\n" - "ro.build.host=SWDD5916\n" - "ro.build.tags=release-keys\n" - "ro.product.model=SAMSUNG-SGH-I337\n" - "ro.product.brand=samsung\n" - "ro.product.name=jflteuc\n" - "ro.product.device=jflteatt\n" - "ro.product.board=MSM8960\n" - "ro.product.cpu.abi=armeabi-v7a\n" - "ro.product.cpu.abi2=armeabi\n" - "ro.product.manufacturer=samsung\n" - "ro.product.locale.language=en\n" - "ro.product.locale.region=US\n" - "ro.wifi.channels=\n" - "ro.board.platform=msm8960\n" - "# ro.build.product is obsolete; use ro.product.device\n" - "ro.build.product=jflteatt\n" - "# Do not try to parse ro.build.description or .fingerprint\n" - "ro.build.description=jflteuc-user 4.4.2 KOT49H I337UCUFNC1 release-keys\n" - "ro.build.fingerprint=samsung/jflteuc/jflteatt:4.4.2/KOT49H/I337UCUFNC1:user/release-keys\n" - "ro.build.characteristics=att\n" - "# Samsung Specific Properties\n" - "ro.build.PDA=I337UCUFNC1\n" - "ro.build.hidden_ver=I337UCUFNC1\n" - "ro.build.changelist=1125940\n" - "ro.product_ship=true\n" - "ro.chipname=apq8064\n" - "# end build properties\n" - "#\n" - "# from device/samsung/jflteatt/system.prop\n" - "#\n" - "#\n" - "# system.prop for surf\n" - "#\n" - "\n" - "ro.sf.lcd_density=480\n" - "\n" - "rild.libpath=/system/lib/libsec-ril.so\n" - "rild.libargs=-d /dev/smd0\n" - "persist.rild.nitz_plmn=\n" - "persist.rild.nitz_long_ons_0=\n" - "persist.rild.nitz_long_ons_1=\n" - "persist.rild.nitz_long_ons_2=\n" - "persist.rild.nitz_long_ons_3=\n" - "persist.rild.nitz_short_ons_0=\n" - "persist.rild.nitz_short_ons_1=\n" - "persist.rild.nitz_short_ons_2=\n" - "persist.rild.nitz_short_ons_3=\n" - "ril.subscription.types=NV,RUIM\n" - "DEVICE_PROVISIONED=1\n" - "debug.sf.hw=1\n" - "debug.egl.hw=1\n" - "debug.composition.type=gpu\n" - "dalvik.vm.heapsize=36m\n" - "debug.enable.wl_log=1\n" - "persist.hwc.mdpcomp.enable=true\n" - "debug.mdpcomp.logs=0\n" - "\n" - "#\n" - "# system props for the cne module\n" - "#\n" - "persist.cne.feature=0\n" - "\n" - "lpa.decode=false\n" - "tunnel.decode=true\n" - "tunnel.audiovideo.decode=false\n" - "lpa.use-stagefright=true\n" - "qcom.hw.aac.encoder=true\n" - "\n" - "#system props for the MM modules\n" - "\n" - "media.stagefright.enable-player=true\n" - "media.stagefright.enable-http=true\n" - "media.stagefright.enable-aac=true\n" - "media.stagefright.enable-qcp=true\n" - "media.stagefright.enable-fma2dp=true\n" - "media.stagefright.enable-scan=true\n" - "mmp.enable.3g2=true\n" - "media.aac_51_output_enabled=true\n" - "#33395 is sum of supported format flags in AAL\n" - "#Formats: AVI AC3 ASF AAC QCP DTS 3G2\n" - "mm.enable.qcom_parser=33395\n" - "\n" - "#\n" - "# system props for the data modules\n" - "#\n" - "ro.use_data_netmgrd=true\n" - "persist.data.netmgrd.qos.enable=false\n" - "\n" - "#system props for time-services\n" - "persist.timed.enable=true\n" - "\n" - "# System props for audio\n" - "persist.audio.fluence.mode=endfire\n" - "persist.audio.vr.enable=false\n" - "persist.audio.handset.mic=digital\n" - "persist.audio.lowlatency.rec=false\n" - "\n" - "# System prop to select audio resampler quality\n" - "af.resampler.quality=255\n" - "# System prop to select MPQAudioPlayer by default on mpq8064\n" - "mpq.audio.decode=true\n" - "\n" - "#\n" - "# system prop for opengles version\n" - "#\n" - "# 196608 is decimal for 0x30000 to report version 3\n" - "ro.opengles.version=196608\n" - "\n" - "# system prop for requesting Master role in incoming Bluetooth connection.\n" - "#\n" - "ro.bluetooth.request.master=true\n" - "#\n" - "# system prop for Bluetooth Auto connect for remote initated connections\n" - "#\n" - "ro.bluetooth.remote.autoconnect=true\n" - "# system property for Bluetooth discoverability time out in seconds\n" - "# 0: Always discoverable\n" - "#debug.bt.discoverable_time=0\n" - "\n" - "#system prop for switching gps driver to qmi\n" - "persist.gps.qmienabled=true\n" - "\n" - "#System prop to enable ehrpd capability\n" - "ro.config.ehrpd=true\n" - "\n" - "# System property for cabl\n" - "ro.qualcomm.cabl=0\n" - "\n" - "\n" - "# System prop for sending transmit power request to RIL during WiFi hotspot on/off\n" - "#\n" - "ro.ril.transmitpower=true\n" - "\n" - "\n" - "#Simulate sdcard on /data/media\n" - "#\n" - "persist.fuse_sdcard=true\n" - "ro.hwui.text_cache_width=2048\n" - "\n" - "#\n" - "# Supports warmboot capabilities\n" - "#\n" - "ro.warmboot.capability=1\n" - "\n" - "#\n" - "#snapdragon value add features\n" - "#\n" - "ro.qc.sdk.audio.ssr=false\n" - "##fluencetype can be \"fluence\" or \"fluencepro\" or \"none\"\n" - "ro.qc.sdk.audio.fluencetype=none\n" - "ro.qc.sdk.camera.facialproc=true\n" - "ro.qc.sdk.gestures.camera=false\n" - "ro.qc.sdk.sensors.gestures=false\n" - "#property to check if dynamic resolution change is supported in framework\n" - "ro.streaming.video.drs=true\n" - "#property to enable user to access Google WFD settings.\n" - "persist.debug.wfd.enable=1\n" - "#property to choose between virtual/external wfd display\n" - "persist.sys.wfd.virtual=0\n" - "\n" - "#system prop for setting rmnet mux mode\n" - "persist.rmnet.mux=disabled\n" - "\n" - "#\n" - "# System prop for Tvout/HDMI\n" - "#\n" - "persist.sys.camera.transform=0\n" - "persist.sys.camera.connect=0\n" - "persist.sys.videomode=0\n" - "ro.hdmi.enable=true\n" - "\n" - "\n" - "# System property for Default Brightness\n" - "ro.lcd_min_brightness=10\n" - "ro.lcd_brightness=143\n" - "\n" - "# System proverty for sys info indication\n" - "persist.radio.add_power_save=1\n" - "\n" - "# Keep SIM state on LPM mode\n" - "persist.radio.apm_sim_not_pwdn=1\n" - "\n" - "# use se table when search list\n" - "persist.radio.use_se_table_only=1\n" - "\n" - "# System prop for PLMN\n" - "persist.radio.fill_eons=1\n" - "\n" - "# System prop for SPN\n" - "persist.radio.prefer_spn=0\n" - "\n" - "media.enable-commonsource=true\n" - "\n" - "#\n" - "# ADDITIONAL_BUILD_PROPERTIES\n" - "#\n" - "dalvik.vm.heapstartsize=8m\n" - "dalvik.vm.heapgrowthlimit=128m\n" - "dalvik.vm.heapsize=512m\n" - "dalvik.vm.heaptargetutilization=0.75\n" - "dalvik.vm.heapminfree=2m\n" - "dalvik.vm.heapmaxfree=8m\n" - "keyguard.no_require_sim=true\n" - "ro.com.android.dateformat=MM-dd-yyyy\n" - "ro.carrier=unknown\n" - "ro.vendor.extension_library=/vendor/lib/libqc-opt.so\n" - "ro.build.scafe=americano\n" - "ro.build.scafe.size=short\n" - "ro.build.scafe.shot=single\n" - "ro.hdcp2.rx=tz\n" - "ro.secwvk=144\n" - "ro.securestorage.support=true\n" - "security.mdpp=None\n" - "ro.security.mdpp.ver=1.0\n" - "ro.security.mdpp.release=2\n" - "security.mdpp.result=None\n" - "ro.sec.fle.encryption=true\n" - "ro.hwui.texture_cache_size=48\n" - "ro.hwui.layer_cache_size=32\n" - "ro.hwui.path_cache_size=8\n" - "ro.hwui.shape_cache_size=2\n" - "ro.hwui.gradient_cache_size=1\n" - "ro.hwui.drop_shadow_cache_size=4\n" - "ro.hwui.texture_cache_flush_rate=0.5\n" - "ro.hwui.text_small_cache_width=1024\n" - "ro.hwui.text_small_cache_height=512\n" - "ro.hwui.text_large_cache_width=2048\n" - "ro.hwui.text_large_cache_height=1024\n" - "ro.error.receiver.default=com.samsung.receiver.error\n" - "ro.config.ringtone=ATT_Firefly_Default.ogg\n" - "ro.config.notification_sound=Whisper.ogg\n" - "ro.config.alarm_alert=Alarm_Morning_flower.ogg\n" - "ro.config.media_sound=Media_preview_Touch_the_light.ogg\n" - "ro.security.mdpp.ux=Enabled\n" - "ro.setupwizard.mode=OPTIONAL\n" - "ro.com.google.clientidbase=android-samsung\n" - "ro.com.google.clientidbase.ms=android-att-us\n" - "ro.com.google.clientidbase.am=android-att-us\n" - "ro.com.google.clientidbase.yt=android-samsung\n" - "ro.com.google.clientidbase.gmm=android-samsung\n" - "ro.com.google.gmsversion=4.4.2_r1\n" - "persist.sys.dalvik.vm.lib=libdvm.so\n" - "ro.kernel.qemu=0\n" - "ro.build.selinux=1\n" - "ro.config.knox=1\n" - "ro.config.tima=1\n" - "ro.config.timaversion=2.0\n" - "net.bt.name=Android\n" - "dalvik.vm.stack-trace-file=/data/anr/traces.txt\n" - "ro.qc.sdk.izat.premium_enabled=1\n" - "ro.qc.sdk.izat.service_mask=0x5\n" - "persist.gps.qc_nlp_in_use=0\n" - "ro.gps.agps_provider=1\n" - "\n", + .content = "# begin build properties\n" + "# autogenerated by buildinfo.sh\n" + "ro.build.id=KOT49H\n" + "ro.build.display.id=KOT49H.I337UCUFNC1\n" + "ro.build.version.incremental=I337UCUFNC1\n" + "ro.build.version.sdk=19\n" + "ro.build.version.codename=REL\n" + "ro.build.version.release=4.4.2\n" + "ro.build.date=Tue Mar 25 13:32:47 KST 2014\n" + "ro.build.date.utc=1395721967\n" + "ro.build.type=user\n" + "ro.build.user=dpi\n" + "ro.build.host=SWDD5916\n" + "ro.build.tags=release-keys\n" + "ro.product.model=SAMSUNG-SGH-I337\n" + "ro.product.brand=samsung\n" + "ro.product.name=jflteuc\n" + "ro.product.device=jflteatt\n" + "ro.product.board=MSM8960\n" + "ro.product.cpu.abi=armeabi-v7a\n" + "ro.product.cpu.abi2=armeabi\n" + "ro.product.manufacturer=samsung\n" + "ro.product.locale.language=en\n" + "ro.product.locale.region=US\n" + "ro.wifi.channels=\n" + "ro.board.platform=msm8960\n" + "# ro.build.product is obsolete; use ro.product.device\n" + "ro.build.product=jflteatt\n" + "# Do not try to parse ro.build.description or .fingerprint\n" + "ro.build.description=jflteuc-user 4.4.2 KOT49H I337UCUFNC1 release-keys\n" + "ro.build.fingerprint=samsung/jflteuc/jflteatt:4.4.2/KOT49H/I337UCUFNC1:user/release-keys\n" + "ro.build.characteristics=att\n" + "# Samsung Specific Properties\n" + "ro.build.PDA=I337UCUFNC1\n" + "ro.build.hidden_ver=I337UCUFNC1\n" + "ro.build.changelist=1125940\n" + "ro.product_ship=true\n" + "ro.chipname=apq8064\n" + "# end build properties\n" + "#\n" + "# from device/samsung/jflteatt/system.prop\n" + "#\n" + "#\n" + "# system.prop for surf\n" + "#\n" + "\n" + "ro.sf.lcd_density=480\n" + "\n" + "rild.libpath=/system/lib/libsec-ril.so\n" + "rild.libargs=-d /dev/smd0\n" + "persist.rild.nitz_plmn=\n" + "persist.rild.nitz_long_ons_0=\n" + "persist.rild.nitz_long_ons_1=\n" + "persist.rild.nitz_long_ons_2=\n" + "persist.rild.nitz_long_ons_3=\n" + "persist.rild.nitz_short_ons_0=\n" + "persist.rild.nitz_short_ons_1=\n" + "persist.rild.nitz_short_ons_2=\n" + "persist.rild.nitz_short_ons_3=\n" + "ril.subscription.types=NV,RUIM\n" + "DEVICE_PROVISIONED=1\n" + "debug.sf.hw=1\n" + "debug.egl.hw=1\n" + "debug.composition.type=gpu\n" + "dalvik.vm.heapsize=36m\n" + "debug.enable.wl_log=1\n" + "persist.hwc.mdpcomp.enable=true\n" + "debug.mdpcomp.logs=0\n" + "\n" + "#\n" + "# system props for the cne module\n" + "#\n" + "persist.cne.feature=0\n" + "\n" + "lpa.decode=false\n" + "tunnel.decode=true\n" + "tunnel.audiovideo.decode=false\n" + "lpa.use-stagefright=true\n" + "qcom.hw.aac.encoder=true\n" + "\n" + "#system props for the MM modules\n" + "\n" + "media.stagefright.enable-player=true\n" + "media.stagefright.enable-http=true\n" + "media.stagefright.enable-aac=true\n" + "media.stagefright.enable-qcp=true\n" + "media.stagefright.enable-fma2dp=true\n" + "media.stagefright.enable-scan=true\n" + "mmp.enable.3g2=true\n" + "media.aac_51_output_enabled=true\n" + "#33395 is sum of supported format flags in AAL\n" + "#Formats: AVI AC3 ASF AAC QCP DTS 3G2\n" + "mm.enable.qcom_parser=33395\n" + "\n" + "#\n" + "# system props for the data modules\n" + "#\n" + "ro.use_data_netmgrd=true\n" + "persist.data.netmgrd.qos.enable=false\n" + "\n" + "#system props for time-services\n" + "persist.timed.enable=true\n" + "\n" + "# System props for audio\n" + "persist.audio.fluence.mode=endfire\n" + "persist.audio.vr.enable=false\n" + "persist.audio.handset.mic=digital\n" + "persist.audio.lowlatency.rec=false\n" + "\n" + "# System prop to select audio resampler quality\n" + "af.resampler.quality=255\n" + "# System prop to select MPQAudioPlayer by default on mpq8064\n" + "mpq.audio.decode=true\n" + "\n" + "#\n" + "# system prop for opengles version\n" + "#\n" + "# 196608 is decimal for 0x30000 to report version 3\n" + "ro.opengles.version=196608\n" + "\n" + "# system prop for requesting Master role in incoming Bluetooth connection.\n" + "#\n" + "ro.bluetooth.request.master=true\n" + "#\n" + "# system prop for Bluetooth Auto connect for remote initated connections\n" + "#\n" + "ro.bluetooth.remote.autoconnect=true\n" + "# system property for Bluetooth discoverability time out in seconds\n" + "# 0: Always discoverable\n" + "#debug.bt.discoverable_time=0\n" + "\n" + "#system prop for switching gps driver to qmi\n" + "persist.gps.qmienabled=true\n" + "\n" + "#System prop to enable ehrpd capability\n" + "ro.config.ehrpd=true\n" + "\n" + "# System property for cabl\n" + "ro.qualcomm.cabl=0\n" + "\n" + "\n" + "# System prop for sending transmit power request to RIL during WiFi hotspot on/off\n" + "#\n" + "ro.ril.transmitpower=true\n" + "\n" + "\n" + "#Simulate sdcard on /data/media\n" + "#\n" + "persist.fuse_sdcard=true\n" + "ro.hwui.text_cache_width=2048\n" + "\n" + "#\n" + "# Supports warmboot capabilities\n" + "#\n" + "ro.warmboot.capability=1\n" + "\n" + "#\n" + "#snapdragon value add features\n" + "#\n" + "ro.qc.sdk.audio.ssr=false\n" + "##fluencetype can be \"fluence\" or \"fluencepro\" or \"none\"\n" + "ro.qc.sdk.audio.fluencetype=none\n" + "ro.qc.sdk.camera.facialproc=true\n" + "ro.qc.sdk.gestures.camera=false\n" + "ro.qc.sdk.sensors.gestures=false\n" + "#property to check if dynamic resolution change is supported in framework\n" + "ro.streaming.video.drs=true\n" + "#property to enable user to access Google WFD settings.\n" + "persist.debug.wfd.enable=1\n" + "#property to choose between virtual/external wfd display\n" + "persist.sys.wfd.virtual=0\n" + "\n" + "#system prop for setting rmnet mux mode\n" + "persist.rmnet.mux=disabled\n" + "\n" + "#\n" + "# System prop for Tvout/HDMI\n" + "#\n" + "persist.sys.camera.transform=0\n" + "persist.sys.camera.connect=0\n" + "persist.sys.videomode=0\n" + "ro.hdmi.enable=true\n" + "\n" + "\n" + "# System property for Default Brightness\n" + "ro.lcd_min_brightness=10\n" + "ro.lcd_brightness=143\n" + "\n" + "# System proverty for sys info indication\n" + "persist.radio.add_power_save=1\n" + "\n" + "# Keep SIM state on LPM mode\n" + "persist.radio.apm_sim_not_pwdn=1\n" + "\n" + "# use se table when search list\n" + "persist.radio.use_se_table_only=1\n" + "\n" + "# System prop for PLMN\n" + "persist.radio.fill_eons=1\n" + "\n" + "# System prop for SPN\n" + "persist.radio.prefer_spn=0\n" + "\n" + "media.enable-commonsource=true\n" + "\n" + "#\n" + "# ADDITIONAL_BUILD_PROPERTIES\n" + "#\n" + "dalvik.vm.heapstartsize=8m\n" + "dalvik.vm.heapgrowthlimit=128m\n" + "dalvik.vm.heapsize=512m\n" + "dalvik.vm.heaptargetutilization=0.75\n" + "dalvik.vm.heapminfree=2m\n" + "dalvik.vm.heapmaxfree=8m\n" + "keyguard.no_require_sim=true\n" + "ro.com.android.dateformat=MM-dd-yyyy\n" + "ro.carrier=unknown\n" + "ro.vendor.extension_library=/vendor/lib/libqc-opt.so\n" + "ro.build.scafe=americano\n" + "ro.build.scafe.size=short\n" + "ro.build.scafe.shot=single\n" + "ro.hdcp2.rx=tz\n" + "ro.secwvk=144\n" + "ro.securestorage.support=true\n" + "security.mdpp=None\n" + "ro.security.mdpp.ver=1.0\n" + "ro.security.mdpp.release=2\n" + "security.mdpp.result=None\n" + "ro.sec.fle.encryption=true\n" + "ro.hwui.texture_cache_size=48\n" + "ro.hwui.layer_cache_size=32\n" + "ro.hwui.path_cache_size=8\n" + "ro.hwui.shape_cache_size=2\n" + "ro.hwui.gradient_cache_size=1\n" + "ro.hwui.drop_shadow_cache_size=4\n" + "ro.hwui.texture_cache_flush_rate=0.5\n" + "ro.hwui.text_small_cache_width=1024\n" + "ro.hwui.text_small_cache_height=512\n" + "ro.hwui.text_large_cache_width=2048\n" + "ro.hwui.text_large_cache_height=1024\n" + "ro.error.receiver.default=com.samsung.receiver.error\n" + "ro.config.ringtone=ATT_Firefly_Default.ogg\n" + "ro.config.notification_sound=Whisper.ogg\n" + "ro.config.alarm_alert=Alarm_Morning_flower.ogg\n" + "ro.config.media_sound=Media_preview_Touch_the_light.ogg\n" + "ro.security.mdpp.ux=Enabled\n" + "ro.setupwizard.mode=OPTIONAL\n" + "ro.com.google.clientidbase=android-samsung\n" + "ro.com.google.clientidbase.ms=android-att-us\n" + "ro.com.google.clientidbase.am=android-att-us\n" + "ro.com.google.clientidbase.yt=android-samsung\n" + "ro.com.google.clientidbase.gmm=android-samsung\n" + "ro.com.google.gmsversion=4.4.2_r1\n" + "persist.sys.dalvik.vm.lib=libdvm.so\n" + "ro.kernel.qemu=0\n" + "ro.build.selinux=1\n" + "ro.config.knox=1\n" + "ro.config.tima=1\n" + "ro.config.timaversion=2.0\n" + "net.bt.name=Android\n" + "dalvik.vm.stack-trace-file=/data/anr/traces.txt\n" + "ro.qc.sdk.izat.premium_enabled=1\n" + "ro.qc.sdk.izat.service_mask=0x5\n" + "persist.gps.qc_nlp_in_use=0\n" + "ro.gps.agps_provider=1\n" + "\n", }, { .path = "/sys/devices/system/cpu/kernel_max", @@ -361,7 +359,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies", .size = 115, - .content = "384000 486000 594000 702000 810000 918000 1026000 1134000 1242000 1350000 1458000 1566000 1674000 1782000 1890000 \n", + .content = + "384000 486000 594000 702000 810000 918000 1026000 1134000 1242000 1350000 1458000 1566000 1674000 1782000 1890000 \n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors", @@ -391,22 +390,21 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 147, - .content = - "384000 0\n" - "486000 0\n" - "594000 0\n" - "702000 0\n" - "810000 0\n" - "918000 1\n" - "1026000 0\n" - "1134000 0\n" - "1242000 0\n" - "1350000 0\n" - "1458000 0\n" - "1566000 0\n" - "1674000 0\n" - "1782000 0\n" - "1890000 1125\n", + .content = "384000 0\n" + "486000 0\n" + "594000 0\n" + "702000 0\n" + "810000 0\n" + "918000 1\n" + "1026000 0\n" + "1134000 0\n" + "1242000 0\n" + "1350000 0\n" + "1458000 0\n" + "1566000 0\n" + "1674000 0\n" + "1782000 0\n" + "1890000 1125\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -471,7 +469,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_frequencies", .size = 115, - .content = "384000 486000 594000 702000 810000 918000 1026000 1134000 1242000 1350000 1458000 1566000 1674000 1782000 1890000 \n", + .content = + "384000 486000 594000 702000 810000 918000 1026000 1134000 1242000 1350000 1458000 1566000 1674000 1782000 1890000 \n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_governors", @@ -506,22 +505,21 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 147, - .content = - "384000 0\n" - "486000 0\n" - "594000 0\n" - "702000 0\n" - "810000 0\n" - "918000 0\n" - "1026000 0\n" - "1134000 0\n" - "1242000 0\n" - "1350000 0\n" - "1458000 0\n" - "1566000 0\n" - "1674000 0\n" - "1782000 0\n" - "1890000 1350\n", + .content = "384000 0\n" + "486000 0\n" + "594000 0\n" + "702000 0\n" + "810000 0\n" + "918000 0\n" + "1026000 0\n" + "1134000 0\n" + "1242000 0\n" + "1350000 0\n" + "1458000 0\n" + "1566000 0\n" + "1674000 0\n" + "1782000 0\n" + "1890000 1350\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -586,7 +584,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_frequencies", .size = 115, - .content = "384000 486000 594000 702000 810000 918000 1026000 1134000 1242000 1350000 1458000 1566000 1674000 1782000 1890000 \n", + .content = + "384000 486000 594000 702000 810000 918000 1026000 1134000 1242000 1350000 1458000 1566000 1674000 1782000 1890000 \n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_governors", @@ -621,22 +620,21 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 147, - .content = - "384000 0\n" - "486000 0\n" - "594000 0\n" - "702000 0\n" - "810000 0\n" - "918000 0\n" - "1026000 0\n" - "1134000 0\n" - "1242000 0\n" - "1350000 0\n" - "1458000 0\n" - "1566000 0\n" - "1674000 0\n" - "1782000 0\n" - "1890000 1588\n", + .content = "384000 0\n" + "486000 0\n" + "594000 0\n" + "702000 0\n" + "810000 0\n" + "918000 0\n" + "1026000 0\n" + "1134000 0\n" + "1242000 0\n" + "1350000 0\n" + "1458000 0\n" + "1566000 0\n" + "1674000 0\n" + "1782000 0\n" + "1890000 1588\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -701,7 +699,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_frequencies", .size = 115, - .content = "384000 486000 594000 702000 810000 918000 1026000 1134000 1242000 1350000 1458000 1566000 1674000 1782000 1890000 \n", + .content = + "384000 486000 594000 702000 810000 918000 1026000 1134000 1242000 1350000 1458000 1566000 1674000 1782000 1890000 \n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_governors", @@ -736,22 +735,21 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 147, - .content = - "384000 0\n" - "486000 0\n" - "594000 0\n" - "702000 0\n" - "810000 0\n" - "918000 0\n" - "1026000 0\n" - "1134000 0\n" - "1242000 0\n" - "1350000 0\n" - "1458000 0\n" - "1566000 0\n" - "1674000 0\n" - "1782000 0\n" - "1890000 1828\n", + .content = "384000 0\n" + "486000 0\n" + "594000 0\n" + "702000 0\n" + "810000 0\n" + "918000 0\n" + "1026000 0\n" + "1134000 0\n" + "1242000 0\n" + "1350000 0\n" + "1458000 0\n" + "1566000 0\n" + "1674000 0\n" + "1782000 0\n" + "1890000 1828\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -788,7 +786,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "8\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ @@ -2081,6 +2079,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wifi.interface", .value = "wlan0", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/galaxy-s5-global.cc b/test/mock/galaxy-s5-global.cc index 147ae2c1..e66f03b1 100644 --- a/test/mock/galaxy-s5-global.cc +++ b/test/mock/galaxy-s5-global.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(8, cpuinfo_get_processors_count()); @@ -334,8 +333,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Samsung Exynos 5422", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Samsung Exynos 5422", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -526,8 +527,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -604,8 +607,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -670,8 +675,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/galaxy-s5-global.h b/test/mock/galaxy-s5-global.h index b8a71d39..61afa435 100644 --- a/test/mock/galaxy-s5-global.h +++ b/test/mock/galaxy-s5-global.h @@ -2,236 +2,234 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 2052, - .content = - "processor\t: 0\n" - "model name\t: ARMv7 Processor rev 3 (v7l)\n" - "BogoMIPS\t: 2585.19\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xc07\n" - "CPU revision\t: 3\n" - "\n" - "processor\t: 1\n" - "model name\t: ARMv7 Processor rev 3 (v7l)\n" - "BogoMIPS\t: 2585.19\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xc07\n" - "CPU revision\t: 3\n" - "\n" - "processor\t: 2\n" - "model name\t: ARMv7 Processor rev 3 (v7l)\n" - "BogoMIPS\t: 2585.19\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xc07\n" - "CPU revision\t: 3\n" - "\n" - "processor\t: 3\n" - "model name\t: ARMv7 Processor rev 3 (v7l)\n" - "BogoMIPS\t: 2585.19\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xc07\n" - "CPU revision\t: 3\n" - "\n" - "processor\t: 4\n" - "model name\t: ARMv7 Processor rev 3 (v7l)\n" - "BogoMIPS\t: 3380.63\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x2\n" - "CPU part\t: 0xc0f\n" - "CPU revision\t: 3\n" - "\n" - "processor\t: 5\n" - "model name\t: ARMv7 Processor rev 3 (v7l)\n" - "BogoMIPS\t: 3380.63\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x2\n" - "CPU part\t: 0xc0f\n" - "CPU revision\t: 3\n" - "\n" - "processor\t: 6\n" - "model name\t: ARMv7 Processor rev 3 (v7l)\n" - "BogoMIPS\t: 3380.63\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x2\n" - "CPU part\t: 0xc0f\n" - "CPU revision\t: 3\n" - "\n" - "processor\t: 7\n" - "model name\t: ARMv7 Processor rev 3 (v7l)\n" - "BogoMIPS\t: 3380.63\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x2\n" - "CPU part\t: 0xc0f\n" - "CPU revision\t: 3\n" - "\n" - "Hardware\t: universal5422\n" - "Revision\t: 000a\n" - "Serial\t\t: 6b31294e2318004d\n", + .content = "processor\t: 0\n" + "model name\t: ARMv7 Processor rev 3 (v7l)\n" + "BogoMIPS\t: 2585.19\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xc07\n" + "CPU revision\t: 3\n" + "\n" + "processor\t: 1\n" + "model name\t: ARMv7 Processor rev 3 (v7l)\n" + "BogoMIPS\t: 2585.19\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xc07\n" + "CPU revision\t: 3\n" + "\n" + "processor\t: 2\n" + "model name\t: ARMv7 Processor rev 3 (v7l)\n" + "BogoMIPS\t: 2585.19\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xc07\n" + "CPU revision\t: 3\n" + "\n" + "processor\t: 3\n" + "model name\t: ARMv7 Processor rev 3 (v7l)\n" + "BogoMIPS\t: 2585.19\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xc07\n" + "CPU revision\t: 3\n" + "\n" + "processor\t: 4\n" + "model name\t: ARMv7 Processor rev 3 (v7l)\n" + "BogoMIPS\t: 3380.63\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x2\n" + "CPU part\t: 0xc0f\n" + "CPU revision\t: 3\n" + "\n" + "processor\t: 5\n" + "model name\t: ARMv7 Processor rev 3 (v7l)\n" + "BogoMIPS\t: 3380.63\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x2\n" + "CPU part\t: 0xc0f\n" + "CPU revision\t: 3\n" + "\n" + "processor\t: 6\n" + "model name\t: ARMv7 Processor rev 3 (v7l)\n" + "BogoMIPS\t: 3380.63\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x2\n" + "CPU part\t: 0xc0f\n" + "CPU revision\t: 3\n" + "\n" + "processor\t: 7\n" + "model name\t: ARMv7 Processor rev 3 (v7l)\n" + "BogoMIPS\t: 3380.63\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x2\n" + "CPU part\t: 0xc0f\n" + "CPU revision\t: 3\n" + "\n" + "Hardware\t: universal5422\n" + "Revision\t: 000a\n" + "Serial\t\t: 6b31294e2318004d\n", }, { .path = "/system/build.prop", .size = 3804, - .content = - "\n" - "# begin build properties\n" - "# autogenerated by buildinfo.sh\n" - "ro.build.id=LRX21T\n" - "ro.build.display.id=LRX21T.G900HXXU1BOE2\n" - "ro.build.version.incremental=G900HXXU1BOE2\n" - "ro.build.version.sdk=21\n" - "ro.build.version.codename=REL\n" - "ro.build.version.all_codenames=REL\n" - "ro.build.version.release=5.0\n" - "ro.build.date=Thu May 21 11:03:12 KST 2015\n" - "ro.build.date.utc=1432173792\n" - "ro.build.type=user\n" - "ro.build.user=dpi\n" - "ro.build.host=SWDD6017\n" - "ro.build.tags=release-keys\n" - "ro.product.model=SM-G900H\n" - "ro.product.brand=samsung\n" - "ro.product.name=k3gxx\n" - "ro.product.device=k3g\n" - "ro.product.board=universal5422\n" - "# ro.product.cpu.abi and ro.product.cpu.abi2 are obsolete,\n" - "# use ro.product.cpu.abilist instead.\n" - "ro.product.cpu.abi=armeabi-v7a\n" - "ro.product.cpu.abi2=armeabi\n" - "ro.product.cpu.abilist=armeabi-v7a,armeabi\n" - "ro.product.cpu.abilist32=armeabi-v7a,armeabi\n" - "ro.product.cpu.abilist64=\n" - "ro.product.manufacturer=samsung\n" - "ro.product.locale.language=en\n" - "ro.product.locale.region=GB\n" - "ro.wifi.channels=\n" - "ro.board.platform=exynos5\n" - "# ro.build.product is obsolete; use ro.product.device\n" - "ro.build.product=k3g\n" - "# Do not try to parse description, fingerprint, or thumbprint\n" - "ro.build.description=k3gxx-user 5.0 LRX21T G900HXXU1BOE2 release-keys\n" - "ro.build.fingerprint=samsung/k3gxx/k3g:5.0/LRX21T/G900HXXU1BOE2:user/release-keys\n" - "ro.build.characteristics=phone\n" - "# Samsung Specific Properties\n" - "ro.build.PDA=G900HXXU1BOE2\n" - "ro.build.hidden_ver=G900HXXU1BOE2\n" - "ro.config.rm_preload_enabled=0\n" - "ro.build.changelist=4521975\n" - "ro.product_ship=true\n" - "ro.chipname=exynos5422\n" - "persist.sys.storage_preload=1\n" - "# end build properties\n" - "#\n" - "# from device/samsung/k3g/system.prop\n" - "#\n" - "\n" - "rild.libpath=/system/lib/libsec-ril.so\n" - "rild.libargs=-d /dev/ttyS0\n" - "\n" - "#\n" - "# system.prop for universal5422\n" - "#\n" - "\n" - "ro.arch=exynos5422\n" - "persist.hdmi.hdcp_enabled=1\n" - "\n" - "\n" - "# LCD Density\n" - "ro.sf.lcd_density=480\n" - "\n" - "\n" - "\n" - "# Multimedia property for Smart View\n" - "media.enable-commonsource=true\n" - "\n" - "\n" - "# VQG - User Agent Header for Video-Streaming Client\n" - "net.streaming.rtsp.uaprof=http://wap.samsungmobile.com/uaprof/\n" - "#\n" - "# ADDITIONAL_BUILD_PROPERTIES\n" - "#\n" - "ro.hwui.texture_cache_size=50\n" - "ro.hwui.layer_cache_size=34\n" - "ro.hwui.path_cache_size=10\n" - "ro.hwui.shape_cache_size=4\n" - "ro.hwui.gradient_cache_size=2\n" - "ro.hwui.drop_shadow_cache_size=6\n" - "ro.hwui.text_small_cache_width=2048\n" - "ro.hwui.text_small_cache_height=2048\n" - "ro.hwui.text_large_cache_width=4096\n" - "ro.hwui.text_large_cache_height=4096\n" - "ro.config.tima=1\n" - "ro.config.timaversion=3.0\n" - "ro.opengles.version=196608\n" - "ro.sf.lcd_density=320\n" - "drm.service.enabled=true\n" - "ro.hdcp2.rx=tz\n" - "ro.secwvk=220\n" - "ro.securestorage.support=true\n" - "dalvik.vm.heapstartsize=8m\n" - "dalvik.vm.heapgrowthlimit=128m\n" - "dalvik.vm.heapsize=512m\n" - "dalvik.vm.heaptargetutilization=0.75\n" - "dalvik.vm.heapminfree=2m\n" - "dalvik.vm.heapmaxfree=8m\n" - "ro.build.scafe=americano\n" - "ro.build.scafe.size=short\n" - "ro.build.scafe.shot=single\n" - "ro.build.scafe.cream=white\n" - "ro.sec.fle.encryption=true\n" - "security.mdpp=None\n" - "ro.security.mdpp.ver=1.1\n" - "ro.security.mdpp.release=4\n" - "ro.security.vpnpp.ver=1.4\n" - "ro.security.vpnpp.release=3\n" - "security.mdpp.result=None\n" - "ro.security.mdpp.ux=Enabled\n" - "ro.security.reactive.triggered=false\n" - "ro.error.receiver.default=com.samsung.receiver.error\n" - "ro.config.ringtone=Over_the_horizon.ogg\n" - "ro.config.notification_sound=S_Whistle.ogg\n" - "ro.config.alarm_alert=Morning_flower.ogg\n" - "ro.config.media_sound=Media_preview_Touch_the_light.ogg\n" - "ro.security.reactive.active=1\n" - "keyguard.no_require_sim=true\n" - "ro.com.android.dateformat=MM-dd-yyyy\n" - "ro.carrier=unknown\n" - "ro.com.google.clientidbase=android-samsung\n" - "ro.security.icd.flagmode=single\n" - "ro.ril.hsxpa=1\n" - "ro.ril.gprsclass=10\n" - "ro.adb.qemud=1\n" - "ro.smps.enable=true\n" - "ro.setupwizard.mode=DISABLED\n" - "ro.com.google.gmsversion=5.0_r2\n" - "persist.sys.dalvik.vm.lib.2=libart.so\n" - "ro.build.selinux=1\n" - "dalvik.vm.isa.arm.features=div\n" - "ro.config.knox=v30\n" - "ro.kernel.qemu=0\n" - "dalvik.vm.dexopt-flags=m=y\n" - "net.bt.name=Android\n" - "dalvik.vm.stack-trace-file=/data/anr/traces.txt\n" - "ro.build.version.sdl=2101\n" - "\n", + .content = "\n" + "# begin build properties\n" + "# autogenerated by buildinfo.sh\n" + "ro.build.id=LRX21T\n" + "ro.build.display.id=LRX21T.G900HXXU1BOE2\n" + "ro.build.version.incremental=G900HXXU1BOE2\n" + "ro.build.version.sdk=21\n" + "ro.build.version.codename=REL\n" + "ro.build.version.all_codenames=REL\n" + "ro.build.version.release=5.0\n" + "ro.build.date=Thu May 21 11:03:12 KST 2015\n" + "ro.build.date.utc=1432173792\n" + "ro.build.type=user\n" + "ro.build.user=dpi\n" + "ro.build.host=SWDD6017\n" + "ro.build.tags=release-keys\n" + "ro.product.model=SM-G900H\n" + "ro.product.brand=samsung\n" + "ro.product.name=k3gxx\n" + "ro.product.device=k3g\n" + "ro.product.board=universal5422\n" + "# ro.product.cpu.abi and ro.product.cpu.abi2 are obsolete,\n" + "# use ro.product.cpu.abilist instead.\n" + "ro.product.cpu.abi=armeabi-v7a\n" + "ro.product.cpu.abi2=armeabi\n" + "ro.product.cpu.abilist=armeabi-v7a,armeabi\n" + "ro.product.cpu.abilist32=armeabi-v7a,armeabi\n" + "ro.product.cpu.abilist64=\n" + "ro.product.manufacturer=samsung\n" + "ro.product.locale.language=en\n" + "ro.product.locale.region=GB\n" + "ro.wifi.channels=\n" + "ro.board.platform=exynos5\n" + "# ro.build.product is obsolete; use ro.product.device\n" + "ro.build.product=k3g\n" + "# Do not try to parse description, fingerprint, or thumbprint\n" + "ro.build.description=k3gxx-user 5.0 LRX21T G900HXXU1BOE2 release-keys\n" + "ro.build.fingerprint=samsung/k3gxx/k3g:5.0/LRX21T/G900HXXU1BOE2:user/release-keys\n" + "ro.build.characteristics=phone\n" + "# Samsung Specific Properties\n" + "ro.build.PDA=G900HXXU1BOE2\n" + "ro.build.hidden_ver=G900HXXU1BOE2\n" + "ro.config.rm_preload_enabled=0\n" + "ro.build.changelist=4521975\n" + "ro.product_ship=true\n" + "ro.chipname=exynos5422\n" + "persist.sys.storage_preload=1\n" + "# end build properties\n" + "#\n" + "# from device/samsung/k3g/system.prop\n" + "#\n" + "\n" + "rild.libpath=/system/lib/libsec-ril.so\n" + "rild.libargs=-d /dev/ttyS0\n" + "\n" + "#\n" + "# system.prop for universal5422\n" + "#\n" + "\n" + "ro.arch=exynos5422\n" + "persist.hdmi.hdcp_enabled=1\n" + "\n" + "\n" + "# LCD Density\n" + "ro.sf.lcd_density=480\n" + "\n" + "\n" + "\n" + "# Multimedia property for Smart View\n" + "media.enable-commonsource=true\n" + "\n" + "\n" + "# VQG - User Agent Header for Video-Streaming Client\n" + "net.streaming.rtsp.uaprof=http://wap.samsungmobile.com/uaprof/\n" + "#\n" + "# ADDITIONAL_BUILD_PROPERTIES\n" + "#\n" + "ro.hwui.texture_cache_size=50\n" + "ro.hwui.layer_cache_size=34\n" + "ro.hwui.path_cache_size=10\n" + "ro.hwui.shape_cache_size=4\n" + "ro.hwui.gradient_cache_size=2\n" + "ro.hwui.drop_shadow_cache_size=6\n" + "ro.hwui.text_small_cache_width=2048\n" + "ro.hwui.text_small_cache_height=2048\n" + "ro.hwui.text_large_cache_width=4096\n" + "ro.hwui.text_large_cache_height=4096\n" + "ro.config.tima=1\n" + "ro.config.timaversion=3.0\n" + "ro.opengles.version=196608\n" + "ro.sf.lcd_density=320\n" + "drm.service.enabled=true\n" + "ro.hdcp2.rx=tz\n" + "ro.secwvk=220\n" + "ro.securestorage.support=true\n" + "dalvik.vm.heapstartsize=8m\n" + "dalvik.vm.heapgrowthlimit=128m\n" + "dalvik.vm.heapsize=512m\n" + "dalvik.vm.heaptargetutilization=0.75\n" + "dalvik.vm.heapminfree=2m\n" + "dalvik.vm.heapmaxfree=8m\n" + "ro.build.scafe=americano\n" + "ro.build.scafe.size=short\n" + "ro.build.scafe.shot=single\n" + "ro.build.scafe.cream=white\n" + "ro.sec.fle.encryption=true\n" + "security.mdpp=None\n" + "ro.security.mdpp.ver=1.1\n" + "ro.security.mdpp.release=4\n" + "ro.security.vpnpp.ver=1.4\n" + "ro.security.vpnpp.release=3\n" + "security.mdpp.result=None\n" + "ro.security.mdpp.ux=Enabled\n" + "ro.security.reactive.triggered=false\n" + "ro.error.receiver.default=com.samsung.receiver.error\n" + "ro.config.ringtone=Over_the_horizon.ogg\n" + "ro.config.notification_sound=S_Whistle.ogg\n" + "ro.config.alarm_alert=Morning_flower.ogg\n" + "ro.config.media_sound=Media_preview_Touch_the_light.ogg\n" + "ro.security.reactive.active=1\n" + "keyguard.no_require_sim=true\n" + "ro.com.android.dateformat=MM-dd-yyyy\n" + "ro.carrier=unknown\n" + "ro.com.google.clientidbase=android-samsung\n" + "ro.security.icd.flagmode=single\n" + "ro.ril.hsxpa=1\n" + "ro.ril.gprsclass=10\n" + "ro.adb.qemud=1\n" + "ro.smps.enable=true\n" + "ro.setupwizard.mode=DISABLED\n" + "ro.com.google.gmsversion=5.0_r2\n" + "persist.sys.dalvik.vm.lib.2=libart.so\n" + "ro.build.selinux=1\n" + "dalvik.vm.isa.arm.features=div\n" + "ro.config.knox=v30\n" + "ro.kernel.qemu=0\n" + "dalvik.vm.dexopt-flags=m=y\n" + "net.bt.name=Android\n" + "dalvik.vm.stack-trace-file=/data/anr/traces.txt\n" + "ro.build.version.sdl=2101\n" + "\n", }, { .path = "/sys/devices/system/cpu/kernel_max", @@ -261,23 +259,22 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpufreq/all_time_in_state", .size = 664, - .content = - "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\t\n" - "500000\t\t0\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "600000\t\t0\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "700000\t\t0\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "800000\t\t17\t\t17\t\t17\t\t17\t\t33\t\t33\t\t33\t\t33\t\t\n" - "900000\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t\n" - "1000000\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t\n" - "1100000\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t\n" - "1200000\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t\n" - "1300000\t\t1838\t\t1838\t\t1838\t\t1838\t\t0\t\t0\t\t0\t\t0\t\t\n" - "1400000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\t0\t\t0\t\t0\t\t\n" - "1500000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\t0\t\t0\t\t0\t\t\n" - "1600000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\t0\t\t0\t\t0\t\t\n" - "1700000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t1822\t\t1822\t\t1822\t\t1822\t\t\n" - "1800000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\t0\t\t0\t\t0\t\t\n" - "1900000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\t0\t\t0\t\t0\t\t\n", + .content = "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\t\n" + "500000\t\t0\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "600000\t\t0\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "700000\t\t0\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "800000\t\t17\t\t17\t\t17\t\t17\t\t33\t\t33\t\t33\t\t33\t\t\n" + "900000\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t\n" + "1000000\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t\n" + "1100000\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t\n" + "1200000\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t0\t\t\n" + "1300000\t\t1838\t\t1838\t\t1838\t\t1838\t\t0\t\t0\t\t0\t\t0\t\t\n" + "1400000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\t0\t\t0\t\t0\t\t\n" + "1500000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\t0\t\t0\t\t0\t\t\n" + "1600000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\t0\t\t0\t\t0\t\t\n" + "1700000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t1822\t\t1822\t\t1822\t\t1822\t\t\n" + "1800000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\t0\t\t0\t\t0\t\t\n" + "1900000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\t0\t\t0\t\t0\t\t\n", }, { .path = "/sys/devices/system/cpu/cpuidle/current_driver", @@ -302,15 +299,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/b.L/core_status", .size = 80, - .content = - "cpu 0 : 1\n" - "cpu 1 : 1\n" - "cpu 2 : 1\n" - "cpu 3 : 1\n" - "cpu 4 : 1\n" - "cpu 5 : 1\n" - "cpu 6 : 1\n" - "cpu 7 : 1\n", + .content = "cpu 0 : 1\n" + "cpu 1 : 1\n" + "cpu 2 : 1\n" + "cpu 3 : 1\n" + "cpu 4 : 1\n" + "cpu 5 : 1\n" + "cpu 6 : 1\n" + "cpu 7 : 1\n", }, { .path = "/sys/devices/system/b.L/little_threads", @@ -380,16 +376,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 89, - .content = - "1300000 1911\n" - "1200000 0\n" - "1100000 0\n" - "1000000 0\n" - "900000 0\n" - "800000 17\n" - "700000 0\n" - "600000 0\n" - "500000 0\n", + .content = "1300000 1911\n" + "1200000 0\n" + "1100000 0\n" + "1000000 0\n" + "900000 0\n" + "800000 17\n" + "700000 0\n" + "600000 0\n" + "500000 0\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -479,16 +474,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 89, - .content = - "1300000 2141\n" - "1200000 0\n" - "1100000 0\n" - "1000000 0\n" - "900000 0\n" - "800000 17\n" - "700000 0\n" - "600000 0\n" - "500000 0\n", + .content = "1300000 2141\n" + "1200000 0\n" + "1100000 0\n" + "1000000 0\n" + "900000 0\n" + "800000 17\n" + "700000 0\n" + "600000 0\n" + "500000 0\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -578,16 +572,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 89, - .content = - "1300000 2381\n" - "1200000 0\n" - "1100000 0\n" - "1000000 0\n" - "900000 0\n" - "800000 17\n" - "700000 0\n" - "600000 0\n" - "500000 0\n", + .content = "1300000 2381\n" + "1200000 0\n" + "1100000 0\n" + "1000000 0\n" + "900000 0\n" + "800000 17\n" + "700000 0\n" + "600000 0\n" + "500000 0\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -677,16 +670,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 89, - .content = - "1300000 2621\n" - "1200000 0\n" - "1100000 0\n" - "1000000 0\n" - "900000 0\n" - "800000 17\n" - "700000 0\n" - "600000 0\n" - "500000 0\n", + .content = "1300000 2621\n" + "1200000 0\n" + "1100000 0\n" + "1000000 0\n" + "900000 0\n" + "800000 17\n" + "700000 0\n" + "600000 0\n" + "500000 0\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -776,19 +768,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/time_in_state", .size = 122, - .content = - "1900000 0\n" - "1800000 0\n" - "1700000 2849\n" - "1600000 0\n" - "1500000 0\n" - "1400000 0\n" - "1300000 0\n" - "1200000 0\n" - "1100000 0\n" - "1000000 0\n" - "900000 0\n" - "800000 33\n", + .content = "1900000 0\n" + "1800000 0\n" + "1700000 2849\n" + "1600000 0\n" + "1500000 0\n" + "1400000 0\n" + "1300000 0\n" + "1200000 0\n" + "1100000 0\n" + "1000000 0\n" + "900000 0\n" + "800000 33\n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/total_trans", @@ -878,19 +869,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/time_in_state", .size = 122, - .content = - "1900000 0\n" - "1800000 0\n" - "1700000 3103\n" - "1600000 0\n" - "1500000 0\n" - "1400000 0\n" - "1300000 0\n" - "1200000 0\n" - "1100000 0\n" - "1000000 0\n" - "900000 0\n" - "800000 33\n", + .content = "1900000 0\n" + "1800000 0\n" + "1700000 3103\n" + "1600000 0\n" + "1500000 0\n" + "1400000 0\n" + "1300000 0\n" + "1200000 0\n" + "1100000 0\n" + "1000000 0\n" + "900000 0\n" + "800000 33\n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/total_trans", @@ -980,19 +970,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/time_in_state", .size = 122, - .content = - "1900000 0\n" - "1800000 0\n" - "1700000 3352\n" - "1600000 0\n" - "1500000 0\n" - "1400000 0\n" - "1300000 0\n" - "1200000 0\n" - "1100000 0\n" - "1000000 0\n" - "900000 0\n" - "800000 33\n", + .content = "1900000 0\n" + "1800000 0\n" + "1700000 3352\n" + "1600000 0\n" + "1500000 0\n" + "1400000 0\n" + "1300000 0\n" + "1200000 0\n" + "1100000 0\n" + "1000000 0\n" + "900000 0\n" + "800000 33\n", }, { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/total_trans", @@ -1082,19 +1071,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/time_in_state", .size = 122, - .content = - "1900000 0\n" - "1800000 0\n" - "1700000 3714\n" - "1600000 0\n" - "1500000 0\n" - "1400000 0\n" - "1300000 0\n" - "1200000 0\n" - "1100000 0\n" - "1000000 0\n" - "900000 0\n" - "800000 33\n", + .content = "1900000 0\n" + "1800000 0\n" + "1700000 3714\n" + "1600000 0\n" + "1500000 0\n" + "1400000 0\n" + "1300000 0\n" + "1200000 0\n" + "1100000 0\n" + "1000000 0\n" + "900000 0\n" + "800000 33\n", }, { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/total_trans", @@ -1131,7 +1119,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 3, .content = "80\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ @@ -2380,6 +2368,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.wfd.status", .value = "disconnected", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/galaxy-s5-us.cc b/test/mock/galaxy-s5-us.cc index 8b00abf6..e9d80fc5 100644 --- a/test/mock/galaxy-s5-us.cc +++ b/test/mock/galaxy-s5-us.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(4, cpuinfo_get_processors_count()); @@ -208,8 +207,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Qualcomm MSM8974PRO-AC", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Qualcomm MSM8974PRO-AC", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -400,8 +401,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -452,8 +455,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -492,9 +497,7 @@ TEST(L2, non_null) { TEST(L2, size) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - switch (i) { - ASSERT_EQ(2 * 1024 * 1024, cpuinfo_get_l2_cache(i)->size); - } + switch (i) { ASSERT_EQ(2 * 1024 * 1024, cpuinfo_get_l2_cache(i)->size); } } } @@ -506,8 +509,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/galaxy-s5-us.h b/test/mock/galaxy-s5-us.h index f9275510..e05d9e6c 100644 --- a/test/mock/galaxy-s5-us.h +++ b/test/mock/galaxy-s5-us.h @@ -2,308 +2,306 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 419, - .content = - "Processor\t: ARMv7 Processor rev 1 (v7l)\n" - "processor\t: 0\n" - "BogoMIPS\t: 38.40\n" - "\n" - "processor\t: 1\n" - "BogoMIPS\t: 38.40\n" - "\n" - "processor\t: 2\n" - "BogoMIPS\t: 38.40\n" - "\n" - "processor\t: 3\n" - "BogoMIPS\t: 38.40\n" - "\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x2\n" - "CPU part\t: 0x06f\n" - "CPU revision\t: 1\n" - "\n" - "Hardware\t: Qualcomm MSM8974PRO-AC\n" - "Revision\t: 000e\n" - "Serial\t\t: 0000cec2000097e3\n", + .content = "Processor\t: ARMv7 Processor rev 1 (v7l)\n" + "processor\t: 0\n" + "BogoMIPS\t: 38.40\n" + "\n" + "processor\t: 1\n" + "BogoMIPS\t: 38.40\n" + "\n" + "processor\t: 2\n" + "BogoMIPS\t: 38.40\n" + "\n" + "processor\t: 3\n" + "BogoMIPS\t: 38.40\n" + "\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x2\n" + "CPU part\t: 0x06f\n" + "CPU revision\t: 1\n" + "\n" + "Hardware\t: Qualcomm MSM8974PRO-AC\n" + "Revision\t: 000e\n" + "Serial\t\t: 0000cec2000097e3\n", }, { .path = "/system/build.prop", .size = 7266, - .content = - "\n" - "# begin build properties\n" - "# autogenerated by buildinfo.sh\n" - "ro.build.id=LMY47X\n" - "ro.build.display.id=LMY47X.G900AUCU4CPA1\n" - "ro.build.version.incremental=G900AUCU4CPA1\n" - "ro.build.version.sdk=22\n" - "ro.build.version.codename=REL\n" - "ro.build.version.all_codenames=REL\n" - "ro.build.version.release=5.1.1\n" - "ro.build.version.security_patch=2016-02-01\n" - "ro.build.version.base_os=\n" - "ro.build.date=Wed Jan 27 21:23:36 KST 2016\n" - "ro.build.date.utc=1453897416\n" - "ro.build.type=user\n" - "ro.build.user=dpi\n" - "ro.build.host=SWHC3812\n" - "ro.build.tags=release-keys\n" - "ro.build.flavor=klteuc-user\n" - "ro.product.model=SAMSUNG-SM-G900A\n" - "ro.product.brand=samsung\n" - "ro.product.name=klteuc\n" - "ro.product.device=klteatt\n" - "ro.product.board=MSM8974\n" - "# ro.product.cpu.abi and ro.product.cpu.abi2 are obsolete,\n" - "# use ro.product.cpu.abilist instead.\n" - "ro.product.cpu.abi=armeabi-v7a\n" - "ro.product.cpu.abi2=armeabi\n" - "ro.product.cpu.abilist=armeabi-v7a,armeabi\n" - "ro.product.cpu.abilist32=armeabi-v7a,armeabi\n" - "ro.product.cpu.abilist64=\n" - "ro.product.manufacturer=samsung\n" - "ro.product.locale.language=en\n" - "ro.product.locale.region=US\n" - "ro.wifi.channels=\n" - "ro.board.platform=msm8974\n" - "# ro.build.product is obsolete; use ro.product.device\n" - "ro.build.product=klteatt\n" - "# Do not try to parse description, fingerprint, or thumbprint\n" - "ro.build.description=klteuc-user 5.1.1 LMY47X G900AUCU4CPA1 release-keys\n" - "ro.build.fingerprint=samsung/klteuc/klteatt:5.1.1/LMY47X/G900AUCU4CPA1:user/release-keys\n" - "ro.build.characteristics=att\n" - "# Samsung Specific Properties\n" - "ro.build.PDA=G900AUCU4CPA1\n" - "ro.build.hidden_ver=G900AUCU4CPA1\n" - "ro.config.rm_preload_enabled=0\n" - "ro.build.changelist=5869384\n" - "ro.product_ship=true\n" - "ro.chipname=MSM8974PRO\n" - "persist.sys.storage_preload=1\n" - "# end build properties\n" - "\n" - "#\n" - "# HWUI_BUILD_PROPERTIES\n" - "#\n" - "ro.hwui.texture_cache_size=50\n" - "ro.hwui.layer_cache_size=34\n" - "ro.hwui.path_cache_size=10\n" - "ro.hwui.shape_cache_size=4\n" - "ro.hwui.gradient_cache_size=2\n" - "ro.hwui.drop_shadow_cache_size=6\n" - "ro.hwui.r_buffer_cache_size=4\n" - "ro.hwui.text_small_cache_width=2048\n" - "ro.hwui.text_small_cache_height=2048\n" - "ro.hwui.text_large_cache_width=4096\n" - "ro.hwui.text_large_cache_height=4096\n" - "ro.hwui.fbo_cache_size=16\n" - "#\n" - "# from device/samsung/klteatt/system.prop\n" - "#\n" - "#\n" - "# system.prop for msm8974\n" - "#\n" - "\n" - "# LCD Density\n" - "ro.sf.lcd_density=480\n" - "\n" - "# Evolution RIL (8xxx)\n" - "rild.libpath=/system/lib/libsec-ril.so\n" - "rild.libargs=-d /dev/smd0\n" - "ril.subscription.types=NV,RUIM\n" - "DEVICE_PROVISIONED=1\n" - "\n" - "debug.sf.hw=1\n" - "debug.egl.hw=1\n" - "debug.composition.type=c2d\n" - "persist.hwc.mdpcomp.enable=true\n" - "debug.mdpcomp.logs=0\n" - "dalvik.vm.heapsize=36m\n" - "dev.pm.dyn_samplingrate=1\n" - "persist.demo.hdmirotationlock=false\n" - "\n" - "ro.hdmi.enable=true\n" - "persist.speaker.prot.enable=false\n" - "qcom.hw.aac.encoder=true\n" - "#\n" - "# system props for the cne module\n" - "#\n" - "#persist.cne.feature=1\n" - "\n" - "#system props for the MM modules\n" - "media.stagefright.enable-player=true\n" - "media.stagefright.enable-http=true\n" - "media.stagefright.enable-aac=true\n" - "media.stagefright.enable-qcp=true\n" - "media.stagefright.enable-fma2dp=true\n" - "media.stagefright.enable-scan=true\n" - "mmp.enable.3g2=true\n" - "mm.enable.smoothstreaming=true\n" - "media.aac_51_output_enabled=true\n" - "#37491 is decimal sum of supported codecs in AAL\n" - "#codecs: AVI AC3 ASF AAC QCP DTS 3G2 MP2TS\n" - "mm.enable.qcom_parser=37491\n" - "\n" - "# VIDC: debug_levels\n" - "# 1:ERROR 2:HIGH 4:LOW 0:NOLOGS 7:AllLOGS\n" - "vidc.debug.level=1\n" - "#\n" - "ro.data.large_tcp_window_size=true\n" - "\n" - "# system prop for opengles version\n" - "#\n" - "# 196608 is decimal for 0x30000 to report version 3\n" - "ro.opengles.version=196608\n" - "\n" - "# System property for cabl\n" - "ro.qualcomm.cabl=1\n" - "\n" - "#\n" - "# System props for bluetooth\n" - "# System prop to turn on hfp client\n" - "bluetooth.hfp.client=1\n" - "\n" - "#\n" - "# System props for bluetooth LE Always on feature\n" - "#\n" - "ro.bluetooth.alwaysbleon=true\n" - "\n" - "#Simulate sdcard on /data/media\n" - "#\n" - "persist.fuse_sdcard=true\n" - "\n" - "#\n" - "#snapdragon value add features\n" - "#\n" - "ro.qc.sdk.audio.ssr=false\n" - "##fluencetype can be \"fluence\" or \"fluencepro\" or \"none\"\n" - "ro.qc.sdk.audio.fluencetype=none\n" - "persist.audio.fluence.voicecall=true\n" - "persist.audio.fluence.voicerec=false\n" - "persist.audio.fluence.speaker=true\n" - "\n" - "ro.qc.sdk.sensors.gestures=true\n" - "ro.qc.sdk.gestures.camera=false\n" - "ro.qc.sdk.camera.facialproc=false\n" - "# system prop for NFC DT\n" - "ro.nfc.port=I2C\n" - "#property to enable user to access Google WFD settings.\n" - "persist.debug.wfd.enable=1\n" - "#property to choose between virtual/external wfd display\n" - "persist.sys.wfd.virtual=0\n" - "tunnel.audio.encode = true\n" - "\n" - "#use VERY_HIGH_QUALITY for audio resampler\n" - "af.resampler.quality=4\n" - "\n" - "#Buffer size in kbytes for compress offload playback\n" - "audio.offload.buffer.size.kb=32\n" - "\n" - "#Enable offload audio video playback by default\n" - "av.offload.enable=true\n" - "\n" - "#enable voice path for PCM VoIP by default\n" - "use.voice.path.for.pcm.voip=true\n" - "\n" - "#hwui properties\n" - "ro.hwui.texture_cache_size=72\n" - "ro.hwui.layer_cache_size=48\n" - "ro.hwui.r_buffer_cache_size=8\n" - "ro.hwui.path_cache_size=32\n" - "ro.hwui.gradient_cache_size=1\n" - "ro.hwui.drop_shadow_cache_size=6\n" - "ro.hwui.texture_cache_flushrate=0.4\n" - "ro.hwui.text_small_cache_width=1024\n" - "ro.hwui.text_small_cache_height=1024\n" - "ro.hwui.text_large_cache_width=2048\n" - "ro.hwui.text_large_cache_height=1024\n" - "\n" - "#disable dsp gapless mode by default\n" - "audio.offload.gapless.enabled=false\n" - "\n" - "\n" - "# Enable time services daemon\n" - "persist.timed.enable=true\n" - "\n" - "# Data modules (For evolution RIL model)\n" - "ro.use_data_netmgrd=false\n" - "persist.data.netmgrd.qos.enable=false\n" - "\n" - "# SAMP SDHA\n" - "ro.config.oomminfree_high32=73728,92160,110592,129024,147456,184320\n" - "\n" - "#\n" - "# ADDITIONAL_BUILD_PROPERTIES\n" - "#\n" - "ro.astcenc.astcsupport=0\n" - "ro.mct.compressiontype=ETC2\n" - "ro.config.tima=1\n" - "ro.config.timaversion=3.0\n" - "ro.config.rkp=true\n" - "ro.use_data_netmgrd=false\n" - "ro.config.alarm_alert=Morning_flower.ogg\n" - "ro.config.ringtone=ATT_Firefly_Default.ogg\n" - "ro.config.notification_sound=Whisper.ogg\n" - "ro.config.ringtone_2=Basic_Bell.ogg\n" - "ro.config.notification_sound_2=S_Charming_Bell.ogg\n" - "keyguard.no_require_sim=true\n" - "ro.com.android.dateformat=MM-dd-yyyy\n" - "ro.carrier=unknown\n" - "ro.com.google.clientidbase=android-samsung\n" - "ro.security.icd.flagmode=single\n" - "ro.vendor.extension_library=libqti-perfd-client.so\n" - "persist.radio.apm_sim_not_pwdn=1\n" - "dalvik.vm.heapstartsize=8m\n" - "dalvik.vm.heapgrowthlimit=128m\n" - "dalvik.vm.heapsize=512m\n" - "dalvik.vm.heaptargetutilization=0.75\n" - "dalvik.vm.heapminfree=2m\n" - "dalvik.vm.heapmaxfree=8m\n" - "ro.build.scafe=americano\n" - "ro.build.scafe.size=short\n" - "ro.build.scafe.shot=single\n" - "ro.build.scafe.cream=white\n" - "ro.sec.fle.encryption=true\n" - "ro.hdcp2.rx=tz\n" - "media.enable-commonsource=true\n" - "ro.secwvk=144\n" - "ro.securestorage.support=true\n" - "security.mdpp=None\n" - "ro.security.mdpp.ver=1.1\n" - "ro.security.mdpp.release=4\n" - "ro.security.vpnpp.ver=1.4\n" - "ro.security.vpnpp.release=5.3\n" - "security.mdpp.result=None\n" - "ro.security.mdpp.ux=Enabled\n" - "ro.config.dha_cached_max=8\n" - "ro.config.dha_empty_init=36\n" - "ro.config.dha_empty_max=36\n" - "ro.config.dha_th_rate=1.83\n" - "ro.config.ldha_ext_enable=true\n" - "ro.error.receiver.default=com.samsung.receiver.error\n" - "ro.security.reactive.active=1\n" - "ro.smps.enable=true\n" - "ro.setupwizard.mode=DISABLED\n" - "ro.com.google.clientidbase.ms=android-att-us\n" - "ro.com.google.clientidbase.am=android-att-us\n" - "ro.com.google.clientidbase.yt=android-samsung\n" - "ro.com.google.clientidbase.gmm=android-samsung\n" - "ro.com.google.gmsversion=5.1_r2\n" - "persist.sys.dalvik.vm.lib.2=libart.so\n" - "ro.build.selinux=1\n" - "dalvik.vm.isa.arm.features=div\n" - "ro.config.knox=v30\n" - "ro.kernel.qemu=0\n" - "net.bt.name=Android\n" - "dalvik.vm.stack-trace-file=/data/anr/traces.txt\n" - "persist.gps.qc_nlp_in_use=1\n" - "persist.loc.nlp_name=com.qualcomm.location\n" - "ro.gps.agps_provider=1\n" - "ro.pip.gated=0\n" - "ro.build.aapt.config.prefer=xxhdpi\n" - "ro.build.version.sdl=2202\n" - "\n", + .content = "\n" + "# begin build properties\n" + "# autogenerated by buildinfo.sh\n" + "ro.build.id=LMY47X\n" + "ro.build.display.id=LMY47X.G900AUCU4CPA1\n" + "ro.build.version.incremental=G900AUCU4CPA1\n" + "ro.build.version.sdk=22\n" + "ro.build.version.codename=REL\n" + "ro.build.version.all_codenames=REL\n" + "ro.build.version.release=5.1.1\n" + "ro.build.version.security_patch=2016-02-01\n" + "ro.build.version.base_os=\n" + "ro.build.date=Wed Jan 27 21:23:36 KST 2016\n" + "ro.build.date.utc=1453897416\n" + "ro.build.type=user\n" + "ro.build.user=dpi\n" + "ro.build.host=SWHC3812\n" + "ro.build.tags=release-keys\n" + "ro.build.flavor=klteuc-user\n" + "ro.product.model=SAMSUNG-SM-G900A\n" + "ro.product.brand=samsung\n" + "ro.product.name=klteuc\n" + "ro.product.device=klteatt\n" + "ro.product.board=MSM8974\n" + "# ro.product.cpu.abi and ro.product.cpu.abi2 are obsolete,\n" + "# use ro.product.cpu.abilist instead.\n" + "ro.product.cpu.abi=armeabi-v7a\n" + "ro.product.cpu.abi2=armeabi\n" + "ro.product.cpu.abilist=armeabi-v7a,armeabi\n" + "ro.product.cpu.abilist32=armeabi-v7a,armeabi\n" + "ro.product.cpu.abilist64=\n" + "ro.product.manufacturer=samsung\n" + "ro.product.locale.language=en\n" + "ro.product.locale.region=US\n" + "ro.wifi.channels=\n" + "ro.board.platform=msm8974\n" + "# ro.build.product is obsolete; use ro.product.device\n" + "ro.build.product=klteatt\n" + "# Do not try to parse description, fingerprint, or thumbprint\n" + "ro.build.description=klteuc-user 5.1.1 LMY47X G900AUCU4CPA1 release-keys\n" + "ro.build.fingerprint=samsung/klteuc/klteatt:5.1.1/LMY47X/G900AUCU4CPA1:user/release-keys\n" + "ro.build.characteristics=att\n" + "# Samsung Specific Properties\n" + "ro.build.PDA=G900AUCU4CPA1\n" + "ro.build.hidden_ver=G900AUCU4CPA1\n" + "ro.config.rm_preload_enabled=0\n" + "ro.build.changelist=5869384\n" + "ro.product_ship=true\n" + "ro.chipname=MSM8974PRO\n" + "persist.sys.storage_preload=1\n" + "# end build properties\n" + "\n" + "#\n" + "# HWUI_BUILD_PROPERTIES\n" + "#\n" + "ro.hwui.texture_cache_size=50\n" + "ro.hwui.layer_cache_size=34\n" + "ro.hwui.path_cache_size=10\n" + "ro.hwui.shape_cache_size=4\n" + "ro.hwui.gradient_cache_size=2\n" + "ro.hwui.drop_shadow_cache_size=6\n" + "ro.hwui.r_buffer_cache_size=4\n" + "ro.hwui.text_small_cache_width=2048\n" + "ro.hwui.text_small_cache_height=2048\n" + "ro.hwui.text_large_cache_width=4096\n" + "ro.hwui.text_large_cache_height=4096\n" + "ro.hwui.fbo_cache_size=16\n" + "#\n" + "# from device/samsung/klteatt/system.prop\n" + "#\n" + "#\n" + "# system.prop for msm8974\n" + "#\n" + "\n" + "# LCD Density\n" + "ro.sf.lcd_density=480\n" + "\n" + "# Evolution RIL (8xxx)\n" + "rild.libpath=/system/lib/libsec-ril.so\n" + "rild.libargs=-d /dev/smd0\n" + "ril.subscription.types=NV,RUIM\n" + "DEVICE_PROVISIONED=1\n" + "\n" + "debug.sf.hw=1\n" + "debug.egl.hw=1\n" + "debug.composition.type=c2d\n" + "persist.hwc.mdpcomp.enable=true\n" + "debug.mdpcomp.logs=0\n" + "dalvik.vm.heapsize=36m\n" + "dev.pm.dyn_samplingrate=1\n" + "persist.demo.hdmirotationlock=false\n" + "\n" + "ro.hdmi.enable=true\n" + "persist.speaker.prot.enable=false\n" + "qcom.hw.aac.encoder=true\n" + "#\n" + "# system props for the cne module\n" + "#\n" + "#persist.cne.feature=1\n" + "\n" + "#system props for the MM modules\n" + "media.stagefright.enable-player=true\n" + "media.stagefright.enable-http=true\n" + "media.stagefright.enable-aac=true\n" + "media.stagefright.enable-qcp=true\n" + "media.stagefright.enable-fma2dp=true\n" + "media.stagefright.enable-scan=true\n" + "mmp.enable.3g2=true\n" + "mm.enable.smoothstreaming=true\n" + "media.aac_51_output_enabled=true\n" + "#37491 is decimal sum of supported codecs in AAL\n" + "#codecs: AVI AC3 ASF AAC QCP DTS 3G2 MP2TS\n" + "mm.enable.qcom_parser=37491\n" + "\n" + "# VIDC: debug_levels\n" + "# 1:ERROR 2:HIGH 4:LOW 0:NOLOGS 7:AllLOGS\n" + "vidc.debug.level=1\n" + "#\n" + "ro.data.large_tcp_window_size=true\n" + "\n" + "# system prop for opengles version\n" + "#\n" + "# 196608 is decimal for 0x30000 to report version 3\n" + "ro.opengles.version=196608\n" + "\n" + "# System property for cabl\n" + "ro.qualcomm.cabl=1\n" + "\n" + "#\n" + "# System props for bluetooth\n" + "# System prop to turn on hfp client\n" + "bluetooth.hfp.client=1\n" + "\n" + "#\n" + "# System props for bluetooth LE Always on feature\n" + "#\n" + "ro.bluetooth.alwaysbleon=true\n" + "\n" + "#Simulate sdcard on /data/media\n" + "#\n" + "persist.fuse_sdcard=true\n" + "\n" + "#\n" + "#snapdragon value add features\n" + "#\n" + "ro.qc.sdk.audio.ssr=false\n" + "##fluencetype can be \"fluence\" or \"fluencepro\" or \"none\"\n" + "ro.qc.sdk.audio.fluencetype=none\n" + "persist.audio.fluence.voicecall=true\n" + "persist.audio.fluence.voicerec=false\n" + "persist.audio.fluence.speaker=true\n" + "\n" + "ro.qc.sdk.sensors.gestures=true\n" + "ro.qc.sdk.gestures.camera=false\n" + "ro.qc.sdk.camera.facialproc=false\n" + "# system prop for NFC DT\n" + "ro.nfc.port=I2C\n" + "#property to enable user to access Google WFD settings.\n" + "persist.debug.wfd.enable=1\n" + "#property to choose between virtual/external wfd display\n" + "persist.sys.wfd.virtual=0\n" + "tunnel.audio.encode = true\n" + "\n" + "#use VERY_HIGH_QUALITY for audio resampler\n" + "af.resampler.quality=4\n" + "\n" + "#Buffer size in kbytes for compress offload playback\n" + "audio.offload.buffer.size.kb=32\n" + "\n" + "#Enable offload audio video playback by default\n" + "av.offload.enable=true\n" + "\n" + "#enable voice path for PCM VoIP by default\n" + "use.voice.path.for.pcm.voip=true\n" + "\n" + "#hwui properties\n" + "ro.hwui.texture_cache_size=72\n" + "ro.hwui.layer_cache_size=48\n" + "ro.hwui.r_buffer_cache_size=8\n" + "ro.hwui.path_cache_size=32\n" + "ro.hwui.gradient_cache_size=1\n" + "ro.hwui.drop_shadow_cache_size=6\n" + "ro.hwui.texture_cache_flushrate=0.4\n" + "ro.hwui.text_small_cache_width=1024\n" + "ro.hwui.text_small_cache_height=1024\n" + "ro.hwui.text_large_cache_width=2048\n" + "ro.hwui.text_large_cache_height=1024\n" + "\n" + "#disable dsp gapless mode by default\n" + "audio.offload.gapless.enabled=false\n" + "\n" + "\n" + "# Enable time services daemon\n" + "persist.timed.enable=true\n" + "\n" + "# Data modules (For evolution RIL model)\n" + "ro.use_data_netmgrd=false\n" + "persist.data.netmgrd.qos.enable=false\n" + "\n" + "# SAMP SDHA\n" + "ro.config.oomminfree_high32=73728,92160,110592,129024,147456,184320\n" + "\n" + "#\n" + "# ADDITIONAL_BUILD_PROPERTIES\n" + "#\n" + "ro.astcenc.astcsupport=0\n" + "ro.mct.compressiontype=ETC2\n" + "ro.config.tima=1\n" + "ro.config.timaversion=3.0\n" + "ro.config.rkp=true\n" + "ro.use_data_netmgrd=false\n" + "ro.config.alarm_alert=Morning_flower.ogg\n" + "ro.config.ringtone=ATT_Firefly_Default.ogg\n" + "ro.config.notification_sound=Whisper.ogg\n" + "ro.config.ringtone_2=Basic_Bell.ogg\n" + "ro.config.notification_sound_2=S_Charming_Bell.ogg\n" + "keyguard.no_require_sim=true\n" + "ro.com.android.dateformat=MM-dd-yyyy\n" + "ro.carrier=unknown\n" + "ro.com.google.clientidbase=android-samsung\n" + "ro.security.icd.flagmode=single\n" + "ro.vendor.extension_library=libqti-perfd-client.so\n" + "persist.radio.apm_sim_not_pwdn=1\n" + "dalvik.vm.heapstartsize=8m\n" + "dalvik.vm.heapgrowthlimit=128m\n" + "dalvik.vm.heapsize=512m\n" + "dalvik.vm.heaptargetutilization=0.75\n" + "dalvik.vm.heapminfree=2m\n" + "dalvik.vm.heapmaxfree=8m\n" + "ro.build.scafe=americano\n" + "ro.build.scafe.size=short\n" + "ro.build.scafe.shot=single\n" + "ro.build.scafe.cream=white\n" + "ro.sec.fle.encryption=true\n" + "ro.hdcp2.rx=tz\n" + "media.enable-commonsource=true\n" + "ro.secwvk=144\n" + "ro.securestorage.support=true\n" + "security.mdpp=None\n" + "ro.security.mdpp.ver=1.1\n" + "ro.security.mdpp.release=4\n" + "ro.security.vpnpp.ver=1.4\n" + "ro.security.vpnpp.release=5.3\n" + "security.mdpp.result=None\n" + "ro.security.mdpp.ux=Enabled\n" + "ro.config.dha_cached_max=8\n" + "ro.config.dha_empty_init=36\n" + "ro.config.dha_empty_max=36\n" + "ro.config.dha_th_rate=1.83\n" + "ro.config.ldha_ext_enable=true\n" + "ro.error.receiver.default=com.samsung.receiver.error\n" + "ro.security.reactive.active=1\n" + "ro.smps.enable=true\n" + "ro.setupwizard.mode=DISABLED\n" + "ro.com.google.clientidbase.ms=android-att-us\n" + "ro.com.google.clientidbase.am=android-att-us\n" + "ro.com.google.clientidbase.yt=android-samsung\n" + "ro.com.google.clientidbase.gmm=android-samsung\n" + "ro.com.google.gmsversion=5.1_r2\n" + "persist.sys.dalvik.vm.lib.2=libart.so\n" + "ro.build.selinux=1\n" + "dalvik.vm.isa.arm.features=div\n" + "ro.config.knox=v30\n" + "ro.kernel.qemu=0\n" + "net.bt.name=Android\n" + "dalvik.vm.stack-trace-file=/data/anr/traces.txt\n" + "persist.gps.qc_nlp_in_use=1\n" + "persist.loc.nlp_name=com.qualcomm.location\n" + "ro.gps.agps_provider=1\n" + "ro.pip.gated=0\n" + "ro.build.aapt.config.prefer=xxhdpi\n" + "ro.build.version.sdl=2202\n" + "\n", }, { .path = "/sys/devices/system/cpu/kernel_max", @@ -368,7 +366,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies", .size = 115, - .content = "300000 422400 652800 729600 883200 960000 1036800 1190400 1267200 1497600 1574400 1728000 1958400 2265600 2457600 \n", + .content = + "300000 422400 652800 729600 883200 960000 1036800 1190400 1267200 1497600 1574400 1728000 1958400 2265600 2457600 \n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors", @@ -398,22 +397,21 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 147, - .content = - "300000 0\n" - "422400 0\n" - "652800 0\n" - "729600 0\n" - "883200 0\n" - "960000 0\n" - "1036800 0\n" - "1190400 0\n" - "1267200 0\n" - "1497600 0\n" - "1574400 0\n" - "1728000 0\n" - "1958400 0\n" - "2265600 0\n" - "2457600 1372\n", + .content = "300000 0\n" + "422400 0\n" + "652800 0\n" + "729600 0\n" + "883200 0\n" + "960000 0\n" + "1036800 0\n" + "1190400 0\n" + "1267200 0\n" + "1497600 0\n" + "1574400 0\n" + "1728000 0\n" + "1958400 0\n" + "2265600 0\n" + "2457600 1372\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -478,7 +476,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_frequencies", .size = 115, - .content = "300000 422400 652800 729600 883200 960000 1036800 1190400 1267200 1497600 1574400 1728000 1958400 2265600 2457600 \n", + .content = + "300000 422400 652800 729600 883200 960000 1036800 1190400 1267200 1497600 1574400 1728000 1958400 2265600 2457600 \n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_governors", @@ -513,22 +512,21 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 147, - .content = - "300000 0\n" - "422400 0\n" - "652800 0\n" - "729600 0\n" - "883200 0\n" - "960000 0\n" - "1036800 0\n" - "1190400 0\n" - "1267200 0\n" - "1497600 0\n" - "1574400 0\n" - "1728000 0\n" - "1958400 0\n" - "2265600 0\n" - "2457600 1612\n", + .content = "300000 0\n" + "422400 0\n" + "652800 0\n" + "729600 0\n" + "883200 0\n" + "960000 0\n" + "1036800 0\n" + "1190400 0\n" + "1267200 0\n" + "1497600 0\n" + "1574400 0\n" + "1728000 0\n" + "1958400 0\n" + "2265600 0\n" + "2457600 1612\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -608,22 +606,21 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 145, - .content = - "300000 0\n" - "422400 0\n" - "652800 0\n" - "729600 0\n" - "883200 0\n" - "960000 0\n" - "1036800 0\n" - "1190400 0\n" - "1267200 0\n" - "1497600 0\n" - "1574400 0\n" - "1728000 0\n" - "1958400 0\n" - "2265600 0\n" - "2457600 11\n", + .content = "300000 0\n" + "422400 0\n" + "652800 0\n" + "729600 0\n" + "883200 0\n" + "960000 0\n" + "1036800 0\n" + "1190400 0\n" + "1267200 0\n" + "1497600 0\n" + "1574400 0\n" + "1728000 0\n" + "1958400 0\n" + "2265600 0\n" + "2457600 11\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -688,7 +685,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_frequencies", .size = 115, - .content = "300000 422400 652800 729600 883200 960000 1036800 1190400 1267200 1497600 1574400 1728000 1958400 2265600 2457600 \n", + .content = + "300000 422400 652800 729600 883200 960000 1036800 1190400 1267200 1497600 1574400 1728000 1958400 2265600 2457600 \n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_governors", @@ -723,22 +721,21 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 146, - .content = - "300000 0\n" - "422400 0\n" - "652800 0\n" - "729600 0\n" - "883200 0\n" - "960000 0\n" - "1036800 0\n" - "1190400 0\n" - "1267200 0\n" - "1497600 0\n" - "1574400 0\n" - "1728000 0\n" - "1958400 0\n" - "2265600 0\n" - "2457600 208\n", + .content = "300000 0\n" + "422400 0\n" + "652800 0\n" + "729600 0\n" + "883200 0\n" + "960000 0\n" + "1036800 0\n" + "1190400 0\n" + "1267200 0\n" + "1497600 0\n" + "1574400 0\n" + "1728000 0\n" + "1958400 0\n" + "2265600 0\n" + "2457600 208\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -775,7 +772,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "8\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ @@ -2500,6 +2497,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.wfd.status", .value = "disconnected", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/galaxy-s6.cc b/test/mock/galaxy-s6.cc index 0085cfdb..2f4af986 100644 --- a/test/mock/galaxy-s6.cc +++ b/test/mock/galaxy-s6.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(8, cpuinfo_get_processors_count()); @@ -334,8 +333,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Samsung Exynos 7420", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Samsung Exynos 7420", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -377,59 +378,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -580,8 +581,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -645,8 +648,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -704,8 +709,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/galaxy-s6.h b/test/mock/galaxy-s6.h index 447a6094..293cd710 100644 --- a/test/mock/galaxy-s6.h +++ b/test/mock/galaxy-s6.h @@ -3,24 +3,23 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 337, - .content = - "Processor\t: AArch64 Processor rev 2 (aarch64)\n" - "processor\t: 0\n" - "processor\t: 1\n" - "processor\t: 2\n" - "processor\t: 3\n" - "processor\t: 4\n" - "processor\t: 5\n" - "processor\t: 6\n" - "processor\t: 7\n" - "Features\t: fp asimd aes pmull sha1 sha2 crc32 \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: AArch64\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 2\n" - "\n" - "Hardware\t: SAMSUNG Exynos7420\n", + .content = "Processor\t: AArch64 Processor rev 2 (aarch64)\n" + "processor\t: 0\n" + "processor\t: 1\n" + "processor\t: 2\n" + "processor\t: 3\n" + "processor\t: 4\n" + "processor\t: 5\n" + "processor\t: 6\n" + "processor\t: 7\n" + "Features\t: fp asimd aes pmull sha1 sha2 crc32 \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: AArch64\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 2\n" + "\n" + "Hardware\t: SAMSUNG Exynos7420\n", }, #elif CPUINFO_ARCH_ARM { @@ -266,28 +265,27 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpufreq/all_time_in_state", .size = 1057, - .content = - "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\t\n" - "400000\t\t8024\t\t8024\t\t8024\t\t8024\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "500000\t\t160\t\t160\t\t160\t\t160\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "600000\t\t82\t\t82\t\t82\t\t82\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "700000\t\t130\t\t130\t\t130\t\t130\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "800000\t\t222\t\t222\t\t222\t\t222\t\t11693\t\t11693\t\t11693\t\t11693\t\t\n" - "900000\t\t1061\t\t1061\t\t1061\t\t1061\t\t86\t\t86\t\t86\t\t86\t\t\n" - "1000000\t\t1703\t\t1703\t\t1703\t\t1703\t\t485\t\t485\t\t485\t\t485\t\t\n" - "1100000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t19\t\t19\t\t19\t\t19\t\t\n" - "1104000\t\t255\t\t255\t\t255\t\t255\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1200000\t\t565\t\t565\t\t565\t\t565\t\t1695\t\t1695\t\t1695\t\t1695\t\t\n" - "1296000\t\t4358\t\t4358\t\t4358\t\t4358\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1300000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t243\t\t243\t\t243\t\t243\t\t\n" - "1400000\t\t2317\t\t2317\t\t2317\t\t2317\t\t60\t\t60\t\t60\t\t60\t\t\n" - "1500000\t\t0\t\t0\t\t0\t\t0\t\t79\t\t79\t\t79\t\t79\t\t\n" - "1600000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t114\t\t114\t\t114\t\t114\t\t\n" - "1704000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t2576\t\t2576\t\t2576\t\t2576\t\t\n" - "1800000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t674\t\t674\t\t674\t\t674\t\t\n" - "1896000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t298\t\t298\t\t298\t\t298\t\t\n" - "2000000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t171\t\t171\t\t171\t\t171\t\t\n" - "2100000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t684\t\t684\t\t684\t\t684\t\t\n", + .content = "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\t\n" + "400000\t\t8024\t\t8024\t\t8024\t\t8024\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "500000\t\t160\t\t160\t\t160\t\t160\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "600000\t\t82\t\t82\t\t82\t\t82\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "700000\t\t130\t\t130\t\t130\t\t130\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "800000\t\t222\t\t222\t\t222\t\t222\t\t11693\t\t11693\t\t11693\t\t11693\t\t\n" + "900000\t\t1061\t\t1061\t\t1061\t\t1061\t\t86\t\t86\t\t86\t\t86\t\t\n" + "1000000\t\t1703\t\t1703\t\t1703\t\t1703\t\t485\t\t485\t\t485\t\t485\t\t\n" + "1100000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t19\t\t19\t\t19\t\t19\t\t\n" + "1104000\t\t255\t\t255\t\t255\t\t255\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "1200000\t\t565\t\t565\t\t565\t\t565\t\t1695\t\t1695\t\t1695\t\t1695\t\t\n" + "1296000\t\t4358\t\t4358\t\t4358\t\t4358\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "1300000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t243\t\t243\t\t243\t\t243\t\t\n" + "1400000\t\t2317\t\t2317\t\t2317\t\t2317\t\t60\t\t60\t\t60\t\t60\t\t\n" + "1500000\t\t0\t\t0\t\t0\t\t0\t\t79\t\t79\t\t79\t\t79\t\t\n" + "1600000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t114\t\t114\t\t114\t\t114\t\t\n" + "1704000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t2576\t\t2576\t\t2576\t\t2576\t\t\n" + "1800000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t674\t\t674\t\t674\t\t674\t\t\n" + "1896000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t298\t\t298\t\t298\t\t298\t\t\n" + "2000000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t171\t\t171\t\t171\t\t171\t\t\n" + "2100000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t684\t\t684\t\t684\t\t684\t\t\n", }, { .path = "/sys/devices/system/cpu/cpuidle/current_driver", @@ -357,19 +355,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 140, - .content = - "1500000 0\n" - "1400000 2317\n" - "1296000 4358\n" - "1200000 565\n" - "1104000 255\n" - "1000000 1703\n" - "900000 1067\n" - "800000 222\n" - "700000 130\n" - "600000 82\n" - "500000 160\n" - "400000 8170\n", + .content = "1500000 0\n" + "1400000 2317\n" + "1296000 4358\n" + "1200000 565\n" + "1104000 255\n" + "1000000 1703\n" + "900000 1067\n" + "800000 222\n" + "700000 130\n" + "600000 82\n" + "500000 160\n" + "400000 8170\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -464,19 +461,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 140, - .content = - "1500000 0\n" - "1400000 2317\n" - "1296000 4358\n" - "1200000 565\n" - "1104000 255\n" - "1000000 1703\n" - "900000 1091\n" - "800000 224\n" - "700000 130\n" - "600000 85\n" - "500000 168\n" - "400000 8396\n", + .content = "1500000 0\n" + "1400000 2317\n" + "1296000 4358\n" + "1200000 565\n" + "1104000 255\n" + "1000000 1703\n" + "900000 1091\n" + "800000 224\n" + "700000 130\n" + "600000 85\n" + "500000 168\n" + "400000 8396\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -571,19 +567,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 140, - .content = - "1500000 0\n" - "1400000 2317\n" - "1296000 4358\n" - "1200000 565\n" - "1104000 255\n" - "1000000 1707\n" - "900000 1109\n" - "800000 224\n" - "700000 130\n" - "600000 91\n" - "500000 168\n" - "400000 8628\n", + .content = "1500000 0\n" + "1400000 2317\n" + "1296000 4358\n" + "1200000 565\n" + "1104000 255\n" + "1000000 1707\n" + "900000 1109\n" + "800000 224\n" + "700000 130\n" + "600000 91\n" + "500000 168\n" + "400000 8628\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -678,19 +673,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 140, - .content = - "1500000 0\n" - "1400000 2317\n" - "1296000 4358\n" - "1200000 565\n" - "1104000 255\n" - "1000000 1707\n" - "900000 1115\n" - "800000 224\n" - "700000 130\n" - "600000 91\n" - "500000 168\n" - "400000 8885\n", + .content = "1500000 0\n" + "1400000 2317\n" + "1296000 4358\n" + "1200000 565\n" + "1104000 255\n" + "1000000 1707\n" + "900000 1115\n" + "800000 224\n" + "700000 130\n" + "600000 91\n" + "500000 168\n" + "400000 8885\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -785,21 +779,20 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/time_in_state", .size = 166, - .content = - "2100000 684\n" - "2000000 171\n" - "1896000 298\n" - "1800000 674\n" - "1704000 2576\n" - "1600000 114\n" - "1500000 79\n" - "1400000 60\n" - "1300000 243\n" - "1200000 1695\n" - "1100000 19\n" - "1000000 485\n" - "900000 86\n" - "800000 12910\n", + .content = "2100000 684\n" + "2000000 171\n" + "1896000 298\n" + "1800000 674\n" + "1704000 2576\n" + "1600000 114\n" + "1500000 79\n" + "1400000 60\n" + "1300000 243\n" + "1200000 1695\n" + "1100000 19\n" + "1000000 485\n" + "900000 86\n" + "800000 12910\n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/total_trans", @@ -894,21 +887,20 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/time_in_state", .size = 166, - .content = - "2100000 684\n" - "2000000 171\n" - "1896000 298\n" - "1800000 674\n" - "1704000 2576\n" - "1600000 114\n" - "1500000 79\n" - "1400000 60\n" - "1300000 243\n" - "1200000 1695\n" - "1100000 19\n" - "1000000 485\n" - "900000 86\n" - "800000 13210\n", + .content = "2100000 684\n" + "2000000 171\n" + "1896000 298\n" + "1800000 674\n" + "1704000 2576\n" + "1600000 114\n" + "1500000 79\n" + "1400000 60\n" + "1300000 243\n" + "1200000 1695\n" + "1100000 19\n" + "1000000 485\n" + "900000 86\n" + "800000 13210\n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/total_trans", @@ -1003,21 +995,20 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/time_in_state", .size = 166, - .content = - "2100000 684\n" - "2000000 171\n" - "1896000 298\n" - "1800000 674\n" - "1704000 2576\n" - "1600000 114\n" - "1500000 79\n" - "1400000 60\n" - "1300000 243\n" - "1200000 1695\n" - "1100000 19\n" - "1000000 485\n" - "900000 86\n" - "800000 13489\n", + .content = "2100000 684\n" + "2000000 171\n" + "1896000 298\n" + "1800000 674\n" + "1704000 2576\n" + "1600000 114\n" + "1500000 79\n" + "1400000 60\n" + "1300000 243\n" + "1200000 1695\n" + "1100000 19\n" + "1000000 485\n" + "900000 86\n" + "800000 13489\n", }, { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/total_trans", @@ -1114,7 +1105,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "7\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -2914,6 +2905,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.wfd.status", .value = "disconnected", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/galaxy-s7-global.cc b/test/mock/galaxy-s7-global.cc index 620f2c1b..b2f1d08d 100644 --- a/test/mock/galaxy-s7-global.cc +++ b/test/mock/galaxy-s7-global.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(8, cpuinfo_get_processors_count()); @@ -354,8 +353,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Samsung Exynos 8890", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Samsung Exynos 8890", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -397,59 +398,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -600,8 +601,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -678,8 +681,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -737,8 +742,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/galaxy-s7-global.h b/test/mock/galaxy-s7-global.h index 1345a8b1..776b8ec2 100644 --- a/test/mock/galaxy-s7-global.h +++ b/test/mock/galaxy-s7-global.h @@ -3,55 +3,54 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 984, - .content = - "processor\t: 0\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 1\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 2\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 3\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 4\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x53\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x1\n" - "CPU part\t: 0x001\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 5\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x53\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x1\n" - "CPU part\t: 0x001\n" - "CPU revision\t: 1\n" - "\n", + .content = "processor\t: 0\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 1\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 2\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 3\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 4\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x53\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0x001\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 5\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x53\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0x001\n" + "CPU revision\t: 1\n" + "\n", }, #elif CPUINFO_ARCH_ARM { @@ -111,176 +110,175 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/system/build.prop", .size = 4795, - .content = - "\n" - "# begin build properties\n" - "# autogenerated by buildinfo.sh\n" - "ro.build.id=NRD90M\n" - "ro.build.display.id=NRD90M.G930FXXU1DQJ8\n" - "ro.build.version.incremental=G930FXXU1DQJ8\n" - "ro.build.version.sdk=24\n" - "ro.build.version.preview_sdk=0\n" - "ro.build.version.codename=REL\n" - "ro.build.version.all_codenames=REL\n" - "ro.build.version.release=7.0\n" - "ro.build.version.security_patch=2017-10-01\n" - "ro.build.version.base_os=\n" - "ro.build.date=Tue Oct 24 15:32:43 KST 2017\n" - "ro.build.date.utc=1508826763\n" - "ro.build.type=user\n" - "ro.build.user=dpi\n" - "ro.build.host=SWDG5301\n" - "ro.build.tags=release-keys\n" - "ro.build.flavor=heroltexx-user\n" - "ro.product.model=SM-G930F\n" - "ro.product.brand=samsung\n" - "ro.product.name=heroltexx\n" - "ro.product.device=herolte\n" - "ro.product.board=universal8890\n" - "# ro.product.cpu.abi and ro.product.cpu.abi2 are obsolete,\n" - "# use ro.product.cpu.abilist instead.\n" - "ro.product.cpu.abi=arm64-v8a\n" - "ro.product.cpu.abilist=arm64-v8a,armeabi-v7a,armeabi\n" - "ro.product.cpu.abilist32=armeabi-v7a,armeabi\n" - "ro.product.cpu.abilist64=arm64-v8a\n" - "ro.product.manufacturer=samsung\n" - "ro.product.locale=en-GB\n" - "ro.wifi.channels=\n" - "ro.board.platform=exynos5\n" - "# ro.build.product is obsolete; use ro.product.device\n" - "ro.build.product=herolte\n" - "# Do not try to parse description, fingerprint, or thumbprint\n" - "ro.build.description=heroltexx-user 7.0 NRD90M G930FXXU1DQJ8 release-keys\n" - "ro.build.fingerprint=samsung/heroltexx/herolte:7.0/NRD90M/G930FXXU1DQJ8:user/release-keys\n" - "ro.build.characteristics=phone,emulator\n" - "# Samsung Specific Properties\n" - "ro.build.PDA=G930FXXU1DQJ8\n" - "ro.build.official.release=true\n" - "ro.build.hidden_ver=G930FXXU1DQJ8\n" - "ro.config.rm_preload_enabled=0\n" - "ro.build.changelist=12365438\n" - "ro.product_ship=true\n" - "ro.chipname=exynos8890\n" - "# end build properties\n" - "\n" - "#\n" - "# HWUI_BUILD_PROPERTIES\n" - "#\n" - "ro.hwui.texture_cache_size=88\n" - "ro.hwui.layer_cache_size=58\n" - "ro.hwui.path_cache_size=16\n" - "ro.hwui.texture_cache_flushrate=0.4\n" - "ro.hwui.shape_cache_size=4\n" - "ro.hwui.gradient_cache_size=2\n" - "ro.hwui.drop_shadow_cache_size=6\n" - "ro.hwui.r_buffer_cache_size=8\n" - "ro.hwui.text_small_cache_width=1024\n" - "ro.hwui.text_small_cache_height=1024\n" - "ro.hwui.text_large_cache_width=4096\n" - "ro.hwui.text_large_cache_height=2048\n" - "#\n" - "# from device/samsung/herolte/system.prop\n" - "#\n" - "#\n" - "# system.prop for universal8890\n" - "#\n" - "\n" - "ro.sf.lcd_density=480\n" - "ro.sf.init.lcd_density=640\n" - "\n" - "ro.arch=exynos8890\n" - "ro.kernel.qemu=0\n" - "ro.kernel.qemu.gles=0\n" - "persist.demo.hdmirotationlock=false\n" - "\n" - "# read DS/SS property\n" - "import /efs/factory.prop\n" - "\n" - "#\n" - "# ADDITIONAL_BUILD_PROPERTIES\n" - "#\n" - "ro.astcenc.astcsupport=1\n" - "ro.mct.compressiontype=ETC1\n" - "persist.radio.sib16_support=1\n" - "ro.config.dmverity=true\n" - "ro.config.rkp=true\n" - "ro.config.kap_default_on=true\n" - "ro.config.kap=true\n" - "ro.supportmodel.mptcp=1\n" - "rild.libpath=/system/lib64/libsec-ril.so\n" - "rild.libpath2=/system/lib64/libsec-ril-dsds.so\n" - "ro.radio.noril=no\n" - "ro.telephony.default_network=9\n" - "ro.multisim.simslotcount=2\n" - "ro.knox.enhance.zygote.aslr=0\n" - "ro.product.first_api_level=23\n" - "ro.config.ringtone=Over_the_Horizon.ogg\n" - "ro.config.notification_sound=Skyline.ogg\n" - "ro.config.alarm_alert=Morning_Flower.ogg\n" - "ro.config.media_sound=Media_preview_Touch_the_light.ogg\n" - "ro.config.ringtone_2=Basic_Bell.ogg\n" - "ro.config.notification_sound_2=S_Charming_Bell.ogg\n" - "ro.config.systemaudiodebug=arizona\n" - "ro.opengles.version=196610\n" - "ro.sf.lcd_density=480\n" - "debug.slsi_platform=1\n" - "debug.hwc.winupdate=1\n" - "ro.exynos.dss=1\n" - "drm.service.enabled=true\n" - "dalvik.vm.heapstartsize=8m\n" - "dalvik.vm.heapgrowthlimit=256m\n" - "dalvik.vm.heapsize=512m\n" - "dalvik.vm.heaptargetutilization=0.75\n" - "dalvik.vm.heapminfree=2m\n" - "dalvik.vm.heapmaxfree=8m\n" - "ro.hdcp2.rx=tz\n" - "ro.securestorage.support=true\n" - "ro.build.scafe.version=2017A\n" - "security.mdpp=None\n" - "ro.security.mdpp.ver=3.0\n" - "ro.security.mdpp.release=2\n" - "ro.security.wlan.ver=1.0\n" - "ro.security.wlan.release=2\n" - "security.mdpp.result=None\n" - "ro.hardware.keystore=mdfpp\n" - "ro.security.vpnpp.ver=1.4\n" - "ro.security.vpnpp.release=8.0\n" - "ro.security.mdpp.ux=Enabled\n" - "ro.frp.pst=/dev/block/persistent\n" - "ro.error.receiver.default=com.samsung.receiver.error\n" - "ro.config.dha_cached_min=8\n" - "ro.config.dha_cached_max=16\n" - "ro.config.dha_empty_min=8\n" - "ro.config.dha_empty_max=32\n" - "ro.config.dha_pwhitelist_enable=1\n" - "ro.config.fall_prevent_enable=true\n" - "keyguard.no_require_sim=true\n" - "ro.carrier=unknown\n" - "ro.security.icd.flagmode=multi\n" - "security.ASKS.policy_version=000000\n" - "ro.com.google.clientidbase=android-samsung\n" - "ro.ril.hsxpa=1\n" - "ro.ril.gprsclass=10\n" - "ro.adb.qemud=1\n" - "ro.setupwizard.mode=OPTIONAL\n" - "ro.com.google.gmsversion=7.0_r8\n" - "ro.build.selinux=1\n" - "persist.sys.dalvik.vm.lib.2=libart.so\n" - "dalvik.vm.isa.arm64.variant=exynos-m1\n" - "dalvik.vm.isa.arm64.features=default\n" - "dalvik.vm.isa.arm.variant=cortex-a15\n" - "dalvik.vm.isa.arm.features=default\n" - "ro.config.knox=v30\n" - "ro.config.tima=1\n" - "ro.config.timaversion=3.0\n" - "ro.config.iccc_version=1.0\n" - "ro.kernel.qemu=0\n" - "net.bt.name=Android\n" - "dalvik.vm.stack-trace-file=/data/anr/traces.txt\n" - "ro.build.version.sem=2402\n" - "ro.build.version.sep=80000\n" - "ro.expect.recovery_id=0x3febbe7420c506f45403ac14bdc221ea9ca7838d000000000000000000000000\n" - "\n", + .content = "\n" + "# begin build properties\n" + "# autogenerated by buildinfo.sh\n" + "ro.build.id=NRD90M\n" + "ro.build.display.id=NRD90M.G930FXXU1DQJ8\n" + "ro.build.version.incremental=G930FXXU1DQJ8\n" + "ro.build.version.sdk=24\n" + "ro.build.version.preview_sdk=0\n" + "ro.build.version.codename=REL\n" + "ro.build.version.all_codenames=REL\n" + "ro.build.version.release=7.0\n" + "ro.build.version.security_patch=2017-10-01\n" + "ro.build.version.base_os=\n" + "ro.build.date=Tue Oct 24 15:32:43 KST 2017\n" + "ro.build.date.utc=1508826763\n" + "ro.build.type=user\n" + "ro.build.user=dpi\n" + "ro.build.host=SWDG5301\n" + "ro.build.tags=release-keys\n" + "ro.build.flavor=heroltexx-user\n" + "ro.product.model=SM-G930F\n" + "ro.product.brand=samsung\n" + "ro.product.name=heroltexx\n" + "ro.product.device=herolte\n" + "ro.product.board=universal8890\n" + "# ro.product.cpu.abi and ro.product.cpu.abi2 are obsolete,\n" + "# use ro.product.cpu.abilist instead.\n" + "ro.product.cpu.abi=arm64-v8a\n" + "ro.product.cpu.abilist=arm64-v8a,armeabi-v7a,armeabi\n" + "ro.product.cpu.abilist32=armeabi-v7a,armeabi\n" + "ro.product.cpu.abilist64=arm64-v8a\n" + "ro.product.manufacturer=samsung\n" + "ro.product.locale=en-GB\n" + "ro.wifi.channels=\n" + "ro.board.platform=exynos5\n" + "# ro.build.product is obsolete; use ro.product.device\n" + "ro.build.product=herolte\n" + "# Do not try to parse description, fingerprint, or thumbprint\n" + "ro.build.description=heroltexx-user 7.0 NRD90M G930FXXU1DQJ8 release-keys\n" + "ro.build.fingerprint=samsung/heroltexx/herolte:7.0/NRD90M/G930FXXU1DQJ8:user/release-keys\n" + "ro.build.characteristics=phone,emulator\n" + "# Samsung Specific Properties\n" + "ro.build.PDA=G930FXXU1DQJ8\n" + "ro.build.official.release=true\n" + "ro.build.hidden_ver=G930FXXU1DQJ8\n" + "ro.config.rm_preload_enabled=0\n" + "ro.build.changelist=12365438\n" + "ro.product_ship=true\n" + "ro.chipname=exynos8890\n" + "# end build properties\n" + "\n" + "#\n" + "# HWUI_BUILD_PROPERTIES\n" + "#\n" + "ro.hwui.texture_cache_size=88\n" + "ro.hwui.layer_cache_size=58\n" + "ro.hwui.path_cache_size=16\n" + "ro.hwui.texture_cache_flushrate=0.4\n" + "ro.hwui.shape_cache_size=4\n" + "ro.hwui.gradient_cache_size=2\n" + "ro.hwui.drop_shadow_cache_size=6\n" + "ro.hwui.r_buffer_cache_size=8\n" + "ro.hwui.text_small_cache_width=1024\n" + "ro.hwui.text_small_cache_height=1024\n" + "ro.hwui.text_large_cache_width=4096\n" + "ro.hwui.text_large_cache_height=2048\n" + "#\n" + "# from device/samsung/herolte/system.prop\n" + "#\n" + "#\n" + "# system.prop for universal8890\n" + "#\n" + "\n" + "ro.sf.lcd_density=480\n" + "ro.sf.init.lcd_density=640\n" + "\n" + "ro.arch=exynos8890\n" + "ro.kernel.qemu=0\n" + "ro.kernel.qemu.gles=0\n" + "persist.demo.hdmirotationlock=false\n" + "\n" + "# read DS/SS property\n" + "import /efs/factory.prop\n" + "\n" + "#\n" + "# ADDITIONAL_BUILD_PROPERTIES\n" + "#\n" + "ro.astcenc.astcsupport=1\n" + "ro.mct.compressiontype=ETC1\n" + "persist.radio.sib16_support=1\n" + "ro.config.dmverity=true\n" + "ro.config.rkp=true\n" + "ro.config.kap_default_on=true\n" + "ro.config.kap=true\n" + "ro.supportmodel.mptcp=1\n" + "rild.libpath=/system/lib64/libsec-ril.so\n" + "rild.libpath2=/system/lib64/libsec-ril-dsds.so\n" + "ro.radio.noril=no\n" + "ro.telephony.default_network=9\n" + "ro.multisim.simslotcount=2\n" + "ro.knox.enhance.zygote.aslr=0\n" + "ro.product.first_api_level=23\n" + "ro.config.ringtone=Over_the_Horizon.ogg\n" + "ro.config.notification_sound=Skyline.ogg\n" + "ro.config.alarm_alert=Morning_Flower.ogg\n" + "ro.config.media_sound=Media_preview_Touch_the_light.ogg\n" + "ro.config.ringtone_2=Basic_Bell.ogg\n" + "ro.config.notification_sound_2=S_Charming_Bell.ogg\n" + "ro.config.systemaudiodebug=arizona\n" + "ro.opengles.version=196610\n" + "ro.sf.lcd_density=480\n" + "debug.slsi_platform=1\n" + "debug.hwc.winupdate=1\n" + "ro.exynos.dss=1\n" + "drm.service.enabled=true\n" + "dalvik.vm.heapstartsize=8m\n" + "dalvik.vm.heapgrowthlimit=256m\n" + "dalvik.vm.heapsize=512m\n" + "dalvik.vm.heaptargetutilization=0.75\n" + "dalvik.vm.heapminfree=2m\n" + "dalvik.vm.heapmaxfree=8m\n" + "ro.hdcp2.rx=tz\n" + "ro.securestorage.support=true\n" + "ro.build.scafe.version=2017A\n" + "security.mdpp=None\n" + "ro.security.mdpp.ver=3.0\n" + "ro.security.mdpp.release=2\n" + "ro.security.wlan.ver=1.0\n" + "ro.security.wlan.release=2\n" + "security.mdpp.result=None\n" + "ro.hardware.keystore=mdfpp\n" + "ro.security.vpnpp.ver=1.4\n" + "ro.security.vpnpp.release=8.0\n" + "ro.security.mdpp.ux=Enabled\n" + "ro.frp.pst=/dev/block/persistent\n" + "ro.error.receiver.default=com.samsung.receiver.error\n" + "ro.config.dha_cached_min=8\n" + "ro.config.dha_cached_max=16\n" + "ro.config.dha_empty_min=8\n" + "ro.config.dha_empty_max=32\n" + "ro.config.dha_pwhitelist_enable=1\n" + "ro.config.fall_prevent_enable=true\n" + "keyguard.no_require_sim=true\n" + "ro.carrier=unknown\n" + "ro.security.icd.flagmode=multi\n" + "security.ASKS.policy_version=000000\n" + "ro.com.google.clientidbase=android-samsung\n" + "ro.ril.hsxpa=1\n" + "ro.ril.gprsclass=10\n" + "ro.adb.qemud=1\n" + "ro.setupwizard.mode=OPTIONAL\n" + "ro.com.google.gmsversion=7.0_r8\n" + "ro.build.selinux=1\n" + "persist.sys.dalvik.vm.lib.2=libart.so\n" + "dalvik.vm.isa.arm64.variant=exynos-m1\n" + "dalvik.vm.isa.arm64.features=default\n" + "dalvik.vm.isa.arm.variant=cortex-a15\n" + "dalvik.vm.isa.arm.features=default\n" + "ro.config.knox=v30\n" + "ro.config.tima=1\n" + "ro.config.timaversion=3.0\n" + "ro.config.iccc_version=1.0\n" + "ro.kernel.qemu=0\n" + "net.bt.name=Android\n" + "dalvik.vm.stack-trace-file=/data/anr/traces.txt\n" + "ro.build.version.sem=2402\n" + "ro.build.version.sep=80000\n" + "ro.expect.recovery_id=0x3febbe7420c506f45403ac14bdc221ea9ca7838d000000000000000000000000\n" + "\n", }, { .path = "/sys/devices/soc0/family", @@ -335,39 +333,38 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpufreq/all_time_in_state", .size = 1182, - .content = - "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\t\n" - "442000\t\t0\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\t\n" - "546000\t\t0\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\t\n" - "650000\t\t0\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\t\n" - "728000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t26\t\t26\t\t\n" - "754000\t\t1293\t\t1293\t\t1293\t\t1293\t\tN/A\t\tN/A\t\t\n" - "832000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\t0\t\t\n" - "858000\t\t38\t\t38\t\t38\t\t38\t\tN/A\t\tN/A\t\t\n" - "936000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\t0\t\t\n" - "962000\t\t29\t\t29\t\t29\t\t29\t\tN/A\t\tN/A\t\t\n" - "1040000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\t0\t\t\n" - "1066000\t\t53\t\t53\t\t53\t\t53\t\tN/A\t\tN/A\t\t\n" - "1144000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\t0\t\t\n" - "1170000\t\t66\t\t66\t\t66\t\t66\t\tN/A\t\tN/A\t\t\n" - "1248000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\t0\t\t\n" - "1274000\t\t13\t\t13\t\t13\t\t13\t\tN/A\t\tN/A\t\t\n" - "1352000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\t0\t\t\n" - "1378000\t\t24\t\t24\t\t24\t\t24\t\tN/A\t\tN/A\t\t\n" - "1456000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\t0\t\t\n" - "1482000\t\t8\t\t8\t\t8\t\t8\t\tN/A\t\tN/A\t\t\n" - "1560000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\t0\t\t\n" - "1586000\t\t3974\t\t3974\t\t3974\t\t3974\t\tN/A\t\tN/A\t\t\n" - "1664000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\t0\t\t\n" - "1768000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t29\t\t29\t\t\n" - "1872000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t1426\t\t1426\t\t\n" - "1976000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t29\t\t29\t\t\n" - "2080000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t13\t\t13\t\t\n" - "2184000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t4\t\t4\t\t\n" - "2288000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t3965\t\t3965\t\t\n" - "2392000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\t0\t\t\n" - "2496000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\t0\t\t\n" - "2600000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t6\t\t6\t\t\n", + .content = "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\t\n" + "442000\t\t0\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\t\n" + "546000\t\t0\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\t\n" + "650000\t\t0\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\t\n" + "728000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t26\t\t26\t\t\n" + "754000\t\t1293\t\t1293\t\t1293\t\t1293\t\tN/A\t\tN/A\t\t\n" + "832000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\t0\t\t\n" + "858000\t\t38\t\t38\t\t38\t\t38\t\tN/A\t\tN/A\t\t\n" + "936000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\t0\t\t\n" + "962000\t\t29\t\t29\t\t29\t\t29\t\tN/A\t\tN/A\t\t\n" + "1040000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\t0\t\t\n" + "1066000\t\t53\t\t53\t\t53\t\t53\t\tN/A\t\tN/A\t\t\n" + "1144000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\t0\t\t\n" + "1170000\t\t66\t\t66\t\t66\t\t66\t\tN/A\t\tN/A\t\t\n" + "1248000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\t0\t\t\n" + "1274000\t\t13\t\t13\t\t13\t\t13\t\tN/A\t\tN/A\t\t\n" + "1352000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\t0\t\t\n" + "1378000\t\t24\t\t24\t\t24\t\t24\t\tN/A\t\tN/A\t\t\n" + "1456000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\t0\t\t\n" + "1482000\t\t8\t\t8\t\t8\t\t8\t\tN/A\t\tN/A\t\t\n" + "1560000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\t0\t\t\n" + "1586000\t\t3974\t\t3974\t\t3974\t\t3974\t\tN/A\t\tN/A\t\t\n" + "1664000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\t0\t\t\n" + "1768000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t29\t\t29\t\t\n" + "1872000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t1426\t\t1426\t\t\n" + "1976000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t29\t\t29\t\t\n" + "2080000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t13\t\t13\t\t\n" + "2184000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t4\t\t4\t\t\n" + "2288000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t3965\t\t3965\t\t\n" + "2392000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\t0\t\t\n" + "2496000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\t0\t\t\n" + "2600000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t6\t\t6\t\t\n", }, { .path = "/sys/devices/system/cpu/cpufreq/current_in_state", @@ -446,19 +443,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 126, - .content = - "1586000 3974\n" - "1482000 8\n" - "1378000 32\n" - "1274000 13\n" - "1170000 69\n" - "1066000 53\n" - "962000 29\n" - "858000 40\n" - "754000 1416\n" - "650000 0\n" - "546000 0\n" - "442000 0\n", + .content = "1586000 3974\n" + "1482000 8\n" + "1378000 32\n" + "1274000 13\n" + "1170000 69\n" + "1066000 53\n" + "962000 29\n" + "858000 40\n" + "754000 1416\n" + "650000 0\n" + "546000 0\n" + "442000 0\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -553,19 +549,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 126, - .content = - "1586000 3974\n" - "1482000 8\n" - "1378000 36\n" - "1274000 13\n" - "1170000 71\n" - "1066000 53\n" - "962000 29\n" - "858000 42\n" - "754000 1645\n" - "650000 0\n" - "546000 0\n" - "442000 0\n", + .content = "1586000 3974\n" + "1482000 8\n" + "1378000 36\n" + "1274000 13\n" + "1170000 71\n" + "1066000 53\n" + "962000 29\n" + "858000 42\n" + "754000 1645\n" + "650000 0\n" + "546000 0\n" + "442000 0\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -660,19 +655,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 126, - .content = - "1586000 3974\n" - "1482000 8\n" - "1378000 36\n" - "1274000 13\n" - "1170000 71\n" - "1066000 53\n" - "962000 29\n" - "858000 42\n" - "754000 1885\n" - "650000 0\n" - "546000 0\n" - "442000 0\n", + .content = "1586000 3974\n" + "1482000 8\n" + "1378000 36\n" + "1274000 13\n" + "1170000 71\n" + "1066000 53\n" + "962000 29\n" + "858000 42\n" + "754000 1885\n" + "650000 0\n" + "546000 0\n" + "442000 0\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -767,19 +761,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 128, - .content = - "1586000 3974\n" - "1482000 8\n" - "1378000 36\n" - "1274000 13\n" - "1170000 71\n" - "1066000 53\n" - "962000 29\n" - "858000 42\n" - "754000 2047\n" - "650000 0\n" - "546000 0\n" - "442000 110\n", + .content = "1586000 3974\n" + "1482000 8\n" + "1378000 36\n" + "1274000 13\n" + "1170000 71\n" + "1066000 53\n" + "962000 29\n" + "858000 42\n" + "754000 2047\n" + "650000 0\n" + "546000 0\n" + "442000 110\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -879,26 +872,25 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/time_in_state", .size = 201, - .content = - "2600000 24\n" - "2496000 0\n" - "2392000 3\n" - "2288000 3965\n" - "2184000 4\n" - "2080000 16\n" - "1976000 29\n" - "1872000 2204\n" - "1768000 29\n" - "1664000 3\n" - "1560000 0\n" - "1456000 14\n" - "1352000 0\n" - "1248000 29\n" - "1144000 0\n" - "1040000 0\n" - "936000 0\n" - "832000 6\n" - "728000 350\n", + .content = "2600000 24\n" + "2496000 0\n" + "2392000 3\n" + "2288000 3965\n" + "2184000 4\n" + "2080000 16\n" + "1976000 29\n" + "1872000 2204\n" + "1768000 29\n" + "1664000 3\n" + "1560000 0\n" + "1456000 14\n" + "1352000 0\n" + "1248000 29\n" + "1144000 0\n" + "1040000 0\n" + "936000 0\n" + "832000 6\n" + "728000 350\n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/total_trans", @@ -998,26 +990,25 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/time_in_state", .size = 202, - .content = - "2600000 74\n" - "2496000 0\n" - "2392000 8\n" - "2288000 3970\n" - "2184000 4\n" - "2080000 16\n" - "1976000 29\n" - "1872000 2204\n" - "1768000 29\n" - "1664000 9\n" - "1560000 0\n" - "1456000 18\n" - "1352000 5\n" - "1248000 29\n" - "1144000 0\n" - "1040000 0\n" - "936000 80\n" - "832000 6\n" - "728000 479\n", + .content = "2600000 74\n" + "2496000 0\n" + "2392000 8\n" + "2288000 3970\n" + "2184000 4\n" + "2080000 16\n" + "1976000 29\n" + "1872000 2204\n" + "1768000 29\n" + "1664000 9\n" + "1560000 0\n" + "1456000 18\n" + "1352000 5\n" + "1248000 29\n" + "1144000 0\n" + "1040000 0\n" + "936000 80\n" + "832000 6\n" + "728000 479\n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/total_trans", @@ -1054,7 +1045,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "5\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -2910,6 +2901,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.wfd.status", .value = "disconnected", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/galaxy-s7-us.cc b/test/mock/galaxy-s7-us.cc index b05c25ce..f09b6a44 100644 --- a/test/mock/galaxy-s7-us.cc +++ b/test/mock/galaxy-s7-us.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(4, cpuinfo_get_processors_count()); @@ -290,8 +289,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Qualcomm MSM8996", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Qualcomm MSM8996", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -333,59 +334,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -510,8 +511,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -562,8 +565,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -621,8 +626,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/galaxy-s7-us.h b/test/mock/galaxy-s7-us.h index f4a1a8c6..6203e582 100644 --- a/test/mock/galaxy-s7-us.h +++ b/test/mock/galaxy-s7-us.h @@ -3,45 +3,44 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 906, - .content = - "processor\t: 0\n" - "model name\t: AArch64 Processor rev 2 (aarch64)\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x1\n" - "CPU part\t: 0x211\n" - "CPU revision\t: 2\n" - "\n" - "processor\t: 1\n" - "model name\t: AArch64 Processor rev 2 (aarch64)\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x1\n" - "CPU part\t: 0x211\n" - "CPU revision\t: 2\n" - "\n" - "processor\t: 2\n" - "model name\t: AArch64 Processor rev 2 (aarch64)\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x1\n" - "CPU part\t: 0x205\n" - "CPU revision\t: 2\n" - "\n" - "processor\t: 3\n" - "model name\t: AArch64 Processor rev 2 (aarch64)\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x1\n" - "CPU part\t: 0x205\n" - "CPU revision\t: 2\n" - "\n" - "Hardware\t: Qualcomm Technologies, Inc MSM8996\n" - "Revision\t: 000f\n", + .content = "processor\t: 0\n" + "model name\t: AArch64 Processor rev 2 (aarch64)\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0x211\n" + "CPU revision\t: 2\n" + "\n" + "processor\t: 1\n" + "model name\t: AArch64 Processor rev 2 (aarch64)\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0x211\n" + "CPU revision\t: 2\n" + "\n" + "processor\t: 2\n" + "model name\t: AArch64 Processor rev 2 (aarch64)\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0x205\n" + "CPU revision\t: 2\n" + "\n" + "processor\t: 3\n" + "model name\t: AArch64 Processor rev 2 (aarch64)\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0x205\n" + "CPU revision\t: 2\n" + "\n" + "Hardware\t: Qualcomm Technologies, Inc MSM8996\n" + "Revision\t: 000f\n", }, #elif CPUINFO_ARCH_ARM { @@ -460,7 +459,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/class/kgsl/kgsl-3d0/devfreq/available_governors", .size = 176, - .content = "spdm_bw_hyp cache_hwmon mem_latency bw_hwmon msm-vidc-vmem+ msm-vidc-vmem msm-vidc-ddr bw_vbif gpubw_mon msm-adreno-tz cpufreq userspace powersave performance simple_ondemand\r\n", + .content = + "spdm_bw_hyp cache_hwmon mem_latency bw_hwmon msm-vidc-vmem+ msm-vidc-vmem msm-vidc-ddr bw_vbif gpubw_mon msm-adreno-tz cpufreq userspace powersave performance simple_ondemand\r\n", }, { .path = "/sys/class/kgsl/kgsl-3d0/devfreq/cur_freq", @@ -495,17 +495,16 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/class/kgsl/kgsl-3d0/devfreq/trans_stat", .size = 679, - .content = - " From : To\r\n" - " :624000000560000000510000000401800000315000000214000000133000000 time(ms)\r\n" - " 624000000: 0 1 0 0 0 0 0 90\r\n" - " 560000000: 0 0 1 0 0 0 0 230\r\n" - " 510000000: 0 0 0 1 0 0 0 150\r\n" - " 401800000: 0 0 0 0 1 0 0 100\r\n" - " 315000000: 0 0 0 0 0 3 0 2420\r\n" - "*214000000: 1 0 0 0 1 0 3 52360\r\n" - " 133000000: 0 0 0 0 1 2 0 3450\r\n" - "Total transition : 15\r\n", + .content = " From : To\r\n" + " :624000000560000000510000000401800000315000000214000000133000000 time(ms)\r\n" + " 624000000: 0 1 0 0 0 0 0 90\r\n" + " 560000000: 0 0 1 0 0 0 0 230\r\n" + " 510000000: 0 0 0 1 0 0 0 150\r\n" + " 401800000: 0 0 0 0 1 0 0 100\r\n" + " 315000000: 0 0 0 0 0 3 0 2420\r\n" + "*214000000: 1 0 0 0 1 0 3 52360\r\n" + " 133000000: 0 0 0 0 1 2 0 3450\r\n" + "Total transition : 15\r\n", }, { .path = "/sys/class/kgsl/kgsl-3d0/ft_fast_hang_detect", @@ -640,71 +639,67 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/soc0/image_crm_version", .size = 5, - .content = - "REL\n" - "\n", + .content = "REL\n" + "\n", }, { .path = "/sys/devices/soc0/image_variant", .size = 17, - .content = - "heroqlteuc-user\n" - "\n", + .content = "heroqlteuc-user\n" + "\n", }, { .path = "/sys/devices/soc0/image_version", .size = 25, - .content = - "10:MMB29M:G930AUCS4APK1\n" - "\n", + .content = "10:MMB29M:G930AUCS4APK1\n" + "\n", }, { .path = "/sys/devices/soc0/images", .size = 611, - .content = - "0:\n" - "\tCRM:\t\t00:BOOT.XF.1.0.C1-00023\n" - "\tVariant:\tM8996LAB\n" - "\tVersion:\tSWHC3505\n" - "\n" - "1:\n" - "\tCRM:\t\t01:TZ.BF.2.0.T200053.2\n" - "\tVariant:\t\n" - "\tVersion:\tOEM VERSION GOES IN THESE BYTES.\n" - "\n" - "3:\n" - "\tCRM:\t\t03:RPM.BF.1.6.C3-00004\n" - "\tVariant:\tAAAAANAAR\n" - "\tVersion:\tSWHC3505\n" - "\n" - "10:\n" - "\tCRM:\t\t10:MMB29M:G930AUCS4APK1\n" - "\n" - "\tVariant:\theroqlteuc-user\n" - "\n" - "\tVersion:\tREL\n" - "\n" - "\n" - "11:\n" - "\tCRM:\t\t11:MPSS.TH.2.0.C2.1-00021\n" - "\tVariant:\t8996.gen.prodQ\n" - "\tVersion:\tSWDB4606\n" - "\n" - "12:\n" - "\tCRM:\t\t12:ADSP.8996.2.7.C1-00026\n" - "\tVariant:\tAAAAAAAAQ\n" - "\tVersion:\tSWDB4606\n" - "\n" - "14:\n" - "\tCRM:\t\t14:VIDEO.VE.4.0-00109\n" - "\tVariant:\tPROD\n" - "\tVersion:\t:CRM\n" - "\n" - "15:\n" - "\tCRM:\t\t15:SLPI.HB.1.0.C1-49586\n" - "\tVariant:\tAAAAAAAAQ\n" - "\tVersion:\tSWHC3505\n" - "\n", + .content = "0:\n" + "\tCRM:\t\t00:BOOT.XF.1.0.C1-00023\n" + "\tVariant:\tM8996LAB\n" + "\tVersion:\tSWHC3505\n" + "\n" + "1:\n" + "\tCRM:\t\t01:TZ.BF.2.0.T200053.2\n" + "\tVariant:\t\n" + "\tVersion:\tOEM VERSION GOES IN THESE BYTES.\n" + "\n" + "3:\n" + "\tCRM:\t\t03:RPM.BF.1.6.C3-00004\n" + "\tVariant:\tAAAAANAAR\n" + "\tVersion:\tSWHC3505\n" + "\n" + "10:\n" + "\tCRM:\t\t10:MMB29M:G930AUCS4APK1\n" + "\n" + "\tVariant:\theroqlteuc-user\n" + "\n" + "\tVersion:\tREL\n" + "\n" + "\n" + "11:\n" + "\tCRM:\t\t11:MPSS.TH.2.0.C2.1-00021\n" + "\tVariant:\t8996.gen.prodQ\n" + "\tVersion:\tSWDB4606\n" + "\n" + "12:\n" + "\tCRM:\t\t12:ADSP.8996.2.7.C1-00026\n" + "\tVariant:\tAAAAAAAAQ\n" + "\tVersion:\tSWDB4606\n" + "\n" + "14:\n" + "\tCRM:\t\t14:VIDEO.VE.4.0-00109\n" + "\tVariant:\tPROD\n" + "\tVersion:\t:CRM\n" + "\n" + "15:\n" + "\tCRM:\t\t15:SLPI.HB.1.0.C1-49586\n" + "\tVariant:\tAAAAAAAAQ\n" + "\tVersion:\tSWHC3505\n" + "\n", }, { .path = "/sys/devices/soc0/machine", @@ -876,7 +871,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies", .size = 121, - .content = "307200 422400 480000 556800 652800 729600 844800 960000 1036800 1113600 1190400 1228800 1324800 1401600 1478400 1593600 \n", + .content = + "307200 422400 480000 556800 652800 729600 844800 960000 1036800 1113600 1190400 1228800 1324800 1401600 1478400 1593600 \n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors", @@ -906,23 +902,22 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 163, - .content = - "307200 2\n" - "422400 1\n" - "480000 0\n" - "556800 3\n" - "652800 2\n" - "729600 1\n" - "844800 2\n" - "960000 67\n" - "1036800 37\n" - "1113600 1836\n" - "1190400 4\n" - "1228800 9\n" - "1324800 21\n" - "1401600 14\n" - "1478400 19\n" - "1593600 4340\n", + .content = "307200 2\n" + "422400 1\n" + "480000 0\n" + "556800 3\n" + "652800 2\n" + "729600 1\n" + "844800 2\n" + "960000 67\n" + "1036800 37\n" + "1113600 1836\n" + "1190400 4\n" + "1228800 9\n" + "1324800 21\n" + "1401600 14\n" + "1478400 19\n" + "1593600 4340\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -992,7 +987,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_frequencies", .size = 121, - .content = "307200 422400 480000 556800 652800 729600 844800 960000 1036800 1113600 1190400 1228800 1324800 1401600 1478400 1593600 \n", + .content = + "307200 422400 480000 556800 652800 729600 844800 960000 1036800 1113600 1190400 1228800 1324800 1401600 1478400 1593600 \n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_governors", @@ -1022,23 +1018,22 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 163, - .content = - "307200 2\n" - "422400 1\n" - "480000 0\n" - "556800 3\n" - "652800 2\n" - "729600 1\n" - "844800 2\n" - "960000 67\n" - "1036800 37\n" - "1113600 1836\n" - "1190400 5\n" - "1228800 9\n" - "1324800 23\n" - "1401600 14\n" - "1478400 19\n" - "1593600 4606\n", + .content = "307200 2\n" + "422400 1\n" + "480000 0\n" + "556800 3\n" + "652800 2\n" + "729600 1\n" + "844800 2\n" + "960000 67\n" + "1036800 37\n" + "1113600 1836\n" + "1190400 5\n" + "1228800 9\n" + "1324800 23\n" + "1401600 14\n" + "1478400 19\n" + "1593600 4606\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -1108,7 +1103,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_frequencies", .size = 192, - .content = "307200 403200 480000 556800 652800 729600 806400 883200 940800 1036800 1113600 1190400 1248000 1324800 1401600 1478400 1555200 1632000 1708800 1785600 1824000 1920000 1996800 2073600 2150400 \n", + .content = + "307200 403200 480000 556800 652800 729600 806400 883200 940800 1036800 1113600 1190400 1248000 1324800 1401600 1478400 1555200 1632000 1708800 1785600 1824000 1920000 1996800 2073600 2150400 \n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_governors", @@ -1143,32 +1139,31 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 248, - .content = - "307200 0\n" - "403200 0\n" - "480000 0\n" - "556800 1\n" - "652800 0\n" - "729600 2\n" - "806400 1\n" - "883200 0\n" - "940800 2\n" - "1036800 2\n" - "1113600 1905\n" - "1190400 0\n" - "1248000 11\n" - "1324800 2\n" - "1401600 1\n" - "1478400 7\n" - "1555200 1\n" - "1632000 4\n" - "1708800 0\n" - "1785600 0\n" - "1824000 2\n" - "1920000 1\n" - "1996800 6\n" - "2073600 6\n" - "2150400 4953\n", + .content = "307200 0\n" + "403200 0\n" + "480000 0\n" + "556800 1\n" + "652800 0\n" + "729600 2\n" + "806400 1\n" + "883200 0\n" + "940800 2\n" + "1036800 2\n" + "1113600 1905\n" + "1190400 0\n" + "1248000 11\n" + "1324800 2\n" + "1401600 1\n" + "1478400 7\n" + "1555200 1\n" + "1632000 4\n" + "1708800 0\n" + "1785600 0\n" + "1824000 2\n" + "1920000 1\n" + "1996800 6\n" + "2073600 6\n" + "2150400 4953\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -1238,7 +1233,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_frequencies", .size = 192, - .content = "307200 403200 480000 556800 652800 729600 806400 883200 940800 1036800 1113600 1190400 1248000 1324800 1401600 1478400 1555200 1632000 1708800 1785600 1824000 1920000 1996800 2073600 2150400 \n", + .content = + "307200 403200 480000 556800 652800 729600 806400 883200 940800 1036800 1113600 1190400 1248000 1324800 1401600 1478400 1555200 1632000 1708800 1785600 1824000 1920000 1996800 2073600 2150400 \n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_governors", @@ -1273,32 +1269,31 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 248, - .content = - "307200 0\n" - "403200 0\n" - "480000 0\n" - "556800 1\n" - "652800 0\n" - "729600 2\n" - "806400 1\n" - "883200 0\n" - "940800 2\n" - "1036800 2\n" - "1113600 1905\n" - "1190400 0\n" - "1248000 11\n" - "1324800 2\n" - "1401600 1\n" - "1478400 7\n" - "1555200 1\n" - "1632000 4\n" - "1708800 0\n" - "1785600 0\n" - "1824000 2\n" - "1920000 1\n" - "1996800 7\n" - "2073600 6\n" - "2150400 5224\n", + .content = "307200 0\n" + "403200 0\n" + "480000 0\n" + "556800 1\n" + "652800 0\n" + "729600 2\n" + "806400 1\n" + "883200 0\n" + "940800 2\n" + "1036800 2\n" + "1113600 1905\n" + "1190400 0\n" + "1248000 11\n" + "1324800 2\n" + "1401600 1\n" + "1478400 7\n" + "1555200 1\n" + "1632000 4\n" + "1708800 0\n" + "1785600 0\n" + "1824000 2\n" + "1920000 1\n" + "1996800 7\n" + "2073600 6\n" + "2150400 5224\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -1335,7 +1330,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "3\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -3751,6 +3746,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.wfd.status", .value = "disconnected", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/galaxy-s8-global.cc b/test/mock/galaxy-s8-global.cc index 30a2826e..d1b677ef 100644 --- a/test/mock/galaxy-s8-global.cc +++ b/test/mock/galaxy-s8-global.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(8, cpuinfo_get_processors_count()); @@ -354,8 +353,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Samsung Exynos 8895", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Samsung Exynos 8895", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -397,59 +398,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -600,8 +601,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -678,8 +681,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -737,8 +742,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/galaxy-s8-global.h b/test/mock/galaxy-s8-global.h index c55f8093..924b0725 100644 --- a/test/mock/galaxy-s8-global.h +++ b/test/mock/galaxy-s8-global.h @@ -3,79 +3,78 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 1448, - .content = - "processor\t: 0\n" - "BogoMIPS\t: 52.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 1\n" - "BogoMIPS\t: 52.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 2\n" - "BogoMIPS\t: 52.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 3\n" - "BogoMIPS\t: 52.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 4\n" - "BogoMIPS\t: 52.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x53\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x4\n" - "CPU part\t: 0x001\n" - "CPU revision\t: 0\n" - "\n" - "processor\t: 5\n" - "BogoMIPS\t: 52.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x53\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x4\n" - "CPU part\t: 0x001\n" - "CPU revision\t: 0\n" - "\n" - "processor\t: 6\n" - "BogoMIPS\t: 52.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x53\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x4\n" - "CPU part\t: 0x001\n" - "CPU revision\t: 0\n" - "\n" - "processor\t: 7\n" - "BogoMIPS\t: 52.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x53\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x4\n" - "CPU part\t: 0x001\n" - "CPU revision\t: 0\n" - "\n", + .content = "processor\t: 0\n" + "BogoMIPS\t: 52.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 1\n" + "BogoMIPS\t: 52.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 2\n" + "BogoMIPS\t: 52.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 3\n" + "BogoMIPS\t: 52.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 4\n" + "BogoMIPS\t: 52.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x53\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x4\n" + "CPU part\t: 0x001\n" + "CPU revision\t: 0\n" + "\n" + "processor\t: 5\n" + "BogoMIPS\t: 52.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x53\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x4\n" + "CPU part\t: 0x001\n" + "CPU revision\t: 0\n" + "\n" + "processor\t: 6\n" + "BogoMIPS\t: 52.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x53\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x4\n" + "CPU part\t: 0x001\n" + "CPU revision\t: 0\n" + "\n" + "processor\t: 7\n" + "BogoMIPS\t: 52.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x53\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x4\n" + "CPU part\t: 0x001\n" + "CPU revision\t: 0\n" + "\n", }, #elif CPUINFO_ARCH_ARM { @@ -479,16 +478,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 101, - .content = - "1690000 6834\n" - "1456000 427\n" - "1248000 277\n" - "1053000 102\n" - "949000 117\n" - "832000 75\n" - "715000 64\n" - "598000 83\n" - "455000 257\n", + .content = "1690000 6834\n" + "1456000 427\n" + "1248000 277\n" + "1053000 102\n" + "949000 117\n" + "832000 75\n" + "715000 64\n" + "598000 83\n" + "455000 257\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -583,16 +581,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 101, - .content = - "1690000 6861\n" - "1456000 471\n" - "1248000 298\n" - "1053000 105\n" - "949000 141\n" - "832000 75\n" - "715000 69\n" - "598000 91\n" - "455000 391\n", + .content = "1690000 6861\n" + "1456000 471\n" + "1248000 298\n" + "1053000 105\n" + "949000 141\n" + "832000 75\n" + "715000 69\n" + "598000 91\n" + "455000 391\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -687,16 +684,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 101, - .content = - "1690000 6861\n" - "1456000 471\n" - "1248000 298\n" - "1053000 105\n" - "949000 150\n" - "832000 75\n" - "715000 71\n" - "598000 95\n" - "455000 647\n", + .content = "1690000 6861\n" + "1456000 471\n" + "1248000 298\n" + "1053000 105\n" + "949000 150\n" + "832000 75\n" + "715000 71\n" + "598000 95\n" + "455000 647\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -791,16 +787,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 102, - .content = - "1690000 6951\n" - "1456000 538\n" - "1248000 301\n" - "1053000 105\n" - "949000 154\n" - "832000 78\n" - "715000 108\n" - "598000 95\n" - "455000 666\n", + .content = "1690000 6951\n" + "1456000 538\n" + "1248000 301\n" + "1053000 105\n" + "949000 154\n" + "832000 78\n" + "715000 108\n" + "598000 95\n" + "455000 666\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -900,20 +895,19 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/time_in_state", .size = 147, - .content = - "2314000 5088\n" - "2158000 62\n" - "2002000 22\n" - "1937000 62\n" - "1807000 120\n" - "1703000 78\n" - "1469000 143\n" - "1261000 691\n" - "1170000 28\n" - "1066000 57\n" - "962000 28\n" - "858000 77\n" - "741000 2792\n", + .content = "2314000 5088\n" + "2158000 62\n" + "2002000 22\n" + "1937000 62\n" + "1807000 120\n" + "1703000 78\n" + "1469000 143\n" + "1261000 691\n" + "1170000 28\n" + "1066000 57\n" + "962000 28\n" + "858000 77\n" + "741000 2792\n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/total_trans", @@ -1013,20 +1007,19 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/time_in_state", .size = 148, - .content = - "2314000 5088\n" - "2158000 68\n" - "2002000 22\n" - "1937000 64\n" - "1807000 127\n" - "1703000 100\n" - "1469000 165\n" - "1261000 750\n" - "1170000 28\n" - "1066000 57\n" - "962000 28\n" - "858000 85\n" - "741000 2932\n", + .content = "2314000 5088\n" + "2158000 68\n" + "2002000 22\n" + "1937000 64\n" + "1807000 127\n" + "1703000 100\n" + "1469000 165\n" + "1261000 750\n" + "1170000 28\n" + "1066000 57\n" + "962000 28\n" + "858000 85\n" + "741000 2932\n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/total_trans", @@ -1126,20 +1119,19 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/time_in_state", .size = 148, - .content = - "2314000 5140\n" - "2158000 73\n" - "2002000 22\n" - "1937000 68\n" - "1807000 128\n" - "1703000 108\n" - "1469000 193\n" - "1261000 824\n" - "1170000 28\n" - "1066000 68\n" - "962000 28\n" - "858000 92\n" - "741000 3016\n", + .content = "2314000 5140\n" + "2158000 73\n" + "2002000 22\n" + "1937000 68\n" + "1807000 128\n" + "1703000 108\n" + "1469000 193\n" + "1261000 824\n" + "1170000 28\n" + "1066000 68\n" + "962000 28\n" + "858000 92\n" + "741000 3016\n", }, { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/total_trans", @@ -1239,20 +1231,19 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/time_in_state", .size = 149, - .content = - "2314000 5140\n" - "2158000 73\n" - "2002000 22\n" - "1937000 68\n" - "1807000 128\n" - "1703000 122\n" - "1469000 220\n" - "1261000 904\n" - "1170000 28\n" - "1066000 70\n" - "962000 36\n" - "858000 108\n" - "741000 3112\n", + .content = "2314000 5140\n" + "2158000 73\n" + "2002000 22\n" + "1937000 68\n" + "1807000 128\n" + "1703000 122\n" + "1469000 220\n" + "1261000 904\n" + "1170000 28\n" + "1066000 70\n" + "962000 36\n" + "858000 108\n" + "741000 3112\n", }, { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/total_trans", @@ -1289,7 +1280,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "7\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -3433,6 +3424,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.wfd.status", .value = "disconnected", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/galaxy-s8-us.cc b/test/mock/galaxy-s8-us.cc index 6c9282b7..13021f80 100644 --- a/test/mock/galaxy-s8-us.cc +++ b/test/mock/galaxy-s8-us.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(8, cpuinfo_get_processors_count()); @@ -334,8 +333,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Qualcomm MSM8998", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Qualcomm MSM8998", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -377,59 +378,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -580,8 +581,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -658,8 +661,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -717,8 +722,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/galaxy-s8-us.h b/test/mock/galaxy-s8-us.h index b2ea973d..9b818efd 100644 --- a/test/mock/galaxy-s8-us.h +++ b/test/mock/galaxy-s8-us.h @@ -3,81 +3,80 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 1540, - .content = - "Processor\t: AArch64 Processor rev 4 (aarch64)\n" - "processor\t: 0\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0xa\n" - "CPU part\t: 0x801\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 1\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0xa\n" - "CPU part\t: 0x801\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 2\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0xa\n" - "CPU part\t: 0x801\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 3\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0xa\n" - "CPU part\t: 0x801\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 4\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0xa\n" - "CPU part\t: 0x800\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 5\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0xa\n" - "CPU part\t: 0x800\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 6\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0xa\n" - "CPU part\t: 0x800\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 7\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0xa\n" - "CPU part\t: 0x800\n" - "CPU revision\t: 1\n" - "\n" - "Hardware\t: Qualcomm Technologies, Inc MSM8998\n", + .content = "Processor\t: AArch64 Processor rev 4 (aarch64)\n" + "processor\t: 0\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0xa\n" + "CPU part\t: 0x801\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 1\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0xa\n" + "CPU part\t: 0x801\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 2\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0xa\n" + "CPU part\t: 0x801\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 3\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0xa\n" + "CPU part\t: 0x801\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 4\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0xa\n" + "CPU part\t: 0x800\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 5\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0xa\n" + "CPU part\t: 0x800\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 6\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0xa\n" + "CPU part\t: 0x800\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 7\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0xa\n" + "CPU part\t: 0x800\n" + "CPU revision\t: 1\n" + "\n" + "Hardware\t: Qualcomm Technologies, Inc MSM8998\n", }, #elif CPUINFO_ARCH_ARM { @@ -519,7 +518,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/class/kgsl/kgsl-3d0/devfreq/available_governors", .size = 163, - .content = "spdm_bw_hyp mem_latency bw_hwmon msm-vidc-vmem+ msm-vidc-vmem msm-vidc-ddr bw_vbif gpubw_mon cpufreq msm-adreno-tz userspace powersave performance simple_ondemand\n", + .content = + "spdm_bw_hyp mem_latency bw_hwmon msm-vidc-vmem+ msm-vidc-vmem msm-vidc-ddr bw_vbif gpubw_mon cpufreq msm-adreno-tz userspace powersave performance simple_ondemand\n", }, { .path = "/sys/class/kgsl/kgsl-3d0/devfreq/cur_freq", @@ -564,16 +564,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/class/kgsl/kgsl-3d0/devfreq/trans_stat", .size = 533, - .content = - " From : To\n" - " :670000000596000000515000000414000000342000000257000000 time(ms)\n" - " 670000000: 0 2 0 0 0 0 750\n" - " 596000000: 0 0 2 0 0 0 180\n" - " 515000000: 0 0 0 0 0 2 980\n" - " 414000000: 0 0 0 0 0 0 0\n" - " 342000000: 0 0 0 0 0 0 0\n" - "*257000000: 2 0 0 0 0 0 8001780\n" - "Total transition : 8\n", + .content = " From : To\n" + " :670000000596000000515000000414000000342000000257000000 time(ms)\n" + " 670000000: 0 2 0 0 0 0 750\n" + " 596000000: 0 0 2 0 0 0 180\n" + " 515000000: 0 0 0 0 0 2 980\n" + " 414000000: 0 0 0 0 0 0 0\n" + " 342000000: 0 0 0 0 0 0 0\n" + "*257000000: 2 0 0 0 0 0 8001780\n" + "Total transition : 8\n", }, { .path = "/sys/class/kgsl/kgsl-3d0/freq_table_mhz", @@ -753,63 +752,59 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/soc0/image_crm_version", .size = 5, - .content = - "REL\n" - "\n", + .content = "REL\n" + "\n", }, { .path = "/sys/devices/soc0/image_variant", .size = 18, - .content = - "dreamqltesq-user\n" - "\n", + .content = "dreamqltesq-user\n" + "\n", }, { .path = "/sys/devices/soc0/image_version", .size = 25, - .content = - "10:NRD90M:G950USQU1AQC9\n" - "\n", + .content = "10:NRD90M:G950USQU1AQC9\n" + "\n", }, { .path = "/sys/devices/soc0/images", .size = 613, - .content = - "0:\n" - "\tCRM:\t\t00:BOOT.XF.1.2-00322\n" - "\tVariant:\tMsm8998LA\n" - "\tVersion:\t:SWHE7721\n" - "1:\n" - "\tCRM:\t\t01:TZ.BF.4.0.6.C1-00028\n" - "\tVariant:\t \n" - "\tVersion:\t:CRM\n" - "3:\n" - "\tCRM:\t\t03:RPM.BF.1.7.C2-00007\n" - "\tVariant:\tAAAAANAZR\n" - "\tVersion:\t:SWHE7721\n" - "10:\n" - "\tCRM:\t\t10:NRD90M:G950USQU1AQC9\n" - "\n" - "\tVariant:\tdreamqltesq-user\n" - "\n" - "\tVersion:\tREL\n" - "\n" - "11:\n" - "\tCRM:\t\t11:MPSS.AT.2.0.C2.2-87307\n" - "\tVariant:\t8998.gen.prodQ\n" - "\tVersion:\t:SWDG4503-VM02\n" - "12:\n" - "\tCRM:\t\t12:ADSP.HT.3.0.c2-00032-CB8998-1\n" - "\tVariant:\tAAAAAAAAQ\n" - "\tVersion:\t:SWDG4503-VM02\n" - "14:\n" - "\tCRM:\t\t14:VIDEO.VE.4.2-00046\n" - "\tVariant:\tPROD\n" - "\tVersion:\t\n" - "15:\n" - "\tCRM:\t\t15:SLPI.HB.2.0.c2-00009-M8998AZL-1.88149.3\n" - "\tVariant:\tAAAAAAAAQ\n" - "\tVersion:\t:SWHE7721\n", + .content = "0:\n" + "\tCRM:\t\t00:BOOT.XF.1.2-00322\n" + "\tVariant:\tMsm8998LA\n" + "\tVersion:\t:SWHE7721\n" + "1:\n" + "\tCRM:\t\t01:TZ.BF.4.0.6.C1-00028\n" + "\tVariant:\t \n" + "\tVersion:\t:CRM\n" + "3:\n" + "\tCRM:\t\t03:RPM.BF.1.7.C2-00007\n" + "\tVariant:\tAAAAANAZR\n" + "\tVersion:\t:SWHE7721\n" + "10:\n" + "\tCRM:\t\t10:NRD90M:G950USQU1AQC9\n" + "\n" + "\tVariant:\tdreamqltesq-user\n" + "\n" + "\tVersion:\tREL\n" + "\n" + "11:\n" + "\tCRM:\t\t11:MPSS.AT.2.0.C2.2-87307\n" + "\tVariant:\t8998.gen.prodQ\n" + "\tVersion:\t:SWDG4503-VM02\n" + "12:\n" + "\tCRM:\t\t12:ADSP.HT.3.0.c2-00032-CB8998-1\n" + "\tVariant:\tAAAAAAAAQ\n" + "\tVersion:\t:SWDG4503-VM02\n" + "14:\n" + "\tCRM:\t\t14:VIDEO.VE.4.2-00046\n" + "\tVariant:\tPROD\n" + "\tVersion:\t\n" + "15:\n" + "\tCRM:\t\t15:SLPI.HB.2.0.c2-00009-M8998AZL-1.88149.3\n" + "\tVariant:\tAAAAAAAAQ\n" + "\tVersion:\t:SWHE7721\n", }, { .path = "/sys/devices/soc0/machine", @@ -939,95 +934,94 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/core_ctl/global_state", .size = 1008, - .content = - "CPU0\n" - "\tCPU: 0\n" - "\tOnline: 1\n" - "\tActive: 1\n" - "\tFirst CPU: 0\n" - "\tBusy%: 1\n" - "\tIs busy: 1\n" - "\tNr running: 0\n" - "\tActive CPUs: 4\n" - "\tNeed CPUs: 4\n" - "\tBoost: 0\n" - "CPU1\n" - "\tCPU: 1\n" - "\tOnline: 1\n" - "\tActive: 1\n" - "\tFirst CPU: 0\n" - "\tBusy%: 0\n" - "\tIs busy: 1\n" - "\tNr running: 0\n" - "\tActive CPUs: 4\n" - "\tNeed CPUs: 4\n" - "\tBoost: 0\n" - "CPU2\n" - "\tCPU: 2\n" - "\tOnline: 1\n" - "\tActive: 1\n" - "\tFirst CPU: 0\n" - "\tBusy%: 0\n" - "\tIs busy: 1\n" - "\tNr running: 0\n" - "\tActive CPUs: 4\n" - "\tNeed CPUs: 4\n" - "\tBoost: 0\n" - "CPU3\n" - "\tCPU: 3\n" - "\tOnline: 1\n" - "\tActive: 1\n" - "\tFirst CPU: 0\n" - "\tBusy%: 0\n" - "\tIs busy: 1\n" - "\tNr running: 0\n" - "\tActive CPUs: 4\n" - "\tNeed CPUs: 4\n" - "\tBoost: 0\n" - "CPU4\n" - "\tCPU: 4\n" - "\tOnline: 1\n" - "\tActive: 1\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "\tNr running: 0\n" - "\tActive CPUs: 2\n" - "\tNeed CPUs: 2\n" - "\tBoost: 0\n" - "CPU5\n" - "\tCPU: 5\n" - "\tOnline: 1\n" - "\tActive: 0\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "\tNr running: 0\n" - "\tActive CPUs: 2\n" - "\tNeed CPUs: 2\n" - "\tBoost: 0\n" - "CPU6\n" - "\tCPU: 6\n" - "\tOnline: 1\n" - "\tActive: 1\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "\tNr running: 0\n" - "\tActive CPUs: 2\n" - "\tNeed CPUs: 2\n" - "\tBoost: 0\n" - "CPU7\n" - "\tCPU: 7\n" - "\tOnline: 1\n" - "\tActive: 0\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "\tNr running: 0\n" - "\tActive CPUs: 2\n" - "\tNeed CPUs: 2\n" - "\tBoost: 0\n", + .content = "CPU0\n" + "\tCPU: 0\n" + "\tOnline: 1\n" + "\tActive: 1\n" + "\tFirst CPU: 0\n" + "\tBusy%: 1\n" + "\tIs busy: 1\n" + "\tNr running: 0\n" + "\tActive CPUs: 4\n" + "\tNeed CPUs: 4\n" + "\tBoost: 0\n" + "CPU1\n" + "\tCPU: 1\n" + "\tOnline: 1\n" + "\tActive: 1\n" + "\tFirst CPU: 0\n" + "\tBusy%: 0\n" + "\tIs busy: 1\n" + "\tNr running: 0\n" + "\tActive CPUs: 4\n" + "\tNeed CPUs: 4\n" + "\tBoost: 0\n" + "CPU2\n" + "\tCPU: 2\n" + "\tOnline: 1\n" + "\tActive: 1\n" + "\tFirst CPU: 0\n" + "\tBusy%: 0\n" + "\tIs busy: 1\n" + "\tNr running: 0\n" + "\tActive CPUs: 4\n" + "\tNeed CPUs: 4\n" + "\tBoost: 0\n" + "CPU3\n" + "\tCPU: 3\n" + "\tOnline: 1\n" + "\tActive: 1\n" + "\tFirst CPU: 0\n" + "\tBusy%: 0\n" + "\tIs busy: 1\n" + "\tNr running: 0\n" + "\tActive CPUs: 4\n" + "\tNeed CPUs: 4\n" + "\tBoost: 0\n" + "CPU4\n" + "\tCPU: 4\n" + "\tOnline: 1\n" + "\tActive: 1\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "\tNr running: 0\n" + "\tActive CPUs: 2\n" + "\tNeed CPUs: 2\n" + "\tBoost: 0\n" + "CPU5\n" + "\tCPU: 5\n" + "\tOnline: 1\n" + "\tActive: 0\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "\tNr running: 0\n" + "\tActive CPUs: 2\n" + "\tNeed CPUs: 2\n" + "\tBoost: 0\n" + "CPU6\n" + "\tCPU: 6\n" + "\tOnline: 1\n" + "\tActive: 1\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "\tNr running: 0\n" + "\tActive CPUs: 2\n" + "\tNeed CPUs: 2\n" + "\tBoost: 0\n" + "CPU7\n" + "\tCPU: 7\n" + "\tOnline: 1\n" + "\tActive: 0\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "\tNr running: 0\n" + "\tActive CPUs: 2\n" + "\tNeed CPUs: 2\n" + "\tBoost: 0\n", }, { .path = "/sys/devices/system/cpu/cpu0/core_ctl/is_big_cluster", @@ -1052,11 +1046,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/core_ctl/not_preferred", .size = 36, - .content = - "\tCPU:0 0\n" - "\tCPU:1 0\n" - "\tCPU:2 0\n" - "\tCPU:3 0\n", + .content = "\tCPU:0 0\n" + "\tCPU:1 0\n" + "\tCPU:2 0\n" + "\tCPU:3 0\n", }, { .path = "/sys/devices/system/cpu/cpu0/core_ctl/offline_delay_ms", @@ -1101,7 +1094,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies", .size = 167, - .content = "300000 364800 441600 518400 595200 672000 748800 825600 883200 960000 1036800 1094400 1171200 1248000 1324800 1401600 1478400 1555200 1670400 1747200 1824000 1900800 \n", + .content = + "300000 364800 441600 518400 595200 672000 748800 825600 883200 960000 1036800 1094400 1171200 1248000 1324800 1401600 1478400 1555200 1670400 1747200 1824000 1900800 \n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors", @@ -1136,29 +1130,28 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 282, - .content = - "300000 592725\n" - "364800 11362\n" - "441600 3149\n" - "518400 2763\n" - "595200 2209\n" - "672000 1661\n" - "748800 1772\n" - "825600 1916\n" - "883200 1551\n" - "960000 2374\n" - "1036800 2238\n" - "1094400 1659\n" - "1171200 41468\n" - "1248000 13041\n" - "1324800 1904\n" - "1401600 4057\n" - "1478400 2750\n" - "1555200 1331\n" - "1670400 2015\n" - "1747200 3649\n" - "1824000 6966\n" - "1900800 98490\n", + .content = "300000 592725\n" + "364800 11362\n" + "441600 3149\n" + "518400 2763\n" + "595200 2209\n" + "672000 1661\n" + "748800 1772\n" + "825600 1916\n" + "883200 1551\n" + "960000 2374\n" + "1036800 2238\n" + "1094400 1659\n" + "1171200 41468\n" + "1248000 13041\n" + "1324800 1904\n" + "1401600 4057\n" + "1478400 2750\n" + "1555200 1331\n" + "1670400 2015\n" + "1747200 3649\n" + "1824000 6966\n" + "1900800 98490\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -1378,7 +1371,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_frequencies", .size = 167, - .content = "300000 364800 441600 518400 595200 672000 748800 825600 883200 960000 1036800 1094400 1171200 1248000 1324800 1401600 1478400 1555200 1670400 1747200 1824000 1900800 \n", + .content = + "300000 364800 441600 518400 595200 672000 748800 825600 883200 960000 1036800 1094400 1171200 1248000 1324800 1401600 1478400 1555200 1670400 1747200 1824000 1900800 \n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_governors", @@ -1413,29 +1407,28 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 282, - .content = - "300000 593150\n" - "364800 11370\n" - "441600 3153\n" - "518400 2765\n" - "595200 2209\n" - "672000 1661\n" - "748800 1776\n" - "825600 1918\n" - "883200 1551\n" - "960000 2374\n" - "1036800 2238\n" - "1094400 1659\n" - "1171200 41492\n" - "1248000 13041\n" - "1324800 1906\n" - "1401600 4059\n" - "1478400 2750\n" - "1555200 1331\n" - "1670400 2015\n" - "1747200 3651\n" - "1824000 6970\n" - "1900800 98497\n", + .content = "300000 593150\n" + "364800 11370\n" + "441600 3153\n" + "518400 2765\n" + "595200 2209\n" + "672000 1661\n" + "748800 1776\n" + "825600 1918\n" + "883200 1551\n" + "960000 2374\n" + "1036800 2238\n" + "1094400 1659\n" + "1171200 41492\n" + "1248000 13041\n" + "1324800 1906\n" + "1401600 4059\n" + "1478400 2750\n" + "1555200 1331\n" + "1670400 2015\n" + "1747200 3651\n" + "1824000 6970\n" + "1900800 98497\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -1480,7 +1473,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_frequencies", .size = 167, - .content = "300000 364800 441600 518400 595200 672000 748800 825600 883200 960000 1036800 1094400 1171200 1248000 1324800 1401600 1478400 1555200 1670400 1747200 1824000 1900800 \n", + .content = + "300000 364800 441600 518400 595200 672000 748800 825600 883200 960000 1036800 1094400 1171200 1248000 1324800 1401600 1478400 1555200 1670400 1747200 1824000 1900800 \n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_governors", @@ -1515,29 +1509,28 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 282, - .content = - "300000 593536\n" - "364800 11384\n" - "441600 3159\n" - "518400 2767\n" - "595200 2211\n" - "672000 1661\n" - "748800 1780\n" - "825600 1918\n" - "883200 1551\n" - "960000 2374\n" - "1036800 2238\n" - "1094400 1659\n" - "1171200 41506\n" - "1248000 13041\n" - "1324800 1906\n" - "1401600 4059\n" - "1478400 2750\n" - "1555200 1331\n" - "1670400 2015\n" - "1747200 3651\n" - "1824000 6970\n" - "1900800 98497\n", + .content = "300000 593536\n" + "364800 11384\n" + "441600 3159\n" + "518400 2767\n" + "595200 2211\n" + "672000 1661\n" + "748800 1780\n" + "825600 1918\n" + "883200 1551\n" + "960000 2374\n" + "1036800 2238\n" + "1094400 1659\n" + "1171200 41506\n" + "1248000 13041\n" + "1324800 1906\n" + "1401600 4059\n" + "1478400 2750\n" + "1555200 1331\n" + "1670400 2015\n" + "1747200 3651\n" + "1824000 6970\n" + "1900800 98497\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -1582,7 +1575,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_frequencies", .size = 167, - .content = "300000 364800 441600 518400 595200 672000 748800 825600 883200 960000 1036800 1094400 1171200 1248000 1324800 1401600 1478400 1555200 1670400 1747200 1824000 1900800 \n", + .content = + "300000 364800 441600 518400 595200 672000 748800 825600 883200 960000 1036800 1094400 1171200 1248000 1324800 1401600 1478400 1555200 1670400 1747200 1824000 1900800 \n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_governors", @@ -1617,29 +1611,28 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 282, - .content = - "300000 593868\n" - "364800 11386\n" - "441600 3165\n" - "518400 2777\n" - "595200 2213\n" - "672000 1665\n" - "748800 1788\n" - "825600 1922\n" - "883200 1555\n" - "960000 2376\n" - "1036800 2242\n" - "1094400 1661\n" - "1171200 41542\n" - "1248000 13045\n" - "1324800 1906\n" - "1401600 4065\n" - "1478400 2752\n" - "1555200 1331\n" - "1670400 2015\n" - "1747200 3653\n" - "1824000 6972\n" - "1900800 98497\n", + .content = "300000 593868\n" + "364800 11386\n" + "441600 3165\n" + "518400 2777\n" + "595200 2213\n" + "672000 1665\n" + "748800 1788\n" + "825600 1922\n" + "883200 1555\n" + "960000 2376\n" + "1036800 2242\n" + "1094400 1661\n" + "1171200 41542\n" + "1248000 13045\n" + "1324800 1906\n" + "1401600 4065\n" + "1478400 2752\n" + "1555200 1331\n" + "1670400 2015\n" + "1747200 3653\n" + "1824000 6972\n" + "1900800 98497\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -1669,95 +1662,94 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/core_ctl/global_state", .size = 1008, - .content = - "CPU0\n" - "\tCPU: 0\n" - "\tOnline: 1\n" - "\tActive: 1\n" - "\tFirst CPU: 0\n" - "\tBusy%: 2\n" - "\tIs busy: 1\n" - "\tNr running: 0\n" - "\tActive CPUs: 4\n" - "\tNeed CPUs: 4\n" - "\tBoost: 0\n" - "CPU1\n" - "\tCPU: 1\n" - "\tOnline: 1\n" - "\tActive: 1\n" - "\tFirst CPU: 0\n" - "\tBusy%: 0\n" - "\tIs busy: 1\n" - "\tNr running: 0\n" - "\tActive CPUs: 4\n" - "\tNeed CPUs: 4\n" - "\tBoost: 0\n" - "CPU2\n" - "\tCPU: 2\n" - "\tOnline: 1\n" - "\tActive: 1\n" - "\tFirst CPU: 0\n" - "\tBusy%: 0\n" - "\tIs busy: 1\n" - "\tNr running: 0\n" - "\tActive CPUs: 4\n" - "\tNeed CPUs: 4\n" - "\tBoost: 0\n" - "CPU3\n" - "\tCPU: 3\n" - "\tOnline: 1\n" - "\tActive: 1\n" - "\tFirst CPU: 0\n" - "\tBusy%: 0\n" - "\tIs busy: 1\n" - "\tNr running: 0\n" - "\tActive CPUs: 4\n" - "\tNeed CPUs: 4\n" - "\tBoost: 0\n" - "CPU4\n" - "\tCPU: 4\n" - "\tOnline: 1\n" - "\tActive: 1\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "\tNr running: 0\n" - "\tActive CPUs: 2\n" - "\tNeed CPUs: 2\n" - "\tBoost: 0\n" - "CPU5\n" - "\tCPU: 5\n" - "\tOnline: 1\n" - "\tActive: 0\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "\tNr running: 0\n" - "\tActive CPUs: 2\n" - "\tNeed CPUs: 2\n" - "\tBoost: 0\n" - "CPU6\n" - "\tCPU: 6\n" - "\tOnline: 1\n" - "\tActive: 1\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "\tNr running: 0\n" - "\tActive CPUs: 2\n" - "\tNeed CPUs: 2\n" - "\tBoost: 0\n" - "CPU7\n" - "\tCPU: 7\n" - "\tOnline: 1\n" - "\tActive: 0\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "\tNr running: 0\n" - "\tActive CPUs: 2\n" - "\tNeed CPUs: 2\n" - "\tBoost: 0\n", + .content = "CPU0\n" + "\tCPU: 0\n" + "\tOnline: 1\n" + "\tActive: 1\n" + "\tFirst CPU: 0\n" + "\tBusy%: 2\n" + "\tIs busy: 1\n" + "\tNr running: 0\n" + "\tActive CPUs: 4\n" + "\tNeed CPUs: 4\n" + "\tBoost: 0\n" + "CPU1\n" + "\tCPU: 1\n" + "\tOnline: 1\n" + "\tActive: 1\n" + "\tFirst CPU: 0\n" + "\tBusy%: 0\n" + "\tIs busy: 1\n" + "\tNr running: 0\n" + "\tActive CPUs: 4\n" + "\tNeed CPUs: 4\n" + "\tBoost: 0\n" + "CPU2\n" + "\tCPU: 2\n" + "\tOnline: 1\n" + "\tActive: 1\n" + "\tFirst CPU: 0\n" + "\tBusy%: 0\n" + "\tIs busy: 1\n" + "\tNr running: 0\n" + "\tActive CPUs: 4\n" + "\tNeed CPUs: 4\n" + "\tBoost: 0\n" + "CPU3\n" + "\tCPU: 3\n" + "\tOnline: 1\n" + "\tActive: 1\n" + "\tFirst CPU: 0\n" + "\tBusy%: 0\n" + "\tIs busy: 1\n" + "\tNr running: 0\n" + "\tActive CPUs: 4\n" + "\tNeed CPUs: 4\n" + "\tBoost: 0\n" + "CPU4\n" + "\tCPU: 4\n" + "\tOnline: 1\n" + "\tActive: 1\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "\tNr running: 0\n" + "\tActive CPUs: 2\n" + "\tNeed CPUs: 2\n" + "\tBoost: 0\n" + "CPU5\n" + "\tCPU: 5\n" + "\tOnline: 1\n" + "\tActive: 0\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "\tNr running: 0\n" + "\tActive CPUs: 2\n" + "\tNeed CPUs: 2\n" + "\tBoost: 0\n" + "CPU6\n" + "\tCPU: 6\n" + "\tOnline: 1\n" + "\tActive: 1\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "\tNr running: 0\n" + "\tActive CPUs: 2\n" + "\tNeed CPUs: 2\n" + "\tBoost: 0\n" + "CPU7\n" + "\tCPU: 7\n" + "\tOnline: 1\n" + "\tActive: 0\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "\tNr running: 0\n" + "\tActive CPUs: 2\n" + "\tNeed CPUs: 2\n" + "\tBoost: 0\n", }, { .path = "/sys/devices/system/cpu/cpu4/core_ctl/is_big_cluster", @@ -1782,11 +1774,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/core_ctl/not_preferred", .size = 36, - .content = - "\tCPU:4 0\n" - "\tCPU:6 0\n" - "\tCPU:5 0\n" - "\tCPU:7 0\n", + .content = "\tCPU:4 0\n" + "\tCPU:6 0\n" + "\tCPU:5 0\n" + "\tCPU:7 0\n", }, { .path = "/sys/devices/system/cpu/cpu4/core_ctl/offline_delay_ms", @@ -1831,7 +1822,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_available_frequencies", .size = 231, - .content = "300000 345600 422400 499200 576000 652800 729600 806400 902400 979200 1056000 1132800 1190400 1267200 1344000 1420800 1497600 1574400 1651200 1728000 1804800 1881600 1958400 2035200 2112000 2208000 2265600 2323200 2342400 2361600 \n", + .content = + "300000 345600 422400 499200 576000 652800 729600 806400 902400 979200 1056000 1132800 1190400 1267200 1344000 1420800 1497600 1574400 1651200 1728000 1804800 1881600 1958400 2035200 2112000 2208000 2265600 2323200 2342400 2361600 \n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_available_governors", @@ -1866,37 +1858,36 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/time_in_state", .size = 351, - .content = - "300000 38889\n" - "345600 23\n" - "422400 41\n" - "499200 26\n" - "576000 67\n" - "652800 73\n" - "729600 59\n" - "806400 46\n" - "902400 742666\n" - "979200 310\n" - "1056000 593\n" - "1132800 249\n" - "1190400 181\n" - "1267200 202\n" - "1344000 242\n" - "1420800 276\n" - "1497600 1249\n" - "1574400 4755\n" - "1651200 572\n" - "1728000 458\n" - "1804800 320\n" - "1881600 369\n" - "1958400 1012\n" - "2035200 689\n" - "2112000 775\n" - "2208000 365\n" - "2265600 204\n" - "2323200 106\n" - "2342400 45\n" - "2361600 7956\n", + .content = "300000 38889\n" + "345600 23\n" + "422400 41\n" + "499200 26\n" + "576000 67\n" + "652800 73\n" + "729600 59\n" + "806400 46\n" + "902400 742666\n" + "979200 310\n" + "1056000 593\n" + "1132800 249\n" + "1190400 181\n" + "1267200 202\n" + "1344000 242\n" + "1420800 276\n" + "1497600 1249\n" + "1574400 4755\n" + "1651200 572\n" + "1728000 458\n" + "1804800 320\n" + "1881600 369\n" + "1958400 1012\n" + "2035200 689\n" + "2112000 775\n" + "2208000 365\n" + "2265600 204\n" + "2323200 106\n" + "2342400 45\n" + "2361600 7956\n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/total_trans", @@ -1941,7 +1932,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_available_frequencies", .size = 231, - .content = "300000 345600 422400 499200 576000 652800 729600 806400 902400 979200 1056000 1132800 1190400 1267200 1344000 1420800 1497600 1574400 1651200 1728000 1804800 1881600 1958400 2035200 2112000 2208000 2265600 2323200 2342400 2361600 \n", + .content = + "300000 345600 422400 499200 576000 652800 729600 806400 902400 979200 1056000 1132800 1190400 1267200 1344000 1420800 1497600 1574400 1651200 1728000 1804800 1881600 1958400 2035200 2112000 2208000 2265600 2323200 2342400 2361600 \n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_available_governors", @@ -1976,37 +1968,36 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/time_in_state", .size = 351, - .content = - "300000 38889\n" - "345600 23\n" - "422400 41\n" - "499200 26\n" - "576000 67\n" - "652800 73\n" - "729600 59\n" - "806400 46\n" - "902400 743103\n" - "979200 310\n" - "1056000 593\n" - "1132800 249\n" - "1190400 181\n" - "1267200 202\n" - "1344000 242\n" - "1420800 276\n" - "1497600 1249\n" - "1574400 4755\n" - "1651200 572\n" - "1728000 458\n" - "1804800 320\n" - "1881600 369\n" - "1958400 1012\n" - "2035200 689\n" - "2112000 775\n" - "2208000 365\n" - "2265600 204\n" - "2323200 106\n" - "2342400 45\n" - "2361600 7956\n", + .content = "300000 38889\n" + "345600 23\n" + "422400 41\n" + "499200 26\n" + "576000 67\n" + "652800 73\n" + "729600 59\n" + "806400 46\n" + "902400 743103\n" + "979200 310\n" + "1056000 593\n" + "1132800 249\n" + "1190400 181\n" + "1267200 202\n" + "1344000 242\n" + "1420800 276\n" + "1497600 1249\n" + "1574400 4755\n" + "1651200 572\n" + "1728000 458\n" + "1804800 320\n" + "1881600 369\n" + "1958400 1012\n" + "2035200 689\n" + "2112000 775\n" + "2208000 365\n" + "2265600 204\n" + "2323200 106\n" + "2342400 45\n" + "2361600 7956\n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/total_trans", @@ -2051,7 +2042,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_available_frequencies", .size = 231, - .content = "300000 345600 422400 499200 576000 652800 729600 806400 902400 979200 1056000 1132800 1190400 1267200 1344000 1420800 1497600 1574400 1651200 1728000 1804800 1881600 1958400 2035200 2112000 2208000 2265600 2323200 2342400 2361600 \n", + .content = + "300000 345600 422400 499200 576000 652800 729600 806400 902400 979200 1056000 1132800 1190400 1267200 1344000 1420800 1497600 1574400 1651200 1728000 1804800 1881600 1958400 2035200 2112000 2208000 2265600 2323200 2342400 2361600 \n", }, { .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_available_governors", @@ -2086,37 +2078,36 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/time_in_state", .size = 351, - .content = - "300000 38889\n" - "345600 23\n" - "422400 41\n" - "499200 26\n" - "576000 67\n" - "652800 73\n" - "729600 59\n" - "806400 46\n" - "902400 743514\n" - "979200 310\n" - "1056000 593\n" - "1132800 249\n" - "1190400 181\n" - "1267200 204\n" - "1344000 244\n" - "1420800 276\n" - "1497600 1249\n" - "1574400 4757\n" - "1651200 572\n" - "1728000 458\n" - "1804800 320\n" - "1881600 369\n" - "1958400 1012\n" - "2035200 689\n" - "2112000 775\n" - "2208000 365\n" - "2265600 204\n" - "2323200 106\n" - "2342400 45\n" - "2361600 7956\n", + .content = "300000 38889\n" + "345600 23\n" + "422400 41\n" + "499200 26\n" + "576000 67\n" + "652800 73\n" + "729600 59\n" + "806400 46\n" + "902400 743514\n" + "979200 310\n" + "1056000 593\n" + "1132800 249\n" + "1190400 181\n" + "1267200 204\n" + "1344000 244\n" + "1420800 276\n" + "1497600 1249\n" + "1574400 4757\n" + "1651200 572\n" + "1728000 458\n" + "1804800 320\n" + "1881600 369\n" + "1958400 1012\n" + "2035200 689\n" + "2112000 775\n" + "2208000 365\n" + "2265600 204\n" + "2323200 106\n" + "2342400 45\n" + "2361600 7956\n", }, { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/total_trans", @@ -2161,7 +2152,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_available_frequencies", .size = 231, - .content = "300000 345600 422400 499200 576000 652800 729600 806400 902400 979200 1056000 1132800 1190400 1267200 1344000 1420800 1497600 1574400 1651200 1728000 1804800 1881600 1958400 2035200 2112000 2208000 2265600 2323200 2342400 2361600 \n", + .content = + "300000 345600 422400 499200 576000 652800 729600 806400 902400 979200 1056000 1132800 1190400 1267200 1344000 1420800 1497600 1574400 1651200 1728000 1804800 1881600 1958400 2035200 2112000 2208000 2265600 2323200 2342400 2361600 \n", }, { .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_available_governors", @@ -2196,37 +2188,36 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/time_in_state", .size = 351, - .content = - "300000 38889\n" - "345600 23\n" - "422400 41\n" - "499200 26\n" - "576000 67\n" - "652800 73\n" - "729600 59\n" - "806400 46\n" - "902400 743938\n" - "979200 310\n" - "1056000 593\n" - "1132800 249\n" - "1190400 181\n" - "1267200 204\n" - "1344000 244\n" - "1420800 276\n" - "1497600 1249\n" - "1574400 4757\n" - "1651200 572\n" - "1728000 458\n" - "1804800 320\n" - "1881600 369\n" - "1958400 1012\n" - "2035200 689\n" - "2112000 775\n" - "2208000 365\n" - "2265600 204\n" - "2323200 106\n" - "2342400 45\n" - "2361600 7956\n", + .content = "300000 38889\n" + "345600 23\n" + "422400 41\n" + "499200 26\n" + "576000 67\n" + "652800 73\n" + "729600 59\n" + "806400 46\n" + "902400 743938\n" + "979200 310\n" + "1056000 593\n" + "1132800 249\n" + "1190400 181\n" + "1267200 204\n" + "1344000 244\n" + "1420800 276\n" + "1497600 1249\n" + "1574400 4757\n" + "1651200 572\n" + "1728000 458\n" + "1804800 320\n" + "1881600 369\n" + "1958400 1012\n" + "2035200 689\n" + "2112000 775\n" + "2208000 365\n" + "2265600 204\n" + "2323200 106\n" + "2342400 45\n" + "2361600 7956\n", }, { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/total_trans", @@ -2238,7 +2229,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "1\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -4942,6 +4933,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.wfd.status", .value = "disconnected", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/galaxy-s9-global.cc b/test/mock/galaxy-s9-global.cc index 6c725133..1a636f51 100644 --- a/test/mock/galaxy-s9-global.cc +++ b/test/mock/galaxy-s9-global.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(8, cpuinfo_get_processors_count()); @@ -367,8 +366,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Samsung Exynos 9810", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Samsung Exynos 9810", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -410,59 +411,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -518,11 +519,11 @@ TEST(ISA, neon_fma) { } TEST(ISA, atomics) { - #if CPUINFO_ARCH_ARM - ASSERT_FALSE(cpuinfo_has_arm_atomics()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_TRUE(cpuinfo_has_arm_atomics()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_FALSE(cpuinfo_has_arm_atomics()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_TRUE(cpuinfo_has_arm_atomics()); +#endif } TEST(ISA, neon_rdm) { @@ -604,8 +605,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -695,8 +698,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -747,8 +752,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } @@ -814,8 +821,10 @@ TEST(L3, associativity) { TEST(L3, sets) { for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l3_cache(i)->size, - cpuinfo_get_l3_cache(i)->sets * cpuinfo_get_l3_cache(i)->line_size * cpuinfo_get_l3_cache(i)->partitions * cpuinfo_get_l3_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l3_cache(i)->size, + cpuinfo_get_l3_cache(i)->sets * cpuinfo_get_l3_cache(i)->line_size * + cpuinfo_get_l3_cache(i)->partitions * cpuinfo_get_l3_cache(i)->associativity); } } diff --git a/test/mock/galaxy-s9-global.h b/test/mock/galaxy-s9-global.h index 99b247b9..eccc6f32 100644 --- a/test/mock/galaxy-s9-global.h +++ b/test/mock/galaxy-s9-global.h @@ -3,79 +3,78 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 1616, - .content = - "processor\t: 0\n" - "BogoMIPS\t: 52.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd05\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 1\n" - "BogoMIPS\t: 52.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd05\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 2\n" - "BogoMIPS\t: 52.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd05\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 3\n" - "BogoMIPS\t: 52.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd05\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 4\n" - "BogoMIPS\t: 52.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" - "CPU implementer\t: 0x53\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x1\n" - "CPU part\t: 0x002\n" - "CPU revision\t: 0\n" - "\n" - "processor\t: 5\n" - "BogoMIPS\t: 52.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" - "CPU implementer\t: 0x53\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x1\n" - "CPU part\t: 0x002\n" - "CPU revision\t: 0\n" - "\n" - "processor\t: 6\n" - "BogoMIPS\t: 52.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" - "CPU implementer\t: 0x53\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x1\n" - "CPU part\t: 0x002\n" - "CPU revision\t: 0\n" - "\n" - "processor\t: 7\n" - "BogoMIPS\t: 52.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" - "CPU implementer\t: 0x53\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x1\n" - "CPU part\t: 0x002\n" - "CPU revision\t: 0\n" - "\n", + .content = "processor\t: 0\n" + "BogoMIPS\t: 52.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd05\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 1\n" + "BogoMIPS\t: 52.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd05\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 2\n" + "BogoMIPS\t: 52.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd05\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 3\n" + "BogoMIPS\t: 52.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd05\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 4\n" + "BogoMIPS\t: 52.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" + "CPU implementer\t: 0x53\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0x002\n" + "CPU revision\t: 0\n" + "\n" + "processor\t: 5\n" + "BogoMIPS\t: 52.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" + "CPU implementer\t: 0x53\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0x002\n" + "CPU revision\t: 0\n" + "\n" + "processor\t: 6\n" + "BogoMIPS\t: 52.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" + "CPU implementer\t: 0x53\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0x002\n" + "CPU revision\t: 0\n" + "\n" + "processor\t: 7\n" + "BogoMIPS\t: 52.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" + "CPU implementer\t: 0x53\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0x002\n" + "CPU revision\t: 0\n" + "\n", }, #elif CPUINFO_ARCH_ARM { @@ -277,17 +276,16 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 131, - .content = - "1794000 28706\n" - "1690000 2524\n" - "1456000 6223\n" - "1248000 3526\n" - "1053000 41990\n" - "949000 3768\n" - "832000 8121\n" - "715000 12524\n" - "598000 23493\n" - "455000 607015\n", + .content = "1794000 28706\n" + "1690000 2524\n" + "1456000 6223\n" + "1248000 3526\n" + "1053000 41990\n" + "949000 3768\n" + "832000 8121\n" + "715000 12524\n" + "598000 23493\n" + "455000 607015\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -402,17 +400,16 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 131, - .content = - "1794000 28706\n" - "1690000 2524\n" - "1456000 6255\n" - "1248000 3570\n" - "1053000 41990\n" - "949000 3768\n" - "832000 8121\n" - "715000 12525\n" - "598000 23510\n" - "455000 607190\n", + .content = "1794000 28706\n" + "1690000 2524\n" + "1456000 6255\n" + "1248000 3570\n" + "1053000 41990\n" + "949000 3768\n" + "832000 8121\n" + "715000 12525\n" + "598000 23510\n" + "455000 607190\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -527,17 +524,16 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 131, - .content = - "1794000 28706\n" - "1690000 2526\n" - "1456000 6285\n" - "1248000 3619\n" - "1053000 41997\n" - "949000 3770\n" - "832000 8122\n" - "715000 12529\n" - "598000 23533\n" - "455000 607355\n", + .content = "1794000 28706\n" + "1690000 2526\n" + "1456000 6285\n" + "1248000 3619\n" + "1053000 41997\n" + "949000 3770\n" + "832000 8122\n" + "715000 12529\n" + "598000 23533\n" + "455000 607355\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -652,17 +648,16 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 131, - .content = - "1794000 28706\n" - "1690000 2529\n" - "1456000 6307\n" - "1248000 3668\n" - "1053000 41998\n" - "949000 3770\n" - "832000 8122\n" - "715000 12534\n" - "598000 23559\n" - "455000 607541\n", + .content = "1794000 28706\n" + "1690000 2529\n" + "1456000 6307\n" + "1248000 3668\n" + "1053000 41998\n" + "949000 3770\n" + "832000 8122\n" + "715000 12534\n" + "598000 23559\n" + "455000 607541\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -742,7 +737,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_available_frequencies", .size = 141, - .content = "2704000 2652000 2496000 2314000 2106000 2002000 1924000 1794000 1690000 1586000 1469000 1261000 1170000 1066000 962000 858000 741000 650000 \n", + .content = + "2704000 2652000 2496000 2314000 2106000 2002000 1924000 1794000 1690000 1586000 1469000 1261000 1170000 1066000 962000 858000 741000 650000 \n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_available_governors", @@ -777,25 +773,24 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/time_in_state", .size = 224, - .content = - "2704000 8469\n" - "2652000 44\n" - "2496000 4623\n" - "2314000 1315\n" - "2106000 620\n" - "2002000 16\n" - "1924000 13\n" - "1794000 10070\n" - "1690000 465\n" - "1586000 1211\n" - "1469000 2430\n" - "1261000 676\n" - "1170000 677\n" - "1066000 1472\n" - "962000 1353\n" - "858000 3174\n" - "741000 41680\n" - "650000 660716\n", + .content = "2704000 8469\n" + "2652000 44\n" + "2496000 4623\n" + "2314000 1315\n" + "2106000 620\n" + "2002000 16\n" + "1924000 13\n" + "1794000 10070\n" + "1690000 465\n" + "1586000 1211\n" + "1469000 2430\n" + "1261000 676\n" + "1170000 677\n" + "1066000 1472\n" + "962000 1353\n" + "858000 3174\n" + "741000 41680\n" + "650000 660716\n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/total_trans", @@ -875,7 +870,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_available_frequencies", .size = 141, - .content = "2704000 2652000 2496000 2314000 2106000 2002000 1924000 1794000 1690000 1586000 1469000 1261000 1170000 1066000 962000 858000 741000 650000 \n", + .content = + "2704000 2652000 2496000 2314000 2106000 2002000 1924000 1794000 1690000 1586000 1469000 1261000 1170000 1066000 962000 858000 741000 650000 \n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_available_governors", @@ -910,25 +906,24 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/time_in_state", .size = 224, - .content = - "2704000 8469\n" - "2652000 44\n" - "2496000 4623\n" - "2314000 1315\n" - "2106000 620\n" - "2002000 16\n" - "1924000 13\n" - "1794000 10070\n" - "1690000 465\n" - "1586000 1211\n" - "1469000 2430\n" - "1261000 676\n" - "1170000 677\n" - "1066000 1472\n" - "962000 1353\n" - "858000 3174\n" - "741000 41680\n" - "650000 660975\n", + .content = "2704000 8469\n" + "2652000 44\n" + "2496000 4623\n" + "2314000 1315\n" + "2106000 620\n" + "2002000 16\n" + "1924000 13\n" + "1794000 10070\n" + "1690000 465\n" + "1586000 1211\n" + "1469000 2430\n" + "1261000 676\n" + "1170000 677\n" + "1066000 1472\n" + "962000 1353\n" + "858000 3174\n" + "741000 41680\n" + "650000 660975\n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/total_trans", @@ -1008,7 +1003,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_available_frequencies", .size = 141, - .content = "2704000 2652000 2496000 2314000 2106000 2002000 1924000 1794000 1690000 1586000 1469000 1261000 1170000 1066000 962000 858000 741000 650000 \n", + .content = + "2704000 2652000 2496000 2314000 2106000 2002000 1924000 1794000 1690000 1586000 1469000 1261000 1170000 1066000 962000 858000 741000 650000 \n", }, { .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_available_governors", @@ -1043,25 +1039,24 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/time_in_state", .size = 224, - .content = - "2704000 8469\n" - "2652000 44\n" - "2496000 4623\n" - "2314000 1315\n" - "2106000 620\n" - "2002000 16\n" - "1924000 13\n" - "1794000 10070\n" - "1690000 465\n" - "1586000 1211\n" - "1469000 2430\n" - "1261000 676\n" - "1170000 677\n" - "1066000 1472\n" - "962000 1353\n" - "858000 3174\n" - "741000 41680\n" - "650000 661245\n", + .content = "2704000 8469\n" + "2652000 44\n" + "2496000 4623\n" + "2314000 1315\n" + "2106000 620\n" + "2002000 16\n" + "1924000 13\n" + "1794000 10070\n" + "1690000 465\n" + "1586000 1211\n" + "1469000 2430\n" + "1261000 676\n" + "1170000 677\n" + "1066000 1472\n" + "962000 1353\n" + "858000 3174\n" + "741000 41680\n" + "650000 661245\n", }, { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/total_trans", @@ -1141,7 +1136,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_available_frequencies", .size = 141, - .content = "2704000 2652000 2496000 2314000 2106000 2002000 1924000 1794000 1690000 1586000 1469000 1261000 1170000 1066000 962000 858000 741000 650000 \n", + .content = + "2704000 2652000 2496000 2314000 2106000 2002000 1924000 1794000 1690000 1586000 1469000 1261000 1170000 1066000 962000 858000 741000 650000 \n", }, { .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_available_governors", @@ -1176,25 +1172,24 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/time_in_state", .size = 224, - .content = - "2704000 8469\n" - "2652000 44\n" - "2496000 4623\n" - "2314000 1315\n" - "2106000 620\n" - "2002000 16\n" - "1924000 13\n" - "1794000 10070\n" - "1690000 465\n" - "1586000 1211\n" - "1469000 2430\n" - "1261000 676\n" - "1170000 677\n" - "1066000 1472\n" - "962000 1353\n" - "858000 3174\n" - "741000 41681\n" - "650000 661544\n", + .content = "2704000 8469\n" + "2652000 44\n" + "2496000 4623\n" + "2314000 1315\n" + "2106000 620\n" + "2002000 16\n" + "1924000 13\n" + "1794000 10070\n" + "1690000 465\n" + "1586000 1211\n" + "1469000 2430\n" + "1261000 676\n" + "1170000 677\n" + "1066000 1472\n" + "962000 1353\n" + "858000 3174\n" + "741000 41681\n" + "650000 661544\n", }, { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/total_trans", @@ -1241,7 +1236,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "7\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -3605,6 +3600,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wifi.interface", .value = "wlan0", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/galaxy-s9-us.cc b/test/mock/galaxy-s9-us.cc index 91c48688..5d795623 100644 --- a/test/mock/galaxy-s9-us.cc +++ b/test/mock/galaxy-s9-us.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(8, cpuinfo_get_processors_count()); @@ -321,8 +320,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Qualcomm Snapdragon 845", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Qualcomm Snapdragon 845", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -364,59 +365,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -472,11 +473,11 @@ TEST(ISA, neon_fma) { } TEST(ISA, atomics) { - #if CPUINFO_ARCH_ARM - ASSERT_FALSE(cpuinfo_has_arm_atomics()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_TRUE(cpuinfo_has_arm_atomics()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_FALSE(cpuinfo_has_arm_atomics()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_TRUE(cpuinfo_has_arm_atomics()); +#endif } TEST(ISA, neon_rdm) { @@ -558,8 +559,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -636,8 +639,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -714,8 +719,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } @@ -766,8 +773,10 @@ TEST(L3, associativity) { TEST(L3, sets) { for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l3_cache(i)->size, - cpuinfo_get_l3_cache(i)->sets * cpuinfo_get_l3_cache(i)->line_size * cpuinfo_get_l3_cache(i)->partitions * cpuinfo_get_l3_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l3_cache(i)->size, + cpuinfo_get_l3_cache(i)->sets * cpuinfo_get_l3_cache(i)->line_size * + cpuinfo_get_l3_cache(i)->partitions * cpuinfo_get_l3_cache(i)->associativity); } } diff --git a/test/mock/galaxy-s9-us.h b/test/mock/galaxy-s9-us.h index 01417d98..147af441 100644 --- a/test/mock/galaxy-s9-us.h +++ b/test/mock/galaxy-s9-us.h @@ -3,81 +3,80 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 1716, - .content = - "Processor\t: AArch64 Processor rev 12 (aarch64)\n" - "processor\t: 0\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x7\n" - "CPU part\t: 0x803\n" - "CPU revision\t: 12\n" - "\n" - "processor\t: 1\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x7\n" - "CPU part\t: 0x803\n" - "CPU revision\t: 12\n" - "\n" - "processor\t: 2\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x7\n" - "CPU part\t: 0x803\n" - "CPU revision\t: 12\n" - "\n" - "processor\t: 3\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x7\n" - "CPU part\t: 0x803\n" - "CPU revision\t: 12\n" - "\n" - "processor\t: 4\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x6\n" - "CPU part\t: 0x802\n" - "CPU revision\t: 13\n" - "\n" - "processor\t: 5\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x6\n" - "CPU part\t: 0x802\n" - "CPU revision\t: 13\n" - "\n" - "processor\t: 6\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x6\n" - "CPU part\t: 0x802\n" - "CPU revision\t: 13\n" - "\n" - "processor\t: 7\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x6\n" - "CPU part\t: 0x802\n" - "CPU revision\t: 13\n" - "\n" - "Hardware\t: Qualcomm Technologies, Inc SDM845\n", + .content = "Processor\t: AArch64 Processor rev 12 (aarch64)\n" + "processor\t: 0\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x7\n" + "CPU part\t: 0x803\n" + "CPU revision\t: 12\n" + "\n" + "processor\t: 1\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x7\n" + "CPU part\t: 0x803\n" + "CPU revision\t: 12\n" + "\n" + "processor\t: 2\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x7\n" + "CPU part\t: 0x803\n" + "CPU revision\t: 12\n" + "\n" + "processor\t: 3\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x7\n" + "CPU part\t: 0x803\n" + "CPU revision\t: 12\n" + "\n" + "processor\t: 4\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x6\n" + "CPU part\t: 0x802\n" + "CPU revision\t: 13\n" + "\n" + "processor\t: 5\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x6\n" + "CPU part\t: 0x802\n" + "CPU revision\t: 13\n" + "\n" + "processor\t: 6\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x6\n" + "CPU part\t: 0x802\n" + "CPU revision\t: 13\n" + "\n" + "processor\t: 7\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x6\n" + "CPU part\t: 0x802\n" + "CPU revision\t: 13\n" + "\n" + "Hardware\t: Qualcomm Technologies, Inc SDM845\n", }, #elif CPUINFO_ARCH_ARM { @@ -401,71 +400,67 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/soc0/image_crm_version", .size = 5, - .content = - "REL\n" - "\n", + .content = "REL\n" + "\n", }, { .path = "/sys/devices/soc0/image_variant", .size = 17, - .content = - "starqltesq-user\n" - "\n", + .content = "starqltesq-user\n" + "\n", }, { .path = "/sys/devices/soc0/image_version", .size = 24, - .content = - "10:R16NW:G960USQU1ARB7\n" - "\n", + .content = "10:R16NW:G960USQU1ARB7\n" + "\n", }, { .path = "/sys/devices/soc0/images", .size = 698, - .content = - "0:\n" - "\tCRM:\t\t00:BOOT.XF.2.0-00340-SDM845LZB-1\n" - "\tVariant:\tSDM845LA\n" - "\tVersion:\tSWDG4715\n" - "\n" - "1:\n" - "\tCRM:\t\t01:TZ.XF.5.0.1-132629-63\n" - "\tVariant:\t \n" - "\tVersion:\tCRM\n" - "\n" - "10:\n" - "\tCRM:\t\t10:R16NW:G960USQU1ARB7\n" - "\n" - "\tVariant:\tstarqltesq-user\n" - "\n" - "\tVersion:\tREL\n" - "\n" - "\n" - "11:\n" - "\tCRM:\t\t11:MPSS.AT.4.0.c2.5-00045-SDM845_GEN_PACK-1.135721.1\n" - "\tVariant:\tsdm845.gen.prodQ\n" - "\tVersion:\tSWDG4510-VM01\n" - "\n" - "12:\n" - "\tCRM:\t\t12:ADSP.HT.4.0.c2-00006-SDM845-1\n" - "\tVariant:\t845.adsp.prodQ\n" - "\tVersion:\tSWDG4510-VM01\n" - "\n" - "14:\n" - "\tCRM:\t\t14:VIDEO.VE.5.0-00062-PROD-1536691\n" - "\tVariant:\tPROD\n" - "\tVersion:\t:HARV-MMUNDHRA\n" - "\n" - "15:\n" - "\tCRM:\t\t15:SLPI.HY.1.0-00272-SDM845AZL-1.129244.1\n" - "\tVariant:\tAAAAAAAAQ\n" - "\tVersion:\tSWDG4715\n" - "\n" - "16:\n" - "\tCRM:\t\t16:CDSP.HT.1.0-00428-SDM845-1\n" - "\tVariant:\t845.cdsp.prodQ\n" - "\tVersion:\tSWDG4715\n" - "\n", + .content = "0:\n" + "\tCRM:\t\t00:BOOT.XF.2.0-00340-SDM845LZB-1\n" + "\tVariant:\tSDM845LA\n" + "\tVersion:\tSWDG4715\n" + "\n" + "1:\n" + "\tCRM:\t\t01:TZ.XF.5.0.1-132629-63\n" + "\tVariant:\t \n" + "\tVersion:\tCRM\n" + "\n" + "10:\n" + "\tCRM:\t\t10:R16NW:G960USQU1ARB7\n" + "\n" + "\tVariant:\tstarqltesq-user\n" + "\n" + "\tVersion:\tREL\n" + "\n" + "\n" + "11:\n" + "\tCRM:\t\t11:MPSS.AT.4.0.c2.5-00045-SDM845_GEN_PACK-1.135721.1\n" + "\tVariant:\tsdm845.gen.prodQ\n" + "\tVersion:\tSWDG4510-VM01\n" + "\n" + "12:\n" + "\tCRM:\t\t12:ADSP.HT.4.0.c2-00006-SDM845-1\n" + "\tVariant:\t845.adsp.prodQ\n" + "\tVersion:\tSWDG4510-VM01\n" + "\n" + "14:\n" + "\tCRM:\t\t14:VIDEO.VE.5.0-00062-PROD-1536691\n" + "\tVariant:\tPROD\n" + "\tVersion:\t:HARV-MMUNDHRA\n" + "\n" + "15:\n" + "\tCRM:\t\t15:SLPI.HY.1.0-00272-SDM845AZL-1.129244.1\n" + "\tVariant:\tAAAAAAAAQ\n" + "\tVersion:\tSWDG4715\n" + "\n" + "16:\n" + "\tCRM:\t\t16:CDSP.HT.1.0-00428-SDM845-1\n" + "\tVariant:\t845.cdsp.prodQ\n" + "\tVersion:\tSWDG4715\n" + "\n", }, { .path = "/sys/devices/soc0/machine", @@ -695,111 +690,110 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/core_ctl/global_state", .size = 1340, - .content = - "CPU0\n" - "\tCPU: 0\n" - "\tOnline: 1\n" - "\tIsolated: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 30\n" - "\tIs busy: 1\n" - "\tNot preferred: 0\n" - "\tNr running: 6\n" - "\tActive CPUs: 4\n" - "\tNeed CPUs: 4\n" - "\tNr isolated CPUs: 0\n" - "\tBoost: 0\n" - "CPU1\n" - "\tCPU: 1\n" - "\tOnline: 1\n" - "\tIsolated: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 20\n" - "\tIs busy: 1\n" - "\tNot preferred: 0\n" - "\tNr running: 6\n" - "\tActive CPUs: 4\n" - "\tNeed CPUs: 4\n" - "\tNr isolated CPUs: 0\n" - "\tBoost: 0\n" - "CPU2\n" - "\tCPU: 2\n" - "\tOnline: 1\n" - "\tIsolated: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 22\n" - "\tIs busy: 1\n" - "\tNot preferred: 0\n" - "\tNr running: 6\n" - "\tActive CPUs: 4\n" - "\tNeed CPUs: 4\n" - "\tNr isolated CPUs: 0\n" - "\tBoost: 0\n" - "CPU3\n" - "\tCPU: 3\n" - "\tOnline: 1\n" - "\tIsolated: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 8\n" - "\tIs busy: 1\n" - "\tNot preferred: 0\n" - "\tNr running: 6\n" - "\tActive CPUs: 4\n" - "\tNeed CPUs: 4\n" - "\tNr isolated CPUs: 0\n" - "\tBoost: 0\n" - "CPU4\n" - "\tCPU: 4\n" - "\tOnline: 1\n" - "\tIsolated: 1\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "\tNot preferred: 0\n" - "\tNr running: 1\n" - "\tActive CPUs: 2\n" - "\tNeed CPUs: 2\n" - "\tNr isolated CPUs: 2\n" - "\tBoost: 0\n" - "CPU5\n" - "\tCPU: 5\n" - "\tOnline: 1\n" - "\tIsolated: 1\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "\tNot preferred: 0\n" - "\tNr running: 1\n" - "\tActive CPUs: 2\n" - "\tNeed CPUs: 2\n" - "\tNr isolated CPUs: 2\n" - "\tBoost: 0\n" - "CPU6\n" - "\tCPU: 6\n" - "\tOnline: 1\n" - "\tIsolated: 0\n" - "\tFirst CPU: 4\n" - "\tBusy%: 11\n" - "\tIs busy: 0\n" - "\tNot preferred: 0\n" - "\tNr running: 1\n" - "\tActive CPUs: 2\n" - "\tNeed CPUs: 2\n" - "\tNr isolated CPUs: 2\n" - "\tBoost: 0\n" - "CPU7\n" - "\tCPU: 7\n" - "\tOnline: 1\n" - "\tIsolated: 0\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "\tNot preferred: 0\n" - "\tNr running: 1\n" - "\tActive CPUs: 2\n" - "\tNeed CPUs: 2\n" - "\tNr isolated CPUs: 2\n" - "\tBoost: 0\n", + .content = "CPU0\n" + "\tCPU: 0\n" + "\tOnline: 1\n" + "\tIsolated: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 30\n" + "\tIs busy: 1\n" + "\tNot preferred: 0\n" + "\tNr running: 6\n" + "\tActive CPUs: 4\n" + "\tNeed CPUs: 4\n" + "\tNr isolated CPUs: 0\n" + "\tBoost: 0\n" + "CPU1\n" + "\tCPU: 1\n" + "\tOnline: 1\n" + "\tIsolated: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 20\n" + "\tIs busy: 1\n" + "\tNot preferred: 0\n" + "\tNr running: 6\n" + "\tActive CPUs: 4\n" + "\tNeed CPUs: 4\n" + "\tNr isolated CPUs: 0\n" + "\tBoost: 0\n" + "CPU2\n" + "\tCPU: 2\n" + "\tOnline: 1\n" + "\tIsolated: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 22\n" + "\tIs busy: 1\n" + "\tNot preferred: 0\n" + "\tNr running: 6\n" + "\tActive CPUs: 4\n" + "\tNeed CPUs: 4\n" + "\tNr isolated CPUs: 0\n" + "\tBoost: 0\n" + "CPU3\n" + "\tCPU: 3\n" + "\tOnline: 1\n" + "\tIsolated: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 8\n" + "\tIs busy: 1\n" + "\tNot preferred: 0\n" + "\tNr running: 6\n" + "\tActive CPUs: 4\n" + "\tNeed CPUs: 4\n" + "\tNr isolated CPUs: 0\n" + "\tBoost: 0\n" + "CPU4\n" + "\tCPU: 4\n" + "\tOnline: 1\n" + "\tIsolated: 1\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "\tNot preferred: 0\n" + "\tNr running: 1\n" + "\tActive CPUs: 2\n" + "\tNeed CPUs: 2\n" + "\tNr isolated CPUs: 2\n" + "\tBoost: 0\n" + "CPU5\n" + "\tCPU: 5\n" + "\tOnline: 1\n" + "\tIsolated: 1\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "\tNot preferred: 0\n" + "\tNr running: 1\n" + "\tActive CPUs: 2\n" + "\tNeed CPUs: 2\n" + "\tNr isolated CPUs: 2\n" + "\tBoost: 0\n" + "CPU6\n" + "\tCPU: 6\n" + "\tOnline: 1\n" + "\tIsolated: 0\n" + "\tFirst CPU: 4\n" + "\tBusy%: 11\n" + "\tIs busy: 0\n" + "\tNot preferred: 0\n" + "\tNr running: 1\n" + "\tActive CPUs: 2\n" + "\tNeed CPUs: 2\n" + "\tNr isolated CPUs: 2\n" + "\tBoost: 0\n" + "CPU7\n" + "\tCPU: 7\n" + "\tOnline: 1\n" + "\tIsolated: 0\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "\tNot preferred: 0\n" + "\tNr running: 1\n" + "\tActive CPUs: 2\n" + "\tNeed CPUs: 2\n" + "\tNr isolated CPUs: 2\n" + "\tBoost: 0\n", }, { .path = "/sys/devices/system/cpu/cpu0/core_ctl/is_big_cluster", @@ -824,11 +818,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/core_ctl/not_preferred", .size = 36, - .content = - "CPU#0: 0\n" - "CPU#1: 0\n" - "CPU#2: 0\n" - "CPU#3: 0\n", + .content = "CPU#0: 0\n" + "CPU#1: 0\n" + "CPU#2: 0\n" + "CPU#3: 0\n", }, { .path = "/sys/devices/system/cpu/cpu0/core_ctl/offline_delay_ms", @@ -873,7 +866,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies", .size = 136, - .content = "300000 403200 480000 576000 652800 748800 825600 902400 979200 1056000 1132800 1228800 1324800 1420800 1516800 1612800 1689600 1766400 \n", + .content = + "300000 403200 480000 576000 652800 748800 825600 902400 979200 1056000 1132800 1228800 1324800 1420800 1516800 1612800 1689600 1766400 \n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors", @@ -908,25 +902,24 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 207, - .content = - "300000 0\n" - "403200 0\n" - "480000 0\n" - "576000 0\n" - "652800 0\n" - "748800 66938\n" - "825600 1324\n" - "902400 680\n" - "979200 569\n" - "1056000 839\n" - "1132800 3428\n" - "1228800 4671\n" - "1324800 1242\n" - "1420800 3520\n" - "1516800 1109\n" - "1612800 830\n" - "1689600 477\n" - "1766400 11777\n", + .content = "300000 0\n" + "403200 0\n" + "480000 0\n" + "576000 0\n" + "652800 0\n" + "748800 66938\n" + "825600 1324\n" + "902400 680\n" + "979200 569\n" + "1056000 839\n" + "1132800 3428\n" + "1228800 4671\n" + "1324800 1242\n" + "1420800 3520\n" + "1516800 1109\n" + "1612800 830\n" + "1689600 477\n" + "1766400 11777\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -1211,7 +1204,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_frequencies", .size = 136, - .content = "300000 403200 480000 576000 652800 748800 825600 902400 979200 1056000 1132800 1228800 1324800 1420800 1516800 1612800 1689600 1766400 \n", + .content = + "300000 403200 480000 576000 652800 748800 825600 902400 979200 1056000 1132800 1228800 1324800 1420800 1516800 1612800 1689600 1766400 \n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_governors", @@ -1246,25 +1240,24 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 207, - .content = - "300000 0\n" - "403200 0\n" - "480000 0\n" - "576000 0\n" - "652800 0\n" - "748800 67202\n" - "825600 1324\n" - "902400 680\n" - "979200 569\n" - "1056000 839\n" - "1132800 3428\n" - "1228800 4671\n" - "1324800 1242\n" - "1420800 3520\n" - "1516800 1109\n" - "1612800 830\n" - "1689600 477\n" - "1766400 11777\n", + .content = "300000 0\n" + "403200 0\n" + "480000 0\n" + "576000 0\n" + "652800 0\n" + "748800 67202\n" + "825600 1324\n" + "902400 680\n" + "979200 569\n" + "1056000 839\n" + "1132800 3428\n" + "1228800 4671\n" + "1324800 1242\n" + "1420800 3520\n" + "1516800 1109\n" + "1612800 830\n" + "1689600 477\n" + "1766400 11777\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -1549,7 +1542,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_frequencies", .size = 136, - .content = "300000 403200 480000 576000 652800 748800 825600 902400 979200 1056000 1132800 1228800 1324800 1420800 1516800 1612800 1689600 1766400 \n", + .content = + "300000 403200 480000 576000 652800 748800 825600 902400 979200 1056000 1132800 1228800 1324800 1420800 1516800 1612800 1689600 1766400 \n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_governors", @@ -1584,25 +1578,24 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 207, - .content = - "300000 0\n" - "403200 0\n" - "480000 0\n" - "576000 0\n" - "652800 0\n" - "748800 67472\n" - "825600 1326\n" - "902400 680\n" - "979200 570\n" - "1056000 839\n" - "1132800 3428\n" - "1228800 4673\n" - "1324800 1242\n" - "1420800 3520\n" - "1516800 1109\n" - "1612800 830\n" - "1689600 477\n" - "1766400 11777\n", + .content = "300000 0\n" + "403200 0\n" + "480000 0\n" + "576000 0\n" + "652800 0\n" + "748800 67472\n" + "825600 1326\n" + "902400 680\n" + "979200 570\n" + "1056000 839\n" + "1132800 3428\n" + "1228800 4673\n" + "1324800 1242\n" + "1420800 3520\n" + "1516800 1109\n" + "1612800 830\n" + "1689600 477\n" + "1766400 11777\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -1887,7 +1880,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_frequencies", .size = 136, - .content = "300000 403200 480000 576000 652800 748800 825600 902400 979200 1056000 1132800 1228800 1324800 1420800 1516800 1612800 1689600 1766400 \n", + .content = + "300000 403200 480000 576000 652800 748800 825600 902400 979200 1056000 1132800 1228800 1324800 1420800 1516800 1612800 1689600 1766400 \n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_governors", @@ -1922,25 +1916,24 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 207, - .content = - "300000 0\n" - "403200 0\n" - "480000 0\n" - "576000 0\n" - "652800 0\n" - "748800 67730\n" - "825600 1331\n" - "902400 683\n" - "979200 570\n" - "1056000 840\n" - "1132800 3428\n" - "1228800 4677\n" - "1324800 1242\n" - "1420800 3520\n" - "1516800 1111\n" - "1612800 832\n" - "1689600 477\n" - "1766400 11784\n", + .content = "300000 0\n" + "403200 0\n" + "480000 0\n" + "576000 0\n" + "652800 0\n" + "748800 67730\n" + "825600 1331\n" + "902400 683\n" + "979200 570\n" + "1056000 840\n" + "1132800 3428\n" + "1228800 4677\n" + "1324800 1242\n" + "1420800 3520\n" + "1516800 1111\n" + "1612800 832\n" + "1689600 477\n" + "1766400 11784\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -2215,111 +2208,110 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/core_ctl/global_state", .size = 1336, - .content = - "CPU0\n" - "\tCPU: 0\n" - "\tOnline: 1\n" - "\tIsolated: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 1\n" - "\tIs busy: 1\n" - "\tNot preferred: 0\n" - "\tNr running: 1\n" - "\tActive CPUs: 4\n" - "\tNeed CPUs: 4\n" - "\tNr isolated CPUs: 0\n" - "\tBoost: 0\n" - "CPU1\n" - "\tCPU: 1\n" - "\tOnline: 1\n" - "\tIsolated: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 1\n" - "\tIs busy: 1\n" - "\tNot preferred: 0\n" - "\tNr running: 1\n" - "\tActive CPUs: 4\n" - "\tNeed CPUs: 4\n" - "\tNr isolated CPUs: 0\n" - "\tBoost: 0\n" - "CPU2\n" - "\tCPU: 2\n" - "\tOnline: 1\n" - "\tIsolated: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 4\n" - "\tIs busy: 1\n" - "\tNot preferred: 0\n" - "\tNr running: 1\n" - "\tActive CPUs: 4\n" - "\tNeed CPUs: 4\n" - "\tNr isolated CPUs: 0\n" - "\tBoost: 0\n" - "CPU3\n" - "\tCPU: 3\n" - "\tOnline: 1\n" - "\tIsolated: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 0\n" - "\tIs busy: 1\n" - "\tNot preferred: 0\n" - "\tNr running: 1\n" - "\tActive CPUs: 4\n" - "\tNeed CPUs: 4\n" - "\tNr isolated CPUs: 0\n" - "\tBoost: 0\n" - "CPU4\n" - "\tCPU: 4\n" - "\tOnline: 1\n" - "\tIsolated: 1\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "\tNot preferred: 0\n" - "\tNr running: 0\n" - "\tActive CPUs: 2\n" - "\tNeed CPUs: 2\n" - "\tNr isolated CPUs: 2\n" - "\tBoost: 0\n" - "CPU5\n" - "\tCPU: 5\n" - "\tOnline: 1\n" - "\tIsolated: 1\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "\tNot preferred: 0\n" - "\tNr running: 0\n" - "\tActive CPUs: 2\n" - "\tNeed CPUs: 2\n" - "\tNr isolated CPUs: 2\n" - "\tBoost: 0\n" - "CPU6\n" - "\tCPU: 6\n" - "\tOnline: 1\n" - "\tIsolated: 0\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "\tNot preferred: 0\n" - "\tNr running: 0\n" - "\tActive CPUs: 2\n" - "\tNeed CPUs: 2\n" - "\tNr isolated CPUs: 2\n" - "\tBoost: 0\n" - "CPU7\n" - "\tCPU: 7\n" - "\tOnline: 1\n" - "\tIsolated: 0\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "\tNot preferred: 0\n" - "\tNr running: 0\n" - "\tActive CPUs: 2\n" - "\tNeed CPUs: 2\n" - "\tNr isolated CPUs: 2\n" - "\tBoost: 0\n", + .content = "CPU0\n" + "\tCPU: 0\n" + "\tOnline: 1\n" + "\tIsolated: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 1\n" + "\tIs busy: 1\n" + "\tNot preferred: 0\n" + "\tNr running: 1\n" + "\tActive CPUs: 4\n" + "\tNeed CPUs: 4\n" + "\tNr isolated CPUs: 0\n" + "\tBoost: 0\n" + "CPU1\n" + "\tCPU: 1\n" + "\tOnline: 1\n" + "\tIsolated: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 1\n" + "\tIs busy: 1\n" + "\tNot preferred: 0\n" + "\tNr running: 1\n" + "\tActive CPUs: 4\n" + "\tNeed CPUs: 4\n" + "\tNr isolated CPUs: 0\n" + "\tBoost: 0\n" + "CPU2\n" + "\tCPU: 2\n" + "\tOnline: 1\n" + "\tIsolated: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 4\n" + "\tIs busy: 1\n" + "\tNot preferred: 0\n" + "\tNr running: 1\n" + "\tActive CPUs: 4\n" + "\tNeed CPUs: 4\n" + "\tNr isolated CPUs: 0\n" + "\tBoost: 0\n" + "CPU3\n" + "\tCPU: 3\n" + "\tOnline: 1\n" + "\tIsolated: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 0\n" + "\tIs busy: 1\n" + "\tNot preferred: 0\n" + "\tNr running: 1\n" + "\tActive CPUs: 4\n" + "\tNeed CPUs: 4\n" + "\tNr isolated CPUs: 0\n" + "\tBoost: 0\n" + "CPU4\n" + "\tCPU: 4\n" + "\tOnline: 1\n" + "\tIsolated: 1\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "\tNot preferred: 0\n" + "\tNr running: 0\n" + "\tActive CPUs: 2\n" + "\tNeed CPUs: 2\n" + "\tNr isolated CPUs: 2\n" + "\tBoost: 0\n" + "CPU5\n" + "\tCPU: 5\n" + "\tOnline: 1\n" + "\tIsolated: 1\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "\tNot preferred: 0\n" + "\tNr running: 0\n" + "\tActive CPUs: 2\n" + "\tNeed CPUs: 2\n" + "\tNr isolated CPUs: 2\n" + "\tBoost: 0\n" + "CPU6\n" + "\tCPU: 6\n" + "\tOnline: 1\n" + "\tIsolated: 0\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "\tNot preferred: 0\n" + "\tNr running: 0\n" + "\tActive CPUs: 2\n" + "\tNeed CPUs: 2\n" + "\tNr isolated CPUs: 2\n" + "\tBoost: 0\n" + "CPU7\n" + "\tCPU: 7\n" + "\tOnline: 1\n" + "\tIsolated: 0\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "\tNot preferred: 0\n" + "\tNr running: 0\n" + "\tActive CPUs: 2\n" + "\tNeed CPUs: 2\n" + "\tNr isolated CPUs: 2\n" + "\tBoost: 0\n", }, { .path = "/sys/devices/system/cpu/cpu4/core_ctl/is_big_cluster", @@ -2344,11 +2336,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/core_ctl/not_preferred", .size = 36, - .content = - "CPU#4: 0\n" - "CPU#5: 0\n" - "CPU#6: 0\n" - "CPU#7: 0\n", + .content = "CPU#4: 0\n" + "CPU#5: 0\n" + "CPU#6: 0\n" + "CPU#7: 0\n", }, { .path = "/sys/devices/system/cpu/cpu4/core_ctl/offline_delay_ms", @@ -2393,7 +2384,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_available_frequencies", .size = 182, - .content = "825600 902400 979200 1056000 1209600 1286400 1363200 1459200 1536000 1612800 1689600 1766400 1843200 1920000 1996800 2092800 2169600 2246400 2323200 2400000 2476800 2553600 2649600 \n", + .content = + "825600 902400 979200 1056000 1209600 1286400 1363200 1459200 1536000 1612800 1689600 1766400 1843200 1920000 1996800 2092800 2169600 2246400 2323200 2400000 2476800 2553600 2649600 \n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_available_governors", @@ -2428,31 +2420,30 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/time_in_state", .size = 280, - .content = - "825600 87365\n" - "902400 90\n" - "979200 211\n" - "1056000 540\n" - "1209600 409\n" - "1286400 268\n" - "1363200 443\n" - "1459200 126\n" - "1536000 56\n" - "1612800 499\n" - "1689600 251\n" - "1766400 156\n" - "1843200 87\n" - "1920000 85\n" - "1996800 172\n" - "2092800 115\n" - "2169600 96\n" - "2246400 70\n" - "2323200 687\n" - "2400000 98\n" - "2476800 238\n" - "2553600 75\n" - "2649600 118\n" - "2803200 6280\n", + .content = "825600 87365\n" + "902400 90\n" + "979200 211\n" + "1056000 540\n" + "1209600 409\n" + "1286400 268\n" + "1363200 443\n" + "1459200 126\n" + "1536000 56\n" + "1612800 499\n" + "1689600 251\n" + "1766400 156\n" + "1843200 87\n" + "1920000 85\n" + "1996800 172\n" + "2092800 115\n" + "2169600 96\n" + "2246400 70\n" + "2323200 687\n" + "2400000 98\n" + "2476800 238\n" + "2553600 75\n" + "2649600 118\n" + "2803200 6280\n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/total_trans", @@ -2737,7 +2728,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_available_frequencies", .size = 182, - .content = "825600 902400 979200 1056000 1209600 1286400 1363200 1459200 1536000 1612800 1689600 1766400 1843200 1920000 1996800 2092800 2169600 2246400 2323200 2400000 2476800 2553600 2649600 \n", + .content = + "825600 902400 979200 1056000 1209600 1286400 1363200 1459200 1536000 1612800 1689600 1766400 1843200 1920000 1996800 2092800 2169600 2246400 2323200 2400000 2476800 2553600 2649600 \n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_available_governors", @@ -2772,31 +2764,30 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/time_in_state", .size = 280, - .content = - "825600 87664\n" - "902400 90\n" - "979200 211\n" - "1056000 540\n" - "1209600 409\n" - "1286400 268\n" - "1363200 443\n" - "1459200 126\n" - "1536000 56\n" - "1612800 499\n" - "1689600 251\n" - "1766400 156\n" - "1843200 87\n" - "1920000 85\n" - "1996800 172\n" - "2092800 115\n" - "2169600 96\n" - "2246400 70\n" - "2323200 687\n" - "2400000 98\n" - "2476800 238\n" - "2553600 75\n" - "2649600 118\n" - "2803200 6280\n", + .content = "825600 87664\n" + "902400 90\n" + "979200 211\n" + "1056000 540\n" + "1209600 409\n" + "1286400 268\n" + "1363200 443\n" + "1459200 126\n" + "1536000 56\n" + "1612800 499\n" + "1689600 251\n" + "1766400 156\n" + "1843200 87\n" + "1920000 85\n" + "1996800 172\n" + "2092800 115\n" + "2169600 96\n" + "2246400 70\n" + "2323200 687\n" + "2400000 98\n" + "2476800 238\n" + "2553600 75\n" + "2649600 118\n" + "2803200 6280\n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/total_trans", @@ -3081,7 +3072,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_available_frequencies", .size = 182, - .content = "825600 902400 979200 1056000 1209600 1286400 1363200 1459200 1536000 1612800 1689600 1766400 1843200 1920000 1996800 2092800 2169600 2246400 2323200 2400000 2476800 2553600 2649600 \n", + .content = + "825600 902400 979200 1056000 1209600 1286400 1363200 1459200 1536000 1612800 1689600 1766400 1843200 1920000 1996800 2092800 2169600 2246400 2323200 2400000 2476800 2553600 2649600 \n", }, { .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_available_governors", @@ -3116,31 +3108,30 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/time_in_state", .size = 280, - .content = - "825600 87975\n" - "902400 90\n" - "979200 211\n" - "1056000 540\n" - "1209600 409\n" - "1286400 272\n" - "1363200 443\n" - "1459200 126\n" - "1536000 56\n" - "1612800 499\n" - "1689600 251\n" - "1766400 156\n" - "1843200 87\n" - "1920000 85\n" - "1996800 172\n" - "2092800 115\n" - "2169600 96\n" - "2246400 70\n" - "2323200 687\n" - "2400000 98\n" - "2476800 238\n" - "2553600 75\n" - "2649600 118\n" - "2803200 6280\n", + .content = "825600 87975\n" + "902400 90\n" + "979200 211\n" + "1056000 540\n" + "1209600 409\n" + "1286400 272\n" + "1363200 443\n" + "1459200 126\n" + "1536000 56\n" + "1612800 499\n" + "1689600 251\n" + "1766400 156\n" + "1843200 87\n" + "1920000 85\n" + "1996800 172\n" + "2092800 115\n" + "2169600 96\n" + "2246400 70\n" + "2323200 687\n" + "2400000 98\n" + "2476800 238\n" + "2553600 75\n" + "2649600 118\n" + "2803200 6280\n", }, { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/total_trans", @@ -3425,7 +3416,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_available_frequencies", .size = 182, - .content = "825600 902400 979200 1056000 1209600 1286400 1363200 1459200 1536000 1612800 1689600 1766400 1843200 1920000 1996800 2092800 2169600 2246400 2323200 2400000 2476800 2553600 2649600 \n", + .content = + "825600 902400 979200 1056000 1209600 1286400 1363200 1459200 1536000 1612800 1689600 1766400 1843200 1920000 1996800 2092800 2169600 2246400 2323200 2400000 2476800 2553600 2649600 \n", }, { .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_available_governors", @@ -3460,31 +3452,30 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/time_in_state", .size = 280, - .content = - "825600 88241\n" - "902400 90\n" - "979200 211\n" - "1056000 540\n" - "1209600 409\n" - "1286400 273\n" - "1363200 448\n" - "1459200 127\n" - "1536000 58\n" - "1612800 500\n" - "1689600 253\n" - "1766400 156\n" - "1843200 87\n" - "1920000 85\n" - "1996800 173\n" - "2092800 115\n" - "2169600 96\n" - "2246400 70\n" - "2323200 687\n" - "2400000 98\n" - "2476800 240\n" - "2553600 75\n" - "2649600 118\n" - "2803200 6293\n", + .content = "825600 88241\n" + "902400 90\n" + "979200 211\n" + "1056000 540\n" + "1209600 409\n" + "1286400 273\n" + "1363200 448\n" + "1459200 127\n" + "1536000 58\n" + "1612800 500\n" + "1689600 253\n" + "1766400 156\n" + "1843200 87\n" + "1920000 85\n" + "1996800 173\n" + "2092800 115\n" + "2169600 96\n" + "2246400 70\n" + "2323200 687\n" + "2400000 98\n" + "2476800 240\n" + "2553600 75\n" + "2649600 118\n" + "2803200 6293\n", }, { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/total_trans", @@ -3736,7 +3727,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 10, .content = "WriteBack\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -6696,6 +6687,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wifi.interface", .value = "wlan0", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/galaxy-tab-3-7.0.cc b/test/mock/galaxy-tab-3-7.0.cc index 1b20a44a..95199088 100644 --- a/test/mock/galaxy-tab-3-7.0.cc +++ b/test/mock/galaxy-tab-3-7.0.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(2, cpuinfo_get_processors_count()); @@ -208,8 +207,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Marvell PXA986", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Marvell PXA986", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -400,8 +401,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -452,8 +455,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -504,8 +509,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/galaxy-tab-3-7.0.h b/test/mock/galaxy-tab-3-7.0.h index 1d73116d..b2e58d9d 100644 --- a/test/mock/galaxy-tab-3-7.0.h +++ b/test/mock/galaxy-tab-3-7.0.h @@ -2,21 +2,20 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 298, - .content = - "Processor\t: ARMv7 Processor rev 0 (v7l)\n" - "processor\t: 0\n" - "BogoMIPS\t: 313.53\n" - "\n" - "Features\t: swp half thumb fastmult vfp edsp thumbee neon vfpv3 tls \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x3\n" - "CPU part\t: 0xc09\n" - "CPU revision\t: 0\n" - "\n" - "Hardware\t: PXA988\n" - "Revision\t: 0007\n" - "Serial\t\t: 4102dcf646581100\n", + .content = "Processor\t: ARMv7 Processor rev 0 (v7l)\n" + "processor\t: 0\n" + "BogoMIPS\t: 313.53\n" + "\n" + "Features\t: swp half thumb fastmult vfp edsp thumbee neon vfpv3 tls \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x3\n" + "CPU part\t: 0xc09\n" + "CPU revision\t: 0\n" + "\n" + "Hardware\t: PXA988\n" + "Revision\t: 0007\n" + "Serial\t\t: 4102dcf646581100\n", }, { .path = "/system/build.prop", @@ -212,11 +211,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 51, - .content = - "312000 11572\n" - "624000 789\n" - "1066000 1053\n" - "1205000 10056\n", + .content = "312000 11572\n" + "624000 789\n" + "1066000 1053\n" + "1205000 10056\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -226,13 +224,12 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/trans_table", .size = 277, - .content = - " From : To\n" - " : 312000 624000 1066000 1205000 \n" - " 312000: 0 0 23 105 \n" - " 624000: 60 0 7 50 \n" - " 1066000: 36 55 0 135 \n" - " 1205000: 33 62 196 0 \n", + .content = " From : To\n" + " : 312000 624000 1066000 1205000 \n" + " 312000: 0 0 23 105 \n" + " 624000: 60 0 7 50 \n" + " 1066000: 36 55 0 135 \n" + " 1205000: 33 62 196 0 \n", }, { .path = "/sys/devices/system/cpu/cpu0/topology/physical_package_id", @@ -264,7 +261,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "1\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ @@ -1097,6 +1094,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.wfd.status", .value = "disconnected", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/galaxy-tab-3-lite.cc b/test/mock/galaxy-tab-3-lite.cc index 9d1efcd8..d61831d3 100644 --- a/test/mock/galaxy-tab-3-lite.cc +++ b/test/mock/galaxy-tab-3-lite.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(4, cpuinfo_get_processors_count()); @@ -208,8 +207,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Spreadtrum SC7730S", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Spreadtrum SC7730S", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -400,8 +401,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -452,8 +455,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -504,8 +509,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/galaxy-tab-3-lite.h b/test/mock/galaxy-tab-3-lite.h index d26613b4..5b24aea6 100644 --- a/test/mock/galaxy-tab-3-lite.h +++ b/test/mock/galaxy-tab-3-lite.h @@ -2,21 +2,20 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 349, - .content = - "Processor\t: ARMv7 Processor rev 5 (v7l)\n" - "processor\t: 0\n" - "model name\t: ARMv7 Processor rev 5 (v7l)\n" - "BogoMIPS\t: 1538.01\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xc07\n" - "CPU revision\t: 5\n" - "\n" - "Hardware\t: sc8830\n" - "Revision\t: 0004\n" - "Serial\t\t: 3100818054f13400\n", + .content = "Processor\t: ARMv7 Processor rev 5 (v7l)\n" + "processor\t: 0\n" + "model name\t: ARMv7 Processor rev 5 (v7l)\n" + "BogoMIPS\t: 1538.01\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xc07\n" + "CPU revision\t: 5\n" + "\n" + "Hardware\t: sc8830\n" + "Revision\t: 0004\n" + "Serial\t\t: 3100818054f13400\n", }, { .path = "/system/build.prop", @@ -281,11 +280,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 51, - .content = - "1300000 7925\n" - "1200000 1060\n" - "1000000 207\n" - "768000 21236\n", + .content = "1300000 7925\n" + "1200000 1060\n" + "1000000 207\n" + "768000 21236\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -322,7 +320,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "1\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ @@ -1599,6 +1597,6 @@ struct cpuinfo_mock_property properties[] = { .key = "zram.disksize", .value = "300", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/galaxy-win-duos.cc b/test/mock/galaxy-win-duos.cc index 33c1733a..73be389e 100644 --- a/test/mock/galaxy-win-duos.cc +++ b/test/mock/galaxy-win-duos.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(4, cpuinfo_get_processors_count()); @@ -208,8 +207,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Qualcomm MSM8625Q", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Qualcomm MSM8625Q", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -400,8 +401,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -452,8 +455,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -504,8 +509,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/galaxy-win-duos.h b/test/mock/galaxy-win-duos.h index 64244a02..c0069c89 100644 --- a/test/mock/galaxy-win-duos.h +++ b/test/mock/galaxy-win-duos.h @@ -2,30 +2,29 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 414, - .content = - "Processor\t: ARMv7 Processor rev 1 (v7l)\n" - "processor\t: 0\n" - "BogoMIPS\t: 159.25\n" - "\n" - "processor\t: 1\n" - "BogoMIPS\t: 159.25\n" - "\n" - "processor\t: 2\n" - "BogoMIPS\t: 159.25\n" - "\n" - "processor\t: 3\n" - "BogoMIPS\t: 159.25\n" - "\n" - "Features\t: swp half thumb fastmult vfp edsp thumbee neon vfpv3 tls vfpv4 \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xc05\n" - "CPU revision\t: 1\n" - "\n" - "Hardware\t: QRD MSM8625Q SKUD\n" - "Revision\t: 0000\n" - "Serial\t\t: 420369c3c4d34128\n", + .content = "Processor\t: ARMv7 Processor rev 1 (v7l)\n" + "processor\t: 0\n" + "BogoMIPS\t: 159.25\n" + "\n" + "processor\t: 1\n" + "BogoMIPS\t: 159.25\n" + "\n" + "processor\t: 2\n" + "BogoMIPS\t: 159.25\n" + "\n" + "processor\t: 3\n" + "BogoMIPS\t: 159.25\n" + "\n" + "Features\t: swp half thumb fastmult vfp edsp thumbee neon vfpv3 tls vfpv4 \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xc05\n" + "CPU revision\t: 1\n" + "\n" + "Hardware\t: QRD MSM8625Q SKUD\n" + "Revision\t: 0000\n" + "Serial\t\t: 420369c3c4d34128\n", }, { .path = "/system/build.prop", @@ -404,13 +403,12 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 71, - .content = - "245760 2541\n" - "320000 144\n" - "480000 164\n" - "700800 394\n" - "1008000 2542\n" - "1209600 2131\n", + .content = "245760 2541\n" + "320000 144\n" + "480000 164\n" + "700800 394\n" + "1008000 2542\n" + "1209600 2131\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -420,15 +418,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/trans_table", .size = 521, - .content = - " From : To\n" - " : 245760 320000 480000 700800 1008000 1209600 \n" - " 245760: 0 0 0 32 0 0 \n" - " 320000: 7 0 0 1 0 0 \n" - " 480000: 5 0 0 13 0 1 \n" - " 700800: 10 2 12 0 34 0 \n" - " 1008000: 5 2 2 5 0 63 \n" - " 1209600: 6 4 4 7 43 0 \n", + .content = " From : To\n" + " : 245760 320000 480000 700800 1008000 1209600 \n" + " 245760: 0 0 0 32 0 0 \n" + " 320000: 7 0 0 1 0 0 \n" + " 480000: 5 0 0 13 0 1 \n" + " 700800: 10 2 12 0 34 0 \n" + " 1008000: 5 2 2 5 0 63 \n" + " 1209600: 6 4 4 7 43 0 \n", }, { .path = "/sys/devices/system/cpu/cpu0/topology/physical_package_id", @@ -460,7 +457,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "1\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ @@ -1841,6 +1838,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.driver.status", .value = "ok", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/huawei-ascend-p7.cc b/test/mock/huawei-ascend-p7.cc index 69349c12..13d1f4be 100644 --- a/test/mock/huawei-ascend-p7.cc +++ b/test/mock/huawei-ascend-p7.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(4, cpuinfo_get_processors_count()); @@ -208,8 +207,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("HiSilicon Kirin 910T", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "HiSilicon Kirin 910T", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -400,8 +401,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -452,8 +455,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -504,8 +509,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/huawei-ascend-p7.h b/test/mock/huawei-ascend-p7.h index 22379e6c..063f5d84 100644 --- a/test/mock/huawei-ascend-p7.h +++ b/test/mock/huawei-ascend-p7.h @@ -2,30 +2,29 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 400, - .content = - "Processor\t: ARMv7 Processor rev 1 (v7l)\n" - "processor\t: 0\n" - "BogoMIPS\t: 3577.00\n" - "\n" - "processor\t: 1\n" - "BogoMIPS\t: 3577.00\n" - "\n" - "processor\t: 2\n" - "BogoMIPS\t: 3577.00\n" - "\n" - "processor\t: 3\n" - "BogoMIPS\t: 3577.00\n" - "\n" - "Features\t: swp half thumb fastmult vfp edsp thumbee neon vfpv3 \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x4\n" - "CPU part\t: 0xc09\n" - "CPU revision\t: 1\n" - "\n" - "Hardware\t: hi6620oem\n" - "Revision\t: 0000\n" - "Serial\t\t: 0000000000000000\n", + .content = "Processor\t: ARMv7 Processor rev 1 (v7l)\n" + "processor\t: 0\n" + "BogoMIPS\t: 3577.00\n" + "\n" + "processor\t: 1\n" + "BogoMIPS\t: 3577.00\n" + "\n" + "processor\t: 2\n" + "BogoMIPS\t: 3577.00\n" + "\n" + "processor\t: 3\n" + "BogoMIPS\t: 3577.00\n" + "\n" + "Features\t: swp half thumb fastmult vfp edsp thumbee neon vfpv3 \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x4\n" + "CPU part\t: 0xc09\n" + "CPU revision\t: 1\n" + "\n" + "Hardware\t: hi6620oem\n" + "Revision\t: 0000\n" + "Serial\t\t: 0000000000000000\n", }, { .path = "/system/build.prop", @@ -363,14 +362,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 81, - .content = - "208000 2430\n" - "416000 211\n" - "624000 432\n" - "798000 195\n" - "1196000 156\n" - "1596000 55\n" - "1795000 6002\n", + .content = "208000 2430\n" + "416000 211\n" + "624000 432\n" + "798000 195\n" + "1196000 156\n" + "1596000 55\n" + "1795000 6002\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -470,14 +468,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 66, - .content = - "208000 0\n" - "416000 0\n" - "624000 0\n" - "798000 0\n" - "1196000 0\n" - "1596000 0\n" - "1795000 0\n", + .content = "208000 0\n" + "416000 0\n" + "624000 0\n" + "798000 0\n" + "1196000 0\n" + "1596000 0\n" + "1795000 0\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -577,14 +574,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 66, - .content = - "208000 0\n" - "416000 0\n" - "624000 0\n" - "798000 0\n" - "1196000 0\n" - "1596000 0\n" - "1795000 0\n", + .content = "208000 0\n" + "416000 0\n" + "624000 0\n" + "798000 0\n" + "1196000 0\n" + "1596000 0\n" + "1795000 0\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -621,7 +617,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "4\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ @@ -2226,6 +2222,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.driver.status", .value = "ok", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/huawei-honor-6.cc b/test/mock/huawei-honor-6.cc index 59ad7553..4784bcf8 100644 --- a/test/mock/huawei-honor-6.cc +++ b/test/mock/huawei-honor-6.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(8, cpuinfo_get_processors_count()); @@ -334,8 +333,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("HiSilicon Kirin 920", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "HiSilicon Kirin 920", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -526,8 +527,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -604,8 +607,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -670,8 +675,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/huawei-honor-6.h b/test/mock/huawei-honor-6.h index 7d47fe9f..0da8a7d1 100644 --- a/test/mock/huawei-honor-6.h +++ b/test/mock/huawei-honor-6.h @@ -2,42 +2,41 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 551, - .content = - "Processor\t: ARMv7 Processor rev 5 (v7l)\n" - "processor\t: 0\n" - "BogoMIPS\t: 12.80\n" - "\n" - "processor\t: 1\n" - "BogoMIPS\t: 12.80\n" - "\n" - "processor\t: 2\n" - "BogoMIPS\t: 12.80\n" - "\n" - "processor\t: 3\n" - "BogoMIPS\t: 12.80\n" - "\n" - "processor\t: 4\n" - "BogoMIPS\t: 38.40\n" - "\n" - "processor\t: 5\n" - "BogoMIPS\t: 38.40\n" - "\n" - "processor\t: 6\n" - "BogoMIPS\t: 38.40\n" - "\n" - "processor\t: 7\n" - "BogoMIPS\t: 38.40\n" - "\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x0 & 0x3\n" - "CPU part\t: 0xc07 & 0xc0f\n" - "CPU revision\t: 5 & 3\n" - "\n" - "Hardware\t: Kirin920\n" - "Revision\t: 0000\n" - "Serial\t\t: 0000000000000000\n", + .content = "Processor\t: ARMv7 Processor rev 5 (v7l)\n" + "processor\t: 0\n" + "BogoMIPS\t: 12.80\n" + "\n" + "processor\t: 1\n" + "BogoMIPS\t: 12.80\n" + "\n" + "processor\t: 2\n" + "BogoMIPS\t: 12.80\n" + "\n" + "processor\t: 3\n" + "BogoMIPS\t: 12.80\n" + "\n" + "processor\t: 4\n" + "BogoMIPS\t: 38.40\n" + "\n" + "processor\t: 5\n" + "BogoMIPS\t: 38.40\n" + "\n" + "processor\t: 6\n" + "BogoMIPS\t: 38.40\n" + "\n" + "processor\t: 7\n" + "BogoMIPS\t: 38.40\n" + "\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x0 & 0x3\n" + "CPU part\t: 0xc07 & 0xc0f\n" + "CPU revision\t: 5 & 3\n" + "\n" + "Hardware\t: Kirin920\n" + "Revision\t: 0000\n" + "Serial\t\t: 0000000000000000\n", }, { .path = "/system/build.prop", @@ -387,13 +386,12 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 74, - .content = - "403200 33253\n" - "604800 313\n" - "806400 307\n" - "1017600 386\n" - "1209600 12625\n" - "1305600 1894\n", + .content = "403200 33253\n" + "604800 313\n" + "806400 307\n" + "1017600 386\n" + "1209600 12625\n" + "1305600 1894\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -498,13 +496,12 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 74, - .content = - "403200 33498\n" - "604800 315\n" - "806400 307\n" - "1017600 386\n" - "1209600 12635\n" - "1305600 1894\n", + .content = "403200 33498\n" + "604800 315\n" + "806400 307\n" + "1017600 386\n" + "1209600 12635\n" + "1305600 1894\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -609,13 +606,12 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 74, - .content = - "403200 33727\n" - "604800 315\n" - "806400 307\n" - "1017600 386\n" - "1209600 12645\n" - "1305600 1894\n", + .content = "403200 33727\n" + "604800 315\n" + "806400 307\n" + "1017600 386\n" + "1209600 12645\n" + "1305600 1894\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -720,13 +716,12 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 74, - .content = - "403200 33974\n" - "604800 315\n" - "806400 307\n" - "1017600 386\n" - "1209600 12645\n" - "1305600 1894\n", + .content = "403200 33974\n" + "604800 315\n" + "806400 307\n" + "1017600 386\n" + "1209600 12645\n" + "1305600 1894\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -831,13 +826,12 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/time_in_state", .size = 67, - .content = - "806400 47983\n" - "1017600 3\n" - "1209600 13\n" - "1382400 8\n" - "1497600 7\n" - "1708800 1760\n", + .content = "806400 47983\n" + "1017600 3\n" + "1209600 13\n" + "1382400 8\n" + "1497600 7\n" + "1708800 1760\n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/total_trans", @@ -942,13 +936,12 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/time_in_state", .size = 67, - .content = - "806400 48237\n" - "1017600 3\n" - "1209600 13\n" - "1382400 8\n" - "1497600 7\n" - "1708800 1760\n", + .content = "806400 48237\n" + "1017600 3\n" + "1209600 13\n" + "1382400 8\n" + "1497600 7\n" + "1708800 1760\n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/total_trans", @@ -1053,13 +1046,12 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/time_in_state", .size = 67, - .content = - "806400 48504\n" - "1017600 3\n" - "1209600 13\n" - "1382400 8\n" - "1497600 7\n" - "1708800 1760\n", + .content = "806400 48504\n" + "1017600 3\n" + "1209600 13\n" + "1382400 8\n" + "1497600 7\n" + "1708800 1760\n", }, { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/total_trans", @@ -1164,13 +1156,12 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/time_in_state", .size = 67, - .content = - "806400 48759\n" - "1017600 3\n" - "1209600 13\n" - "1382400 8\n" - "1497600 7\n" - "1708800 1760\n", + .content = "806400 48759\n" + "1017600 3\n" + "1209600 13\n" + "1382400 8\n" + "1497600 7\n" + "1708800 1760\n", }, { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/total_trans", @@ -1207,7 +1198,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "7\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -2971,6 +2962,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.driver.status", .value = "ok", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/huawei-mate-10.cc b/test/mock/huawei-mate-10.cc index 92be5aad..d9a85855 100644 --- a/test/mock/huawei-mate-10.cc +++ b/test/mock/huawei-mate-10.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(8, cpuinfo_get_processors_count()); @@ -334,8 +333,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("HiSilicon Kirin 970", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "HiSilicon Kirin 970", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -377,59 +378,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -580,8 +581,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -658,8 +661,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -717,8 +722,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/huawei-mate-10.h b/test/mock/huawei-mate-10.h index bd2168f0..c0623d93 100644 --- a/test/mock/huawei-mate-10.h +++ b/test/mock/huawei-mate-10.h @@ -3,79 +3,78 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 1440, - .content = - "processor\t: 0\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 1\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 2\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 3\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 4\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd09\n" - "CPU revision\t: 2\n" - "\n" - "processor\t: 5\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd09\n" - "CPU revision\t: 2\n" - "\n" - "processor\t: 6\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd09\n" - "CPU revision\t: 2\n" - "\n" - "processor\t: 7\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd09\n" - "CPU revision\t: 2\n" - "\n", + .content = "processor\t: 0\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 1\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 2\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 3\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 4\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd09\n" + "CPU revision\t: 2\n" + "\n" + "processor\t: 5\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd09\n" + "CPU revision\t: 2\n" + "\n" + "processor\t: 6\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd09\n" + "CPU revision\t: 2\n" + "\n" + "processor\t: 7\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd09\n" + "CPU revision\t: 2\n" + "\n", }, #elif CPUINFO_ARCH_ARM { @@ -272,14 +271,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 77, - .content = - "509000 94\n" - "1018000 97\n" - "1210000 8\n" - "1402000 79\n" - "1556000 23\n" - "1690000 52\n" - "1844000 8524\n", + .content = "509000 94\n" + "1018000 97\n" + "1210000 8\n" + "1402000 79\n" + "1556000 23\n" + "1690000 52\n" + "1844000 8524\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -289,16 +287,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/trans_table", .size = 673, - .content = - " From : To\n" - " : 509000 1018000 1210000 1402000 1556000 1690000 1844000 \n" - " 509000: 0 3 0 5 0 0 0 \n" - " 1018000: 1 0 1 5 0 0 0 \n" - " 1210000: 1 0 0 0 0 0 0 \n" - " 1402000: 1 2 0 0 3 6 0 \n" - " 1556000: 1 0 0 0 0 2 3 \n" - " 1690000: 1 0 0 0 1 0 10 \n" - " 1844000: 3 2 0 2 2 3 0 \n", + .content = " From : To\n" + " : 509000 1018000 1210000 1402000 1556000 1690000 1844000 \n" + " 509000: 0 3 0 5 0 0 0 \n" + " 1018000: 1 0 1 5 0 0 0 \n" + " 1210000: 1 0 0 0 0 0 0 \n" + " 1402000: 1 2 0 0 3 6 0 \n" + " 1556000: 1 0 0 0 0 2 3 \n" + " 1690000: 1 0 0 0 1 0 10 \n" + " 1844000: 3 2 0 2 2 3 0 \n", }, { .path = "/sys/devices/system/cpu/cpu0/topology/core_id", @@ -393,14 +390,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 77, - .content = - "509000 94\n" - "1018000 97\n" - "1210000 8\n" - "1402000 79\n" - "1556000 23\n" - "1690000 52\n" - "1844000 8742\n", + .content = "509000 94\n" + "1018000 97\n" + "1210000 8\n" + "1402000 79\n" + "1556000 23\n" + "1690000 52\n" + "1844000 8742\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -410,16 +406,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/trans_table", .size = 673, - .content = - " From : To\n" - " : 509000 1018000 1210000 1402000 1556000 1690000 1844000 \n" - " 509000: 0 3 0 5 0 0 0 \n" - " 1018000: 1 0 1 5 0 0 0 \n" - " 1210000: 1 0 0 0 0 0 0 \n" - " 1402000: 1 2 0 0 3 6 0 \n" - " 1556000: 1 0 0 0 0 2 3 \n" - " 1690000: 1 0 0 0 1 0 10 \n" - " 1844000: 3 2 0 2 2 3 0 \n", + .content = " From : To\n" + " : 509000 1018000 1210000 1402000 1556000 1690000 1844000 \n" + " 509000: 0 3 0 5 0 0 0 \n" + " 1018000: 1 0 1 5 0 0 0 \n" + " 1210000: 1 0 0 0 0 0 0 \n" + " 1402000: 1 2 0 0 3 6 0 \n" + " 1556000: 1 0 0 0 0 2 3 \n" + " 1690000: 1 0 0 0 1 0 10 \n" + " 1844000: 3 2 0 2 2 3 0 \n", }, { .path = "/sys/devices/system/cpu/cpu1/topology/core_id", @@ -514,14 +509,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 77, - .content = - "509000 94\n" - "1018000 97\n" - "1210000 8\n" - "1402000 79\n" - "1556000 23\n" - "1690000 52\n" - "1844000 8984\n", + .content = "509000 94\n" + "1018000 97\n" + "1210000 8\n" + "1402000 79\n" + "1556000 23\n" + "1690000 52\n" + "1844000 8984\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -531,16 +525,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/trans_table", .size = 673, - .content = - " From : To\n" - " : 509000 1018000 1210000 1402000 1556000 1690000 1844000 \n" - " 509000: 0 3 0 5 0 0 0 \n" - " 1018000: 1 0 1 5 0 0 0 \n" - " 1210000: 1 0 0 0 0 0 0 \n" - " 1402000: 1 2 0 0 3 6 0 \n" - " 1556000: 1 0 0 0 0 2 3 \n" - " 1690000: 1 0 0 0 1 0 10 \n" - " 1844000: 3 2 0 2 2 3 0 \n", + .content = " From : To\n" + " : 509000 1018000 1210000 1402000 1556000 1690000 1844000 \n" + " 509000: 0 3 0 5 0 0 0 \n" + " 1018000: 1 0 1 5 0 0 0 \n" + " 1210000: 1 0 0 0 0 0 0 \n" + " 1402000: 1 2 0 0 3 6 0 \n" + " 1556000: 1 0 0 0 0 2 3 \n" + " 1690000: 1 0 0 0 1 0 10 \n" + " 1844000: 3 2 0 2 2 3 0 \n", }, { .path = "/sys/devices/system/cpu/cpu2/topology/core_id", @@ -635,14 +628,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 77, - .content = - "509000 94\n" - "1018000 97\n" - "1210000 8\n" - "1402000 79\n" - "1556000 23\n" - "1690000 52\n" - "1844000 9255\n", + .content = "509000 94\n" + "1018000 97\n" + "1210000 8\n" + "1402000 79\n" + "1556000 23\n" + "1690000 52\n" + "1844000 9255\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -652,16 +644,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/trans_table", .size = 673, - .content = - " From : To\n" - " : 509000 1018000 1210000 1402000 1556000 1690000 1844000 \n" - " 509000: 0 3 0 5 0 0 0 \n" - " 1018000: 1 0 1 5 0 0 0 \n" - " 1210000: 1 0 0 0 0 0 0 \n" - " 1402000: 1 2 0 0 3 6 0 \n" - " 1556000: 1 0 0 0 0 2 3 \n" - " 1690000: 1 0 0 0 1 0 10 \n" - " 1844000: 3 2 0 2 2 3 0 \n", + .content = " From : To\n" + " : 509000 1018000 1210000 1402000 1556000 1690000 1844000 \n" + " 509000: 0 3 0 5 0 0 0 \n" + " 1018000: 1 0 1 5 0 0 0 \n" + " 1210000: 1 0 0 0 0 0 0 \n" + " 1402000: 1 2 0 0 3 6 0 \n" + " 1556000: 1 0 0 0 0 2 3 \n" + " 1690000: 1 0 0 0 1 0 10 \n" + " 1844000: 3 2 0 2 2 3 0 \n", }, { .path = "/sys/devices/system/cpu/cpu3/topology/core_id", @@ -761,16 +752,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/time_in_state", .size = 107, - .content = - "682000 867\n" - "1018000 259\n" - "1210000 66\n" - "1364000 481\n" - "1498000 232\n" - "1652000 328\n" - "1863000 287\n" - "2093000 240\n" - "2362000 7089\n", + .content = "682000 867\n" + "1018000 259\n" + "1210000 66\n" + "1364000 481\n" + "1498000 232\n" + "1652000 328\n" + "1863000 287\n" + "2093000 240\n" + "2362000 7089\n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/total_trans", @@ -891,16 +881,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/time_in_state", .size = 108, - .content = - "682000 926\n" - "1018000 272\n" - "1210000 100\n" - "1364000 534\n" - "1498000 253\n" - "1652000 368\n" - "1863000 299\n" - "2093000 246\n" - "2362000 7116\n", + .content = "682000 926\n" + "1018000 272\n" + "1210000 100\n" + "1364000 534\n" + "1498000 253\n" + "1652000 368\n" + "1863000 299\n" + "2093000 246\n" + "2362000 7116\n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/total_trans", @@ -1021,16 +1010,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/time_in_state", .size = 108, - .content = - "682000 941\n" - "1018000 313\n" - "1210000 117\n" - "1364000 548\n" - "1498000 264\n" - "1652000 379\n" - "1863000 310\n" - "2093000 253\n" - "2362000 7247\n", + .content = "682000 941\n" + "1018000 313\n" + "1210000 117\n" + "1364000 548\n" + "1498000 264\n" + "1652000 379\n" + "1863000 310\n" + "2093000 253\n" + "2362000 7247\n", }, { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/total_trans", @@ -1151,16 +1139,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/time_in_state", .size = 108, - .content = - "682000 941\n" - "1018000 313\n" - "1210000 117\n" - "1364000 548\n" - "1498000 264\n" - "1652000 379\n" - "1863000 310\n" - "2093000 253\n" - "2362000 7450\n", + .content = "682000 941\n" + "1018000 313\n" + "1210000 117\n" + "1364000 548\n" + "1498000 264\n" + "1652000 379\n" + "1863000 310\n" + "2093000 253\n" + "2362000 7450\n", }, { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/total_trans", @@ -1213,7 +1200,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "7\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -4425,6 +4412,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wifi.interface", .value = "wlan0", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/huawei-mate-20.cc b/test/mock/huawei-mate-20.cc index 0ba4c594..b5dcc062 100644 --- a/test/mock/huawei-mate-20.cc +++ b/test/mock/huawei-mate-20.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(8, cpuinfo_get_processors_count()); @@ -360,8 +359,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("HiSilicon Kirin 980", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "HiSilicon Kirin 980", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -403,59 +404,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -511,11 +512,11 @@ TEST(ISA, neon_fma) { } TEST(ISA, atomics) { - #if CPUINFO_ARCH_ARM - ASSERT_FALSE(cpuinfo_has_arm_atomics()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_TRUE(cpuinfo_has_arm_atomics()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_FALSE(cpuinfo_has_arm_atomics()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_TRUE(cpuinfo_has_arm_atomics()); +#endif } TEST(ISA, neon_rdm) { @@ -597,8 +598,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -662,8 +665,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -740,8 +745,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } @@ -805,8 +812,10 @@ TEST(L3, associativity) { TEST(L3, sets) { for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l3_cache(i)->size, - cpuinfo_get_l3_cache(i)->sets * cpuinfo_get_l3_cache(i)->line_size * cpuinfo_get_l3_cache(i)->partitions * cpuinfo_get_l3_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l3_cache(i)->size, + cpuinfo_get_l3_cache(i)->sets * cpuinfo_get_l3_cache(i)->line_size * + cpuinfo_get_l3_cache(i)->partitions * cpuinfo_get_l3_cache(i)->associativity); } } diff --git a/test/mock/huawei-mate-20.h b/test/mock/huawei-mate-20.h index 70e04dd8..da8dc94a 100644 --- a/test/mock/huawei-mate-20.h +++ b/test/mock/huawei-mate-20.h @@ -3,79 +3,78 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 1608, - .content = - "processor\t: 0\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x1\n" - "CPU part\t: 0xd05\n" - "CPU revision\t: 0\n" - "\n" - "processor\t: 1\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x1\n" - "CPU part\t: 0xd05\n" - "CPU revision\t: 0\n" - "\n" - "processor\t: 2\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x1\n" - "CPU part\t: 0xd05\n" - "CPU revision\t: 0\n" - "\n" - "processor\t: 3\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x1\n" - "CPU part\t: 0xd05\n" - "CPU revision\t: 0\n" - "\n" - "processor\t: 4\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" - "CPU implementer\t: 0x48\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x1\n" - "CPU part\t: 0xd40\n" - "CPU revision\t: 0\n" - "\n" - "processor\t: 5\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" - "CPU implementer\t: 0x48\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x1\n" - "CPU part\t: 0xd40\n" - "CPU revision\t: 0\n" - "\n" - "processor\t: 6\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" - "CPU implementer\t: 0x48\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x1\n" - "CPU part\t: 0xd40\n" - "CPU revision\t: 0\n" - "\n" - "processor\t: 7\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" - "CPU implementer\t: 0x48\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x1\n" - "CPU part\t: 0xd40\n" - "CPU revision\t: 0\n" - "\n", + .content = "processor\t: 0\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0xd05\n" + "CPU revision\t: 0\n" + "\n" + "processor\t: 1\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0xd05\n" + "CPU revision\t: 0\n" + "\n" + "processor\t: 2\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0xd05\n" + "CPU revision\t: 0\n" + "\n" + "processor\t: 3\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0xd05\n" + "CPU revision\t: 0\n" + "\n" + "processor\t: 4\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" + "CPU implementer\t: 0x48\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0xd40\n" + "CPU revision\t: 0\n" + "\n" + "processor\t: 5\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" + "CPU implementer\t: 0x48\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0xd40\n" + "CPU revision\t: 0\n" + "\n" + "processor\t: 6\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" + "CPU implementer\t: 0x48\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0xd40\n" + "CPU revision\t: 0\n" + "\n" + "processor\t: 7\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" + "CPU implementer\t: 0x48\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0xd40\n" + "CPU revision\t: 0\n" + "\n", }, #elif CPUINFO_ARCH_ARM { @@ -261,18 +260,17 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 139, - .content = - "830000 210230\n" - "980000 5490\n" - "1056000 388\n" - "1152000 777\n" - "1248000 3390\n" - "1325000 800\n" - "1421000 1754\n" - "1517000 673\n" - "1613000 6759\n" - "1709000 1696\n" - "1805000 5590\n", + .content = "830000 210230\n" + "980000 5490\n" + "1056000 388\n" + "1152000 777\n" + "1248000 3390\n" + "1325000 800\n" + "1421000 1754\n" + "1517000 673\n" + "1613000 6759\n" + "1709000 1696\n" + "1805000 5590\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -390,18 +388,17 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 139, - .content = - "830000 210358\n" - "980000 5510\n" - "1056000 388\n" - "1152000 777\n" - "1248000 3404\n" - "1325000 800\n" - "1421000 1760\n" - "1517000 673\n" - "1613000 6759\n" - "1709000 1696\n" - "1805000 5590\n", + .content = "830000 210358\n" + "980000 5510\n" + "1056000 388\n" + "1152000 777\n" + "1248000 3404\n" + "1325000 800\n" + "1421000 1760\n" + "1517000 673\n" + "1613000 6759\n" + "1709000 1696\n" + "1805000 5590\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -519,18 +516,17 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 139, - .content = - "830000 210488\n" - "980000 5536\n" - "1056000 394\n" - "1152000 777\n" - "1248000 3410\n" - "1325000 800\n" - "1421000 1764\n" - "1517000 673\n" - "1613000 6759\n" - "1709000 1696\n" - "1805000 5590\n", + .content = "830000 210488\n" + "980000 5536\n" + "1056000 394\n" + "1152000 777\n" + "1248000 3410\n" + "1325000 800\n" + "1421000 1764\n" + "1517000 673\n" + "1613000 6759\n" + "1709000 1696\n" + "1805000 5590\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -648,18 +644,17 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 139, - .content = - "830000 210606\n" - "980000 5556\n" - "1056000 394\n" - "1152000 785\n" - "1248000 3428\n" - "1325000 800\n" - "1421000 1764\n" - "1517000 673\n" - "1613000 6765\n" - "1709000 1696\n" - "1805000 5590\n", + .content = "830000 210606\n" + "980000 5556\n" + "1056000 394\n" + "1152000 785\n" + "1248000 3428\n" + "1325000 800\n" + "1421000 1764\n" + "1517000 673\n" + "1613000 6765\n" + "1709000 1696\n" + "1805000 5590\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -757,7 +752,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_available_frequencies", .size = 95, - .content = "826000 903000 1018000 1114000 1210000 1306000 1402000 1517000 1594000 1671000 1805000 1901000 \n", + .content = + "826000 903000 1018000 1114000 1210000 1306000 1402000 1517000 1594000 1671000 1805000 1901000 \n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_available_governors", @@ -777,19 +773,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/time_in_state", .size = 149, - .content = - "826000 217030\n" - "903000 393\n" - "1018000 728\n" - "1114000 316\n" - "1210000 200\n" - "1306000 1820\n" - "1402000 386\n" - "1517000 784\n" - "1594000 159\n" - "1671000 9174\n" - "1805000 1695\n" - "1901000 5547\n", + .content = "826000 217030\n" + "903000 393\n" + "1018000 728\n" + "1114000 316\n" + "1210000 200\n" + "1306000 1820\n" + "1402000 386\n" + "1517000 784\n" + "1594000 159\n" + "1671000 9174\n" + "1805000 1695\n" + "1901000 5547\n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/total_trans", @@ -888,7 +883,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_available_frequencies", .size = 95, - .content = "826000 903000 1018000 1114000 1210000 1306000 1402000 1517000 1594000 1671000 1805000 1901000 \n", + .content = + "826000 903000 1018000 1114000 1210000 1306000 1402000 1517000 1594000 1671000 1805000 1901000 \n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_available_governors", @@ -908,19 +904,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/time_in_state", .size = 149, - .content = - "826000 217210\n" - "903000 393\n" - "1018000 728\n" - "1114000 316\n" - "1210000 200\n" - "1306000 1820\n" - "1402000 386\n" - "1517000 784\n" - "1594000 159\n" - "1671000 9174\n" - "1805000 1695\n" - "1901000 5547\n", + .content = "826000 217210\n" + "903000 393\n" + "1018000 728\n" + "1114000 316\n" + "1210000 200\n" + "1306000 1820\n" + "1402000 386\n" + "1517000 784\n" + "1594000 159\n" + "1671000 9174\n" + "1805000 1695\n" + "1901000 5547\n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/total_trans", @@ -1019,7 +1014,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_available_frequencies", .size = 105, - .content = "1460000 1594000 1671000 1767000 1863000 1959000 2036000 2112000 2208000 2304000 2420000 2496000 2600000 \n", + .content = + "1460000 1594000 1671000 1767000 1863000 1959000 2036000 2112000 2208000 2304000 2420000 2496000 2600000 \n", }, { .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_available_governors", @@ -1039,20 +1035,19 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/time_in_state", .size = 162, - .content = - "1460000 224532\n" - "1594000 224\n" - "1671000 266\n" - "1767000 2223\n" - "1863000 566\n" - "1959000 1390\n" - "2036000 544\n" - "2112000 476\n" - "2208000 427\n" - "2304000 636\n" - "2420000 312\n" - "2496000 189\n" - "2600000 6810\n", + .content = "1460000 224532\n" + "1594000 224\n" + "1671000 266\n" + "1767000 2223\n" + "1863000 566\n" + "1959000 1390\n" + "2036000 544\n" + "2112000 476\n" + "2208000 427\n" + "2304000 636\n" + "2420000 312\n" + "2496000 189\n" + "2600000 6810\n", }, { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/total_trans", @@ -1152,7 +1147,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_available_frequencies", .size = 105, - .content = "1460000 1594000 1671000 1767000 1863000 1959000 2036000 2112000 2208000 2304000 2420000 2496000 2600000 \n", + .content = + "1460000 1594000 1671000 1767000 1863000 1959000 2036000 2112000 2208000 2304000 2420000 2496000 2600000 \n", }, { .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_available_governors", @@ -1172,20 +1168,19 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/time_in_state", .size = 162, - .content = - "1460000 224720\n" - "1594000 224\n" - "1671000 266\n" - "1767000 2223\n" - "1863000 566\n" - "1959000 1390\n" - "2036000 544\n" - "2112000 476\n" - "2208000 427\n" - "2304000 636\n" - "2420000 312\n" - "2496000 189\n" - "2600000 6810\n", + .content = "1460000 224720\n" + "1594000 224\n" + "1671000 266\n" + "1767000 2223\n" + "1863000 566\n" + "1959000 1390\n" + "2036000 544\n" + "2112000 476\n" + "2208000 427\n" + "2304000 636\n" + "2420000 312\n" + "2496000 189\n" + "2600000 6810\n", }, { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/total_trans", @@ -1252,7 +1247,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "7\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -4324,6 +4319,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wifi.interface", .value = "wlan0", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/huawei-mate-8.cc b/test/mock/huawei-mate-8.cc index 0922c7f3..287326ed 100644 --- a/test/mock/huawei-mate-8.cc +++ b/test/mock/huawei-mate-8.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(8, cpuinfo_get_processors_count()); @@ -334,8 +333,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("HiSilicon Kirin 950", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "HiSilicon Kirin 950", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -377,59 +378,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -580,8 +581,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -645,8 +648,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -704,8 +709,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/huawei-mate-8.h b/test/mock/huawei-mate-8.h index d1e049f6..f84916b6 100644 --- a/test/mock/huawei-mate-8.h +++ b/test/mock/huawei-mate-8.h @@ -3,80 +3,79 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 1486, - .content = - "Processor\t: AArch64 Processor rev 0 (aarch64)\n" - "processor\t: 0\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 1\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 2\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 3\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 4\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd08\n" - "CPU revision\t: 0\n" - "\n" - "processor\t: 5\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd08\n" - "CPU revision\t: 0\n" - "\n" - "processor\t: 6\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd08\n" - "CPU revision\t: 0\n" - "\n" - "processor\t: 7\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd08\n" - "CPU revision\t: 0\n" - "\n", + .content = "Processor\t: AArch64 Processor rev 0 (aarch64)\n" + "processor\t: 0\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 1\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 2\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 3\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 4\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd08\n" + "CPU revision\t: 0\n" + "\n" + "processor\t: 5\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd08\n" + "CPU revision\t: 0\n" + "\n" + "processor\t: 6\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd08\n" + "CPU revision\t: 0\n" + "\n" + "processor\t: 7\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd08\n" + "CPU revision\t: 0\n" + "\n", }, #elif CPUINFO_ARCH_ARM { @@ -332,13 +331,12 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 66, - .content = - "480000 721\n" - "807000 5\n" - "1018000 0\n" - "1306000 641\n" - "1517000 53\n" - "1805000 3868\n", + .content = "480000 721\n" + "807000 5\n" + "1018000 0\n" + "1306000 641\n" + "1517000 53\n" + "1805000 3868\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -348,15 +346,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/trans_table", .size = 521, - .content = - " From : To\n" - " : 480000 807000 1018000 1306000 1517000 1805000 \n" - " 480000: 0 0 0 21 0 0 \n" - " 807000: 0 0 0 1 0 0 \n" - " 1018000: 0 0 0 0 0 0 \n" - " 1306000: 12 0 0 0 4 7 \n" - " 1517000: 1 1 0 1 0 3 \n" - " 1805000: 8 0 0 1 2 0 \n", + .content = " From : To\n" + " : 480000 807000 1018000 1306000 1517000 1805000 \n" + " 480000: 0 0 0 21 0 0 \n" + " 807000: 0 0 0 1 0 0 \n" + " 1018000: 0 0 0 0 0 0 \n" + " 1306000: 12 0 0 0 4 7 \n" + " 1517000: 1 1 0 1 0 3 \n" + " 1805000: 8 0 0 1 2 0 \n", }, { .path = "/sys/devices/system/cpu/cpu0/topology/core_id", @@ -451,13 +448,12 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 66, - .content = - "480000 879\n" - "807000 5\n" - "1018000 0\n" - "1306000 685\n" - "1517000 53\n" - "1805000 3887\n", + .content = "480000 879\n" + "807000 5\n" + "1018000 0\n" + "1306000 685\n" + "1517000 53\n" + "1805000 3887\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -467,15 +463,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/trans_table", .size = 521, - .content = - " From : To\n" - " : 480000 807000 1018000 1306000 1517000 1805000 \n" - " 480000: 0 0 0 22 0 0 \n" - " 807000: 0 0 0 1 0 0 \n" - " 1018000: 0 0 0 0 0 0 \n" - " 1306000: 13 0 0 0 4 8 \n" - " 1517000: 1 1 0 1 0 3 \n" - " 1805000: 9 0 0 1 2 0 \n", + .content = " From : To\n" + " : 480000 807000 1018000 1306000 1517000 1805000 \n" + " 480000: 0 0 0 22 0 0 \n" + " 807000: 0 0 0 1 0 0 \n" + " 1018000: 0 0 0 0 0 0 \n" + " 1306000: 13 0 0 0 4 8 \n" + " 1517000: 1 1 0 1 0 3 \n" + " 1805000: 9 0 0 1 2 0 \n", }, { .path = "/sys/devices/system/cpu/cpu1/topology/core_id", @@ -570,13 +565,12 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 67, - .content = - "480000 1044\n" - "807000 5\n" - "1018000 0\n" - "1306000 742\n" - "1517000 53\n" - "1805000 3887\n", + .content = "480000 1044\n" + "807000 5\n" + "1018000 0\n" + "1306000 742\n" + "1517000 53\n" + "1805000 3887\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -586,15 +580,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/trans_table", .size = 521, - .content = - " From : To\n" - " : 480000 807000 1018000 1306000 1517000 1805000 \n" - " 480000: 0 0 0 24 0 0 \n" - " 807000: 0 0 0 1 0 0 \n" - " 1018000: 0 0 0 0 0 0 \n" - " 1306000: 15 0 0 0 4 8 \n" - " 1517000: 1 1 0 1 0 3 \n" - " 1805000: 9 0 0 1 2 0 \n", + .content = " From : To\n" + " : 480000 807000 1018000 1306000 1517000 1805000 \n" + " 480000: 0 0 0 24 0 0 \n" + " 807000: 0 0 0 1 0 0 \n" + " 1018000: 0 0 0 0 0 0 \n" + " 1306000: 15 0 0 0 4 8 \n" + " 1517000: 1 1 0 1 0 3 \n" + " 1805000: 9 0 0 1 2 0 \n", }, { .path = "/sys/devices/system/cpu/cpu2/topology/core_id", @@ -689,13 +682,12 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 67, - .content = - "480000 1205\n" - "807000 8\n" - "1018000 0\n" - "1306000 753\n" - "1517000 55\n" - "1805000 3937\n", + .content = "480000 1205\n" + "807000 8\n" + "1018000 0\n" + "1306000 753\n" + "1517000 55\n" + "1805000 3937\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -705,15 +697,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/trans_table", .size = 521, - .content = - " From : To\n" - " : 480000 807000 1018000 1306000 1517000 1805000 \n" - " 480000: 0 0 0 26 0 0 \n" - " 807000: 0 0 0 2 0 0 \n" - " 1018000: 0 0 0 0 0 0 \n" - " 1306000: 15 0 0 0 5 10 \n" - " 1517000: 1 1 0 1 0 4 \n" - " 1805000: 10 1 0 1 2 0 \n", + .content = " From : To\n" + " : 480000 807000 1018000 1306000 1517000 1805000 \n" + " 480000: 0 0 0 26 0 0 \n" + " 807000: 0 0 0 2 0 0 \n" + " 1018000: 0 0 0 0 0 0 \n" + " 1306000: 15 0 0 0 5 10 \n" + " 1517000: 1 1 0 1 0 4 \n" + " 1805000: 10 1 0 1 2 0 \n", }, { .path = "/sys/devices/system/cpu/cpu3/topology/core_id", @@ -813,14 +804,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/time_in_state", .size = 79, - .content = - "480000 0\n" - "807000 3016\n" - "1210000 349\n" - "1517000 46\n" - "1805000 5\n" - "2016000 140\n" - "2304000 2629\n", + .content = "480000 0\n" + "807000 3016\n" + "1210000 349\n" + "1517000 46\n" + "1805000 5\n" + "2016000 140\n" + "2304000 2629\n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/total_trans", @@ -830,16 +820,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/trans_table", .size = 673, - .content = - " From : To\n" - " : 480000 807000 1210000 1517000 1805000 2016000 2304000 \n" - " 480000: 0 0 0 0 0 0 0 \n" - " 807000: 0 0 20 0 0 2 0 \n" - " 1210000: 0 8 0 13 0 2 0 \n" - " 1517000: 0 1 1 0 2 9 1 \n" - " 1805000: 0 0 0 0 0 1 1 \n" - " 2016000: 0 6 1 0 0 0 9 \n" - " 2304000: 0 8 1 0 0 2 0 \n", + .content = " From : To\n" + " : 480000 807000 1210000 1517000 1805000 2016000 2304000 \n" + " 480000: 0 0 0 0 0 0 0 \n" + " 807000: 0 0 20 0 0 2 0 \n" + " 1210000: 0 8 0 13 0 2 0 \n" + " 1517000: 0 1 1 0 2 9 1 \n" + " 1805000: 0 0 0 0 0 1 1 \n" + " 2016000: 0 6 1 0 0 0 9 \n" + " 2304000: 0 8 1 0 0 2 0 \n", }, { .path = "/sys/devices/system/cpu/cpu4/topology/core_id", @@ -939,14 +928,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/time_in_state", .size = 79, - .content = - "480000 0\n" - "807000 3229\n" - "1210000 359\n" - "1517000 46\n" - "1805000 5\n" - "2016000 140\n" - "2304000 2629\n", + .content = "480000 0\n" + "807000 3229\n" + "1210000 359\n" + "1517000 46\n" + "1805000 5\n" + "2016000 140\n" + "2304000 2629\n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/total_trans", @@ -956,16 +944,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/trans_table", .size = 673, - .content = - " From : To\n" - " : 480000 807000 1210000 1517000 1805000 2016000 2304000 \n" - " 480000: 0 0 0 0 0 0 0 \n" - " 807000: 0 0 21 0 0 2 0 \n" - " 1210000: 0 9 0 13 0 2 0 \n" - " 1517000: 0 1 1 0 2 9 1 \n" - " 1805000: 0 0 0 0 0 1 1 \n" - " 2016000: 0 6 1 0 0 0 9 \n" - " 2304000: 0 8 1 0 0 2 0 \n", + .content = " From : To\n" + " : 480000 807000 1210000 1517000 1805000 2016000 2304000 \n" + " 480000: 0 0 0 0 0 0 0 \n" + " 807000: 0 0 21 0 0 2 0 \n" + " 1210000: 0 9 0 13 0 2 0 \n" + " 1517000: 0 1 1 0 2 9 1 \n" + " 1805000: 0 0 0 0 0 1 1 \n" + " 2016000: 0 6 1 0 0 0 9 \n" + " 2304000: 0 8 1 0 0 2 0 \n", }, { .path = "/sys/devices/system/cpu/cpu5/topology/core_id", @@ -1065,14 +1052,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/time_in_state", .size = 79, - .content = - "480000 0\n" - "807000 3456\n" - "1210000 360\n" - "1517000 46\n" - "1805000 5\n" - "2016000 140\n" - "2304000 2629\n", + .content = "480000 0\n" + "807000 3456\n" + "1210000 360\n" + "1517000 46\n" + "1805000 5\n" + "2016000 140\n" + "2304000 2629\n", }, { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/total_trans", @@ -1082,16 +1068,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/trans_table", .size = 673, - .content = - " From : To\n" - " : 480000 807000 1210000 1517000 1805000 2016000 2304000 \n" - " 480000: 0 0 0 0 0 0 0 \n" - " 807000: 0 0 21 0 0 2 0 \n" - " 1210000: 0 9 0 13 0 2 0 \n" - " 1517000: 0 1 1 0 2 9 1 \n" - " 1805000: 0 0 0 0 0 1 1 \n" - " 2016000: 0 6 1 0 0 0 9 \n" - " 2304000: 0 8 1 0 0 2 0 \n", + .content = " From : To\n" + " : 480000 807000 1210000 1517000 1805000 2016000 2304000 \n" + " 480000: 0 0 0 0 0 0 0 \n" + " 807000: 0 0 21 0 0 2 0 \n" + " 1210000: 0 9 0 13 0 2 0 \n" + " 1517000: 0 1 1 0 2 9 1 \n" + " 1805000: 0 0 0 0 0 1 1 \n" + " 2016000: 0 6 1 0 0 0 9 \n" + " 2304000: 0 8 1 0 0 2 0 \n", }, { .path = "/sys/devices/system/cpu/cpu6/topology/core_id", @@ -1191,14 +1176,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/time_in_state", .size = 79, - .content = - "480000 0\n" - "807000 3684\n" - "1210000 370\n" - "1517000 46\n" - "1805000 5\n" - "2016000 140\n" - "2304000 2629\n", + .content = "480000 0\n" + "807000 3684\n" + "1210000 370\n" + "1517000 46\n" + "1805000 5\n" + "2016000 140\n" + "2304000 2629\n", }, { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/total_trans", @@ -1208,16 +1192,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/trans_table", .size = 673, - .content = - " From : To\n" - " : 480000 807000 1210000 1517000 1805000 2016000 2304000 \n" - " 480000: 0 0 0 0 0 0 0 \n" - " 807000: 0 0 22 0 0 2 0 \n" - " 1210000: 0 10 0 13 0 2 0 \n" - " 1517000: 0 1 1 0 2 9 1 \n" - " 1805000: 0 0 0 0 0 1 1 \n" - " 2016000: 0 6 1 0 0 0 9 \n" - " 2304000: 0 8 1 0 0 2 0 \n", + .content = " From : To\n" + " : 480000 807000 1210000 1517000 1805000 2016000 2304000 \n" + " 480000: 0 0 0 0 0 0 0 \n" + " 807000: 0 0 22 0 0 2 0 \n" + " 1210000: 0 10 0 13 0 2 0 \n" + " 1517000: 0 1 1 0 2 9 1 \n" + " 1805000: 0 0 0 0 0 1 1 \n" + " 2016000: 0 6 1 0 0 0 9 \n" + " 2304000: 0 8 1 0 0 2 0 \n", }, { .path = "/sys/devices/system/cpu/cpu7/topology/core_id", @@ -1249,7 +1232,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "7\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -3765,6 +3748,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.driver.status", .value = "ok", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/huawei-mate-9.cc b/test/mock/huawei-mate-9.cc index 703b7e0d..90c9625c 100644 --- a/test/mock/huawei-mate-9.cc +++ b/test/mock/huawei-mate-9.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(8, cpuinfo_get_processors_count()); @@ -334,8 +333,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("HiSilicon Kirin 960", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "HiSilicon Kirin 960", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -377,59 +378,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -580,8 +581,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -658,8 +661,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -717,8 +722,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/huawei-mate-9.h b/test/mock/huawei-mate-9.h index 9f00d50b..9a74d119 100644 --- a/test/mock/huawei-mate-9.h +++ b/test/mock/huawei-mate-9.h @@ -3,80 +3,79 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 1486, - .content = - "Processor\t: AArch64 Processor rev 1 (aarch64)\n" - "processor\t: 0\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 1\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 2\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 3\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 4\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd09\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 5\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd09\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 6\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd09\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 7\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd09\n" - "CPU revision\t: 1\n" - "\n", + .content = "Processor\t: AArch64 Processor rev 1 (aarch64)\n" + "processor\t: 0\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 1\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 2\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 3\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 4\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd09\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 5\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd09\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 6\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd09\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 7\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd09\n" + "CPU revision\t: 1\n" + "\n", }, #elif CPUINFO_ARCH_ARM { @@ -334,12 +333,11 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 60, - .content = - "533000 1865\n" - "999000 78\n" - "1402000 1860\n" - "1709000 231\n" - "1844000 7168\n", + .content = "533000 1865\n" + "999000 78\n" + "1402000 1860\n" + "1709000 231\n" + "1844000 7168\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -349,14 +347,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/trans_table", .size = 389, - .content = - " From : To\n" - " : 533000 999000 1402000 1709000 1844000 \n" - " 533000: 0 0 47 0 0 \n" - " 999000: 4 0 3 0 0 \n" - " 1402000: 29 3 0 32 3 \n" - " 1709000: 6 2 11 0 22 \n" - " 1844000: 9 2 6 9 0 \n", + .content = " From : To\n" + " : 533000 999000 1402000 1709000 1844000 \n" + " 533000: 0 0 47 0 0 \n" + " 999000: 4 0 3 0 0 \n" + " 1402000: 29 3 0 32 3 \n" + " 1709000: 6 2 11 0 22 \n" + " 1844000: 9 2 6 9 0 \n", }, { .path = "/sys/devices/system/cpu/cpu0/topology/core_id", @@ -451,12 +448,11 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 60, - .content = - "533000 2045\n" - "999000 78\n" - "1402000 1898\n" - "1709000 231\n" - "1844000 7168\n", + .content = "533000 2045\n" + "999000 78\n" + "1402000 1898\n" + "1709000 231\n" + "1844000 7168\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -466,14 +462,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/trans_table", .size = 389, - .content = - " From : To\n" - " : 533000 999000 1402000 1709000 1844000 \n" - " 533000: 0 0 48 0 0 \n" - " 999000: 4 0 3 0 0 \n" - " 1402000: 30 3 0 32 3 \n" - " 1709000: 6 2 11 0 22 \n" - " 1844000: 9 2 6 9 0 \n", + .content = " From : To\n" + " : 533000 999000 1402000 1709000 1844000 \n" + " 533000: 0 0 48 0 0 \n" + " 999000: 4 0 3 0 0 \n" + " 1402000: 30 3 0 32 3 \n" + " 1709000: 6 2 11 0 22 \n" + " 1844000: 9 2 6 9 0 \n", }, { .path = "/sys/devices/system/cpu/cpu1/topology/core_id", @@ -568,12 +563,11 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 60, - .content = - "533000 2218\n" - "999000 78\n" - "1402000 1932\n" - "1709000 234\n" - "1844000 7179\n", + .content = "533000 2218\n" + "999000 78\n" + "1402000 1932\n" + "1709000 234\n" + "1844000 7179\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -583,14 +577,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/trans_table", .size = 389, - .content = - " From : To\n" - " : 533000 999000 1402000 1709000 1844000 \n" - " 533000: 0 0 50 0 0 \n" - " 999000: 4 0 3 0 0 \n" - " 1402000: 31 3 0 33 3 \n" - " 1709000: 6 2 11 0 23 \n" - " 1844000: 10 2 6 9 0 \n", + .content = " From : To\n" + " : 533000 999000 1402000 1709000 1844000 \n" + " 533000: 0 0 50 0 0 \n" + " 999000: 4 0 3 0 0 \n" + " 1402000: 31 3 0 33 3 \n" + " 1709000: 6 2 11 0 23 \n" + " 1844000: 10 2 6 9 0 \n", }, { .path = "/sys/devices/system/cpu/cpu2/topology/core_id", @@ -685,12 +678,11 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 60, - .content = - "533000 2442\n" - "999000 78\n" - "1402000 1937\n" - "1709000 234\n" - "1844000 7179\n", + .content = "533000 2442\n" + "999000 78\n" + "1402000 1937\n" + "1709000 234\n" + "1844000 7179\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -700,14 +692,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/trans_table", .size = 389, - .content = - " From : To\n" - " : 533000 999000 1402000 1709000 1844000 \n" - " 533000: 0 0 50 0 0 \n" - " 999000: 4 0 3 0 0 \n" - " 1402000: 31 3 0 33 3 \n" - " 1709000: 6 2 11 0 23 \n" - " 1844000: 10 2 6 9 0 \n", + .content = " From : To\n" + " : 533000 999000 1402000 1709000 1844000 \n" + " 533000: 0 0 50 0 0 \n" + " 999000: 4 0 3 0 0 \n" + " 1402000: 31 3 0 33 3 \n" + " 1709000: 6 2 11 0 23 \n" + " 1844000: 10 2 6 9 0 \n", }, { .path = "/sys/devices/system/cpu/cpu3/topology/core_id", @@ -807,12 +798,11 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/time_in_state", .size = 60, - .content = - "903000 6470\n" - "1421000 63\n" - "1805000 522\n" - "2112000 264\n" - "2362000 4777\n", + .content = "903000 6470\n" + "1421000 63\n" + "1805000 522\n" + "2112000 264\n" + "2362000 4777\n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/total_trans", @@ -822,14 +812,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/trans_table", .size = 389, - .content = - " From : To\n" - " : 903000 1421000 1805000 2112000 2362000 \n" - " 903000: 0 0 59 2 3 \n" - " 1421000: 3 0 6 0 2 \n" - " 1805000: 15 5 0 2 49 \n" - " 2112000: 2 0 0 0 8 \n" - " 2362000: 45 5 6 6 0 \n", + .content = " From : To\n" + " : 903000 1421000 1805000 2112000 2362000 \n" + " 903000: 0 0 59 2 3 \n" + " 1421000: 3 0 6 0 2 \n" + " 1805000: 15 5 0 2 49 \n" + " 2112000: 2 0 0 0 8 \n" + " 2362000: 45 5 6 6 0 \n", }, { .path = "/sys/devices/system/cpu/cpu4/topology/core_id", @@ -929,12 +918,11 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/time_in_state", .size = 60, - .content = - "903000 6703\n" - "1421000 63\n" - "1805000 522\n" - "2112000 264\n" - "2362000 4777\n", + .content = "903000 6703\n" + "1421000 63\n" + "1805000 522\n" + "2112000 264\n" + "2362000 4777\n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/total_trans", @@ -944,14 +932,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/trans_table", .size = 389, - .content = - " From : To\n" - " : 903000 1421000 1805000 2112000 2362000 \n" - " 903000: 0 0 59 2 3 \n" - " 1421000: 3 0 6 0 2 \n" - " 1805000: 15 5 0 2 49 \n" - " 2112000: 2 0 0 0 8 \n" - " 2362000: 45 5 6 6 0 \n", + .content = " From : To\n" + " : 903000 1421000 1805000 2112000 2362000 \n" + " 903000: 0 0 59 2 3 \n" + " 1421000: 3 0 6 0 2 \n" + " 1805000: 15 5 0 2 49 \n" + " 2112000: 2 0 0 0 8 \n" + " 2362000: 45 5 6 6 0 \n", }, { .path = "/sys/devices/system/cpu/cpu5/topology/core_id", @@ -1051,12 +1038,11 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/time_in_state", .size = 60, - .content = - "903000 6909\n" - "1421000 63\n" - "1805000 526\n" - "2112000 266\n" - "2362000 4804\n", + .content = "903000 6909\n" + "1421000 63\n" + "1805000 526\n" + "2112000 266\n" + "2362000 4804\n", }, { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/total_trans", @@ -1066,14 +1052,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/trans_table", .size = 389, - .content = - " From : To\n" - " : 903000 1421000 1805000 2112000 2362000 \n" - " 903000: 0 0 61 2 3 \n" - " 1421000: 3 0 6 0 2 \n" - " 1805000: 15 5 0 3 50 \n" - " 2112000: 2 0 0 0 9 \n" - " 2362000: 46 5 6 6 0 \n", + .content = " From : To\n" + " : 903000 1421000 1805000 2112000 2362000 \n" + " 903000: 0 0 61 2 3 \n" + " 1421000: 3 0 6 0 2 \n" + " 1805000: 15 5 0 3 50 \n" + " 2112000: 2 0 0 0 9 \n" + " 2362000: 46 5 6 6 0 \n", }, { .path = "/sys/devices/system/cpu/cpu6/topology/core_id", @@ -1173,12 +1158,11 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/time_in_state", .size = 60, - .content = - "903000 7079\n" - "1421000 63\n" - "1805000 526\n" - "2112000 266\n" - "2362000 4863\n", + .content = "903000 7079\n" + "1421000 63\n" + "1805000 526\n" + "2112000 266\n" + "2362000 4863\n", }, { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/total_trans", @@ -1188,14 +1172,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/trans_table", .size = 389, - .content = - " From : To\n" - " : 903000 1421000 1805000 2112000 2362000 \n" - " 903000: 0 0 61 2 3 \n" - " 1421000: 3 0 6 0 2 \n" - " 1805000: 15 5 0 3 50 \n" - " 2112000: 2 0 0 0 9 \n" - " 2362000: 47 5 6 6 0 \n", + .content = " From : To\n" + " : 903000 1421000 1805000 2112000 2362000 \n" + " 903000: 0 0 61 2 3 \n" + " 1421000: 3 0 6 0 2 \n" + " 1805000: 15 5 0 3 50 \n" + " 2112000: 2 0 0 0 9 \n" + " 2362000: 47 5 6 6 0 \n", }, { .path = "/sys/devices/system/cpu/cpu7/topology/core_id", @@ -1227,7 +1210,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "7\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -3855,6 +3838,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.driver.status", .value = "ok", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/huawei-p20-pro.cc b/test/mock/huawei-p20-pro.cc index 93568b58..74284709 100644 --- a/test/mock/huawei-p20-pro.cc +++ b/test/mock/huawei-p20-pro.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(8, cpuinfo_get_processors_count()); @@ -334,8 +333,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("HiSilicon Kirin 970", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "HiSilicon Kirin 970", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -377,59 +378,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -580,8 +581,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -658,8 +661,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -717,8 +722,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/huawei-p20-pro.h b/test/mock/huawei-p20-pro.h index bd6d2e5c..bc2962c9 100644 --- a/test/mock/huawei-p20-pro.h +++ b/test/mock/huawei-p20-pro.h @@ -3,79 +3,78 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 1440, - .content = - "processor\t: 0\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 1\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 2\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 3\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 4\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd09\n" - "CPU revision\t: 2\n" - "\n" - "processor\t: 5\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd09\n" - "CPU revision\t: 2\n" - "\n" - "processor\t: 6\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd09\n" - "CPU revision\t: 2\n" - "\n" - "processor\t: 7\n" - "BogoMIPS\t: 3.84\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd09\n" - "CPU revision\t: 2\n" - "\n", + .content = "processor\t: 0\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 1\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 2\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 3\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 4\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd09\n" + "CPU revision\t: 2\n" + "\n" + "processor\t: 5\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd09\n" + "CPU revision\t: 2\n" + "\n" + "processor\t: 6\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd09\n" + "CPU revision\t: 2\n" + "\n" + "processor\t: 7\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd09\n" + "CPU revision\t: 2\n" + "\n", }, #elif CPUINFO_ARCH_ARM { @@ -271,14 +270,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 89, - .content = - "509000 27173\n" - "1018000 2729\n" - "1210000 184\n" - "1402000 1366\n" - "1556000 446\n" - "1690000 1044\n" - "1844000 5229\n", + .content = "509000 27173\n" + "1018000 2729\n" + "1210000 184\n" + "1402000 1366\n" + "1556000 446\n" + "1690000 1044\n" + "1844000 5229\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -288,16 +286,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/trans_table", .size = 673, - .content = - " From : To\n" - " : 509000 1018000 1210000 1402000 1556000 1690000 1844000 \n" - " 509000: 0 47 0 67 0 2 0 \n" - " 1018000: 22 0 28 67 0 2 0 \n" - " 1210000: 3 5 0 24 0 0 0 \n" - " 1402000: 32 36 1 0 59 40 0 \n" - " 1556000: 18 3 0 1 0 42 0 \n" - " 1690000: 14 13 2 1 0 0 63 \n" - " 1844000: 28 15 1 8 5 6 0 \n", + .content = " From : To\n" + " : 509000 1018000 1210000 1402000 1556000 1690000 1844000 \n" + " 509000: 0 47 0 67 0 2 0 \n" + " 1018000: 22 0 28 67 0 2 0 \n" + " 1210000: 3 5 0 24 0 0 0 \n" + " 1402000: 32 36 1 0 59 40 0 \n" + " 1556000: 18 3 0 1 0 42 0 \n" + " 1690000: 14 13 2 1 0 0 63 \n" + " 1844000: 28 15 1 8 5 6 0 \n", }, { .path = "/sys/devices/system/cpu/cpu0/topology/core_id", @@ -392,14 +389,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 89, - .content = - "509000 27380\n" - "1018000 2729\n" - "1210000 184\n" - "1402000 1366\n" - "1556000 446\n" - "1690000 1044\n" - "1844000 5229\n", + .content = "509000 27380\n" + "1018000 2729\n" + "1210000 184\n" + "1402000 1366\n" + "1556000 446\n" + "1690000 1044\n" + "1844000 5229\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -409,16 +405,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/trans_table", .size = 673, - .content = - " From : To\n" - " : 509000 1018000 1210000 1402000 1556000 1690000 1844000 \n" - " 509000: 0 47 0 67 0 2 0 \n" - " 1018000: 22 0 28 67 0 2 0 \n" - " 1210000: 3 5 0 24 0 0 0 \n" - " 1402000: 32 36 1 0 59 40 0 \n" - " 1556000: 18 3 0 1 0 42 0 \n" - " 1690000: 14 13 2 1 0 0 63 \n" - " 1844000: 28 15 1 8 5 6 0 \n", + .content = " From : To\n" + " : 509000 1018000 1210000 1402000 1556000 1690000 1844000 \n" + " 509000: 0 47 0 67 0 2 0 \n" + " 1018000: 22 0 28 67 0 2 0 \n" + " 1210000: 3 5 0 24 0 0 0 \n" + " 1402000: 32 36 1 0 59 40 0 \n" + " 1556000: 18 3 0 1 0 42 0 \n" + " 1690000: 14 13 2 1 0 0 63 \n" + " 1844000: 28 15 1 8 5 6 0 \n", }, { .path = "/sys/devices/system/cpu/cpu1/topology/core_id", @@ -513,14 +508,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 89, - .content = - "509000 27589\n" - "1018000 2729\n" - "1210000 184\n" - "1402000 1366\n" - "1556000 446\n" - "1690000 1044\n" - "1844000 5229\n", + .content = "509000 27589\n" + "1018000 2729\n" + "1210000 184\n" + "1402000 1366\n" + "1556000 446\n" + "1690000 1044\n" + "1844000 5229\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -530,16 +524,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/trans_table", .size = 673, - .content = - " From : To\n" - " : 509000 1018000 1210000 1402000 1556000 1690000 1844000 \n" - " 509000: 0 47 0 67 0 2 0 \n" - " 1018000: 22 0 28 67 0 2 0 \n" - " 1210000: 3 5 0 24 0 0 0 \n" - " 1402000: 32 36 1 0 59 40 0 \n" - " 1556000: 18 3 0 1 0 42 0 \n" - " 1690000: 14 13 2 1 0 0 63 \n" - " 1844000: 28 15 1 8 5 6 0 \n", + .content = " From : To\n" + " : 509000 1018000 1210000 1402000 1556000 1690000 1844000 \n" + " 509000: 0 47 0 67 0 2 0 \n" + " 1018000: 22 0 28 67 0 2 0 \n" + " 1210000: 3 5 0 24 0 0 0 \n" + " 1402000: 32 36 1 0 59 40 0 \n" + " 1556000: 18 3 0 1 0 42 0 \n" + " 1690000: 14 13 2 1 0 0 63 \n" + " 1844000: 28 15 1 8 5 6 0 \n", }, { .path = "/sys/devices/system/cpu/cpu2/topology/core_id", @@ -634,14 +627,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 89, - .content = - "509000 27803\n" - "1018000 2729\n" - "1210000 184\n" - "1402000 1366\n" - "1556000 446\n" - "1690000 1044\n" - "1844000 5229\n", + .content = "509000 27803\n" + "1018000 2729\n" + "1210000 184\n" + "1402000 1366\n" + "1556000 446\n" + "1690000 1044\n" + "1844000 5229\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -651,16 +643,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/trans_table", .size = 673, - .content = - " From : To\n" - " : 509000 1018000 1210000 1402000 1556000 1690000 1844000 \n" - " 509000: 0 47 0 67 0 2 0 \n" - " 1018000: 22 0 28 67 0 2 0 \n" - " 1210000: 3 5 0 24 0 0 0 \n" - " 1402000: 32 36 1 0 59 40 0 \n" - " 1556000: 18 3 0 1 0 42 0 \n" - " 1690000: 14 13 2 1 0 0 63 \n" - " 1844000: 28 15 1 8 5 6 0 \n", + .content = " From : To\n" + " : 509000 1018000 1210000 1402000 1556000 1690000 1844000 \n" + " 509000: 0 47 0 67 0 2 0 \n" + " 1018000: 22 0 28 67 0 2 0 \n" + " 1210000: 3 5 0 24 0 0 0 \n" + " 1402000: 32 36 1 0 59 40 0 \n" + " 1556000: 18 3 0 1 0 42 0 \n" + " 1690000: 14 13 2 1 0 0 63 \n" + " 1844000: 28 15 1 8 5 6 0 \n", }, { .path = "/sys/devices/system/cpu/cpu3/topology/core_id", @@ -760,16 +751,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/time_in_state", .size = 109, - .content = - "682000 33445\n" - "1018000 417\n" - "1210000 89\n" - "1364000 777\n" - "1498000 359\n" - "1652000 380\n" - "1863000 313\n" - "2093000 376\n" - "2362000 2856\n", + .content = "682000 33445\n" + "1018000 417\n" + "1210000 89\n" + "1364000 777\n" + "1498000 359\n" + "1652000 380\n" + "1863000 313\n" + "2093000 376\n" + "2362000 2856\n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/total_trans", @@ -890,16 +880,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/time_in_state", .size = 109, - .content = - "682000 33660\n" - "1018000 417\n" - "1210000 89\n" - "1364000 777\n" - "1498000 359\n" - "1652000 380\n" - "1863000 313\n" - "2093000 376\n" - "2362000 2856\n", + .content = "682000 33660\n" + "1018000 417\n" + "1210000 89\n" + "1364000 777\n" + "1498000 359\n" + "1652000 380\n" + "1863000 313\n" + "2093000 376\n" + "2362000 2856\n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/total_trans", @@ -1020,16 +1009,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/time_in_state", .size = 109, - .content = - "682000 33874\n" - "1018000 417\n" - "1210000 89\n" - "1364000 777\n" - "1498000 359\n" - "1652000 380\n" - "1863000 313\n" - "2093000 376\n" - "2362000 2856\n", + .content = "682000 33874\n" + "1018000 417\n" + "1210000 89\n" + "1364000 777\n" + "1498000 359\n" + "1652000 380\n" + "1863000 313\n" + "2093000 376\n" + "2362000 2856\n", }, { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/total_trans", @@ -1150,16 +1138,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/time_in_state", .size = 109, - .content = - "682000 34092\n" - "1018000 417\n" - "1210000 89\n" - "1364000 777\n" - "1498000 359\n" - "1652000 380\n" - "1863000 313\n" - "2093000 376\n" - "2362000 2856\n", + .content = "682000 34092\n" + "1018000 417\n" + "1210000 89\n" + "1364000 777\n" + "1498000 359\n" + "1652000 380\n" + "1863000 313\n" + "2093000 376\n" + "2362000 2856\n", }, { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/total_trans", @@ -1212,7 +1199,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "7\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -4624,6 +4611,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wifi.interface", .value = "wlan0", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/huawei-p8-lite.cc b/test/mock/huawei-p8-lite.cc index 9b8548e0..d378dc8f 100644 --- a/test/mock/huawei-p8-lite.cc +++ b/test/mock/huawei-p8-lite.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(8, cpuinfo_get_processors_count()); @@ -261,8 +260,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("HiSilicon Kirin 620", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "HiSilicon Kirin 620", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -304,59 +305,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -481,8 +482,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -533,8 +536,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -585,8 +590,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/huawei-p8-lite.h b/test/mock/huawei-p8-lite.h index d0754bfa..f765c56e 100644 --- a/test/mock/huawei-p8-lite.h +++ b/test/mock/huawei-p8-lite.h @@ -3,24 +3,23 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 336, - .content = - "Processor\t: AArch64 Processor rev 3 (aarch64)\n" - "processor\t: 0\n" - "processor\t: 1\n" - "processor\t: 2\n" - "processor\t: 3\n" - "processor\t: 4\n" - "processor\t: 5\n" - "processor\t: 6\n" - "processor\t: 7\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: AArch64\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 3\n" - "\n" - "Hardware\t: hi6210sft\n", + .content = "Processor\t: AArch64 Processor rev 3 (aarch64)\n" + "processor\t: 0\n" + "processor\t: 1\n" + "processor\t: 2\n" + "processor\t: 3\n" + "processor\t: 4\n" + "processor\t: 5\n" + "processor\t: 6\n" + "processor\t: 7\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: AArch64\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 3\n" + "\n" + "Hardware\t: hi6210sft\n", }, #elif CPUINFO_ARCH_ARM { @@ -370,13 +369,12 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpufreq/all_time_in_state", .size = 201, - .content = - "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\t\n" - "208000\t\t561\t\t561\t\t561\t\t561\t\t\n" - "432000\t\t148\t\t148\t\t148\t\t148\t\t\n" - "729000\t\t86\t\t86\t\t86\t\t86\t\t\n" - "960000\t\t179\t\t179\t\t179\t\t179\t\t\n" - "1200000\t\t6037\t\t6037\t\t6037\t\t6037\t\t\n", + .content = "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\t\n" + "208000\t\t561\t\t561\t\t561\t\t561\t\t\n" + "432000\t\t148\t\t148\t\t148\t\t148\t\t\n" + "729000\t\t86\t\t86\t\t86\t\t86\t\t\n" + "960000\t\t179\t\t179\t\t179\t\t179\t\t\n" + "1200000\t\t6037\t\t6037\t\t6037\t\t6037\t\t\n", }, { .path = "/sys/devices/system/cpu/cpuidle/current_driver", @@ -451,12 +449,11 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 56, - .content = - "208000 705\n" - "432000 152\n" - "729000 86\n" - "960000 179\n" - "1200000 6037\n", + .content = "208000 705\n" + "432000 152\n" + "729000 86\n" + "960000 179\n" + "1200000 6037\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -556,12 +553,11 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 56, - .content = - "208000 940\n" - "432000 164\n" - "729000 86\n" - "960000 189\n" - "1200000 6051\n", + .content = "208000 940\n" + "432000 164\n" + "729000 86\n" + "960000 189\n" + "1200000 6051\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -661,12 +657,11 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 57, - .content = - "208000 1197\n" - "432000 172\n" - "729000 86\n" - "960000 189\n" - "1200000 6051\n", + .content = "208000 1197\n" + "432000 172\n" + "729000 86\n" + "960000 189\n" + "1200000 6051\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -766,12 +761,11 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 57, - .content = - "208000 1384\n" - "432000 181\n" - "729000 87\n" - "960000 202\n" - "1200000 6079\n", + .content = "208000 1384\n" + "432000 181\n" + "729000 87\n" + "960000 202\n" + "1200000 6079\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -928,7 +922,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "7\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -3012,6 +3006,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.driver.status", .value = "ok", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/huawei-p9-lite.cc b/test/mock/huawei-p9-lite.cc index 29db0d36..c0922f41 100644 --- a/test/mock/huawei-p9-lite.cc +++ b/test/mock/huawei-p9-lite.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(8, cpuinfo_get_processors_count()); @@ -294,8 +293,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("HiSilicon Kirin 650", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "HiSilicon Kirin 650", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -337,59 +338,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -514,8 +515,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -566,8 +569,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -618,8 +623,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/huawei-p9-lite.h b/test/mock/huawei-p9-lite.h index e5539b88..4ad9b9ba 100644 --- a/test/mock/huawei-p9-lite.h +++ b/test/mock/huawei-p9-lite.h @@ -3,24 +3,23 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 333, - .content = - "Processor\t: AArch64 Processor rev 4 (aarch64)\n" - "processor\t: 0\n" - "processor\t: 1\n" - "processor\t: 2\n" - "processor\t: 3\n" - "processor\t: 4\n" - "processor\t: 5\n" - "processor\t: 6\n" - "processor\t: 7\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: AArch64\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "Hardware\t: hi6250\n", + .content = "Processor\t: AArch64 Processor rev 4 (aarch64)\n" + "processor\t: 0\n" + "processor\t: 1\n" + "processor\t: 2\n" + "processor\t: 3\n" + "processor\t: 4\n" + "processor\t: 5\n" + "processor\t: 6\n" + "processor\t: 7\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: AArch64\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "Hardware\t: hi6250\n", }, #elif CPUINFO_ARCH_ARM { @@ -49,287 +48,286 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/system/build.prop", .size = 7249, - .content = - "\n" - "# begin build properties\n" - "# autogenerated by buildinfo.sh\n" - "ro.build.id=MRA58K\n" - "#ro.build.display.id=deleted\n" - "#ro.build.version.incremental=deleted\n" - "ro.build.version.sdk=23\n" - "ro.build.version.preview_sdk=0\n" - "ro.build.version.codename=REL\n" - "ro.build.version.all_codenames=REL\n" - "ro.build.version.release=6.0\n" - "ro.build.version.security_patch=2016-11-01\n" - "ro.build.version.base_os=\n" - "ro.build.date=Fri Nov 25 19:25:55 CST 2016\n" - "ro.build.date.utc=1480073155\n" - "ro.build.type=user\n" - "ro.build.user=jenkins\n" - "ro.build.host=huawei-RH2288H-V2-12L\n" - "ro.build.flavor=hi6250-user\n" - "ro.product.model=hi6250\n" - "ro.product.brand=HUAWEI\n" - "ro.product.name=hi6250\n" - "ro.product.device=HWVNS-H\n" - "# ro.product.cpu.abi and ro.product.cpu.abi2 are obsolete,\n" - "# use ro.product.cpu.abilist instead.\n" - "ro.product.cpu.abi=arm64-v8a\n" - "ro.product.cpu.abilist=arm64-v8a,armeabi-v7a,armeabi\n" - "ro.product.cpu.abilist32=armeabi-v7a,armeabi\n" - "ro.product.cpu.abilist64=arm64-v8a\n" - "ro.product.manufacturer=HUAWEI\n" - "ro.product.locale=en-US\n" - "ro.wifi.channels=\n" - "ro.board.platform=hi6250\n" - "# ro.build.product is obsolete; use ro.product.device\n" - "ro.build.product=hi6250\n" - "# Do not try to parse description, fingerprint, or thumbprint\n" - "#ro.build.description=deleted\n" - "#ro.build.fingerprint=deleted\n" - "ro.build.characteristics=nosdcard\n" - "ro.build.hide=false\n" - "# end build properties\n" - "\n" - "# begin huawei emui properties\n" - "# autogenerated by build_emui_info.sh\n" - "ro.build.hw_emui_api_level=10\n" - "# end huawei emui properties\n" - "\n" - "#\n" - "# from device/hisi/hi6250/system.prop\n" - "#\n" - "ro.config.mmu_en=1\n" - "dalvik.vm.heapsize=512m\n" - "ro.opengles.version=196609\n" - "ro.sf.lcd_density=480\n" - "hw.lcd.density=480\n" - "persist.fw.force_adoptable=true\n" - "dalvik.vm.checkjni=false\n" - "ro.bt.bdaddr_path=/data/misc/bluedroid/macbt\n" - "ro.config.hw_navigationbar=true\n" - "ro.hwui.texture_cache_size=48\n" - "ro.hwui.texture_cache_flushrate=0.4\n" - "ro.hwui.layer_cache_size=32\n" - "ro.hwui.path_cache_size=16\n" - "ro.hwui.shape_cache_size=2\n" - "ro.hwui.drop_shadow_cache_size=6\n" - "ro.hwui.gradient_cache_size=1\n" - "ro.hwui.text_large_cache_height=1024\n" - "ro.hwui.text_large_cache_width=2048\n" - "ro.hwui.text_small_cache_height=1024\n" - "ro.hwui.text_small_cache_width=1024\n" - "ro.hwui.r_buffer_cache_size=8\n" - "ro.hwui.fbo_cache_size=0\n" - "debug.hwui.render_dirty_regions=false\n" - "debug.hwui.enable_bp_cache=false\n" - "ro.config.hw_music_lp=true\n" - "ro.tui.service=true\n" - "persist.media.offload.enable=true\n" - "ro.config.hw_sensorhub=true\n" - "ro.hwcamera.sm.video_size=640x480\n" - "build.hisi_perf_opt=true\n" - "ro.config.hw_perfhub=true\n" - "ro.product.platform.pseudonym=1ARB9CV\n" - "persist.sys.jankenable=true\n" - "\n" - "#\n" - "# ADDITIONAL_BUILD_PROPERTIES\n" - "#\n" - "ro.config.ringtone=Dream_It_Possible.ogg\n" - "ro.config.notification_sound=Bongo.ogg\n" - "ro.carrier=unknown\n" - "ro.config.alarm_alert=Creamy.ogg\n" - "ro.setupwizard.mode=OPTIONAL\n" - "ro.com.google.gmsversion=6.0_r8\n" - "persist.sys.dalvik.vm.lib.2=libart\n" - "dalvik.vm.isa.arm64.variant=generic\n" - "dalvik.vm.isa.arm64.features=default\n" - "dalvik.vm.isa.arm.variant=cortex-a15\n" - "dalvik.vm.isa.arm.features=default\n" - "net.bt.name=Android\n" - "dalvik.vm.stack-trace-file=/data/anr/traces.txt\n" - "ro.expect.recovery_id=\n" - "\n" - "ro.config.fm_type=libbcmfm_if\n" - "\n" - "\n" - "persist.radio.apm_sim_not_pwdn=1\n" - "persist.service.tm2.tofile=true\n" - "persist.sys.dualcards=true\n" - "ril.hw_modem0.rssi=-1\n" - "ril.hw_modem1.rssi=-1\n" - "ro.cellbroadcast.emergencyids=0-65534\n" - "ro.config.delay_send_signal=true\n" - "ro.config.hw_accesscontrol=true\n" - "ro.config.hw_disable_cops=true\n" - "ro.config.hw_useCtrlSocket=true\n" - "ro.config.updatelocation=true\n" - "ro.networkstatus.delaytimer=20\n" - "ro.ril.ecclist=112,911,#911,*911\n" - "ro.check.modem_network=true\n" - "ro.config.ipv4.mtu=1400\n" - "gsm.fastdormancy.mode=3\n" - "ro.config.hw_hotswap_on=true\n" - "\n" - "\n" - "\n" - "\n" - "\n" - "\n" - "\n" - "\n" - "\n" - "ro.config.hw_showTestInfo=true\n" - "\n" - "ro.config.app_big_icon_size=172\n" - "ro.config.launcher_matchcard=0\n" - "ro.config.hw_navi_launcher=false\n" - "ro.build.hw_emui_lite.enable=true\n" - "keyguard.no_require_sim=true\n" - "ro.config.hwft_PinPukUnlockscr=true\n" - "\n" - "ro.config.bg_call_twinking=true\n" - "ro.config.carkitmodenotif=true\n" - "ro.config.hw_sim2airplane=true\n" - "modify_ram_show=true\n" - "ro.config.colorTemperature_K3=true\n" - "ro.config.hw_glovemode_enabled=1\n" - "ro.config.readBtAddress=true\n" - "ro.config.show2846=true\n" - "\n" - "ro.config.hw_enable_merge=true\n" - "ro.config.hw_gps_power_track=true\n" - "ro.config.hw_smartcardservice=true\n" - "ro.config.hw_subtitle_support=true\n" - "ro.config.hw_support_geofence=true\n" - "ro.dual.sim.phone=true\n" - "ro.hwcamera.previeweffects=true\n" - "ro.config.lvm_mode=true\n" - "\n" - "ro.config.hw_wifipro_enable=true\n" - "ro.config.signalplus.tas=true\n" - "ro.config.signalplus.xpass=true\n" - "ro.config.linkplus.roaming=true\n" - "ro.config.linkplus.liveupdate=true\n" - "ro.systemui.debug=true\n" - "ro.config.fp_navigation=true\n" - "ro.config.conn_diagnose=true\n" - "ro.config.earphone_hint=true\n" - "ro.config.hw_multiscreen=true\n" - "\n" - "ro.cust.cdrom=/system/cdrom/autorun.iso\n" - "\n" - "sys.refresh.dirty=1\n" - "ro.config.ringtone2=Huawei_Tune.ogg\n" - "qemu.hw.mainkeys=0\n" - "ro.config.hw_singlehand=1\n" - "ro.config.show6130=true\n" - "ro.config.apn_cancel_nopop=true\n" - "ro.config.hw_testingsettings=true\n" - "ro.config.isSLEntitleSet=true\n" - "ro.config.hw_easywakeup=false\n" - "ro.config.fp_launch_app=false\n" - "ro.config.cpu_info_display=Kirin 650\n" - "ro.config.hw_smart_backlight=0\n" - "ro.config.hw_lite_oom=true\n" - "ro.product.hardwareversion=HL2VENUSM\n" - "ro.config.colorTemperature_3d=true\n" - "ro.config.hw_eyes_protection=7\n" - "ro.config.antimal_enable=true\n" - "audioril.lib=libhuawei-audio-ril.so\n" - "media.stagefright.use-awesome=false\n" - "ro.config.hw_media_flags=3\n" - "ro.config.widevine_level3=true\n" - "drm.service.enabled=true\n" - "ro.camera.sound.forced=1\n" - "persist.hw_camera.video_sta=false\n" - "ro.config.hw_camera_docbeauty=true\n" - "ro.config.hw_camera_smartae=false\n" - "ro.config.speed_control_enable=true\n" - "ro.config.hw_auto_scene=true\n" - "ro.config.hw_dts=false\n" - "ro.config.hw_sws=true\n" - "ro.config.hw_dts_settings=true\n" - "ro.config.swsAlwaysActiveForSPK=true\n" - "audio.offload.disable=1\n" - "ro.media.radar=0\n" - "ro.media.NxpSmartPACurve=VNS_HISI_1225:1,-40:87,-4:93,-2:100,0.0:-15:\n" - "ro.config.hw_camera_omron=true\n" - "ro.config.hw_camera_hdr=true\n" - "ro.config.hw_camera_bestShot=true\n" - "ro.config.hw_camera_refocus=true\n" - "ro.config.small.previewpos=left\n" - "ro.config.camera_target_track=true\n" - "ro.config.hw_camera_zsl=true\n" - "ro.config.hw_camera_mfd=true\n" - "ro.config.hw_burst_snapshot=true\n" - "ro.config.hw_manual_focus=true\n" - "ro.config.hw_camera_davinci=true\n" - "ro.config.hw_photo_beauty=true\n" - "ro.config.hw_video_beauty=true\n" - "ro.hwcamera.jpeg.quality=95\n" - "ro.config.slow_play_enable=true\n" - "ro.config.hw.security_volume=10\n" - "ro.config.amrwb_disable=true\n" - "ro.config.hw_audio_plus=false\n" - "ro.config.hwinternet_audio=1\n" - "ro.config.hw_dolby=false\n" - "ro.hwcamera.isdm=false\n" - "ro.config.sws_version=sws2\n" - "ro.gallery.thumbnailLoading=true\n" - "ro.hwcamera.SlowMotionZoom=false\n" - "ro.hwcamera.BackSnapShotLimit=true\n" - "ro.hwcamera.brightness_range=60,178\n" - "ro.media.maxmem=4294967295\n" - "\n" - "ro.com.google.clientidbase=android-huawei\n" - "\n" - "ro.config.incall_notify_mms=true\n" - "ro.config.huawei_smallwindow=0\n" - "ro.com.android.mobiledata=true\n" - "ro.config.hw_power_saving=true\n" - "\n" - "ro.build.hide.matchers=Honor;ARM;hi6250;Mali-T830;Mali-T880;\n" - "ro.build.hide.replacements=Huawei;unknown;unknown;unknown;unknown;\n" - "ro.build.hide.settings=4;1.2 GHz;1.0GB;405 MB;4.00 GB;540 x 960;4.3;3.0.8;2.0\n" - "\n" - "dalvik.vm.heaptargetutilization=0.75\n" - "dalvik.vm.heapgrowthlimit=192m\n" - "dalvik.vm.heapstartsize=8m\n" - "ro.config.hw_directly_callfdn=true\n" - "ro.am.reschedule_service=true\n" - "ro.readfastboot=0\n" - "debug.aps.battery_limit=5\n" - "\n" - "\n" - "\n" - "\n" - "\n" - "\n" - "\n" - "\n" - "\n" - "\n" - "\n" - "\n" - "\n" - "\n" - "\n" - "\n" - "\n" - "\n" - "ro.build.version.emui=EmotionUI_4.1.1\n" - "persist.sys.hidewindow.enable=true\n" - "\n" - "ro.product.board=VNS\n" - "\n" - "ro.build.tags=release-keys\n" - "\n" - "ro.product.BaseVersion=VNS-C900B120\n" - "\n" - "ro.confg.hw_systemversion=VNS-C900B120_SYSTEM\n", + .content = "\n" + "# begin build properties\n" + "# autogenerated by buildinfo.sh\n" + "ro.build.id=MRA58K\n" + "#ro.build.display.id=deleted\n" + "#ro.build.version.incremental=deleted\n" + "ro.build.version.sdk=23\n" + "ro.build.version.preview_sdk=0\n" + "ro.build.version.codename=REL\n" + "ro.build.version.all_codenames=REL\n" + "ro.build.version.release=6.0\n" + "ro.build.version.security_patch=2016-11-01\n" + "ro.build.version.base_os=\n" + "ro.build.date=Fri Nov 25 19:25:55 CST 2016\n" + "ro.build.date.utc=1480073155\n" + "ro.build.type=user\n" + "ro.build.user=jenkins\n" + "ro.build.host=huawei-RH2288H-V2-12L\n" + "ro.build.flavor=hi6250-user\n" + "ro.product.model=hi6250\n" + "ro.product.brand=HUAWEI\n" + "ro.product.name=hi6250\n" + "ro.product.device=HWVNS-H\n" + "# ro.product.cpu.abi and ro.product.cpu.abi2 are obsolete,\n" + "# use ro.product.cpu.abilist instead.\n" + "ro.product.cpu.abi=arm64-v8a\n" + "ro.product.cpu.abilist=arm64-v8a,armeabi-v7a,armeabi\n" + "ro.product.cpu.abilist32=armeabi-v7a,armeabi\n" + "ro.product.cpu.abilist64=arm64-v8a\n" + "ro.product.manufacturer=HUAWEI\n" + "ro.product.locale=en-US\n" + "ro.wifi.channels=\n" + "ro.board.platform=hi6250\n" + "# ro.build.product is obsolete; use ro.product.device\n" + "ro.build.product=hi6250\n" + "# Do not try to parse description, fingerprint, or thumbprint\n" + "#ro.build.description=deleted\n" + "#ro.build.fingerprint=deleted\n" + "ro.build.characteristics=nosdcard\n" + "ro.build.hide=false\n" + "# end build properties\n" + "\n" + "# begin huawei emui properties\n" + "# autogenerated by build_emui_info.sh\n" + "ro.build.hw_emui_api_level=10\n" + "# end huawei emui properties\n" + "\n" + "#\n" + "# from device/hisi/hi6250/system.prop\n" + "#\n" + "ro.config.mmu_en=1\n" + "dalvik.vm.heapsize=512m\n" + "ro.opengles.version=196609\n" + "ro.sf.lcd_density=480\n" + "hw.lcd.density=480\n" + "persist.fw.force_adoptable=true\n" + "dalvik.vm.checkjni=false\n" + "ro.bt.bdaddr_path=/data/misc/bluedroid/macbt\n" + "ro.config.hw_navigationbar=true\n" + "ro.hwui.texture_cache_size=48\n" + "ro.hwui.texture_cache_flushrate=0.4\n" + "ro.hwui.layer_cache_size=32\n" + "ro.hwui.path_cache_size=16\n" + "ro.hwui.shape_cache_size=2\n" + "ro.hwui.drop_shadow_cache_size=6\n" + "ro.hwui.gradient_cache_size=1\n" + "ro.hwui.text_large_cache_height=1024\n" + "ro.hwui.text_large_cache_width=2048\n" + "ro.hwui.text_small_cache_height=1024\n" + "ro.hwui.text_small_cache_width=1024\n" + "ro.hwui.r_buffer_cache_size=8\n" + "ro.hwui.fbo_cache_size=0\n" + "debug.hwui.render_dirty_regions=false\n" + "debug.hwui.enable_bp_cache=false\n" + "ro.config.hw_music_lp=true\n" + "ro.tui.service=true\n" + "persist.media.offload.enable=true\n" + "ro.config.hw_sensorhub=true\n" + "ro.hwcamera.sm.video_size=640x480\n" + "build.hisi_perf_opt=true\n" + "ro.config.hw_perfhub=true\n" + "ro.product.platform.pseudonym=1ARB9CV\n" + "persist.sys.jankenable=true\n" + "\n" + "#\n" + "# ADDITIONAL_BUILD_PROPERTIES\n" + "#\n" + "ro.config.ringtone=Dream_It_Possible.ogg\n" + "ro.config.notification_sound=Bongo.ogg\n" + "ro.carrier=unknown\n" + "ro.config.alarm_alert=Creamy.ogg\n" + "ro.setupwizard.mode=OPTIONAL\n" + "ro.com.google.gmsversion=6.0_r8\n" + "persist.sys.dalvik.vm.lib.2=libart\n" + "dalvik.vm.isa.arm64.variant=generic\n" + "dalvik.vm.isa.arm64.features=default\n" + "dalvik.vm.isa.arm.variant=cortex-a15\n" + "dalvik.vm.isa.arm.features=default\n" + "net.bt.name=Android\n" + "dalvik.vm.stack-trace-file=/data/anr/traces.txt\n" + "ro.expect.recovery_id=\n" + "\n" + "ro.config.fm_type=libbcmfm_if\n" + "\n" + "\n" + "persist.radio.apm_sim_not_pwdn=1\n" + "persist.service.tm2.tofile=true\n" + "persist.sys.dualcards=true\n" + "ril.hw_modem0.rssi=-1\n" + "ril.hw_modem1.rssi=-1\n" + "ro.cellbroadcast.emergencyids=0-65534\n" + "ro.config.delay_send_signal=true\n" + "ro.config.hw_accesscontrol=true\n" + "ro.config.hw_disable_cops=true\n" + "ro.config.hw_useCtrlSocket=true\n" + "ro.config.updatelocation=true\n" + "ro.networkstatus.delaytimer=20\n" + "ro.ril.ecclist=112,911,#911,*911\n" + "ro.check.modem_network=true\n" + "ro.config.ipv4.mtu=1400\n" + "gsm.fastdormancy.mode=3\n" + "ro.config.hw_hotswap_on=true\n" + "\n" + "\n" + "\n" + "\n" + "\n" + "\n" + "\n" + "\n" + "\n" + "ro.config.hw_showTestInfo=true\n" + "\n" + "ro.config.app_big_icon_size=172\n" + "ro.config.launcher_matchcard=0\n" + "ro.config.hw_navi_launcher=false\n" + "ro.build.hw_emui_lite.enable=true\n" + "keyguard.no_require_sim=true\n" + "ro.config.hwft_PinPukUnlockscr=true\n" + "\n" + "ro.config.bg_call_twinking=true\n" + "ro.config.carkitmodenotif=true\n" + "ro.config.hw_sim2airplane=true\n" + "modify_ram_show=true\n" + "ro.config.colorTemperature_K3=true\n" + "ro.config.hw_glovemode_enabled=1\n" + "ro.config.readBtAddress=true\n" + "ro.config.show2846=true\n" + "\n" + "ro.config.hw_enable_merge=true\n" + "ro.config.hw_gps_power_track=true\n" + "ro.config.hw_smartcardservice=true\n" + "ro.config.hw_subtitle_support=true\n" + "ro.config.hw_support_geofence=true\n" + "ro.dual.sim.phone=true\n" + "ro.hwcamera.previeweffects=true\n" + "ro.config.lvm_mode=true\n" + "\n" + "ro.config.hw_wifipro_enable=true\n" + "ro.config.signalplus.tas=true\n" + "ro.config.signalplus.xpass=true\n" + "ro.config.linkplus.roaming=true\n" + "ro.config.linkplus.liveupdate=true\n" + "ro.systemui.debug=true\n" + "ro.config.fp_navigation=true\n" + "ro.config.conn_diagnose=true\n" + "ro.config.earphone_hint=true\n" + "ro.config.hw_multiscreen=true\n" + "\n" + "ro.cust.cdrom=/system/cdrom/autorun.iso\n" + "\n" + "sys.refresh.dirty=1\n" + "ro.config.ringtone2=Huawei_Tune.ogg\n" + "qemu.hw.mainkeys=0\n" + "ro.config.hw_singlehand=1\n" + "ro.config.show6130=true\n" + "ro.config.apn_cancel_nopop=true\n" + "ro.config.hw_testingsettings=true\n" + "ro.config.isSLEntitleSet=true\n" + "ro.config.hw_easywakeup=false\n" + "ro.config.fp_launch_app=false\n" + "ro.config.cpu_info_display=Kirin 650\n" + "ro.config.hw_smart_backlight=0\n" + "ro.config.hw_lite_oom=true\n" + "ro.product.hardwareversion=HL2VENUSM\n" + "ro.config.colorTemperature_3d=true\n" + "ro.config.hw_eyes_protection=7\n" + "ro.config.antimal_enable=true\n" + "audioril.lib=libhuawei-audio-ril.so\n" + "media.stagefright.use-awesome=false\n" + "ro.config.hw_media_flags=3\n" + "ro.config.widevine_level3=true\n" + "drm.service.enabled=true\n" + "ro.camera.sound.forced=1\n" + "persist.hw_camera.video_sta=false\n" + "ro.config.hw_camera_docbeauty=true\n" + "ro.config.hw_camera_smartae=false\n" + "ro.config.speed_control_enable=true\n" + "ro.config.hw_auto_scene=true\n" + "ro.config.hw_dts=false\n" + "ro.config.hw_sws=true\n" + "ro.config.hw_dts_settings=true\n" + "ro.config.swsAlwaysActiveForSPK=true\n" + "audio.offload.disable=1\n" + "ro.media.radar=0\n" + "ro.media.NxpSmartPACurve=VNS_HISI_1225:1,-40:87,-4:93,-2:100,0.0:-15:\n" + "ro.config.hw_camera_omron=true\n" + "ro.config.hw_camera_hdr=true\n" + "ro.config.hw_camera_bestShot=true\n" + "ro.config.hw_camera_refocus=true\n" + "ro.config.small.previewpos=left\n" + "ro.config.camera_target_track=true\n" + "ro.config.hw_camera_zsl=true\n" + "ro.config.hw_camera_mfd=true\n" + "ro.config.hw_burst_snapshot=true\n" + "ro.config.hw_manual_focus=true\n" + "ro.config.hw_camera_davinci=true\n" + "ro.config.hw_photo_beauty=true\n" + "ro.config.hw_video_beauty=true\n" + "ro.hwcamera.jpeg.quality=95\n" + "ro.config.slow_play_enable=true\n" + "ro.config.hw.security_volume=10\n" + "ro.config.amrwb_disable=true\n" + "ro.config.hw_audio_plus=false\n" + "ro.config.hwinternet_audio=1\n" + "ro.config.hw_dolby=false\n" + "ro.hwcamera.isdm=false\n" + "ro.config.sws_version=sws2\n" + "ro.gallery.thumbnailLoading=true\n" + "ro.hwcamera.SlowMotionZoom=false\n" + "ro.hwcamera.BackSnapShotLimit=true\n" + "ro.hwcamera.brightness_range=60,178\n" + "ro.media.maxmem=4294967295\n" + "\n" + "ro.com.google.clientidbase=android-huawei\n" + "\n" + "ro.config.incall_notify_mms=true\n" + "ro.config.huawei_smallwindow=0\n" + "ro.com.android.mobiledata=true\n" + "ro.config.hw_power_saving=true\n" + "\n" + "ro.build.hide.matchers=Honor;ARM;hi6250;Mali-T830;Mali-T880;\n" + "ro.build.hide.replacements=Huawei;unknown;unknown;unknown;unknown;\n" + "ro.build.hide.settings=4;1.2 GHz;1.0GB;405 MB;4.00 GB;540 x 960;4.3;3.0.8;2.0\n" + "\n" + "dalvik.vm.heaptargetutilization=0.75\n" + "dalvik.vm.heapgrowthlimit=192m\n" + "dalvik.vm.heapstartsize=8m\n" + "ro.config.hw_directly_callfdn=true\n" + "ro.am.reschedule_service=true\n" + "ro.readfastboot=0\n" + "debug.aps.battery_limit=5\n" + "\n" + "\n" + "\n" + "\n" + "\n" + "\n" + "\n" + "\n" + "\n" + "\n" + "\n" + "\n" + "\n" + "\n" + "\n" + "\n" + "\n" + "\n" + "ro.build.version.emui=EmotionUI_4.1.1\n" + "persist.sys.hidewindow.enable=true\n" + "\n" + "ro.product.board=VNS\n" + "\n" + "ro.build.tags=release-keys\n" + "\n" + "ro.product.BaseVersion=VNS-C900B120\n" + "\n" + "ro.confg.hw_systemversion=VNS-C900B120_SYSTEM\n", }, { .path = "/sys/devices/system/cpu/kernel_max", @@ -364,24 +362,22 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpufreq/all_time_in_state", .size = 431, - .content = - "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\t\n" - "480000\t\t28116\t\t28116\t\t28116\t\t28116\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "807000\t\t444\t\t444\t\t444\t\t444\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1306000\t\t137\t\t137\t\t137\t\t137\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1402000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t33207\t\t33207\t\t33207\t\t33207\t\t\n" - "1709000\t\t13225\t\t13225\t\t13225\t\t13225\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1805000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t889\t\t889\t\t889\t\t889\t\t\n" - "2016000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t7826\t\t7826\t\t7826\t\t7826\t\t\n", + .content = "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\t\n" + "480000\t\t28116\t\t28116\t\t28116\t\t28116\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "807000\t\t444\t\t444\t\t444\t\t444\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "1306000\t\t137\t\t137\t\t137\t\t137\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "1402000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t33207\t\t33207\t\t33207\t\t33207\t\t\n" + "1709000\t\t13225\t\t13225\t\t13225\t\t13225\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "1805000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t889\t\t889\t\t889\t\t889\t\t\n" + "2016000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t7826\t\t7826\t\t7826\t\t7826\t\t\n", }, { .path = "/sys/devices/system/cpu/cpufreq/current_in_state", .size = 176, - .content = - "CPU4:480000=0 807000=0 1306000=0 1709000=0 \n" - "CPU5:480000=0 807000=0 1306000=0 1709000=0 \n" - "CPU6:480000=0 807000=0 1306000=0 1709000=0 \n" - "CPU7:480000=0 807000=0 1306000=0 1709000=0 \n", + .content = "CPU4:480000=0 807000=0 1306000=0 1709000=0 \n" + "CPU5:480000=0 807000=0 1306000=0 1709000=0 \n" + "CPU6:480000=0 807000=0 1306000=0 1709000=0 \n" + "CPU7:480000=0 807000=0 1306000=0 1709000=0 \n", }, { .path = "/sys/devices/system/cpu/cpuidle/current_driver", @@ -461,11 +457,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 50, - .content = - "480000 28222\n" - "807000 445\n" - "1306000 137\n" - "1709000 13257\n", + .content = "480000 28222\n" + "807000 445\n" + "1306000 137\n" + "1709000 13257\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -475,13 +470,12 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/trans_table", .size = 277, - .content = - " From : To\n" - " : 480000 807000 1306000 1709000 \n" - " 480000: 0 56 0 78 \n" - " 807000: 28 0 5 31 \n" - " 1306000: 3 1 0 9 \n" - " 1709000: 102 8 8 0 \n", + .content = " From : To\n" + " : 480000 807000 1306000 1709000 \n" + " 480000: 0 56 0 78 \n" + " 807000: 28 0 5 31 \n" + " 1306000: 3 1 0 9 \n" + " 1709000: 102 8 8 0 \n", }, { .path = "/sys/devices/system/cpu/cpu0/topology/core_id", @@ -581,11 +575,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 50, - .content = - "480000 28423\n" - "807000 454\n" - "1306000 137\n" - "1709000 13267\n", + .content = "480000 28423\n" + "807000 454\n" + "1306000 137\n" + "1709000 13267\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -595,13 +588,12 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/trans_table", .size = 277, - .content = - " From : To\n" - " : 480000 807000 1306000 1709000 \n" - " 480000: 0 56 0 79 \n" - " 807000: 29 0 5 31 \n" - " 1306000: 3 1 0 9 \n" - " 1709000: 103 8 8 0 \n", + .content = " From : To\n" + " : 480000 807000 1306000 1709000 \n" + " 480000: 0 56 0 79 \n" + " 807000: 29 0 5 31 \n" + " 1306000: 3 1 0 9 \n" + " 1709000: 103 8 8 0 \n", }, { .path = "/sys/devices/system/cpu/cpu1/topology/core_id", @@ -701,11 +693,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 50, - .content = - "480000 28586\n" - "807000 456\n" - "1306000 137\n" - "1709000 13325\n", + .content = "480000 28586\n" + "807000 456\n" + "1306000 137\n" + "1709000 13325\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -715,13 +706,12 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/trans_table", .size = 277, - .content = - " From : To\n" - " : 480000 807000 1306000 1709000 \n" - " 480000: 0 57 0 81 \n" - " 807000: 29 0 5 32 \n" - " 1306000: 3 1 0 9 \n" - " 1709000: 105 8 8 0 \n", + .content = " From : To\n" + " : 480000 807000 1306000 1709000 \n" + " 480000: 0 57 0 81 \n" + " 807000: 29 0 5 32 \n" + " 1306000: 3 1 0 9 \n" + " 1709000: 105 8 8 0 \n", }, { .path = "/sys/devices/system/cpu/cpu2/topology/core_id", @@ -821,11 +811,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 50, - .content = - "480000 28762\n" - "807000 458\n" - "1306000 137\n" - "1709000 13396\n", + .content = "480000 28762\n" + "807000 458\n" + "1306000 137\n" + "1709000 13396\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -835,13 +824,12 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/trans_table", .size = 277, - .content = - " From : To\n" - " : 480000 807000 1306000 1709000 \n" - " 480000: 0 58 0 82 \n" - " 807000: 29 0 5 33 \n" - " 1306000: 3 1 0 9 \n" - " 1709000: 108 8 8 0 \n", + .content = " From : To\n" + " : 480000 807000 1306000 1709000 \n" + " 480000: 0 58 0 82 \n" + " 807000: 29 0 5 33 \n" + " 1306000: 3 1 0 9 \n" + " 1709000: 108 8 8 0 \n", }, { .path = "/sys/devices/system/cpu/cpu3/topology/core_id", @@ -941,10 +929,9 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/time_in_state", .size = 39, - .content = - "1402000 34215\n" - "1805000 894\n" - "2016000 7902\n", + .content = "1402000 34215\n" + "1805000 894\n" + "2016000 7902\n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/total_trans", @@ -954,12 +941,11 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/trans_table", .size = 185, - .content = - " From : To\n" - " : 1402000 1805000 2016000 \n" - " 1402000: 0 102 56 \n" - " 1805000: 97 0 45 \n" - " 2016000: 61 40 0 \n", + .content = " From : To\n" + " : 1402000 1805000 2016000 \n" + " 1402000: 0 102 56 \n" + " 1805000: 97 0 45 \n" + " 2016000: 61 40 0 \n", }, { .path = "/sys/devices/system/cpu/cpu4/topology/core_id", @@ -1059,10 +1045,9 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/time_in_state", .size = 39, - .content = - "1402000 34481\n" - "1805000 894\n" - "2016000 7902\n", + .content = "1402000 34481\n" + "1805000 894\n" + "2016000 7902\n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/total_trans", @@ -1072,12 +1057,11 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/trans_table", .size = 185, - .content = - " From : To\n" - " : 1402000 1805000 2016000 \n" - " 1402000: 0 102 56 \n" - " 1805000: 97 0 45 \n" - " 2016000: 61 40 0 \n", + .content = " From : To\n" + " : 1402000 1805000 2016000 \n" + " 1402000: 0 102 56 \n" + " 1805000: 97 0 45 \n" + " 2016000: 61 40 0 \n", }, { .path = "/sys/devices/system/cpu/cpu5/topology/core_id", @@ -1177,10 +1161,9 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/time_in_state", .size = 39, - .content = - "1402000 34735\n" - "1805000 894\n" - "2016000 7902\n", + .content = "1402000 34735\n" + "1805000 894\n" + "2016000 7902\n", }, { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/total_trans", @@ -1190,12 +1173,11 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/trans_table", .size = 185, - .content = - " From : To\n" - " : 1402000 1805000 2016000 \n" - " 1402000: 0 102 56 \n" - " 1805000: 97 0 45 \n" - " 2016000: 61 40 0 \n", + .content = " From : To\n" + " : 1402000 1805000 2016000 \n" + " 1402000: 0 102 56 \n" + " 1805000: 97 0 45 \n" + " 2016000: 61 40 0 \n", }, { .path = "/sys/devices/system/cpu/cpu6/topology/core_id", @@ -1295,10 +1277,9 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/time_in_state", .size = 39, - .content = - "1402000 34972\n" - "1805000 894\n" - "2016000 7902\n", + .content = "1402000 34972\n" + "1805000 894\n" + "2016000 7902\n", }, { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/total_trans", @@ -1308,12 +1289,11 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/trans_table", .size = 185, - .content = - " From : To\n" - " : 1402000 1805000 2016000 \n" - " 1402000: 0 102 56 \n" - " 1805000: 97 0 45 \n" - " 2016000: 61 40 0 \n", + .content = " From : To\n" + " : 1402000 1805000 2016000 \n" + " 1402000: 0 102 56 \n" + " 1805000: 97 0 45 \n" + " 2016000: 61 40 0 \n", }, { .path = "/sys/devices/system/cpu/cpu7/topology/core_id", @@ -1345,7 +1325,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "7\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -4005,6 +3985,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.driver.status", .value = "ok", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/iconia-one-10.cc b/test/mock/iconia-one-10.cc index 03e26f2d..058ee276 100644 --- a/test/mock/iconia-one-10.cc +++ b/test/mock/iconia-one-10.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(4, cpuinfo_get_processors_count()); @@ -208,8 +207,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("MediaTek MT8167B", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "MediaTek MT8167B", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -251,59 +252,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -428,8 +429,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -480,8 +483,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -532,8 +537,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/iconia-one-10.h b/test/mock/iconia-one-10.h index d3e66450..97695009 100644 --- a/test/mock/iconia-one-10.h +++ b/test/mock/iconia-one-10.h @@ -3,41 +3,40 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 841, - .content = - "processor\t: 0\n" - "Processor\t: AArch64 Processor rev 1 (aarch64)\n" - "model name\t: AArch64 Processor rev 1 (aarch64)\n" - "BogoMIPS\t: 26.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd04\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 1\n" - "Processor\t: AArch64 Processor rev 1 (aarch64)\n" - "model name\t: AArch64 Processor rev 1 (aarch64)\n" - "BogoMIPS\t: 26.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd04\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 2\n" - "Processor\t: AArch64 Processor rev 1 (aarch64)\n" - "model name\t: AArch64 Processor rev 1 (aarch64)\n" - "BogoMIPS\t: 26.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd04\n" - "CPU revision\t: 1\n" - "\n" - "Hardware\t: MT8167B\n", + .content = "processor\t: 0\n" + "Processor\t: AArch64 Processor rev 1 (aarch64)\n" + "model name\t: AArch64 Processor rev 1 (aarch64)\n" + "BogoMIPS\t: 26.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd04\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 1\n" + "Processor\t: AArch64 Processor rev 1 (aarch64)\n" + "model name\t: AArch64 Processor rev 1 (aarch64)\n" + "BogoMIPS\t: 26.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd04\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 2\n" + "Processor\t: AArch64 Processor rev 1 (aarch64)\n" + "model name\t: AArch64 Processor rev 1 (aarch64)\n" + "BogoMIPS\t: 26.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd04\n" + "CPU revision\t: 1\n" + "\n" + "Hardware\t: MT8167B\n", }, #elif CPUINFO_ARCH_ARM { @@ -403,11 +402,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cputopo/glbinfo", .size = 58, - .content = - "big/little arch: no\n" - "nr_cups: 4\n" - "nr_clusters: 1\n" - "cluster0: f\n", + .content = "big/little arch: no\n" + "nr_cups: 4\n" + "nr_clusters: 1\n" + "cluster0: f\n", }, { .path = "/sys/devices/system/cpu/cputopo/is_big_little", @@ -487,12 +485,11 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 60, - .content = - "598000 2118\n" - "747500 263\n" - "1040000 619\n" - "1196000 458\n" - "1300000 5963\n", + .content = "598000 2118\n" + "747500 263\n" + "1040000 619\n" + "1196000 458\n" + "1300000 5963\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -502,14 +499,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/trans_table", .size = 389, - .content = - " From : To\n" - " : 598000 747500 1040000 1196000 1300000 \n" - " 598000: 0 14 0 0 38 \n" - " 747500: 5 0 14 0 9 \n" - " 1040000: 6 3 0 12 11 \n" - " 1196000: 3 1 1 0 19 \n" - " 1300000: 39 10 16 12 0 \n", + .content = " From : To\n" + " : 598000 747500 1040000 1196000 1300000 \n" + " 598000: 0 14 0 0 38 \n" + " 747500: 5 0 14 0 9 \n" + " 1040000: 6 3 0 12 11 \n" + " 1196000: 3 1 1 0 19 \n" + " 1300000: 39 10 16 12 0 \n", }, { .path = "/sys/devices/system/cpu/cpu0/topology/core_id", @@ -604,12 +600,11 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 60, - .content = - "598000 2359\n" - "747500 263\n" - "1040000 619\n" - "1196000 458\n" - "1300000 5963\n", + .content = "598000 2359\n" + "747500 263\n" + "1040000 619\n" + "1196000 458\n" + "1300000 5963\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -619,14 +614,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/trans_table", .size = 389, - .content = - " From : To\n" - " : 598000 747500 1040000 1196000 1300000 \n" - " 598000: 0 14 0 0 38 \n" - " 747500: 5 0 14 0 9 \n" - " 1040000: 6 3 0 12 11 \n" - " 1196000: 3 1 1 0 19 \n" - " 1300000: 39 10 16 12 0 \n", + .content = " From : To\n" + " : 598000 747500 1040000 1196000 1300000 \n" + " 598000: 0 14 0 0 38 \n" + " 747500: 5 0 14 0 9 \n" + " 1040000: 6 3 0 12 11 \n" + " 1196000: 3 1 1 0 19 \n" + " 1300000: 39 10 16 12 0 \n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/affected_cpus", @@ -691,12 +685,11 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 60, - .content = - "598000 2600\n" - "747500 263\n" - "1040000 619\n" - "1196000 458\n" - "1300000 5963\n", + .content = "598000 2600\n" + "747500 263\n" + "1040000 619\n" + "1196000 458\n" + "1300000 5963\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -706,14 +699,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/trans_table", .size = 389, - .content = - " From : To\n" - " : 598000 747500 1040000 1196000 1300000 \n" - " 598000: 0 14 0 0 38 \n" - " 747500: 5 0 14 0 9 \n" - " 1040000: 6 3 0 12 11 \n" - " 1196000: 3 1 1 0 19 \n" - " 1300000: 39 10 16 12 0 \n", + .content = " From : To\n" + " : 598000 747500 1040000 1196000 1300000 \n" + " 598000: 0 14 0 0 38 \n" + " 747500: 5 0 14 0 9 \n" + " 1040000: 6 3 0 12 11 \n" + " 1196000: 3 1 1 0 19 \n" + " 1300000: 39 10 16 12 0 \n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/affected_cpus", @@ -778,12 +770,11 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 60, - .content = - "598000 2821\n" - "747500 263\n" - "1040000 619\n" - "1196000 458\n" - "1300000 5963\n", + .content = "598000 2821\n" + "747500 263\n" + "1040000 619\n" + "1196000 458\n" + "1300000 5963\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -793,16 +784,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/trans_table", .size = 389, - .content = - " From : To\n" - " : 598000 747500 1040000 1196000 1300000 \n" - " 598000: 0 14 0 0 38 \n" - " 747500: 5 0 14 0 9 \n" - " 1040000: 6 3 0 12 11 \n" - " 1196000: 3 1 1 0 19 \n" - " 1300000: 39 10 16 12 0 \n", - }, - { NULL }, + .content = " From : To\n" + " : 598000 747500 1040000 1196000 1300000 \n" + " 598000: 0 14 0 0 38 \n" + " 747500: 5 0 14 0 9 \n" + " 1040000: 6 3 0 12 11 \n" + " 1196000: 3 1 1 0 19 \n" + " 1300000: 39 10 16 12 0 \n", + }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -2346,6 +2336,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.wfd.security.image", .value = "1", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/leagoo-t5c.cc b/test/mock/leagoo-t5c.cc index f39e1789..48cd5cec 100644 --- a/test/mock/leagoo-t5c.cc +++ b/test/mock/leagoo-t5c.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(8, cpuinfo_get_processors_count()); @@ -212,8 +211,10 @@ TEST(PACKAGES, non_null) { TEST(PACKAGES, DISABLED_name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Spreadtrum SC9853I-IA", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Spreadtrum SC9853I-IA", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -536,8 +537,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -588,8 +591,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -640,8 +645,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/leagoo-t5c.h b/test/mock/leagoo-t5c.h index 28c3f65a..35c7fe8f 100644 --- a/test/mock/leagoo-t5c.h +++ b/test/mock/leagoo-t5c.h @@ -505,283 +505,282 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/system/build.prop", .size = 8107, - .content = - "\n" - "# begin build properties\n" - "# autogenerated by buildinfo.sh\n" - "ro.build.id=NRD90M\n" - "###\n" - "ro.build.version.incremental=eng.root.20180112.175428\n" - "ro.build.version.sdk=24\n" - "ro.build.version.preview_sdk=0\n" - "ro.build.version.codename=REL\n" - "ro.build.version.all_codenames=REL\n" - "ro.build.version.release=7.0\n" - "ro.build.version.security_patch=2017-12-05\n" - "ro.build.version.base_os=\n" - "ro.build.date=Fri Jan 12 17:54:28 CST 2018\n" - "ro.build.date.utc=1515750868\n" - "ro.build.type=user\n" - "ro.build.user=root\n" - "ro.build.host=lxh\n" - "ro.build.tags=release-keys\n" - "ro.build.flavor=k500_lgt_511-user\n" - "ro.product.model=T5c\n" - "ro.product.brand=LEAGOO\n" - "ro.product.name=T5c\n" - "ro.product.device=T5c\n" - "ro.product.board=k500_lgt_511_vmm\n" - "# ro.product.cpu.abi and ro.product.cpu.abi2 are obsolete,\n" - "# use ro.product.cpu.abilist instead.\n" - "ro.product.cpu.abi=x86_64\n" - "ro.product.cpu.abilist=x86_64,x86,armeabi-v7a,armeabi,arm64-v8a\n" - "ro.product.cpu.abilist32=x86,armeabi-v7a,armeabi\n" - "ro.product.cpu.abilist64=x86_64,arm64-v8a\n" - "ro.product.manufacturer=LEAGOO\n" - "ro.product.locale=en-US\n" - "ro.wifi.channels=\n" - "ro.board.platform=sp9853i\n" - "# ro.build.product is obsolete; use ro.product.device\n" - "ro.build.product=T5c\n" - "# Do not try to parse description, fingerprint, or thumbprint\n" - "ro.build.description=k500_lgt_511-user 7.0 NRD90M eng.root.20180112.175428 release-keys\n" - "ro.build.fingerprint=LEAGOO/T5c/T5c:7.0/NRD90M/01121754:user/release-keys\n" - "ro.build.characteristics=nosdcard\n" - "# end build properties\n" - "#\n" - "# from device/sprd/isharkl2/k500_lgt_511/system.prop\n" - "#\n" - "# Default density config\n" - "ro.product.hardware=k500_lgt_511_v1.0.0\n" - "# Set Opengl ES Version 3.2\n" - "ro.opengles.version=196610\n" - "\n" - "\n" - "#enable audio nr tuning\n" - "ro.audio_tunning.nr=1\n" - "\n" - "#enable audio dual spk tuning\n" - "ro.audio_tunning.dual_spk=0\n" - "\n" - "\n" - "ro.fm.chip.port.UART.androidm=false\n" - "\n" - "persist.sys.cam.eois.dc.back=false\n" - "persist.sys.cam.eois.dc.front=false\n" - "persist.sys.cam.eois.dv.back=true\n" - "persist.sys.cam.eois.dv.front=false\n" - "persist.sys.cam.pipviv=false\n" - "\n" - "persist.sys.cam.battery.flash=15\n" - "\n" - "#FRP property for pst device\n" - "ro.frp.pst=/dev/block/platform/sdio_emmc/by-name/persist\n" - "\n" - "persist.sys.cam.refocus.enable=false\n" - "persist.sys.cam.ba.blur.version=0\n" - "persist.sys.cam.api.version=1\n" - "\n" - "persist.sys.blending.enable=true\n" - "\n" - "persist.sys.sprd.refocus.bokeh=true\n" - "qemu.hw.mainkeys=0\n" - "\n" - "#Enable sdcardfs feature\n" - "ro.sys.sdcardfs=true\n" - "persist.sys.sdcardfs=force_on\n" - "persist.bindcore.hdr=_4_0_1_2_3\n" - "\n" - "#disable partial update\n" - "debug.hwui.use_partial_updates=false\n" - "\n" - "persist.sys.fp.ck.period=3\n" - "#\n" - "# from device/sprd/isharkl2/k500_lgt_511/custom_config/custom.prop\n" - "#\n" - "ro.macro.custom.leagoo=true\n" - "ro.com.google.clientidbase=android-leagoo\n" - "ro.build.display.id=LEAGOO_T5c_OS2.1_E_20180112\n" - "ro.build.display.spid=SC9853_K500_LGT_511_V2.2_20180112\n" - "ro.build.display.spid.customer=LEAGOO_T5c_OS2.1_E_20180112\n" - "ro.leagoo.baseband.version=LEAGOO T5c_OS2.1\n" - "ro.product.bt.name=LEAGOO T5c\n" - "ro.leagoo.storage.ui=true\n" - "ro.modify.settings.icon=true\n" - "ro.lock.disable.statusbar=true\n" - "ro.leagoo.power.ui=true\n" - "ro.message.wake.up.screen=false\n" - "ro.sim.no.switch.languages=true\n" - "ro.test.playsound.outside=true\n" - "ro.hide.smart.control=true\n" - "persist.sys.fp.ck.period=3\n" - "ro.single.point.y.index=150\n" - "ro.email.signatures.same=true\n" - "ro.modify.message.notify=true\n" - "ro.temp.ntc=true\n" - "ro.disable.sound.effects=true\n" - "ro.not.support.menu.key=true\n" - "ro.not.support.back.key=true\n" - "ro.not.support.home.key=true\n" - "ro.ram.display.config.3gb=true\n" - "ro.rm.calllog.geocode=true\n" - "ro.preload.media.internel=true\n" - "ro.support.video.dream=true\n" - "#\n" - "# ADDITIONAL_BUILD_PROPERTIES\n" - "#\n" - "persist.radio.modem.config=TL_LF_TD_W_G,W_G\n" - "persist.radio.modem.workmode=9,255\n" - "ro.radio.modem.capability=TL_LF_TD_W_G,W_G\n" - "ro.dalvik.vm.isa.arm=x86\n" - "ro.enable.native.bridge.exec=1\n" - "ro.dalvik.vm.isa.arm64=x86_64\n" - "ro.enable.native.bridge.exec64=1\n" - "ro.sys.prc_compatibility=1\n" - "ro.hwui.layer_cache_size=48\n" - "ro.hwui.r_buffer_cache_size=8\n" - "ro.hwui.path_cache_size=32\n" - "ro.hwui.gradient_cache_size=1\n" - "ro.hwui.drop_shadow_cache_size=6\n" - "ro.hwui.texture_cache_flushrate=0.4\n" - "ro.hwui.text_small_cache_width=1024\n" - "ro.hwui.text_small_cache_height=1024\n" - "ro.hwui.text_large_cache_width=2048\n" - "ro.hwui.text_large_cache_height=1024\n" - "dalvik.vm.sprd_usejitprofiles=false\n" - "ro.config.notification_sound=LEAGOO-Pops.mp3\n" - "ro.config.alarm_alert=Alarm_Classic.ogg\n" - "ro.config.ringtone=LEAGOO-Turkish.mp3\n" - "ro.config.ringtone0=LEAGOO-Turkish.mp3\n" - "ro.config.ringtone1=LEAGOO-Turkish.mp3\n" - "ro.config.message_sound0=Argon.ogg\n" - "ro.config.message_sound1=Argon.ogg\n" - "ro.config.message_sound=pixiedust.ogg\n" - "ro.product.locale.language=en\n" - "ro.product.locale.region=US\n" - "persist.sys.timezone=Asia/Calcutta\n" - "persist.sys.defaulttimezone=Asia/Calcutta\n" - "ro.product.first_api_level=24\n" - "ro.carrier=unknown\n" - "rild.libpath=/system/lib64/libsprd-ril.so\n" - "ro.radio.modemtype=l\n" - "ro.telephony.default_network=9\n" - "keyguard.no_require_sim=true\n" - "ro.com.android.dataroaming=false\n" - "ro.simlock.unlock.autoshow=1\n" - "ro.simlock.unlock.bynv=0\n" - "ro.simlock.onekey.lock=0\n" - "persist.sys.engpc.disable=1\n" - "persist.sys.sprd.modemreset=1\n" - "ro.product.partitionpath=/dev/block/platform/sdio_emmc/by-name/\n" - "ro.modem.l.dev=/proc/cptl/\n" - "ro.modem.l.tty=/dev/stty_lte\n" - "ro.modem.l.diag=/dev/sdiag_lte\n" - "ro.modem.l.log=/dev/slog_lte\n" - "ro.modem.l.assert=/dev/spipe_lte2\n" - "ro.modem.l.fixnv_size=0xc8000\n" - "ro.modem.l.runnv_size=0xe8000\n" - "ro.sp.log=/dev/slog_pm\n" - "persist.modem.l.nvp=l_\n" - "persist.modem.l.enable=1\n" - "ro.storage.flash_type=2\n" - "sys.internal.emulated=1\n" - "persist.storage.type=2\n" - "ro.storage.install2internal=0\n" - "drm.service.enabled=true\n" - "persist.sys.sprd.wcnreset=1\n" - "persist.sys.start_udpdatastall=0\n" - "persist.sys.apr.enabled=0\n" - "persist.sys.ag.enable=false\n" - "ro.adb.secure=1\n" - "persist.sys.apr.intervaltime=1\n" - "persist.sys.apr.testgroup=CSSLAB\n" - "persist.sys.apr.autoupload=1\n" - "ro.modem.l.eth=seth_lte\n" - "ro.modem.l.snd=1\n" - "ro.modem.l.loop=/dev/spipe_lte0\n" - "ro.modem.l.nv=/dev/spipe_lte1\n" - "ro.modem.l.vbc=/dev/spipe_lte6\n" - "ro.modem.l.id=0\n" - "persist.sys.heartbeat.enable=1\n" - "persist.sys.powerHint.enable=1\n" - "persist.ylog.modem.shutdownlog=1\n" - "persist.sys.cam.photo.gallery=true\n" - "persist.sys.ucam.puzzle=false\n" - "persist.sys.ucam.edit=false\n" - "persist.sys.cam.timestamp=false\n" - "persist.sys.cam.gif=false\n" - "persist.sys.cam.scenery=false\n" - "persist.sys.cam.vgesture=false\n" - "persist.sys.cam.gps=true\n" - "persist.sys.cam.normalhdr=true\n" - "persist.sys.cam.sfv.alter=true\n" - "persist.sys.cam.arcsoft.filter=true\n" - "persist.sys.cam.filter.highfps=true\n" - "persist.sys.cam.new.wideangle=true\n" - "persist.sys.cam.3dnr=true\n" - "persist.sys.bsservice.enable=1\n" - "ro.wcn.hardware.product=marlin2\n" - "ro.bt.bdaddr_path=/data/misc/bluedroid/btmac.txt\n" - "persist.sys.volte.enable=true\n" - "ro.trim.config=true\n" - "persist.sys.vilte.socket=ap\n" - "persist.dbg.wfc_avail_ovr=1\n" - "persist.sys.vowifi.voice=cp\n" - "ro.modem.wcn.enable=1\n" - "ro.modem.wcn.diag=/dev/slog_wcn\n" - "ro.modem.wcn.id=1\n" - "ro.modem.wcn.count=1\n" - "ro.modem.l.count=2\n" - "persist.msms.phone_count=2\n" - "persist.radio.multisim.config=dsds\n" - "ro.modem.gnss.diag=/dev/slog_gnss\n" - "persist.sys.support.vt=true\n" - "persist.sys.csvt=false\n" - "persist.radio.ssda.mode=csfb\n" - "ro.wcn.gpschip=ge2\n" - "ro.hotspot.enabled=1\n" - "reset_default_http_response=true\n" - "ro.void_charge_tip=true\n" - "ro.softaplte.coexist=true\n" - "ro.vowifi.softap.ee_warning=false\n" - "persist.sys.wifi.pocketmode=true\n" - "ro.wcn=enabled\n" - "ro.softap.whitelist=true\n" - "ro.btwifisoftap.coexist=true\n" - "persist.wifi.func.hidessid=true\n" - "ro.wifi.softap.maxstanum=10\n" - "ro.wifi.signal.optimized=true\n" - "ro.support.auto.roam=disabled\n" - "ro.wifip2p.coexist=true\n" - "persist.sys.notify.light.color=1\n" - "persist.sys.charging.tone=1\n" - "persist.support.fingerprint=true\n" - "persist.sprd.fp.lockapp=true\n" - "persist.sprd.fp.launchapp=true\n" - "persist.sys.volte.mode=Normal\n" - "ro.setupwizard.mode=OPTIONAL\n" - "ro.com.google.gmsversion=7.0_r12\n" - "ro.launcher.circleslide=true\n" - "ro.launcher.shakewallpaper=true\n" - "ro.launcher.defaultfoldername=true\n" - "ro.launcher.unreadinfo=true\n" - "ro.launcher.dynamicicon=true\n" - "ro.launcher.dynamicclock=true\n" - "ro.launcher.dynamiccalendar=true\n" - "ril.sim.phone_ex.start=true\n" - "persist.netmon.linger=10000\n" - "persist.sys.dalvik.vm.lib.2=libart.so\n" - "dalvik.vm.isa.x86_64.variant=silvermont\n" - "dalvik.vm.isa.x86_64.features=default\n" - "dalvik.vm.isa.x86.variant=silvermont\n" - "dalvik.vm.isa.x86.features=default\n" - "net.bt.name=Android\n" - "dalvik.vm.stack-trace-file=/data/anr/traces.txt\n" - "\n" - "# begin redstonefota properties\n" - "ro.redstone.version=LEAGOO_T5c_OS2.1_E_20180112\n" - "# end fota properties\n" - "ro.expect.recovery_id=0x0041a640e4805f06ee66e08584f90e9343c058db000000000000000000000000\n", + .content = "\n" + "# begin build properties\n" + "# autogenerated by buildinfo.sh\n" + "ro.build.id=NRD90M\n" + "###\n" + "ro.build.version.incremental=eng.root.20180112.175428\n" + "ro.build.version.sdk=24\n" + "ro.build.version.preview_sdk=0\n" + "ro.build.version.codename=REL\n" + "ro.build.version.all_codenames=REL\n" + "ro.build.version.release=7.0\n" + "ro.build.version.security_patch=2017-12-05\n" + "ro.build.version.base_os=\n" + "ro.build.date=Fri Jan 12 17:54:28 CST 2018\n" + "ro.build.date.utc=1515750868\n" + "ro.build.type=user\n" + "ro.build.user=root\n" + "ro.build.host=lxh\n" + "ro.build.tags=release-keys\n" + "ro.build.flavor=k500_lgt_511-user\n" + "ro.product.model=T5c\n" + "ro.product.brand=LEAGOO\n" + "ro.product.name=T5c\n" + "ro.product.device=T5c\n" + "ro.product.board=k500_lgt_511_vmm\n" + "# ro.product.cpu.abi and ro.product.cpu.abi2 are obsolete,\n" + "# use ro.product.cpu.abilist instead.\n" + "ro.product.cpu.abi=x86_64\n" + "ro.product.cpu.abilist=x86_64,x86,armeabi-v7a,armeabi,arm64-v8a\n" + "ro.product.cpu.abilist32=x86,armeabi-v7a,armeabi\n" + "ro.product.cpu.abilist64=x86_64,arm64-v8a\n" + "ro.product.manufacturer=LEAGOO\n" + "ro.product.locale=en-US\n" + "ro.wifi.channels=\n" + "ro.board.platform=sp9853i\n" + "# ro.build.product is obsolete; use ro.product.device\n" + "ro.build.product=T5c\n" + "# Do not try to parse description, fingerprint, or thumbprint\n" + "ro.build.description=k500_lgt_511-user 7.0 NRD90M eng.root.20180112.175428 release-keys\n" + "ro.build.fingerprint=LEAGOO/T5c/T5c:7.0/NRD90M/01121754:user/release-keys\n" + "ro.build.characteristics=nosdcard\n" + "# end build properties\n" + "#\n" + "# from device/sprd/isharkl2/k500_lgt_511/system.prop\n" + "#\n" + "# Default density config\n" + "ro.product.hardware=k500_lgt_511_v1.0.0\n" + "# Set Opengl ES Version 3.2\n" + "ro.opengles.version=196610\n" + "\n" + "\n" + "#enable audio nr tuning\n" + "ro.audio_tunning.nr=1\n" + "\n" + "#enable audio dual spk tuning\n" + "ro.audio_tunning.dual_spk=0\n" + "\n" + "\n" + "ro.fm.chip.port.UART.androidm=false\n" + "\n" + "persist.sys.cam.eois.dc.back=false\n" + "persist.sys.cam.eois.dc.front=false\n" + "persist.sys.cam.eois.dv.back=true\n" + "persist.sys.cam.eois.dv.front=false\n" + "persist.sys.cam.pipviv=false\n" + "\n" + "persist.sys.cam.battery.flash=15\n" + "\n" + "#FRP property for pst device\n" + "ro.frp.pst=/dev/block/platform/sdio_emmc/by-name/persist\n" + "\n" + "persist.sys.cam.refocus.enable=false\n" + "persist.sys.cam.ba.blur.version=0\n" + "persist.sys.cam.api.version=1\n" + "\n" + "persist.sys.blending.enable=true\n" + "\n" + "persist.sys.sprd.refocus.bokeh=true\n" + "qemu.hw.mainkeys=0\n" + "\n" + "#Enable sdcardfs feature\n" + "ro.sys.sdcardfs=true\n" + "persist.sys.sdcardfs=force_on\n" + "persist.bindcore.hdr=_4_0_1_2_3\n" + "\n" + "#disable partial update\n" + "debug.hwui.use_partial_updates=false\n" + "\n" + "persist.sys.fp.ck.period=3\n" + "#\n" + "# from device/sprd/isharkl2/k500_lgt_511/custom_config/custom.prop\n" + "#\n" + "ro.macro.custom.leagoo=true\n" + "ro.com.google.clientidbase=android-leagoo\n" + "ro.build.display.id=LEAGOO_T5c_OS2.1_E_20180112\n" + "ro.build.display.spid=SC9853_K500_LGT_511_V2.2_20180112\n" + "ro.build.display.spid.customer=LEAGOO_T5c_OS2.1_E_20180112\n" + "ro.leagoo.baseband.version=LEAGOO T5c_OS2.1\n" + "ro.product.bt.name=LEAGOO T5c\n" + "ro.leagoo.storage.ui=true\n" + "ro.modify.settings.icon=true\n" + "ro.lock.disable.statusbar=true\n" + "ro.leagoo.power.ui=true\n" + "ro.message.wake.up.screen=false\n" + "ro.sim.no.switch.languages=true\n" + "ro.test.playsound.outside=true\n" + "ro.hide.smart.control=true\n" + "persist.sys.fp.ck.period=3\n" + "ro.single.point.y.index=150\n" + "ro.email.signatures.same=true\n" + "ro.modify.message.notify=true\n" + "ro.temp.ntc=true\n" + "ro.disable.sound.effects=true\n" + "ro.not.support.menu.key=true\n" + "ro.not.support.back.key=true\n" + "ro.not.support.home.key=true\n" + "ro.ram.display.config.3gb=true\n" + "ro.rm.calllog.geocode=true\n" + "ro.preload.media.internel=true\n" + "ro.support.video.dream=true\n" + "#\n" + "# ADDITIONAL_BUILD_PROPERTIES\n" + "#\n" + "persist.radio.modem.config=TL_LF_TD_W_G,W_G\n" + "persist.radio.modem.workmode=9,255\n" + "ro.radio.modem.capability=TL_LF_TD_W_G,W_G\n" + "ro.dalvik.vm.isa.arm=x86\n" + "ro.enable.native.bridge.exec=1\n" + "ro.dalvik.vm.isa.arm64=x86_64\n" + "ro.enable.native.bridge.exec64=1\n" + "ro.sys.prc_compatibility=1\n" + "ro.hwui.layer_cache_size=48\n" + "ro.hwui.r_buffer_cache_size=8\n" + "ro.hwui.path_cache_size=32\n" + "ro.hwui.gradient_cache_size=1\n" + "ro.hwui.drop_shadow_cache_size=6\n" + "ro.hwui.texture_cache_flushrate=0.4\n" + "ro.hwui.text_small_cache_width=1024\n" + "ro.hwui.text_small_cache_height=1024\n" + "ro.hwui.text_large_cache_width=2048\n" + "ro.hwui.text_large_cache_height=1024\n" + "dalvik.vm.sprd_usejitprofiles=false\n" + "ro.config.notification_sound=LEAGOO-Pops.mp3\n" + "ro.config.alarm_alert=Alarm_Classic.ogg\n" + "ro.config.ringtone=LEAGOO-Turkish.mp3\n" + "ro.config.ringtone0=LEAGOO-Turkish.mp3\n" + "ro.config.ringtone1=LEAGOO-Turkish.mp3\n" + "ro.config.message_sound0=Argon.ogg\n" + "ro.config.message_sound1=Argon.ogg\n" + "ro.config.message_sound=pixiedust.ogg\n" + "ro.product.locale.language=en\n" + "ro.product.locale.region=US\n" + "persist.sys.timezone=Asia/Calcutta\n" + "persist.sys.defaulttimezone=Asia/Calcutta\n" + "ro.product.first_api_level=24\n" + "ro.carrier=unknown\n" + "rild.libpath=/system/lib64/libsprd-ril.so\n" + "ro.radio.modemtype=l\n" + "ro.telephony.default_network=9\n" + "keyguard.no_require_sim=true\n" + "ro.com.android.dataroaming=false\n" + "ro.simlock.unlock.autoshow=1\n" + "ro.simlock.unlock.bynv=0\n" + "ro.simlock.onekey.lock=0\n" + "persist.sys.engpc.disable=1\n" + "persist.sys.sprd.modemreset=1\n" + "ro.product.partitionpath=/dev/block/platform/sdio_emmc/by-name/\n" + "ro.modem.l.dev=/proc/cptl/\n" + "ro.modem.l.tty=/dev/stty_lte\n" + "ro.modem.l.diag=/dev/sdiag_lte\n" + "ro.modem.l.log=/dev/slog_lte\n" + "ro.modem.l.assert=/dev/spipe_lte2\n" + "ro.modem.l.fixnv_size=0xc8000\n" + "ro.modem.l.runnv_size=0xe8000\n" + "ro.sp.log=/dev/slog_pm\n" + "persist.modem.l.nvp=l_\n" + "persist.modem.l.enable=1\n" + "ro.storage.flash_type=2\n" + "sys.internal.emulated=1\n" + "persist.storage.type=2\n" + "ro.storage.install2internal=0\n" + "drm.service.enabled=true\n" + "persist.sys.sprd.wcnreset=1\n" + "persist.sys.start_udpdatastall=0\n" + "persist.sys.apr.enabled=0\n" + "persist.sys.ag.enable=false\n" + "ro.adb.secure=1\n" + "persist.sys.apr.intervaltime=1\n" + "persist.sys.apr.testgroup=CSSLAB\n" + "persist.sys.apr.autoupload=1\n" + "ro.modem.l.eth=seth_lte\n" + "ro.modem.l.snd=1\n" + "ro.modem.l.loop=/dev/spipe_lte0\n" + "ro.modem.l.nv=/dev/spipe_lte1\n" + "ro.modem.l.vbc=/dev/spipe_lte6\n" + "ro.modem.l.id=0\n" + "persist.sys.heartbeat.enable=1\n" + "persist.sys.powerHint.enable=1\n" + "persist.ylog.modem.shutdownlog=1\n" + "persist.sys.cam.photo.gallery=true\n" + "persist.sys.ucam.puzzle=false\n" + "persist.sys.ucam.edit=false\n" + "persist.sys.cam.timestamp=false\n" + "persist.sys.cam.gif=false\n" + "persist.sys.cam.scenery=false\n" + "persist.sys.cam.vgesture=false\n" + "persist.sys.cam.gps=true\n" + "persist.sys.cam.normalhdr=true\n" + "persist.sys.cam.sfv.alter=true\n" + "persist.sys.cam.arcsoft.filter=true\n" + "persist.sys.cam.filter.highfps=true\n" + "persist.sys.cam.new.wideangle=true\n" + "persist.sys.cam.3dnr=true\n" + "persist.sys.bsservice.enable=1\n" + "ro.wcn.hardware.product=marlin2\n" + "ro.bt.bdaddr_path=/data/misc/bluedroid/btmac.txt\n" + "persist.sys.volte.enable=true\n" + "ro.trim.config=true\n" + "persist.sys.vilte.socket=ap\n" + "persist.dbg.wfc_avail_ovr=1\n" + "persist.sys.vowifi.voice=cp\n" + "ro.modem.wcn.enable=1\n" + "ro.modem.wcn.diag=/dev/slog_wcn\n" + "ro.modem.wcn.id=1\n" + "ro.modem.wcn.count=1\n" + "ro.modem.l.count=2\n" + "persist.msms.phone_count=2\n" + "persist.radio.multisim.config=dsds\n" + "ro.modem.gnss.diag=/dev/slog_gnss\n" + "persist.sys.support.vt=true\n" + "persist.sys.csvt=false\n" + "persist.radio.ssda.mode=csfb\n" + "ro.wcn.gpschip=ge2\n" + "ro.hotspot.enabled=1\n" + "reset_default_http_response=true\n" + "ro.void_charge_tip=true\n" + "ro.softaplte.coexist=true\n" + "ro.vowifi.softap.ee_warning=false\n" + "persist.sys.wifi.pocketmode=true\n" + "ro.wcn=enabled\n" + "ro.softap.whitelist=true\n" + "ro.btwifisoftap.coexist=true\n" + "persist.wifi.func.hidessid=true\n" + "ro.wifi.softap.maxstanum=10\n" + "ro.wifi.signal.optimized=true\n" + "ro.support.auto.roam=disabled\n" + "ro.wifip2p.coexist=true\n" + "persist.sys.notify.light.color=1\n" + "persist.sys.charging.tone=1\n" + "persist.support.fingerprint=true\n" + "persist.sprd.fp.lockapp=true\n" + "persist.sprd.fp.launchapp=true\n" + "persist.sys.volte.mode=Normal\n" + "ro.setupwizard.mode=OPTIONAL\n" + "ro.com.google.gmsversion=7.0_r12\n" + "ro.launcher.circleslide=true\n" + "ro.launcher.shakewallpaper=true\n" + "ro.launcher.defaultfoldername=true\n" + "ro.launcher.unreadinfo=true\n" + "ro.launcher.dynamicicon=true\n" + "ro.launcher.dynamicclock=true\n" + "ro.launcher.dynamiccalendar=true\n" + "ril.sim.phone_ex.start=true\n" + "persist.netmon.linger=10000\n" + "persist.sys.dalvik.vm.lib.2=libart.so\n" + "dalvik.vm.isa.x86_64.variant=silvermont\n" + "dalvik.vm.isa.x86_64.features=default\n" + "dalvik.vm.isa.x86.variant=silvermont\n" + "dalvik.vm.isa.x86.features=default\n" + "net.bt.name=Android\n" + "dalvik.vm.stack-trace-file=/data/anr/traces.txt\n" + "\n" + "# begin redstonefota properties\n" + "ro.redstone.version=LEAGOO_T5c_OS2.1_E_20180112\n" + "# end fota properties\n" + "ro.expect.recovery_id=0x0041a640e4805f06ee66e08584f90e9343c058db000000000000000000000000\n", }, { .path = "/sys/devices/system/cpu/kernel_max", @@ -811,7 +810,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/modalias", .size = 324, - .content = "cpu:type:x86,ven0000fam0006mod0075:feature:,0000,0001,0002,0003,0004,0005,0006,0007,0008,0009,000B,000C,000D,000E,000F,0010,0011,0013,0017,0018,0019,001A,001B,001C,0034,003B,003D,0068,006B,006F,0070,0072,0074,0075,0076,0078,0080,0081,0083,0089,008D,008E,008F,0093,0094,0096,0097,0098,0099,00C0,00C8,00E1,0121,0127,0129,012D\n", + .content = + "cpu:type:x86,ven0000fam0006mod0075:feature:,0000,0001,0002,0003,0004,0005,0006,0007,0008,0009,000B,000C,000D,000E,000F,0010,0011,0013,0017,0018,0019,001A,001B,001C,0034,003B,003D,0068,006B,006F,0070,0072,0074,0075,0076,0078,0080,0081,0083,0089,008D,008E,008F,0093,0094,0096,0097,0098,0099,00C0,00C8,00E1,0121,0127,0129,012D\n", }, { .path = "/sys/devices/system/cpu/cpuidle/current_driver", @@ -881,13 +881,12 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 76, - .content = - "624000 1030325\n" - "936000 1271\n" - "1248000 723\n" - "1560000 1240\n" - "1872000 22490\n" - "2028000 0\n", + .content = "624000 1030325\n" + "936000 1271\n" + "1248000 723\n" + "1560000 1240\n" + "1872000 22490\n" + "2028000 0\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -897,15 +896,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/trans_table", .size = 521, - .content = - " From : To\n" - " : 624000 936000 1248000 1560000 1872000 2028000 \n" - " 624000: 0 166 0 5 507 0 \n" - " 936000: 222 0 42 1 76 0 \n" - " 1248000: 74 39 0 22 88 0 \n" - " 1560000: 46 19 34 0 132 0 \n" - " 1872000: 337 117 147 202 0 0 \n" - " 2028000: 0 0 0 0 0 0 \n", + .content = " From : To\n" + " : 624000 936000 1248000 1560000 1872000 2028000 \n" + " 624000: 0 166 0 5 507 0 \n" + " 936000: 222 0 42 1 76 0 \n" + " 1248000: 74 39 0 22 88 0 \n" + " 1560000: 46 19 34 0 132 0 \n" + " 1872000: 337 117 147 202 0 0 \n" + " 2028000: 0 0 0 0 0 0 \n", }, { .path = "/sys/devices/system/cpu/cpu0/topology/core_id", @@ -995,13 +993,12 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 76, - .content = - "624000 1030676\n" - "936000 1271\n" - "1248000 723\n" - "1560000 1240\n" - "1872000 22490\n" - "2028000 0\n", + .content = "624000 1030676\n" + "936000 1271\n" + "1248000 723\n" + "1560000 1240\n" + "1872000 22490\n" + "2028000 0\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -1011,15 +1008,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/trans_table", .size = 521, - .content = - " From : To\n" - " : 624000 936000 1248000 1560000 1872000 2028000 \n" - " 624000: 0 166 0 5 507 0 \n" - " 936000: 222 0 42 1 76 0 \n" - " 1248000: 74 39 0 22 88 0 \n" - " 1560000: 46 19 34 0 132 0 \n" - " 1872000: 337 117 147 202 0 0 \n" - " 2028000: 0 0 0 0 0 0 \n", + .content = " From : To\n" + " : 624000 936000 1248000 1560000 1872000 2028000 \n" + " 624000: 0 166 0 5 507 0 \n" + " 936000: 222 0 42 1 76 0 \n" + " 1248000: 74 39 0 22 88 0 \n" + " 1560000: 46 19 34 0 132 0 \n" + " 1872000: 337 117 147 202 0 0 \n" + " 2028000: 0 0 0 0 0 0 \n", }, { .path = "/sys/devices/system/cpu/cpu1/topology/core_id", @@ -1109,13 +1105,12 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 76, - .content = - "624000 1031019\n" - "936000 1271\n" - "1248000 723\n" - "1560000 1240\n" - "1872000 22495\n" - "2028000 0\n", + .content = "624000 1031019\n" + "936000 1271\n" + "1248000 723\n" + "1560000 1240\n" + "1872000 22495\n" + "2028000 0\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -1125,15 +1120,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/trans_table", .size = 521, - .content = - " From : To\n" - " : 624000 936000 1248000 1560000 1872000 2028000 \n" - " 624000: 0 166 0 5 508 0 \n" - " 936000: 222 0 42 1 76 0 \n" - " 1248000: 74 39 0 22 88 0 \n" - " 1560000: 46 19 34 0 132 0 \n" - " 1872000: 338 117 147 202 0 0 \n" - " 2028000: 0 0 0 0 0 0 \n", + .content = " From : To\n" + " : 624000 936000 1248000 1560000 1872000 2028000 \n" + " 624000: 0 166 0 5 508 0 \n" + " 936000: 222 0 42 1 76 0 \n" + " 1248000: 74 39 0 22 88 0 \n" + " 1560000: 46 19 34 0 132 0 \n" + " 1872000: 338 117 147 202 0 0 \n" + " 2028000: 0 0 0 0 0 0 \n", }, { .path = "/sys/devices/system/cpu/cpu2/topology/core_id", @@ -1223,13 +1217,12 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 76, - .content = - "624000 1031362\n" - "936000 1271\n" - "1248000 723\n" - "1560000 1240\n" - "1872000 22495\n" - "2028000 0\n", + .content = "624000 1031362\n" + "936000 1271\n" + "1248000 723\n" + "1560000 1240\n" + "1872000 22495\n" + "2028000 0\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -1239,15 +1232,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/trans_table", .size = 521, - .content = - " From : To\n" - " : 624000 936000 1248000 1560000 1872000 2028000 \n" - " 624000: 0 166 0 5 508 0 \n" - " 936000: 222 0 42 1 76 0 \n" - " 1248000: 74 39 0 22 88 0 \n" - " 1560000: 46 19 34 0 132 0 \n" - " 1872000: 338 117 147 202 0 0 \n" - " 2028000: 0 0 0 0 0 0 \n", + .content = " From : To\n" + " : 624000 936000 1248000 1560000 1872000 2028000 \n" + " 624000: 0 166 0 5 508 0 \n" + " 936000: 222 0 42 1 76 0 \n" + " 1248000: 74 39 0 22 88 0 \n" + " 1560000: 46 19 34 0 132 0 \n" + " 1872000: 338 117 147 202 0 0 \n" + " 2028000: 0 0 0 0 0 0 \n", }, { .path = "/sys/devices/system/cpu/cpu3/topology/core_id", @@ -1337,12 +1329,11 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/time_in_state", .size = 65, - .content = - "624000 1047415\n" - "936000 1704\n" - "1248000 2590\n" - "1560000 705\n" - "1872000 5034\n", + .content = "624000 1047415\n" + "936000 1704\n" + "1248000 2590\n" + "1560000 705\n" + "1872000 5034\n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/total_trans", @@ -1352,14 +1343,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/trans_table", .size = 389, - .content = - " From : To\n" - " : 624000 936000 1248000 1560000 1872000 \n" - " 624000: 0 72 2 13 122 \n" - " 936000: 52 0 48 3 29 \n" - " 1248000: 42 30 0 24 21 \n" - " 1560000: 23 8 25 0 36 \n" - " 1872000: 92 22 42 52 0 \n", + .content = " From : To\n" + " : 624000 936000 1248000 1560000 1872000 \n" + " 624000: 0 72 2 13 122 \n" + " 936000: 52 0 48 3 29 \n" + " 1248000: 42 30 0 24 21 \n" + " 1560000: 23 8 25 0 36 \n" + " 1872000: 92 22 42 52 0 \n", }, { .path = "/sys/devices/system/cpu/cpu4/topology/core_id", @@ -1449,12 +1439,11 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/time_in_state", .size = 65, - .content = - "624000 1047808\n" - "936000 1704\n" - "1248000 2590\n" - "1560000 705\n" - "1872000 5034\n", + .content = "624000 1047808\n" + "936000 1704\n" + "1248000 2590\n" + "1560000 705\n" + "1872000 5034\n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/total_trans", @@ -1464,14 +1453,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/trans_table", .size = 389, - .content = - " From : To\n" - " : 624000 936000 1248000 1560000 1872000 \n" - " 624000: 0 72 2 13 122 \n" - " 936000: 52 0 48 3 29 \n" - " 1248000: 42 30 0 24 21 \n" - " 1560000: 23 8 25 0 36 \n" - " 1872000: 92 22 42 52 0 \n", + .content = " From : To\n" + " : 624000 936000 1248000 1560000 1872000 \n" + " 624000: 0 72 2 13 122 \n" + " 936000: 52 0 48 3 29 \n" + " 1248000: 42 30 0 24 21 \n" + " 1560000: 23 8 25 0 36 \n" + " 1872000: 92 22 42 52 0 \n", }, { .path = "/sys/devices/system/cpu/cpu5/topology/core_id", @@ -1561,12 +1549,11 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/time_in_state", .size = 65, - .content = - "624000 1048171\n" - "936000 1704\n" - "1248000 2590\n" - "1560000 705\n" - "1872000 5034\n", + .content = "624000 1048171\n" + "936000 1704\n" + "1248000 2590\n" + "1560000 705\n" + "1872000 5034\n", }, { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/total_trans", @@ -1576,14 +1563,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/trans_table", .size = 389, - .content = - " From : To\n" - " : 624000 936000 1248000 1560000 1872000 \n" - " 624000: 0 72 2 13 122 \n" - " 936000: 52 0 48 3 29 \n" - " 1248000: 42 30 0 24 21 \n" - " 1560000: 23 8 25 0 36 \n" - " 1872000: 92 22 42 52 0 \n", + .content = " From : To\n" + " : 624000 936000 1248000 1560000 1872000 \n" + " 624000: 0 72 2 13 122 \n" + " 936000: 52 0 48 3 29 \n" + " 1248000: 42 30 0 24 21 \n" + " 1560000: 23 8 25 0 36 \n" + " 1872000: 92 22 42 52 0 \n", }, { .path = "/sys/devices/system/cpu/cpu6/topology/core_id", @@ -1673,12 +1659,11 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/time_in_state", .size = 65, - .content = - "624000 1048515\n" - "936000 1704\n" - "1248000 2590\n" - "1560000 705\n" - "1872000 5034\n", + .content = "624000 1048515\n" + "936000 1704\n" + "1248000 2590\n" + "1560000 705\n" + "1872000 5034\n", }, { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/total_trans", @@ -1688,14 +1673,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/trans_table", .size = 389, - .content = - " From : To\n" - " : 624000 936000 1248000 1560000 1872000 \n" - " 624000: 0 72 2 13 122 \n" - " 936000: 52 0 48 3 29 \n" - " 1248000: 42 30 0 24 21 \n" - " 1560000: 23 8 25 0 36 \n" - " 1872000: 92 22 42 52 0 \n", + .content = " From : To\n" + " : 624000 936000 1248000 1560000 1872000 \n" + " 624000: 0 72 2 13 122 \n" + " 936000: 52 0 48 3 29 \n" + " 1248000: 42 30 0 24 21 \n" + " 1560000: 23 8 25 0 36 \n" + " 1872000: 92 22 42 52 0 \n", }, { .path = "/sys/devices/system/cpu/cpu7/topology/core_id", @@ -1727,7 +1711,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "7\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -3399,6 +3383,6 @@ struct cpuinfo_mock_property properties[] = { .key = "zram.disksize", .value = "1024", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/lenovo-a6600-plus.cc b/test/mock/lenovo-a6600-plus.cc index 0af9e97f..0a4492ad 100644 --- a/test/mock/lenovo-a6600-plus.cc +++ b/test/mock/lenovo-a6600-plus.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(4, cpuinfo_get_processors_count()); @@ -208,8 +207,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("MediaTek MT6735P", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "MediaTek MT6735P", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -400,8 +401,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -452,8 +455,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -504,8 +509,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/lenovo-a6600-plus.h b/test/mock/lenovo-a6600-plus.h index 9b7a5044..0c87dd43 100644 --- a/test/mock/lenovo-a6600-plus.h +++ b/test/mock/lenovo-a6600-plus.h @@ -363,25 +363,23 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpufreq/all_time_in_state", .size = 215, - .content = - "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\t\n" - "221000\t\t31\t\t31\t\t31\t\t31\t\t\n" - "364000\t\t0\t\t0\t\t0\t\t0\t\t\n" - "494000\t\t0\t\t0\t\t0\t\t0\t\t\n" - "637000\t\t4\t\t4\t\t4\t\t4\t\t\n" - "793000\t\t13\t\t13\t\t13\t\t13\t\t\n" - "858000\t\t0\t\t0\t\t0\t\t0\t\t\n" - "923000\t\t8\t\t8\t\t8\t\t8\t\t\n" - "988000\t\t605\t\t605\t\t605\t\t605\t\t\n", + .content = "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\t\n" + "221000\t\t31\t\t31\t\t31\t\t31\t\t\n" + "364000\t\t0\t\t0\t\t0\t\t0\t\t\n" + "494000\t\t0\t\t0\t\t0\t\t0\t\t\n" + "637000\t\t4\t\t4\t\t4\t\t4\t\t\n" + "793000\t\t13\t\t13\t\t13\t\t13\t\t\n" + "858000\t\t0\t\t0\t\t0\t\t0\t\t\n" + "923000\t\t8\t\t8\t\t8\t\t8\t\t\n" + "988000\t\t605\t\t605\t\t605\t\t605\t\t\n", }, { .path = "/sys/devices/system/cpu/cpufreq/current_in_state", .size = 312, - .content = - "CPU0:988000=0 923000=0 858000=0 793000=0 637000=0 494000=0 364000=0 221000=0 \n" - "CPU1:988000=0 923000=0 858000=0 793000=0 637000=0 494000=0 364000=0 221000=0 \n" - "CPU2:988000=0 923000=0 858000=0 793000=0 637000=0 494000=0 364000=0 221000=0 \n" - "CPU3:988000=0 923000=0 858000=0 793000=0 637000=0 494000=0 364000=0 221000=0 \n", + .content = "CPU0:988000=0 923000=0 858000=0 793000=0 637000=0 494000=0 364000=0 221000=0 \n" + "CPU1:988000=0 923000=0 858000=0 793000=0 637000=0 494000=0 364000=0 221000=0 \n" + "CPU2:988000=0 923000=0 858000=0 793000=0 637000=0 494000=0 364000=0 221000=0 \n" + "CPU3:988000=0 923000=0 858000=0 793000=0 637000=0 494000=0 364000=0 221000=0 \n", }, { .path = "/sys/devices/system/cpu/cpuidle/current_driver", @@ -401,11 +399,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cputopo/glbinfo", .size = 58, - .content = - "big/little arch: no\n" - "nr_cups: 4\n" - "nr_clusters: 1\n" - "cluster0: f\n", + .content = "big/little arch: no\n" + "nr_cups: 4\n" + "nr_clusters: 1\n" + "cluster0: f\n", }, { .path = "/sys/devices/system/cpu/cputopo/is_big_little", @@ -480,15 +477,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 76, - .content = - "988000 732\n" - "923000 8\n" - "858000 0\n" - "793000 13\n" - "637000 4\n" - "494000 0\n" - "364000 0\n" - "221000 31\n", + .content = "988000 732\n" + "923000 8\n" + "858000 0\n" + "793000 13\n" + "637000 4\n" + "494000 0\n" + "364000 0\n" + "221000 31\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -598,15 +594,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 77, - .content = - "988000 1000\n" - "923000 8\n" - "858000 0\n" - "793000 13\n" - "637000 4\n" - "494000 0\n" - "364000 0\n" - "221000 31\n", + .content = "988000 1000\n" + "923000 8\n" + "858000 0\n" + "793000 13\n" + "637000 4\n" + "494000 0\n" + "364000 0\n" + "221000 31\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -716,15 +711,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 77, - .content = - "988000 1248\n" - "923000 8\n" - "858000 0\n" - "793000 13\n" - "637000 4\n" - "494000 0\n" - "364000 0\n" - "221000 31\n", + .content = "988000 1248\n" + "923000 8\n" + "858000 0\n" + "793000 13\n" + "637000 4\n" + "494000 0\n" + "364000 0\n" + "221000 31\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -776,7 +770,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 3, .content = "04\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ @@ -2373,6 +2367,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wifi.tethering.interface", .value = "ap0", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/lenovo-vibe-x2.cc b/test/mock/lenovo-vibe-x2.cc index cc931d78..63a72589 100644 --- a/test/mock/lenovo-vibe-x2.cc +++ b/test/mock/lenovo-vibe-x2.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(8, cpuinfo_get_processors_count()); @@ -315,8 +314,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("MediaTek MT6595", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "MediaTek MT6595", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -520,8 +521,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -585,8 +588,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -651,8 +656,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/lenovo-vibe-x2.h b/test/mock/lenovo-vibe-x2.h index 6aca439c..76a2d406 100644 --- a/test/mock/lenovo-vibe-x2.h +++ b/test/mock/lenovo-vibe-x2.h @@ -2,20 +2,19 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 314, - .content = - "Processor\t: ARMv7 Processor rev 5 (v7l)\n" - "processor\t: 0\n" - "BogoMIPS\t: 38.40\n" - "Features\t: swp half thumb fastmult vfp edsp thumbee neon vfpv3 tls vfpv4 idiva idivt \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xc07\n" - "CPU revision\t: 5\n" - "\n" - "Hardware\t: MT6595\n" - "Revision\t: 0000\n" - "Serial\t\t: 0000000000000000\n", + .content = "Processor\t: ARMv7 Processor rev 5 (v7l)\n" + "processor\t: 0\n" + "BogoMIPS\t: 38.40\n" + "Features\t: swp half thumb fastmult vfp edsp thumbee neon vfpv3 tls vfpv4 idiva idivt \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xc07\n" + "CPU revision\t: 5\n" + "\n" + "Hardware\t: MT6595\n" + "Revision\t: 0000\n" + "Serial\t\t: 0000000000000000\n", }, { .path = "/system/build.prop", @@ -252,11 +251,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cputopo/glbinfo", .size = 72, - .content = - "big/little arch: yes\n" - "big/little cpumask:f0/0f\n" - "nr_cups: 8\n" - "nr_clusters: 2\n", + .content = "big/little arch: yes\n" + "big/little cpumask:f0/0f\n" + "nr_cups: 8\n" + "nr_clusters: 2\n", }, { .path = "/sys/devices/system/cpu/cputopo/is_big_little", @@ -336,15 +334,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 87, - .content = - "1690000 1493\n" - "1495000 0\n" - "1365000 8\n" - "1248000 4\n" - "1144000 20654\n" - "1001000 12\n" - "806000 33\n" - "403000 0\n", + .content = "1690000 1493\n" + "1495000 0\n" + "1365000 8\n" + "1248000 4\n" + "1144000 20654\n" + "1001000 12\n" + "806000 33\n" + "403000 0\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -396,7 +393,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 3, .content = "01\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ @@ -1853,6 +1850,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.wfd.security.image", .value = "1", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/lg-k10-eu.cc b/test/mock/lg-k10-eu.cc index 6b8c8bcf..794b6627 100644 --- a/test/mock/lg-k10-eu.cc +++ b/test/mock/lg-k10-eu.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(4, cpuinfo_get_processors_count()); @@ -208,8 +207,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Qualcomm MSM8916", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Qualcomm MSM8916", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -400,8 +401,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -452,8 +455,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -504,8 +509,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/lg-k10-eu.h b/test/mock/lg-k10-eu.h index 31cc93fd..9c3e846d 100644 --- a/test/mock/lg-k10-eu.h +++ b/test/mock/lg-k10-eu.h @@ -2,51 +2,50 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 1141, - .content = - "processor\t: 0\n" - "model name\t: ARMv7 Processor rev 0 (v7l)\n" - "BogoMIPS\t: 38.40\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 0\n" - "\n" - "processor\t: 1\n" - "model name\t: ARMv7 Processor rev 0 (v7l)\n" - "BogoMIPS\t: 38.40\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 0\n" - "\n" - "processor\t: 2\n" - "model name\t: ARMv7 Processor rev 0 (v7l)\n" - "BogoMIPS\t: 38.40\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 0\n" - "\n" - "processor\t: 3\n" - "model name\t: ARMv7 Processor rev 0 (v7l)\n" - "BogoMIPS\t: 38.40\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 0\n" - "\n" - "Hardware\t: Qualcomm Technologies, Inc MSM8916\n" - "Revision\t: 0009\n" - "Serial\t\t: 0000000000000000\n" - "Processor\t: ARMv7 Processor rev 0 (v7l)\n", + .content = "processor\t: 0\n" + "model name\t: ARMv7 Processor rev 0 (v7l)\n" + "BogoMIPS\t: 38.40\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 0\n" + "\n" + "processor\t: 1\n" + "model name\t: ARMv7 Processor rev 0 (v7l)\n" + "BogoMIPS\t: 38.40\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 0\n" + "\n" + "processor\t: 2\n" + "model name\t: ARMv7 Processor rev 0 (v7l)\n" + "BogoMIPS\t: 38.40\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 0\n" + "\n" + "processor\t: 3\n" + "model name\t: ARMv7 Processor rev 0 (v7l)\n" + "BogoMIPS\t: 38.40\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 0\n" + "\n" + "Hardware\t: Qualcomm Technologies, Inc MSM8916\n" + "Revision\t: 0009\n" + "Serial\t\t: 0000000000000000\n" + "Processor\t: ARMv7 Processor rev 0 (v7l)\n", }, { .path = "/system/build.prop", @@ -481,15 +480,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 84, - .content = - "200000 0\n" - "400000 0\n" - "533333 0\n" - "800000 141\n" - "998400 290\n" - "1094400 74\n" - "1152000 82\n" - "1209600 4075\n", + .content = "200000 0\n" + "400000 0\n" + "533333 0\n" + "800000 141\n" + "998400 290\n" + "1094400 74\n" + "1152000 82\n" + "1209600 4075\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -579,15 +577,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 84, - .content = - "200000 0\n" - "400000 0\n" - "533333 0\n" - "800000 347\n" - "998400 295\n" - "1094400 74\n" - "1152000 95\n" - "1209600 4085\n", + .content = "200000 0\n" + "400000 0\n" + "533333 0\n" + "800000 347\n" + "998400 295\n" + "1094400 74\n" + "1152000 95\n" + "1209600 4085\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -677,15 +674,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 84, - .content = - "200000 0\n" - "400000 0\n" - "533333 0\n" - "800000 568\n" - "998400 306\n" - "1094400 74\n" - "1152000 95\n" - "1209600 4085\n", + .content = "200000 0\n" + "400000 0\n" + "533333 0\n" + "800000 568\n" + "998400 306\n" + "1094400 74\n" + "1152000 95\n" + "1209600 4085\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -775,15 +771,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 84, - .content = - "200000 0\n" - "400000 0\n" - "533333 0\n" - "800000 805\n" - "998400 306\n" - "1094400 74\n" - "1152000 95\n" - "1209600 4085\n", + .content = "200000 0\n" + "400000 0\n" + "533333 0\n" + "800000 805\n" + "998400 306\n" + "1094400 74\n" + "1152000 95\n" + "1209600 4085\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -820,7 +815,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "8\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ @@ -2897,6 +2892,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.monitor.status", .value = "attach", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/lg-optimus-g-pro.cc b/test/mock/lg-optimus-g-pro.cc index a6630203..0425f81f 100644 --- a/test/mock/lg-optimus-g-pro.cc +++ b/test/mock/lg-optimus-g-pro.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(4, cpuinfo_get_processors_count()); @@ -208,8 +207,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Qualcomm APQ8064", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Qualcomm APQ8064", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -400,8 +401,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -452,8 +455,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -492,9 +497,7 @@ TEST(L2, non_null) { TEST(L2, size) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - switch (i) { - ASSERT_EQ(2 * 1024 * 1024, cpuinfo_get_l2_cache(i)->size); - } + switch (i) { ASSERT_EQ(2 * 1024 * 1024, cpuinfo_get_l2_cache(i)->size); } } } @@ -506,8 +509,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/lg-optimus-g-pro.h b/test/mock/lg-optimus-g-pro.h index 20c72008..d34c2f82 100644 --- a/test/mock/lg-optimus-g-pro.h +++ b/test/mock/lg-optimus-g-pro.h @@ -2,30 +2,29 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 400, - .content = - "Processor\t: ARMv7 Processor rev 0 (v7l)\n" - "processor\t: 0\n" - "BogoMIPS\t: 13.53\n" - "\n" - "processor\t: 1\n" - "BogoMIPS\t: 13.53\n" - "\n" - "processor\t: 2\n" - "BogoMIPS\t: 13.53\n" - "\n" - "processor\t: 3\n" - "BogoMIPS\t: 13.53\n" - "\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 \n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x1\n" - "CPU part\t: 0x06f\n" - "CPU revision\t: 0\n" - "\n" - "Hardware\t: QCT APQ8064 MTP\n" - "Revision\t: 000a\n" - "Serial\t\t: 0000000000000000\n", + .content = "Processor\t: ARMv7 Processor rev 0 (v7l)\n" + "processor\t: 0\n" + "BogoMIPS\t: 13.53\n" + "\n" + "processor\t: 1\n" + "BogoMIPS\t: 13.53\n" + "\n" + "processor\t: 2\n" + "BogoMIPS\t: 13.53\n" + "\n" + "processor\t: 3\n" + "BogoMIPS\t: 13.53\n" + "\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 \n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0x06f\n" + "CPU revision\t: 0\n" + "\n" + "Hardware\t: QCT APQ8064 MTP\n" + "Revision\t: 000a\n" + "Serial\t\t: 0000000000000000\n", }, { .path = "/system/build.prop", @@ -504,7 +503,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies", .size = 107, - .content = "384000 486000 594000 702000 810000 918000 1026000 1134000 1242000 1350000 1458000 1566000 1674000 1728000 \n", + .content = + "384000 486000 594000 702000 810000 918000 1026000 1134000 1242000 1350000 1458000 1566000 1674000 1728000 \n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors", @@ -534,21 +534,20 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 142, - .content = - "384000 0\n" - "486000 0\n" - "594000 0\n" - "702000 0\n" - "810000 0\n" - "918000 0\n" - "1026000 22\n" - "1134000 20\n" - "1242000 2882\n" - "1350000 0\n" - "1458000 0\n" - "1566000 0\n" - "1674000 0\n" - "1728000 1175\n", + .content = "384000 0\n" + "486000 0\n" + "594000 0\n" + "702000 0\n" + "810000 0\n" + "918000 0\n" + "1026000 22\n" + "1134000 20\n" + "1242000 2882\n" + "1350000 0\n" + "1458000 0\n" + "1566000 0\n" + "1674000 0\n" + "1728000 1175\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -613,7 +612,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_frequencies", .size = 107, - .content = "384000 486000 594000 702000 810000 918000 1026000 1134000 1242000 1350000 1458000 1566000 1674000 1728000 \n", + .content = + "384000 486000 594000 702000 810000 918000 1026000 1134000 1242000 1350000 1458000 1566000 1674000 1728000 \n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_governors", @@ -648,21 +648,20 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 145, - .content = - "384000 11\n" - "486000 0\n" - "594000 0\n" - "702000 0\n" - "810000 0\n" - "918000 70\n" - "1026000 337\n" - "1134000 10\n" - "1242000 484\n" - "1350000 24\n" - "1458000 30\n" - "1566000 0\n" - "1674000 0\n" - "1728000 987\n", + .content = "384000 11\n" + "486000 0\n" + "594000 0\n" + "702000 0\n" + "810000 0\n" + "918000 70\n" + "1026000 337\n" + "1134000 10\n" + "1242000 484\n" + "1350000 24\n" + "1458000 30\n" + "1566000 0\n" + "1674000 0\n" + "1728000 987\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -707,21 +706,20 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 134, - .content = - "384000 0\n" - "486000 0\n" - "594000 0\n" - "702000 0\n" - "810000 0\n" - "918000 0\n" - "1026000 8\n" - "1134000 0\n" - "1242000 0\n" - "1350000 0\n" - "1458000 0\n" - "1566000 0\n" - "1674000 0\n" - "1728000 0\n", + .content = "384000 0\n" + "486000 0\n" + "594000 0\n" + "702000 0\n" + "810000 0\n" + "918000 0\n" + "1026000 8\n" + "1134000 0\n" + "1242000 0\n" + "1350000 0\n" + "1458000 0\n" + "1566000 0\n" + "1674000 0\n" + "1728000 0\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -758,7 +756,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "2\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -2538,6 +2536,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.lge.wifidisplay", .value = "both", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/meizu-pro-6.cc b/test/mock/meizu-pro-6.cc index 36cdd2a4..213bb725 100644 --- a/test/mock/meizu-pro-6.cc +++ b/test/mock/meizu-pro-6.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(10, cpuinfo_get_processors_count()); @@ -389,8 +388,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("MediaTek MT6797T", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "MediaTek MT6797T", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -432,59 +433,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -639,8 +640,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -721,8 +724,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -781,8 +786,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/meizu-pro-6.h b/test/mock/meizu-pro-6.h index abf2cae4..296100e8 100644 --- a/test/mock/meizu-pro-6.h +++ b/test/mock/meizu-pro-6.h @@ -2,388 +2,386 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 749, - .content = - "Processor\t: AArch64 Processor rev 4 (aarch64)\n" - "processor\t: 4\n" - "model name\t: AArch64 Processor rev 4 (aarch64)\n" - "BogoMIPS\t: 26.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 5\n" - "model name\t: AArch64 Processor rev 4 (aarch64)\n" - "BogoMIPS\t: 26.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 6\n" - "model name\t: AArch64 Processor rev 4 (aarch64)\n" - "BogoMIPS\t: 26.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "Hardware\t: MT6797T\n", + .content = "Processor\t: AArch64 Processor rev 4 (aarch64)\n" + "processor\t: 4\n" + "model name\t: AArch64 Processor rev 4 (aarch64)\n" + "BogoMIPS\t: 26.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 5\n" + "model name\t: AArch64 Processor rev 4 (aarch64)\n" + "BogoMIPS\t: 26.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 6\n" + "model name\t: AArch64 Processor rev 4 (aarch64)\n" + "BogoMIPS\t: 26.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "Hardware\t: MT6797T\n", }, { .path = "/system/build.prop", .size = 9280, - .content = - "\n" - "import /custom/cip-build.prop\n" - "# begin build properties\n" - "# autogenerated by buildinfo.sh\n" - "ro.build.cta=noncta\n" - "ro.meizu.build.spt=0\n" - "ro.build.id=MRA58K\n" - "ro.build.mask.id=6.0-1498662354_intlstable\n" - "ro.build.inside.id=6.0-20170628230554\n" - "ro.build.version.incremental=1498663073\n" - "ro.build.version.sdk=23\n" - "ro.build.version.preview_sdk=0\n" - "ro.build.version.codename=REL\n" - "ro.build.version.all_codenames=REL\n" - "ro.build.version.release=6.0\n" - "ro.build.version.security_patch=2017-04-05\n" - "ro.build.version.base_os=\n" - "ro.build.date=Wed Jun 28 23:25:45 CST 2017\n" - "ro.build.date.utc=1498663545\n" - "ro.build.type=user\n" - "ro.build.user=flyme\n" - "ro.build.host=mz-builder-l1\n" - "ro.build.tags=release-keys\n" - "ro.build.flavor=full_meizu6797_6c_m-user\n" - "# ro.product.cpu.abi and ro.product.cpu.abi2 are obsolete,\n" - "# use ro.product.cpu.abilist instead.\n" - "ro.product.cpu.abi=arm64-v8a\n" - "ro.product.cpu.abilist=arm64-v8a,armeabi-v7a,armeabi\n" - "ro.product.cpu.abilist32=armeabi-v7a,armeabi\n" - "ro.product.cpu.abilist64=arm64-v8a\n" - "ro.product.locale=en-US\n" - "ro.wifi.channels=\n" - "ro.board.platform=mt6797\n" - "# ro.build.product is obsolete; use ro.product.device\n" - "# Do not try to parse description, fingerprint, or thumbprint\n" - "ro.build.characteristics=default\n" - "ro.product.brand=Meizu\n" - "ro.product.manufacturer=Meizu\n" - "ro.build.display.id=Flyme 6.1.0.0G\n" - "ro.product.model=PRO 6\n" - "ro.meizu.product.model=PRO6\n" - "ro.product.name=meizu_PRO6\n" - "ro.product.device=PRO6\n" - "ro.product.board=PRO6\n" - "# ro.build.product is obsolete; use ro.product.device\n" - "ro.build.product=PRO6\n" - "# Do not try to parse ro.build.description or .fingerprint\n" - "ro.build.description=meizu_PRO6-user 6.0 MRA58K 1498663073 release-keys\n" - "ro.build.fingerprint=Meizu/meizu_PRO6/PRO6:6.0/MRA58K/1498663073:user/release-keys\n" - "ro.meizu.project.id=m8097-5\n" - "ro.product.flyme.model=8097\n" - "ro.flyme.published = true\n" - "ro.meizu.has_datamigration_app=true\n" - "# end build properties\n" - "#\n" - "# from device/meizu/meizu6797_6c_m/system.prop\n" - "#\n" - "#\n" - "# system.prop for generic sdk\n" - "#\n" - "\n" - "rild.libpath=mtk-ril.so\n" - "rild.libargs=-d /dev/ttyC0\n" - "\n" - "\n" - "# MTK, Infinity, 20090720 {\n" - "wifi.interface=wlan0\n" - "# MTK, Infinity, 20090720 }\n" - "\n" - "# MTK, mtk03034, 20101210 {\n" - "ro.mediatek.wlan.wsc=1\n" - "# MTK, mtk03034 20101210}\n" - "# MTK, mtk03034, 20110318 {\n" - "ro.mediatek.wlan.p2p=1\n" - "# MTK, mtk03034 20110318}\n" - "\n" - "# MTK, mtk03034, 20101213 {\n" - "mediatek.wlan.ctia=0\n" - "# MTK, mtk03034 20101213}\n" - "\n" - "\n" - "#\n" - "wifi.tethering.interface=ap0\n" - "#\n" - "\n" - "ro.opengles.version=196608\n" - "#ro.kernel.qemu=1\n" - "\n" - "wifi.direct.interface=p2p0\n" - "dalvik.vm.heapgrowthlimit=256m\n" - "dalvik.vm.heapsize=512m\n" - "\n" - "# USB MTP WHQL\n" - "ro.sys.usb.mtp.whql.enable=0\n" - "\n" - "# Power off opt in IPO\n" - "sys.ipo.pwrdncap=2\n" - "\n" - "ro.sys.usb.storage.type=mtp,mass_storage\n" - "\n" - "# USB BICR function\n" - "ro.sys.usb.bicr=yes\n" - "\n" - "# USB Charge only function\n" - "ro.sys.usb.charging.only=yes\n" - "\n" - "# audio\n" - "ro.camera.sound.forced=0\n" - "ro.audio.silent=0\n" - "\n" - "ro.zygote.preload.enable=0\n" - "\n" - "# temporary enables NAV bar (soft keys)\n" - "qemu.hw.mainkeys=1\n" - "\n" - "ro.kernel.zio=38,108,105,16\n" - "#ro.kernel.qemu=1\n" - "#ro.kernel.qemu.gles=0\n" - "#ro.boot.selinux=disable\n" - "\n" - "# Disable dirty region for Mali\n" - "#debug.hwui.render_dirty_regions=false\n" - "\n" - "ro.sf.lcd_density=480\n" - "\n" - "# performance\n" - "ro.mtk_perf_simple_start_win=1\n" - "ro.mtk_perf_fast_start_win=0\n" - "ro.mtk_perf_response_time=1\n" - "\n" - "# Define PhoneApp ToneVolume\n" - "persist.dialpad.volume=60\n" - "persist.dialpad.ecc.volume=60\n" - "persist.dtmf.volume=70\n" - "persist.call.waiting.volume=85\n" - "persist.ring.back.volume=85\n" - "\n" - "#\n" - "# ADDITIONAL_BUILD_PROPERTIES\n" - "#\n" - "ro.hardware.hifi.support=true\n" - "ro.com.android.dateformat=MM-dd-yyyy\n" - "ro.config.ringtone=03_Flyme.ogg\n" - "ro.config.notification_sound=02_Reminder.ogg\n" - "ro.config.mms_sound=01_Triumph.ogg\n" - "ro.config.email_sound=02_Reminder.ogg\n" - "ro.config.calendar_sound=03_Doorbell.ogg\n" - "ro.config.alarm_alert=19_Waltz.ogg\n" - "log.tag.VibeTonz=ERROR\n" - "ro.carrier=unknown\n" - "ro.mediatek.chip_ver=S01\n" - "ro.mediatek.version.release=alps-mp-m0.mp9-V1.13.2_meizu6797.6c.m\n" - "ro.mediatek.platform=MT6797\n" - "ro.telephony.sim.count=2\n" - "persist.radio.default.sim=0\n" - "persist.radio.multisim.config=dsds\n" - "persist.gemini.sim_num=2\n" - "ro.gemini.smart_sim_switch=false\n" - "ril.specific.sm_cause=0\n" - "bgw.current3gband=0\n" - "ril.external.md=0\n" - "ro.mtk_cam_lomo_support=1\n" - "ro.sf.hwrotation=0\n" - "ro.mediatek.gemini_support=true\n" - "persist.radio.fd.counter=15\n" - "persist.radio.fd.off.counter=5\n" - "persist.radio.fd.r8.counter=15\n" - "persist.radio.fd.off.r8.counter=5\n" - "drm.service.enabled=true\n" - "fmradio.driver.enable=0\n" - "ril.first.md=1\n" - "ril.flightmode.poweroffMD=0\n" - "ril.telephony.mode=0\n" - "dalvik.vm.mtk-stack-trace-file=/data/anr/mtk_traces.txt\n" - "mediatek.wlan.chip=CONSYS_MT6797\n" - "mediatek.wlan.module.postfix=_consys_mt6797\n" - "ril.read.imsi=1\n" - "ril.radiooff.poweroffMD=0\n" - "ro.frp.pst=/dev/block/platform/mtk-msdc.0/11230000.msdc0/by-name/frp\n" - "ro.mediatek.version.branch=alps-mp-m0.mp9\n" - "ro.mediatek.version.sdk=4\n" - "ro.mtk_gemini_support=1\n" - "persist.radio.gemini_support=1\n" - "ril.current.share_modem=2\n" - "ro.mtk_audenh_support=1\n" - "ro.mtk_bessurround_support=1\n" - "ro.mtk_wapi_support=1\n" - "ro.mtk_bt_support=1\n" - "ro.mtk_wappush_support=1\n" - "ro.mtk_agps_app=1\n" - "ro.mtk_audio_tuning_tool_ver=V2.2\n" - "ro.mtk_wlan_support=1\n" - "ro.mtk_gps_support=1\n" - "ro.mtk_omacp_support=1\n" - "ro.mtk_search_db_support=1\n" - "ro.mtk_dialer_search_support=1\n" - "ro.mtk_dhcpv6c_wifi=1\n" - "ro.have_aacencode_feature=1\n" - "ro.mtk_fd_support=1\n" - "ro.mtk_oma_drm_support=1\n" - "ro.mtk_cta_drm_support=1\n" - "ro.mtk_widevine_drm_l3_support=1\n" - "ro.mtk_eap_sim_aka=1\n" - "ro.mtk_audio_ape_support=1\n" - "ro.mtk_flv_playback_support=1\n" - "ro.mtk_wmv_playback_support=1\n" - "ro.mtk_send_rr_support=1\n" - "ro.mtk_emmc_support=1\n" - "ro.mtk_tetheringipv6_support=1\n" - "ro.telephony.default_network=9\n" - "ro.mtk_shared_sdcard=1\n" - "ro.mtk_enable_md1=1\n" - "ro.mtk_afw_support=1\n" - "ro.mtk_soter_support=1\n" - "ro.mtk_benchmark_boost_tp=1\n" - "ro.mtk_aal_support=1\n" - "ro.mtk_pq_support=3\n" - "ro.mtk_pq_color_mode=3\n" - "ro.mtk_miravision_support=1\n" - "ro.mtk_miravision_image_dc=1\n" - "ro.mtk_blulight_def_support=1\n" - "ro.mtk_wfd_support=1\n" - "ro.mtk_wfd_sink_support=1\n" - "ro.mtk_wfd_sink_uibc_support=1\n" - "ro.mtk_wifi_mcc_support=1\n" - "ro.mtk_sim_hot_swap=1\n" - "ro.mtk_thumbnail_play_support=1\n" - "ro.mtk_bip_scws=1\n" - "ro.mtk_cmcc_ft_precheck_support=1\n" - "ro.mtk_world_phone_policy=0\n" - "ro.mtk_md_world_mode_support=1\n" - "ro.mtk_perfservice_support=1\n" - "ro.mtk_sim_hot_swap_common_slot=1\n" - "ro.mtk_cta_set=1\n" - "ro.mtk_mobile_management=1\n" - "ro.mtk_antibricking_level=2\n" - "ro.mtk_zsdhdr_support=1\n" - "ro.mtk_cam_mfb_support=3\n" - "ro.mtk_lte_support=1\n" - "ro.mtk_safemedia_support=1\n" - "ro.mtk_single_imei=1\n" - "ro.mtk_cam_vfb=1\n" - "ro.mtk_rild_read_imsi=1\n" - "ro.sim_refresh_reset_by_modem=1\n" - "ro.mtk_external_sim_support=1\n" - "ro.mtk_persist_vsim_disabled=1\n" - "ro.mtk_external_sim_only_slots=0\n" - "ro.mtk_slidevideo_support=1\n" - "ro.mtk_passpoint_r1_support=1\n" - "ro.mtk_privacy_protection_lock=1\n" - "ro.mtk_bg_power_saving_ui=1\n" - "ro.have_aee_feature=1\n" - "ro.sim_me_lock_mode=0\n" - "ro.mtk_dual_mic_support=1\n" - "ro.mtk_is_tablet=0\n" - "ro.mtk_ims_support=1\n" - "ro.mtk_vilte_support=0\n" - "ro.mtk_vilte_ut_support=0\n" - "wfd.dummy.enable=1\n" - "wfd.iframesize.level=0\n" - "ro.mediatek.project.path=device/meizu/meizu6797_6c_m\n" - "ro.mtk_trustonic_tee_support=1\n" - "ro.flyme_softsim_tee_enable=1\n" - "persist.mtk.wcn.combo.chipid=-1\n" - "persist.mtk.wcn.fwlog.status=no\n" - "persist.mtk.wcn.dynamic.dump=0\n" - "service.wcn.driver.ready=no\n" - "service.wcn.coredump.mode=2\n" - "ro.com.android.mobiledata=false\n" - "persist.radio.mobile.data=0,0\n" - "persist.radio.mobile.enable=1,1\n" - "persist.meta.dumpdata=0\n" - "ro.mtk_hetcomm_support=1\n" - "ro.mtk_deinterlace_support=1\n" - "ro.mtk_md_sbp_custom_value=0\n" - "ro.mtk_modem_monitor_support=1\n" - "persist.mtklog.modem.mini.log=1\n" - "persist.power.usetwilightadj=true\n" - "ro.meizu.enable.stepcounter=true\n" - "persist.perf.url.wxhb=http://wx.gtimg.com/hongbao/1701/hb.png\n" - "debug.hwui.render_dirty_regions=true\n" - "ro.hwui.disable_asset_atlas=true\n" - "dalvik.vm.heapgrowthlimit=256m\n" - "dalvik.vm.heapsize=512m\n" - "ro.hwui.texture_cache_size=48\n" - "ro.hwui.layer_cache_size=32\n" - "ro.hwui.r_buffer_cache_size=8\n" - "ro.hwui.path_cache_size=32\n" - "ro.hwui.gradient_cache_size=3\n" - "ro.hwui.drop_shadow_cache_size=6\n" - "ro.hwui.fbo_cache_size=25\n" - "ro.hwui.texture_cache_flushrate=0.4\n" - "ro.hwui.text_small_cache_width=1024\n" - "ro.hwui.text_small_cache_height=1024\n" - "ro.hwui.text_large_cache_width=2048\n" - "ro.hwui.text_large_cache_height=1024\n" - "ro.product.perf.config=M80_base\n" - "persist.sf.startingwindow.gles=1\n" - "persist.sys.app.compiler=speed\n" - "persist.sys.app.thread=6\n" - "persist.sys.plugin.thread=6\n" - "persist.sys.plugin.compiler=interpret-only\n" - "persist.sys.mstore.dl.num=1\n" - "persist.sf.ssr.controlbar=0\n" - "persist.sys.lock.charge=true\n" - "ro.aeesp=normal\n" - "ro.meizu.carrier.model=M570H\n" - "persist.sys.timezone=Asia/Shanghai\n" - "persist.sys.meizu.region=cn\n" - "persist.sys.meizu.codepage=gbk\n" - "ro.meizu.setupwizard.flyme=true\n" - "ro.meizu.setupwizard.setlang=true\n" - "ro.meizu.region.enable=true\n" - "ro.meizu.contactmsg.auth=false\n" - "ro.meizu.customize.pccw=false\n" - "ro.meizu.autorecorder=true\n" - "ro.meizu.visualvoicemail=true\n" - "ro.meizu.security=false\n" - "ro.meizu.permanentkey=false\n" - "ro.meizu.sip.support=true\n" - "ro.meizu.voip.support=false\n" - "sys.meizu.m35x.white.config=false\n" - "sys.meizu.white.config=false\n" - "persist.sys.log-main.enable=0\n" - "persist.sys.log-system.enable=0\n" - "persist.sys.log-events.enable=0\n" - "persist.sys.log-radio.enable=0\n" - "persist.sys.use.flyme.icon=true\n" - "ro.adb.secure=1\n" - "persist.sys.ui.hw=true\n" - "keyguard.no_require_sim=true\n" - "persist.sys.keyguard_intercept=true\n" - "persist.sys.disable_blur_view=true\n" - "persist.sys.static_blur_mode=false\n" - "ro.meizu.published.type=prd\n" - "qemu.hw.mainkeys=1\n" - "persist.sys.dalvik.vm.lib.2=libart\n" - "dalvik.vm.isa.arm64.variant=cortex-a53\n" - "dalvik.vm.isa.arm64.features=default\n" - "dalvik.vm.isa.arm.variant=cortex-a53\n" - "dalvik.vm.isa.arm.features=default\n" - "net.bt.name=Android\n" - "dalvik.vm.stack-trace-file=/data/anr/traces.txt\n" - "ro.expect.recovery_id=0xc68184e76824cdec195acf3ae9c1a0b84b7f11d6000000000000000000000000\n", + .content = "\n" + "import /custom/cip-build.prop\n" + "# begin build properties\n" + "# autogenerated by buildinfo.sh\n" + "ro.build.cta=noncta\n" + "ro.meizu.build.spt=0\n" + "ro.build.id=MRA58K\n" + "ro.build.mask.id=6.0-1498662354_intlstable\n" + "ro.build.inside.id=6.0-20170628230554\n" + "ro.build.version.incremental=1498663073\n" + "ro.build.version.sdk=23\n" + "ro.build.version.preview_sdk=0\n" + "ro.build.version.codename=REL\n" + "ro.build.version.all_codenames=REL\n" + "ro.build.version.release=6.0\n" + "ro.build.version.security_patch=2017-04-05\n" + "ro.build.version.base_os=\n" + "ro.build.date=Wed Jun 28 23:25:45 CST 2017\n" + "ro.build.date.utc=1498663545\n" + "ro.build.type=user\n" + "ro.build.user=flyme\n" + "ro.build.host=mz-builder-l1\n" + "ro.build.tags=release-keys\n" + "ro.build.flavor=full_meizu6797_6c_m-user\n" + "# ro.product.cpu.abi and ro.product.cpu.abi2 are obsolete,\n" + "# use ro.product.cpu.abilist instead.\n" + "ro.product.cpu.abi=arm64-v8a\n" + "ro.product.cpu.abilist=arm64-v8a,armeabi-v7a,armeabi\n" + "ro.product.cpu.abilist32=armeabi-v7a,armeabi\n" + "ro.product.cpu.abilist64=arm64-v8a\n" + "ro.product.locale=en-US\n" + "ro.wifi.channels=\n" + "ro.board.platform=mt6797\n" + "# ro.build.product is obsolete; use ro.product.device\n" + "# Do not try to parse description, fingerprint, or thumbprint\n" + "ro.build.characteristics=default\n" + "ro.product.brand=Meizu\n" + "ro.product.manufacturer=Meizu\n" + "ro.build.display.id=Flyme 6.1.0.0G\n" + "ro.product.model=PRO 6\n" + "ro.meizu.product.model=PRO6\n" + "ro.product.name=meizu_PRO6\n" + "ro.product.device=PRO6\n" + "ro.product.board=PRO6\n" + "# ro.build.product is obsolete; use ro.product.device\n" + "ro.build.product=PRO6\n" + "# Do not try to parse ro.build.description or .fingerprint\n" + "ro.build.description=meizu_PRO6-user 6.0 MRA58K 1498663073 release-keys\n" + "ro.build.fingerprint=Meizu/meizu_PRO6/PRO6:6.0/MRA58K/1498663073:user/release-keys\n" + "ro.meizu.project.id=m8097-5\n" + "ro.product.flyme.model=8097\n" + "ro.flyme.published = true\n" + "ro.meizu.has_datamigration_app=true\n" + "# end build properties\n" + "#\n" + "# from device/meizu/meizu6797_6c_m/system.prop\n" + "#\n" + "#\n" + "# system.prop for generic sdk\n" + "#\n" + "\n" + "rild.libpath=mtk-ril.so\n" + "rild.libargs=-d /dev/ttyC0\n" + "\n" + "\n" + "# MTK, Infinity, 20090720 {\n" + "wifi.interface=wlan0\n" + "# MTK, Infinity, 20090720 }\n" + "\n" + "# MTK, mtk03034, 20101210 {\n" + "ro.mediatek.wlan.wsc=1\n" + "# MTK, mtk03034 20101210}\n" + "# MTK, mtk03034, 20110318 {\n" + "ro.mediatek.wlan.p2p=1\n" + "# MTK, mtk03034 20110318}\n" + "\n" + "# MTK, mtk03034, 20101213 {\n" + "mediatek.wlan.ctia=0\n" + "# MTK, mtk03034 20101213}\n" + "\n" + "\n" + "#\n" + "wifi.tethering.interface=ap0\n" + "#\n" + "\n" + "ro.opengles.version=196608\n" + "#ro.kernel.qemu=1\n" + "\n" + "wifi.direct.interface=p2p0\n" + "dalvik.vm.heapgrowthlimit=256m\n" + "dalvik.vm.heapsize=512m\n" + "\n" + "# USB MTP WHQL\n" + "ro.sys.usb.mtp.whql.enable=0\n" + "\n" + "# Power off opt in IPO\n" + "sys.ipo.pwrdncap=2\n" + "\n" + "ro.sys.usb.storage.type=mtp,mass_storage\n" + "\n" + "# USB BICR function\n" + "ro.sys.usb.bicr=yes\n" + "\n" + "# USB Charge only function\n" + "ro.sys.usb.charging.only=yes\n" + "\n" + "# audio\n" + "ro.camera.sound.forced=0\n" + "ro.audio.silent=0\n" + "\n" + "ro.zygote.preload.enable=0\n" + "\n" + "# temporary enables NAV bar (soft keys)\n" + "qemu.hw.mainkeys=1\n" + "\n" + "ro.kernel.zio=38,108,105,16\n" + "#ro.kernel.qemu=1\n" + "#ro.kernel.qemu.gles=0\n" + "#ro.boot.selinux=disable\n" + "\n" + "# Disable dirty region for Mali\n" + "#debug.hwui.render_dirty_regions=false\n" + "\n" + "ro.sf.lcd_density=480\n" + "\n" + "# performance\n" + "ro.mtk_perf_simple_start_win=1\n" + "ro.mtk_perf_fast_start_win=0\n" + "ro.mtk_perf_response_time=1\n" + "\n" + "# Define PhoneApp ToneVolume\n" + "persist.dialpad.volume=60\n" + "persist.dialpad.ecc.volume=60\n" + "persist.dtmf.volume=70\n" + "persist.call.waiting.volume=85\n" + "persist.ring.back.volume=85\n" + "\n" + "#\n" + "# ADDITIONAL_BUILD_PROPERTIES\n" + "#\n" + "ro.hardware.hifi.support=true\n" + "ro.com.android.dateformat=MM-dd-yyyy\n" + "ro.config.ringtone=03_Flyme.ogg\n" + "ro.config.notification_sound=02_Reminder.ogg\n" + "ro.config.mms_sound=01_Triumph.ogg\n" + "ro.config.email_sound=02_Reminder.ogg\n" + "ro.config.calendar_sound=03_Doorbell.ogg\n" + "ro.config.alarm_alert=19_Waltz.ogg\n" + "log.tag.VibeTonz=ERROR\n" + "ro.carrier=unknown\n" + "ro.mediatek.chip_ver=S01\n" + "ro.mediatek.version.release=alps-mp-m0.mp9-V1.13.2_meizu6797.6c.m\n" + "ro.mediatek.platform=MT6797\n" + "ro.telephony.sim.count=2\n" + "persist.radio.default.sim=0\n" + "persist.radio.multisim.config=dsds\n" + "persist.gemini.sim_num=2\n" + "ro.gemini.smart_sim_switch=false\n" + "ril.specific.sm_cause=0\n" + "bgw.current3gband=0\n" + "ril.external.md=0\n" + "ro.mtk_cam_lomo_support=1\n" + "ro.sf.hwrotation=0\n" + "ro.mediatek.gemini_support=true\n" + "persist.radio.fd.counter=15\n" + "persist.radio.fd.off.counter=5\n" + "persist.radio.fd.r8.counter=15\n" + "persist.radio.fd.off.r8.counter=5\n" + "drm.service.enabled=true\n" + "fmradio.driver.enable=0\n" + "ril.first.md=1\n" + "ril.flightmode.poweroffMD=0\n" + "ril.telephony.mode=0\n" + "dalvik.vm.mtk-stack-trace-file=/data/anr/mtk_traces.txt\n" + "mediatek.wlan.chip=CONSYS_MT6797\n" + "mediatek.wlan.module.postfix=_consys_mt6797\n" + "ril.read.imsi=1\n" + "ril.radiooff.poweroffMD=0\n" + "ro.frp.pst=/dev/block/platform/mtk-msdc.0/11230000.msdc0/by-name/frp\n" + "ro.mediatek.version.branch=alps-mp-m0.mp9\n" + "ro.mediatek.version.sdk=4\n" + "ro.mtk_gemini_support=1\n" + "persist.radio.gemini_support=1\n" + "ril.current.share_modem=2\n" + "ro.mtk_audenh_support=1\n" + "ro.mtk_bessurround_support=1\n" + "ro.mtk_wapi_support=1\n" + "ro.mtk_bt_support=1\n" + "ro.mtk_wappush_support=1\n" + "ro.mtk_agps_app=1\n" + "ro.mtk_audio_tuning_tool_ver=V2.2\n" + "ro.mtk_wlan_support=1\n" + "ro.mtk_gps_support=1\n" + "ro.mtk_omacp_support=1\n" + "ro.mtk_search_db_support=1\n" + "ro.mtk_dialer_search_support=1\n" + "ro.mtk_dhcpv6c_wifi=1\n" + "ro.have_aacencode_feature=1\n" + "ro.mtk_fd_support=1\n" + "ro.mtk_oma_drm_support=1\n" + "ro.mtk_cta_drm_support=1\n" + "ro.mtk_widevine_drm_l3_support=1\n" + "ro.mtk_eap_sim_aka=1\n" + "ro.mtk_audio_ape_support=1\n" + "ro.mtk_flv_playback_support=1\n" + "ro.mtk_wmv_playback_support=1\n" + "ro.mtk_send_rr_support=1\n" + "ro.mtk_emmc_support=1\n" + "ro.mtk_tetheringipv6_support=1\n" + "ro.telephony.default_network=9\n" + "ro.mtk_shared_sdcard=1\n" + "ro.mtk_enable_md1=1\n" + "ro.mtk_afw_support=1\n" + "ro.mtk_soter_support=1\n" + "ro.mtk_benchmark_boost_tp=1\n" + "ro.mtk_aal_support=1\n" + "ro.mtk_pq_support=3\n" + "ro.mtk_pq_color_mode=3\n" + "ro.mtk_miravision_support=1\n" + "ro.mtk_miravision_image_dc=1\n" + "ro.mtk_blulight_def_support=1\n" + "ro.mtk_wfd_support=1\n" + "ro.mtk_wfd_sink_support=1\n" + "ro.mtk_wfd_sink_uibc_support=1\n" + "ro.mtk_wifi_mcc_support=1\n" + "ro.mtk_sim_hot_swap=1\n" + "ro.mtk_thumbnail_play_support=1\n" + "ro.mtk_bip_scws=1\n" + "ro.mtk_cmcc_ft_precheck_support=1\n" + "ro.mtk_world_phone_policy=0\n" + "ro.mtk_md_world_mode_support=1\n" + "ro.mtk_perfservice_support=1\n" + "ro.mtk_sim_hot_swap_common_slot=1\n" + "ro.mtk_cta_set=1\n" + "ro.mtk_mobile_management=1\n" + "ro.mtk_antibricking_level=2\n" + "ro.mtk_zsdhdr_support=1\n" + "ro.mtk_cam_mfb_support=3\n" + "ro.mtk_lte_support=1\n" + "ro.mtk_safemedia_support=1\n" + "ro.mtk_single_imei=1\n" + "ro.mtk_cam_vfb=1\n" + "ro.mtk_rild_read_imsi=1\n" + "ro.sim_refresh_reset_by_modem=1\n" + "ro.mtk_external_sim_support=1\n" + "ro.mtk_persist_vsim_disabled=1\n" + "ro.mtk_external_sim_only_slots=0\n" + "ro.mtk_slidevideo_support=1\n" + "ro.mtk_passpoint_r1_support=1\n" + "ro.mtk_privacy_protection_lock=1\n" + "ro.mtk_bg_power_saving_ui=1\n" + "ro.have_aee_feature=1\n" + "ro.sim_me_lock_mode=0\n" + "ro.mtk_dual_mic_support=1\n" + "ro.mtk_is_tablet=0\n" + "ro.mtk_ims_support=1\n" + "ro.mtk_vilte_support=0\n" + "ro.mtk_vilte_ut_support=0\n" + "wfd.dummy.enable=1\n" + "wfd.iframesize.level=0\n" + "ro.mediatek.project.path=device/meizu/meizu6797_6c_m\n" + "ro.mtk_trustonic_tee_support=1\n" + "ro.flyme_softsim_tee_enable=1\n" + "persist.mtk.wcn.combo.chipid=-1\n" + "persist.mtk.wcn.fwlog.status=no\n" + "persist.mtk.wcn.dynamic.dump=0\n" + "service.wcn.driver.ready=no\n" + "service.wcn.coredump.mode=2\n" + "ro.com.android.mobiledata=false\n" + "persist.radio.mobile.data=0,0\n" + "persist.radio.mobile.enable=1,1\n" + "persist.meta.dumpdata=0\n" + "ro.mtk_hetcomm_support=1\n" + "ro.mtk_deinterlace_support=1\n" + "ro.mtk_md_sbp_custom_value=0\n" + "ro.mtk_modem_monitor_support=1\n" + "persist.mtklog.modem.mini.log=1\n" + "persist.power.usetwilightadj=true\n" + "ro.meizu.enable.stepcounter=true\n" + "persist.perf.url.wxhb=http://wx.gtimg.com/hongbao/1701/hb.png\n" + "debug.hwui.render_dirty_regions=true\n" + "ro.hwui.disable_asset_atlas=true\n" + "dalvik.vm.heapgrowthlimit=256m\n" + "dalvik.vm.heapsize=512m\n" + "ro.hwui.texture_cache_size=48\n" + "ro.hwui.layer_cache_size=32\n" + "ro.hwui.r_buffer_cache_size=8\n" + "ro.hwui.path_cache_size=32\n" + "ro.hwui.gradient_cache_size=3\n" + "ro.hwui.drop_shadow_cache_size=6\n" + "ro.hwui.fbo_cache_size=25\n" + "ro.hwui.texture_cache_flushrate=0.4\n" + "ro.hwui.text_small_cache_width=1024\n" + "ro.hwui.text_small_cache_height=1024\n" + "ro.hwui.text_large_cache_width=2048\n" + "ro.hwui.text_large_cache_height=1024\n" + "ro.product.perf.config=M80_base\n" + "persist.sf.startingwindow.gles=1\n" + "persist.sys.app.compiler=speed\n" + "persist.sys.app.thread=6\n" + "persist.sys.plugin.thread=6\n" + "persist.sys.plugin.compiler=interpret-only\n" + "persist.sys.mstore.dl.num=1\n" + "persist.sf.ssr.controlbar=0\n" + "persist.sys.lock.charge=true\n" + "ro.aeesp=normal\n" + "ro.meizu.carrier.model=M570H\n" + "persist.sys.timezone=Asia/Shanghai\n" + "persist.sys.meizu.region=cn\n" + "persist.sys.meizu.codepage=gbk\n" + "ro.meizu.setupwizard.flyme=true\n" + "ro.meizu.setupwizard.setlang=true\n" + "ro.meizu.region.enable=true\n" + "ro.meizu.contactmsg.auth=false\n" + "ro.meizu.customize.pccw=false\n" + "ro.meizu.autorecorder=true\n" + "ro.meizu.visualvoicemail=true\n" + "ro.meizu.security=false\n" + "ro.meizu.permanentkey=false\n" + "ro.meizu.sip.support=true\n" + "ro.meizu.voip.support=false\n" + "sys.meizu.m35x.white.config=false\n" + "sys.meizu.white.config=false\n" + "persist.sys.log-main.enable=0\n" + "persist.sys.log-system.enable=0\n" + "persist.sys.log-events.enable=0\n" + "persist.sys.log-radio.enable=0\n" + "persist.sys.use.flyme.icon=true\n" + "ro.adb.secure=1\n" + "persist.sys.ui.hw=true\n" + "keyguard.no_require_sim=true\n" + "persist.sys.keyguard_intercept=true\n" + "persist.sys.disable_blur_view=true\n" + "persist.sys.static_blur_mode=false\n" + "ro.meizu.published.type=prd\n" + "qemu.hw.mainkeys=1\n" + "persist.sys.dalvik.vm.lib.2=libart\n" + "dalvik.vm.isa.arm64.variant=cortex-a53\n" + "dalvik.vm.isa.arm64.features=default\n" + "dalvik.vm.isa.arm.variant=cortex-a53\n" + "dalvik.vm.isa.arm.features=default\n" + "net.bt.name=Android\n" + "dalvik.vm.stack-trace-file=/data/anr/traces.txt\n" + "ro.expect.recovery_id=0xc68184e76824cdec195acf3ae9c1a0b84b7f11d6000000000000000000000000\n", }, { .path = "/sys/devices/system/cpu/kernel_max", @@ -418,52 +416,51 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpufreq/all_time_in_state", .size = 890, - .content = - "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\tcpu8\t\tcpu9\t\t\n" - "221000\t\tN/A\t\tN/A\t\t\n" - "325000\t\t15\t\tN/A\t\t\n" - "338000\t\tN/A\t\t19\t\t\n" - "468000\t\t0\t\tN/A\t\t\n" - "481000\t\tN/A\t\tN/A\t\t\n" - "624000\t\tN/A\t\tN/A\t\t\n" - "650000\t\t0\t\tN/A\t\t\n" - "676000\t\tN/A\t\t0\t\t\n" - "715000\t\tN/A\t\tN/A\t\t\n" - "806000\t\tN/A\t\tN/A\t\t\n" - "832000\t\t7\t\tN/A\t\t\n" - "845000\t\tN/A\t\t15\t\t\n" - "897000\t\tN/A\t\tN/A\t\t\n" - "962000\t\t35\t\tN/A\t\t\n" - "1001000\t\tN/A\t\t11\t\t\n" - "1014000\t\tN/A\t\tN/A\t\t\n" - "1079000\t\t8\t\tN/A\t\t\n" - "1118000\t\tN/A\t\tN/A\t\t\n" - "1131000\t\tN/A\t\t0\t\t\n" - "1209000\t\t122\t\tN/A\t\t\n" - "1222000\t\tN/A\t\tN/A\t\t\n" - "1274000\t\tN/A\t\tN/A\t\t\n" - "1339000\t\tN/A\t\tN/A\t\t\n" - "1352000\t\t189\t\tN/A\t\t\n" - "1378000\t\tN/A\t\t0\t\t\n" - "1391000\t\tN/A\t\tN/A\t\t\n" - "1443000\t\tN/A\t\tN/A\t\t\n" - "1495000\t\t4\t\t0\t\t\n" - "1547000\t\tN/A\t\tN/A\t\t\n" - "1625000\t\t14\t\tN/A\t\t\n" - "1677000\t\tN/A\t\t0\t\t\n" - "1703000\t\t6\t\tN/A\t\t\n" - "1755000\t\t17\t\tN/A\t\t\n" - "1820000\t\t10\t\tN/A\t\t\n" - "1885000\t\t69\t\t4\t\t\n" - "1950000\t\t38\t\tN/A\t\t\n" - "2002000\t\t3223\t\tN/A\t\t\n" - "2093000\t\tN/A\t\t4\t\t\n" - "2158000\t\tN/A\t\t0\t\t\n" - "2223000\t\tN/A\t\t0\t\t\n" - "2262000\t\tN/A\t\t1\t\t\n" - "2327000\t\tN/A\t\t952\t\t\n" - "2392000\t\tN/A\t\t0\t\t\n" - "2522000\t\tN/A\t\t191\t\t\n", + .content = "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\tcpu8\t\tcpu9\t\t\n" + "221000\t\tN/A\t\tN/A\t\t\n" + "325000\t\t15\t\tN/A\t\t\n" + "338000\t\tN/A\t\t19\t\t\n" + "468000\t\t0\t\tN/A\t\t\n" + "481000\t\tN/A\t\tN/A\t\t\n" + "624000\t\tN/A\t\tN/A\t\t\n" + "650000\t\t0\t\tN/A\t\t\n" + "676000\t\tN/A\t\t0\t\t\n" + "715000\t\tN/A\t\tN/A\t\t\n" + "806000\t\tN/A\t\tN/A\t\t\n" + "832000\t\t7\t\tN/A\t\t\n" + "845000\t\tN/A\t\t15\t\t\n" + "897000\t\tN/A\t\tN/A\t\t\n" + "962000\t\t35\t\tN/A\t\t\n" + "1001000\t\tN/A\t\t11\t\t\n" + "1014000\t\tN/A\t\tN/A\t\t\n" + "1079000\t\t8\t\tN/A\t\t\n" + "1118000\t\tN/A\t\tN/A\t\t\n" + "1131000\t\tN/A\t\t0\t\t\n" + "1209000\t\t122\t\tN/A\t\t\n" + "1222000\t\tN/A\t\tN/A\t\t\n" + "1274000\t\tN/A\t\tN/A\t\t\n" + "1339000\t\tN/A\t\tN/A\t\t\n" + "1352000\t\t189\t\tN/A\t\t\n" + "1378000\t\tN/A\t\t0\t\t\n" + "1391000\t\tN/A\t\tN/A\t\t\n" + "1443000\t\tN/A\t\tN/A\t\t\n" + "1495000\t\t4\t\t0\t\t\n" + "1547000\t\tN/A\t\tN/A\t\t\n" + "1625000\t\t14\t\tN/A\t\t\n" + "1677000\t\tN/A\t\t0\t\t\n" + "1703000\t\t6\t\tN/A\t\t\n" + "1755000\t\t17\t\tN/A\t\t\n" + "1820000\t\t10\t\tN/A\t\t\n" + "1885000\t\t69\t\t4\t\t\n" + "1950000\t\t38\t\tN/A\t\t\n" + "2002000\t\t3223\t\tN/A\t\t\n" + "2093000\t\tN/A\t\t4\t\t\n" + "2158000\t\tN/A\t\t0\t\t\n" + "2223000\t\tN/A\t\t0\t\t\n" + "2262000\t\tN/A\t\t1\t\t\n" + "2327000\t\tN/A\t\t952\t\t\n" + "2392000\t\tN/A\t\t0\t\t\n" + "2522000\t\tN/A\t\t191\t\t\n", }, { .path = "/sys/devices/system/cpu/cpufreq/current_in_state", @@ -493,21 +490,19 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cputopo/cpus_per_cluster", .size = 39, - .content = - "cluster0: f\n" - "cluster1: f0\n" - "cluster2: 300\n", + .content = "cluster0: f\n" + "cluster1: f0\n" + "cluster2: 300\n", }, { .path = "/sys/devices/system/cpu/cputopo/glbinfo", .size = 87, - .content = - "big/little arch: yes\n" - "nr_cups: 10\n" - "nr_clusters: 3\n" - "cluster0: f\n" - "cluster1: f0\n" - "cluster2: 300\n", + .content = "big/little arch: yes\n" + "nr_cups: 10\n" + "nr_clusters: 3\n" + "cluster0: f\n" + "cluster1: f0\n" + "cluster2: 300\n", }, { .path = "/sys/devices/system/cpu/cputopo/is_big_little", @@ -552,7 +547,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies", .size = 124, - .content = "2002000 1950000 1885000 1820000 1755000 1703000 1625000 1495000 1352000 1209000 1079000 962000 832000 650000 468000 325000 \n", + .content = + "2002000 1950000 1885000 1820000 1755000 1703000 1625000 1495000 1352000 1209000 1079000 962000 832000 650000 468000 325000 \n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors", @@ -582,23 +578,22 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 169, - .content = - "2002000 3298\n" - "1950000 38\n" - "1885000 69\n" - "1820000 10\n" - "1755000 17\n" - "1703000 6\n" - "1625000 14\n" - "1495000 4\n" - "1352000 189\n" - "1209000 122\n" - "1079000 8\n" - "962000 35\n" - "832000 7\n" - "650000 0\n" - "468000 0\n" - "325000 15\n", + .content = "2002000 3298\n" + "1950000 38\n" + "1885000 69\n" + "1820000 10\n" + "1755000 17\n" + "1703000 6\n" + "1625000 14\n" + "1495000 4\n" + "1352000 189\n" + "1209000 122\n" + "1079000 8\n" + "962000 35\n" + "832000 7\n" + "650000 0\n" + "468000 0\n" + "325000 15\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -656,7 +651,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_available_frequencies", .size = 124, - .content = "2002000 1950000 1885000 1820000 1755000 1703000 1625000 1495000 1352000 1209000 1079000 962000 832000 650000 468000 325000 \n", + .content = + "2002000 1950000 1885000 1820000 1755000 1703000 1625000 1495000 1352000 1209000 1079000 962000 832000 650000 468000 325000 \n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_available_governors", @@ -686,23 +682,22 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/time_in_state", .size = 170, - .content = - "2002000 4578\n" - "1950000 38\n" - "1885000 69\n" - "1820000 10\n" - "1755000 17\n" - "1703000 14\n" - "1625000 14\n" - "1495000 9\n" - "1352000 189\n" - "1209000 122\n" - "1079000 8\n" - "962000 35\n" - "832000 7\n" - "650000 0\n" - "468000 0\n" - "325000 15\n", + .content = "2002000 4578\n" + "1950000 38\n" + "1885000 69\n" + "1820000 10\n" + "1755000 17\n" + "1703000 14\n" + "1625000 14\n" + "1495000 9\n" + "1352000 189\n" + "1209000 122\n" + "1079000 8\n" + "962000 35\n" + "832000 7\n" + "650000 0\n" + "468000 0\n" + "325000 15\n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/total_trans", @@ -775,7 +770,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_available_frequencies", .size = 124, - .content = "2002000 1950000 1885000 1820000 1755000 1703000 1625000 1495000 1352000 1209000 1079000 962000 832000 650000 468000 325000 \n", + .content = + "2002000 1950000 1885000 1820000 1755000 1703000 1625000 1495000 1352000 1209000 1079000 962000 832000 650000 468000 325000 \n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_available_governors", @@ -785,23 +781,22 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/time_in_state", .size = 170, - .content = - "2002000 5587\n" - "1950000 38\n" - "1885000 69\n" - "1820000 10\n" - "1755000 17\n" - "1703000 14\n" - "1625000 14\n" - "1495000 9\n" - "1352000 189\n" - "1209000 122\n" - "1079000 8\n" - "962000 35\n" - "832000 7\n" - "650000 0\n" - "468000 0\n" - "325000 15\n", + .content = "2002000 5587\n" + "1950000 38\n" + "1885000 69\n" + "1820000 10\n" + "1755000 17\n" + "1703000 14\n" + "1625000 14\n" + "1495000 9\n" + "1352000 189\n" + "1209000 122\n" + "1079000 8\n" + "962000 35\n" + "832000 7\n" + "650000 0\n" + "468000 0\n" + "325000 15\n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/total_trans", @@ -841,23 +836,22 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu8/cpufreq/stats/time_in_state", .size = 166, - .content = - "2522000 191\n" - "2392000 0\n" - "2327000 3012\n" - "2262000 3\n" - "2223000 0\n" - "2158000 0\n" - "2093000 10\n" - "1885000 6\n" - "1677000 2\n" - "1495000 0\n" - "1378000 0\n" - "1131000 2\n" - "1001000 11\n" - "845000 22\n" - "676000 0\n" - "338000 19\n", + .content = "2522000 191\n" + "2392000 0\n" + "2327000 3012\n" + "2262000 3\n" + "2223000 0\n" + "2158000 0\n" + "2093000 10\n" + "1885000 6\n" + "1677000 2\n" + "1495000 0\n" + "1378000 0\n" + "1131000 2\n" + "1001000 11\n" + "845000 22\n" + "676000 0\n" + "338000 19\n", }, { .path = "/sys/devices/system/cpu/cpu8/cpufreq/stats/total_trans", @@ -879,7 +873,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "0\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ @@ -3216,6 +3210,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.wfd.security.image", .value = "1", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/meizu-pro-6s.cc b/test/mock/meizu-pro-6s.cc index 7593caae..ef9e7c3c 100644 --- a/test/mock/meizu-pro-6s.cc +++ b/test/mock/meizu-pro-6s.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(10, cpuinfo_get_processors_count()); @@ -389,8 +388,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("MediaTek MT6797T", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "MediaTek MT6797T", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -432,59 +433,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -639,8 +640,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -721,8 +724,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -781,8 +786,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/meizu-pro-6s.h b/test/mock/meizu-pro-6s.h index 00025c04..f6a629d9 100644 --- a/test/mock/meizu-pro-6s.h +++ b/test/mock/meizu-pro-6s.h @@ -1,1307 +1,1307 @@ -struct cpuinfo_mock_file filesystem[] = { - { - .path = "/proc/cpuinfo", - .size = 1661, - .content = - "Processor\t: AArch64 Processor rev 4 (aarch64)\n" - "processor\t: 0\n" - "model name\t: AArch64 Processor rev 4 (aarch64)\n" - "BogoMIPS\t: 26.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 1\n" - "model name\t: AArch64 Processor rev 4 (aarch64)\n" - "BogoMIPS\t: 26.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 2\n" - "model name\t: AArch64 Processor rev 4 (aarch64)\n" - "BogoMIPS\t: 26.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 4\n" - "model name\t: AArch64 Processor rev 4 (aarch64)\n" - "BogoMIPS\t: 26.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 5\n" - "model name\t: AArch64 Processor rev 4 (aarch64)\n" - "BogoMIPS\t: 26.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 6\n" - "model name\t: AArch64 Processor rev 4 (aarch64)\n" - "BogoMIPS\t: 26.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 7\n" - "model name\t: AArch64 Processor rev 4 (aarch64)\n" - "BogoMIPS\t: 26.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "Hardware\t: MT6797T\n", - }, - { - .path = "/system/build.prop", - .size = 9920, - .content = - "\n" - "import /custom/cip-build.prop\n" - "# begin build properties\n" - "# autogenerated by buildinfo.sh\n" - "ro.build.cta=noncta\n" - "ro.meizu.build.spt=0\n" - "ro.build.id=MRA58K\n" - "ro.build.mask.id=6.0-1484499354_stable\n" - "ro.build.inside.id=6.0-20170116005554\n" - "ro.build.version.incremental=1484499894\n" - "ro.build.version.sdk=23\n" - "ro.build.version.preview_sdk=0\n" - "ro.build.version.codename=REL\n" - "ro.build.version.all_codenames=REL\n" - "ro.build.version.release=6.0\n" - "ro.build.version.security_patch=2016-11-05\n" - "ro.build.version.base_os=\n" - "ro.build.date=Mon Jan 16 01:09:06 CST 2017\n" - "ro.build.date.utc=1484500146\n" - "ro.build.type=user\n" - "ro.build.user=flyme\n" - "ro.build.host=Mz-Builder-l10\n" - "ro.build.tags=release-keys\n" - "ro.build.flavor=full_meizu6797_6c_m-user\n" - "# ro.product.cpu.abi and ro.product.cpu.abi2 are obsolete,\n" - "# use ro.product.cpu.abilist instead.\n" - "ro.product.cpu.abi=arm64-v8a\n" - "ro.product.cpu.abilist=arm64-v8a,armeabi-v7a,armeabi\n" - "ro.product.cpu.abilist32=armeabi-v7a,armeabi\n" - "ro.product.cpu.abilist64=arm64-v8a\n" - "ro.product.locale=en-US\n" - "ro.wifi.channels=\n" - "ro.board.platform=mt6797\n" - "# ro.build.product is obsolete; use ro.product.device\n" - "# Do not try to parse description, fingerprint, or thumbprint\n" - "ro.build.characteristics=default\n" - "ro.product.brand=Meizu\n" - "ro.product.manufacturer=Meizu\n" - "ro.build.display.id=Flyme 6.0.1.0A\n" - "ro.product.model=PRO 6\n" - "ro.meizu.product.model=PRO6\n" - "ro.product.name=meizu_PRO6\n" - "ro.product.device=PRO6\n" - "ro.product.board=PRO6\n" - "# ro.build.product is obsolete; use ro.product.device\n" - "ro.build.product=PRO6\n" - "# Do not try to parse ro.build.description or .fingerprint\n" - "ro.build.description=meizu_PRO6-user 6.0 MRA58K 1484499894 release-keys\n" - "ro.build.fingerprint=Meizu/meizu_PRO6/PRO6:6.0/MRA58K/1484499894:user/release-keys\n" - "ro.meizu.project.id=m8097-5\n" - "ro.product.flyme.model=8097\n" - "ro.flyme.published = true\n" - "ro.meizu.has_datamigration_app=true\n" - "# end build properties\n" - "#\n" - "# from device/meizu/meizu6797_6c_m/system.prop\n" - "#\n" - "#\n" - "# system.prop for generic sdk\n" - "#\n" - "\n" - "rild.libpath=mtk-ril.so\n" - "rild.libargs=-d /dev/ttyC0\n" - "\n" - "\n" - "# MTK, Infinity, 20090720 {\n" - "wifi.interface=wlan0\n" - "# MTK, Infinity, 20090720 }\n" - "\n" - "# MTK, mtk03034, 20101210 {\n" - "ro.mediatek.wlan.wsc=1\n" - "# MTK, mtk03034 20101210}\n" - "# MTK, mtk03034, 20110318 {\n" - "ro.mediatek.wlan.p2p=1\n" - "# MTK, mtk03034 20110318}\n" - "\n" - "# MTK, mtk03034, 20101213 {\n" - "mediatek.wlan.ctia=0\n" - "# MTK, mtk03034 20101213}\n" - "\n" - "\n" - "#\n" - "wifi.tethering.interface=ap0\n" - "#\n" - "\n" - "ro.opengles.version=196608\n" - "#ro.kernel.qemu=1\n" - "\n" - "wifi.direct.interface=p2p0\n" - "dalvik.vm.heapgrowthlimit=256m\n" - "dalvik.vm.heapsize=512m\n" - "\n" - "# USB MTP WHQL\n" - "ro.sys.usb.mtp.whql.enable=0\n" - "\n" - "# Power off opt in IPO\n" - "sys.ipo.pwrdncap=2\n" - "\n" - "ro.sys.usb.storage.type=mtp,mass_storage\n" - "\n" - "# USB BICR function\n" - "ro.sys.usb.bicr=yes\n" - "\n" - "# USB Charge only function\n" - "ro.sys.usb.charging.only=yes\n" - "\n" - "# audio\n" - "ro.camera.sound.forced=0\n" - "ro.audio.silent=0\n" - "\n" - "ro.zygote.preload.enable=0\n" - "\n" - "# temporary enables NAV bar (soft keys)\n" - "qemu.hw.mainkeys=1\n" - "\n" - "ro.kernel.zio=38,108,105,16\n" - "#ro.kernel.qemu=1\n" - "#ro.kernel.qemu.gles=0\n" - "#ro.boot.selinux=disable\n" - "\n" - "# Disable dirty region for Mali\n" - "#debug.hwui.render_dirty_regions=false\n" - "\n" - "ro.sf.lcd_density=480\n" - "\n" - "# performance\n" - "ro.mtk_perf_simple_start_win=1\n" - "ro.mtk_perf_fast_start_win=0\n" - "ro.mtk_perf_response_time=1\n" - "\n" - "# Define PhoneApp ToneVolume\n" - "persist.dialpad.volume=60\n" - "persist.dialpad.ecc.volume=60\n" - "persist.dtmf.volume=70\n" - "persist.call.waiting.volume=85\n" - "persist.ring.back.volume=85\n" - "\n" - "#\n" - "# ADDITIONAL_BUILD_PROPERTIES\n" - "#\n" - "ro.hardware.hifi.support=true\n" - "ro.com.android.dateformat=MM-dd-yyyy\n" - "ro.config.ringtone=03_Flyme.ogg\n" - "ro.config.notification_sound=02_Reminder.ogg\n" - "ro.config.mms_sound=01_Triumph.ogg\n" - "ro.config.email_sound=02_Reminder.ogg\n" - "ro.config.calendar_sound=03_Doorbell.ogg\n" - "ro.config.alarm_alert=19_Waltz.ogg\n" - "log.tag.VibeTonz=ERROR\n" - "ro.carrier=unknown\n" - "ro.mediatek.chip_ver=S01\n" - "ro.mediatek.version.release=alps-mp-m0.mp9-V1.13.2_meizu6797.6c.m\n" - "ro.mediatek.platform=MT6797\n" - "ro.telephony.sim.count=2\n" - "persist.radio.default.sim=0\n" - "persist.radio.multisim.config=dsds\n" - "persist.gemini.sim_num=2\n" - "ro.gemini.smart_sim_switch=false\n" - "ril.specific.sm_cause=0\n" - "bgw.current3gband=0\n" - "ril.external.md=0\n" - "ro.mtk_cam_lomo_support=1\n" - "ro.sf.hwrotation=0\n" - "ro.mediatek.gemini_support=true\n" - "persist.radio.fd.counter=15\n" - "persist.radio.fd.off.counter=5\n" - "persist.radio.fd.r8.counter=15\n" - "persist.radio.fd.off.r8.counter=5\n" - "drm.service.enabled=true\n" - "fmradio.driver.enable=0\n" - "mtk.eccci.c2k=enabled\n" - "ril.first.md=1\n" - "ril.flightmode.poweroffMD=0\n" - "ril.telephony.mode=0\n" - "dalvik.vm.mtk-stack-trace-file=/data/anr/mtk_traces.txt\n" - "mediatek.wlan.chip=CONSYS_MT6797\n" - "mediatek.wlan.module.postfix=_consys_mt6797\n" - "ril.read.imsi=1\n" - "ril.radiooff.poweroffMD=0\n" - "ro.frp.pst=/dev/block/platform/mtk-msdc.0/11230000.msdc0/by-name/frp\n" - "ro.mediatek.version.branch=alps-mp-m0.mp9\n" - "ro.mediatek.version.sdk=4\n" - "ro.mtk_gemini_support=1\n" - "persist.radio.gemini_support=1\n" - "ril.current.share_modem=2\n" - "ro.mtk_audenh_support=1\n" - "ro.mtk_bessurround_support=1\n" - "ro.mtk_wapi_support=1\n" - "ro.mtk_bt_support=1\n" - "ro.mtk_wappush_support=1\n" - "ro.mtk_agps_app=1\n" - "ro.mtk_audio_tuning_tool_ver=V2.2\n" - "ro.mtk_wlan_support=1\n" - "ro.mtk_gps_support=1\n" - "ro.mtk_omacp_support=1\n" - "ro.mtk_search_db_support=1\n" - "ro.mtk_dialer_search_support=1\n" - "ro.mtk_dhcpv6c_wifi=1\n" - "ro.have_aacencode_feature=1\n" - "ro.mtk_fd_support=1\n" - "ro.mtk_oma_drm_support=1\n" - "ro.mtk_cta_drm_support=1\n" - "ro.mtk_widevine_drm_l3_support=1\n" - "ro.mtk_eap_sim_aka=1\n" - "ro.mtk_audio_ape_support=1\n" - "ro.mtk_flv_playback_support=1\n" - "ro.mtk_wmv_playback_support=1\n" - "ro.mtk_send_rr_support=1\n" - "persist.sys.esn_track_switch=0\n" - "ro.mtk_emmc_support=1\n" - "ro.mtk_tetheringipv6_support=1\n" - "ro.mtk_c2k_support=1\n" - "persist.radio.flashless.fsm=0\n" - "persist.radio.flashless.fsm_cst=0\n" - "persist.radio.flashless.fsm_rw=0\n" - "ro.cdma.cfu.enable=*72\n" - "ro.cdma.cfu.disable=*720\n" - "ro.cdma.cfb.enable=*90\n" - "ro.cdma.cfb.disable=*900\n" - "ro.cdma.cfnr.enable=*92\n" - "ro.cdma.cfnr.disable=*920\n" - "ro.cdma.cfdf.enable=*68\n" - "ro.cdma.cfdf.disable=*680\n" - "ro.cdma.cfall.disable=*730\n" - "ro.cdma.cw.enable=*74\n" - "ro.cdma.cw.disable=*740\n" - "telephony.lteOnCdmaDevice=1\n" - "ro.telephony.default_network=10,10\n" - "ro.mtk_srlte_support=1\n" - "mtk.md1.status=stop\n" - "mtk.md3.status=stop\n" - "ro.c2k.irat.support=1\n" - "ro.mtk.c2k.slot2.support=1\n" - "ro.mtk_shared_sdcard=1\n" - "ro.mtk_enable_md1=1\n" - "ro.mtk_enable_md3=1\n" - "ro.mtk_afw_support=1\n" - "ro.mtk_soter_support=1\n" - "ro.mtk_benchmark_boost_tp=1\n" - "ro.mtk_aal_support=1\n" - "ro.mtk_pq_support=3\n" - "ro.mtk_pq_color_mode=1\n" - "ro.mtk_miravision_support=1\n" - "ro.mtk_miravision_image_dc=1\n" - "ro.mtk_blulight_def_support=1\n" - "ro.mtk_wfd_support=1\n" - "ro.mtk_wfd_sink_support=1\n" - "ro.mtk_wfd_sink_uibc_support=1\n" - "ro.mtk_wifi_mcc_support=1\n" - "ro.mtk_sim_hot_swap=1\n" - "ro.mtk_thumbnail_play_support=1\n" - "ro.mtk_bip_scws=1\n" - "ro.mtk_world_phone=1\n" - "ro.mtk_world_phone_policy=0\n" - "ro.mtk_md_world_mode_support=1\n" - "ro.mtk_perfservice_support=1\n" - "ro.mtk_sim_hot_swap_common_slot=1\n" - "ro.mtk_cta_set=1\n" - "ro.mtk_mobile_management=1\n" - "ro.mtk_antibricking_level=2\n" - "ro.mtk_zsdhdr_support=1\n" - "ro.mtk_cam_mfb_support=3\n" - "ro.mtk_lte_support=1\n" - "ro.mtk_safemedia_support=1\n" - "ro.mtk_cam_vfb=1\n" - "ro.mtk_rild_read_imsi=1\n" - "ro.sim_refresh_reset_by_modem=1\n" - "ro.mtk_external_sim_support=1\n" - "ro.mtk_persist_vsim_disabled=1\n" - "ro.mtk_external_sim_only_slots=0\n" - "ro.mtk_slidevideo_support=1\n" - "ro.mtk_passpoint_r1_support=1\n" - "ro.mtk_privacy_protection_lock=1\n" - "ro.mtk_bg_power_saving_ui=1\n" - "ro.have_aee_feature=1\n" - "ro.sim_me_lock_mode=0\n" - "ro.mtk_dual_mic_support=1\n" - "ro.mtk_is_tablet=0\n" - "ro.mtk_ims_support=1\n" - "ro.mtk_volte_support=1\n" - "persist.mtk.volte.enable=0\n" - "ro.mtk_vilte_support=0\n" - "ro.mtk_vilte_ut_support=0\n" - "wfd.dummy.enable=1\n" - "wfd.iframesize.level=0\n" - "ro.mediatek.project.path=device/meizu/meizu6797_6c_m\n" - "ro.mtk_trustonic_tee_support=1\n" - "ro.flyme_softsim_tee_enable=1\n" - "persist.mtk.wcn.combo.chipid=-1\n" - "persist.mtk.wcn.fwlog.status=no\n" - "persist.mtk.wcn.dynamic.dump=0\n" - "service.wcn.driver.ready=no\n" - "service.wcn.coredump.mode=2\n" - "ro.com.android.mobiledata=false\n" - "persist.radio.mobile.data=0,0\n" - "persist.radio.mobile.enable=1,1\n" - "persist.meta.dumpdata=0\n" - "ro.mtk_hetcomm_support=1\n" - "ro.mtk_deinterlace_support=1\n" - "ro.mtk.c2k.om.mode=cllwtg\n" - "ro.mtk_md_sbp_custom_value=0\n" - "persist.radio.mtk_dsbp_support=1\n" - "persist.mtk_dynamic_ims_switch=0\n" - "ro.mtk_modem_monitor_support=1\n" - "persist.power.usetwilightadj=true\n" - "ro.meizu.enable.stepcounter=true\n" - "debug.hwui.render_dirty_regions=true\n" - "ro.hwui.disable_asset_atlas=true\n" - "dalvik.vm.heapgrowthlimit=256m\n" - "dalvik.vm.heapsize=512m\n" - "ro.hwui.texture_cache_size=48\n" - "ro.hwui.layer_cache_size=32\n" - "ro.hwui.r_buffer_cache_size=8\n" - "ro.hwui.path_cache_size=32\n" - "ro.hwui.gradient_cache_size=3\n" - "ro.hwui.drop_shadow_cache_size=6\n" - "ro.hwui.fbo_cache_size=25\n" - "ro.hwui.texture_cache_flushrate=0.4\n" - "ro.hwui.text_small_cache_width=1024\n" - "ro.hwui.text_small_cache_height=1024\n" - "ro.hwui.text_large_cache_width=2048\n" - "ro.hwui.text_large_cache_height=1024\n" - "ro.product.perf.config=M80_base\n" - "persist.perf.url.wxhbpng=http://wx.gtimg.com/hongbao/1605/hb.png\n" - "persist.sf.startingwindow.gles=1\n" - "persist.sys.plugin.path=/data/data/|/data/user/\n" - "persist.sys.plugin.compiler=interpret-only\n" - "persist.sys.app.compiler=speed\n" - "persist.sys.app.thread=4\n" - "persist.sys.mstore.dl.num=1\n" - "persist.sf.ssr.controlbar=0\n" - "ro.aeesp=normal\n" - "persist.sys.timezone=Asia/Shanghai\n" - "persist.sys.meizu.region=cn\n" - "persist.sys.meizu.codepage=gbk\n" - "ro.meizu.region.enable=true\n" - "ro.meizu.contactmsg.auth=false\n" - "ro.meizu.customize.pccw=false\n" - "ro.meizu.autorecorder=true\n" - "ro.meizu.visualvoicemail=true\n" - "ro.meizu.permanentkey=false\n" - "ro.meizu.sip.support=true\n" - "ro.meizu.voip.support=true\n" - "ro.meizu.setupwizard.flyme=true\n" - "ro.meizu.setupwizard.setlang=true\n" - "ro.meizu.security=true\n" - "sys.meizu.m35x.white.config=false\n" - "sys.meizu.white.config=false\n" - "persist.sys.log-main.enable=0\n" - "persist.sys.log-system.enable=0\n" - "persist.sys.log-events.enable=0\n" - "persist.sys.log-radio.enable=0\n" - "persist.sys.use.flyme.icon=true\n" - "ro.adb.secure=1\n" - "persist.sys.ui.hw=true\n" - "keyguard.no_require_sim=true\n" - "persist.sys.keyguard_intercept=true\n" - "persist.sys.disable_blur_view=true\n" - "persist.sys.static_blur_mode=false\n" - "ro.meizu.published.type=prd\n" - "qemu.hw.mainkeys=1\n" - "persist.sys.dalvik.vm.lib.2=libart\n" - "dalvik.vm.isa.arm64.variant=cortex-a53\n" - "dalvik.vm.isa.arm64.features=default\n" - "dalvik.vm.isa.arm.variant=cortex-a53\n" - "dalvik.vm.isa.arm.features=default\n" - "net.bt.name=Android\n" - "dalvik.vm.stack-trace-file=/data/anr/traces.txt\n" - "ro.expect.recovery_id=0x03287262ca56d93a9305bd4e8725b166b5f6cd04000000000000000000000000\n", - }, - { - .path = "/sys/devices/system/cpu/kernel_max", - .size = 2, - .content = "9\n", - }, - { - .path = "/sys/devices/system/cpu/possible", - .size = 4, - .content = "0-9\n", - }, - { - .path = "/sys/devices/system/cpu/present", - .size = 4, - .content = "0-9\n", - }, - { - .path = "/sys/devices/system/cpu/online", - .size = 6, - .content = "4-6,8\n", - }, - { - .path = "/sys/devices/system/cpu/offline", - .size = 4, - .content = "3,9\n", - }, - { - .path = "/sys/devices/system/cpu/modalias", - .size = 66, - .content = "cpu:type:aarch64:feature:,0000,0001,0002,0003,0004,0005,0006,0007\n", - }, - { - .path = "/sys/devices/system/cpu/cpufreq/all_time_in_state", - .size = 1488, - .content = - "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\tcpu8\t\tcpu9\t\t\n" - "221000\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "325000\t\tN/A\t\t15\t\t15\t\t15\t\t15\t\t\n" - "338000\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "468000\t\tN/A\t\t0\t\t0\t\t0\t\t0\t\t\n" - "481000\t\t3\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "624000\t\t5\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "650000\t\tN/A\t\t2\t\t2\t\t2\t\t2\t\t\n" - "676000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "715000\t\t3\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "806000\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "832000\t\tN/A\t\t0\t\t0\t\t0\t\t0\t\t\n" - "845000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "897000\t\t195\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "962000\t\tN/A\t\t0\t\t0\t\t0\t\t0\t\t\n" - "1001000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1014000\t\t66\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1079000\t\tN/A\t\t0\t\t0\t\t0\t\t0\t\t\n" - "1118000\t\t39\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1131000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1209000\t\tN/A\t\t190\t\t190\t\t190\t\t190\t\t\n" - "1222000\t\t8\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1274000\t\t34\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1339000\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1352000\t\tN/A\t\t71\t\t71\t\t71\t\t71\t\t\n" - "1378000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1391000\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1443000\t\t8\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1495000\t\t0\t\t3\t\t3\t\t3\t\t3\t\t\n" - "1547000\t\t562\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1625000\t\tN/A\t\t67\t\t67\t\t67\t\t67\t\t\n" - "1677000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1703000\t\tN/A\t\t52\t\t52\t\t52\t\t52\t\t\n" - "1755000\t\tN/A\t\t34\t\t34\t\t34\t\t34\t\t\n" - "1820000\t\tN/A\t\t70\t\t70\t\t70\t\t70\t\t\n" - "1885000\t\tN/A\t\t8\t\t8\t\t8\t\t8\t\t\n" - "1950000\t\tN/A\t\t16\t\t16\t\t16\t\t16\t\t\n" - "2002000\t\tN/A\t\t1817\t\t1817\t\t1817\t\t1817\t\t\n" - "2093000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "2158000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "2223000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "2262000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "2327000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "2392000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "2522000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n", - }, - { - .path = "/sys/devices/system/cpu/cpufreq/current_in_state", - .size = 1590, - .content = - "CPU0:1547000=0 1495000=0 1443000=0 1391000=0 1339000=0 1274000=0 1222000=0 1118000=0 1014000=0 897000=0 806000=0 715000=0 624000=0 481000=0 338000=0 221000=0 \n" - "CPU1:1547000=0 1495000=0 1443000=0 1391000=0 1339000=0 1274000=0 1222000=0 1118000=0 1014000=0 897000=0 806000=0 715000=0 624000=0 481000=0 338000=0 221000=0 \n" - "CPU2:1547000=0 1495000=0 1443000=0 1391000=0 1339000=0 1274000=0 1222000=0 1118000=0 1014000=0 897000=0 806000=0 715000=0 624000=0 481000=0 338000=0 221000=0 \n" - "CPU3:1547000=0 1495000=0 1443000=0 1391000=0 1339000=0 1274000=0 1222000=0 1118000=0 1014000=0 897000=0 806000=0 715000=0 624000=0 481000=0 338000=0 221000=0 \n" - "CPU4:1547000=0 1495000=0 1443000=0 1391000=0 1339000=0 1274000=0 1222000=0 1118000=0 1014000=0 897000=0 806000=0 715000=0 624000=0 481000=0 338000=0 221000=0 \n" - "CPU5:1547000=0 1495000=0 1443000=0 1391000=0 1339000=0 1274000=0 1222000=0 1118000=0 1014000=0 897000=0 806000=0 715000=0 624000=0 481000=0 338000=0 221000=0 \n" - "CPU6:1547000=0 1495000=0 1443000=0 1391000=0 1339000=0 1274000=0 1222000=0 1118000=0 1014000=0 897000=0 806000=0 715000=0 624000=0 481000=0 338000=0 221000=0 \n" - "CPU7:1547000=0 1495000=0 1443000=0 1391000=0 1339000=0 1274000=0 1222000=0 1118000=0 1014000=0 897000=0 806000=0 715000=0 624000=0 481000=0 338000=0 221000=0 \n" - "CPU8:1547000=0 1495000=0 1443000=0 1391000=0 1339000=0 1274000=0 1222000=0 1118000=0 1014000=0 897000=0 806000=0 715000=0 624000=0 481000=0 338000=0 221000=0 \n" - "CPU9:1547000=0 1495000=0 1443000=0 1391000=0 1339000=0 1274000=0 1222000=0 1118000=0 1014000=0 897000=0 806000=0 715000=0 624000=0 481000=0 338000=0 221000=0 \n", - }, - { - .path = "/sys/devices/system/cpu/cpuidle/current_driver", - .size = 18, - .content = "mt67xx_v2_cpuidle\n", - }, - { - .path = "/sys/devices/system/cpu/cpuidle/current_governor_ro", - .size = 13, - .content = "mtk_governor\n", - }, - { - .path = "/sys/devices/system/cpu/cputopo/cpus_per_cluster", - .size = 39, - .content = - "cluster0: f\n" - "cluster1: f0\n" - "cluster2: 300\n", - }, - { - .path = "/sys/devices/system/cpu/cputopo/glbinfo", - .size = 87, - .content = - "big/little arch: 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"/sys/devices/system/cpu/cpu6/topology/core_id", - .size = 2, - .content = "2\n", - }, - { - .path = "/sys/devices/system/cpu/cpu6/topology/thread_siblings_list", - .size = 2, - .content = "6\n", - }, - { - .path = "/sys/devices/system/cpu/cpu6/topology/thread_siblings", - .size = 4, - .content = "040\n", - }, - { - .path = "/sys/devices/system/cpu/cpu7/cpufreq/affected_cpus", - .size = 8, - .content = "4 5 6 7\n", - }, - { - .path = "/sys/devices/system/cpu/cpu7/cpufreq/cpuinfo_max_freq", - .size = 8, - .content = "2002000\n", - }, - { - .path = "/sys/devices/system/cpu/cpu7/cpufreq/cpuinfo_min_freq", - .size = 7, - .content = "325000\n", - }, - { - .path = "/sys/devices/system/cpu/cpu7/cpufreq/cpuinfo_transition_latency", - .size = 5, - .content = "1000\n", - }, - { - .path = "/sys/devices/system/cpu/cpu7/cpufreq/related_cpus", - .size = 8, - .content = "4 5 6 7\n", - }, - { - .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_available_frequencies", - .size = 124, - .content = "2002000 1950000 1885000 1820000 1755000 1703000 1625000 1495000 1352000 1209000 1079000 962000 832000 650000 468000 325000 \n", - }, - { - .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_available_governors", - .size = 13, - .content = "interactive \n", - }, - { - .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_cur_freq", - .size = 8, - .content = "1495000\n", - }, - { - .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_driver", - .size = 11, - .content = "mt-cpufreq\n", - }, - { - .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_governor", - .size = 12, - .content = "interactive\n", - }, - { - .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_max_freq", - .size = 8, - .content = "2002000\n", - }, - { - .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_min_freq", - .size = 7, - .content = "325000\n", - }, - { - .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/time_in_state", - .size = 173, - .content = - "2002000 2600\n" - "1950000 30\n" - "1885000 16\n" - "1820000 84\n" - "1755000 34\n" - "1703000 65\n" - "1625000 81\n" - "1495000 14\n" - "1352000 364\n" - "1209000 704\n" - "1079000 0\n" - "962000 71\n" - "832000 82\n" - "650000 2\n" - "468000 20\n" - "325000 15\n", - }, - { - .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/total_trans", - .size = 4, - .content = "228\n", - }, - { - .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/trans_table", - .size = 2941, - .content = - " From : To\n" - " : 2002000 1950000 1885000 1820000 1755000 1703000 1625000 1495000 1352000 1209000 1079000 962000 832000 650000 468000 325000 \n" - " 2002000: 0 0 1 7 2 1 2 0 7 23 0 3 1 0 0 1 \n" - " 1950000: 8 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 \n" - " 1885000: 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \n" - " 1820000: 5 2 3 0 0 2 2 0 0 1 0 0 0 0 0 0 \n" - " 1755000: 1 0 0 3 0 0 3 0 0 0 0 0 0 0 0 0 \n" - " 1703000: 1 0 1 2 2 0 1 0 0 0 0 0 0 0 0 0 \n" - " 1625000: 7 0 0 1 3 3 0 0 0 0 0 0 0 0 0 0 \n" - " 1495000: 1 1 0 0 0 1 4 0 0 0 0 0 0 0 0 0 \n" - " 1352000: 5 0 0 1 0 0 2 6 0 13 0 2 0 0 0 0 \n" - " 1209000: 15 1 0 0 0 0 0 1 20 0 0 6 0 1 4 0 \n" - " 1079000: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \n" - " 962000: 2 0 0 0 0 0 0 0 3 11 0 0 4 0 0 0 \n" - " 832000: 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 \n" - " 650000: 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \n" - " 468000: 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 \n" - " 325000: 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \n", - }, - { - .path = "/sys/devices/system/cpu/cpu7/topology/physical_package_id", - .size = 2, - .content = "1\n", - }, - { - .path = "/sys/devices/system/cpu/cpu7/topology/core_siblings_list", - .size = 4, - .content = "4-7\n", - }, - { - .path = "/sys/devices/system/cpu/cpu7/topology/core_siblings", - .size = 4, - .content = "0f0\n", - }, - { - .path = "/sys/devices/system/cpu/cpu7/topology/core_id", - .size = 2, - .content = "3\n", - }, - { - .path = "/sys/devices/system/cpu/cpu7/topology/thread_siblings_list", - .size = 2, - .content = "7\n", - }, - { - .path = "/sys/devices/system/cpu/cpu7/topology/thread_siblings", - .size = 4, - .content = "080\n", - }, - { - .path = "/sys/devices/system/cpu/cpu9/cpufreq/related_cpus", - .size = 4, - .content = "8 9\n", - }, - { - .path = "/sys/devices/system/cpu/cpu9/cpufreq/scaling_available_frequencies", - .size = 126, - .content = "2522000 2392000 2327000 2262000 2223000 2158000 2093000 1885000 1677000 1495000 1378000 1131000 1001000 845000 676000 338000 \n", - }, - { NULL }, +struct cpuinfo_mock_file + filesystem[] = + { + { + .path = "/proc/cpuinfo", + .size = 1661, + .content = "Processor\t: AArch64 Processor rev 4 (aarch64)\n" + "processor\t: 0\n" + "model name\t: AArch64 Processor rev 4 (aarch64)\n" + "BogoMIPS\t: 26.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 1\n" + "model name\t: AArch64 Processor rev 4 (aarch64)\n" + "BogoMIPS\t: 26.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 2\n" + "model name\t: AArch64 Processor rev 4 (aarch64)\n" + "BogoMIPS\t: 26.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 4\n" + "model name\t: AArch64 Processor rev 4 (aarch64)\n" + "BogoMIPS\t: 26.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 5\n" + "model name\t: AArch64 Processor rev 4 (aarch64)\n" + "BogoMIPS\t: 26.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 6\n" + "model name\t: AArch64 Processor rev 4 (aarch64)\n" + "BogoMIPS\t: 26.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 7\n" + "model name\t: AArch64 Processor rev 4 (aarch64)\n" + "BogoMIPS\t: 26.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "Hardware\t: MT6797T\n", + }, + { + .path = "/system/build.prop", + .size = 9920, + .content = + "\n" + "import /custom/cip-build.prop\n" + "# begin build properties\n" + "# autogenerated by buildinfo.sh\n" + "ro.build.cta=noncta\n" + "ro.meizu.build.spt=0\n" + "ro.build.id=MRA58K\n" + "ro.build.mask.id=6.0-1484499354_stable\n" + "ro.build.inside.id=6.0-20170116005554\n" + "ro.build.version.incremental=1484499894\n" + "ro.build.version.sdk=23\n" + "ro.build.version.preview_sdk=0\n" + "ro.build.version.codename=REL\n" + "ro.build.version.all_codenames=REL\n" + "ro.build.version.release=6.0\n" + "ro.build.version.security_patch=2016-11-05\n" + "ro.build.version.base_os=\n" + "ro.build.date=Mon Jan 16 01:09:06 CST 2017\n" + "ro.build.date.utc=1484500146\n" + "ro.build.type=user\n" + "ro.build.user=flyme\n" + "ro.build.host=Mz-Builder-l10\n" + "ro.build.tags=release-keys\n" + "ro.build.flavor=full_meizu6797_6c_m-user\n" + "# ro.product.cpu.abi and ro.product.cpu.abi2 are obsolete,\n" + "# use ro.product.cpu.abilist instead.\n" + "ro.product.cpu.abi=arm64-v8a\n" + "ro.product.cpu.abilist=arm64-v8a,armeabi-v7a,armeabi\n" + "ro.product.cpu.abilist32=armeabi-v7a,armeabi\n" + "ro.product.cpu.abilist64=arm64-v8a\n" + "ro.product.locale=en-US\n" + "ro.wifi.channels=\n" + "ro.board.platform=mt6797\n" + "# ro.build.product is obsolete; use ro.product.device\n" + "# Do not try to parse description, fingerprint, or thumbprint\n" + "ro.build.characteristics=default\n" + "ro.product.brand=Meizu\n" + "ro.product.manufacturer=Meizu\n" + "ro.build.display.id=Flyme 6.0.1.0A\n" + "ro.product.model=PRO 6\n" + "ro.meizu.product.model=PRO6\n" + "ro.product.name=meizu_PRO6\n" + "ro.product.device=PRO6\n" + "ro.product.board=PRO6\n" + "# ro.build.product is obsolete; use ro.product.device\n" + "ro.build.product=PRO6\n" + "# Do not try to parse ro.build.description or .fingerprint\n" + "ro.build.description=meizu_PRO6-user 6.0 MRA58K 1484499894 release-keys\n" + "ro.build.fingerprint=Meizu/meizu_PRO6/PRO6:6.0/MRA58K/1484499894:user/release-keys\n" + "ro.meizu.project.id=m8097-5\n" + "ro.product.flyme.model=8097\n" + "ro.flyme.published = true\n" + "ro.meizu.has_datamigration_app=true\n" + "# end build properties\n" + "#\n" + "# from device/meizu/meizu6797_6c_m/system.prop\n" + "#\n" + "#\n" + "# system.prop for generic sdk\n" + "#\n" + "\n" + "rild.libpath=mtk-ril.so\n" + "rild.libargs=-d /dev/ttyC0\n" + "\n" + "\n" + "# MTK, Infinity, 20090720 {\n" + "wifi.interface=wlan0\n" + "# MTK, Infinity, 20090720 }\n" + "\n" + "# MTK, mtk03034, 20101210 {\n" + "ro.mediatek.wlan.wsc=1\n" + "# MTK, mtk03034 20101210}\n" + "# MTK, mtk03034, 20110318 {\n" + "ro.mediatek.wlan.p2p=1\n" + "# MTK, mtk03034 20110318}\n" + "\n" + "# MTK, mtk03034, 20101213 {\n" + "mediatek.wlan.ctia=0\n" + "# MTK, mtk03034 20101213}\n" + "\n" + "\n" + "#\n" + "wifi.tethering.interface=ap0\n" + "#\n" + "\n" + "ro.opengles.version=196608\n" + "#ro.kernel.qemu=1\n" + "\n" + "wifi.direct.interface=p2p0\n" + "dalvik.vm.heapgrowthlimit=256m\n" + "dalvik.vm.heapsize=512m\n" + "\n" + "# USB MTP WHQL\n" + "ro.sys.usb.mtp.whql.enable=0\n" + "\n" + "# Power off opt in IPO\n" + "sys.ipo.pwrdncap=2\n" + "\n" + "ro.sys.usb.storage.type=mtp,mass_storage\n" + "\n" + "# USB BICR function\n" + "ro.sys.usb.bicr=yes\n" + "\n" + "# USB Charge only function\n" + "ro.sys.usb.charging.only=yes\n" + "\n" + "# audio\n" + "ro.camera.sound.forced=0\n" + "ro.audio.silent=0\n" + "\n" + "ro.zygote.preload.enable=0\n" + "\n" + "# temporary enables NAV bar (soft keys)\n" + "qemu.hw.mainkeys=1\n" + "\n" + "ro.kernel.zio=38,108,105,16\n" + "#ro.kernel.qemu=1\n" + "#ro.kernel.qemu.gles=0\n" + "#ro.boot.selinux=disable\n" + "\n" + "# Disable dirty region for Mali\n" + "#debug.hwui.render_dirty_regions=false\n" + "\n" + "ro.sf.lcd_density=480\n" + "\n" + "# performance\n" + "ro.mtk_perf_simple_start_win=1\n" + "ro.mtk_perf_fast_start_win=0\n" + "ro.mtk_perf_response_time=1\n" + "\n" + "# Define PhoneApp ToneVolume\n" + "persist.dialpad.volume=60\n" + "persist.dialpad.ecc.volume=60\n" + "persist.dtmf.volume=70\n" + "persist.call.waiting.volume=85\n" + "persist.ring.back.volume=85\n" + "\n" + "#\n" + "# ADDITIONAL_BUILD_PROPERTIES\n" + "#\n" + "ro.hardware.hifi.support=true\n" + "ro.com.android.dateformat=MM-dd-yyyy\n" + "ro.config.ringtone=03_Flyme.ogg\n" + "ro.config.notification_sound=02_Reminder.ogg\n" + "ro.config.mms_sound=01_Triumph.ogg\n" + "ro.config.email_sound=02_Reminder.ogg\n" + "ro.config.calendar_sound=03_Doorbell.ogg\n" + "ro.config.alarm_alert=19_Waltz.ogg\n" + "log.tag.VibeTonz=ERROR\n" + "ro.carrier=unknown\n" + "ro.mediatek.chip_ver=S01\n" + "ro.mediatek.version.release=alps-mp-m0.mp9-V1.13.2_meizu6797.6c.m\n" + "ro.mediatek.platform=MT6797\n" + "ro.telephony.sim.count=2\n" + "persist.radio.default.sim=0\n" + "persist.radio.multisim.config=dsds\n" + "persist.gemini.sim_num=2\n" + "ro.gemini.smart_sim_switch=false\n" + "ril.specific.sm_cause=0\n" + "bgw.current3gband=0\n" + "ril.external.md=0\n" + "ro.mtk_cam_lomo_support=1\n" + "ro.sf.hwrotation=0\n" + "ro.mediatek.gemini_support=true\n" + "persist.radio.fd.counter=15\n" + "persist.radio.fd.off.counter=5\n" + "persist.radio.fd.r8.counter=15\n" + "persist.radio.fd.off.r8.counter=5\n" + "drm.service.enabled=true\n" + "fmradio.driver.enable=0\n" + "mtk.eccci.c2k=enabled\n" + "ril.first.md=1\n" + "ril.flightmode.poweroffMD=0\n" + "ril.telephony.mode=0\n" + "dalvik.vm.mtk-stack-trace-file=/data/anr/mtk_traces.txt\n" + "mediatek.wlan.chip=CONSYS_MT6797\n" + "mediatek.wlan.module.postfix=_consys_mt6797\n" + "ril.read.imsi=1\n" + "ril.radiooff.poweroffMD=0\n" + "ro.frp.pst=/dev/block/platform/mtk-msdc.0/11230000.msdc0/by-name/frp\n" + "ro.mediatek.version.branch=alps-mp-m0.mp9\n" + "ro.mediatek.version.sdk=4\n" + "ro.mtk_gemini_support=1\n" + "persist.radio.gemini_support=1\n" + "ril.current.share_modem=2\n" + "ro.mtk_audenh_support=1\n" + "ro.mtk_bessurround_support=1\n" + "ro.mtk_wapi_support=1\n" + "ro.mtk_bt_support=1\n" + "ro.mtk_wappush_support=1\n" + "ro.mtk_agps_app=1\n" + "ro.mtk_audio_tuning_tool_ver=V2.2\n" + "ro.mtk_wlan_support=1\n" + "ro.mtk_gps_support=1\n" + "ro.mtk_omacp_support=1\n" + "ro.mtk_search_db_support=1\n" + "ro.mtk_dialer_search_support=1\n" + "ro.mtk_dhcpv6c_wifi=1\n" + "ro.have_aacencode_feature=1\n" + "ro.mtk_fd_support=1\n" + "ro.mtk_oma_drm_support=1\n" + "ro.mtk_cta_drm_support=1\n" + "ro.mtk_widevine_drm_l3_support=1\n" + "ro.mtk_eap_sim_aka=1\n" + "ro.mtk_audio_ape_support=1\n" + "ro.mtk_flv_playback_support=1\n" + "ro.mtk_wmv_playback_support=1\n" + "ro.mtk_send_rr_support=1\n" + "persist.sys.esn_track_switch=0\n" + "ro.mtk_emmc_support=1\n" + "ro.mtk_tetheringipv6_support=1\n" + "ro.mtk_c2k_support=1\n" + "persist.radio.flashless.fsm=0\n" + "persist.radio.flashless.fsm_cst=0\n" + "persist.radio.flashless.fsm_rw=0\n" + "ro.cdma.cfu.enable=*72\n" + "ro.cdma.cfu.disable=*720\n" + "ro.cdma.cfb.enable=*90\n" + "ro.cdma.cfb.disable=*900\n" + "ro.cdma.cfnr.enable=*92\n" + "ro.cdma.cfnr.disable=*920\n" + "ro.cdma.cfdf.enable=*68\n" + "ro.cdma.cfdf.disable=*680\n" + "ro.cdma.cfall.disable=*730\n" + "ro.cdma.cw.enable=*74\n" + "ro.cdma.cw.disable=*740\n" + "telephony.lteOnCdmaDevice=1\n" + "ro.telephony.default_network=10,10\n" + "ro.mtk_srlte_support=1\n" + "mtk.md1.status=stop\n" + "mtk.md3.status=stop\n" + "ro.c2k.irat.support=1\n" + "ro.mtk.c2k.slot2.support=1\n" + "ro.mtk_shared_sdcard=1\n" + "ro.mtk_enable_md1=1\n" + "ro.mtk_enable_md3=1\n" + "ro.mtk_afw_support=1\n" + "ro.mtk_soter_support=1\n" + "ro.mtk_benchmark_boost_tp=1\n" + "ro.mtk_aal_support=1\n" + "ro.mtk_pq_support=3\n" + "ro.mtk_pq_color_mode=1\n" + "ro.mtk_miravision_support=1\n" + "ro.mtk_miravision_image_dc=1\n" + "ro.mtk_blulight_def_support=1\n" + "ro.mtk_wfd_support=1\n" + "ro.mtk_wfd_sink_support=1\n" + "ro.mtk_wfd_sink_uibc_support=1\n" + "ro.mtk_wifi_mcc_support=1\n" + "ro.mtk_sim_hot_swap=1\n" + "ro.mtk_thumbnail_play_support=1\n" + "ro.mtk_bip_scws=1\n" + "ro.mtk_world_phone=1\n" + "ro.mtk_world_phone_policy=0\n" + "ro.mtk_md_world_mode_support=1\n" + "ro.mtk_perfservice_support=1\n" + "ro.mtk_sim_hot_swap_common_slot=1\n" + "ro.mtk_cta_set=1\n" + "ro.mtk_mobile_management=1\n" + "ro.mtk_antibricking_level=2\n" + "ro.mtk_zsdhdr_support=1\n" + "ro.mtk_cam_mfb_support=3\n" + "ro.mtk_lte_support=1\n" + "ro.mtk_safemedia_support=1\n" + "ro.mtk_cam_vfb=1\n" + "ro.mtk_rild_read_imsi=1\n" + "ro.sim_refresh_reset_by_modem=1\n" + "ro.mtk_external_sim_support=1\n" + "ro.mtk_persist_vsim_disabled=1\n" + "ro.mtk_external_sim_only_slots=0\n" + "ro.mtk_slidevideo_support=1\n" + "ro.mtk_passpoint_r1_support=1\n" + "ro.mtk_privacy_protection_lock=1\n" + "ro.mtk_bg_power_saving_ui=1\n" + "ro.have_aee_feature=1\n" + "ro.sim_me_lock_mode=0\n" + "ro.mtk_dual_mic_support=1\n" + "ro.mtk_is_tablet=0\n" + "ro.mtk_ims_support=1\n" + "ro.mtk_volte_support=1\n" + "persist.mtk.volte.enable=0\n" + "ro.mtk_vilte_support=0\n" + "ro.mtk_vilte_ut_support=0\n" + "wfd.dummy.enable=1\n" + "wfd.iframesize.level=0\n" + "ro.mediatek.project.path=device/meizu/meizu6797_6c_m\n" + "ro.mtk_trustonic_tee_support=1\n" + "ro.flyme_softsim_tee_enable=1\n" + "persist.mtk.wcn.combo.chipid=-1\n" + "persist.mtk.wcn.fwlog.status=no\n" + "persist.mtk.wcn.dynamic.dump=0\n" + "service.wcn.driver.ready=no\n" + "service.wcn.coredump.mode=2\n" + "ro.com.android.mobiledata=false\n" + "persist.radio.mobile.data=0,0\n" + "persist.radio.mobile.enable=1,1\n" + "persist.meta.dumpdata=0\n" + "ro.mtk_hetcomm_support=1\n" + "ro.mtk_deinterlace_support=1\n" + "ro.mtk.c2k.om.mode=cllwtg\n" + "ro.mtk_md_sbp_custom_value=0\n" + "persist.radio.mtk_dsbp_support=1\n" + "persist.mtk_dynamic_ims_switch=0\n" + "ro.mtk_modem_monitor_support=1\n" + "persist.power.usetwilightadj=true\n" + "ro.meizu.enable.stepcounter=true\n" + "debug.hwui.render_dirty_regions=true\n" + "ro.hwui.disable_asset_atlas=true\n" + "dalvik.vm.heapgrowthlimit=256m\n" + "dalvik.vm.heapsize=512m\n" + "ro.hwui.texture_cache_size=48\n" + "ro.hwui.layer_cache_size=32\n" + "ro.hwui.r_buffer_cache_size=8\n" + "ro.hwui.path_cache_size=32\n" + "ro.hwui.gradient_cache_size=3\n" + "ro.hwui.drop_shadow_cache_size=6\n" + "ro.hwui.fbo_cache_size=25\n" + "ro.hwui.texture_cache_flushrate=0.4\n" + "ro.hwui.text_small_cache_width=1024\n" + "ro.hwui.text_small_cache_height=1024\n" + "ro.hwui.text_large_cache_width=2048\n" + "ro.hwui.text_large_cache_height=1024\n" + "ro.product.perf.config=M80_base\n" + "persist.perf.url.wxhbpng=http://wx.gtimg.com/hongbao/1605/hb.png\n" + "persist.sf.startingwindow.gles=1\n" + "persist.sys.plugin.path=/data/data/|/data/user/\n" + "persist.sys.plugin.compiler=interpret-only\n" + "persist.sys.app.compiler=speed\n" + "persist.sys.app.thread=4\n" + "persist.sys.mstore.dl.num=1\n" + "persist.sf.ssr.controlbar=0\n" + "ro.aeesp=normal\n" + "persist.sys.timezone=Asia/Shanghai\n" + "persist.sys.meizu.region=cn\n" + "persist.sys.meizu.codepage=gbk\n" + "ro.meizu.region.enable=true\n" + "ro.meizu.contactmsg.auth=false\n" + "ro.meizu.customize.pccw=false\n" + "ro.meizu.autorecorder=true\n" + "ro.meizu.visualvoicemail=true\n" + "ro.meizu.permanentkey=false\n" + "ro.meizu.sip.support=true\n" + "ro.meizu.voip.support=true\n" + "ro.meizu.setupwizard.flyme=true\n" + "ro.meizu.setupwizard.setlang=true\n" + "ro.meizu.security=true\n" + "sys.meizu.m35x.white.config=false\n" + "sys.meizu.white.config=false\n" + "persist.sys.log-main.enable=0\n" + "persist.sys.log-system.enable=0\n" + "persist.sys.log-events.enable=0\n" + "persist.sys.log-radio.enable=0\n" + "persist.sys.use.flyme.icon=true\n" + "ro.adb.secure=1\n" + "persist.sys.ui.hw=true\n" + "keyguard.no_require_sim=true\n" + "persist.sys.keyguard_intercept=true\n" + "persist.sys.disable_blur_view=true\n" + "persist.sys.static_blur_mode=false\n" + "ro.meizu.published.type=prd\n" + "qemu.hw.mainkeys=1\n" + "persist.sys.dalvik.vm.lib.2=libart\n" + "dalvik.vm.isa.arm64.variant=cortex-a53\n" + "dalvik.vm.isa.arm64.features=default\n" + "dalvik.vm.isa.arm.variant=cortex-a53\n" + "dalvik.vm.isa.arm.features=default\n" + "net.bt.name=Android\n" + "dalvik.vm.stack-trace-file=/data/anr/traces.txt\n" + "ro.expect.recovery_id=0x03287262ca56d93a9305bd4e8725b166b5f6cd04000000000000000000000000\n", + }, + { + .path = "/sys/devices/system/cpu/kernel_max", + .size = 2, + .content = "9\n", + }, + { + .path = "/sys/devices/system/cpu/possible", + .size = 4, + .content = "0-9\n", + }, + { + .path = "/sys/devices/system/cpu/present", + .size = 4, + .content = "0-9\n", + }, + { + .path = "/sys/devices/system/cpu/online", + .size = 6, + .content = "4-6,8\n", + }, + { + .path = "/sys/devices/system/cpu/offline", + .size = 4, + .content = "3,9\n", + }, + { + .path = "/sys/devices/system/cpu/modalias", + .size = 66, + .content = "cpu:type:aarch64:feature:,0000,0001,0002,0003,0004,0005,0006,0007\n", + }, + { + .path = "/sys/devices/system/cpu/cpufreq/all_time_in_state", + .size = 1488, + .content = + "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\tcpu8\t\tcpu9\t\t\n" + "221000\t\t0\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "325000\t\tN/A\t\t15\t\t15\t\t15\t\t15\t\t\n" + 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1118000=0 1014000=0 897000=0 806000=0 715000=0 624000=0 481000=0 338000=0 221000=0 \n" + "CPU5:1547000=0 1495000=0 1443000=0 1391000=0 1339000=0 1274000=0 1222000=0 1118000=0 1014000=0 897000=0 806000=0 715000=0 624000=0 481000=0 338000=0 221000=0 \n" + "CPU6:1547000=0 1495000=0 1443000=0 1391000=0 1339000=0 1274000=0 1222000=0 1118000=0 1014000=0 897000=0 806000=0 715000=0 624000=0 481000=0 338000=0 221000=0 \n" + "CPU7:1547000=0 1495000=0 1443000=0 1391000=0 1339000=0 1274000=0 1222000=0 1118000=0 1014000=0 897000=0 806000=0 715000=0 624000=0 481000=0 338000=0 221000=0 \n" + "CPU8:1547000=0 1495000=0 1443000=0 1391000=0 1339000=0 1274000=0 1222000=0 1118000=0 1014000=0 897000=0 806000=0 715000=0 624000=0 481000=0 338000=0 221000=0 \n" + "CPU9:1547000=0 1495000=0 1443000=0 1391000=0 1339000=0 1274000=0 1222000=0 1118000=0 1014000=0 897000=0 806000=0 715000=0 624000=0 481000=0 338000=0 221000=0 \n", + }, + { + .path = "/sys/devices/system/cpu/cpuidle/current_driver", + .size = 18, + .content = "mt67xx_v2_cpuidle\n", + }, + { + .path = "/sys/devices/system/cpu/cpuidle/current_governor_ro", + .size = 13, + .content = "mtk_governor\n", + }, + { + .path = "/sys/devices/system/cpu/cputopo/cpus_per_cluster", + .size = 39, + .content = "cluster0: f\n" + "cluster1: f0\n" + "cluster2: 300\n", + }, + { + .path = "/sys/devices/system/cpu/cputopo/glbinfo", + .size = 87, + .content = "big/little arch: yes\n" + "nr_cups: 10\n" + "nr_clusters: 3\n" + "cluster0: f\n" + "cluster1: f0\n" + "cluster2: 300\n", + }, + { + .path = "/sys/devices/system/cpu/cputopo/is_big_little", + .size = 2, + .content = "1\n", + }, + { + .path = "/sys/devices/system/cpu/cputopo/is_multi_cluster", + .size = 2, + .content = "1\n", + }, + { + .path = "/sys/devices/system/cpu/cputopo/nr_clusters", + .size = 2, + .content = "3\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/affected_cpus", + .size = 6, + .content = "0 1 2\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq", + .size = 8, + .content = "1547000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_min_freq", + .size = 7, + .content = "221000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_transition_latency", + .size = 5, + .content = "1000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/related_cpus", + .size = 8, + .content = "0 1 2 3\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies", + .size = 122, + .content = + "1547000 1495000 1443000 1391000 1339000 1274000 1222000 1118000 1014000 897000 806000 715000 624000 481000 338000 221000 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors", + .size = 13, + .content = "interactive \n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq", + .size = 8, + .content = "1274000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_driver", + .size = 11, + .content = "mt-cpufreq\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_governor", + .size = 12, + .content = "interactive\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq", + .size = 7, + .content = "897000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_min_freq", + .size = 7, + .content = "221000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", + .size = 160, + .content = "1547000 578\n" + "1495000 0\n" + "1443000 8\n" + "1391000 0\n" + "1339000 0\n" + "1274000 42\n" + "1222000 8\n" + "1118000 49\n" + "1014000 87\n" + "897000 232\n" + "806000 0\n" + "715000 3\n" + "624000 5\n" + "481000 3\n" + "338000 0\n" + "221000 1\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", + .size = 3, + .content = "81\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/trans_table", + .size = 2941, + .content = + " From : To\n" + " : 1547000 1495000 1443000 1391000 1339000 1274000 1222000 1118000 1014000 897000 806000 715000 624000 481000 338000 221000 \n" + " 1547000: 0 0 0 0 0 0 0 2 2 13 0 0 1 1 0 0 \n" + " 1495000: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \n" + " 1443000: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \n" + " 1391000: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \n" + " 1339000: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \n" + " 1274000: 2 0 2 0 0 0 0 0 0 1 0 0 0 0 0 0 \n" + " 1222000: 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 \n" + " 1118000: 1 0 0 0 0 5 2 0 0 1 0 0 0 0 0 0 \n" + " 1014000: 1 0 0 0 0 0 0 7 0 2 0 0 0 0 0 0 \n" + " 897000: 7 0 0 0 0 0 0 3 8 0 0 0 0 0 0 0 \n" + " 806000: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \n" + " 715000: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \n" + " 624000: 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 \n" + " 481000: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \n" + " 338000: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \n" + " 221000: 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/topology/physical_package_id", + .size = 2, + .content = "0\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/topology/core_siblings_list", + .size = 4, + .content = "0-3\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/topology/core_siblings", + .size = 4, + .content = "00f\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/topology/core_id", + .size = 2, + .content = "0\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/topology/thread_siblings_list", + .size = 2, + .content = "0\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/topology/thread_siblings", + .size = 4, + .content = "001\n", + }, + { + .path = "/sys/devices/system/cpu/cpu1/cpufreq/affected_cpus", + .size = 6, + .content = "0 1 2\n", + }, + { + .path = "/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_max_freq", + .size = 8, + .content = "1547000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_min_freq", + .size = 7, + .content = "221000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/cpufreq/affected_cpus", + .size = 8, + .content = "0 1 2 3\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/cpufreq/cpuinfo_max_freq", + .size = 8, + .content = "1547000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/cpufreq/cpuinfo_min_freq", + .size = 7, + .content = "221000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/cpufreq/cpuinfo_transition_latency", + .size = 5, + .content = "1000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/cpufreq/related_cpus", + .size = 8, + .content = "0 1 2 3\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_frequencies", + .size = 122, + .content = + "1547000 1495000 1443000 1391000 1339000 1274000 1222000 1118000 1014000 897000 806000 715000 624000 481000 338000 221000 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_governors", + .size = 13, + .content = "interactive \n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_cur_freq", + .size = 7, + .content = "897000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_driver", + .size = 11, + .content = "mt-cpufreq\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_governor", + .size = 12, + .content = "interactive\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_max_freq", + .size = 7, + .content = "897000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_min_freq", + .size = 7, + .content = "221000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", + .size = 166, + .content = "1547000 634\n" + "1495000 6\n" + "1443000 29\n" + "1391000 2\n" + "1339000 0\n" + "1274000 48\n" + "1222000 12\n" + "1118000 76\n" + "1014000 167\n" + "897000 417\n" + "806000 3\n" + "715000 47\n" + "624000 74\n" + "481000 3\n" + "338000 23\n" + "221000 1\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/topology/core_siblings_list", + .size = 4, + .content = "0-3\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/topology/core_siblings", + .size = 4, + .content = "00f\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/topology/core_id", + .size = 2, + .content = "2\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/topology/thread_siblings_list", + .size = 2, + .content = "2\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/affected_cpus", + .size = 8, + .content = "4 5 6 7\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/cpuinfo_max_freq", + .size = 8, + .content = "2002000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/cpuinfo_min_freq", + .size = 7, + .content = "325000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/cpuinfo_transition_latency", + .size = 5, + .content = "1000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/related_cpus", + .size = 8, + .content = "4 5 6 7\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_available_frequencies", + .size = 124, + .content = + "2002000 1950000 1885000 1820000 1755000 1703000 1625000 1495000 1352000 1209000 1079000 962000 832000 650000 468000 325000 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_available_governors", + .size = 13, + .content = "interactive \n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_cur_freq", + .size = 8, + .content = "2002000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_driver", + .size = 11, + .content = "mt-cpufreq\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_governor", + .size = 12, + .content = "interactive\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_max_freq", + .size = 8, + .content = "2002000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_min_freq", + .size = 7, + .content = "325000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/time_in_state", + .size = 173, + .content = "2002000 2326\n" + "1950000 27\n" + "1885000 14\n" + "1820000 83\n" + "1755000 34\n" + "1703000 64\n" + "1625000 77\n" + "1495000 10\n" + "1352000 253\n" + "1209000 439\n" + "1079000 0\n" + "962000 47\n" + "832000 73\n" + "650000 2\n" + "468000 15\n" + "325000 15\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/total_trans", + .size = 4, + .content = "183\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/trans_table", + .size = 2941, + .content = " From : To\n" + " : 2002000 1950000 1885000 1820000 1755000 1703000 1625000 1495000 1352000 1209000 1079000 962000 832000 650000 468000 325000 \n" + " 2002000: 0 0 1 7 2 1 2 0 7 21 0 1 1 0 0 1 \n" + " 1950000: 7 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 \n" + " 1885000: 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \n" + " 1820000: 5 2 2 0 0 2 2 0 0 1 0 0 0 0 0 0 \n" + " 1755000: 1 0 0 3 0 0 3 0 0 0 0 0 0 0 0 0 \n" + " 1703000: 1 0 1 1 2 0 1 0 0 0 0 0 0 0 0 0 \n" + " 1625000: 6 0 0 1 3 3 0 0 0 0 0 0 0 0 0 0 \n" + " 1495000: 1 1 0 0 0 0 3 0 0 0 0 0 0 0 0 0 \n" + " 1352000: 5 0 0 1 0 0 2 5 0 7 0 2 0 0 0 0 \n" + " 1209000: 14 1 0 0 0 0 0 0 13 0 0 3 0 1 3 0 \n" + " 1079000: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \n" + " 962000: 2 0 0 0 0 0 0 0 2 6 0 0 2 0 0 0 \n" + " 832000: 0 0 0 0 0 0 0 0 0 0 0 6 0 0 0 0 \n" + " 650000: 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \n" + " 468000: 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 \n" + " 325000: 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/topology/physical_package_id", + .size = 2, + .content = "1\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/topology/core_siblings_list", + .size = 4, + .content = "4-7\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/topology/core_siblings", + .size = 4, + .content = "0f0\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/topology/core_id", + .size = 2, + .content = "0\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/topology/thread_siblings_list", + .size = 2, + .content = "4\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/topology/thread_siblings", + .size = 4, + .content = "010\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/affected_cpus", + .size = 8, + .content = "4 5 6 7\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/cpuinfo_max_freq", + .size = 8, + .content = "2002000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/cpuinfo_min_freq", + .size = 7, + .content = "325000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/cpuinfo_transition_latency", + .size = 5, + .content = "1000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/related_cpus", + .size = 8, + .content = "4 5 6 7\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_available_frequencies", + .size = 124, + .content = + "2002000 1950000 1885000 1820000 1755000 1703000 1625000 1495000 1352000 1209000 1079000 962000 832000 650000 468000 325000 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/affected_cpus", + .size = 8, + .content = "4 5 6 7\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/cpuinfo_max_freq", + .size = 8, + .content = "2002000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/cpuinfo_min_freq", + .size = 7, + .content = "325000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/cpuinfo_transition_latency", + .size = 5, + .content = "1000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/related_cpus", + .size = 8, + .content = "4 5 6 7\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_available_frequencies", + .size = 124, + .content = + "2002000 1950000 1885000 1820000 1755000 1703000 1625000 1495000 1352000 1209000 1079000 962000 832000 650000 468000 325000 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_available_governors", + .size = 13, + .content = "interactive \n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_cur_freq", + .size = 8, + .content = "2002000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_driver", + .size = 11, + .content = "mt-cpufreq\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_governor", + .size = 12, + .content = "interactive\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_max_freq", + .size = 7, + .content = "962000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_min_freq", + .size = 7, + .content = "325000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/time_in_state", + .size = 173, + .content = "2002000 2532\n" + "1950000 30\n" + "1885000 14\n" + "1820000 83\n" + "1755000 34\n" + "1703000 64\n" + "1625000 81\n" + "1495000 12\n" + "1352000 339\n" + "1209000 530\n" + "1079000 0\n" + "962000 56\n" + "832000 79\n" + "650000 2\n" + "468000 15\n" + "325000 15\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/total_trans", + .size = 4, + .content = "205\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/trans_table", + .size = 2941, + .content = + " From : To\n" + " : 2002000 1950000 1885000 1820000 1755000 1703000 1625000 1495000 1352000 1209000 1079000 962000 832000 650000 468000 325000 \n" + " 2002000: 0 0 1 7 2 1 2 0 7 23 0 2 1 0 0 1 \n" + " 1950000: 8 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 \n" + " 1885000: 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \n" + " 1820000: 5 2 2 0 0 2 2 0 0 1 0 0 0 0 0 0 \n" + " 1755000: 1 0 0 3 0 0 3 0 0 0 0 0 0 0 0 0 \n" + " 1703000: 1 0 1 1 2 0 1 0 0 0 0 0 0 0 0 0 \n" + " 1625000: 7 0 0 1 3 3 0 0 0 0 0 0 0 0 0 0 \n" + " 1495000: 1 1 0 0 0 0 4 0 0 0 0 0 0 0 0 0 \n" + " 1352000: 5 0 0 1 0 0 2 6 0 9 0 2 0 0 0 0 \n" + " 1209000: 14 1 0 0 0 0 0 0 17 0 0 5 0 1 3 0 \n" + " 1079000: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \n" + " 962000: 2 0 0 0 0 0 0 0 2 9 0 0 3 0 0 0 \n" + " 832000: 0 0 0 0 0 0 0 0 0 0 0 7 0 0 0 0 \n" + " 650000: 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \n" + " 468000: 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 \n" + " 325000: 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/topology/physical_package_id", + .size = 2, + .content = "1\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/topology/core_siblings_list", + .size = 4, + .content = "4-7\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/topology/core_siblings", + .size = 4, + .content = "0f0\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/topology/core_id", + .size = 2, + .content = "2\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/topology/thread_siblings_list", + .size = 2, + .content = "6\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/topology/thread_siblings", + .size = 4, + .content = "040\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/affected_cpus", + .size = 8, + .content = "4 5 6 7\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/cpuinfo_max_freq", + .size = 8, + .content = "2002000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/cpuinfo_min_freq", + .size = 7, + .content = "325000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/cpuinfo_transition_latency", + .size = 5, + .content = "1000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/related_cpus", + .size = 8, + .content = "4 5 6 7\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_available_frequencies", + .size = 124, + .content = + "2002000 1950000 1885000 1820000 1755000 1703000 1625000 1495000 1352000 1209000 1079000 962000 832000 650000 468000 325000 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_available_governors", + .size = 13, + .content = "interactive \n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_cur_freq", + .size = 8, + .content = "1495000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_driver", + .size = 11, + .content = "mt-cpufreq\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_governor", + .size = 12, + .content = "interactive\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_max_freq", + .size = 8, + .content = "2002000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_min_freq", + .size = 7, + .content = "325000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/time_in_state", + .size = 173, + .content = "2002000 2600\n" + "1950000 30\n" + "1885000 16\n" + "1820000 84\n" + "1755000 34\n" + "1703000 65\n" + "1625000 81\n" + "1495000 14\n" + "1352000 364\n" + "1209000 704\n" + "1079000 0\n" + "962000 71\n" + "832000 82\n" + "650000 2\n" + "468000 20\n" + "325000 15\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/total_trans", + .size = 4, + .content = "228\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/trans_table", + .size = 2941, + .content = + " From : To\n" + " : 2002000 1950000 1885000 1820000 1755000 1703000 1625000 1495000 1352000 1209000 1079000 962000 832000 650000 468000 325000 \n" + " 2002000: 0 0 1 7 2 1 2 0 7 23 0 3 1 0 0 1 \n" + " 1950000: 8 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 \n" + " 1885000: 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \n" + " 1820000: 5 2 3 0 0 2 2 0 0 1 0 0 0 0 0 0 \n" + " 1755000: 1 0 0 3 0 0 3 0 0 0 0 0 0 0 0 0 \n" + " 1703000: 1 0 1 2 2 0 1 0 0 0 0 0 0 0 0 0 \n" + " 1625000: 7 0 0 1 3 3 0 0 0 0 0 0 0 0 0 0 \n" + " 1495000: 1 1 0 0 0 1 4 0 0 0 0 0 0 0 0 0 \n" + " 1352000: 5 0 0 1 0 0 2 6 0 13 0 2 0 0 0 0 \n" + " 1209000: 15 1 0 0 0 0 0 1 20 0 0 6 0 1 4 0 \n" + " 1079000: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \n" + " 962000: 2 0 0 0 0 0 0 0 3 11 0 0 4 0 0 0 \n" + " 832000: 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 \n" + " 650000: 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \n" + " 468000: 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 \n" + " 325000: 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/topology/physical_package_id", + .size = 2, + .content = "1\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/topology/core_siblings_list", + .size = 4, + .content = "4-7\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/topology/core_siblings", + .size = 4, + .content = "0f0\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/topology/core_id", + .size = 2, + .content = "3\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/topology/thread_siblings_list", + .size = 2, + .content = "7\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/topology/thread_siblings", + .size = 4, + .content = "080\n", + }, + { + .path = "/sys/devices/system/cpu/cpu9/cpufreq/related_cpus", + .size = 4, + .content = "8 9\n", + }, + { + .path = "/sys/devices/system/cpu/cpu9/cpufreq/scaling_available_frequencies", + .size = 126, + .content = + "2522000 2392000 2327000 2262000 2223000 2158000 2093000 1885000 1677000 1495000 1378000 1131000 1001000 845000 676000 338000 \n", + }, + {NULL}, }; #ifdef __ANDROID__ @@ -3846,6 +3846,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.wfd.security.image", .value = "1", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/meizu-pro-7-plus.cc b/test/mock/meizu-pro-7-plus.cc index f64b1863..c81ef484 100644 --- a/test/mock/meizu-pro-7-plus.cc +++ b/test/mock/meizu-pro-7-plus.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(10, cpuinfo_get_processors_count()); @@ -397,8 +396,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("MediaTek MT6799", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "MediaTek MT6799", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -440,59 +441,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -647,8 +648,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -729,8 +732,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -797,8 +802,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/meizu-pro-7-plus.h b/test/mock/meizu-pro-7-plus.h index 73a9b203..e6fe14e9 100644 --- a/test/mock/meizu-pro-7-plus.h +++ b/test/mock/meizu-pro-7-plus.h @@ -1,1640 +1,1633 @@ -struct cpuinfo_mock_file filesystem[] = { - { - .path = "/proc/cpuinfo", - .size = 1662, - .content = - "processor\t: 0\n" - "Processor\t: AArch64 Processor rev 1 (aarch64)\n" - "model name\t: AArch64 Processor rev 1 (aarch64)\n" - "BogoMIPS\t: 26.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd04\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 1\n" - "Processor\t: AArch64 Processor rev 1 (aarch64)\n" - "model name\t: AArch64 Processor rev 1 (aarch64)\n" - "BogoMIPS\t: 26.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd04\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 2\n" - "Processor\t: AArch64 Processor rev 1 (aarch64)\n" - "model name\t: AArch64 Processor rev 1 (aarch64)\n" - "BogoMIPS\t: 26.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd04\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 3\n" - "Processor\t: AArch64 Processor rev 1 (aarch64)\n" - "model name\t: AArch64 Processor rev 1 (aarch64)\n" - "BogoMIPS\t: 26.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd04\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 4\n" - "Processor\t: AArch64 Processor rev 4 (aarch64)\n" - "model name\t: AArch64 Processor rev 4 (aarch64)\n" - "BogoMIPS\t: 26.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 8\n" - "Processor\t: AArch64 Processor rev 2 (aarch64)\n" - "model name\t: AArch64 Processor rev 2 (aarch64)\n" - "BogoMIPS\t: 26.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd09\n" - "CPU revision\t: 2\n" - "\n" - "Hardware\t: mt6799\n", - }, - { - .path = "/system/build.prop", - .size = 10516, - .content = - "\n" - "# begin build properties\n" - "# autogenerated by buildinfo.sh\n" - "ro.build.cta=noncta\n" - "ro.meizu.build.spt=0\n" - "ro.build.id=NRD90M\n" - "ro.build.mask.id=7.0-1501681220_stable\n" - "ro.build.inside.id=7.0-20170802214020\n" - "ro.build.version.incremental=1501682079\n" - "ro.build.version.sdk=24\n" - "ro.build.version.preview_sdk=0\n" - "ro.build.version.codename=REL\n" - "ro.build.version.all_codenames=REL\n" - "ro.build.version.release=7.0\n" - "ro.build.version.security_patch=2017-04-05\n" - "ro.build.version.base_os=\n" - "ro.build.date=Wed Aug 2 21:54:37 CST 2017\n" - "ro.build.date.utc=1501682077\n" - "ro.build.type=user\n" - "ro.build.user=flyme\n" - "ro.build.host=mz-builder-5\n" - "ro.build.tags=release-keys\n" - "ro.build.flavor=full_mz6799_6m_v2_2k_n-user\n" - "# ro.product.cpu.abi and ro.product.cpu.abi2 are obsolete,\n" - "# use ro.product.cpu.abilist instead.\n" - "ro.product.cpu.abi=arm64-v8a\n" - "ro.product.cpu.abilist=arm64-v8a,armeabi-v7a,armeabi\n" - "ro.product.cpu.abilist32=armeabi-v7a,armeabi\n" - "ro.product.cpu.abilist64=arm64-v8a\n" - "ro.product.locale=en-US\n" - "ro.wifi.channels=\n" - "ro.board.platform=mt6799\n" - "# ro.build.product is obsolete; use ro.product.device\n" - "# Do not try to parse description, fingerprint, or thumbprint\n" - "ro.build.characteristics=default\n" - "ro.product.brand=Meizu\n" - "ro.product.manufacturer=Meizu\n" - "ro.build.display.id=Flyme 6.1.2.2A\n" - "ro.product.model=PRO 7 Plus\n" - "ro.meizu.product.model=PRO7Plus\n" - "ro.product.name=meizu_PRO7Plus\n" - "ro.product.device=PRO7Plus\n" - "ro.product.board=PRO7Plus\n" - "# ro.build.product is obsolete; use ro.product.device\n" - "ro.build.product=PRO7Plus\n" - "# Do not try to parse ro.build.description or .fingerprint\n" - "ro.build.description=meizu_PRO7Plus-user 7.0 NRD90M 1501682079 release-keys\n" - "ro.build.fingerprint=Meizu/meizu_PRO7Plus/PRO7Plus:7.0/NRD90M/1501682079:user/release-keys\n" - "ro.meizu.project.id=m1793-6\n" - "ro.product.flyme.model=m1793\n" - "ro.flyme.published = true\n" - "# end build properties\n" - "ro.meizu.build.number=201708022204\n" - "#\n" - "# from device/mediatek/mz6799_6m_v2_2k_n/system.prop\n" - "#\n" - "#\n" - "# system.prop for generic sdk\n" - "#\n" - "\n" - "rild.libpath=mtk-ril.so\n" - "rild.libargs=-d /dev/ttyC0\n" - "\n" - "\n" - "# MTK, Infinity, 20090720 {\n" - "wifi.interface=wlan0\n" - "# MTK, Infinity, 20090720 }\n" - "\n" - "# MTK, mtk03034, 20101210 {\n" - "ro.mediatek.wlan.wsc=1\n" - "# MTK, mtk03034 20101210}\n" - "# MTK, mtk03034, 20110318 {\n" - "ro.mediatek.wlan.p2p=1\n" - "# MTK, mtk03034 20110318}\n" - "\n" - "# MTK, mtk03034, 20101213 {\n" - "mediatek.wlan.ctia=0\n" - "# MTK, mtk03034 20101213}\n" - "\n" - "\n" - "#\n" - "wifi.tethering.interface=ap0\n" - "#\n" - "\n" - "ro.opengles.version=196610\n" - "#ro.kernel.qemu=1\n" - "# ro.kernel.qemu.gles=0\n" - "\n" - "wifi.direct.interface=p2p0\n" - "#dalvik.vm.heapgrowthlimit=256m\n" - "#dalvik.vm.heapsize=512m\n" - "\n" - "# USB MTP WHQL\n" - "ro.sys.usb.mtp.whql.enable=0\n" - "\n" - "# Power off opt in IPO\n" - "sys.ipo.pwrdncap=2\n" - "\n" - "ro.sys.usb.storage.type=mtp\n" - "\n" - "# USB BICR function\n" - "ro.sys.usb.bicr=yes\n" - "\n" - "# USB Charge only function\n" - "ro.sys.usb.charging.only=yes\n" - "\n" - "# audio\n" - "ro.camera.sound.forced=0\n" - "ro.audio.silent=0\n" - "\n" - "ro.zygote.preload.enable=0\n" - "\n" - "# temporary enables NAV bar (soft keys)\n" - "qemu.hw.mainkeys=0\n" - "\n" - "ro.kernel.zio=38,108,105,16\n" - "#ro.kernel.qemu=1\n" - "#ro.kernel.qemu.gles=0\n" - "#ro.boot.selinux=disable\n" - "\n" - "# Disable dirty region for Mali\n" - "#debug.hwui.render_dirty_regions=false\n" - "\n" - "ro.sf.lcd_density=640\n" - "\n" - "# performance\n" - "ro.mtk_perf_simple_start_win=1\n" - "ro.mtk_perf_fast_start_win=1\n" - "ro.mtk_perf_response_time=1\n" - "\n" - "# meizu mobile name\n" - "ro.product.mobile.name=m1793\n" - "\n" - "#\n" - "# ADDITIONAL_BUILD_PROPERTIES\n" - "#\n" - "ro.hardware.hifi.support=true\n" - "ro.com.android.dateformat=MM-dd-yyyy\n" - "ro.config.ringtone=03_Flyme.ogg\n" - "ro.config.notification_sound=02_Reminder.ogg\n" - "ro.config.mms_sound=01_Triumph.ogg\n" - "ro.config.email_sound=02_Reminder.ogg\n" - "ro.config.calendar_sound=03_Doorbell.ogg\n" - "ro.config.alarm_alert=19_Waltz.ogg\n" - "log.tag.VibeTonz=ERROR\n" - "ro.carrier=unknown\n" - "ro.mediatek.chip_ver=S01\n" - "ro.mediatek.platform=MT6799\n" - "ro.telephony.sim.count=2\n" - "persist.radio.default.sim=0\n" - "persist.sys.mtk_app_aal_support=1\n" - "ril.specific.sm_cause=0\n" - "bgw.current3gband=0\n" - "ril.external.md=0\n" - "ro.mtk_cam_lomo_support=1\n" - "ro.sf.hwrotation=0\n" - "persist.radio.fd.counter=150\n" - "persist.radio.fd.off.counter=50\n" - "persist.radio.fd.r8.counter=150\n" - "persist.radio.fd.off.r8.counter=50\n" - "drm.service.enabled=true\n" - "fmradio.driver.enable=0\n" - "mtk.eccci.c2k=enabled\n" - "ril.first.md=1\n" - "ril.flightmode.poweroffMD=0\n" - "ril.telephony.mode=0\n" - "dalvik.vm.mtk-stack-trace-file=/data/anr/mtk_traces.txt\n" - "mediatek.wlan.chip=CONSYS_MT6799\n" - "mediatek.wlan.module.postfix=_consys_mt6799\n" - "ril.read.imsi=1\n" - "ril.radiooff.poweroffMD=0\n" - "ro.frp.pst=/dev/block/platform/bootdevice/by-name/frp\n" - "ro.mtk_protocol1_rat_config=C/Lf/Lt/W/T/G\n" - "ro.mtk_telephony_switch=1\n" - "ro.mediatek.version.branch=alps-trunk-n0.tk\n" - "ro.mediatek.version.release=alps-mp-n0.mp8\n" - "ro.mediatek.version.sdk=4\n" - "ro.num_md_protocol=2\n" - "persist.radio.multisim.config=dsds\n" - "ro.mtk_wapi_support=1\n" - "ro.mtk_bt_support=1\n" - "ro.mtk_wappush_support=1\n" - "ro.mtk_agps_app=1\n" - "ro.mtk_audio_tuning_tool_ver=V2.2\n" - "ro.mtk_wlan_support=1\n" - "ro.mtk_gps_support=1\n" - "ro.mtk_omacp_support=1\n" - "ro.mtk_search_db_support=1\n" - "ro.mtk_dialer_search_support=1\n" - "ro.mtk_dhcpv6c_wifi=1\n" - "ro.have_aacencode_feature=1\n" - "ro.mtk_fd_support=1\n" - "ro.mtk_oma_drm_support=1\n" - "ro.mtk_cta_drm_support=1\n" - "ro.mtk_widevine_drm_l3_support=1\n" - "ro.mtk_eap_sim_aka=1\n" - "ro.mtk_send_rr_support=1\n" - "ro.mtk_ufs_booting=1\n" - "ro.mtk_tetheringipv6_support=1\n" - "ro.mtk_c2k_support=1\n" - "persist.radio.flashless.fsm=0\n" - "persist.radio.flashless.fsm_cst=0\n" - "persist.radio.flashless.fsm_rw=0\n" - "ro.cdma.cfu.enable=*72\n" - "ro.cdma.cfu.disable=*720\n" - "ro.cdma.cfb.enable=*90\n" - "ro.cdma.cfb.disable=*900\n" - "ro.cdma.cfnr.enable=*92\n" - "ro.cdma.cfnr.disable=*920\n" - "ro.cdma.cfdf.enable=*68\n" - "ro.cdma.cfdf.disable=*680\n" - "ro.cdma.cfall.disable=*730\n" - "ro.cdma.cw.enable=*74\n" - "ro.cdma.cw.disable=*740\n" - "telephony.lteOnCdmaDevice=1\n" - "ro.telephony.default_network=10,10\n" - "ro.mtk_shared_sdcard=1\n" - "ro.mtk_enable_md1=1\n" - "ro.mtk_enable_md3=1\n" - "ro.mtk_afw_support=1\n" - "ro.meizu_soter_support=1\n" - "ro.mtk_aal_support=1\n" - "ro.mtk_dre30_support=1\n" - "ro.mtk_pq_support=3\n" - "ro.mtk_pq_color_mode=1\n" - "ro.mtk_blulight_def_support=1\n" - "ro.mtk_wfd_support=1\n" - "ro.mtk_wifi_mcc_support=1\n" - "ro.mtk_sim_hot_swap=1\n" - "ro.mtk_bip_scws=1\n" - "ro.mtk_world_phone_policy=0\n" - "ro.mtk_md_world_mode_support=1\n" - "ro.mtk_perfservice_support=1\n" - "ro.mtk_sim_hot_swap_common_slot=1\n" - "ro.mtk_cta_set=1\n" - "ro.mtk_devreg_app=1\n" - "ro.mtk_ct4greg_app=1\n" - "ro.mtk_zsdhdr_support=1\n" - "ro.mtk_cam_mfb_support=3\n" - "ro.mtk_cam_dualdenoise_support=1\n" - "ro.mtk_slow_motion_support=1\n" - "ro.mtk_cam_img_refocus_support=1\n" - "ro.mtk_lte_support=1\n" - "ro.mtk_rild_read_imsi=1\n" - "ro.sim_refresh_reset_by_modem=1\n" - "ro.mtk_external_sim_support=1\n" - "ro.mtk_external_sim_only_slots=0\n" - "ro.mtk_bg_power_saving_ui=1\n" - "ro.sim_me_lock_mode=0\n" - "ro.ap_info_monitor=0\n" - "ro.mtk_dual_mic_support=1\n" - "ro.mtk_is_tablet=0\n" - "ro.mtk_pow_perf_support=1\n" - "persist.mtk_nlp_switch_support=1\n" - "persist.mtk_ims_support=1\n" - "ro.mtk_multiple_ims_support=1\n" - "persist.mtk_volte_support=1\n" - "persist.mtk.volte.enable=1\n" - "persist.mtk_vilte_support=0\n" - "ro.mtk_vilte_ut_support=0\n" - "wfd.dummy.enable=1\n" - "wfd.iframesize.level=0\n" - "ro.mediatek.project.path=device/mediatek/mz6799_6m_v2_2k_n\n" - "ro.mtk_microtrust_tee_support=1\n" - "ro.flyme_softsim_mtee_enable=1\n" - "persist.mtk.wcn.combo.chipid=-1\n" - "persist.mtk.wcn.patch.version=-1\n" - "persist.mtk.wcn.dynamic.dump=0\n" - "service.wcn.driver.ready=no\n" - "service.wcn.coredump.mode=0\n" - "persist.mtk.connsys.poweron.ctl=0\n" - "ro.com.android.mobiledata=true\n" - "persist.radio.mobile.data=0,0\n" - "persist.radio.fourgOff=1\n" - "persist.meta.dumpdata=0\n" - "ro.mtk_deinterlace_support=1\n" - "ro.mtk_md_direct_tethering=1\n" - "ro.tethering.bridge.interface=mdbr0\n" - "sys.mtk_md_direct_tether_enable=true\n" - "persist.radio.mtk_dsbp_support=1\n" - "persist.radio.mtk_ps2_rat=W/G\n" - "persist.radio.mtk_ps3_rat=G\n" - "ro.boot.opt_c2k_lte_mode=2\n" - "ro.boot.opt_md1_support=12\n" - "ro.boot.opt_md3_support=2\n" - "ro.boot.opt_lte_support=1\n" - "ro.boot.opt_irat_support=1\n" - "persist.log.tag.DCT=D\n" - "ro.boot.opt_eccci_c2k=1\n" - "ro.boot.opt_using_default=1\n" - "ro.boot.opt_c2k_support=1\n" - "persist.log.tag.C2K_AT=I\n" - "persist.log.tag.C2K_RILC=I\n" - "persist.log.tag.C2K_ATConfig=I\n" - "persist.log.tag.LIBC2K_RIL=I\n" - "mtk.vdec.waitkeyframeforplay=1\n" - "ro.sys.sdcardfs=1\n" - "ro.mtk_res_switch=1\n" - "ro.mtk_hdr_video_support=1\n" - "ro.ksc5601_write=0\n" - "ro.email_support_ucs2=0\n" - "ro.ussd_ksc5601=0\n" - "persist.log.tag.CdmaMoSms=I\n" - "persist.log.tag.CdmaMtSms=I\n" - "ro.mtk_log_hide_gps=0\n" - "ro.mtk_modem_monitor_support=1\n" - "ro.have_aee_feature=1\n" - "persist.sf.dualdisplay=1\n" - "persist.perf.url.wxhb=http://wx.gtimg.com/hongbao/1701/hb.png\n" - "debug.hwui.render_dirty_regions=true\n" - "ro.hwui.disable_asset_atlas=true\n" - "dalvik.vm.heapgrowthlimit=256m\n" - "dalvik.vm.heapsize=512m\n" - "ro.mtk_benchmark_boost_tp=1\n" - "ro.hwui.texture_cache_size=120\n" - "ro.hwui.layer_cache_size=60\n" - "ro.hwui.fbo_cache_size=60\n" - "ro.hwui.path_cache_size=60\n" - "ro.hwui.r_buffer_cache_size=9\n" - "ro.hwui.texture_cache_flushrate=0.4\n" - "ro.hwui.gradient_cache_size=4\n" - "ro.hwui.drop_shadow_cache_size=8\n" - "ro.hwui.text_small_cache_width=1024\n" - "ro.hwui.text_small_cache_height=1024\n" - "ro.hwui.text_large_cache_width=2048\n" - "ro.hwui.text_large_cache_height=1024\n" - "ro.product.perf.config=M1793_base\n" - "persist.sf.startingwindow.gles=1\n" - "persist.sys.plugin.path=/data/data/|/data/user/\n" - "persist.sys.plugin.compiler=interpret-only\n" - "persist.sys.app.compiler=speed\n" - "persist.sys.app.thread=4\n" - "persist.sys.mstore.dl.num=1\n" - "persist.sf.ssr.controlbar=0\n" - "persist.sys.lock.charge=true\n" - "persist.sys.sf.camera=1\n" - "persist.perf.wm_static_blur=true\n" - "persist.thermalmanager.enable=true\n" - "persist.thermalmanager.path=/vendor/bin/thermal_manager\n" - "persist.thermalconfig.off=/vendor/etc/.tp/thermal.off.conf\n" - "persist.thermalconfig.powersave=/vendor/etc/.tp/thermal.low.conf\n" - "persist.thermalconfig.mid=/vendor/etc/.tp/thermal.mid.conf\n" - "persist.thermalconfig.high=/vendor/etc/.tp/thermal.high.conf\n" - "persist.mtkperfservice.enable=false\n" - "debug.choreographer.janklog=false\n" - "ro.meizu.ess.support=1\n" - "persist.sys.timezone=Asia/Shanghai\n" - "persist.sys.meizu.region=cn\n" - "persist.sys.meizu.codepage=gbk\n" - "ro.meizu.region.enable=true\n" - "ro.meizu.contactmsg.auth=false\n" - "ro.meizu.customize.pccw=false\n" - "ro.meizu.autorecorder=true\n" - "ro.meizu.visualvoicemail=true\n" - "ro.meizu.permanentkey=false\n" - "ro.meizu.sip.support=true\n" - "ro.meizu.voip.support=false\n" - "ro.meizu.setupwizard.flyme=true\n" - "ro.meizu.setupwizard.setlang=true\n" - "ro.meizu.security=false\n" - "sys.meizu.m35x.white.config=false\n" - "sys.meizu.white.config=false\n" - "persist.sys.log-main.enable=0\n" - "persist.sys.log-system.enable=0\n" - "persist.sys.log-events.enable=0\n" - "persist.sys.log-radio.enable=0\n" - "persist.sys.use.flyme.icon=true\n" - "ro.adb.secure=1\n" - "persist.sys.ui.hw=true\n" - "keyguard.no_require_sim=true\n" - "persist.sys.keyguard_intercept=true\n" - "persist.sys.disable_blur_view=true\n" - "persist.sys.static_blur_mode=false\n" - "ro.meizu.published.type=prd\n" - "ro.meizu.upgrade.config=false\n" - "qemu.hw.mainkeys=1\n" - "persist.sys.dalvik.vm.lib.2=libart.so\n" - "dalvik.vm.isa.arm64.variant=cortex-a53\n" - "dalvik.vm.isa.arm64.features=default\n" - "dalvik.vm.isa.arm.variant=cortex-a53\n" - "dalvik.vm.isa.arm.features=default\n" - "net.bt.name=Android\n" - "dalvik.vm.stack-trace-file=/data/anr/traces.txt\n" - "ro.expect.recovery_id=0x89560126b36ef1427a8df246bc8b28e54e31ce82000000000000000000000000\n", - }, - { - .path = "/sys/devices/system/cpu/kernel_max", - .size = 2, - .content = "9\n", - }, - { - .path = "/sys/devices/system/cpu/possible", - .size = 4, - .content = "0-9\n", - }, - { - .path = "/sys/devices/system/cpu/present", - .size = 4, - .content = "0-9\n", - }, - { - .path = "/sys/devices/system/cpu/online", - .size = 6, - .content = "0-4,8\n", - }, - { - .path = "/sys/devices/system/cpu/offline", - .size = 6, - .content = "5-7,9\n", - }, - { - .path = "/sys/devices/system/cpu/modalias", - .size = 66, - .content = "cpu:type:aarch64:feature:,0000,0001,0002,0003,0004,0005,0006,0007\n", - }, - { - .path = "/sys/devices/system/cpu/cpuidle/current_driver", - .size = 18, - .content = "mt67xx_v3_cpuidle\n", - }, - { - .path = "/sys/devices/system/cpu/cpuidle/current_governor_ro", - .size = 13, - .content = "mtk_governor\n", - }, - { - .path = "/sys/devices/system/cpu/cputopo/cpus_per_cluster", - .size = 39, - .content = - "cluster0: f\n" - "cluster1: f0\n" - "cluster2: 300\n", - }, - { - .path = "/sys/devices/system/cpu/cputopo/glbinfo", - .size = 87, - .content = - "big/little arch: yes\n" - "nr_cups: 10\n" - "nr_clusters: 3\n" - "cluster0: f\n" - "cluster1: f0\n" - "cluster2: 300\n", - }, - { - .path = "/sys/devices/system/cpu/cputopo/is_big_little", - .size = 2, - .content = "1\n", - }, - { - .path = "/sys/devices/system/cpu/cputopo/is_multi_cluster", - .size = 2, - .content = "1\n", - }, - { - .path = "/sys/devices/system/cpu/cputopo/nr_clusters", - .size = 2, - .content = "3\n", - }, - { - .path = "/sys/devices/system/cpu/cpu0/cpufreq/affected_cpus", - .size = 6, - .content = "0 1 2\n", - }, - { - .path = "/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq", - .size = 8, - .content = "1898000\n", - }, - { - .path = "/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_min_freq", - .size = 7, - .content = "249000\n", - }, - { - .path = "/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_transition_latency", - .size = 5, - .content = "1000\n", - }, - { - .path = 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.path = "/sys/devices/system/cpu/cpu0/topology/thread_siblings_list", - .size = 2, - .content = "0\n", - }, - { - .path = "/sys/devices/system/cpu/cpu0/topology/thread_siblings", - .size = 4, - .content = "001\n", - }, - { - .path = "/sys/devices/system/cpu/cpu1/cpufreq/affected_cpus", - .size = 8, - .content = "0 1 2 3\n", - }, - { - .path = "/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_max_freq", - .size = 8, - .content = "1898000\n", - }, - { - .path = "/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_min_freq", - .size = 7, - .content = "249000\n", - }, - { - .path = "/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_transition_latency", - .size = 5, - .content = "1000\n", - }, - { - .path = "/sys/devices/system/cpu/cpu1/cpufreq/related_cpus", - .size = 8, - .content = "0 1 2 3\n", - }, - { - .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_frequencies", - .size = 125, - .content = "1898000 1863000 1828000 1769000 1678000 1604000 1512000 1421000 1347000 1237000 1145000 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"/sys/devices/system/cpu/cpu9/cpufreq/stats/total_trans", - .size = 4, - .content = "474\n", - }, - { - .path = "/sys/devices/system/cpu/cpu9/cpufreq/stats/trans_table", - .size = 2941, - .content = - " From : To\n" - " : 2600000 2452000 2408000 2318000 2173000 2057000 1911000 1766000 1649000 1475000 1329000 1169000 974000 771000 551000 328000 \n" - " 2600000: 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 1 \n" - " 2452000: 1 0 5 3 0 1 1 0 0 0 1 0 0 2 1 0 \n" - " 2408000: 1 4 0 6 3 1 3 0 0 0 1 0 0 0 0 0 \n" - " 2318000: 0 4 3 0 5 5 2 1 1 0 2 0 0 0 0 0 \n" - " 2173000: 0 3 7 5 0 4 0 0 2 3 1 1 2 0 0 0 \n" - " 2057000: 0 2 2 4 5 0 5 6 2 0 0 0 0 0 0 0 \n" - " 1911000: 0 1 1 4 10 11 0 2 2 2 4 1 1 4 0 0 \n" - " 1766000: 1 0 0 0 1 2 8 0 4 2 2 2 0 0 0 0 \n" - " 1649000: 1 0 0 1 0 1 7 7 0 5 2 3 0 1 0 0 \n" - " 1475000: 0 0 0 0 3 1 6 3 9 0 9 3 0 2 0 0 \n" - " 1329000: 0 1 0 0 1 0 6 1 2 12 0 6 1 1 0 0 \n" - " 1169000: 0 0 0 0 0 0 0 0 6 7 4 0 9 4 1 1 \n" - " 974000: 0 0 0 0 0 0 2 2 0 2 2 8 0 28 2 0 \n" - " 771000: 0 0 1 0 0 0 2 0 0 3 1 4 32 0 16 1 \n" - " 551000: 0 0 0 0 0 0 0 0 0 0 0 2 1 17 0 19 \n" - " 328000: 0 0 0 0 0 0 0 0 0 0 1 1 0 2 18 0 \n", - }, - { NULL }, +struct + cpuinfo_mock_file + filesystem + [] = + { + { + .path = "/proc/cpuinfo", + .size = 1662, + .content = "processor\t: 0\n" + "Processor\t: AArch64 Processor rev 1 (aarch64)\n" + "model name\t: AArch64 Processor rev 1 (aarch64)\n" + "BogoMIPS\t: 26.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd04\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 1\n" + "Processor\t: AArch64 Processor rev 1 (aarch64)\n" + "model name\t: AArch64 Processor rev 1 (aarch64)\n" + "BogoMIPS\t: 26.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd04\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 2\n" + "Processor\t: AArch64 Processor rev 1 (aarch64)\n" + "model name\t: AArch64 Processor rev 1 (aarch64)\n" + "BogoMIPS\t: 26.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd04\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 3\n" + "Processor\t: AArch64 Processor rev 1 (aarch64)\n" + "model name\t: AArch64 Processor rev 1 (aarch64)\n" + "BogoMIPS\t: 26.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd04\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 4\n" + "Processor\t: AArch64 Processor rev 4 (aarch64)\n" + "model name\t: AArch64 Processor rev 4 (aarch64)\n" + "BogoMIPS\t: 26.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 8\n" + "Processor\t: AArch64 Processor rev 2 (aarch64)\n" + "model name\t: AArch64 Processor rev 2 (aarch64)\n" + "BogoMIPS\t: 26.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd09\n" + "CPU revision\t: 2\n" + "\n" + "Hardware\t: mt6799\n", + }, + { + .path = "/system/build.prop", + .size = 10516, + .content = + "\n" + "# begin build properties\n" + "# autogenerated by buildinfo.sh\n" + "ro.build.cta=noncta\n" + "ro.meizu.build.spt=0\n" + "ro.build.id=NRD90M\n" + "ro.build.mask.id=7.0-1501681220_stable\n" + "ro.build.inside.id=7.0-20170802214020\n" + "ro.build.version.incremental=1501682079\n" + "ro.build.version.sdk=24\n" + "ro.build.version.preview_sdk=0\n" + "ro.build.version.codename=REL\n" + "ro.build.version.all_codenames=REL\n" + "ro.build.version.release=7.0\n" + "ro.build.version.security_patch=2017-04-05\n" + "ro.build.version.base_os=\n" + "ro.build.date=Wed Aug 2 21:54:37 CST 2017\n" + "ro.build.date.utc=1501682077\n" + "ro.build.type=user\n" + "ro.build.user=flyme\n" + "ro.build.host=mz-builder-5\n" + "ro.build.tags=release-keys\n" + "ro.build.flavor=full_mz6799_6m_v2_2k_n-user\n" + "# ro.product.cpu.abi and ro.product.cpu.abi2 are obsolete,\n" + "# use ro.product.cpu.abilist instead.\n" + "ro.product.cpu.abi=arm64-v8a\n" + "ro.product.cpu.abilist=arm64-v8a,armeabi-v7a,armeabi\n" + "ro.product.cpu.abilist32=armeabi-v7a,armeabi\n" + "ro.product.cpu.abilist64=arm64-v8a\n" + "ro.product.locale=en-US\n" + "ro.wifi.channels=\n" + "ro.board.platform=mt6799\n" + "# ro.build.product is obsolete; use ro.product.device\n" + "# Do not try to parse description, fingerprint, or thumbprint\n" + "ro.build.characteristics=default\n" + "ro.product.brand=Meizu\n" + "ro.product.manufacturer=Meizu\n" + "ro.build.display.id=Flyme 6.1.2.2A\n" + "ro.product.model=PRO 7 Plus\n" + "ro.meizu.product.model=PRO7Plus\n" + "ro.product.name=meizu_PRO7Plus\n" + "ro.product.device=PRO7Plus\n" + "ro.product.board=PRO7Plus\n" + "# ro.build.product is obsolete; use ro.product.device\n" + "ro.build.product=PRO7Plus\n" + "# Do not try to parse ro.build.description or .fingerprint\n" + "ro.build.description=meizu_PRO7Plus-user 7.0 NRD90M 1501682079 release-keys\n" + "ro.build.fingerprint=Meizu/meizu_PRO7Plus/PRO7Plus:7.0/NRD90M/1501682079:user/release-keys\n" + "ro.meizu.project.id=m1793-6\n" + "ro.product.flyme.model=m1793\n" + "ro.flyme.published = true\n" + "# end build properties\n" + "ro.meizu.build.number=201708022204\n" + "#\n" + "# from device/mediatek/mz6799_6m_v2_2k_n/system.prop\n" + "#\n" + "#\n" + "# system.prop for generic sdk\n" + "#\n" + "\n" + "rild.libpath=mtk-ril.so\n" + "rild.libargs=-d /dev/ttyC0\n" + "\n" + "\n" + "# MTK, Infinity, 20090720 {\n" + "wifi.interface=wlan0\n" + "# MTK, Infinity, 20090720 }\n" + "\n" + "# MTK, mtk03034, 20101210 {\n" + "ro.mediatek.wlan.wsc=1\n" + "# MTK, mtk03034 20101210}\n" + "# MTK, mtk03034, 20110318 {\n" + "ro.mediatek.wlan.p2p=1\n" + "# MTK, mtk03034 20110318}\n" + "\n" + "# MTK, mtk03034, 20101213 {\n" + "mediatek.wlan.ctia=0\n" + "# MTK, mtk03034 20101213}\n" + "\n" + "\n" + "#\n" + "wifi.tethering.interface=ap0\n" + "#\n" + "\n" + "ro.opengles.version=196610\n" + "#ro.kernel.qemu=1\n" + "# ro.kernel.qemu.gles=0\n" + "\n" + "wifi.direct.interface=p2p0\n" + "#dalvik.vm.heapgrowthlimit=256m\n" + "#dalvik.vm.heapsize=512m\n" + "\n" + "# USB MTP WHQL\n" + "ro.sys.usb.mtp.whql.enable=0\n" + "\n" + "# Power off opt in IPO\n" + "sys.ipo.pwrdncap=2\n" + "\n" + "ro.sys.usb.storage.type=mtp\n" + "\n" + "# USB BICR function\n" + "ro.sys.usb.bicr=yes\n" + "\n" + "# USB Charge only function\n" + "ro.sys.usb.charging.only=yes\n" + "\n" + "# audio\n" + "ro.camera.sound.forced=0\n" + "ro.audio.silent=0\n" + "\n" + "ro.zygote.preload.enable=0\n" + "\n" + "# temporary enables NAV bar (soft keys)\n" + "qemu.hw.mainkeys=0\n" + "\n" + "ro.kernel.zio=38,108,105,16\n" + "#ro.kernel.qemu=1\n" + "#ro.kernel.qemu.gles=0\n" + "#ro.boot.selinux=disable\n" + "\n" + "# Disable dirty region for Mali\n" + "#debug.hwui.render_dirty_regions=false\n" + "\n" + "ro.sf.lcd_density=640\n" + "\n" + "# performance\n" + "ro.mtk_perf_simple_start_win=1\n" + "ro.mtk_perf_fast_start_win=1\n" + "ro.mtk_perf_response_time=1\n" + "\n" + "# meizu mobile name\n" + "ro.product.mobile.name=m1793\n" + "\n" + "#\n" + "# ADDITIONAL_BUILD_PROPERTIES\n" + "#\n" + "ro.hardware.hifi.support=true\n" + "ro.com.android.dateformat=MM-dd-yyyy\n" + "ro.config.ringtone=03_Flyme.ogg\n" + "ro.config.notification_sound=02_Reminder.ogg\n" + "ro.config.mms_sound=01_Triumph.ogg\n" + "ro.config.email_sound=02_Reminder.ogg\n" + "ro.config.calendar_sound=03_Doorbell.ogg\n" + "ro.config.alarm_alert=19_Waltz.ogg\n" + "log.tag.VibeTonz=ERROR\n" + "ro.carrier=unknown\n" + "ro.mediatek.chip_ver=S01\n" + "ro.mediatek.platform=MT6799\n" + "ro.telephony.sim.count=2\n" + "persist.radio.default.sim=0\n" + "persist.sys.mtk_app_aal_support=1\n" + "ril.specific.sm_cause=0\n" + "bgw.current3gband=0\n" + "ril.external.md=0\n" + "ro.mtk_cam_lomo_support=1\n" + "ro.sf.hwrotation=0\n" + "persist.radio.fd.counter=150\n" + "persist.radio.fd.off.counter=50\n" + "persist.radio.fd.r8.counter=150\n" + "persist.radio.fd.off.r8.counter=50\n" + "drm.service.enabled=true\n" + "fmradio.driver.enable=0\n" + "mtk.eccci.c2k=enabled\n" + "ril.first.md=1\n" + "ril.flightmode.poweroffMD=0\n" + "ril.telephony.mode=0\n" + "dalvik.vm.mtk-stack-trace-file=/data/anr/mtk_traces.txt\n" + "mediatek.wlan.chip=CONSYS_MT6799\n" + "mediatek.wlan.module.postfix=_consys_mt6799\n" + "ril.read.imsi=1\n" + "ril.radiooff.poweroffMD=0\n" + "ro.frp.pst=/dev/block/platform/bootdevice/by-name/frp\n" + "ro.mtk_protocol1_rat_config=C/Lf/Lt/W/T/G\n" + "ro.mtk_telephony_switch=1\n" + "ro.mediatek.version.branch=alps-trunk-n0.tk\n" + "ro.mediatek.version.release=alps-mp-n0.mp8\n" + "ro.mediatek.version.sdk=4\n" + "ro.num_md_protocol=2\n" + "persist.radio.multisim.config=dsds\n" + "ro.mtk_wapi_support=1\n" + "ro.mtk_bt_support=1\n" + "ro.mtk_wappush_support=1\n" + "ro.mtk_agps_app=1\n" + "ro.mtk_audio_tuning_tool_ver=V2.2\n" + "ro.mtk_wlan_support=1\n" + "ro.mtk_gps_support=1\n" + "ro.mtk_omacp_support=1\n" + "ro.mtk_search_db_support=1\n" + "ro.mtk_dialer_search_support=1\n" + "ro.mtk_dhcpv6c_wifi=1\n" + "ro.have_aacencode_feature=1\n" + "ro.mtk_fd_support=1\n" + "ro.mtk_oma_drm_support=1\n" + "ro.mtk_cta_drm_support=1\n" + "ro.mtk_widevine_drm_l3_support=1\n" + "ro.mtk_eap_sim_aka=1\n" + "ro.mtk_send_rr_support=1\n" + "ro.mtk_ufs_booting=1\n" + "ro.mtk_tetheringipv6_support=1\n" + "ro.mtk_c2k_support=1\n" + "persist.radio.flashless.fsm=0\n" + "persist.radio.flashless.fsm_cst=0\n" + "persist.radio.flashless.fsm_rw=0\n" + "ro.cdma.cfu.enable=*72\n" + "ro.cdma.cfu.disable=*720\n" + "ro.cdma.cfb.enable=*90\n" + "ro.cdma.cfb.disable=*900\n" + "ro.cdma.cfnr.enable=*92\n" + "ro.cdma.cfnr.disable=*920\n" + "ro.cdma.cfdf.enable=*68\n" + "ro.cdma.cfdf.disable=*680\n" + "ro.cdma.cfall.disable=*730\n" + "ro.cdma.cw.enable=*74\n" + "ro.cdma.cw.disable=*740\n" + "telephony.lteOnCdmaDevice=1\n" + "ro.telephony.default_network=10,10\n" + "ro.mtk_shared_sdcard=1\n" + "ro.mtk_enable_md1=1\n" + "ro.mtk_enable_md3=1\n" + "ro.mtk_afw_support=1\n" + "ro.meizu_soter_support=1\n" + "ro.mtk_aal_support=1\n" + "ro.mtk_dre30_support=1\n" + "ro.mtk_pq_support=3\n" + "ro.mtk_pq_color_mode=1\n" + "ro.mtk_blulight_def_support=1\n" + "ro.mtk_wfd_support=1\n" + "ro.mtk_wifi_mcc_support=1\n" + "ro.mtk_sim_hot_swap=1\n" + "ro.mtk_bip_scws=1\n" + "ro.mtk_world_phone_policy=0\n" + "ro.mtk_md_world_mode_support=1\n" + "ro.mtk_perfservice_support=1\n" + "ro.mtk_sim_hot_swap_common_slot=1\n" + "ro.mtk_cta_set=1\n" + "ro.mtk_devreg_app=1\n" + "ro.mtk_ct4greg_app=1\n" + "ro.mtk_zsdhdr_support=1\n" + "ro.mtk_cam_mfb_support=3\n" + "ro.mtk_cam_dualdenoise_support=1\n" + "ro.mtk_slow_motion_support=1\n" + "ro.mtk_cam_img_refocus_support=1\n" + "ro.mtk_lte_support=1\n" + "ro.mtk_rild_read_imsi=1\n" + "ro.sim_refresh_reset_by_modem=1\n" + "ro.mtk_external_sim_support=1\n" + "ro.mtk_external_sim_only_slots=0\n" + "ro.mtk_bg_power_saving_ui=1\n" + "ro.sim_me_lock_mode=0\n" + "ro.ap_info_monitor=0\n" + "ro.mtk_dual_mic_support=1\n" + "ro.mtk_is_tablet=0\n" + "ro.mtk_pow_perf_support=1\n" + "persist.mtk_nlp_switch_support=1\n" + "persist.mtk_ims_support=1\n" + "ro.mtk_multiple_ims_support=1\n" + "persist.mtk_volte_support=1\n" + "persist.mtk.volte.enable=1\n" + "persist.mtk_vilte_support=0\n" + "ro.mtk_vilte_ut_support=0\n" + "wfd.dummy.enable=1\n" + "wfd.iframesize.level=0\n" + "ro.mediatek.project.path=device/mediatek/mz6799_6m_v2_2k_n\n" + "ro.mtk_microtrust_tee_support=1\n" + "ro.flyme_softsim_mtee_enable=1\n" + "persist.mtk.wcn.combo.chipid=-1\n" + "persist.mtk.wcn.patch.version=-1\n" + "persist.mtk.wcn.dynamic.dump=0\n" + "service.wcn.driver.ready=no\n" + "service.wcn.coredump.mode=0\n" + "persist.mtk.connsys.poweron.ctl=0\n" + "ro.com.android.mobiledata=true\n" + "persist.radio.mobile.data=0,0\n" + "persist.radio.fourgOff=1\n" + "persist.meta.dumpdata=0\n" + "ro.mtk_deinterlace_support=1\n" + "ro.mtk_md_direct_tethering=1\n" + "ro.tethering.bridge.interface=mdbr0\n" + "sys.mtk_md_direct_tether_enable=true\n" + "persist.radio.mtk_dsbp_support=1\n" + "persist.radio.mtk_ps2_rat=W/G\n" + "persist.radio.mtk_ps3_rat=G\n" + "ro.boot.opt_c2k_lte_mode=2\n" + "ro.boot.opt_md1_support=12\n" + "ro.boot.opt_md3_support=2\n" + "ro.boot.opt_lte_support=1\n" + "ro.boot.opt_irat_support=1\n" + "persist.log.tag.DCT=D\n" + "ro.boot.opt_eccci_c2k=1\n" + "ro.boot.opt_using_default=1\n" + "ro.boot.opt_c2k_support=1\n" + "persist.log.tag.C2K_AT=I\n" + "persist.log.tag.C2K_RILC=I\n" + "persist.log.tag.C2K_ATConfig=I\n" + "persist.log.tag.LIBC2K_RIL=I\n" + "mtk.vdec.waitkeyframeforplay=1\n" + "ro.sys.sdcardfs=1\n" + "ro.mtk_res_switch=1\n" + "ro.mtk_hdr_video_support=1\n" + "ro.ksc5601_write=0\n" + "ro.email_support_ucs2=0\n" + "ro.ussd_ksc5601=0\n" + "persist.log.tag.CdmaMoSms=I\n" + "persist.log.tag.CdmaMtSms=I\n" + "ro.mtk_log_hide_gps=0\n" + "ro.mtk_modem_monitor_support=1\n" + "ro.have_aee_feature=1\n" + "persist.sf.dualdisplay=1\n" + "persist.perf.url.wxhb=http://wx.gtimg.com/hongbao/1701/hb.png\n" + "debug.hwui.render_dirty_regions=true\n" + "ro.hwui.disable_asset_atlas=true\n" + "dalvik.vm.heapgrowthlimit=256m\n" + "dalvik.vm.heapsize=512m\n" + "ro.mtk_benchmark_boost_tp=1\n" + "ro.hwui.texture_cache_size=120\n" + "ro.hwui.layer_cache_size=60\n" + "ro.hwui.fbo_cache_size=60\n" + "ro.hwui.path_cache_size=60\n" + "ro.hwui.r_buffer_cache_size=9\n" + "ro.hwui.texture_cache_flushrate=0.4\n" + "ro.hwui.gradient_cache_size=4\n" + "ro.hwui.drop_shadow_cache_size=8\n" + "ro.hwui.text_small_cache_width=1024\n" + "ro.hwui.text_small_cache_height=1024\n" + "ro.hwui.text_large_cache_width=2048\n" + "ro.hwui.text_large_cache_height=1024\n" + "ro.product.perf.config=M1793_base\n" + "persist.sf.startingwindow.gles=1\n" + "persist.sys.plugin.path=/data/data/|/data/user/\n" + "persist.sys.plugin.compiler=interpret-only\n" + "persist.sys.app.compiler=speed\n" + "persist.sys.app.thread=4\n" + "persist.sys.mstore.dl.num=1\n" + "persist.sf.ssr.controlbar=0\n" + "persist.sys.lock.charge=true\n" + "persist.sys.sf.camera=1\n" + "persist.perf.wm_static_blur=true\n" + "persist.thermalmanager.enable=true\n" + "persist.thermalmanager.path=/vendor/bin/thermal_manager\n" + "persist.thermalconfig.off=/vendor/etc/.tp/thermal.off.conf\n" + "persist.thermalconfig.powersave=/vendor/etc/.tp/thermal.low.conf\n" + "persist.thermalconfig.mid=/vendor/etc/.tp/thermal.mid.conf\n" + "persist.thermalconfig.high=/vendor/etc/.tp/thermal.high.conf\n" + "persist.mtkperfservice.enable=false\n" + "debug.choreographer.janklog=false\n" + "ro.meizu.ess.support=1\n" + "persist.sys.timezone=Asia/Shanghai\n" + "persist.sys.meizu.region=cn\n" + "persist.sys.meizu.codepage=gbk\n" + "ro.meizu.region.enable=true\n" + "ro.meizu.contactmsg.auth=false\n" + "ro.meizu.customize.pccw=false\n" + "ro.meizu.autorecorder=true\n" + "ro.meizu.visualvoicemail=true\n" + "ro.meizu.permanentkey=false\n" + "ro.meizu.sip.support=true\n" + "ro.meizu.voip.support=false\n" + "ro.meizu.setupwizard.flyme=true\n" + "ro.meizu.setupwizard.setlang=true\n" + "ro.meizu.security=false\n" + "sys.meizu.m35x.white.config=false\n" + "sys.meizu.white.config=false\n" + "persist.sys.log-main.enable=0\n" + "persist.sys.log-system.enable=0\n" + "persist.sys.log-events.enable=0\n" + "persist.sys.log-radio.enable=0\n" + "persist.sys.use.flyme.icon=true\n" + "ro.adb.secure=1\n" + "persist.sys.ui.hw=true\n" + "keyguard.no_require_sim=true\n" + "persist.sys.keyguard_intercept=true\n" + "persist.sys.disable_blur_view=true\n" + "persist.sys.static_blur_mode=false\n" + "ro.meizu.published.type=prd\n" + "ro.meizu.upgrade.config=false\n" + "qemu.hw.mainkeys=1\n" + "persist.sys.dalvik.vm.lib.2=libart.so\n" + "dalvik.vm.isa.arm64.variant=cortex-a53\n" + "dalvik.vm.isa.arm64.features=default\n" + "dalvik.vm.isa.arm.variant=cortex-a53\n" + "dalvik.vm.isa.arm.features=default\n" + "net.bt.name=Android\n" + "dalvik.vm.stack-trace-file=/data/anr/traces.txt\n" + "ro.expect.recovery_id=0x89560126b36ef1427a8df246bc8b28e54e31ce82000000000000000000000000\n", + }, + { + .path = "/sys/devices/system/cpu/kernel_max", + .size = 2, + .content = "9\n", + }, + { + .path = "/sys/devices/system/cpu/possible", + .size = 4, + .content = "0-9\n", + }, + { + .path = "/sys/devices/system/cpu/present", + .size = 4, + .content = "0-9\n", + }, + { + .path = "/sys/devices/system/cpu/online", + .size = 6, + .content = "0-4,8\n", + }, + { + .path = "/sys/devices/system/cpu/offline", + .size = 6, + .content = "5-7,9\n", + }, + { + .path = "/sys/devices/system/cpu/modalias", + .size = 66, + .content = + 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5 6 7\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_available_governors", + .size = 19, + .content = "sched interactive \n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_cur_freq", + .size = 7, + .content = "687000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_driver", + .size = 11, + .content = "mt-cpufreq\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_governor", + .size = 12, + .content = "interactive\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_max_freq", + .size = 8, + .content = "2197000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_min_freq", + .size = 7, + .content = "687000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/time_in_state", + .size = 185, + .content = "2197000 1085\n" + "2157000 64\n" + "2117000 87\n" + "2040000 100\n" + "1917000 170\n" + "1818000 122\n" + "1694000 77\n" + "1571000 34\n" + "1472000 95\n" + "1324000 100\n" + "1200000 549\n" + "1053000 370\n" + "873000 236\n" + "687000 2183\n" + "484000 144\n" + "279000 450\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/total_trans", + .size = 4, + .content = "582\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/trans_table", + .size = 2941, + .content = + " From : To\n" + " : 2197000 2157000 2117000 2040000 1917000 1818000 1694000 1571000 1472000 1324000 1200000 1053000 873000 687000 484000 279000 \n" + " 2197000: 0 8 5 4 1 3 2 0 0 1 3 1 0 0 0 0 \n" + " 2157000: 8 0 3 4 1 2 0 2 0 0 0 0 0 1 0 0 \n" + " 2117000: 8 3 0 3 2 2 2 0 2 0 0 0 0 0 1 0 \n" + " 2040000: 5 2 7 0 5 1 3 1 3 1 0 0 0 0 0 2 \n" + " 1917000: 2 4 4 7 0 4 1 3 1 2 4 0 0 0 0 0 \n" + " 1818000: 2 3 3 7 7 0 2 0 2 0 2 0 0 1 0 0 \n" + " 1694000: 1 0 0 1 2 8 0 3 2 2 1 0 0 0 0 0 \n" + " 1571000: 0 0 0 0 2 5 3 0 2 1 1 0 0 1 0 0 \n" + " 1472000: 0 0 1 3 1 4 1 5 0 4 4 4 2 0 0 0 \n" + " 1324000: 0 1 0 0 4 0 1 0 12 0 6 0 1 0 0 1 \n" + " 1200000: 2 0 0 0 6 0 2 0 3 9 0 18 3 7 0 0 \n" + " 1053000: 0 0 0 0 0 0 1 0 1 4 16 0 23 10 2 1 \n" + " 873000: 0 0 0 1 0 0 0 0 0 0 6 19 0 35 3 6 \n" + " 687000: 0 0 0 0 0 0 1 1 0 1 5 14 33 0 15 6 \n" + " 484000: 0 0 0 0 0 0 0 0 0 1 2 0 6 12 0 19 \n" + " 279000: 0 0 0 0 1 0 1 0 0 0 0 2 2 10 19 0 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/affected_cpus", + .size = 1, + .content = "\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/cpuinfo_max_freq", + .size = 8, + .content = "2197000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/cpuinfo_min_freq", + .size = 7, + .content = "279000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/cpuinfo_transition_latency", + .size = 5, + .content = "1000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/related_cpus", + .size = 8, + .content = "4 5 6 7\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_available_governors", + .size = 19, + .content = "sched interactive \n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_cur_freq", + .size = 7, + .content = "687000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_driver", + .size = 11, + .content = "mt-cpufreq\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_governor", + .size = 12, + .content = "interactive\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_max_freq", + .size = 8, + .content = "2197000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_min_freq", + .size = 7, + .content = "687000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/time_in_state", + .size = 185, + .content = "2197000 1085\n" + "2157000 64\n" + "2117000 87\n" + "2040000 100\n" + "1917000 170\n" + "1818000 122\n" + "1694000 77\n" + "1571000 34\n" + "1472000 95\n" + "1324000 100\n" + "1200000 549\n" + "1053000 370\n" + "873000 236\n" + "687000 3187\n" + "484000 144\n" + "279000 450\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/total_trans", + .size = 4, + .content = "582\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/trans_table", + .size = 2941, + .content = + " From : To\n" + " : 2197000 2157000 2117000 2040000 1917000 1818000 1694000 1571000 1472000 1324000 1200000 1053000 873000 687000 484000 279000 \n" + " 2197000: 0 8 5 4 1 3 2 0 0 1 3 1 0 0 0 0 \n" + " 2157000: 8 0 3 4 1 2 0 2 0 0 0 0 0 1 0 0 \n" + " 2117000: 8 3 0 3 2 2 2 0 2 0 0 0 0 0 1 0 \n" + " 2040000: 5 2 7 0 5 1 3 1 3 1 0 0 0 0 0 2 \n" + " 1917000: 2 4 4 7 0 4 1 3 1 2 4 0 0 0 0 0 \n" + " 1818000: 2 3 3 7 7 0 2 0 2 0 2 0 0 1 0 0 \n" + " 1694000: 1 0 0 1 2 8 0 3 2 2 1 0 0 0 0 0 \n" + " 1571000: 0 0 0 0 2 5 3 0 2 1 1 0 0 1 0 0 \n" + " 1472000: 0 0 1 3 1 4 1 5 0 4 4 4 2 0 0 0 \n" + " 1324000: 0 1 0 0 4 0 1 0 12 0 6 0 1 0 0 1 \n" + " 1200000: 2 0 0 0 6 0 2 0 3 9 0 18 3 7 0 0 \n" + " 1053000: 0 0 0 0 0 0 1 0 1 4 16 0 23 10 2 1 \n" + " 873000: 0 0 0 1 0 0 0 0 0 0 6 19 0 35 3 6 \n" + " 687000: 0 0 0 0 0 0 1 1 0 1 5 14 33 0 15 6 \n" + " 484000: 0 0 0 0 0 0 0 0 0 1 2 0 6 12 0 19 \n" + " 279000: 0 0 0 0 1 0 1 0 0 0 0 2 2 10 19 0 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/affected_cpus", + .size = 1, + .content = "\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/cpuinfo_max_freq", + .size = 8, + .content = "2197000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/cpuinfo_min_freq", + .size = 7, + .content = "279000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/cpuinfo_transition_latency", + .size = 5, + .content = "1000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/related_cpus", + .size = 8, + .content = "4 5 6 7\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_available_governors", + .size = 19, + .content = "sched interactive \n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_cur_freq", + .size = 7, + .content = "687000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_driver", + .size = 11, + .content = "mt-cpufreq\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_governor", + .size = 12, + .content = "interactive\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_max_freq", + .size = 8, + .content = "2197000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_min_freq", + .size = 7, + .content = "687000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/time_in_state", + .size = 185, + .content = "2197000 1085\n" + "2157000 64\n" + "2117000 87\n" + "2040000 100\n" + "1917000 170\n" + "1818000 122\n" + "1694000 77\n" + "1571000 34\n" + "1472000 95\n" + "1324000 100\n" + "1200000 549\n" + "1053000 370\n" + "873000 236\n" + "687000 3449\n" + "484000 144\n" + "279000 450\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/total_trans", + .size = 4, + .content = "582\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/trans_table", + .size = 2941, + .content = " From : To\n" + " : 2197000 2157000 2117000 2040000 1917000 1818000 1694000 1571000 1472000 1324000 1200000 1053000 873000 687000 484000 279000 \n" + " 2197000: 0 8 5 4 1 3 2 0 0 1 3 1 0 0 0 0 \n" + " 2157000: 8 0 3 4 1 2 0 2 0 0 0 0 0 1 0 0 \n" + " 2117000: 8 3 0 3 2 2 2 0 2 0 0 0 0 0 1 0 \n" + " 2040000: 5 2 7 0 5 1 3 1 3 1 0 0 0 0 0 2 \n" + " 1917000: 2 4 4 7 0 4 1 3 1 2 4 0 0 0 0 0 \n" + " 1818000: 2 3 3 7 7 0 2 0 2 0 2 0 0 1 0 0 \n" + " 1694000: 1 0 0 1 2 8 0 3 2 2 1 0 0 0 0 0 \n" + " 1571000: 0 0 0 0 2 5 3 0 2 1 1 0 0 1 0 0 \n" + " 1472000: 0 0 1 3 1 4 1 5 0 4 4 4 2 0 0 0 \n" + " 1324000: 0 1 0 0 4 0 1 0 12 0 6 0 1 0 0 1 \n" + " 1200000: 2 0 0 0 6 0 2 0 3 9 0 18 3 7 0 0 \n" + " 1053000: 0 0 0 0 0 0 1 0 1 4 16 0 23 10 2 1 \n" + " 873000: 0 0 0 1 0 0 0 0 0 0 6 19 0 35 3 6 \n" + " 687000: 0 0 0 0 0 0 1 1 0 1 5 14 33 0 15 6 \n" + " 484000: 0 0 0 0 0 0 0 0 0 1 2 0 6 12 0 19 \n" + " 279000: 0 0 0 0 1 0 1 0 0 0 0 2 2 10 19 0 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/affected_cpus", + .size = 1, + .content = "\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/cpuinfo_max_freq", + .size = 8, + .content = "2197000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/cpuinfo_min_freq", + .size = 7, + .content = "279000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/cpuinfo_transition_latency", + .size = 5, + .content = "1000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/related_cpus", + .size = 8, + .content = "4 5 6 7\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_available_governors", + .size = 19, + .content = "sched interactive \n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_cur_freq", + .size = 7, + .content = "687000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_driver", + .size = 11, + .content = "mt-cpufreq\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_governor", + .size = 12, + .content = "interactive\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_max_freq", + .size = 8, + .content = "2197000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_min_freq", + .size = 7, + .content = "687000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/time_in_state", + .size = 186, + .content = "2197000 1085\n" + "2157000 64\n" + "2117000 87\n" + "2040000 100\n" + "1917000 174\n" + "1818000 122\n" + "1694000 77\n" + "1571000 36\n" + "1472000 104\n" + "1324000 160\n" + "1200000 556\n" + "1053000 372\n" + "873000 242\n" + "687000 4306\n" + "484000 144\n" + "279000 450\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/total_trans", + .size = 4, + .content = "599\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/trans_table", + .size = 2941, + .content = + " From : To\n" + " : 2197000 2157000 2117000 2040000 1917000 1818000 1694000 1571000 1472000 1324000 1200000 1053000 873000 687000 484000 279000 \n" + " 2197000: 0 8 5 4 1 3 2 0 0 1 3 1 0 0 0 0 \n" + " 2157000: 8 0 3 4 1 2 0 2 0 0 0 0 0 1 0 0 \n" + " 2117000: 8 3 0 3 2 2 2 0 2 0 0 0 0 0 1 0 \n" + " 2040000: 5 2 7 0 5 1 3 1 3 1 0 0 0 0 0 2 \n" + " 1917000: 2 4 4 7 0 4 1 3 1 2 4 1 0 0 0 0 \n" + " 1818000: 2 3 3 7 7 0 2 0 2 0 2 0 0 1 0 0 \n" + " 1694000: 1 0 0 1 2 8 0 3 2 2 1 0 0 0 0 0 \n" + " 1571000: 0 0 0 0 3 5 3 0 2 1 1 0 0 1 0 0 \n" + " 1472000: 0 0 1 3 1 4 1 6 0 4 5 4 2 0 0 0 \n" + " 1324000: 0 1 0 0 4 0 1 0 12 0 6 0 2 2 0 1 \n" + " 1200000: 2 0 0 0 6 0 2 0 4 10 0 18 4 7 0 0 \n" + " 1053000: 0 0 0 0 0 0 1 0 1 5 16 0 23 10 2 1 \n" + " 873000: 0 0 0 1 0 0 0 0 0 0 8 19 0 36 3 6 \n" + " 687000: 0 0 0 0 0 0 1 1 1 2 5 14 34 0 15 6 \n" + " 484000: 0 0 0 0 0 0 0 0 0 1 2 0 6 12 0 19 \n" + " 279000: 0 0 0 0 1 0 1 0 0 0 0 2 2 10 19 0 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu8/cpufreq/affected_cpus", + .size = 1, + .content = "\n", + }, + { + .path = "/sys/devices/system/cpu/cpu8/cpufreq/cpuinfo_max_freq", + .size = 8, + .content = "2600000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu8/cpufreq/cpuinfo_min_freq", + .size = 7, + .content = "328000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu8/cpufreq/cpuinfo_transition_latency", + .size = 5, + .content = "1000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu8/cpufreq/related_cpus", + .size = 4, + .content = "8 9\n", + }, + { + .path = "/sys/devices/system/cpu/cpu8/cpufreq/scaling_available_governors", + .size = 19, + .content = "sched interactive \n", + }, + { + .path = "/sys/devices/system/cpu/cpu8/cpufreq/scaling_cur_freq", + .size = 7, + .content = "771000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu8/cpufreq/scaling_driver", + .size = 11, + .content = "mt-cpufreq\n", + }, + { + .path = "/sys/devices/system/cpu/cpu8/cpufreq/scaling_governor", + .size = 12, + .content = "interactive\n", + }, + { + .path = "/sys/devices/system/cpu/cpu8/cpufreq/scaling_max_freq", + .size = 8, + .content = "2452000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu8/cpufreq/scaling_min_freq", + .size = 7, + .content = "771000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu8/cpufreq/stats/time_in_state", + .size = 184, + .content = "2600000 551\n" + "2452000 562\n" + "2408000 66\n" + "2318000 80\n" + "2173000 124\n" + "2057000 91\n" + "1911000 356\n" + "1766000 413\n" + "1649000 77\n" + "1475000 264\n" + "1329000 573\n" + "1169000 89\n" + "974000 179\n" + "771000 4387\n" + "551000 225\n" + "328000 313\n", + }, + { + .path = "/sys/devices/system/cpu/cpu8/cpufreq/stats/total_trans", + .size = 4, + .content = "474\n", + }, + { + .path = "/sys/devices/system/cpu/cpu8/cpufreq/stats/trans_table", + .size = 2941, + .content = " From : To\n" + " : 2600000 2452000 2408000 2318000 2173000 2057000 1911000 1766000 1649000 1475000 1329000 1169000 974000 771000 551000 328000 \n" + " 2600000: 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 1 \n" + " 2452000: 1 0 5 3 0 1 1 0 0 0 1 0 0 2 1 0 \n" + " 2408000: 1 4 0 6 3 1 3 0 0 0 1 0 0 0 0 0 \n" + " 2318000: 0 4 3 0 5 5 2 1 1 0 2 0 0 0 0 0 \n" + " 2173000: 0 3 7 5 0 4 0 0 2 3 1 1 2 0 0 0 \n" + " 2057000: 0 2 2 4 5 0 5 6 2 0 0 0 0 0 0 0 \n" + " 1911000: 0 1 1 4 10 11 0 2 2 2 4 1 1 4 0 0 \n" + " 1766000: 1 0 0 0 1 2 8 0 4 2 2 2 0 0 0 0 \n" + " 1649000: 1 0 0 1 0 1 7 7 0 5 2 3 0 1 0 0 \n" + " 1475000: 0 0 0 0 3 1 6 3 9 0 9 3 0 2 0 0 \n" + " 1329000: 0 1 0 0 1 0 6 1 2 12 0 6 1 1 0 0 \n" + " 1169000: 0 0 0 0 0 0 0 0 6 7 4 0 9 4 1 1 \n" + " 974000: 0 0 0 0 0 0 2 2 0 2 2 8 0 28 2 0 \n" + " 771000: 0 0 1 0 0 0 2 0 0 3 1 4 32 0 16 1 \n" + " 551000: 0 0 0 0 0 0 0 0 0 0 0 2 1 17 0 19 \n" + " 328000: 0 0 0 0 0 0 0 0 0 0 1 1 0 2 18 0 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu9/cpufreq/affected_cpus", + .size = 1, + .content = "\n", + }, + { + .path = "/sys/devices/system/cpu/cpu9/cpufreq/cpuinfo_max_freq", + .size = 8, + .content = "2600000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu9/cpufreq/cpuinfo_min_freq", + .size = 7, + .content = "328000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu9/cpufreq/cpuinfo_transition_latency", + .size = 5, + .content = "1000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu9/cpufreq/related_cpus", + .size = 4, + .content = "8 9\n", + }, + { + .path = "/sys/devices/system/cpu/cpu9/cpufreq/scaling_available_governors", + .size = 19, + .content = "sched interactive \n", + }, + { + .path = "/sys/devices/system/cpu/cpu9/cpufreq/scaling_cur_freq", + .size = 7, + .content = "771000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu9/cpufreq/scaling_driver", + .size = 11, + .content = "mt-cpufreq\n", + }, + { + .path = "/sys/devices/system/cpu/cpu9/cpufreq/scaling_governor", + .size = 12, + .content = "interactive\n", + }, + { + .path = "/sys/devices/system/cpu/cpu9/cpufreq/scaling_max_freq", + .size = 8, + .content = "2452000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu9/cpufreq/scaling_min_freq", + .size = 7, + .content = "771000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu9/cpufreq/stats/time_in_state", + .size = 184, + .content = "2600000 551\n" + "2452000 562\n" + "2408000 66\n" + "2318000 80\n" + "2173000 124\n" + "2057000 91\n" + "1911000 356\n" + "1766000 413\n" + "1649000 77\n" + "1475000 264\n" + "1329000 573\n" + "1169000 89\n" + "974000 179\n" + "771000 5352\n" + "551000 225\n" + "328000 313\n", + }, + { + .path = "/sys/devices/system/cpu/cpu9/cpufreq/stats/total_trans", + .size = 4, + .content = "474\n", + }, + { + .path = "/sys/devices/system/cpu/cpu9/cpufreq/stats/trans_table", + .size = 2941, + .content = + " From : To\n" + " : 2600000 2452000 2408000 2318000 2173000 2057000 1911000 1766000 1649000 1475000 1329000 1169000 974000 771000 551000 328000 \n" + " 2600000: 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 1 \n" + " 2452000: 1 0 5 3 0 1 1 0 0 0 1 0 0 2 1 0 \n" + " 2408000: 1 4 0 6 3 1 3 0 0 0 1 0 0 0 0 0 \n" + " 2318000: 0 4 3 0 5 5 2 1 1 0 2 0 0 0 0 0 \n" + " 2173000: 0 3 7 5 0 4 0 0 2 3 1 1 2 0 0 0 \n" + " 2057000: 0 2 2 4 5 0 5 6 2 0 0 0 0 0 0 0 \n" + " 1911000: 0 1 1 4 10 11 0 2 2 2 4 1 1 4 0 0 \n" + " 1766000: 1 0 0 0 1 2 8 0 4 2 2 2 0 0 0 0 \n" + " 1649000: 1 0 0 1 0 1 7 7 0 5 2 3 0 1 0 0 \n" + " 1475000: 0 0 0 0 3 1 6 3 9 0 9 3 0 2 0 0 \n" + " 1329000: 0 1 0 0 1 0 6 1 2 12 0 6 1 1 0 0 \n" + " 1169000: 0 0 0 0 0 0 0 0 6 7 4 0 9 4 1 1 \n" + " 974000: 0 0 0 0 0 0 2 2 0 2 2 8 0 28 2 0 \n" + " 771000: 0 0 1 0 0 0 2 0 0 3 1 4 32 0 16 1 \n" + " 551000: 0 0 0 0 0 0 0 0 0 0 0 2 1 17 0 19 \n" + " 328000: 0 0 0 0 0 0 0 0 0 0 1 1 0 2 18 0 \n", + }, + {NULL}, }; #ifdef __ANDROID__ @@ -4331,6 +4324,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.wfd.security.image", .value = "1", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/memo-pad-7.cc b/test/mock/memo-pad-7.cc index b72431a7..618dc344 100644 --- a/test/mock/memo-pad-7.cc +++ b/test/mock/memo-pad-7.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(4, cpuinfo_get_processors_count()); @@ -212,8 +211,10 @@ TEST(PACKAGES, non_null) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Intel Atom Z3745", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Intel Atom Z3745", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -536,8 +537,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -588,8 +591,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -640,8 +645,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/memo-pad-7.h b/test/mock/memo-pad-7.h index 669be93e..f7c2d1ec 100644 --- a/test/mock/memo-pad-7.h +++ b/test/mock/memo-pad-7.h @@ -425,7 +425,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/modalias", .size = 426, - .content = "x86cpu:vendor:0000:family:0006:model:0037:feature:,0000,0001,0002,0003,0004,0005,0006,0007,0008,0009,000B,000C,000D,000E,000F,0010,0011,0013,0015,0016,0017,0018,0019,001A,001B,001C,001D,001F,0034,003B,003D,0066,0068,006B,006C,006D,0072,0076,0078,007C,007E,0080,0081,0082,0083,0084,0085,0087,0088,0089,008D,008E,008F,0093,0094,0096,0097,0098,0099,009E,00C0,00C8,00E0,00E1,00E3,00E7,0100,0101,0102,0103,0104,0121,0127,0129,012D\n", + .content = + "x86cpu:vendor:0000:family:0006:model:0037:feature:,0000,0001,0002,0003,0004,0005,0006,0007,0008,0009,000B,000C,000D,000E,000F,0010,0011,0013,0015,0016,0017,0018,0019,001A,001B,001C,001D,001F,0034,003B,003D,0066,0068,006B,006C,006D,0072,0076,0078,007C,007E,0080,0081,0082,0083,0084,0085,0087,0088,0089,008D,008E,008F,0093,0094,0096,0097,0098,0099,009E,00C0,00C8,00E0,00E1,00E3,00E7,0100,0101,0102,0103,0104,0121,0127,0129,012D\n", }, { .path = "/sys/devices/system/cpu/cpuidle/current_driver", @@ -495,18 +496,17 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 125, - .content = - "1862000 12139\n" - "1729000 47\n" - "1596000 50\n" - "1463000 331\n" - "1330000 29\n" - "1197000 71\n" - "1064000 50\n" - "931000 74\n" - "798000 101\n" - "665000 386\n" - "532000 6409\n", + .content = "1862000 12139\n" + "1729000 47\n" + "1596000 50\n" + "1463000 331\n" + "1330000 29\n" + "1197000 71\n" + "1064000 50\n" + "931000 74\n" + "798000 101\n" + "665000 386\n" + "532000 6409\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -739,18 +739,17 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 125, - .content = - "1862000 12167\n" - "1729000 47\n" - "1596000 50\n" - "1463000 331\n" - "1330000 29\n" - "1197000 71\n" - "1064000 50\n" - "931000 74\n" - "798000 101\n" - "665000 388\n" - "532000 6701\n", + .content = "1862000 12167\n" + "1729000 47\n" + "1596000 50\n" + "1463000 331\n" + "1330000 29\n" + "1197000 71\n" + "1064000 50\n" + "931000 74\n" + "798000 101\n" + "665000 388\n" + "532000 6701\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -983,18 +982,17 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 125, - .content = - "1862000 12194\n" - "1729000 47\n" - "1596000 50\n" - "1463000 331\n" - "1330000 29\n" - "1197000 71\n" - "1064000 50\n" - "931000 75\n" - "798000 101\n" - "665000 400\n" - "532000 6969\n", + .content = "1862000 12194\n" + "1729000 47\n" + "1596000 50\n" + "1463000 331\n" + "1330000 29\n" + "1197000 71\n" + "1064000 50\n" + "931000 75\n" + "798000 101\n" + "665000 400\n" + "532000 6969\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -1227,18 +1225,17 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 125, - .content = - "1862000 12209\n" - "1729000 47\n" - "1596000 50\n" - "1463000 331\n" - "1330000 29\n" - "1197000 71\n" - "1064000 50\n" - "931000 75\n" - "798000 101\n" - "665000 414\n" - "532000 7250\n", + .content = "1862000 12209\n" + "1729000 47\n" + "1596000 50\n" + "1463000 331\n" + "1330000 29\n" + "1197000 71\n" + "1064000 50\n" + "931000 75\n" + "798000 101\n" + "665000 414\n" + "532000 7250\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -1413,7 +1410,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 3, .content = "16\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ @@ -2498,6 +2495,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wpa_supplicant.pid", .value = "593", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/moto-e-gen1.cc b/test/mock/moto-e-gen1.cc index 190e96f8..d1ffddc8 100644 --- a/test/mock/moto-e-gen1.cc +++ b/test/mock/moto-e-gen1.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(2, cpuinfo_get_processors_count()); @@ -208,8 +207,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Qualcomm MSM8610", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Qualcomm MSM8610", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -400,8 +401,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -452,8 +455,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -504,8 +509,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/moto-e-gen1.h b/test/mock/moto-e-gen1.h index c4bd0618..44506b17 100644 --- a/test/mock/moto-e-gen1.h +++ b/test/mock/moto-e-gen1.h @@ -2,27 +2,26 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 428, - .content = - "Processor\t: ARMv7 Processor rev 3 (v7l)\n" - "processor\t: 0\n" - "BogoMIPS\t: 38.40\n" - "\n" - "processor\t: 1\n" - "BogoMIPS\t: 38.40\n" - "\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xc07\n" - "CPU revision\t: 3\n" - "\n" - "Hardware\t: Qualcomm MSM 8610 (Flattened Device Tree)\n" - "Revision\t: 82b0\n" - "Serial\t\t: 9433a00212000000\n" - "Device\t\t: condor\n" - "Radio\t\t: 1\n" - "MSM Hardware\t: MSM8210 CS\n", + .content = "Processor\t: ARMv7 Processor rev 3 (v7l)\n" + "processor\t: 0\n" + "BogoMIPS\t: 38.40\n" + "\n" + "processor\t: 1\n" + "BogoMIPS\t: 38.40\n" + "\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xc07\n" + "CPU revision\t: 3\n" + "\n" + "Hardware\t: Qualcomm MSM 8610 (Flattened Device Tree)\n" + "Revision\t: 82b0\n" + "Serial\t\t: 9433a00212000000\n" + "Device\t\t: condor\n" + "Radio\t\t: 1\n" + "MSM Hardware\t: MSM8210 CS\n", }, { .path = "/system/build.prop", @@ -397,13 +396,12 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 69, - .content = - "300000 226957\n" - "384000 42\n" - "600000 89\n" - "787200 17\n" - "998400 3281\n" - "1190400 4758\n", + .content = "300000 226957\n" + "384000 42\n" + "600000 89\n" + "787200 17\n" + "998400 3281\n" + "1190400 4758\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -440,7 +438,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "1\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ @@ -1841,6 +1839,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.driver.status", .value = "ok", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/moto-g-gen1.cc b/test/mock/moto-g-gen1.cc index b90216b9..9364ba77 100644 --- a/test/mock/moto-g-gen1.cc +++ b/test/mock/moto-g-gen1.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(4, cpuinfo_get_processors_count()); @@ -208,8 +207,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Qualcomm MSM8226", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Qualcomm MSM8226", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -400,8 +401,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -452,8 +455,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -504,8 +509,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/moto-g-gen1.h b/test/mock/moto-g-gen1.h index 08c5cae7..a69cb70f 100644 --- a/test/mock/moto-g-gen1.h +++ b/test/mock/moto-g-gen1.h @@ -2,33 +2,32 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 492, - .content = - "Processor\t: ARMv7 Processor rev 3 (v7l)\n" - "processor\t: 0\n" - "BogoMIPS\t: 38.40\n" - "\n" - "processor\t: 1\n" - "BogoMIPS\t: 38.40\n" - "\n" - "processor\t: 2\n" - "BogoMIPS\t: 38.40\n" - "\n" - "processor\t: 3\n" - "BogoMIPS\t: 38.40\n" - "\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xc07\n" - "CPU revision\t: 3\n" - "\n" - "Hardware\t: Qualcomm MSM 8226 (Flattened Device Tree)\n" - "Revision\t: 82d0\n" - "Serial\t\t: 1063b20615000000\n" - "Device\t\t: peregrine\n" - "Radio\t\t: 1\n" - "MSM Hardware\t: MSM8926\n", + .content = "Processor\t: ARMv7 Processor rev 3 (v7l)\n" + "processor\t: 0\n" + "BogoMIPS\t: 38.40\n" + "\n" + "processor\t: 1\n" + "BogoMIPS\t: 38.40\n" + "\n" + "processor\t: 2\n" + "BogoMIPS\t: 38.40\n" + "\n" + "processor\t: 3\n" + "BogoMIPS\t: 38.40\n" + "\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xc07\n" + "CPU revision\t: 3\n" + "\n" + "Hardware\t: Qualcomm MSM 8226 (Flattened Device Tree)\n" + "Revision\t: 82d0\n" + "Serial\t\t: 1063b20615000000\n" + "Device\t\t: peregrine\n" + "Radio\t\t: 1\n" + "MSM Hardware\t: MSM8926\n", }, { .path = "/system/build.prop", @@ -378,14 +377,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 80, - .content = - "300000 7753\n" - "384000 91\n" - "600000 160\n" - "787200 21\n" - "998400 3794\n" - "1094400 480\n" - "1190400 6702\n", + .content = "300000 7753\n" + "384000 91\n" + "600000 160\n" + "787200 21\n" + "998400 3794\n" + "1094400 480\n" + "1190400 6702\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -422,7 +420,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "0\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -1798,6 +1796,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.driver.status", .value = "ok", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/moto-g-gen2.cc b/test/mock/moto-g-gen2.cc index b6a1586a..8fce8d0e 100644 --- a/test/mock/moto-g-gen2.cc +++ b/test/mock/moto-g-gen2.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(4, cpuinfo_get_processors_count()); @@ -208,8 +207,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Qualcomm MSM8226", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Qualcomm MSM8226", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -400,8 +401,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -452,8 +455,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -504,8 +509,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/moto-g-gen2.h b/test/mock/moto-g-gen2.h index 9e09ca73..0fc56755 100644 --- a/test/mock/moto-g-gen2.h +++ b/test/mock/moto-g-gen2.h @@ -2,33 +2,32 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 466, - .content = - "Processor\t: ARMv7 Processor rev 3 (v7l)\n" - "processor\t: 0\n" - "BogoMIPS\t: 38.40\n" - "\n" - "processor\t: 1\n" - "BogoMIPS\t: 38.40\n" - "\n" - "processor\t: 2\n" - "BogoMIPS\t: 38.40\n" - "\n" - "processor\t: 3\n" - "BogoMIPS\t: 38.40\n" - "\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xc07\n" - "CPU revision\t: 3\n" - "\n" - "Hardware\t: Qualcomm MSM8226\n" - "Revision\t: 8400\n" - "Serial\t\t: d1c59d080f000000\n" - "Device\t\t: titan\n" - "Radio\t\t: 5\n" - "MSM Hardware\t: MSM8226 CS\n", + .content = "Processor\t: ARMv7 Processor rev 3 (v7l)\n" + "processor\t: 0\n" + "BogoMIPS\t: 38.40\n" + "\n" + "processor\t: 1\n" + "BogoMIPS\t: 38.40\n" + "\n" + "processor\t: 2\n" + "BogoMIPS\t: 38.40\n" + "\n" + "processor\t: 3\n" + "BogoMIPS\t: 38.40\n" + "\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xc07\n" + "CPU revision\t: 3\n" + "\n" + "Hardware\t: Qualcomm MSM8226\n" + "Revision\t: 8400\n" + "Serial\t\t: d1c59d080f000000\n" + "Device\t\t: titan\n" + "Radio\t\t: 5\n" + "MSM Hardware\t: MSM8226 CS\n", }, { .path = "/system/build.prop", @@ -426,14 +425,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 68, - .content = - "300000 0\n" - "384000 0\n" - "600000 0\n" - "787200 0\n" - "998400 0\n" - "1094400 0\n" - "1190400 2628\n", + .content = "300000 0\n" + "384000 0\n" + "600000 0\n" + "787200 0\n" + "998400 0\n" + "1094400 0\n" + "1190400 2628\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -523,14 +521,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 68, - .content = - "300000 0\n" - "384000 0\n" - "600000 0\n" - "787200 0\n" - "998400 0\n" - "1094400 0\n" - "1190400 2897\n", + .content = "300000 0\n" + "384000 0\n" + "600000 0\n" + "787200 0\n" + "998400 0\n" + "1094400 0\n" + "1190400 2897\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -630,14 +627,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 68, - .content = - "300000 0\n" - "384000 0\n" - "600000 0\n" - "787200 0\n" - "998400 0\n" - "1094400 6\n" - "1190400 3170\n", + .content = "300000 0\n" + "384000 0\n" + "600000 0\n" + "787200 0\n" + "998400 0\n" + "1094400 6\n" + "1190400 3170\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -697,14 +693,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 69, - .content = - "300000 0\n" - "384000 0\n" - "600000 0\n" - "787200 0\n" - "998400 2\n" - "1094400 15\n" - "1190400 3428\n", + .content = "300000 0\n" + "384000 0\n" + "600000 0\n" + "787200 0\n" + "998400 2\n" + "1094400 15\n" + "1190400 3428\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -726,7 +721,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 4, .content = "0-3\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -2246,6 +2241,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.driver.status", .value = "ok", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/moto-g-gen3.cc b/test/mock/moto-g-gen3.cc index 624aca27..8c049d20 100644 --- a/test/mock/moto-g-gen3.cc +++ b/test/mock/moto-g-gen3.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(4, cpuinfo_get_processors_count()); @@ -208,8 +207,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Qualcomm MSM8916", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Qualcomm MSM8916", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -400,8 +401,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -452,8 +455,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -504,8 +509,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/moto-g-gen3.h b/test/mock/moto-g-gen3.h index af535d8b..57f88be5 100644 --- a/test/mock/moto-g-gen3.h +++ b/test/mock/moto-g-gen3.h @@ -473,16 +473,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 88, - .content = - "200000 0\n" - "400000 0\n" - "533333 0\n" - "800000 0\n" - "998400 0\n" - "1094400 0\n" - "1152000 0\n" - "1209600 0\n" - "1363200 2118\n", + .content = "200000 0\n" + "400000 0\n" + "533333 0\n" + "800000 0\n" + "998400 0\n" + "1094400 0\n" + "1152000 0\n" + "1209600 0\n" + "1363200 2118\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -572,16 +571,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 88, - .content = - "200000 0\n" - "400000 0\n" - "533333 0\n" - "800000 0\n" - "998400 0\n" - "1094400 0\n" - "1152000 0\n" - "1209600 0\n" - "1363200 2354\n", + .content = "200000 0\n" + "400000 0\n" + "533333 0\n" + "800000 0\n" + "998400 0\n" + "1094400 0\n" + "1152000 0\n" + "1209600 0\n" + "1363200 2354\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -671,16 +669,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 88, - .content = - "200000 0\n" - "400000 0\n" - "533333 0\n" - "800000 0\n" - "998400 0\n" - "1094400 0\n" - "1152000 0\n" - "1209600 0\n" - "1363200 2600\n", + .content = "200000 0\n" + "400000 0\n" + "533333 0\n" + "800000 0\n" + "998400 0\n" + "1094400 0\n" + "1152000 0\n" + "1209600 0\n" + "1363200 2600\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -770,16 +767,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 88, - .content = - "200000 0\n" - "400000 0\n" - "533333 0\n" - "800000 0\n" - "998400 2\n" - "1094400 0\n" - "1152000 0\n" - "1209600 4\n" - "1363200 2853\n", + .content = "200000 0\n" + "400000 0\n" + "533333 0\n" + "800000 0\n" + "998400 2\n" + "1094400 0\n" + "1152000 0\n" + "1209600 4\n" + "1363200 2853\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -816,7 +812,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 3, .content = "08\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ @@ -2421,6 +2417,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.driver.status", .value = "ok", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/moto-g-gen4.cc b/test/mock/moto-g-gen4.cc index 1da127c1..3a341f9d 100644 --- a/test/mock/moto-g-gen4.cc +++ b/test/mock/moto-g-gen4.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(8, cpuinfo_get_processors_count()); @@ -274,8 +273,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Qualcomm MSM8952", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Qualcomm MSM8952", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -317,59 +318,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -494,8 +495,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -546,8 +549,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -605,8 +610,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/moto-g-gen4.h b/test/mock/moto-g-gen4.h index 5cc9224c..13cb1157 100644 --- a/test/mock/moto-g-gen4.h +++ b/test/mock/moto-g-gen4.h @@ -642,12 +642,11 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 53, - .content = - "960000 739\n" - "1094400 0\n" - "1344000 9\n" - "1440000 8\n" - "1516800 255\n", + .content = "960000 739\n" + "1094400 0\n" + "1344000 9\n" + "1440000 8\n" + "1516800 255\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -752,12 +751,11 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 54, - .content = - "960000 861\n" - "1094400 0\n" - "1344000 9\n" - "1440000 24\n" - "1516800 308\n", + .content = "960000 861\n" + "1094400 0\n" + "1344000 9\n" + "1440000 24\n" + "1516800 308\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -872,11 +870,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/time_in_state", .size = 47, - .content = - "806400 1011\n" - "998400 149\n" - "1094400 20\n" - "1209600 3422\n", + .content = "806400 1011\n" + "998400 149\n" + "1094400 20\n" + "1209600 3422\n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/total_trans", @@ -981,11 +978,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/time_in_state", .size = 47, - .content = - "806400 1163\n" - "998400 154\n" - "1094400 20\n" - "1209600 3437\n", + .content = "806400 1163\n" + "998400 154\n" + "1094400 20\n" + "1209600 3437\n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/total_trans", @@ -1090,11 +1086,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/time_in_state", .size = 47, - .content = - "806400 1317\n" - "998400 159\n" - "1094400 20\n" - "1209600 3453\n", + .content = "806400 1317\n" + "998400 159\n" + "1094400 20\n" + "1209600 3453\n", }, { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/total_trans", @@ -1199,11 +1194,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/time_in_state", .size = 47, - .content = - "806400 1494\n" - "998400 165\n" - "1094400 20\n" - "1209600 3453\n", + .content = "806400 1494\n" + "998400 165\n" + "1094400 20\n" + "1209600 3453\n", }, { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/total_trans", @@ -1240,7 +1234,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "7\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -3280,6 +3274,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.driver.status", .value = "ok", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/moto-g-gen5.cc b/test/mock/moto-g-gen5.cc index f29c7da8..5882c79c 100644 --- a/test/mock/moto-g-gen5.cc +++ b/test/mock/moto-g-gen5.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(8, cpuinfo_get_processors_count()); @@ -287,8 +286,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Qualcomm MSM8937", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Qualcomm MSM8937", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -479,8 +480,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -531,8 +534,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -590,8 +595,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/moto-g-gen5.h b/test/mock/moto-g-gen5.h index c8b0b470..2295a3fb 100644 --- a/test/mock/moto-g-gen5.h +++ b/test/mock/moto-g-gen5.h @@ -598,71 +598,67 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/soc0/image_crm_version", .size = 5, - .content = - "REL\n" - "\n", + .content = "REL\n" + "\n", }, { .path = "/sys/devices/soc0/image_variant", .size = 13, - .content = - "cedric-user\n" - "\n", + .content = "cedric-user\n" + "\n", }, { .path = "/sys/devices/soc0/image_version", .size = 20, - .content = - "10:NPP25.137-15:13\n" - "\n", + .content = "10:NPP25.137-15:13\n" + "\n", }, { .path = "/sys/devices/soc0/images", .size = 570, - .content = - "0:\n" - "\tCRM:\t\t00:BOOT.BF.3.3-00193\n" - "\tVariant:\tFAASANAZA\n" - "\tVersion:\tshws28\n" - "\n" - "1:\n" - "\tCRM:\t\t01:TZ.BF.4.0.5-00030\n" - "\tVariant:\t\n" - "\tVersion:\tCRM\n" - "\n" - "3:\n" - "\tCRM:\t\t03:RPM.BF.2.2-00209\n" - "\tVariant:\tAAAAANAAR\n" - "\tVersion:\tshws28\n" - "\n" - "10:\n" - "\tCRM:\t\t10:NPP25.137-15:13\n" - "\n" - "\tVariant:\tcedric-user\n" - "\n" - "\tVersion:\tREL\n" - "\n" - "\n" - "11:\n" - "\tCRM:\t\t11:MPSS.JO.2.0.C1-00122\n" - "\tVariant:\t8937.genns.prodQ\n" - "\tVersion:\tilclbld116/hudsonmd/3106b73\n" - "\n" - "12:\n" - "\tCRM:\t\t12:ADSP.8953.2.8.2-00042\n" - "\tVariant:\tAAAAAAAAQ\n" - "\tVersion:\tCRM\n" - "\n" - "13:\n" - "\tCRM:\t\t13:CNSS.PR.4.0-80391\n" - "\tVariant:\tSCAQJAZM\n" - "\tVersion:\tCRM\n" - "\n" - "14:\n" - "\tCRM:\t\t14:VIDEO.VE_ULT.3.1-00025\n" - "\tVariant:\tPROD\n" - "\tVersion:\t:CRM\n" - "\n", + .content = "0:\n" + "\tCRM:\t\t00:BOOT.BF.3.3-00193\n" + "\tVariant:\tFAASANAZA\n" + "\tVersion:\tshws28\n" + "\n" + "1:\n" + "\tCRM:\t\t01:TZ.BF.4.0.5-00030\n" + "\tVariant:\t\n" + "\tVersion:\tCRM\n" + "\n" + "3:\n" + "\tCRM:\t\t03:RPM.BF.2.2-00209\n" + "\tVariant:\tAAAAANAAR\n" + "\tVersion:\tshws28\n" + "\n" + "10:\n" + "\tCRM:\t\t10:NPP25.137-15:13\n" + "\n" + "\tVariant:\tcedric-user\n" + "\n" + "\tVersion:\tREL\n" + "\n" + "\n" + "11:\n" + "\tCRM:\t\t11:MPSS.JO.2.0.C1-00122\n" + "\tVariant:\t8937.genns.prodQ\n" + "\tVersion:\tilclbld116/hudsonmd/3106b73\n" + "\n" + "12:\n" + "\tCRM:\t\t12:ADSP.8953.2.8.2-00042\n" + "\tVariant:\tAAAAAAAAQ\n" + "\tVersion:\tCRM\n" + "\n" + "13:\n" + "\tCRM:\t\t13:CNSS.PR.4.0-80391\n" + "\tVariant:\tSCAQJAZM\n" + "\tVersion:\tCRM\n" + "\n" + "14:\n" + "\tCRM:\t\t14:VIDEO.VE_ULT.3.1-00025\n" + "\tVariant:\tPROD\n" + "\tVersion:\t:CRM\n" + "\n", }, { .path = "/sys/devices/soc0/machine", @@ -757,17 +753,16 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpufreq/all_time_in_state", .size = 513, - .content = - "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\t\n" - "768000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t41124\t\t41124\t\t41124\t\t41124\t\t\n" - "902400\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t220\t\t220\t\t220\t\t220\t\t\n" - "960000\t\t41797\t\t41797\t\t41797\t\t41797\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "998400\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t32\t\t32\t\t32\t\t32\t\t\n" - "1094400\t\t452\t\t452\t\t452\t\t452\t\t5481\t\t5481\t\t5481\t\t5481\t\t\n" - "1209600\t\t70\t\t70\t\t70\t\t70\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1248000\t\t860\t\t860\t\t860\t\t860\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1344000\t\t24\t\t24\t\t24\t\t24\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1401000\t\t3653\t\t3653\t\t3653\t\t3653\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n", + .content = "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\t\n" + "768000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t41124\t\t41124\t\t41124\t\t41124\t\t\n" + "902400\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t220\t\t220\t\t220\t\t220\t\t\n" + "960000\t\t41797\t\t41797\t\t41797\t\t41797\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "998400\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t32\t\t32\t\t32\t\t32\t\t\n" + "1094400\t\t452\t\t452\t\t452\t\t452\t\t5481\t\t5481\t\t5481\t\t5481\t\t\n" + "1209600\t\t70\t\t70\t\t70\t\t70\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "1248000\t\t860\t\t860\t\t860\t\t860\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "1344000\t\t24\t\t24\t\t24\t\t24\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "1401000\t\t3653\t\t3653\t\t3653\t\t3653\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n", }, { .path = "/sys/devices/system/cpu/cpufreq/current_in_state", @@ -842,13 +837,12 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 72, - .content = - "960000 41917\n" - "1094400 452\n" - "1209600 70\n" - "1248000 860\n" - "1344000 24\n" - "1401000 3653\n", + .content = "960000 41917\n" + "1094400 452\n" + "1209600 70\n" + "1248000 860\n" + "1344000 24\n" + "1401000 3653\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -943,13 +937,12 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 72, - .content = - "960000 42135\n" - "1094400 452\n" - "1209600 70\n" - "1248000 860\n" - "1344000 24\n" - "1401000 3653\n", + .content = "960000 42135\n" + "1094400 452\n" + "1209600 70\n" + "1248000 860\n" + "1344000 24\n" + "1401000 3653\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -1044,13 +1037,12 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 72, - .content = - "960000 42339\n" - "1094400 452\n" - "1209600 70\n" - "1248000 860\n" - "1344000 24\n" - "1401000 3653\n", + .content = "960000 42339\n" + "1094400 452\n" + "1209600 70\n" + "1248000 860\n" + "1344000 24\n" + "1401000 3653\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -1145,13 +1137,12 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 72, - .content = - "960000 42558\n" - "1094400 452\n" - "1209600 70\n" - "1248000 860\n" - "1344000 24\n" - "1401000 3653\n", + .content = "960000 42558\n" + "1094400 452\n" + "1209600 70\n" + "1248000 860\n" + "1344000 24\n" + "1401000 3653\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -1256,11 +1247,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/time_in_state", .size = 47, - .content = - "768000 42073\n" - "902400 224\n" - "998400 32\n" - "1094400 5491\n", + .content = "768000 42073\n" + "902400 224\n" + "998400 32\n" + "1094400 5491\n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/total_trans", @@ -1365,11 +1355,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/time_in_state", .size = 47, - .content = - "768000 42293\n" - "902400 224\n" - "998400 32\n" - "1094400 5491\n", + .content = "768000 42293\n" + "902400 224\n" + "998400 32\n" + "1094400 5491\n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/total_trans", @@ -1474,11 +1463,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/time_in_state", .size = 47, - .content = - "768000 42511\n" - "902400 224\n" - "998400 32\n" - "1094400 5491\n", + .content = "768000 42511\n" + "902400 224\n" + "998400 32\n" + "1094400 5491\n", }, { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/total_trans", @@ -1583,11 +1571,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/time_in_state", .size = 47, - .content = - "768000 42736\n" - "902400 224\n" - "998400 32\n" - "1094400 5491\n", + .content = "768000 42736\n" + "902400 224\n" + "998400 32\n" + "1094400 5491\n", }, { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/total_trans", @@ -1624,7 +1611,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "7\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -3844,6 +3831,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.driver.status", .value = "ok", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/nexus-s.cc b/test/mock/nexus-s.cc index 42199b99..20693d31 100644 --- a/test/mock/nexus-s.cc +++ b/test/mock/nexus-s.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(1, cpuinfo_get_processors_count()); @@ -208,8 +207,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Samsung Exynos 3110", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Samsung Exynos 3110", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -502,8 +503,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/nexus-s.h b/test/mock/nexus-s.h index 045fc3a4..488cac3f 100644 --- a/test/mock/nexus-s.h +++ b/test/mock/nexus-s.h @@ -2,19 +2,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 280, - .content = - "Processor\t: ARMv7 Processor rev 2 (v7l)\n" - "BogoMIPS\t: 994.65\n" - "Features\t: swp half thumb fastmult vfp edsp thumbee neon vfpv3 \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x2\n" - "CPU part\t: 0xc08\n" - "CPU revision\t: 2\n" - "\n" - "Hardware\t: herring\n" - "Revision\t: 0022\n" - "Serial\t\t: 363581cc0b5f00ec\n", + .content = "Processor\t: ARMv7 Processor rev 2 (v7l)\n" + "BogoMIPS\t: 994.65\n" + "Features\t: swp half thumb fastmult vfp edsp thumbee neon vfpv3 \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x2\n" + "CPU part\t: 0xc08\n" + "CPU revision\t: 2\n" + "\n" + "Hardware\t: herring\n" + "Revision\t: 0022\n" + "Serial\t\t: 363581cc0b5f00ec\n", }, { .path = "/system/build.prop", @@ -186,19 +185,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 56, - .content = - "1000000 2511\n" - "800000 211\n" - "400000 223\n" - "200000 233\n" - "100000 28\n", + .content = "1000000 2511\n" + "800000 211\n" + "400000 223\n" + "200000 233\n" + "100000 28\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", .size = 3, .content = "88\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ @@ -819,6 +817,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wifi.supplicant_scan_interval", .value = "15", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/nexus10.cc b/test/mock/nexus10.cc index b3bcaabd..6a335e9d 100644 --- a/test/mock/nexus10.cc +++ b/test/mock/nexus10.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(2, cpuinfo_get_processors_count()); @@ -208,8 +207,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Samsung Exynos 5250", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Samsung Exynos 5250", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -400,8 +401,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -452,8 +455,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -504,8 +509,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/nexus10.h b/test/mock/nexus10.h index 1a6e9793..66e91932 100644 --- a/test/mock/nexus10.h +++ b/test/mock/nexus10.h @@ -2,24 +2,23 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 340, - .content = - "Processor\t: ARMv7 Processor rev 4 (v7l)\n" - "processor\t: 0\n" - "BogoMIPS\t: 997.78\n" - "\n" - "processor\t: 1\n" - "BogoMIPS\t: 997.78\n" - "\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xc0f\n" - "CPU revision\t: 4\n" - "\n" - "Hardware\t: Manta\n" - "Revision\t: 0008\n" - "Serial\t\t: 4733303344323352\n", + .content = "Processor\t: ARMv7 Processor rev 4 (v7l)\n" + "processor\t: 0\n" + "BogoMIPS\t: 997.78\n" + "\n" + "processor\t: 1\n" + "BogoMIPS\t: 997.78\n" + "\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xc0f\n" + "CPU revision\t: 4\n" + "\n" + "Hardware\t: Manta\n" + "Revision\t: 0008\n" + "Serial\t\t: 4733303344323352\n", }, { .path = "/system/build.prop", @@ -153,24 +152,23 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpufreq/all_time_in_state", .size = 309, - .content = - "freq\t\tcpu0\t\tcpu1\t\t\n" - "200000\t\t219\t\t219\t\t\n" - "300000\t\t17\t\t17\t\t\n" - "400000\t\t10\t\t10\t\t\n" - "500000\t\t17\t\t17\t\t\n" - "600000\t\t10\t\t10\t\t\n" - "700000\t\t0\t\t0\t\t\n" - "800000\t\t1\t\t1\t\t\n" - "900000\t\t19\t\t19\t\t\n" - "1000000\t\t519\t\t519\t\t\n" - "1100000\t\t33\t\t33\t\t\n" - "1200000\t\t50\t\t50\t\t\n" - "1300000\t\t54\t\t54\t\t\n" - "1400000\t\t232\t\t232\t\t\n" - "1500000\t\t219\t\t219\t\t\n" - "1600000\t\t131\t\t131\t\t\n" - "1700000\t\t1211\t\t1211\t\t\n", + .content = "freq\t\tcpu0\t\tcpu1\t\t\n" + "200000\t\t219\t\t219\t\t\n" + "300000\t\t17\t\t17\t\t\n" + "400000\t\t10\t\t10\t\t\n" + "500000\t\t17\t\t17\t\t\n" + "600000\t\t10\t\t10\t\t\n" + "700000\t\t0\t\t0\t\t\n" + "800000\t\t1\t\t1\t\t\n" + "900000\t\t19\t\t19\t\t\n" + "1000000\t\t519\t\t519\t\t\n" + "1100000\t\t33\t\t33\t\t\n" + "1200000\t\t50\t\t50\t\t\n" + "1300000\t\t54\t\t54\t\t\n" + "1400000\t\t232\t\t232\t\t\n" + "1500000\t\t219\t\t219\t\t\n" + "1600000\t\t131\t\t131\t\t\n" + "1700000\t\t1211\t\t1211\t\t\n", }, { .path = "/sys/devices/system/cpu/cpuidle/current_driver", @@ -235,23 +233,22 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 173, - .content = - "1700000 1211\n" - "1600000 145\n" - "1500000 265\n" - "1400000 249\n" - "1300000 57\n" - "1200000 50\n" - "1100000 33\n" - "1000000 524\n" - "900000 19\n" - "800000 1\n" - "700000 0\n" - "600000 10\n" - "500000 17\n" - "400000 10\n" - "300000 17\n" - "200000 219\n", + .content = "1700000 1211\n" + "1600000 145\n" + "1500000 265\n" + "1400000 249\n" + "1300000 57\n" + "1200000 50\n" + "1100000 33\n" + "1000000 524\n" + "900000 19\n" + "800000 1\n" + "700000 0\n" + "600000 10\n" + "500000 17\n" + "400000 10\n" + "300000 17\n" + "200000 219\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -341,23 +338,22 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 173, - .content = - "1700000 1211\n" - "1600000 151\n" - "1500000 302\n" - "1400000 264\n" - "1300000 61\n" - "1200000 54\n" - "1100000 33\n" - "1000000 585\n" - "900000 19\n" - "800000 1\n" - "700000 2\n" - "600000 10\n" - "500000 23\n" - "400000 10\n" - "300000 33\n" - "200000 338\n", + .content = "1700000 1211\n" + "1600000 151\n" + "1500000 302\n" + "1400000 264\n" + "1300000 61\n" + "1200000 54\n" + "1100000 33\n" + "1000000 585\n" + "900000 19\n" + "800000 1\n" + "700000 2\n" + "600000 10\n" + "500000 23\n" + "400000 10\n" + "300000 33\n" + "200000 338\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -394,7 +390,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "1\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -1130,6 +1126,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.driver.status", .value = "ok", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/nexus4.cc b/test/mock/nexus4.cc index 241a5173..1e1b0d78 100644 --- a/test/mock/nexus4.cc +++ b/test/mock/nexus4.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(4, cpuinfo_get_processors_count()); @@ -208,8 +207,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Qualcomm APQ8064", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Qualcomm APQ8064", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -400,8 +401,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -452,8 +455,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -504,8 +509,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/nexus4.h b/test/mock/nexus4.h index 4a5b3cb6..f0169ea5 100644 --- a/test/mock/nexus4.h +++ b/test/mock/nexus4.h @@ -2,30 +2,29 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 401, - .content = - "Processor\t: ARMv7 Processor rev 2 (v7l)\n" - "processor\t: 0\n" - "BogoMIPS\t: 13.53\n" - "\n" - "processor\t: 1\n" - "BogoMIPS\t: 13.53\n" - "\n" - "processor\t: 2\n" - "BogoMIPS\t: 13.53\n" - "\n" - "processor\t: 3\n" - "BogoMIPS\t: 13.53\n" - "\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 \n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0x06f\n" - "CPU revision\t: 2\n" - "\n" - "Hardware\t: QCT APQ8064 MAKO\n" - "Revision\t: 000b\n" - "Serial\t\t: 0000000000000000\n", + .content = "Processor\t: ARMv7 Processor rev 2 (v7l)\n" + "processor\t: 0\n" + "BogoMIPS\t: 13.53\n" + "\n" + "processor\t: 1\n" + "BogoMIPS\t: 13.53\n" + "\n" + "processor\t: 2\n" + "BogoMIPS\t: 13.53\n" + "\n" + "processor\t: 3\n" + "BogoMIPS\t: 13.53\n" + "\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 \n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0x06f\n" + "CPU revision\t: 2\n" + "\n" + "Hardware\t: QCT APQ8064 MAKO\n" + "Revision\t: 000b\n" + "Serial\t\t: 0000000000000000\n", }, { .path = "/system/build.prop", @@ -156,20 +155,19 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpufreq/all_time_in_state", .size = 244, - .content = - "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\t\n" - "384000\t\t332\t\t71\t\t\n" - "486000\t\t35\t\t0\t\t\n" - "594000\t\t45\t\t6\t\t\n" - "702000\t\t30\t\t29\t\t\n" - "810000\t\t5\t\t35\t\t\n" - "918000\t\t25\t\t25\t\t\n" - "1026000\t\t368\t\t134\t\t\n" - "1134000\t\t35\t\t15\t\t\n" - "1242000\t\t50\t\t50\t\t\n" - "1350000\t\t20\t\t61\t\t\n" - "1458000\t\t35\t\t5\t\t\n" - "1512000\t\t1642\t\t2152\t\t\n", + .content = "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\t\n" + "384000\t\t332\t\t71\t\t\n" + "486000\t\t35\t\t0\t\t\n" + "594000\t\t45\t\t6\t\t\n" + "702000\t\t30\t\t29\t\t\n" + "810000\t\t5\t\t35\t\t\n" + "918000\t\t25\t\t25\t\t\n" + "1026000\t\t368\t\t134\t\t\n" + "1134000\t\t35\t\t15\t\t\n" + "1242000\t\t50\t\t50\t\t\n" + "1350000\t\t20\t\t61\t\t\n" + "1458000\t\t35\t\t5\t\t\n" + "1512000\t\t1642\t\t2152\t\t\n", }, { .path = "/sys/devices/system/cpu/cpuidle/current_driver", @@ -209,7 +207,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies", .size = 91, - .content = "384000 486000 594000 702000 810000 918000 1026000 1134000 1242000 1350000 1458000 1512000 \n", + .content = + "384000 486000 594000 702000 810000 918000 1026000 1134000 1242000 1350000 1458000 1512000 \n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors", @@ -239,19 +238,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 129, - .content = - "384000 346\n" - "486000 35\n" - "594000 45\n" - "702000 30\n" - "810000 5\n" - "918000 25\n" - "1026000 392\n" - "1134000 35\n" - "1242000 50\n" - "1350000 20\n" - "1458000 45\n" - "1512000 1677\n", + .content = "384000 346\n" + "486000 35\n" + "594000 45\n" + "702000 30\n" + "810000 5\n" + "918000 25\n" + "1026000 392\n" + "1134000 35\n" + "1242000 50\n" + "1350000 20\n" + "1458000 45\n" + "1512000 1677\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -316,7 +314,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_frequencies", .size = 91, - .content = "384000 486000 594000 702000 810000 918000 1026000 1134000 1242000 1350000 1458000 1512000 \n", + .content = + "384000 486000 594000 702000 810000 918000 1026000 1134000 1242000 1350000 1458000 1512000 \n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_governors", @@ -351,19 +350,18 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 117, - .content = - "384000 3\n" - "486000 0\n" - "594000 5\n" - "702000 0\n" - "810000 0\n" - "918000 10\n" - "1026000 0\n" - "1134000 5\n" - "1242000 5\n" - "1350000 5\n" - "1458000 0\n" - "1512000 120\n", + .content = "384000 3\n" + "486000 0\n" + "594000 5\n" + "702000 0\n" + "810000 0\n" + "918000 10\n" + "1026000 0\n" + "1134000 5\n" + "1242000 5\n" + "1350000 5\n" + "1458000 0\n" + "1512000 120\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -428,7 +426,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_frequencies", .size = 91, - .content = "384000 486000 594000 702000 810000 918000 1026000 1134000 1242000 1350000 1458000 1512000 \n", + .content = + "384000 486000 594000 702000 810000 918000 1026000 1134000 1242000 1350000 1458000 1512000 \n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_governors", @@ -440,7 +439,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 7, .content = "384000\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ @@ -1161,6 +1160,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.driver.status", .value = "ok", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/nexus5x.cc b/test/mock/nexus5x.cc index 228bae0c..32a4c35d 100644 --- a/test/mock/nexus5x.cc +++ b/test/mock/nexus5x.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(6, cpuinfo_get_processors_count()); @@ -334,8 +333,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Qualcomm MSM8992", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Qualcomm MSM8992", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -377,59 +378,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -576,8 +577,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -639,8 +642,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -698,8 +703,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/nexus5x.h b/test/mock/nexus5x.h index b80b6db9..2a01e7c7 100644 --- a/test/mock/nexus5x.h +++ b/test/mock/nexus5x.h @@ -3,56 +3,55 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 1030, - .content = - "processor\t: 0\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 3\n" - "\n" - "processor\t: 1\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 3\n" - "\n" - "processor\t: 2\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 3\n" - "\n" - "processor\t: 3\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 3\n" - "\n" - "processor\t: 4\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x1\n" - "CPU part\t: 0xd07\n" - "CPU revision\t: 2\n" - "\n" - "processor\t: 5\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x1\n" - "CPU part\t: 0xd07\n" - "CPU revision\t: 2\n" - "\n" - "Hardware\t: Qualcomm Technologies, Inc MSM8992\n", + .content = "processor\t: 0\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 3\n" + "\n" + "processor\t: 1\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 3\n" + "\n" + "processor\t: 2\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 3\n" + "\n" + "processor\t: 3\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 3\n" + "\n" + "processor\t: 4\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0xd07\n" + "CPU revision\t: 2\n" + "\n" + "processor\t: 5\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0xd07\n" + "CPU revision\t: 2\n" + "\n" + "Hardware\t: Qualcomm Technologies, Inc MSM8992\n", }, #elif CPUINFO_ARCH_ARM { @@ -334,16 +333,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 95, - .content = - "384000 192\n" - "460800 44\n" - "600000 18\n" - "672000 5\n" - "787200 95\n" - "864000 42\n" - "960000 103\n" - "1248000 21\n" - "1440000 4796\n", + .content = "384000 192\n" + "460800 44\n" + "600000 18\n" + "672000 5\n" + "787200 95\n" + "864000 42\n" + "960000 103\n" + "1248000 21\n" + "1440000 4796\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -443,16 +441,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 95, - .content = - "384000 283\n" - "460800 51\n" - "600000 25\n" - "672000 5\n" - "787200 99\n" - "864000 42\n" - "960000 127\n" - "1248000 23\n" - "1440000 4899\n", + .content = "384000 283\n" + "460800 51\n" + "600000 25\n" + "672000 5\n" + "787200 99\n" + "864000 42\n" + "960000 127\n" + "1248000 23\n" + "1440000 4899\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -552,16 +549,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 95, - .content = - "384000 492\n" - "460800 59\n" - "600000 34\n" - "672000 5\n" - "787200 99\n" - "864000 42\n" - "960000 142\n" - "1248000 32\n" - "1440000 4899\n", + .content = "384000 492\n" + "460800 59\n" + "600000 34\n" + "672000 5\n" + "787200 99\n" + "864000 42\n" + "960000 142\n" + "1248000 32\n" + "1440000 4899\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -661,16 +657,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 95, - .content = - "384000 703\n" - "460800 76\n" - "600000 36\n" - "672000 5\n" - "787200 99\n" - "864000 42\n" - "960000 157\n" - "1248000 40\n" - "1440000 4922\n", + .content = "384000 703\n" + "460800 76\n" + "600000 36\n" + "672000 5\n" + "787200 99\n" + "864000 42\n" + "960000 157\n" + "1248000 40\n" + "1440000 4922\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -717,7 +712,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 9, .content = "msm_idle\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -1989,6 +1984,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wifi.supplicant_scan_interval", .value = "15", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/nexus6.cc b/test/mock/nexus6.cc index 07846071..0ce7563e 100644 --- a/test/mock/nexus6.cc +++ b/test/mock/nexus6.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(4, cpuinfo_get_processors_count()); @@ -208,8 +207,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Qualcomm APQ8084", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Qualcomm APQ8084", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -400,8 +401,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -452,8 +455,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -504,8 +509,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/nexus6.h b/test/mock/nexus6.h index f1994bf2..609a9495 100644 --- a/test/mock/nexus6.h +++ b/test/mock/nexus6.h @@ -2,53 +2,52 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 1136, - .content = - "processor\t: 0\n" - "model name\t: ARMv7 Processor rev 1 (v7l)\n" - "BogoMIPS\t: 38.40\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x3\n" - "CPU part\t: 0x06f\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 1\n" - "model name\t: ARMv7 Processor rev 1 (v7l)\n" - "BogoMIPS\t: 38.40\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x3\n" - "CPU part\t: 0x06f\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 2\n" - "model name\t: ARMv7 Processor rev 1 (v7l)\n" - "BogoMIPS\t: 38.40\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x3\n" - "CPU part\t: 0x06f\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 3\n" - "model name\t: ARMv7 Processor rev 1 (v7l)\n" - "BogoMIPS\t: 38.40\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x3\n" - "CPU part\t: 0x06f\n" - "CPU revision\t: 1\n" - "\n" - "Hardware\t: Qualcomm APQ 8084 (Flattened Device Tree)\n" - "Revision\t: 83a0\n" - "Serial\t\t: 68123d0111000000\n" - "Device\t\t: shamu\n" - "Radio\t\t: 6\n" - "MSM Hardware\t: APQ8084 ES1.1\n", + .content = "processor\t: 0\n" + "model name\t: ARMv7 Processor rev 1 (v7l)\n" + "BogoMIPS\t: 38.40\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x3\n" + "CPU part\t: 0x06f\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 1\n" + "model name\t: ARMv7 Processor rev 1 (v7l)\n" + "BogoMIPS\t: 38.40\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x3\n" + "CPU part\t: 0x06f\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 2\n" + "model name\t: ARMv7 Processor rev 1 (v7l)\n" + "BogoMIPS\t: 38.40\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x3\n" + "CPU part\t: 0x06f\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 3\n" + "model name\t: ARMv7 Processor rev 1 (v7l)\n" + "BogoMIPS\t: 38.40\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x3\n" + "CPU part\t: 0x06f\n" + "CPU revision\t: 1\n" + "\n" + "Hardware\t: Qualcomm APQ 8084 (Flattened Device Tree)\n" + "Revision\t: 83a0\n" + "Serial\t\t: 68123d0111000000\n" + "Device\t\t: shamu\n" + "Radio\t\t: 6\n" + "MSM Hardware\t: APQ8084 ES1.1\n", }, { .path = "/system/build.prop", @@ -278,7 +277,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies", .size = 139, - .content = "300000 422400 652800 729600 883200 960000 1036800 1190400 1267200 1497600 1574400 1728000 1958400 2265600 2457600 2496000 2572800 2649600 \n", + .content = + "300000 422400 652800 729600 883200 960000 1036800 1190400 1267200 1497600 1574400 1728000 1958400 2265600 2457600 2496000 2572800 2649600 \n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors", @@ -308,25 +308,24 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 190, - .content = - "300000 75\n" - "422400 8\n" - "652800 28\n" - "729600 18\n" - "883200 52\n" - "960000 36\n" - "1036800 42\n" - "1190400 38\n" - "1267200 50\n" - "1497600 224\n" - "1574400 64\n" - "1728000 2427\n" - "1958400 0\n" - "2265600 0\n" - "2457600 0\n" - "2496000 0\n" - "2572800 0\n" - "2649600 293\n", + .content = "300000 75\n" + "422400 8\n" + "652800 28\n" + "729600 18\n" + "883200 52\n" + "960000 36\n" + "1036800 42\n" + "1190400 38\n" + "1267200 50\n" + "1497600 224\n" + "1574400 64\n" + "1728000 2427\n" + "1958400 0\n" + "2265600 0\n" + "2457600 0\n" + "2496000 0\n" + "2572800 0\n" + "2649600 293\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -391,7 +390,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_frequencies", .size = 139, - .content = "300000 422400 652800 729600 883200 960000 1036800 1190400 1267200 1497600 1574400 1728000 1958400 2265600 2457600 2496000 2572800 2649600 \n", + .content = + "300000 422400 652800 729600 883200 960000 1036800 1190400 1267200 1497600 1574400 1728000 1958400 2265600 2457600 2496000 2572800 2649600 \n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_governors", @@ -426,25 +426,24 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 179, - .content = - "300000 0\n" - "422400 4\n" - "652800 0\n" - "729600 0\n" - "883200 0\n" - "960000 0\n" - "1036800 0\n" - "1190400 0\n" - "1267200 0\n" - "1497600 4\n" - "1574400 4\n" - "1728000 3242\n" - "1958400 0\n" - "2265600 0\n" - "2457600 0\n" - "2496000 0\n" - "2572800 0\n" - "2649600 376\n", + .content = "300000 0\n" + "422400 4\n" + "652800 0\n" + "729600 0\n" + "883200 0\n" + "960000 0\n" + "1036800 0\n" + "1190400 0\n" + "1267200 0\n" + "1497600 4\n" + "1574400 4\n" + "1728000 3242\n" + "1958400 0\n" + "2265600 0\n" + "2457600 0\n" + "2496000 0\n" + "2572800 0\n" + "2649600 376\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -481,7 +480,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "2\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ @@ -1574,6 +1573,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.driver.status", .value = "ok", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/nexus6p.cc b/test/mock/nexus6p.cc index 70e9f35e..f6713f5b 100644 --- a/test/mock/nexus6p.cc +++ b/test/mock/nexus6p.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(8, cpuinfo_get_processors_count()); @@ -334,8 +333,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Qualcomm MSM8994", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Qualcomm MSM8994", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -377,59 +378,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -580,8 +581,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -645,8 +648,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -704,8 +709,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/nexus6p.h b/test/mock/nexus6p.h index 95c1ed83..37b96685 100644 --- a/test/mock/nexus6p.h +++ b/test/mock/nexus6p.h @@ -3,24 +3,23 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 355, - .content = - "Processor\t: AArch64 Processor rev 2 (aarch64)\n" - "processor\t: 0\n" - "processor\t: 1\n" - "processor\t: 2\n" - "processor\t: 3\n" - "processor\t: 4\n" - "processor\t: 5\n" - "processor\t: 6\n" - "processor\t: 7\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 2\n" - "\n" - "Hardware\t: Qualcomm Technologies, Inc MSM8994\n", + .content = "Processor\t: AArch64 Processor rev 2 (aarch64)\n" + "processor\t: 0\n" + "processor\t: 1\n" + "processor\t: 2\n" + "processor\t: 3\n" + "processor\t: 4\n" + "processor\t: 5\n" + "processor\t: 6\n" + "processor\t: 7\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 2\n" + "\n" + "Hardware\t: Qualcomm Technologies, Inc MSM8994\n", }, #elif CPUINFO_ARCH_ARM { @@ -228,22 +227,21 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpufreq/all_time_in_state", .size = 659, - .content = - "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\t\n" - "384000\t\t28047\t\t0\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\t0\t\t\n" - "480000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\tN/A\t\tN/A\t\t0\t\t\n" - "633600\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\tN/A\t\tN/A\t\t0\t\t\n" - "768000\t\t66\t\t0\t\t0\t\t0\t\t10\t\tN/A\t\tN/A\t\t0\t\t\n" - "864000\t\t70\t\t0\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\t0\t\t\n" - "960000\t\t378\t\t0\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\t0\t\t\n" - "1248000\t\t3074\t\t0\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\t0\t\t\n" - "1344000\t\t572\t\t0\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\t0\t\t\n" - "1440000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\tN/A\t\tN/A\t\t0\t\t\n" - "1536000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\tN/A\t\tN/A\t\t0\t\t\n" - "1632000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\tN/A\t\tN/A\t\t0\t\t\n" - "1728000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\tN/A\t\tN/A\t\t0\t\t\n" - "1824000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\tN/A\t\tN/A\t\t0\t\t\n" - "1958400\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\tN/A\t\tN/A\t\t0\t\t\n", + .content = "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\t\n" + "384000\t\t28047\t\t0\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\t0\t\t\n" + "480000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\tN/A\t\tN/A\t\t0\t\t\n" + "633600\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\tN/A\t\tN/A\t\t0\t\t\n" + "768000\t\t66\t\t0\t\t0\t\t0\t\t10\t\tN/A\t\tN/A\t\t0\t\t\n" + "864000\t\t70\t\t0\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\t0\t\t\n" + "960000\t\t378\t\t0\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\t0\t\t\n" + "1248000\t\t3074\t\t0\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\t0\t\t\n" + "1344000\t\t572\t\t0\t\t0\t\t0\t\t0\t\tN/A\t\tN/A\t\t0\t\t\n" + "1440000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\tN/A\t\tN/A\t\t0\t\t\n" + "1536000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\tN/A\t\tN/A\t\t0\t\t\n" + "1632000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\tN/A\t\tN/A\t\t0\t\t\n" + "1728000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\tN/A\t\tN/A\t\t0\t\t\n" + "1824000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\tN/A\t\tN/A\t\t0\t\t\n" + "1958400\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\tN/A\t\tN/A\t\t0\t\t\n", }, { .path = "/sys/devices/system/cpu/cpufreq/current_in_state", @@ -331,18 +329,17 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 126, - .content = - "384000 28193\n" - "460800 226\n" - "600000 173\n" - "672000 58\n" - "768000 66\n" - "864000 70\n" - "960000 378\n" - "1248000 3074\n" - "1344000 572\n" - "1478400 199\n" - "1555200 7711\n", + .content = "384000 28193\n" + "460800 226\n" + "600000 173\n" + "672000 58\n" + "768000 66\n" + "864000 70\n" + "960000 378\n" + "1248000 3074\n" + "1344000 572\n" + "1478400 199\n" + "1555200 7711\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -442,18 +439,17 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 126, - .content = - "384000 28473\n" - "460800 226\n" - "600000 173\n" - "672000 58\n" - "768000 66\n" - "864000 70\n" - "960000 378\n" - "1248000 3074\n" - "1344000 572\n" - "1478400 199\n" - "1555200 7711\n", + .content = "384000 28473\n" + "460800 226\n" + "600000 173\n" + "672000 58\n" + "768000 66\n" + "864000 70\n" + "960000 378\n" + "1248000 3074\n" + "1344000 572\n" + "1478400 199\n" + "1555200 7711\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -553,18 +549,17 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 126, - .content = - "384000 28764\n" - "460800 226\n" - "600000 173\n" - "672000 58\n" - "768000 66\n" - "864000 70\n" - "960000 378\n" - "1248000 3074\n" - "1344000 572\n" - "1478400 199\n" - "1555200 7711\n", + .content = "384000 28764\n" + "460800 226\n" + "600000 173\n" + "672000 58\n" + "768000 66\n" + "864000 70\n" + "960000 378\n" + "1248000 3074\n" + "1344000 572\n" + "1478400 199\n" + "1555200 7711\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -664,18 +659,17 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 126, - .content = - "384000 29036\n" - "460800 226\n" - "600000 173\n" - "672000 58\n" - "768000 66\n" - "864000 70\n" - "960000 378\n" - "1248000 3074\n" - "1344000 572\n" - "1478400 199\n" - "1555200 7711\n", + .content = "384000 29036\n" + "460800 226\n" + "600000 173\n" + "672000 58\n" + "768000 66\n" + "864000 70\n" + "960000 378\n" + "1248000 3074\n" + "1344000 572\n" + "1478400 199\n" + "1555200 7711\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -732,7 +726,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 9, .content = "msm_idle\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -1924,6 +1918,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.driver.status", .value = "ok", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/nexus9.cc b/test/mock/nexus9.cc index 5d4fd8b8..352efcd3 100644 --- a/test/mock/nexus9.cc +++ b/test/mock/nexus9.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(2, cpuinfo_get_processors_count()); @@ -208,8 +207,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Nvidia Tegra T132", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Nvidia Tegra T132", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -251,59 +252,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -428,8 +429,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -480,8 +483,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -532,8 +537,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/nexus9.h b/test/mock/nexus9.h index adbfd00d..a2d20ca0 100644 --- a/test/mock/nexus9.h +++ b/test/mock/nexus9.h @@ -2,26 +2,25 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 369, - .content = - "processor\t: 0\n" - "BogoMIPS\t: 24.00\n" - "Features\t: fp asimd aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x4e\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0x000\n" - "CPU revision\t: 0\n" - "\n" - "processor\t: 1\n" - "BogoMIPS\t: 24.00\n" - "Features\t: fp asimd aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x4e\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0x000\n" - "CPU revision\t: 0\n" - "\n" - "MTS version\t: 33985182\n", + .content = "processor\t: 0\n" + "BogoMIPS\t: 24.00\n" + "Features\t: fp asimd aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x4e\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0x000\n" + "CPU revision\t: 0\n" + "\n" + "processor\t: 1\n" + "BogoMIPS\t: 24.00\n" + "Features\t: fp asimd aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x4e\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0x000\n" + "CPU revision\t: 0\n" + "\n" + "MTS version\t: 33985182\n", }, { .path = "/system/build.prop", @@ -172,56 +171,55 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpufreq/all_time_in_state", .size = 773, - .content = - "freq\t\tcpu0\t\tcpu1\t\t\n" - "204000\t\t0\t\t0\t\t\n" - "229500\t\t0\t\t0\t\t\n" - "255000\t\t0\t\t0\t\t\n" - "280500\t\t0\t\t0\t\t\n" - "306000\t\t0\t\t0\t\t\n" - "331500\t\t0\t\t0\t\t\n" - "357000\t\t0\t\t0\t\t\n" - "382500\t\t0\t\t0\t\t\n" - "408000\t\t0\t\t0\t\t\n" - "433500\t\t0\t\t0\t\t\n" - "459000\t\t0\t\t0\t\t\n" - "484500\t\t0\t\t0\t\t\n" - "510000\t\t11\t\t11\t\t\n" - "535500\t\t0\t\t0\t\t\n" - "561000\t\t0\t\t0\t\t\n" - "586500\t\t0\t\t0\t\t\n" - "612000\t\t2\t\t2\t\t\n" - "637500\t\t4\t\t4\t\t\n" - "663000\t\t0\t\t0\t\t\n" - "688500\t\t844\t\t844\t\t\n" - "714000\t\t2\t\t2\t\t\n" - "739500\t\t0\t\t0\t\t\n" - "765000\t\t0\t\t0\t\t\n" - "790500\t\t0\t\t0\t\t\n" - "816000\t\t3\t\t3\t\t\n" - "841500\t\t0\t\t0\t\t\n" - "867000\t\t0\t\t0\t\t\n" - "892500\t\t0\t\t0\t\t\n" - "918000\t\t0\t\t0\t\t\n" - "943500\t\t3\t\t3\t\t\n" - "969000\t\t0\t\t0\t\t\n" - "994500\t\t24\t\t24\t\t\n" - "1020000\t\t0\t\t0\t\t\n" - "1122000\t\t4\t\t4\t\t\n" - "1224000\t\t0\t\t0\t\t\n" - "1326000\t\t1\t\t1\t\t\n" - "1428000\t\t0\t\t0\t\t\n" - "1530000\t\t26\t\t26\t\t\n" - "1632000\t\t1\t\t1\t\t\n" - "1734000\t\t6\t\t6\t\t\n" - "1836000\t\t7\t\t7\t\t\n" - "1938000\t\t3\t\t3\t\t\n" - "2014500\t\t0\t\t0\t\t\n" - "2091000\t\t1\t\t1\t\t\n" - "2193000\t\t84\t\t84\t\t\n" - "2295000\t\t1467\t\t1467\t\t\n" - "2397000\t\t0\t\t0\t\t\n" - "2499000\t\t0\t\t0\t\t\n", + .content = "freq\t\tcpu0\t\tcpu1\t\t\n" + "204000\t\t0\t\t0\t\t\n" + "229500\t\t0\t\t0\t\t\n" + "255000\t\t0\t\t0\t\t\n" + "280500\t\t0\t\t0\t\t\n" + "306000\t\t0\t\t0\t\t\n" + "331500\t\t0\t\t0\t\t\n" + "357000\t\t0\t\t0\t\t\n" + "382500\t\t0\t\t0\t\t\n" + "408000\t\t0\t\t0\t\t\n" + "433500\t\t0\t\t0\t\t\n" + "459000\t\t0\t\t0\t\t\n" + "484500\t\t0\t\t0\t\t\n" + "510000\t\t11\t\t11\t\t\n" + "535500\t\t0\t\t0\t\t\n" + "561000\t\t0\t\t0\t\t\n" + "586500\t\t0\t\t0\t\t\n" + "612000\t\t2\t\t2\t\t\n" + "637500\t\t4\t\t4\t\t\n" + "663000\t\t0\t\t0\t\t\n" + "688500\t\t844\t\t844\t\t\n" + "714000\t\t2\t\t2\t\t\n" + "739500\t\t0\t\t0\t\t\n" + "765000\t\t0\t\t0\t\t\n" + "790500\t\t0\t\t0\t\t\n" + "816000\t\t3\t\t3\t\t\n" + "841500\t\t0\t\t0\t\t\n" + "867000\t\t0\t\t0\t\t\n" + "892500\t\t0\t\t0\t\t\n" + "918000\t\t0\t\t0\t\t\n" + "943500\t\t3\t\t3\t\t\n" + "969000\t\t0\t\t0\t\t\n" + "994500\t\t24\t\t24\t\t\n" + "1020000\t\t0\t\t0\t\t\n" + "1122000\t\t4\t\t4\t\t\n" + "1224000\t\t0\t\t0\t\t\n" + "1326000\t\t1\t\t1\t\t\n" + "1428000\t\t0\t\t0\t\t\n" + "1530000\t\t26\t\t26\t\t\n" + "1632000\t\t1\t\t1\t\t\n" + "1734000\t\t6\t\t6\t\t\n" + "1836000\t\t7\t\t7\t\t\n" + "1938000\t\t3\t\t3\t\t\n" + "2014500\t\t0\t\t0\t\t\n" + "2091000\t\t1\t\t1\t\t\n" + "2193000\t\t84\t\t84\t\t\n" + "2295000\t\t1467\t\t1467\t\t\n" + "2397000\t\t0\t\t0\t\t\n" + "2499000\t\t0\t\t0\t\t\n", }, { .path = "/sys/devices/system/cpu/cpufreq/current_in_state", @@ -268,7 +266,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies", .size = 353, - .content = "204000 229500 255000 280500 306000 331500 357000 382500 408000 433500 459000 484500 510000 535500 561000 586500 612000 637500 663000 688500 714000 739500 765000 790500 816000 841500 867000 892500 918000 943500 969000 994500 1020000 1122000 1224000 1326000 1428000 1530000 1632000 1734000 1836000 1938000 2014500 2091000 2193000 2295000 2397000 2499000 \n", + .content = + "204000 229500 255000 280500 306000 331500 357000 382500 408000 433500 459000 484500 510000 535500 561000 586500 612000 637500 663000 688500 714000 739500 765000 790500 816000 841500 867000 892500 918000 943500 969000 994500 1020000 1122000 1224000 1326000 1428000 1530000 1632000 1734000 1836000 1938000 2014500 2091000 2193000 2295000 2397000 2499000 \n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors", @@ -298,55 +297,54 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 459, - .content = - "204000 0\n" - "229500 0\n" - "255000 0\n" - "280500 0\n" - "306000 0\n" - "331500 0\n" - "357000 0\n" - "382500 0\n" - "408000 0\n" - "433500 0\n" - "459000 0\n" - "484500 0\n" - "510000 11\n" - "535500 0\n" - "561000 0\n" - "586500 0\n" - "612000 2\n" - "637500 4\n" - "663000 0\n" - "688500 844\n" - "714000 2\n" - "739500 0\n" - "765000 0\n" - "790500 0\n" - "816000 3\n" - "841500 0\n" - "867000 0\n" - "892500 0\n" - "918000 0\n" - "943500 3\n" - "969000 0\n" - "994500 24\n" - "1020000 0\n" - "1122000 4\n" - "1224000 0\n" - "1326000 1\n" - "1428000 0\n" - "1530000 28\n" - "1632000 8\n" - "1734000 11\n" - "1836000 11\n" - "1938000 3\n" - "2014500 0\n" - "2091000 3\n" - "2193000 89\n" - "2295000 1556\n" - "2397000 0\n" - "2499000 0\n", + .content = "204000 0\n" + "229500 0\n" + "255000 0\n" + "280500 0\n" + "306000 0\n" + "331500 0\n" + "357000 0\n" + "382500 0\n" + "408000 0\n" + "433500 0\n" + "459000 0\n" + "484500 0\n" + "510000 11\n" + "535500 0\n" + "561000 0\n" + "586500 0\n" + "612000 2\n" + "637500 4\n" + "663000 0\n" + "688500 844\n" + "714000 2\n" + "739500 0\n" + "765000 0\n" + "790500 0\n" + "816000 3\n" + "841500 0\n" + "867000 0\n" + "892500 0\n" + "918000 0\n" + "943500 3\n" + "969000 0\n" + "994500 24\n" + "1020000 0\n" + "1122000 4\n" + "1224000 0\n" + "1326000 1\n" + "1428000 0\n" + "1530000 28\n" + "1632000 8\n" + "1734000 11\n" + "1836000 11\n" + "1938000 3\n" + "2014500 0\n" + "2091000 3\n" + "2193000 89\n" + "2295000 1556\n" + "2397000 0\n" + "2499000 0\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -411,7 +409,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_frequencies", .size = 353, - .content = "204000 229500 255000 280500 306000 331500 357000 382500 408000 433500 459000 484500 510000 535500 561000 586500 612000 637500 663000 688500 714000 739500 765000 790500 816000 841500 867000 892500 918000 943500 969000 994500 1020000 1122000 1224000 1326000 1428000 1530000 1632000 1734000 1836000 1938000 2014500 2091000 2193000 2295000 2397000 2499000 \n", + .content = + "204000 229500 255000 280500 306000 331500 357000 382500 408000 433500 459000 484500 510000 535500 561000 586500 612000 637500 663000 688500 714000 739500 765000 790500 816000 841500 867000 892500 918000 943500 969000 994500 1020000 1122000 1224000 1326000 1428000 1530000 1632000 1734000 1836000 1938000 2014500 2091000 2193000 2295000 2397000 2499000 \n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_governors", @@ -441,55 +440,54 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 465, - .content = - "204000 0\n" - "229500 0\n" - "255000 0\n" - "280500 0\n" - "306000 0\n" - "331500 0\n" - "357000 0\n" - "382500 0\n" - "408000 0\n" - "433500 0\n" - "459000 0\n" - "484500 0\n" - "510000 84\n" - "535500 2\n" - "561000 2\n" - "586500 6\n" - "612000 4\n" - "637500 42\n" - "663000 11\n" - "688500 846\n" - "714000 10\n" - "739500 0\n" - "765000 15\n" - "790500 0\n" - "816000 3\n" - "841500 0\n" - "867000 0\n" - "892500 0\n" - "918000 0\n" - "943500 3\n" - "969000 0\n" - "994500 24\n" - "1020000 0\n" - "1122000 8\n" - "1224000 0\n" - "1326000 1\n" - "1428000 33\n" - "1530000 58\n" - "1632000 18\n" - "1734000 21\n" - "1836000 30\n" - "1938000 3\n" - "2014500 0\n" - "2091000 3\n" - "2193000 89\n" - "2295000 1556\n" - "2397000 0\n" - "2499000 0\n", + .content = "204000 0\n" + "229500 0\n" + "255000 0\n" + "280500 0\n" + "306000 0\n" + "331500 0\n" + "357000 0\n" + "382500 0\n" + "408000 0\n" + "433500 0\n" + "459000 0\n" + "484500 0\n" + "510000 84\n" + "535500 2\n" + "561000 2\n" + "586500 6\n" + "612000 4\n" + "637500 42\n" + "663000 11\n" + "688500 846\n" + "714000 10\n" + "739500 0\n" + "765000 15\n" + "790500 0\n" + "816000 3\n" + "841500 0\n" + "867000 0\n" + "892500 0\n" + "918000 0\n" + "943500 3\n" + "969000 0\n" + "994500 24\n" + "1020000 0\n" + "1122000 8\n" + "1224000 0\n" + "1326000 1\n" + "1428000 33\n" + "1530000 58\n" + "1632000 18\n" + "1734000 21\n" + "1836000 30\n" + "1938000 3\n" + "2014500 0\n" + "2091000 3\n" + "2193000 89\n" + "2295000 1556\n" + "2397000 0\n" + "2499000 0\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -526,7 +524,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "2\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ @@ -1363,6 +1361,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.driver.status", .value = "ok", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/oneplus-3t.cc b/test/mock/oneplus-3t.cc index 16728d12..d8e89516 100644 --- a/test/mock/oneplus-3t.cc +++ b/test/mock/oneplus-3t.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(4, cpuinfo_get_processors_count()); @@ -290,8 +289,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Qualcomm MSM8996PRO-AB", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Qualcomm MSM8996PRO-AB", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -333,59 +334,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -510,8 +511,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -562,8 +565,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -621,8 +626,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/oneplus-3t.h b/test/mock/oneplus-3t.h index 5cc2a764..b312bc20 100644 --- a/test/mock/oneplus-3t.h +++ b/test/mock/oneplus-3t.h @@ -3,44 +3,43 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 773, - .content = - "processor\t: 0\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x2\n" - "CPU part\t: 0x201\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 1\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x2\n" - "CPU part\t: 0x201\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 2\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x2\n" - "CPU part\t: 0x205\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 3\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x2\n" - "CPU part\t: 0x205\n" - "CPU revision\t: 1\n" - "\n" - "Hardware\t: Qualcomm Technologies, Inc MSM8996pro\n", + .content = "processor\t: 0\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x2\n" + "CPU part\t: 0x201\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 1\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x2\n" + "CPU part\t: 0x201\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 2\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x2\n" + "CPU part\t: 0x205\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 3\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x2\n" + "CPU part\t: 0x205\n" + "CPU revision\t: 1\n" + "\n" + "Hardware\t: Qualcomm Technologies, Inc MSM8996pro\n", }, #elif CPUINFO_ARCH_ARM { @@ -114,71 +113,67 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/soc0/image_crm_version", .size = 5, - .content = - "REL\n" - "\n", + .content = "REL\n" + "\n", }, { .path = "/sys/devices/soc0/image_variant", .size = 15, - .content = - "OnePlus3-user\n" - "\n", + .content = "OnePlus3-user\n" + "\n", }, { .path = "/sys/devices/soc0/image_version", .size = 22, - .content = - "10:OPR6.170623.013:5\n" - "\n", + .content = "10:OPR6.170623.013:5\n" + "\n", }, { .path = "/sys/devices/soc0/images", .size = 580, - .content = - "0:\n" - "\tCRM:\t\t00:BOOT.XF.1.0-00316\n" - "\tVariant:\tM8996LAB\n" - "\tVersion:\tubuntu-142\n" - "\n" - "1:\n" - "\tCRM:\t\t01:TZ.BF.4.0.1-123590\n" - "\tVariant:\t\n" - "\tVersion:\tCRM\n" - "\n" - "3:\n" - "\tCRM:\t\t03:RPM.BF.1.6-00153\n" - "\tVariant:\tAAAAANAAR\n" - "\tVersion:\tubuntu-142\n" - "\n" - "10:\n" - "\tCRM:\t\t10:OPR6.170623.013:5\n" - "\n" - "\tVariant:\tOnePlus3-user\n" - "\n" - "\tVersion:\tREL\n" - "\n" - "\n" - "11:\n" - "\tCRM:\t\t11:MPSS.TH.2.0.C1.9-119765\n" - "\tVariant:\t8996.gen.prodQ\n" - "\tVersion:\tubuntu-142\n" - "\n" - "12:\n" - "\tCRM:\t\t12:ADSP.8996.2.7.1.C3-00009\n" - "\tVariant:\tAAAAAAAAQ\n" - "\tVersion:\tubuntu-142\n" - "\n" - "14:\n" - "\tCRM:\t\t14:VIDEO.VE.4.2-00057\n" - "\tVariant:\tPROD\n" - "\tVersion:\t:CRM\n" - "\n" - "15:\n" - "\tCRM:\t\t15:SLPI.HB.1.0-00311\n" - "\tVariant:\tAAAAAAAAQ\n" - "\tVersion:\tubuntu-142\n" - "\n", + .content = "0:\n" + "\tCRM:\t\t00:BOOT.XF.1.0-00316\n" + "\tVariant:\tM8996LAB\n" + "\tVersion:\tubuntu-142\n" + "\n" + "1:\n" + "\tCRM:\t\t01:TZ.BF.4.0.1-123590\n" + "\tVariant:\t\n" + "\tVersion:\tCRM\n" + "\n" + "3:\n" + "\tCRM:\t\t03:RPM.BF.1.6-00153\n" + "\tVariant:\tAAAAANAAR\n" + "\tVersion:\tubuntu-142\n" + "\n" + "10:\n" + "\tCRM:\t\t10:OPR6.170623.013:5\n" + "\n" + "\tVariant:\tOnePlus3-user\n" + "\n" + "\tVersion:\tREL\n" + "\n" + "\n" + "11:\n" + "\tCRM:\t\t11:MPSS.TH.2.0.C1.9-119765\n" + "\tVariant:\t8996.gen.prodQ\n" + "\tVersion:\tubuntu-142\n" + "\n" + "12:\n" + "\tCRM:\t\t12:ADSP.8996.2.7.1.C3-00009\n" + "\tVariant:\tAAAAAAAAQ\n" + "\tVersion:\tubuntu-142\n" + "\n" + "14:\n" + "\tCRM:\t\t14:VIDEO.VE.4.2-00057\n" + "\tVariant:\tPROD\n" + "\tVersion:\t:CRM\n" + "\n" + "15:\n" + "\tCRM:\t\t15:SLPI.HB.1.0-00311\n" + "\tVariant:\tAAAAAAAAQ\n" + "\tVersion:\tubuntu-142\n" + "\n", }, { .path = "/sys/devices/soc0/machine", @@ -330,7 +325,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies", .size = 143, - .content = "307200 384000 460800 537600 614400 691200 768000 844800 902400 979200 1056000 1132800 1209600 1286400 1363200 1440000 1516800 1593600 2188800 \n", + .content = + "307200 384000 460800 537600 614400 691200 768000 844800 902400 979200 1056000 1132800 1209600 1286400 1363200 1440000 1516800 1593600 2188800 \n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors", @@ -360,26 +356,25 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 204, - .content = - "307200 1791\n" - "384000 60\n" - "460800 25\n" - "537600 18\n" - "614400 15\n" - "691200 10\n" - "768000 17\n" - "844800 23\n" - "902400 2\n" - "979200 221\n" - "1056000 19\n" - "1132800 14\n" - "1209600 13\n" - "1286400 28\n" - "1363200 55\n" - "1440000 12\n" - "1516800 11\n" - "1593600 3217\n" - "2188800 568\n", + .content = "307200 1791\n" + "384000 60\n" + "460800 25\n" + "537600 18\n" + "614400 15\n" + "691200 10\n" + "768000 17\n" + "844800 23\n" + "902400 2\n" + "979200 221\n" + "1056000 19\n" + "1132800 14\n" + "1209600 13\n" + "1286400 28\n" + "1363200 55\n" + "1440000 12\n" + "1516800 11\n" + "1593600 3217\n" + "2188800 568\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -449,7 +444,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_frequencies", .size = 143, - .content = "307200 384000 460800 537600 614400 691200 768000 844800 902400 979200 1056000 1132800 1209600 1286400 1363200 1440000 1516800 1593600 2188800 \n", + .content = + "307200 384000 460800 537600 614400 691200 768000 844800 902400 979200 1056000 1132800 1209600 1286400 1363200 1440000 1516800 1593600 2188800 \n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_governors", @@ -479,26 +475,25 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 204, - .content = - "307200 1955\n" - "384000 70\n" - "460800 33\n" - "537600 26\n" - "614400 20\n" - "691200 10\n" - "768000 17\n" - "844800 27\n" - "902400 7\n" - "979200 245\n" - "1056000 19\n" - "1132800 22\n" - "1209600 13\n" - "1286400 28\n" - "1363200 60\n" - "1440000 14\n" - "1516800 13\n" - "1593600 3240\n" - "2188800 568\n", + .content = "307200 1955\n" + "384000 70\n" + "460800 33\n" + "537600 26\n" + "614400 20\n" + "691200 10\n" + "768000 17\n" + "844800 27\n" + "902400 7\n" + "979200 245\n" + "1056000 19\n" + "1132800 22\n" + "1209600 13\n" + "1286400 28\n" + "1363200 60\n" + "1440000 14\n" + "1516800 13\n" + "1593600 3240\n" + "2188800 568\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -568,7 +563,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_frequencies", .size = 207, - .content = "307200 384000 460800 537600 614400 691200 748800 825600 902400 979200 1056000 1132800 1209600 1286400 1363200 1440000 1516800 1593600 1670400 1747200 1824000 1900800 1977600 2054400 2150400 2246400 2342400 \n", + .content = + "307200 384000 460800 537600 614400 691200 748800 825600 902400 979200 1056000 1132800 1209600 1286400 1363200 1440000 1516800 1593600 1670400 1747200 1824000 1900800 1977600 2054400 2150400 2246400 2342400 \n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_governors", @@ -603,34 +599,33 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 285, - .content = - "307200 1945\n" - "384000 40\n" - "460800 23\n" - "537600 23\n" - "614400 25\n" - "691200 21\n" - "748800 9\n" - "825600 16\n" - "902400 18\n" - "979200 17\n" - "1056000 22\n" - "1132800 31\n" - "1209600 18\n" - "1286400 321\n" - "1363200 43\n" - "1440000 14\n" - "1516800 50\n" - "1593600 11\n" - "1670400 4\n" - "1747200 4\n" - "1824000 0\n" - "1900800 0\n" - "1977600 10\n" - "2054400 0\n" - "2150400 90\n" - "2246400 6\n" - "2342400 3885\n", + .content = "307200 1945\n" + "384000 40\n" + "460800 23\n" + "537600 23\n" + "614400 25\n" + "691200 21\n" + "748800 9\n" + "825600 16\n" + "902400 18\n" + "979200 17\n" + "1056000 22\n" + "1132800 31\n" + "1209600 18\n" + "1286400 321\n" + "1363200 43\n" + "1440000 14\n" + "1516800 50\n" + "1593600 11\n" + "1670400 4\n" + "1747200 4\n" + "1824000 0\n" + "1900800 0\n" + "1977600 10\n" + "2054400 0\n" + "2150400 90\n" + "2246400 6\n" + "2342400 3885\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -700,7 +695,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_frequencies", .size = 207, - .content = "307200 384000 460800 537600 614400 691200 748800 825600 902400 979200 1056000 1132800 1209600 1286400 1363200 1440000 1516800 1593600 1670400 1747200 1824000 1900800 1977600 2054400 2150400 2246400 2342400 \n", + .content = + "307200 384000 460800 537600 614400 691200 748800 825600 902400 979200 1056000 1132800 1209600 1286400 1363200 1440000 1516800 1593600 1670400 1747200 1824000 1900800 1977600 2054400 2150400 2246400 2342400 \n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_governors", @@ -735,34 +731,33 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 285, - .content = - "307200 2186\n" - "384000 42\n" - "460800 23\n" - "537600 25\n" - "614400 25\n" - "691200 21\n" - "748800 9\n" - "825600 16\n" - "902400 18\n" - "979200 17\n" - "1056000 23\n" - "1132800 31\n" - "1209600 18\n" - "1286400 329\n" - "1363200 43\n" - "1440000 14\n" - "1516800 50\n" - "1593600 11\n" - "1670400 4\n" - "1747200 4\n" - "1824000 0\n" - "1900800 0\n" - "1977600 10\n" - "2054400 0\n" - "2150400 90\n" - "2246400 6\n" - "2342400 3889\n", + .content = "307200 2186\n" + "384000 42\n" + "460800 23\n" + "537600 25\n" + "614400 25\n" + "691200 21\n" + "748800 9\n" + "825600 16\n" + "902400 18\n" + "979200 17\n" + "1056000 23\n" + "1132800 31\n" + "1209600 18\n" + "1286400 329\n" + "1363200 43\n" + "1440000 14\n" + "1516800 50\n" + "1593600 11\n" + "1670400 4\n" + "1747200 4\n" + "1824000 0\n" + "1900800 0\n" + "1977600 10\n" + "2054400 0\n" + "2150400 90\n" + "2246400 6\n" + "2342400 3889\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -799,7 +794,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "3\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -3203,6 +3198,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wifi.interface", .value = "wlan0", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/oneplus-5.cc b/test/mock/oneplus-5.cc index 849e2446..11f197cd 100644 --- a/test/mock/oneplus-5.cc +++ b/test/mock/oneplus-5.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(8, cpuinfo_get_processors_count()); @@ -334,8 +333,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Qualcomm MSM8998", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Qualcomm MSM8998", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -377,59 +378,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -580,8 +581,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -658,8 +661,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -717,8 +722,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/oneplus-5.h b/test/mock/oneplus-5.h index 3976e09c..88db77bd 100644 --- a/test/mock/oneplus-5.h +++ b/test/mock/oneplus-5.h @@ -3,81 +3,80 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 1540, - .content = - "Processor\t: AArch64 Processor rev 4 (aarch64)\n" - "processor\t: 0\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0xa\n" - "CPU part\t: 0x801\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 1\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0xa\n" - "CPU part\t: 0x801\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 2\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0xa\n" - "CPU part\t: 0x801\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 3\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0xa\n" - "CPU part\t: 0x801\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 4\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0xa\n" - "CPU part\t: 0x800\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 5\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0xa\n" - "CPU part\t: 0x800\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 6\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0xa\n" - "CPU part\t: 0x800\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 7\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0xa\n" - "CPU part\t: 0x800\n" - "CPU revision\t: 1\n" - "\n" - "Hardware\t: Qualcomm Technologies, Inc MSM8998\n", + .content = "Processor\t: AArch64 Processor rev 4 (aarch64)\n" + "processor\t: 0\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0xa\n" + "CPU part\t: 0x801\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 1\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0xa\n" + "CPU part\t: 0x801\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 2\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0xa\n" + "CPU part\t: 0x801\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 3\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0xa\n" + "CPU part\t: 0x801\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 4\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0xa\n" + "CPU part\t: 0x800\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 5\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0xa\n" + "CPU part\t: 0x800\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 6\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0xa\n" + "CPU part\t: 0x800\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 7\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0xa\n" + "CPU part\t: 0x800\n" + "CPU revision\t: 1\n" + "\n" + "Hardware\t: Qualcomm Technologies, Inc MSM8998\n", }, #elif CPUINFO_ARCH_ARM { @@ -196,63 +195,59 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/soc0/image_crm_version", .size = 5, - .content = - "REL\n" - "\n", + .content = "REL\n" + "\n", }, { .path = "/sys/devices/soc0/image_variant", .size = 15, - .content = - "OnePlus5-user\n" - "\n", + .content = "OnePlus5-user\n" + "\n", }, { .path = "/sys/devices/soc0/image_version", .size = 24, - .content = - "10:OPR1.170623.032:119\n" - "\n", + .content = "10:OPR1.170623.032:119\n" + "\n", }, { .path = "/sys/devices/soc0/images", .size = 637, - .content = - "0:\n" - "\tCRM:\t\t00:BOOT.XF.1.2.2.c1-00021-M8998LZB-1\n" - "\tVariant:\tMsm8998LA\n" - "\tVersion:\t:ubuntu-23\n" - "1:\n" - "\tCRM:\t\t01:TZ.BF.4.0.6-00144\n" - "\tVariant:\t \n" - "\tVersion:\t:CRM\n" - "3:\n" - "\tCRM:\t\t03:RPM.BF.1.7-00128\n" - "\tVariant:\tAAAAANAZR\n" - "\tVersion:\t:ubuntu-23\n" - "10:\n" - "\tCRM:\t\t10:OPR1.170623.032:119\n" - "\n" - "\tVariant:\tOnePlus5-user\n" - "\n" - "\tVersion:\tREL\n" - "\n" - "11:\n" - "\tCRM:\t\t11:MPSS.AT.2.0.c4.7-00070-8998_GEN_PACK-2.130961.1.131284.2\n" - "\tVariant:\t8998.gen.prodQ\n" - "\tVersion:\t:ubuntu-23\n" - "12:\n" - "\tCRM:\t\t12:ADSP.HT.3.0-00366-CB8998-1\n" - "\tVariant:\tAAAAAAAAQ\n" - "\tVersion:\t:ubuntu-23\n" - "14:\n" - "\tCRM:\t\t14:VIDEO.VE.4.4-00031\n" - "\tVariant:\tPROD\n" - "\tVersion:\t\n" - "15:\n" - "\tCRM:\t\t15:SLPI.HB.2.0.c3-00012-M8998AZL-1\n" - "\tVariant:\tAAAAAAAAQ\n" - "\tVersion:\t:ubuntu-23\n", + .content = "0:\n" + "\tCRM:\t\t00:BOOT.XF.1.2.2.c1-00021-M8998LZB-1\n" + "\tVariant:\tMsm8998LA\n" + "\tVersion:\t:ubuntu-23\n" + "1:\n" + "\tCRM:\t\t01:TZ.BF.4.0.6-00144\n" + "\tVariant:\t \n" + "\tVersion:\t:CRM\n" + "3:\n" + "\tCRM:\t\t03:RPM.BF.1.7-00128\n" + "\tVariant:\tAAAAANAZR\n" + "\tVersion:\t:ubuntu-23\n" + "10:\n" + "\tCRM:\t\t10:OPR1.170623.032:119\n" + "\n" + "\tVariant:\tOnePlus5-user\n" + "\n" + "\tVersion:\tREL\n" + "\n" + "11:\n" + "\tCRM:\t\t11:MPSS.AT.2.0.c4.7-00070-8998_GEN_PACK-2.130961.1.131284.2\n" + "\tVariant:\t8998.gen.prodQ\n" + "\tVersion:\t:ubuntu-23\n" + "12:\n" + "\tCRM:\t\t12:ADSP.HT.3.0-00366-CB8998-1\n" + "\tVariant:\tAAAAAAAAQ\n" + "\tVersion:\t:ubuntu-23\n" + "14:\n" + "\tCRM:\t\t14:VIDEO.VE.4.4-00031\n" + "\tVariant:\tPROD\n" + "\tVersion:\t\n" + "15:\n" + "\tCRM:\t\t15:SLPI.HB.2.0.c3-00012-M8998AZL-1\n" + "\tVariant:\tAAAAAAAAQ\n" + "\tVersion:\t:ubuntu-23\n", }, { .path = "/sys/devices/soc0/machine", @@ -387,111 +382,110 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/core_ctl/global_state", .size = 1336, - .content = - "CPU0\n" - "\tCPU: 0\n" - "\tOnline: 1\n" - "\tIsolated: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 2\n" - "\tIs busy: 1\n" - "\tNot preferred: 0\n" - "\tNr running: 1\n" - "\tActive CPUs: 4\n" - "\tNeed CPUs: 4\n" - "\tNr isolated CPUs: 0\n" - "\tBoost: 0\n" - "CPU1\n" - "\tCPU: 1\n" - "\tOnline: 1\n" - "\tIsolated: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 4\n" - "\tIs busy: 1\n" - "\tNot preferred: 0\n" - "\tNr running: 1\n" - "\tActive CPUs: 4\n" - "\tNeed CPUs: 4\n" - "\tNr isolated CPUs: 0\n" - "\tBoost: 0\n" - "CPU2\n" - "\tCPU: 2\n" - "\tOnline: 1\n" - "\tIsolated: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 2\n" - "\tIs busy: 1\n" - "\tNot preferred: 0\n" - "\tNr running: 1\n" - "\tActive CPUs: 4\n" - "\tNeed CPUs: 4\n" - "\tNr isolated CPUs: 0\n" - "\tBoost: 0\n" - "CPU3\n" - "\tCPU: 3\n" - "\tOnline: 1\n" - "\tIsolated: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 2\n" - "\tIs busy: 1\n" - "\tNot preferred: 0\n" - "\tNr running: 1\n" - "\tActive CPUs: 4\n" - "\tNeed CPUs: 4\n" - "\tNr isolated CPUs: 0\n" - "\tBoost: 0\n" - "CPU4\n" - "\tCPU: 4\n" - "\tOnline: 1\n" - "\tIsolated: 0\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "\tNot preferred: 0\n" - "\tNr running: 0\n" - "\tActive CPUs: 2\n" - "\tNeed CPUs: 2\n" - "\tNr isolated CPUs: 2\n" - "\tBoost: 0\n" - "CPU5\n" - "\tCPU: 5\n" - "\tOnline: 1\n" - "\tIsolated: 1\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "\tNot preferred: 0\n" - "\tNr running: 0\n" - "\tActive CPUs: 2\n" - "\tNeed CPUs: 2\n" - "\tNr isolated CPUs: 2\n" - "\tBoost: 0\n" - "CPU6\n" - "\tCPU: 6\n" - "\tOnline: 1\n" - "\tIsolated: 1\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "\tNot preferred: 0\n" - "\tNr running: 0\n" - "\tActive CPUs: 2\n" - "\tNeed CPUs: 2\n" - "\tNr isolated CPUs: 2\n" - "\tBoost: 0\n" - "CPU7\n" - "\tCPU: 7\n" - "\tOnline: 1\n" - "\tIsolated: 0\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "\tNot preferred: 0\n" - "\tNr running: 0\n" - "\tActive CPUs: 2\n" - "\tNeed CPUs: 2\n" - "\tNr isolated CPUs: 2\n" - "\tBoost: 0\n", + .content = "CPU0\n" + "\tCPU: 0\n" + "\tOnline: 1\n" + "\tIsolated: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 2\n" + "\tIs busy: 1\n" + "\tNot preferred: 0\n" + "\tNr running: 1\n" + "\tActive CPUs: 4\n" + "\tNeed CPUs: 4\n" + "\tNr isolated CPUs: 0\n" + "\tBoost: 0\n" + "CPU1\n" + "\tCPU: 1\n" + "\tOnline: 1\n" + "\tIsolated: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 4\n" + "\tIs busy: 1\n" + "\tNot preferred: 0\n" + "\tNr running: 1\n" + "\tActive CPUs: 4\n" + "\tNeed CPUs: 4\n" + "\tNr isolated CPUs: 0\n" + "\tBoost: 0\n" + "CPU2\n" + "\tCPU: 2\n" + "\tOnline: 1\n" + "\tIsolated: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 2\n" + "\tIs busy: 1\n" + "\tNot preferred: 0\n" + "\tNr running: 1\n" + "\tActive CPUs: 4\n" + "\tNeed CPUs: 4\n" + "\tNr isolated CPUs: 0\n" + "\tBoost: 0\n" + "CPU3\n" + "\tCPU: 3\n" + "\tOnline: 1\n" + "\tIsolated: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 2\n" + "\tIs busy: 1\n" + "\tNot preferred: 0\n" + "\tNr running: 1\n" + "\tActive CPUs: 4\n" + "\tNeed CPUs: 4\n" + "\tNr isolated CPUs: 0\n" + "\tBoost: 0\n" + "CPU4\n" + "\tCPU: 4\n" + "\tOnline: 1\n" + "\tIsolated: 0\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "\tNot preferred: 0\n" + "\tNr running: 0\n" + "\tActive CPUs: 2\n" + "\tNeed CPUs: 2\n" + "\tNr isolated CPUs: 2\n" + "\tBoost: 0\n" + "CPU5\n" + "\tCPU: 5\n" + "\tOnline: 1\n" + "\tIsolated: 1\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "\tNot preferred: 0\n" + "\tNr running: 0\n" + "\tActive CPUs: 2\n" + "\tNeed CPUs: 2\n" + "\tNr isolated CPUs: 2\n" + "\tBoost: 0\n" + "CPU6\n" + "\tCPU: 6\n" + "\tOnline: 1\n" + "\tIsolated: 1\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "\tNot preferred: 0\n" + "\tNr running: 0\n" + "\tActive CPUs: 2\n" + "\tNeed CPUs: 2\n" + "\tNr isolated CPUs: 2\n" + "\tBoost: 0\n" + "CPU7\n" + "\tCPU: 7\n" + "\tOnline: 1\n" + "\tIsolated: 0\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "\tNot preferred: 0\n" + "\tNr running: 0\n" + "\tActive CPUs: 2\n" + "\tNeed CPUs: 2\n" + "\tNr isolated CPUs: 2\n" + "\tBoost: 0\n", }, { .path = "/sys/devices/system/cpu/cpu0/core_ctl/is_big_cluster", @@ -516,11 +510,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/core_ctl/not_preferred", .size = 36, - .content = - "CPU#0: 0\n" - "CPU#1: 0\n" - "CPU#2: 0\n" - "CPU#3: 0\n", + .content = "CPU#0: 0\n" + "CPU#1: 0\n" + "CPU#2: 0\n" + "CPU#3: 0\n", }, { .path = "/sys/devices/system/cpu/cpu0/core_ctl/offline_delay_ms", @@ -565,7 +558,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies", .size = 167, - .content = "300000 364800 441600 518400 595200 672000 748800 825600 883200 960000 1036800 1094400 1171200 1248000 1324800 1401600 1478400 1555200 1670400 1747200 1824000 1900800 \n", + .content = + "300000 364800 441600 518400 595200 672000 748800 825600 883200 960000 1036800 1094400 1171200 1248000 1324800 1401600 1478400 1555200 1670400 1747200 1824000 1900800 \n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors", @@ -595,29 +589,28 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 234, - .content = - "300000 0\n" - "364800 0\n" - "441600 0\n" - "518400 2291\n" - "595200 25\n" - "672000 32\n" - "748800 31\n" - "825600 31\n" - "883200 23\n" - "960000 20\n" - "1036800 35\n" - "1094400 4\n" - "1171200 12\n" - "1248000 548\n" - "1324800 53\n" - "1401600 14\n" - "1478400 31\n" - "1555200 60\n" - "1670400 40\n" - "1747200 20\n" - "1824000 156\n" - "1900800 4081\n", + .content = "300000 0\n" + "364800 0\n" + "441600 0\n" + "518400 2291\n" + "595200 25\n" + "672000 32\n" + "748800 31\n" + "825600 31\n" + "883200 23\n" + "960000 20\n" + "1036800 35\n" + "1094400 4\n" + "1171200 12\n" + "1248000 548\n" + "1324800 53\n" + "1401600 14\n" + "1478400 31\n" + "1555200 60\n" + "1670400 40\n" + "1747200 20\n" + "1824000 156\n" + "1900800 4081\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -837,7 +830,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_frequencies", .size = 167, - .content = "300000 364800 441600 518400 595200 672000 748800 825600 883200 960000 1036800 1094400 1171200 1248000 1324800 1401600 1478400 1555200 1670400 1747200 1824000 1900800 \n", + .content = + "300000 364800 441600 518400 595200 672000 748800 825600 883200 960000 1036800 1094400 1171200 1248000 1324800 1401600 1478400 1555200 1670400 1747200 1824000 1900800 \n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_governors", @@ -867,29 +861,28 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 234, - .content = - "300000 0\n" - "364800 0\n" - "441600 0\n" - "518400 2482\n" - "595200 25\n" - "672000 32\n" - "748800 31\n" - "825600 31\n" - "883200 23\n" - "960000 20\n" - "1036800 35\n" - "1094400 4\n" - "1171200 12\n" - "1248000 564\n" - "1324800 53\n" - "1401600 17\n" - "1478400 31\n" - "1555200 70\n" - "1670400 48\n" - "1747200 22\n" - "1824000 176\n" - "1900800 4115\n", + .content = "300000 0\n" + "364800 0\n" + "441600 0\n" + "518400 2482\n" + "595200 25\n" + "672000 32\n" + "748800 31\n" + "825600 31\n" + "883200 23\n" + "960000 20\n" + "1036800 35\n" + "1094400 4\n" + "1171200 12\n" + "1248000 564\n" + "1324800 53\n" + "1401600 17\n" + "1478400 31\n" + "1555200 70\n" + "1670400 48\n" + "1747200 22\n" + "1824000 176\n" + "1900800 4115\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -1109,7 +1102,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_frequencies", .size = 167, - .content = "300000 364800 441600 518400 595200 672000 748800 825600 883200 960000 1036800 1094400 1171200 1248000 1324800 1401600 1478400 1555200 1670400 1747200 1824000 1900800 \n", + .content = + "300000 364800 441600 518400 595200 672000 748800 825600 883200 960000 1036800 1094400 1171200 1248000 1324800 1401600 1478400 1555200 1670400 1747200 1824000 1900800 \n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_governors", @@ -1139,29 +1133,28 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 234, - .content = - "300000 0\n" - "364800 0\n" - "441600 0\n" - "518400 2769\n" - "595200 25\n" - "672000 32\n" - "748800 33\n" - "825600 31\n" - "883200 23\n" - "960000 20\n" - "1036800 35\n" - "1094400 4\n" - "1171200 12\n" - "1248000 596\n" - "1324800 53\n" - "1401600 17\n" - "1478400 31\n" - "1555200 70\n" - "1670400 48\n" - "1747200 22\n" - "1824000 176\n" - "1900800 4121\n", + .content = "300000 0\n" + "364800 0\n" + "441600 0\n" + "518400 2769\n" + "595200 25\n" + "672000 32\n" + "748800 33\n" + "825600 31\n" + "883200 23\n" + "960000 20\n" + "1036800 35\n" + "1094400 4\n" + "1171200 12\n" + "1248000 596\n" + "1324800 53\n" + "1401600 17\n" + "1478400 31\n" + "1555200 70\n" + "1670400 48\n" + "1747200 22\n" + "1824000 176\n" + "1900800 4121\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -1381,7 +1374,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_frequencies", .size = 167, - .content = "300000 364800 441600 518400 595200 672000 748800 825600 883200 960000 1036800 1094400 1171200 1248000 1324800 1401600 1478400 1555200 1670400 1747200 1824000 1900800 \n", + .content = + "300000 364800 441600 518400 595200 672000 748800 825600 883200 960000 1036800 1094400 1171200 1248000 1324800 1401600 1478400 1555200 1670400 1747200 1824000 1900800 \n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_governors", @@ -1411,29 +1405,28 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 234, - .content = - "300000 0\n" - "364800 0\n" - "441600 0\n" - "518400 3023\n" - "595200 25\n" - "672000 32\n" - "748800 33\n" - "825600 31\n" - "883200 23\n" - "960000 20\n" - "1036800 35\n" - "1094400 4\n" - "1171200 16\n" - "1248000 624\n" - "1324800 53\n" - "1401600 19\n" - "1478400 31\n" - "1555200 70\n" - "1670400 48\n" - "1747200 22\n" - "1824000 176\n" - "1900800 4133\n", + .content = "300000 0\n" + "364800 0\n" + "441600 0\n" + "518400 3023\n" + "595200 25\n" + "672000 32\n" + "748800 33\n" + "825600 31\n" + "883200 23\n" + "960000 20\n" + "1036800 35\n" + "1094400 4\n" + "1171200 16\n" + "1248000 624\n" + "1324800 53\n" + "1401600 19\n" + "1478400 31\n" + "1555200 70\n" + "1670400 48\n" + "1747200 22\n" + "1824000 176\n" + "1900800 4133\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -1643,111 +1636,110 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/core_ctl/global_state", .size = 1336, - .content = - "CPU0\n" - "\tCPU: 0\n" - "\tOnline: 1\n" - "\tIsolated: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 1\n" - "\tIs busy: 1\n" - "\tNot preferred: 0\n" - "\tNr running: 1\n" - "\tActive CPUs: 4\n" - "\tNeed CPUs: 4\n" - "\tNr isolated CPUs: 0\n" - "\tBoost: 0\n" - "CPU1\n" - "\tCPU: 1\n" - "\tOnline: 1\n" - "\tIsolated: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 1\n" - "\tIs busy: 1\n" - "\tNot preferred: 0\n" - "\tNr running: 1\n" - "\tActive CPUs: 4\n" - "\tNeed CPUs: 4\n" - "\tNr isolated CPUs: 0\n" - "\tBoost: 0\n" - "CPU2\n" - "\tCPU: 2\n" - "\tOnline: 1\n" - "\tIsolated: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 0\n" - "\tIs busy: 1\n" - "\tNot preferred: 0\n" - "\tNr running: 1\n" - "\tActive CPUs: 4\n" - "\tNeed CPUs: 4\n" - "\tNr isolated CPUs: 0\n" - "\tBoost: 0\n" - "CPU3\n" - "\tCPU: 3\n" - "\tOnline: 1\n" - "\tIsolated: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 4\n" - "\tIs busy: 1\n" - "\tNot preferred: 0\n" - "\tNr running: 1\n" - "\tActive CPUs: 4\n" - "\tNeed CPUs: 4\n" - "\tNr isolated CPUs: 0\n" - "\tBoost: 0\n" - "CPU4\n" - "\tCPU: 4\n" - "\tOnline: 1\n" - "\tIsolated: 0\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "\tNot preferred: 0\n" - "\tNr running: 0\n" - "\tActive CPUs: 2\n" - "\tNeed CPUs: 2\n" - "\tNr isolated CPUs: 2\n" - "\tBoost: 0\n" - "CPU5\n" - "\tCPU: 5\n" - "\tOnline: 1\n" - "\tIsolated: 1\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "\tNot preferred: 0\n" - "\tNr running: 0\n" - "\tActive CPUs: 2\n" - "\tNeed CPUs: 2\n" - "\tNr isolated CPUs: 2\n" - "\tBoost: 0\n" - "CPU6\n" - "\tCPU: 6\n" - "\tOnline: 1\n" - "\tIsolated: 1\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "\tNot preferred: 0\n" - "\tNr running: 0\n" - "\tActive CPUs: 2\n" - "\tNeed CPUs: 2\n" - "\tNr isolated CPUs: 2\n" - "\tBoost: 0\n" - "CPU7\n" - "\tCPU: 7\n" - "\tOnline: 1\n" - "\tIsolated: 0\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "\tNot preferred: 0\n" - "\tNr running: 0\n" - "\tActive CPUs: 2\n" - "\tNeed CPUs: 2\n" - "\tNr isolated CPUs: 2\n" - "\tBoost: 0\n", + .content = "CPU0\n" + "\tCPU: 0\n" + "\tOnline: 1\n" + "\tIsolated: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 1\n" + "\tIs busy: 1\n" + "\tNot preferred: 0\n" + "\tNr running: 1\n" + "\tActive CPUs: 4\n" + "\tNeed CPUs: 4\n" + "\tNr isolated CPUs: 0\n" + "\tBoost: 0\n" + "CPU1\n" + "\tCPU: 1\n" + "\tOnline: 1\n" + "\tIsolated: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 1\n" + "\tIs busy: 1\n" + "\tNot preferred: 0\n" + "\tNr running: 1\n" + "\tActive CPUs: 4\n" + "\tNeed CPUs: 4\n" + "\tNr isolated CPUs: 0\n" + "\tBoost: 0\n" + "CPU2\n" + "\tCPU: 2\n" + "\tOnline: 1\n" + "\tIsolated: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 0\n" + "\tIs busy: 1\n" + "\tNot preferred: 0\n" + "\tNr running: 1\n" + "\tActive CPUs: 4\n" + "\tNeed CPUs: 4\n" + "\tNr isolated CPUs: 0\n" + "\tBoost: 0\n" + "CPU3\n" + "\tCPU: 3\n" + "\tOnline: 1\n" + "\tIsolated: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 4\n" + "\tIs busy: 1\n" + "\tNot preferred: 0\n" + "\tNr running: 1\n" + "\tActive CPUs: 4\n" + "\tNeed CPUs: 4\n" + "\tNr isolated CPUs: 0\n" + "\tBoost: 0\n" + "CPU4\n" + "\tCPU: 4\n" + "\tOnline: 1\n" + "\tIsolated: 0\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "\tNot preferred: 0\n" + "\tNr running: 0\n" + "\tActive CPUs: 2\n" + "\tNeed CPUs: 2\n" + "\tNr isolated CPUs: 2\n" + "\tBoost: 0\n" + "CPU5\n" + "\tCPU: 5\n" + "\tOnline: 1\n" + "\tIsolated: 1\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "\tNot preferred: 0\n" + "\tNr running: 0\n" + "\tActive CPUs: 2\n" + "\tNeed CPUs: 2\n" + "\tNr isolated CPUs: 2\n" + "\tBoost: 0\n" + "CPU6\n" + "\tCPU: 6\n" + "\tOnline: 1\n" + "\tIsolated: 1\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "\tNot preferred: 0\n" + "\tNr running: 0\n" + "\tActive CPUs: 2\n" + "\tNeed CPUs: 2\n" + "\tNr isolated CPUs: 2\n" + "\tBoost: 0\n" + "CPU7\n" + "\tCPU: 7\n" + "\tOnline: 1\n" + "\tIsolated: 0\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "\tNot preferred: 0\n" + "\tNr running: 0\n" + "\tActive CPUs: 2\n" + "\tNeed CPUs: 2\n" + "\tNr isolated CPUs: 2\n" + "\tBoost: 0\n", }, { .path = "/sys/devices/system/cpu/cpu4/core_ctl/is_big_cluster", @@ -1772,11 +1764,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/core_ctl/not_preferred", .size = 36, - .content = - "CPU#4: 0\n" - "CPU#5: 0\n" - "CPU#6: 0\n" - "CPU#7: 0\n", + .content = "CPU#4: 0\n" + "CPU#5: 0\n" + "CPU#6: 0\n" + "CPU#7: 0\n", }, { .path = "/sys/devices/system/cpu/cpu4/core_ctl/offline_delay_ms", @@ -1821,7 +1812,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_available_frequencies", .size = 239, - .content = "300000 345600 422400 499200 576000 652800 729600 806400 902400 979200 1056000 1132800 1190400 1267200 1344000 1420800 1497600 1574400 1651200 1728000 1804800 1881600 1958400 2035200 2112000 2208000 2265600 2323200 2342400 2361600 2457600 \n", + .content = + "300000 345600 422400 499200 576000 652800 729600 806400 902400 979200 1056000 1132800 1190400 1267200 1344000 1420800 1497600 1574400 1651200 1728000 1804800 1881600 1958400 2035200 2112000 2208000 2265600 2323200 2342400 2361600 2457600 \n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_available_governors", @@ -1856,38 +1848,37 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/time_in_state", .size = 323, - .content = - "300000 0\n" - "345600 0\n" - "422400 0\n" - "499200 0\n" - "576000 0\n" - "652800 0\n" - "729600 0\n" - "806400 5163\n" - "902400 16\n" - "979200 19\n" - "1056000 14\n" - "1132800 16\n" - "1190400 5\n" - "1267200 15\n" - "1344000 10\n" - "1420800 16\n" - "1497600 12\n" - "1574400 239\n" - "1651200 14\n" - "1728000 19\n" - "1804800 9\n" - "1881600 5\n" - "1958400 31\n" - "2035200 16\n" - "2112000 9\n" - "2208000 1\n" - "2265600 4\n" - "2323200 3\n" - "2342400 1\n" - "2361600 1990\n" - "2457600 1104\n", + .content = "300000 0\n" + "345600 0\n" + "422400 0\n" + "499200 0\n" + "576000 0\n" + "652800 0\n" + "729600 0\n" + "806400 5163\n" + "902400 16\n" + "979200 19\n" + "1056000 14\n" + "1132800 16\n" + "1190400 5\n" + "1267200 15\n" + "1344000 10\n" + "1420800 16\n" + "1497600 12\n" + "1574400 239\n" + "1651200 14\n" + "1728000 19\n" + "1804800 9\n" + "1881600 5\n" + "1958400 31\n" + "2035200 16\n" + "2112000 9\n" + "2208000 1\n" + "2265600 4\n" + "2323200 3\n" + "2342400 1\n" + "2361600 1990\n" + "2457600 1104\n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/total_trans", @@ -2107,7 +2098,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_available_frequencies", .size = 239, - .content = "300000 345600 422400 499200 576000 652800 729600 806400 902400 979200 1056000 1132800 1190400 1267200 1344000 1420800 1497600 1574400 1651200 1728000 1804800 1881600 1958400 2035200 2112000 2208000 2265600 2323200 2342400 2361600 2457600 \n", + .content = + "300000 345600 422400 499200 576000 652800 729600 806400 902400 979200 1056000 1132800 1190400 1267200 1344000 1420800 1497600 1574400 1651200 1728000 1804800 1881600 1958400 2035200 2112000 2208000 2265600 2323200 2342400 2361600 2457600 \n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_available_governors", @@ -2142,38 +2134,37 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/time_in_state", .size = 323, - .content = - "300000 0\n" - "345600 0\n" - "422400 0\n" - "499200 0\n" - "576000 0\n" - "652800 0\n" - "729600 0\n" - "806400 5477\n" - "902400 16\n" - "979200 19\n" - "1056000 14\n" - "1132800 16\n" - "1190400 5\n" - "1267200 15\n" - "1344000 10\n" - "1420800 16\n" - "1497600 12\n" - "1574400 239\n" - "1651200 14\n" - "1728000 19\n" - "1804800 9\n" - "1881600 5\n" - "1958400 31\n" - "2035200 16\n" - "2112000 9\n" - "2208000 1\n" - "2265600 4\n" - "2323200 3\n" - "2342400 1\n" - "2361600 1990\n" - "2457600 1104\n", + .content = "300000 0\n" + "345600 0\n" + "422400 0\n" + "499200 0\n" + "576000 0\n" + "652800 0\n" + "729600 0\n" + "806400 5477\n" + "902400 16\n" + "979200 19\n" + "1056000 14\n" + "1132800 16\n" + "1190400 5\n" + "1267200 15\n" + "1344000 10\n" + "1420800 16\n" + "1497600 12\n" + "1574400 239\n" + "1651200 14\n" + "1728000 19\n" + "1804800 9\n" + "1881600 5\n" + "1958400 31\n" + "2035200 16\n" + "2112000 9\n" + "2208000 1\n" + "2265600 4\n" + "2323200 3\n" + "2342400 1\n" + "2361600 1990\n" + "2457600 1104\n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/total_trans", @@ -2393,7 +2384,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_available_frequencies", .size = 239, - .content = "300000 345600 422400 499200 576000 652800 729600 806400 902400 979200 1056000 1132800 1190400 1267200 1344000 1420800 1497600 1574400 1651200 1728000 1804800 1881600 1958400 2035200 2112000 2208000 2265600 2323200 2342400 2361600 2457600 \n", + .content = + "300000 345600 422400 499200 576000 652800 729600 806400 902400 979200 1056000 1132800 1190400 1267200 1344000 1420800 1497600 1574400 1651200 1728000 1804800 1881600 1958400 2035200 2112000 2208000 2265600 2323200 2342400 2361600 2457600 \n", }, { .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_available_governors", @@ -2428,38 +2420,37 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/time_in_state", .size = 323, - .content = - "300000 0\n" - "345600 0\n" - "422400 0\n" - "499200 0\n" - "576000 0\n" - "652800 0\n" - "729600 0\n" - "806400 5834\n" - "902400 16\n" - "979200 19\n" - "1056000 14\n" - "1132800 16\n" - "1190400 5\n" - "1267200 15\n" - "1344000 10\n" - "1420800 16\n" - "1497600 12\n" - "1574400 239\n" - "1651200 14\n" - "1728000 19\n" - "1804800 9\n" - "1881600 5\n" - "1958400 31\n" - "2035200 16\n" - "2112000 9\n" - "2208000 1\n" - "2265600 4\n" - "2323200 3\n" - "2342400 1\n" - "2361600 1990\n" - "2457600 1104\n", + .content = "300000 0\n" + "345600 0\n" + "422400 0\n" + "499200 0\n" + "576000 0\n" + "652800 0\n" + "729600 0\n" + "806400 5834\n" + "902400 16\n" + "979200 19\n" + "1056000 14\n" + "1132800 16\n" + "1190400 5\n" + "1267200 15\n" + "1344000 10\n" + "1420800 16\n" + "1497600 12\n" + "1574400 239\n" + "1651200 14\n" + "1728000 19\n" + "1804800 9\n" + "1881600 5\n" + "1958400 31\n" + "2035200 16\n" + "2112000 9\n" + "2208000 1\n" + "2265600 4\n" + "2323200 3\n" + "2342400 1\n" + "2361600 1990\n" + "2457600 1104\n", }, { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/total_trans", @@ -2679,7 +2670,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_available_frequencies", .size = 239, - .content = "300000 345600 422400 499200 576000 652800 729600 806400 902400 979200 1056000 1132800 1190400 1267200 1344000 1420800 1497600 1574400 1651200 1728000 1804800 1881600 1958400 2035200 2112000 2208000 2265600 2323200 2342400 2361600 2457600 \n", + .content = + "300000 345600 422400 499200 576000 652800 729600 806400 902400 979200 1056000 1132800 1190400 1267200 1344000 1420800 1497600 1574400 1651200 1728000 1804800 1881600 1958400 2035200 2112000 2208000 2265600 2323200 2342400 2361600 2457600 \n", }, { .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_available_governors", @@ -2714,38 +2706,37 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/time_in_state", .size = 323, - .content = - "300000 0\n" - "345600 0\n" - "422400 0\n" - "499200 0\n" - "576000 0\n" - "652800 0\n" - "729600 0\n" - "806400 6189\n" - "902400 16\n" - "979200 19\n" - "1056000 14\n" - "1132800 16\n" - "1190400 5\n" - "1267200 15\n" - "1344000 10\n" - "1420800 16\n" - "1497600 12\n" - "1574400 239\n" - "1651200 14\n" - "1728000 19\n" - "1804800 9\n" - "1881600 5\n" - "1958400 31\n" - "2035200 16\n" - "2112000 9\n" - "2208000 1\n" - "2265600 4\n" - "2323200 3\n" - "2342400 1\n" - "2361600 1990\n" - "2457600 1104\n", + .content = "300000 0\n" + "345600 0\n" + "422400 0\n" + "499200 0\n" + "576000 0\n" + "652800 0\n" + "729600 0\n" + "806400 6189\n" + "902400 16\n" + "979200 19\n" + "1056000 14\n" + "1132800 16\n" + "1190400 5\n" + "1267200 15\n" + "1344000 10\n" + "1420800 16\n" + "1497600 12\n" + "1574400 239\n" + "1651200 14\n" + "1728000 19\n" + "1804800 9\n" + "1881600 5\n" + "1958400 31\n" + "2035200 16\n" + "2112000 9\n" + "2208000 1\n" + "2265600 4\n" + "2323200 3\n" + "2342400 1\n" + "2361600 1990\n" + "2457600 1104\n", }, { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/total_trans", @@ -2932,7 +2923,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 10, .content = "WriteBack\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -5384,6 +5375,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wifi.interface", .value = "wlan0", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/oneplus-5t.cc b/test/mock/oneplus-5t.cc index e58ebfe4..4416f490 100644 --- a/test/mock/oneplus-5t.cc +++ b/test/mock/oneplus-5t.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(8, cpuinfo_get_processors_count()); @@ -334,8 +333,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Qualcomm MSM8998", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Qualcomm MSM8998", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -377,59 +378,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -580,8 +581,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -658,8 +661,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -717,8 +722,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/oneplus-5t.h b/test/mock/oneplus-5t.h index a5057f2a..d13f1973 100644 --- a/test/mock/oneplus-5t.h +++ b/test/mock/oneplus-5t.h @@ -3,81 +3,80 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 1540, - .content = - "Processor\t: AArch64 Processor rev 4 (aarch64)\n" - "processor\t: 0\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0xa\n" - "CPU part\t: 0x801\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 1\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0xa\n" - "CPU part\t: 0x801\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 2\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0xa\n" - "CPU part\t: 0x801\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 3\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0xa\n" - "CPU part\t: 0x801\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 4\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0xa\n" - "CPU part\t: 0x800\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 5\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0xa\n" - "CPU part\t: 0x800\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 6\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0xa\n" - "CPU part\t: 0x800\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 7\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0xa\n" - "CPU part\t: 0x800\n" - "CPU revision\t: 1\n" - "\n" - "Hardware\t: Qualcomm Technologies, Inc MSM8998\n", + .content = "Processor\t: AArch64 Processor rev 4 (aarch64)\n" + "processor\t: 0\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0xa\n" + "CPU part\t: 0x801\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 1\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0xa\n" + "CPU part\t: 0x801\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 2\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0xa\n" + "CPU part\t: 0x801\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 3\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0xa\n" + "CPU part\t: 0x801\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 4\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0xa\n" + "CPU part\t: 0x800\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 5\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0xa\n" + "CPU part\t: 0x800\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 6\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0xa\n" + "CPU part\t: 0x800\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 7\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0xa\n" + "CPU part\t: 0x800\n" + "CPU revision\t: 1\n" + "\n" + "Hardware\t: Qualcomm Technologies, Inc MSM8998\n", }, #elif CPUINFO_ARCH_ARM { @@ -196,63 +195,59 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/soc0/image_crm_version", .size = 5, - .content = - "REL\n" - "\n", + .content = "REL\n" + "\n", }, { .path = "/sys/devices/soc0/image_variant", .size = 16, - .content = - "OnePlus5T-user\n" - "\n", + .content = "OnePlus5T-user\n" + "\n", }, { .path = "/sys/devices/soc0/image_version", .size = 23, - .content = - "10:OPR1.170623.032:88\n" - "\n", + .content = "10:OPR1.170623.032:88\n" + "\n", }, { .path = "/sys/devices/soc0/images", .size = 642, - .content = - "0:\n" - "\tCRM:\t\t00:BOOT.XF.1.2.2.c1-00021-M8998LZB-1\n" - "\tVariant:\tMsm8998LA\n" - "\tVersion:\t:ubuntu-143\n" - "1:\n" - "\tCRM:\t\t01:TZ.BF.4.0.6-00144\n" - "\tVariant:\t \n" - "\tVersion:\t:CRM\n" - "3:\n" - "\tCRM:\t\t03:RPM.BF.1.7-00128\n" - "\tVariant:\tAAAAANAZR\n" - "\tVersion:\t:ubuntu-143\n" - "10:\n" - "\tCRM:\t\t10:OPR1.170623.032:88\n" - "\n" - "\tVariant:\tOnePlus5T-user\n" - "\n" - "\tVersion:\tREL\n" - "\n" - "11:\n" - "\tCRM:\t\t11:MPSS.AT.2.0.c4.7-00070-8998_GEN_PACK-2.130961.1.131284.2\n" - "\tVariant:\t8998.gen.prodQ\n" - "\tVersion:\t:ubuntu-143\n" - "12:\n" - "\tCRM:\t\t12:ADSP.HT.3.0-00366-CB8998-1\n" - "\tVariant:\tAAAAAAAAQ\n" - "\tVersion:\t:ubuntu-143\n" - "14:\n" - "\tCRM:\t\t14:VIDEO.VE.4.4-00031\n" - "\tVariant:\tPROD\n" - "\tVersion:\t\n" - "15:\n" - "\tCRM:\t\t15:SLPI.HB.2.0.c3-00012-M8998AZL-1\n" - "\tVariant:\tAAAAAAAAQ\n" - "\tVersion:\t:ubuntu-143\n", + .content = "0:\n" + "\tCRM:\t\t00:BOOT.XF.1.2.2.c1-00021-M8998LZB-1\n" + "\tVariant:\tMsm8998LA\n" + "\tVersion:\t:ubuntu-143\n" + "1:\n" + "\tCRM:\t\t01:TZ.BF.4.0.6-00144\n" + "\tVariant:\t \n" + "\tVersion:\t:CRM\n" + "3:\n" + "\tCRM:\t\t03:RPM.BF.1.7-00128\n" + "\tVariant:\tAAAAANAZR\n" + "\tVersion:\t:ubuntu-143\n" + "10:\n" + "\tCRM:\t\t10:OPR1.170623.032:88\n" + "\n" + "\tVariant:\tOnePlus5T-user\n" + "\n" + "\tVersion:\tREL\n" + "\n" + "11:\n" + "\tCRM:\t\t11:MPSS.AT.2.0.c4.7-00070-8998_GEN_PACK-2.130961.1.131284.2\n" + "\tVariant:\t8998.gen.prodQ\n" + "\tVersion:\t:ubuntu-143\n" + "12:\n" + "\tCRM:\t\t12:ADSP.HT.3.0-00366-CB8998-1\n" + "\tVariant:\tAAAAAAAAQ\n" + "\tVersion:\t:ubuntu-143\n" + "14:\n" + "\tCRM:\t\t14:VIDEO.VE.4.4-00031\n" + "\tVariant:\tPROD\n" + "\tVersion:\t\n" + "15:\n" + "\tCRM:\t\t15:SLPI.HB.2.0.c3-00012-M8998AZL-1\n" + "\tVariant:\tAAAAAAAAQ\n" + "\tVersion:\t:ubuntu-143\n", }, { .path = "/sys/devices/soc0/machine", @@ -387,111 +382,110 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/core_ctl/global_state", .size = 1336, - .content = - "CPU0\n" - "\tCPU: 0\n" - "\tOnline: 1\n" - "\tIsolated: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 8\n" - "\tIs busy: 1\n" - "\tNot preferred: 0\n" - "\tNr running: 1\n" - "\tActive CPUs: 4\n" - "\tNeed CPUs: 4\n" - "\tNr isolated CPUs: 0\n" - "\tBoost: 0\n" - "CPU1\n" - "\tCPU: 1\n" - "\tOnline: 1\n" - "\tIsolated: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 5\n" - "\tIs busy: 1\n" - "\tNot preferred: 0\n" - "\tNr running: 1\n" - "\tActive CPUs: 4\n" - "\tNeed CPUs: 4\n" - "\tNr isolated CPUs: 0\n" - "\tBoost: 0\n" - "CPU2\n" - "\tCPU: 2\n" - "\tOnline: 1\n" - "\tIsolated: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 3\n" - "\tIs busy: 1\n" - "\tNot preferred: 0\n" - "\tNr running: 1\n" - "\tActive CPUs: 4\n" - "\tNeed CPUs: 4\n" - "\tNr isolated CPUs: 0\n" - "\tBoost: 0\n" - "CPU3\n" - "\tCPU: 3\n" - "\tOnline: 1\n" - "\tIsolated: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 1\n" - "\tIs busy: 1\n" - "\tNot preferred: 0\n" - "\tNr running: 1\n" - "\tActive CPUs: 4\n" - "\tNeed CPUs: 4\n" - "\tNr isolated CPUs: 0\n" - "\tBoost: 0\n" - "CPU4\n" - "\tCPU: 4\n" - "\tOnline: 1\n" - "\tIsolated: 0\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "\tNot preferred: 0\n" - "\tNr running: 0\n" - "\tActive CPUs: 2\n" - "\tNeed CPUs: 2\n" - "\tNr isolated CPUs: 2\n" - "\tBoost: 0\n" - "CPU5\n" - "\tCPU: 5\n" - "\tOnline: 1\n" - "\tIsolated: 1\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "\tNot preferred: 0\n" - "\tNr running: 0\n" - "\tActive CPUs: 2\n" - "\tNeed CPUs: 2\n" - "\tNr isolated CPUs: 2\n" - "\tBoost: 0\n" - "CPU6\n" - "\tCPU: 6\n" - "\tOnline: 1\n" - "\tIsolated: 1\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "\tNot preferred: 0\n" - "\tNr running: 0\n" - "\tActive CPUs: 2\n" - "\tNeed CPUs: 2\n" - "\tNr isolated CPUs: 2\n" - "\tBoost: 0\n" - "CPU7\n" - "\tCPU: 7\n" - "\tOnline: 1\n" - "\tIsolated: 0\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "\tNot preferred: 0\n" - "\tNr running: 0\n" - "\tActive CPUs: 2\n" - "\tNeed CPUs: 2\n" - "\tNr isolated CPUs: 2\n" - "\tBoost: 0\n", + .content = "CPU0\n" + "\tCPU: 0\n" + "\tOnline: 1\n" + "\tIsolated: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 8\n" + "\tIs busy: 1\n" + "\tNot preferred: 0\n" + "\tNr running: 1\n" + "\tActive CPUs: 4\n" + "\tNeed CPUs: 4\n" + "\tNr isolated CPUs: 0\n" + "\tBoost: 0\n" + "CPU1\n" + "\tCPU: 1\n" + "\tOnline: 1\n" + "\tIsolated: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 5\n" + "\tIs busy: 1\n" + "\tNot preferred: 0\n" + "\tNr running: 1\n" + "\tActive CPUs: 4\n" + "\tNeed CPUs: 4\n" + "\tNr isolated CPUs: 0\n" + "\tBoost: 0\n" + "CPU2\n" + "\tCPU: 2\n" + "\tOnline: 1\n" + "\tIsolated: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 3\n" + "\tIs busy: 1\n" + "\tNot preferred: 0\n" + "\tNr running: 1\n" + "\tActive CPUs: 4\n" + "\tNeed CPUs: 4\n" + "\tNr isolated CPUs: 0\n" + "\tBoost: 0\n" + "CPU3\n" + "\tCPU: 3\n" + "\tOnline: 1\n" + "\tIsolated: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 1\n" + "\tIs busy: 1\n" + "\tNot preferred: 0\n" + "\tNr running: 1\n" + "\tActive CPUs: 4\n" + "\tNeed CPUs: 4\n" + "\tNr isolated CPUs: 0\n" + "\tBoost: 0\n" + "CPU4\n" + "\tCPU: 4\n" + "\tOnline: 1\n" + "\tIsolated: 0\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "\tNot preferred: 0\n" + "\tNr running: 0\n" + "\tActive CPUs: 2\n" + "\tNeed CPUs: 2\n" + "\tNr isolated CPUs: 2\n" + "\tBoost: 0\n" + "CPU5\n" + "\tCPU: 5\n" + "\tOnline: 1\n" + "\tIsolated: 1\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "\tNot preferred: 0\n" + "\tNr running: 0\n" + "\tActive CPUs: 2\n" + "\tNeed CPUs: 2\n" + "\tNr isolated CPUs: 2\n" + "\tBoost: 0\n" + "CPU6\n" + "\tCPU: 6\n" + "\tOnline: 1\n" + "\tIsolated: 1\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "\tNot preferred: 0\n" + "\tNr running: 0\n" + "\tActive CPUs: 2\n" + "\tNeed CPUs: 2\n" + "\tNr isolated CPUs: 2\n" + "\tBoost: 0\n" + "CPU7\n" + "\tCPU: 7\n" + "\tOnline: 1\n" + "\tIsolated: 0\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "\tNot preferred: 0\n" + "\tNr running: 0\n" + "\tActive CPUs: 2\n" + "\tNeed CPUs: 2\n" + "\tNr isolated CPUs: 2\n" + "\tBoost: 0\n", }, { .path = "/sys/devices/system/cpu/cpu0/core_ctl/is_big_cluster", @@ -516,11 +510,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/core_ctl/not_preferred", .size = 36, - .content = - "CPU#0: 0\n" - "CPU#1: 0\n" - "CPU#2: 0\n" - "CPU#3: 0\n", + .content = "CPU#0: 0\n" + "CPU#1: 0\n" + "CPU#2: 0\n" + "CPU#3: 0\n", }, { .path = "/sys/devices/system/cpu/cpu0/core_ctl/offline_delay_ms", @@ -565,7 +558,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies", .size = 167, - .content = "300000 364800 441600 518400 595200 672000 748800 825600 883200 960000 1036800 1094400 1171200 1248000 1324800 1401600 1478400 1555200 1670400 1747200 1824000 1900800 \n", + .content = + "300000 364800 441600 518400 595200 672000 748800 825600 883200 960000 1036800 1094400 1171200 1248000 1324800 1401600 1478400 1555200 1670400 1747200 1824000 1900800 \n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors", @@ -595,29 +589,28 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 231, - .content = - "300000 0\n" - "364800 0\n" - "441600 0\n" - "518400 485\n" - "595200 16\n" - "672000 8\n" - "748800 10\n" - "825600 12\n" - "883200 8\n" - "960000 13\n" - "1036800 14\n" - "1094400 12\n" - "1171200 6\n" - "1248000 225\n" - "1324800 29\n" - "1401600 30\n" - "1478400 28\n" - "1555200 86\n" - "1670400 28\n" - "1747200 26\n" - "1824000 102\n" - "1900800 2838\n", + .content = "300000 0\n" + "364800 0\n" + "441600 0\n" + "518400 485\n" + "595200 16\n" + "672000 8\n" + "748800 10\n" + "825600 12\n" + "883200 8\n" + "960000 13\n" + "1036800 14\n" + "1094400 12\n" + "1171200 6\n" + "1248000 225\n" + "1324800 29\n" + "1401600 30\n" + "1478400 28\n" + "1555200 86\n" + "1670400 28\n" + "1747200 26\n" + "1824000 102\n" + "1900800 2838\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -837,7 +830,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_frequencies", .size = 167, - .content = "300000 364800 441600 518400 595200 672000 748800 825600 883200 960000 1036800 1094400 1171200 1248000 1324800 1401600 1478400 1555200 1670400 1747200 1824000 1900800 \n", + .content = + "300000 364800 441600 518400 595200 672000 748800 825600 883200 960000 1036800 1094400 1171200 1248000 1324800 1401600 1478400 1555200 1670400 1747200 1824000 1900800 \n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_governors", @@ -867,29 +861,28 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 233, - .content = - "300000 0\n" - "364800 0\n" - "441600 0\n" - "518400 589\n" - "595200 16\n" - "672000 12\n" - "748800 12\n" - "825600 14\n" - "883200 10\n" - "960000 13\n" - "1036800 14\n" - "1094400 12\n" - "1171200 6\n" - "1248000 263\n" - "1324800 35\n" - "1401600 34\n" - "1478400 30\n" - "1555200 90\n" - "1670400 36\n" - "1747200 28\n" - "1824000 125\n" - "1900800 2917\n", + .content = "300000 0\n" + "364800 0\n" + "441600 0\n" + "518400 589\n" + "595200 16\n" + "672000 12\n" + "748800 12\n" + "825600 14\n" + "883200 10\n" + "960000 13\n" + "1036800 14\n" + "1094400 12\n" + "1171200 6\n" + "1248000 263\n" + "1324800 35\n" + "1401600 34\n" + "1478400 30\n" + "1555200 90\n" + "1670400 36\n" + "1747200 28\n" + "1824000 125\n" + "1900800 2917\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -1109,7 +1102,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_frequencies", .size = 167, - .content = "300000 364800 441600 518400 595200 672000 748800 825600 883200 960000 1036800 1094400 1171200 1248000 1324800 1401600 1478400 1555200 1670400 1747200 1824000 1900800 \n", + .content = + "300000 364800 441600 518400 595200 672000 748800 825600 883200 960000 1036800 1094400 1171200 1248000 1324800 1401600 1478400 1555200 1670400 1747200 1824000 1900800 \n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_governors", @@ -1139,29 +1133,28 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 233, - .content = - "300000 0\n" - "364800 0\n" - "441600 0\n" - "518400 800\n" - "595200 16\n" - "672000 12\n" - "748800 14\n" - "825600 14\n" - "883200 10\n" - "960000 13\n" - "1036800 14\n" - "1094400 12\n" - "1171200 8\n" - "1248000 329\n" - "1324800 39\n" - "1401600 34\n" - "1478400 32\n" - "1555200 96\n" - "1670400 36\n" - "1747200 30\n" - "1824000 127\n" - "1900800 2941\n", + .content = "300000 0\n" + "364800 0\n" + "441600 0\n" + "518400 800\n" + "595200 16\n" + "672000 12\n" + "748800 14\n" + "825600 14\n" + "883200 10\n" + "960000 13\n" + "1036800 14\n" + "1094400 12\n" + "1171200 8\n" + "1248000 329\n" + "1324800 39\n" + "1401600 34\n" + "1478400 32\n" + "1555200 96\n" + "1670400 36\n" + "1747200 30\n" + "1824000 127\n" + "1900800 2941\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -1381,7 +1374,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_frequencies", .size = 167, - .content = "300000 364800 441600 518400 595200 672000 748800 825600 883200 960000 1036800 1094400 1171200 1248000 1324800 1401600 1478400 1555200 1670400 1747200 1824000 1900800 \n", + .content = + "300000 364800 441600 518400 595200 672000 748800 825600 883200 960000 1036800 1094400 1171200 1248000 1324800 1401600 1478400 1555200 1670400 1747200 1824000 1900800 \n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_governors", @@ -1411,29 +1405,28 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 234, - .content = - "300000 0\n" - "364800 0\n" - "441600 0\n" - "518400 1039\n" - "595200 20\n" - "672000 16\n" - "748800 18\n" - "825600 14\n" - "883200 14\n" - "960000 15\n" - "1036800 16\n" - "1094400 16\n" - "1171200 8\n" - "1248000 377\n" - "1324800 43\n" - "1401600 36\n" - "1478400 36\n" - "1555200 96\n" - "1670400 36\n" - "1747200 30\n" - "1824000 127\n" - "1900800 2943\n", + .content = "300000 0\n" + "364800 0\n" + "441600 0\n" + "518400 1039\n" + "595200 20\n" + "672000 16\n" + "748800 18\n" + "825600 14\n" + "883200 14\n" + "960000 15\n" + "1036800 16\n" + "1094400 16\n" + "1171200 8\n" + "1248000 377\n" + "1324800 43\n" + "1401600 36\n" + "1478400 36\n" + "1555200 96\n" + "1670400 36\n" + "1747200 30\n" + "1824000 127\n" + "1900800 2943\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -1643,111 +1636,110 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/core_ctl/global_state", .size = 1336, - .content = - "CPU0\n" - "\tCPU: 0\n" - "\tOnline: 1\n" - "\tIsolated: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 0\n" - "\tIs busy: 1\n" - "\tNot preferred: 0\n" - "\tNr running: 1\n" - "\tActive CPUs: 4\n" - "\tNeed CPUs: 4\n" - "\tNr isolated CPUs: 0\n" - "\tBoost: 0\n" - "CPU1\n" - "\tCPU: 1\n" - "\tOnline: 1\n" - "\tIsolated: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 4\n" - "\tIs busy: 1\n" - "\tNot preferred: 0\n" - "\tNr running: 1\n" - "\tActive CPUs: 4\n" - "\tNeed CPUs: 4\n" - "\tNr isolated CPUs: 0\n" - "\tBoost: 0\n" - "CPU2\n" - "\tCPU: 2\n" - "\tOnline: 1\n" - "\tIsolated: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 0\n" - "\tIs busy: 1\n" - "\tNot preferred: 0\n" - "\tNr running: 1\n" - "\tActive CPUs: 4\n" - "\tNeed CPUs: 4\n" - "\tNr isolated CPUs: 0\n" - "\tBoost: 0\n" - "CPU3\n" - "\tCPU: 3\n" - "\tOnline: 1\n" - "\tIsolated: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 1\n" - "\tIs busy: 1\n" - "\tNot preferred: 0\n" - "\tNr running: 1\n" - "\tActive CPUs: 4\n" - "\tNeed CPUs: 4\n" - "\tNr isolated CPUs: 0\n" - "\tBoost: 0\n" - "CPU4\n" - "\tCPU: 4\n" - "\tOnline: 1\n" - "\tIsolated: 1\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "\tNot preferred: 0\n" - "\tNr running: 0\n" - "\tActive CPUs: 2\n" - "\tNeed CPUs: 2\n" - "\tNr isolated CPUs: 2\n" - "\tBoost: 0\n" - "CPU5\n" - "\tCPU: 5\n" - "\tOnline: 1\n" - "\tIsolated: 0\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "\tNot preferred: 0\n" - "\tNr running: 0\n" - "\tActive CPUs: 2\n" - "\tNeed CPUs: 2\n" - "\tNr isolated CPUs: 2\n" - "\tBoost: 0\n" - "CPU6\n" - "\tCPU: 6\n" - "\tOnline: 1\n" - "\tIsolated: 0\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "\tNot preferred: 0\n" - "\tNr running: 0\n" - "\tActive CPUs: 2\n" - "\tNeed CPUs: 2\n" - "\tNr isolated CPUs: 2\n" - "\tBoost: 0\n" - "CPU7\n" - "\tCPU: 7\n" - "\tOnline: 1\n" - "\tIsolated: 1\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "\tNot preferred: 0\n" - "\tNr running: 0\n" - "\tActive CPUs: 2\n" - "\tNeed CPUs: 2\n" - "\tNr isolated CPUs: 2\n" - "\tBoost: 0\n", + .content = "CPU0\n" + "\tCPU: 0\n" + "\tOnline: 1\n" + "\tIsolated: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 0\n" + "\tIs busy: 1\n" + "\tNot preferred: 0\n" + "\tNr running: 1\n" + "\tActive CPUs: 4\n" + "\tNeed CPUs: 4\n" + "\tNr isolated CPUs: 0\n" + "\tBoost: 0\n" + "CPU1\n" + "\tCPU: 1\n" + "\tOnline: 1\n" + "\tIsolated: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 4\n" + "\tIs busy: 1\n" + "\tNot preferred: 0\n" + "\tNr running: 1\n" + "\tActive CPUs: 4\n" + "\tNeed CPUs: 4\n" + "\tNr isolated CPUs: 0\n" + "\tBoost: 0\n" + "CPU2\n" + "\tCPU: 2\n" + "\tOnline: 1\n" + "\tIsolated: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 0\n" + "\tIs busy: 1\n" + "\tNot preferred: 0\n" + "\tNr running: 1\n" + "\tActive CPUs: 4\n" + "\tNeed CPUs: 4\n" + "\tNr isolated CPUs: 0\n" + "\tBoost: 0\n" + "CPU3\n" + "\tCPU: 3\n" + "\tOnline: 1\n" + "\tIsolated: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 1\n" + "\tIs busy: 1\n" + "\tNot preferred: 0\n" + "\tNr running: 1\n" + "\tActive CPUs: 4\n" + "\tNeed CPUs: 4\n" + "\tNr isolated CPUs: 0\n" + "\tBoost: 0\n" + "CPU4\n" + "\tCPU: 4\n" + "\tOnline: 1\n" + "\tIsolated: 1\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "\tNot preferred: 0\n" + "\tNr running: 0\n" + "\tActive CPUs: 2\n" + "\tNeed CPUs: 2\n" + "\tNr isolated CPUs: 2\n" + "\tBoost: 0\n" + "CPU5\n" + "\tCPU: 5\n" + "\tOnline: 1\n" + "\tIsolated: 0\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "\tNot preferred: 0\n" + "\tNr running: 0\n" + "\tActive CPUs: 2\n" + "\tNeed CPUs: 2\n" + "\tNr isolated CPUs: 2\n" + "\tBoost: 0\n" + "CPU6\n" + "\tCPU: 6\n" + "\tOnline: 1\n" + "\tIsolated: 0\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "\tNot preferred: 0\n" + "\tNr running: 0\n" + "\tActive CPUs: 2\n" + "\tNeed CPUs: 2\n" + "\tNr isolated CPUs: 2\n" + "\tBoost: 0\n" + "CPU7\n" + "\tCPU: 7\n" + "\tOnline: 1\n" + "\tIsolated: 1\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "\tNot preferred: 0\n" + "\tNr running: 0\n" + "\tActive CPUs: 2\n" + "\tNeed CPUs: 2\n" + "\tNr isolated CPUs: 2\n" + "\tBoost: 0\n", }, { .path = "/sys/devices/system/cpu/cpu4/core_ctl/is_big_cluster", @@ -1772,11 +1764,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/core_ctl/not_preferred", .size = 36, - .content = - "CPU#4: 0\n" - "CPU#5: 0\n" - "CPU#6: 0\n" - "CPU#7: 0\n", + .content = "CPU#4: 0\n" + "CPU#5: 0\n" + "CPU#6: 0\n" + "CPU#7: 0\n", }, { .path = "/sys/devices/system/cpu/cpu4/core_ctl/offline_delay_ms", @@ -1821,7 +1812,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_available_frequencies", .size = 239, - .content = "300000 345600 422400 499200 576000 652800 729600 806400 902400 979200 1056000 1132800 1190400 1267200 1344000 1420800 1497600 1574400 1651200 1728000 1804800 1881600 1958400 2035200 2112000 2208000 2265600 2323200 2342400 2361600 2457600 \n", + .content = + "300000 345600 422400 499200 576000 652800 729600 806400 902400 979200 1056000 1132800 1190400 1267200 1344000 1420800 1497600 1574400 1651200 1728000 1804800 1881600 1958400 2035200 2112000 2208000 2265600 2323200 2342400 2361600 2457600 \n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_available_governors", @@ -1856,38 +1848,37 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/time_in_state", .size = 313, - .content = - "300000 0\n" - "345600 0\n" - "422400 0\n" - "499200 0\n" - "576000 0\n" - "652800 0\n" - "729600 0\n" - "806400 2401\n" - "902400 7\n" - "979200 8\n" - "1056000 4\n" - "1132800 4\n" - "1190400 6\n" - "1267200 9\n" - "1344000 9\n" - "1420800 9\n" - "1497600 10\n" - "1574400 140\n" - "1651200 8\n" - "1728000 6\n" - "1804800 7\n" - "1881600 5\n" - "1958400 27\n" - "2035200 6\n" - "2112000 11\n" - "2208000 9\n" - "2265600 8\n" - "2323200 0\n" - "2342400 2\n" - "2361600 1611\n" - "2457600 913\n", + .content = "300000 0\n" + "345600 0\n" + "422400 0\n" + "499200 0\n" + "576000 0\n" + "652800 0\n" + "729600 0\n" + "806400 2401\n" + "902400 7\n" + "979200 8\n" + "1056000 4\n" + "1132800 4\n" + "1190400 6\n" + "1267200 9\n" + "1344000 9\n" + "1420800 9\n" + "1497600 10\n" + "1574400 140\n" + "1651200 8\n" + "1728000 6\n" + "1804800 7\n" + "1881600 5\n" + "1958400 27\n" + "2035200 6\n" + "2112000 11\n" + "2208000 9\n" + "2265600 8\n" + "2323200 0\n" + "2342400 2\n" + "2361600 1611\n" + "2457600 913\n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/total_trans", @@ -2107,7 +2098,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_available_frequencies", .size = 239, - .content = "300000 345600 422400 499200 576000 652800 729600 806400 902400 979200 1056000 1132800 1190400 1267200 1344000 1420800 1497600 1574400 1651200 1728000 1804800 1881600 1958400 2035200 2112000 2208000 2265600 2323200 2342400 2361600 2457600 \n", + .content = + "300000 345600 422400 499200 576000 652800 729600 806400 902400 979200 1056000 1132800 1190400 1267200 1344000 1420800 1497600 1574400 1651200 1728000 1804800 1881600 1958400 2035200 2112000 2208000 2265600 2323200 2342400 2361600 2457600 \n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_available_governors", @@ -2142,38 +2134,37 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/time_in_state", .size = 314, - .content = - "300000 0\n" - "345600 0\n" - "422400 0\n" - "499200 0\n" - "576000 0\n" - "652800 0\n" - "729600 0\n" - "806400 2715\n" - "902400 7\n" - "979200 8\n" - "1056000 4\n" - "1132800 4\n" - "1190400 6\n" - "1267200 9\n" - "1344000 9\n" - "1420800 9\n" - "1497600 10\n" - "1574400 144\n" - "1651200 8\n" - "1728000 6\n" - "1804800 7\n" - "1881600 5\n" - "1958400 27\n" - "2035200 6\n" - "2112000 11\n" - "2208000 9\n" - "2265600 10\n" - "2323200 0\n" - "2342400 2\n" - "2361600 1615\n" - "2457600 913\n", + .content = "300000 0\n" + "345600 0\n" + "422400 0\n" + "499200 0\n" + "576000 0\n" + "652800 0\n" + "729600 0\n" + "806400 2715\n" + "902400 7\n" + "979200 8\n" + "1056000 4\n" + "1132800 4\n" + "1190400 6\n" + "1267200 9\n" + "1344000 9\n" + "1420800 9\n" + "1497600 10\n" + "1574400 144\n" + "1651200 8\n" + "1728000 6\n" + "1804800 7\n" + "1881600 5\n" + "1958400 27\n" + "2035200 6\n" + "2112000 11\n" + "2208000 9\n" + "2265600 10\n" + "2323200 0\n" + "2342400 2\n" + "2361600 1615\n" + "2457600 913\n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/total_trans", @@ -2393,7 +2384,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_available_frequencies", .size = 239, - .content = "300000 345600 422400 499200 576000 652800 729600 806400 902400 979200 1056000 1132800 1190400 1267200 1344000 1420800 1497600 1574400 1651200 1728000 1804800 1881600 1958400 2035200 2112000 2208000 2265600 2323200 2342400 2361600 2457600 \n", + .content = + "300000 345600 422400 499200 576000 652800 729600 806400 902400 979200 1056000 1132800 1190400 1267200 1344000 1420800 1497600 1574400 1651200 1728000 1804800 1881600 1958400 2035200 2112000 2208000 2265600 2323200 2342400 2361600 2457600 \n", }, { .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_available_governors", @@ -2428,38 +2420,37 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/time_in_state", .size = 314, - .content = - "300000 0\n" - "345600 0\n" - "422400 0\n" - "499200 0\n" - "576000 0\n" - "652800 0\n" - "729600 0\n" - "806400 3016\n" - "902400 7\n" - "979200 8\n" - "1056000 4\n" - "1132800 4\n" - "1190400 6\n" - "1267200 9\n" - "1344000 9\n" - "1420800 9\n" - "1497600 12\n" - "1574400 156\n" - "1651200 8\n" - "1728000 6\n" - "1804800 7\n" - "1881600 7\n" - "1958400 29\n" - "2035200 6\n" - "2112000 11\n" - "2208000 9\n" - "2265600 10\n" - "2323200 0\n" - "2342400 2\n" - "2361600 1629\n" - "2457600 913\n", + .content = "300000 0\n" + "345600 0\n" + "422400 0\n" + "499200 0\n" + "576000 0\n" + "652800 0\n" + "729600 0\n" + "806400 3016\n" + "902400 7\n" + "979200 8\n" + "1056000 4\n" + "1132800 4\n" + "1190400 6\n" + "1267200 9\n" + "1344000 9\n" + "1420800 9\n" + "1497600 12\n" + "1574400 156\n" + "1651200 8\n" + "1728000 6\n" + "1804800 7\n" + "1881600 7\n" + "1958400 29\n" + "2035200 6\n" + "2112000 11\n" + "2208000 9\n" + "2265600 10\n" + "2323200 0\n" + "2342400 2\n" + "2361600 1629\n" + "2457600 913\n", }, { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/total_trans", @@ -2679,7 +2670,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_available_frequencies", .size = 239, - .content = "300000 345600 422400 499200 576000 652800 729600 806400 902400 979200 1056000 1132800 1190400 1267200 1344000 1420800 1497600 1574400 1651200 1728000 1804800 1881600 1958400 2035200 2112000 2208000 2265600 2323200 2342400 2361600 2457600 \n", + .content = + "300000 345600 422400 499200 576000 652800 729600 806400 902400 979200 1056000 1132800 1190400 1267200 1344000 1420800 1497600 1574400 1651200 1728000 1804800 1881600 1958400 2035200 2112000 2208000 2265600 2323200 2342400 2361600 2457600 \n", }, { .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_available_governors", @@ -2714,38 +2706,37 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/time_in_state", .size = 314, - .content = - "300000 0\n" - "345600 0\n" - "422400 0\n" - "499200 0\n" - "576000 0\n" - "652800 0\n" - "729600 0\n" - "806400 3342\n" - "902400 7\n" - "979200 8\n" - "1056000 4\n" - "1132800 4\n" - "1190400 6\n" - "1267200 9\n" - "1344000 9\n" - "1420800 9\n" - "1497600 12\n" - "1574400 156\n" - "1651200 8\n" - "1728000 6\n" - "1804800 7\n" - "1881600 7\n" - "1958400 29\n" - "2035200 6\n" - "2112000 11\n" - "2208000 9\n" - "2265600 10\n" - "2323200 0\n" - "2342400 2\n" - "2361600 1629\n" - "2457600 913\n", + .content = "300000 0\n" + "345600 0\n" + "422400 0\n" + "499200 0\n" + "576000 0\n" + "652800 0\n" + "729600 0\n" + "806400 3342\n" + "902400 7\n" + "979200 8\n" + "1056000 4\n" + "1132800 4\n" + "1190400 6\n" + "1267200 9\n" + "1344000 9\n" + "1420800 9\n" + "1497600 12\n" + "1574400 156\n" + "1651200 8\n" + "1728000 6\n" + "1804800 7\n" + "1881600 7\n" + "1958400 29\n" + "2035200 6\n" + "2112000 11\n" + "2208000 9\n" + "2265600 10\n" + "2323200 0\n" + "2342400 2\n" + "2361600 1629\n" + "2457600 913\n", }, { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/total_trans", @@ -2932,7 +2923,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 10, .content = "WriteBack\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -5424,6 +5415,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wifi.interface", .value = "wlan0", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/oppo-a37.cc b/test/mock/oppo-a37.cc index 5065ab69..a48ad54f 100644 --- a/test/mock/oppo-a37.cc +++ b/test/mock/oppo-a37.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(4, cpuinfo_get_processors_count()); @@ -208,8 +207,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Qualcomm MSM8916", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Qualcomm MSM8916", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -251,59 +252,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -403,11 +404,11 @@ TEST(ISA, pmull) { } TEST(ISA, crc32) { - #if CPUINFO_ARCH_ARM - ASSERT_FALSE(cpuinfo_has_arm_crc32()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_TRUE(cpuinfo_has_arm_crc32()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_FALSE(cpuinfo_has_arm_crc32()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_TRUE(cpuinfo_has_arm_crc32()); +#endif } TEST(L1I, count) { @@ -432,8 +433,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -484,8 +487,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -536,8 +541,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/oppo-a37.h b/test/mock/oppo-a37.h index 5dfe8106..87b4dfd6 100644 --- a/test/mock/oppo-a37.h +++ b/test/mock/oppo-a37.h @@ -3,20 +3,19 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 279, - .content = - "Processor\t: AArch64 Processor rev 0 (aarch64)\n" - "processor\t: 0\n" - "processor\t: 1\n" - "processor\t: 2\n" - "processor\t: 3\n" - "Features\t: fp asimd evtstrm crc32 \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 0\n" - "\n" - "Hardware\t: Qualcomm Technologies, Inc MSM8916\n", + .content = "Processor\t: AArch64 Processor rev 0 (aarch64)\n" + "processor\t: 0\n" + "processor\t: 1\n" + "processor\t: 2\n" + "processor\t: 3\n" + "Features\t: fp asimd evtstrm crc32 \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 0\n" + "\n" + "Hardware\t: Qualcomm Technologies, Inc MSM8916\n", }, #elif CPUINFO_ARCH_ARM { @@ -427,7 +426,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/class/kgsl/kgsl-3d0/devfreq/available_governors", .size = 89, - .content = "bw_vbif gpubw_mon msm-adreno-tz cpufreq userspace powersave performance simple_ondemand\r\n", + .content = + "bw_vbif gpubw_mon msm-adreno-tz cpufreq userspace powersave performance simple_ondemand\r\n", }, { .path = "/sys/class/kgsl/kgsl-3d0/devfreq/cur_freq", @@ -462,13 +462,12 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/class/kgsl/kgsl-3d0/devfreq/trans_stat", .size = 232, - .content = - " From : To\r\n" - " :400000000310000000200000000 time(ms)\r\n" - "*400000000: 0 49 0 43170\r\n" - " 310000000: 49 0 11 584160\r\n" - " 200000000: 1 10 0 6310\r\n" - "Total transition : 120\r\n", + .content = " From : To\r\n" + " :400000000310000000200000000 time(ms)\r\n" + "*400000000: 0 49 0 43170\r\n" + " 310000000: 49 0 11 584160\r\n" + " 200000000: 1 10 0 6310\r\n" + "Total transition : 120\r\n", }, { .path = "/sys/class/kgsl/kgsl-3d0/ft_fast_hang_detect", @@ -583,23 +582,20 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/soc0/image_crm_version", .size = 5, - .content = - "REL\n" - "\n", + .content = "REL\n" + "\n", }, { .path = "/sys/devices/soc0/image_variant", .size = 12, - .content = - "A37fw-user\n" - "\n", + .content = "A37fw-user\n" + "\n", }, { .path = "/sys/devices/soc0/image_version", .size = 22, - .content = - "10:LMY47V:1456818039\n" - "\n", + .content = "10:LMY47V:1456818039\n" + "\n", }, { .path = "/sys/devices/soc0/machine", @@ -759,15 +755,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 89, - .content = - "200000 0\n" - "400000 0\n" - "533333 0\n" - "800000 53148\n" - "998400 2868\n" - "1094400 127\n" - "1152000 240\n" - "1209600 7183\n", + .content = "200000 0\n" + "400000 0\n" + "533333 0\n" + "800000 53148\n" + "998400 2868\n" + "1094400 127\n" + "1152000 240\n" + "1209600 7183\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -862,15 +857,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 89, - .content = - "200000 0\n" - "400000 0\n" - "533333 0\n" - "800000 53373\n" - "998400 2868\n" - "1094400 127\n" - "1152000 240\n" - "1209600 7183\n", + .content = "200000 0\n" + "400000 0\n" + "533333 0\n" + "800000 53373\n" + "998400 2868\n" + "1094400 127\n" + "1152000 240\n" + "1209600 7183\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -965,15 +959,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 89, - .content = - "200000 0\n" - "400000 0\n" - "533333 0\n" - "800000 53580\n" - "998400 2876\n" - "1094400 127\n" - "1152000 240\n" - "1209600 7183\n", + .content = "200000 0\n" + "400000 0\n" + "533333 0\n" + "800000 53580\n" + "998400 2876\n" + "1094400 127\n" + "1152000 240\n" + "1209600 7183\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -1068,15 +1061,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 89, - .content = - "200000 0\n" - "400000 0\n" - "533333 0\n" - "800000 53818\n" - "998400 2876\n" - "1094400 127\n" - "1152000 240\n" - "1209600 7183\n", + .content = "200000 0\n" + "400000 0\n" + "533333 0\n" + "800000 53818\n" + "998400 2876\n" + "1094400 127\n" + "1152000 240\n" + "1209600 7183\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -1113,7 +1105,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "3\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -2865,6 +2857,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.driver.status", .value = "ok", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/oppo-r15.cc b/test/mock/oppo-r15.cc index 16db06f4..cae43223 100644 --- a/test/mock/oppo-r15.cc +++ b/test/mock/oppo-r15.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(8, cpuinfo_get_processors_count()); @@ -314,8 +313,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("MediaTek MT6771V/C", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "MediaTek MT6771V/C", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -357,59 +358,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -560,8 +561,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -638,8 +641,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -697,8 +702,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/oppo-r15.h b/test/mock/oppo-r15.h index a1246bea..dbd38b70 100644 --- a/test/mock/oppo-r15.h +++ b/test/mock/oppo-r15.h @@ -1,1428 +1,1437 @@ -struct cpuinfo_mock_file filesystem[] = { +struct + cpuinfo_mock_file + filesystem + [] = + { #if CPUINFO_ARCH_ARM64 - { - .path = "/proc/cpuinfo", - .size = 1515, - .content = - "Processor\t: AArch64 Processor rev 4 (aarch64)\n" - "processor\t: 0\n" - "BogoMIPS\t: 26.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 1\n" - "BogoMIPS\t: 26.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 2\n" - "BogoMIPS\t: 26.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 3\n" - "BogoMIPS\t: 26.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 4\n" - "BogoMIPS\t: 26.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd09\n" - "CPU revision\t: 2\n" - "\n" - "processor\t: 5\n" - "BogoMIPS\t: 26.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd09\n" - "CPU revision\t: 2\n" - "\n" - "processor\t: 6\n" - "BogoMIPS\t: 26.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd09\n" - "CPU revision\t: 2\n" - "\n" - "processor\t: 7\n" - "BogoMIPS\t: 26.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd09\n" - "CPU revision\t: 2\n" - "\n" - "Hardware\t: MT6771V/C\n", - }, + { + .path = "/proc/cpuinfo", + .size = 1515, + .content = "Processor\t: AArch64 Processor rev 4 (aarch64)\n" + "processor\t: 0\n" + "BogoMIPS\t: 26.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 1\n" + "BogoMIPS\t: 26.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 2\n" + "BogoMIPS\t: 26.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 3\n" + "BogoMIPS\t: 26.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 4\n" + "BogoMIPS\t: 26.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd09\n" + "CPU revision\t: 2\n" + "\n" + "processor\t: 5\n" + "BogoMIPS\t: 26.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd09\n" + "CPU revision\t: 2\n" + "\n" + "processor\t: 6\n" + "BogoMIPS\t: 26.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd09\n" + "CPU revision\t: 2\n" + "\n" + "processor\t: 7\n" + "BogoMIPS\t: 26.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd09\n" + "CPU revision\t: 2\n" + "\n" + "Hardware\t: MT6771V/C\n", + }, #elif CPUINFO_ARCH_ARM - { - .path = "/proc/cpuinfo", - .size = 2306, - .content = - "Processor\t: AArch64 Processor rev 4 (aarch64)\n" - "processor\t: 0\n" - "model name\t: ARMv8 Processor rev 4 (v8l)\n" - "BogoMIPS\t: 26.00\n" - "Features\t: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt lpae evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 1\n" - "model name\t: ARMv8 Processor rev 4 (v8l)\n" - "BogoMIPS\t: 26.00\n" - "Features\t: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt lpae evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 2\n" - "model name\t: ARMv8 Processor rev 4 (v8l)\n" - "BogoMIPS\t: 26.00\n" - "Features\t: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt lpae evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 3\n" - "model name\t: ARMv8 Processor rev 4 (v8l)\n" - "BogoMIPS\t: 26.00\n" - "Features\t: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt lpae evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 4\n" - "model name\t: ARMv8 Processor rev 2 (v8l)\n" - "BogoMIPS\t: 26.00\n" - "Features\t: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt lpae evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd09\n" - "CPU revision\t: 2\n" - "\n" - "processor\t: 5\n" - "model name\t: ARMv8 Processor rev 2 (v8l)\n" - "BogoMIPS\t: 26.00\n" - "Features\t: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt lpae evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd09\n" - "CPU revision\t: 2\n" - "\n" - "processor\t: 6\n" - "model name\t: ARMv8 Processor rev 2 (v8l)\n" - "BogoMIPS\t: 26.00\n" - "Features\t: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt lpae evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd09\n" - "CPU revision\t: 2\n" - "\n" - "processor\t: 7\n" - "model name\t: ARMv8 Processor rev 2 (v8l)\n" - "BogoMIPS\t: 26.00\n" - "Features\t: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt lpae evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd09\n" - "CPU revision\t: 2\n" - "\n" - "Hardware\t: MT6771V/C", - }, + { + .path = "/proc/cpuinfo", + .size = 2306, + .content = + "Processor\t: AArch64 Processor rev 4 (aarch64)\n" + "processor\t: 0\n" + "model name\t: ARMv8 Processor rev 4 (v8l)\n" + "BogoMIPS\t: 26.00\n" + "Features\t: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt lpae evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 1\n" + "model name\t: ARMv8 Processor rev 4 (v8l)\n" + "BogoMIPS\t: 26.00\n" + "Features\t: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt lpae evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 2\n" + "model name\t: ARMv8 Processor rev 4 (v8l)\n" + "BogoMIPS\t: 26.00\n" + "Features\t: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt lpae evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 3\n" + "model name\t: ARMv8 Processor rev 4 (v8l)\n" + "BogoMIPS\t: 26.00\n" + "Features\t: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt lpae evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 4\n" + "model name\t: ARMv8 Processor rev 2 (v8l)\n" + "BogoMIPS\t: 26.00\n" + "Features\t: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt lpae evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd09\n" + "CPU revision\t: 2\n" + "\n" + "processor\t: 5\n" + "model name\t: ARMv8 Processor rev 2 (v8l)\n" + "BogoMIPS\t: 26.00\n" + "Features\t: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt lpae evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd09\n" + "CPU revision\t: 2\n" + "\n" + "processor\t: 6\n" + "model name\t: ARMv8 Processor rev 2 (v8l)\n" + "BogoMIPS\t: 26.00\n" + "Features\t: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt lpae evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd09\n" + "CPU revision\t: 2\n" + "\n" + "processor\t: 7\n" + "model name\t: ARMv8 Processor rev 2 (v8l)\n" + "BogoMIPS\t: 26.00\n" + "Features\t: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt lpae evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd09\n" + "CPU revision\t: 2\n" + "\n" + "Hardware\t: MT6771V/C", + }, #endif - { - .path = "/sys/devices/system/cpu/isolated", - .size = 1, - .content = "\n", - }, - { - .path = "/sys/devices/system/cpu/kernel_max", - .size = 2, - .content = "7\n", - }, - { - .path = "/sys/devices/system/cpu/modalias", - .size = 66, - .content = "cpu:type:aarch64:feature:,0000,0001,0002,0003,0004,0005,0006,0007\n", - }, - { - .path = "/sys/devices/system/cpu/offline", - .size = 1, - .content = "\n", - }, - { - .path = "/sys/devices/system/cpu/online", - .size = 4, - .content = "0-7\n", - }, - { - .path = "/sys/devices/system/cpu/possible", - .size = 4, - .content = "0-7\n", - }, - { - .path = "/sys/devices/system/cpu/present", - .size = 4, - .content = "0-7\n", - }, - { - .path = "/sys/devices/system/cpu/sched_isolated", - .size = 4, - .content = "4-7\n", - }, - { - .path = "/sys/devices/system/cpu/cpuidle/current_driver", - .size = 26, - .content = "mt67xx_acao_cpuidle_set_0\n", - }, - { - .path = "/sys/devices/system/cpu/cpuidle/current_governor_ro", - .size = 9, - .content = "mtk_menu\n", - }, - { - .path = "/sys/devices/system/cpu/cputopo/cpus_per_cluster", - .size = 25, - .content = - "cluster0: f\n" - "cluster1: f0\n", - }, - { - .path = "/sys/devices/system/cpu/cputopo/glbinfo", - .size = 72, - .content = - "big/little arch: yes\n" - "nr_cups: 8\n" - "nr_clusters: 2\n" - "cluster0: f\n" - "cluster1: f0\n", - }, - { - .path = "/sys/devices/system/cpu/cputopo/is_big_little", - .size = 2, - .content = "1\n", - }, - { - .path = "/sys/devices/system/cpu/cputopo/is_multi_cluster", - .size = 2, - .content = "1\n", - }, - { - .path = "/sys/devices/system/cpu/cputopo/nr_clusters", - .size = 2, - .content = "2\n", - }, - { - .path = "/sys/devices/system/cpu/cpu0/cpuidle/driver/name", - .size = 26, - .content = "mt67xx_acao_cpuidle_set_0\n", - }, - { - .path = "/sys/devices/system/cpu/cpu0/cpufreq/affected_cpus", - .size = 8, - .content = "0 1 2 3\n", - }, - { - .path = "/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq", - .size = 8, - .content = "1989000\n", - }, - { - .path = "/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_min_freq", - .size = 7, - .content = "793000\n", - }, - { - .path = "/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_transition_latency", - .size = 5, - .content = "1000\n", - }, - { - .path = "/sys/devices/system/cpu/cpu0/cpufreq/related_cpus", - .size = 8, - .content = "0 1 2 3\n", - }, - { - .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies", - .size = 127, - .content = "1989000 1924000 1846000 1781000 1716000 1677000 1625000 1586000 1508000 1417000 1326000 1248000 1131000 1014000 910000 793000 \n", - }, - { - .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors", - .size = 64, - .content = "ondemand userspace powersave interactive performance schedplus \n", - }, - { - .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq", - .size = 7, - .content = "793000\n", - }, - { - .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_driver", - .size = 11, - .content = "mt-cpufreq\n", - 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"/sys/devices/system/cpu/cpu4/cpufreq/cpuinfo_transition_latency", + .size = 5, + .content = "1000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/related_cpus", + .size = 8, + .content = "4 5 6 7\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_available_frequencies", + .size = 127, + .content = + "1989000 1924000 1846000 1781000 1716000 1677000 1625000 1586000 1508000 1417000 1326000 1248000 1131000 1014000 910000 793000 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_available_governors", + .size = 64, + .content = + "ondemand userspace powersave interactive performance schedplus \n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_cur_freq", + .size = 7, + .content = "793000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_driver", + .size = 11, + .content = "mt-cpufreq\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_max_freq", + .size = 7, + .content = "793000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_min_freq", + .size = 7, + .content = "793000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/sched/down_throttle_nsec", + .size = 8, + .content = "4000000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/sched/up_throttle_nsec", + .size = 2, + .content = "0\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/time_in_state", + .size = 178, + .content = "1989000 5860\n" + "1924000 14\n" + "1846000 100\n" + "1781000 2\n" + "1716000 2\n" + "1677000 0\n" + "1625000 12\n" + "1586000 10\n" + "1508000 0\n" + "1417000 12\n" + "1326000 4\n" + "1248000 51\n" + "1131000 240\n" + "1014000 138\n" + "910000 180\n" + "793000 94210\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/total_trans", + .size = 4, + .content = "162\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/trans_table", + .size = 2941, + .content = + " From : To\n" + " : 1989000 1924000 1846000 1781000 1716000 1677000 1625000 1586000 1508000 1417000 1326000 1248000 1131000 1014000 910000 793000 \n" + " 1989000: 0 4 5 1 0 0 1 1 0 3 1 0 1 0 2 14 \n" + " 1924000: 4 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 \n" + " 1846000: 9 0 0 0 0 0 0 0 0 0 0 0 0 2 4 1 \n" + " 1781000: 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 \n" + " 1716000: 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 \n" + " 1677000: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \n" + " 1625000: 2 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 \n" + " 1586000: 2 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 \n" + " 1508000: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \n" + " 1417000: 2 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 \n" + " 1326000: 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 \n" + " 1248000: 1 1 0 0 0 0 0 1 0 1 1 0 3 0 0 2 \n" + " 1131000: 3 0 0 0 0 0 0 0 0 0 0 3 0 2 0 8 \n" + " 1014000: 2 0 2 0 0 0 0 0 0 0 0 0 5 0 1 2 \n" + " 910000: 5 0 1 0 0 0 0 0 0 0 0 1 0 2 0 7 \n" + " 793000: 3 0 8 0 0 0 1 1 0 0 0 2 6 5 9 0 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/topology/core_id", + .size = 2, + .content = "0\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/topology/core_siblings", + .size = 3, + .content = "f0\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/topology/core_siblings_list", + .size = 4, + .content = "4-7\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/topology/physical_package_id", + .size = 2, + .content = "1\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/topology/thread_siblings", + .size = 3, + .content = "10\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/topology/thread_siblings_list", + .size = 2, + .content = "4\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpuidle/driver/name", + .size = 26, + .content = "mt67xx_acao_cpuidle_set_1\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/affected_cpus", + .size = 8, + .content = "4 5 6 7\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/cpuinfo_max_freq", + .size = 8, + .content = "1989000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/cpuinfo_min_freq", + .size = 7, + .content = "793000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/cpuinfo_transition_latency", + .size = 5, + .content = "1000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/related_cpus", + .size = 8, + .content = "4 5 6 7\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_available_frequencies", + .size = 127, + .content = + "1989000 1924000 1846000 1781000 1716000 1677000 1625000 1586000 1508000 1417000 1326000 1248000 1131000 1014000 910000 793000 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_available_governors", + .size = 64, + .content = + "ondemand userspace powersave interactive performance schedplus \n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_cur_freq", + .size = 7, + .content = "793000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_driver", + .size = 11, + .content = "mt-cpufreq\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_max_freq", + .size = 7, + .content = "793000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_min_freq", + .size = 7, + .content = "793000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/sched/down_throttle_nsec", + .size = 8, + .content = "4000000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/sched/up_throttle_nsec", + .size = 2, + .content = "0\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/time_in_state", + .size = 178, + .content = "1989000 5860\n" + "1924000 14\n" + "1846000 100\n" + "1781000 2\n" + "1716000 2\n" + "1677000 0\n" + "1625000 12\n" + "1586000 10\n" + "1508000 0\n" + "1417000 12\n" + "1326000 4\n" + "1248000 51\n" + "1131000 240\n" + "1014000 138\n" + "910000 180\n" + "793000 94410\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/total_trans", + .size = 4, + .content = "162\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/trans_table", + .size = 2941, + .content = " From : To\n" + " : 1989000 1924000 1846000 1781000 1716000 1677000 1625000 1586000 1508000 1417000 1326000 1248000 1131000 1014000 910000 793000 \n" + " 1989000: 0 4 5 1 0 0 1 1 0 3 1 0 1 0 2 14 \n" + " 1924000: 4 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 \n" + " 1846000: 9 0 0 0 0 0 0 0 0 0 0 0 0 2 4 1 \n" + " 1781000: 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 \n" + " 1716000: 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 \n" + " 1677000: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \n" + " 1625000: 2 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 \n" + " 1586000: 2 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 \n" + " 1508000: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \n" + " 1417000: 2 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 \n" + " 1326000: 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 \n" + " 1248000: 1 1 0 0 0 0 0 1 0 1 1 0 3 0 0 2 \n" + " 1131000: 3 0 0 0 0 0 0 0 0 0 0 3 0 2 0 8 \n" + " 1014000: 2 0 2 0 0 0 0 0 0 0 0 0 5 0 1 2 \n" + " 910000: 5 0 1 0 0 0 0 0 0 0 0 1 0 2 0 7 \n" + " 793000: 3 0 8 0 0 0 1 1 0 0 0 2 6 5 9 0 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/topology/core_id", + .size = 2, + .content = "1\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/topology/core_siblings", + .size = 3, + .content = "f0\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/topology/core_siblings_list", + .size = 4, + .content = "4-7\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/topology/physical_package_id", + .size = 2, + .content = "1\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/topology/thread_siblings", + .size = 3, + .content = "20\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/topology/thread_siblings_list", + .size = 2, + .content = "5\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpuidle/driver/name", + .size = 26, + .content = "mt67xx_acao_cpuidle_set_1\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/affected_cpus", + .size = 8, + .content = "4 5 6 7\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/cpuinfo_max_freq", + .size = 8, + .content = "1989000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/cpuinfo_min_freq", + .size = 7, + .content = "793000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/cpuinfo_transition_latency", + .size = 5, + .content = "1000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/related_cpus", + .size = 8, + .content = "4 5 6 7\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_available_frequencies", + .size = 127, + .content = + "1989000 1924000 1846000 1781000 1716000 1677000 1625000 1586000 1508000 1417000 1326000 1248000 1131000 1014000 910000 793000 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_available_governors", + .size = 64, + .content = + "ondemand userspace powersave interactive performance schedplus \n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_cur_freq", + .size = 7, + .content = "793000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_driver", + .size = 11, + .content = "mt-cpufreq\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_max_freq", + .size = 7, + .content = "793000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_min_freq", + .size = 7, + .content = "793000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/sched/down_throttle_nsec", + .size = 8, + .content = "4000000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/sched/up_throttle_nsec", + .size = 2, + .content = "0\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/time_in_state", + .size = 178, + .content = "1989000 5860\n" + "1924000 14\n" + "1846000 100\n" + "1781000 2\n" + "1716000 2\n" + "1677000 0\n" + "1625000 12\n" + "1586000 10\n" + "1508000 0\n" + "1417000 12\n" + "1326000 4\n" + "1248000 51\n" + "1131000 240\n" + "1014000 138\n" + "910000 180\n" + "793000 94609\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/total_trans", + .size = 4, + .content = "162\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/trans_table", + .size = 2941, + .content = + " From : To\n" + " : 1989000 1924000 1846000 1781000 1716000 1677000 1625000 1586000 1508000 1417000 1326000 1248000 1131000 1014000 910000 793000 \n" + " 1989000: 0 4 5 1 0 0 1 1 0 3 1 0 1 0 2 14 \n" + " 1924000: 4 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 \n" + " 1846000: 9 0 0 0 0 0 0 0 0 0 0 0 0 2 4 1 \n" + " 1781000: 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 \n" + " 1716000: 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 \n" + " 1677000: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \n" + " 1625000: 2 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 \n" + " 1586000: 2 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 \n" + " 1508000: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \n" + " 1417000: 2 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 \n" + " 1326000: 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 \n" + " 1248000: 1 1 0 0 0 0 0 1 0 1 1 0 3 0 0 2 \n" + " 1131000: 3 0 0 0 0 0 0 0 0 0 0 3 0 2 0 8 \n" + " 1014000: 2 0 2 0 0 0 0 0 0 0 0 0 5 0 1 2 \n" + " 910000: 5 0 1 0 0 0 0 0 0 0 0 1 0 2 0 7 \n" + " 793000: 3 0 8 0 0 0 1 1 0 0 0 2 6 5 9 0 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/topology/core_id", + .size = 2, + .content = "2\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/topology/core_siblings", + .size = 3, + .content = "f0\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/topology/core_siblings_list", + .size = 4, + .content = "4-7\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/topology/physical_package_id", + .size = 2, + .content = "1\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/topology/thread_siblings", + .size = 3, + .content = "40\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/topology/thread_siblings_list", + .size = 2, + .content = "6\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpuidle/driver/name", + .size = 26, + .content = "mt67xx_acao_cpuidle_set_1\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/affected_cpus", + .size = 8, + .content = "4 5 6 7\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/cpuinfo_max_freq", + .size = 8, + .content = "1989000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/cpuinfo_min_freq", + .size = 7, + .content = "793000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/cpuinfo_transition_latency", + .size = 5, + .content = "1000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/related_cpus", + .size = 8, + .content = "4 5 6 7\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_available_frequencies", + .size = 127, + .content = + "1989000 1924000 1846000 1781000 1716000 1677000 1625000 1586000 1508000 1417000 1326000 1248000 1131000 1014000 910000 793000 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_available_governors", + .size = 64, + .content = + "ondemand userspace powersave interactive performance schedplus \n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_cur_freq", + .size = 7, + .content = "793000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_driver", + .size = 11, + .content = "mt-cpufreq\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_max_freq", + .size = 7, + .content = "793000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_min_freq", + .size = 7, + .content = "793000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/sched/down_throttle_nsec", + .size = 8, + .content = "4000000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/sched/up_throttle_nsec", + .size = 2, + .content = "0\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/time_in_state", + .size = 178, + .content = "1989000 5860\n" + "1924000 14\n" + "1846000 100\n" + "1781000 2\n" + "1716000 2\n" + "1677000 0\n" + "1625000 12\n" + "1586000 10\n" + "1508000 0\n" + "1417000 12\n" + "1326000 4\n" + "1248000 51\n" + "1131000 240\n" + "1014000 138\n" + "910000 180\n" + "793000 94810\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/total_trans", + .size = 4, + .content = "162\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/trans_table", + .size = 2941, + .content = + " From : To\n" + " : 1989000 1924000 1846000 1781000 1716000 1677000 1625000 1586000 1508000 1417000 1326000 1248000 1131000 1014000 910000 793000 \n" + " 1989000: 0 4 5 1 0 0 1 1 0 3 1 0 1 0 2 14 \n" + " 1924000: 4 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 \n" + " 1846000: 9 0 0 0 0 0 0 0 0 0 0 0 0 2 4 1 \n" + " 1781000: 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 \n" + " 1716000: 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 \n" + " 1677000: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \n" + " 1625000: 2 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 \n" + " 1586000: 2 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 \n" + " 1508000: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 \n" + " 1417000: 2 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 \n" + " 1326000: 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 \n" + " 1248000: 1 1 0 0 0 0 0 1 0 1 1 0 3 0 0 2 \n" + " 1131000: 3 0 0 0 0 0 0 0 0 0 0 3 0 2 0 8 \n" + " 1014000: 2 0 2 0 0 0 0 0 0 0 0 0 5 0 1 2 \n" + " 910000: 5 0 1 0 0 0 0 0 0 0 0 1 0 2 0 7 \n" + " 793000: 3 0 8 0 0 0 1 1 0 0 0 2 6 5 9 0 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/topology/core_id", + .size = 2, + .content = "3\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/topology/core_siblings", + .size = 3, + .content = "f0\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/topology/core_siblings_list", + .size = 4, + .content = "4-7\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/topology/physical_package_id", + .size = 2, + .content = "1\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/topology/thread_siblings", + .size = 3, + .content = "80\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/topology/thread_siblings_list", + .size = 2, + .content = "7\n", + }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -5486,6 +5495,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wifi.tethering.interface", .value = "ap0", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/oppo-r9.cc b/test/mock/oppo-r9.cc index e45e2e35..28499db3 100644 --- a/test/mock/oppo-r9.cc +++ b/test/mock/oppo-r9.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(8, cpuinfo_get_processors_count()); @@ -294,8 +293,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("MediaTek MT6755", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "MediaTek MT6755", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -337,59 +338,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -473,43 +474,43 @@ TEST(ISA, fcma) { } TEST(ISA, aes) { - #if CPUINFO_ARCH_ARM64 - ASSERT_TRUE(cpuinfo_has_arm_aes()); - #elif CPUINFO_ARCH_ARM - ASSERT_FALSE(cpuinfo_has_arm_aes()); - #endif +#if CPUINFO_ARCH_ARM64 + ASSERT_TRUE(cpuinfo_has_arm_aes()); +#elif CPUINFO_ARCH_ARM + ASSERT_FALSE(cpuinfo_has_arm_aes()); +#endif } TEST(ISA, sha1) { - #if CPUINFO_ARCH_ARM64 - ASSERT_TRUE(cpuinfo_has_arm_sha1()); - #elif CPUINFO_ARCH_ARM - ASSERT_FALSE(cpuinfo_has_arm_sha1()); - #endif +#if CPUINFO_ARCH_ARM64 + ASSERT_TRUE(cpuinfo_has_arm_sha1()); +#elif CPUINFO_ARCH_ARM + ASSERT_FALSE(cpuinfo_has_arm_sha1()); +#endif } TEST(ISA, sha2) { - #if CPUINFO_ARCH_ARM64 - ASSERT_TRUE(cpuinfo_has_arm_sha2()); - #elif CPUINFO_ARCH_ARM - ASSERT_FALSE(cpuinfo_has_arm_sha2()); - #endif +#if CPUINFO_ARCH_ARM64 + ASSERT_TRUE(cpuinfo_has_arm_sha2()); +#elif CPUINFO_ARCH_ARM + ASSERT_FALSE(cpuinfo_has_arm_sha2()); +#endif } TEST(ISA, pmull) { - #if CPUINFO_ARCH_ARM64 - ASSERT_TRUE(cpuinfo_has_arm_pmull()); - #elif CPUINFO_ARCH_ARM - ASSERT_FALSE(cpuinfo_has_arm_pmull()); - #endif +#if CPUINFO_ARCH_ARM64 + ASSERT_TRUE(cpuinfo_has_arm_pmull()); +#elif CPUINFO_ARCH_ARM + ASSERT_FALSE(cpuinfo_has_arm_pmull()); +#endif } TEST(ISA, crc32) { - #if CPUINFO_ARCH_ARM64 - ASSERT_TRUE(cpuinfo_has_arm_crc32()); - #elif CPUINFO_ARCH_ARM - ASSERT_FALSE(cpuinfo_has_arm_crc32()); - #endif +#if CPUINFO_ARCH_ARM64 + ASSERT_TRUE(cpuinfo_has_arm_crc32()); +#elif CPUINFO_ARCH_ARM + ASSERT_FALSE(cpuinfo_has_arm_crc32()); +#endif } TEST(L1I, count) { @@ -534,8 +535,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -586,8 +589,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -638,8 +643,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/oppo-r9.h b/test/mock/oppo-r9.h index 5b687a20..53f6dc5b 100644 --- a/test/mock/oppo-r9.h +++ b/test/mock/oppo-r9.h @@ -3,26 +3,25 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 421, - .content = - "Processor\t: AArch64 Processor rev 2 (aarch64)\n" - "processor\t: 0\n" - "BogoMIPS\t: 26.00\n" - "Features\t: fp asimd aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: AArch64\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 2\n" - "processor\t: 1\n" - "BogoMIPS\t: 26.00\n" - "Features\t: fp asimd aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: AArch64\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 2\n" - "\n" - "Hardware\t: MT6755\n", + .content = "Processor\t: AArch64 Processor rev 2 (aarch64)\n" + "processor\t: 0\n" + "BogoMIPS\t: 26.00\n" + "Features\t: fp asimd aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: AArch64\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 2\n" + "processor\t: 1\n" + "BogoMIPS\t: 26.00\n" + "Features\t: fp asimd aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: AArch64\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 2\n" + "\n" + "Hardware\t: MT6755\n", }, #elif CPUINFO_ARCH_ARM { @@ -457,23 +456,22 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpufreq/all_time_in_state", .size = 260, - .content = - "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\t\n" - "156000\t\t0\t\t\n" - "286000\t\tN/A\t\t\n" - "338000\t\t0\t\t\n" - "494000\t\t0\t\t\n" - "598000\t\t0\t\t\n" - "663000\t\tN/A\t\t\n" - "689000\t\t0\t\t\n" - "871000\t\t0\t\t\n" - "1014000\t\t0\t\t\n" - "1027000\t\tN/A\t\t\n" - "1144000\t\t18232\t\t\n" - "1196000\t\tN/A\t\t\n" - "1573000\t\tN/A\t\t\n" - "1755000\t\tN/A\t\t\n" - "1950000\t\tN/A\t\t\n", + .content = "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\t\n" + "156000\t\t0\t\t\n" + "286000\t\tN/A\t\t\n" + "338000\t\t0\t\t\n" + "494000\t\t0\t\t\n" + "598000\t\t0\t\t\n" + "663000\t\tN/A\t\t\n" + "689000\t\t0\t\t\n" + "871000\t\t0\t\t\n" + "1014000\t\t0\t\t\n" + "1027000\t\tN/A\t\t\n" + "1144000\t\t18232\t\t\n" + "1196000\t\tN/A\t\t\n" + "1573000\t\tN/A\t\t\n" + "1755000\t\tN/A\t\t\n" + "1950000\t\tN/A\t\t\n", }, { .path = "/sys/devices/system/cpu/cpuidle/current_driver", @@ -493,11 +491,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cputopo/glbinfo", .size = 71, - .content = - "big/little arch: yes\n" - "big/little cpumask:f0/f\n" - "nr_cups: 8\n" - "nr_clusters: 2\n", + .content = "big/little arch: yes\n" + "big/little cpumask:f0/f\n" + "nr_cups: 8\n" + "nr_clusters: 2\n", }, { .path = "/sys/devices/system/cpu/cputopo/is_big_little", @@ -592,9 +589,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/trans_table", .size = 29, - .content = - " From : To\n" - " : \n", + .content = " From : To\n" + " : \n", }, { .path = "/sys/devices/system/cpu/cpu0/topology/core_id", @@ -651,7 +647,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 8, .content = "1144000\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -2687,6 +2683,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.wfd.security.image", .value = "1", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/padcod-10.1.cc b/test/mock/padcod-10.1.cc index a9a2ee27..95083eef 100644 --- a/test/mock/padcod-10.1.cc +++ b/test/mock/padcod-10.1.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(4, cpuinfo_get_processors_count()); @@ -208,8 +207,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Allwinner A33", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Allwinner A33", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -400,8 +401,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -452,8 +455,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -504,8 +509,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/padcod-10.1.h b/test/mock/padcod-10.1.h index 056bbd72..48785e69 100644 --- a/test/mock/padcod-10.1.h +++ b/test/mock/padcod-10.1.h @@ -2,122 +2,120 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 320, - .content = - "Processor\t: ARMv7 Processor rev 5 (v7l)\n" - "processor\t: 0\n" - "BogoMIPS\t: 3428.56\n" - "\n" - "Features\t: swp half thumb fastmult vfp edsp thumbee neon vfpv3 tls vfpv4 idiva idivt \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xc07\n" - "CPU revision\t: 5\n" - "\n" - "Hardware\t: sun8i\n" - "Revision\t: 0000\n" - "Serial\t\t: 86441af7d7f700000000\n", + .content = "Processor\t: ARMv7 Processor rev 5 (v7l)\n" + "processor\t: 0\n" + "BogoMIPS\t: 3428.56\n" + "\n" + "Features\t: swp half thumb fastmult vfp edsp thumbee neon vfpv3 tls vfpv4 idiva idivt \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xc07\n" + "CPU revision\t: 5\n" + "\n" + "Hardware\t: sun8i\n" + "Revision\t: 0000\n" + "Serial\t\t: 86441af7d7f700000000\n", }, { .path = "/system/build.prop", .size = 2845, - .content = - "# begin build properties\n" - "# autogenerated by buildinfo.sh\n" - "ro.build.id=KVT49L\n" - "ro.build.display.id=astar_y3-eng 4.4.2 KVT49L 20151112 test-keys\n" - "ro.build.version.incremental=20151112\n" - "ro.build.version.sdk=19\n" - "ro.build.version.codename=REL\n" - "ro.build.version.release=4.4.2\n" - "ro.build.date=2015xC4xEA 11xD4xC2 12xC8xD5 xD0xC7xC6xDAxCBxC4 16:07:41 CST\n" - "ro.build.date.utc=1447315661\n" - "ro.build.type=eng\n" - "ro.build.user=ytx\n" - "ro.build.host=Android\n" - "ro.build.tags=test-keys\n" - "ro.product.model=V11\n" - "ro.product.brand=Allwinner\n" - "ro.product.name=astar_y3\n" - "ro.product.device=astar-y3\n" - "ro.product.board=exdroid\n" - "ro.product.cpu.abi=armeabi-v7a\n" - "ro.product.cpu.abi2=armeabi\n" - "ro.product.manufacturer=softwinner\n" - "ro.product.locale.language=en\n" - "ro.product.locale.region=US\n" - "ro.wifi.channels=\n" - "ro.board.platform=polaris\n" - "# ro.build.product is obsolete; use ro.product.device\n" - "ro.build.product=astar-y3\n" - "# Do not try to parse ro.build.description or .fingerprint\n" - "ro.build.description=astar_y3-eng 4.4.2 KVT49L 20151112 test-keys\n" - "ro.build.fingerprint=Allwinner/astar_y3/astar-y3:4.4.2/KVT49L/20151112:eng/test-keys\n" - "ro.build.characteristics=tablet\n" - "# end build properties\n" - "\n" - "#\n" - "# ADDITIONAL_BUILD_PROPERTIES\n" - "#\n" - "ro.com.android.dateformat=MM-dd-yyyy\n" - "ro.config.ringtone=Ring_Synth_04.ogg\n" - "ro.config.notification_sound=pixiedust.ogg\n" - "ro.carrier=unknown\n" - "ro.config.alarm_alert=Alarm_Classic.ogg\n" - "ro.zygote.disable_gl_preload=true\n" - "persist.sys.strictmode.visual=0\n" - "persist.sys.strictmode.disable=1\n" - "persist.sys.plimit=0\n" - "ro.opengles.version=131072\n" - "ro.kernel.android.checkjni=0\n" - "ro.reversion.aw_sdk_tag=exdroid4.4.2_r2-a33-v2.0\n" - "ro.sys.cputype=QuadCore-A33\n" - "wifi.interface=wlan0\n" - "wifi.supplicant_scan_interval=15\n" - "keyguard.no_require_sim=true\n" - "ro.sys.network_location=true\n" - "persist.demo.hdmirotationlock=0\n" - "drm.service.enabled=true\n" - "dalvik.vm.heapstartsize=8m\n" - "dalvik.vm.heapgrowthlimit=64m\n" - "dalvik.vm.heapsize=384m\n" - "dalvik.vm.heaptargetutilization=0.75\n" - "dalvik.vm.heapminfree=512k\n" - "dalvik.vm.heapmaxfree=8m\n" - "ro.sw.embeded.telephony=false\n" - "persist.sys.timezone=Europe/London\n" - "persist.sys.language=en\n" - "persist.sys.country=US\n" - "ro.product.8723b_bt.used=true\n" - "persist.sys.usb.config=mass_storage,adb\n" - "ro.udisk.lable=Polaris\n" - "ro.font.scale=1.15\n" - "ro.hwa.force=false\n" - "rw.logger=0\n" - "ro.sys.bootfast=true\n" - "debug.hwc.showfps=0\n" - "eken.board.platform=exDroid\n" - "eken.device.telephone=false\n" - "eken.wmt.homepage_base=http://www.google.com\n" - "eken.hardware=sun7i\n" - "eken.hardware.screen.size=11\n" - "eken.hardware.screen.res=1024x600\n" - "eken.build.version.release=4.4.1\n" - "eken.build.version.sdk=17\n" - "eken.product.model=V11\n" - "eken.product.device=astar_y3\n" - "eken.product.name=astar_y3\n" - "eken.product.manufacturer=eken\n" - "debug.hwui.render_dirty_regions=false\n" - "ro.sys.mutedrm=true\n" - "ro.sf.lcd_density=160\n" - "ro.product.firmware=v2.0\n" - "ro.setupwizard.mode=OPTIONAL\n" - "ro.com.google.gmsversion=4.4_r3\n" - "persist.sys.dalvik.vm.lib=libdvm.so\n" - "dalvik.vm.dexopt-flags=v=n,m=y\n" - "net.bt.name=Android\n" - "dalvik.vm.stack-trace-file=/data/anr/traces.txt\n", + .content = "# begin build properties\n" + "# autogenerated by buildinfo.sh\n" + "ro.build.id=KVT49L\n" + "ro.build.display.id=astar_y3-eng 4.4.2 KVT49L 20151112 test-keys\n" + "ro.build.version.incremental=20151112\n" + "ro.build.version.sdk=19\n" + "ro.build.version.codename=REL\n" + "ro.build.version.release=4.4.2\n" + "ro.build.date=2015xC4xEA 11xD4xC2 12xC8xD5 xD0xC7xC6xDAxCBxC4 16:07:41 CST\n" + "ro.build.date.utc=1447315661\n" + "ro.build.type=eng\n" + "ro.build.user=ytx\n" + "ro.build.host=Android\n" + "ro.build.tags=test-keys\n" + "ro.product.model=V11\n" + "ro.product.brand=Allwinner\n" + "ro.product.name=astar_y3\n" + "ro.product.device=astar-y3\n" + "ro.product.board=exdroid\n" + "ro.product.cpu.abi=armeabi-v7a\n" + "ro.product.cpu.abi2=armeabi\n" + "ro.product.manufacturer=softwinner\n" + "ro.product.locale.language=en\n" + "ro.product.locale.region=US\n" + "ro.wifi.channels=\n" + "ro.board.platform=polaris\n" + "# ro.build.product is obsolete; use ro.product.device\n" + "ro.build.product=astar-y3\n" + "# Do not try to parse ro.build.description or .fingerprint\n" + "ro.build.description=astar_y3-eng 4.4.2 KVT49L 20151112 test-keys\n" + "ro.build.fingerprint=Allwinner/astar_y3/astar-y3:4.4.2/KVT49L/20151112:eng/test-keys\n" + "ro.build.characteristics=tablet\n" + "# end build properties\n" + "\n" + "#\n" + "# ADDITIONAL_BUILD_PROPERTIES\n" + "#\n" + "ro.com.android.dateformat=MM-dd-yyyy\n" + "ro.config.ringtone=Ring_Synth_04.ogg\n" + "ro.config.notification_sound=pixiedust.ogg\n" + "ro.carrier=unknown\n" + "ro.config.alarm_alert=Alarm_Classic.ogg\n" + "ro.zygote.disable_gl_preload=true\n" + "persist.sys.strictmode.visual=0\n" + "persist.sys.strictmode.disable=1\n" + "persist.sys.plimit=0\n" + "ro.opengles.version=131072\n" + "ro.kernel.android.checkjni=0\n" + "ro.reversion.aw_sdk_tag=exdroid4.4.2_r2-a33-v2.0\n" + "ro.sys.cputype=QuadCore-A33\n" + "wifi.interface=wlan0\n" + "wifi.supplicant_scan_interval=15\n" + "keyguard.no_require_sim=true\n" + "ro.sys.network_location=true\n" + "persist.demo.hdmirotationlock=0\n" + "drm.service.enabled=true\n" + "dalvik.vm.heapstartsize=8m\n" + "dalvik.vm.heapgrowthlimit=64m\n" + "dalvik.vm.heapsize=384m\n" + "dalvik.vm.heaptargetutilization=0.75\n" + "dalvik.vm.heapminfree=512k\n" + "dalvik.vm.heapmaxfree=8m\n" + "ro.sw.embeded.telephony=false\n" + "persist.sys.timezone=Europe/London\n" + "persist.sys.language=en\n" + "persist.sys.country=US\n" + "ro.product.8723b_bt.used=true\n" + "persist.sys.usb.config=mass_storage,adb\n" + "ro.udisk.lable=Polaris\n" + "ro.font.scale=1.15\n" + "ro.hwa.force=false\n" + "rw.logger=0\n" + "ro.sys.bootfast=true\n" + "debug.hwc.showfps=0\n" + "eken.board.platform=exDroid\n" + "eken.device.telephone=false\n" + "eken.wmt.homepage_base=http://www.google.com\n" + "eken.hardware=sun7i\n" + "eken.hardware.screen.size=11\n" + "eken.hardware.screen.res=1024x600\n" + "eken.build.version.release=4.4.1\n" + "eken.build.version.sdk=17\n" + "eken.product.model=V11\n" + "eken.product.device=astar_y3\n" + "eken.product.name=astar_y3\n" + "eken.product.manufacturer=eken\n" + "debug.hwui.render_dirty_regions=false\n" + "ro.sys.mutedrm=true\n" + "ro.sf.lcd_density=160\n" + "ro.product.firmware=v2.0\n" + "ro.setupwizard.mode=OPTIONAL\n" + "ro.com.google.gmsversion=4.4_r3\n" + "persist.sys.dalvik.vm.lib=libdvm.so\n" + "dalvik.vm.dexopt-flags=v=n,m=y\n" + "net.bt.name=Android\n" + "dalvik.vm.stack-trace-file=/data/anr/traces.txt\n", }, { .path = "/sys/devices/system/cpu/kernel_max", @@ -202,24 +200,23 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 171, - .content = - "60000 0\n" - "120000 213\n" - "240000 106\n" - "312000 6\n" - "408000 29\n" - "504000 0\n" - "600000 0\n" - "648000 163\n" - "720000 48\n" - "816000 62\n" - "912000 5\n" - "1008000 7\n" - "1104000 47\n" - "1200000 3381\n" - "1344000 0\n" - "1440000 0\n" - "1536000 0\n", + .content = "60000 0\n" + "120000 213\n" + "240000 106\n" + "312000 6\n" + "408000 29\n" + "504000 0\n" + "600000 0\n" + "648000 163\n" + "720000 48\n" + "816000 62\n" + "912000 5\n" + "1008000 7\n" + "1104000 47\n" + "1200000 3381\n" + "1344000 0\n" + "1440000 0\n" + "1536000 0\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -280,7 +277,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "0\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -968,6 +965,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.driver.status", .value = "ok", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/pixel-2-xl.cc b/test/mock/pixel-2-xl.cc index 612acb1a..3a8a7205 100644 --- a/test/mock/pixel-2-xl.cc +++ b/test/mock/pixel-2-xl.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(8, cpuinfo_get_processors_count()); @@ -334,8 +333,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Qualcomm MSM8998", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Qualcomm MSM8998", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -377,59 +378,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -580,8 +581,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -658,8 +661,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -717,8 +722,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/pixel-2-xl.h b/test/mock/pixel-2-xl.h index 28c379c8..a891d17a 100644 --- a/test/mock/pixel-2-xl.h +++ b/test/mock/pixel-2-xl.h @@ -2,81 +2,80 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 1540, - .content = - "Processor\t: AArch64 Processor rev 1 (aarch64)\n" - "processor\t: 0\n" - "BogoMIPS\t: 38.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0xa\n" - "CPU part\t: 0x801\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 1\n" - "BogoMIPS\t: 38.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0xa\n" - "CPU part\t: 0x801\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 2\n" - "BogoMIPS\t: 38.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0xa\n" - "CPU part\t: 0x801\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 3\n" - "BogoMIPS\t: 38.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0xa\n" - "CPU part\t: 0x801\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 4\n" - "BogoMIPS\t: 38.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0xa\n" - "CPU part\t: 0x800\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 5\n" - "BogoMIPS\t: 38.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0xa\n" - "CPU part\t: 0x800\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 6\n" - "BogoMIPS\t: 38.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0xa\n" - "CPU part\t: 0x800\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 7\n" - "BogoMIPS\t: 38.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0xa\n" - "CPU part\t: 0x800\n" - "CPU revision\t: 1\n" - "\n" - "Hardware\t: Qualcomm Technologies, Inc MSM8998\n", + .content = "Processor\t: AArch64 Processor rev 1 (aarch64)\n" + "processor\t: 0\n" + "BogoMIPS\t: 38.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0xa\n" + "CPU part\t: 0x801\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 1\n" + "BogoMIPS\t: 38.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0xa\n" + "CPU part\t: 0x801\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 2\n" + "BogoMIPS\t: 38.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0xa\n" + "CPU part\t: 0x801\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 3\n" + "BogoMIPS\t: 38.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0xa\n" + "CPU part\t: 0x801\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 4\n" + "BogoMIPS\t: 38.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0xa\n" + "CPU part\t: 0x800\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 5\n" + "BogoMIPS\t: 38.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0xa\n" + "CPU part\t: 0x800\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 6\n" + "BogoMIPS\t: 38.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0xa\n" + "CPU part\t: 0x800\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 7\n" + "BogoMIPS\t: 38.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0xa\n" + "CPU part\t: 0x800\n" + "CPU revision\t: 1\n" + "\n" + "Hardware\t: Qualcomm Technologies, Inc MSM8998\n", }, { .path = "/sys/devices/system/cpu/kernel_max", @@ -111,61 +110,60 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpufreq/all_time_in_state", .size = 2793, - .content = - "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\t\n" - "300000\t\t622774\t\t622774\t\t622774\t\t622774\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "364800\t\t7579\t\t7579\t\t7579\t\t7579\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "441600\t\t7761\t\t7761\t\t7761\t\t7761\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "518400\t\t6959\t\t6959\t\t6959\t\t6959\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "595200\t\t1061\t\t1061\t\t1061\t\t1061\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "672000\t\t1038\t\t1038\t\t1038\t\t1038\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "748800\t\t1601\t\t1601\t\t1601\t\t1601\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "825600\t\t1238\t\t1238\t\t1238\t\t1238\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "883200\t\t476\t\t476\t\t476\t\t476\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "960000\t\t742\t\t742\t\t742\t\t742\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1036800\t\t482\t\t482\t\t482\t\t482\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1094400\t\t1064\t\t1064\t\t1064\t\t1064\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1171200\t\t1026\t\t1026\t\t1026\t\t1026\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1248000\t\t1072\t\t1072\t\t1072\t\t1072\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1324800\t\t485\t\t485\t\t485\t\t485\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1401600\t\t826\t\t826\t\t826\t\t826\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1478400\t\t410\t\t410\t\t410\t\t410\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1555200\t\t1405\t\t1405\t\t1405\t\t1405\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1670400\t\t997\t\t997\t\t997\t\t997\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1747200\t\t1330\t\t1330\t\t1330\t\t1330\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1824000\t\t816\t\t816\t\t816\t\t816\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "1900800\t\t34020\t\t34020\t\t34020\t\t34020\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" - "300000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t659914\t\t659914\t\t659914\t\t659914\t\t\n" - "345600\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t1638\t\t1638\t\t1638\t\t1638\t\t\n" - "422400\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t1418\t\t1418\t\t1418\t\t1418\t\t\n" - "499200\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t1723\t\t1723\t\t1723\t\t1723\t\t\n" - "576000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t1435\t\t1435\t\t1435\t\t1435\t\t\n" - "652800\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t1728\t\t1728\t\t1728\t\t1728\t\t\n" - "729600\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t751\t\t751\t\t751\t\t751\t\t\n" - "806400\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t1014\t\t1014\t\t1014\t\t1014\t\t\n" - "902400\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t799\t\t799\t\t799\t\t799\t\t\n" - "979200\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t536\t\t536\t\t536\t\t536\t\t\n" - "1056000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t704\t\t704\t\t704\t\t704\t\t\n" - "1132800\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t1112\t\t1112\t\t1112\t\t1112\t\t\n" - "1190400\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t463\t\t463\t\t463\t\t463\t\t\n" - "1267200\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t381\t\t381\t\t381\t\t381\t\t\n" - "1344000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t391\t\t391\t\t391\t\t391\t\t\n" - "1420800\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t568\t\t568\t\t568\t\t568\t\t\n" - "1497600\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t290\t\t290\t\t290\t\t290\t\t\n" - "1574400\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t261\t\t261\t\t261\t\t261\t\t\n" - "1651200\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t422\t\t422\t\t422\t\t422\t\t\n" - "1728000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t669\t\t669\t\t669\t\t669\t\t\n" - "1804800\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t337\t\t337\t\t337\t\t337\t\t\n" - "1881600\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t229\t\t229\t\t229\t\t229\t\t\n" - "1958400\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t225\t\t225\t\t225\t\t225\t\t\n" - "2035200\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t237\t\t237\t\t237\t\t237\t\t\n" - "2112000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t357\t\t357\t\t357\t\t357\t\t\n" - "2208000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t297\t\t297\t\t297\t\t297\t\t\n" - "2265600\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t162\t\t162\t\t162\t\t162\t\t\n" - "2323200\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t141\t\t141\t\t141\t\t141\t\t\n" - "2342400\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t72\t\t72\t\t72\t\t72\t\t\n" - "2361600\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t68\t\t68\t\t68\t\t68\t\t\n" - "2457600\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t16815\t\t16815\t\t16815\t\t16815\t\t\n", + .content = "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\t\n" + "300000\t\t622774\t\t622774\t\t622774\t\t622774\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "364800\t\t7579\t\t7579\t\t7579\t\t7579\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "441600\t\t7761\t\t7761\t\t7761\t\t7761\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "518400\t\t6959\t\t6959\t\t6959\t\t6959\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "595200\t\t1061\t\t1061\t\t1061\t\t1061\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "672000\t\t1038\t\t1038\t\t1038\t\t1038\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "748800\t\t1601\t\t1601\t\t1601\t\t1601\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "825600\t\t1238\t\t1238\t\t1238\t\t1238\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "883200\t\t476\t\t476\t\t476\t\t476\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "960000\t\t742\t\t742\t\t742\t\t742\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "1036800\t\t482\t\t482\t\t482\t\t482\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "1094400\t\t1064\t\t1064\t\t1064\t\t1064\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "1171200\t\t1026\t\t1026\t\t1026\t\t1026\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "1248000\t\t1072\t\t1072\t\t1072\t\t1072\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "1324800\t\t485\t\t485\t\t485\t\t485\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "1401600\t\t826\t\t826\t\t826\t\t826\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "1478400\t\t410\t\t410\t\t410\t\t410\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "1555200\t\t1405\t\t1405\t\t1405\t\t1405\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "1670400\t\t997\t\t997\t\t997\t\t997\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "1747200\t\t1330\t\t1330\t\t1330\t\t1330\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "1824000\t\t816\t\t816\t\t816\t\t816\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "1900800\t\t34020\t\t34020\t\t34020\t\t34020\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t\n" + "300000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t659914\t\t659914\t\t659914\t\t659914\t\t\n" + "345600\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t1638\t\t1638\t\t1638\t\t1638\t\t\n" + "422400\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t1418\t\t1418\t\t1418\t\t1418\t\t\n" + "499200\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t1723\t\t1723\t\t1723\t\t1723\t\t\n" + "576000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t1435\t\t1435\t\t1435\t\t1435\t\t\n" + "652800\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t1728\t\t1728\t\t1728\t\t1728\t\t\n" + "729600\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t751\t\t751\t\t751\t\t751\t\t\n" + "806400\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t1014\t\t1014\t\t1014\t\t1014\t\t\n" + "902400\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t799\t\t799\t\t799\t\t799\t\t\n" + "979200\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t536\t\t536\t\t536\t\t536\t\t\n" + "1056000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t704\t\t704\t\t704\t\t704\t\t\n" + "1132800\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t1112\t\t1112\t\t1112\t\t1112\t\t\n" + "1190400\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t463\t\t463\t\t463\t\t463\t\t\n" + "1267200\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t381\t\t381\t\t381\t\t381\t\t\n" + "1344000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t391\t\t391\t\t391\t\t391\t\t\n" + "1420800\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t568\t\t568\t\t568\t\t568\t\t\n" + "1497600\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t290\t\t290\t\t290\t\t290\t\t\n" + "1574400\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t261\t\t261\t\t261\t\t261\t\t\n" + "1651200\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t422\t\t422\t\t422\t\t422\t\t\n" + "1728000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t669\t\t669\t\t669\t\t669\t\t\n" + "1804800\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t337\t\t337\t\t337\t\t337\t\t\n" + "1881600\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t229\t\t229\t\t229\t\t229\t\t\n" + "1958400\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t225\t\t225\t\t225\t\t225\t\t\n" + "2035200\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t237\t\t237\t\t237\t\t237\t\t\n" + "2112000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t357\t\t357\t\t357\t\t357\t\t\n" + "2208000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t297\t\t297\t\t297\t\t297\t\t\n" + "2265600\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t162\t\t162\t\t162\t\t162\t\t\n" + "2323200\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t141\t\t141\t\t141\t\t141\t\t\n" + "2342400\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t72\t\t72\t\t72\t\t72\t\t\n" + "2361600\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t68\t\t68\t\t68\t\t68\t\t\n" + "2457600\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t16815\t\t16815\t\t16815\t\t16815\t\t\n", }, { .path = "/sys/devices/system/cpu/cpuidle/current_driver", @@ -210,7 +208,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies", .size = 167, - .content = "300000 364800 441600 518400 595200 672000 748800 825600 883200 960000 1036800 1094400 1171200 1248000 1324800 1401600 1478400 1555200 1670400 1747200 1824000 1900800 \n", + .content = + "300000 364800 441600 518400 595200 672000 748800 825600 883200 960000 1036800 1094400 1171200 1248000 1324800 1401600 1478400 1555200 1670400 1747200 1824000 1900800 \n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors", @@ -240,29 +239,28 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 271, - .content = - "300000 622775\n" - "364800 7579\n" - "441600 7761\n" - "518400 6959\n" - "595200 1061\n" - "672000 1038\n" - "748800 1601\n" - "825600 1238\n" - "883200 476\n" - "960000 742\n" - "1036800 482\n" - "1094400 1064\n" - "1171200 1026\n" - "1248000 1072\n" - "1324800 485\n" - "1401600 826\n" - "1478400 410\n" - "1555200 1405\n" - "1670400 997\n" - "1747200 1330\n" - "1824000 816\n" - "1900800 34144\n", + .content = "300000 622775\n" + "364800 7579\n" + "441600 7761\n" + "518400 6959\n" + "595200 1061\n" + "672000 1038\n" + "748800 1601\n" + "825600 1238\n" + "883200 476\n" + "960000 742\n" + "1036800 482\n" + "1094400 1064\n" + "1171200 1026\n" + "1248000 1072\n" + "1324800 485\n" + "1401600 826\n" + "1478400 410\n" + "1555200 1405\n" + "1670400 997\n" + "1747200 1330\n" + "1824000 816\n" + "1900800 34144\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -477,7 +475,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_frequencies", .size = 167, - .content = "300000 364800 441600 518400 595200 672000 748800 825600 883200 960000 1036800 1094400 1171200 1248000 1324800 1401600 1478400 1555200 1670400 1747200 1824000 1900800 \n", + .content = + "300000 364800 441600 518400 595200 672000 748800 825600 883200 960000 1036800 1094400 1171200 1248000 1324800 1401600 1478400 1555200 1670400 1747200 1824000 1900800 \n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_governors", @@ -507,29 +506,28 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 271, - .content = - "300000 622778\n" - "364800 7579\n" - "441600 7761\n" - "518400 6959\n" - "595200 1061\n" - "672000 1038\n" - "748800 1601\n" - "825600 1238\n" - "883200 476\n" - "960000 742\n" - "1036800 482\n" - "1094400 1064\n" - "1171200 1026\n" - "1248000 1072\n" - "1324800 485\n" - "1401600 826\n" - "1478400 410\n" - "1555200 1405\n" - "1670400 997\n" - "1747200 1330\n" - "1824000 816\n" - "1900800 34439\n", + .content = "300000 622778\n" + "364800 7579\n" + "441600 7761\n" + "518400 6959\n" + "595200 1061\n" + "672000 1038\n" + "748800 1601\n" + "825600 1238\n" + "883200 476\n" + "960000 742\n" + "1036800 482\n" + "1094400 1064\n" + "1171200 1026\n" + "1248000 1072\n" + "1324800 485\n" + "1401600 826\n" + "1478400 410\n" + "1555200 1405\n" + "1670400 997\n" + "1747200 1330\n" + "1824000 816\n" + "1900800 34439\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -744,7 +742,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_frequencies", .size = 167, - .content = "300000 364800 441600 518400 595200 672000 748800 825600 883200 960000 1036800 1094400 1171200 1248000 1324800 1401600 1478400 1555200 1670400 1747200 1824000 1900800 \n", + .content = + "300000 364800 441600 518400 595200 672000 748800 825600 883200 960000 1036800 1094400 1171200 1248000 1324800 1401600 1478400 1555200 1670400 1747200 1824000 1900800 \n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_governors", @@ -774,29 +773,28 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 271, - .content = - "300000 622780\n" - "364800 7579\n" - "441600 7761\n" - "518400 6959\n" - "595200 1061\n" - "672000 1038\n" - "748800 1601\n" - "825600 1238\n" - "883200 476\n" - "960000 742\n" - "1036800 482\n" - "1094400 1064\n" - "1171200 1026\n" - "1248000 1072\n" - "1324800 485\n" - "1401600 826\n" - "1478400 410\n" - "1555200 1405\n" - "1670400 997\n" - "1747200 1330\n" - "1824000 816\n" - "1900800 34716\n", + .content = "300000 622780\n" + "364800 7579\n" + "441600 7761\n" + "518400 6959\n" + "595200 1061\n" + "672000 1038\n" + "748800 1601\n" + "825600 1238\n" + "883200 476\n" + "960000 742\n" + "1036800 482\n" + "1094400 1064\n" + "1171200 1026\n" + "1248000 1072\n" + "1324800 485\n" + "1401600 826\n" + "1478400 410\n" + "1555200 1405\n" + "1670400 997\n" + "1747200 1330\n" + "1824000 816\n" + "1900800 34716\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -1011,7 +1009,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_frequencies", .size = 167, - .content = "300000 364800 441600 518400 595200 672000 748800 825600 883200 960000 1036800 1094400 1171200 1248000 1324800 1401600 1478400 1555200 1670400 1747200 1824000 1900800 \n", + .content = + "300000 364800 441600 518400 595200 672000 748800 825600 883200 960000 1036800 1094400 1171200 1248000 1324800 1401600 1478400 1555200 1670400 1747200 1824000 1900800 \n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_governors", @@ -1041,29 +1040,28 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 271, - .content = - "300000 622782\n" - "364800 7579\n" - "441600 7761\n" - "518400 6959\n" - "595200 1061\n" - "672000 1038\n" - "748800 1601\n" - "825600 1238\n" - "883200 476\n" - "960000 742\n" - "1036800 482\n" - "1094400 1064\n" - "1171200 1026\n" - "1248000 1072\n" - "1324800 485\n" - "1401600 826\n" - "1478400 410\n" - "1555200 1405\n" - "1670400 997\n" - "1747200 1330\n" - "1824000 816\n" - "1900800 35016\n", + .content = "300000 622782\n" + "364800 7579\n" + "441600 7761\n" + "518400 6959\n" + "595200 1061\n" + "672000 1038\n" + "748800 1601\n" + "825600 1238\n" + "883200 476\n" + "960000 742\n" + "1036800 482\n" + "1094400 1064\n" + "1171200 1026\n" + "1248000 1072\n" + "1324800 485\n" + "1401600 826\n" + "1478400 410\n" + "1555200 1405\n" + "1670400 997\n" + "1747200 1330\n" + "1824000 816\n" + "1900800 35016\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -1278,7 +1276,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_available_frequencies", .size = 239, - .content = "300000 345600 422400 499200 576000 652800 729600 806400 902400 979200 1056000 1132800 1190400 1267200 1344000 1420800 1497600 1574400 1651200 1728000 1804800 1881600 1958400 2035200 2112000 2208000 2265600 2323200 2342400 2361600 2457600 \n", + .content = + "300000 345600 422400 499200 576000 652800 729600 806400 902400 979200 1056000 1132800 1190400 1267200 1344000 1420800 1497600 1574400 1651200 1728000 1804800 1881600 1958400 2035200 2112000 2208000 2265600 2323200 2342400 2361600 2457600 \n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_available_governors", @@ -1313,38 +1312,37 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/time_in_state", .size = 372, - .content = - "300000 661160\n" - "345600 1638\n" - "422400 1424\n" - "499200 1728\n" - "576000 1435\n" - "652800 1733\n" - "729600 752\n" - "806400 1022\n" - "902400 799\n" - "979200 538\n" - "1056000 706\n" - "1132800 1112\n" - "1190400 465\n" - "1267200 384\n" - "1344000 391\n" - "1420800 570\n" - "1497600 290\n" - "1574400 263\n" - "1651200 422\n" - "1728000 671\n" - "1804800 337\n" - "1881600 229\n" - "1958400 225\n" - "2035200 239\n" - "2112000 357\n" - "2208000 299\n" - "2265600 162\n" - "2323200 141\n" - "2342400 72\n" - "2361600 68\n" - "2457600 16817\n", + .content = "300000 661160\n" + "345600 1638\n" + "422400 1424\n" + "499200 1728\n" + "576000 1435\n" + "652800 1733\n" + "729600 752\n" + "806400 1022\n" + "902400 799\n" + "979200 538\n" + "1056000 706\n" + "1132800 1112\n" + "1190400 465\n" + "1267200 384\n" + "1344000 391\n" + "1420800 570\n" + "1497600 290\n" + "1574400 263\n" + "1651200 422\n" + "1728000 671\n" + "1804800 337\n" + "1881600 229\n" + "1958400 225\n" + "2035200 239\n" + "2112000 357\n" + "2208000 299\n" + "2265600 162\n" + "2323200 141\n" + "2342400 72\n" + "2361600 68\n" + "2457600 16817\n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/total_trans", @@ -1559,7 +1557,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_available_frequencies", .size = 239, - .content = "300000 345600 422400 499200 576000 652800 729600 806400 902400 979200 1056000 1132800 1190400 1267200 1344000 1420800 1497600 1574400 1651200 1728000 1804800 1881600 1958400 2035200 2112000 2208000 2265600 2323200 2342400 2361600 2457600 \n", + .content = + "300000 345600 422400 499200 576000 652800 729600 806400 902400 979200 1056000 1132800 1190400 1267200 1344000 1420800 1497600 1574400 1651200 1728000 1804800 1881600 1958400 2035200 2112000 2208000 2265600 2323200 2342400 2361600 2457600 \n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_available_governors", @@ -1594,38 +1593,37 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/time_in_state", .size = 372, - .content = - "300000 661459\n" - "345600 1638\n" - "422400 1424\n" - "499200 1728\n" - "576000 1435\n" - "652800 1733\n" - "729600 752\n" - "806400 1022\n" - "902400 799\n" - "979200 538\n" - "1056000 706\n" - "1132800 1112\n" - "1190400 465\n" - "1267200 384\n" - "1344000 391\n" - "1420800 570\n" - "1497600 290\n" - "1574400 263\n" - "1651200 422\n" - "1728000 671\n" - "1804800 337\n" - "1881600 229\n" - "1958400 225\n" - "2035200 239\n" - "2112000 357\n" - "2208000 299\n" - "2265600 162\n" - "2323200 141\n" - "2342400 72\n" - "2361600 68\n" - "2457600 16817\n", + .content = "300000 661459\n" + "345600 1638\n" + "422400 1424\n" + "499200 1728\n" + "576000 1435\n" + "652800 1733\n" + "729600 752\n" + "806400 1022\n" + "902400 799\n" + "979200 538\n" + "1056000 706\n" + "1132800 1112\n" + "1190400 465\n" + "1267200 384\n" + "1344000 391\n" + "1420800 570\n" + "1497600 290\n" + "1574400 263\n" + "1651200 422\n" + "1728000 671\n" + "1804800 337\n" + "1881600 229\n" + "1958400 225\n" + "2035200 239\n" + "2112000 357\n" + "2208000 299\n" + "2265600 162\n" + "2323200 141\n" + "2342400 72\n" + "2361600 68\n" + "2457600 16817\n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/total_trans", @@ -1840,7 +1838,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_available_frequencies", .size = 239, - .content = "300000 345600 422400 499200 576000 652800 729600 806400 902400 979200 1056000 1132800 1190400 1267200 1344000 1420800 1497600 1574400 1651200 1728000 1804800 1881600 1958400 2035200 2112000 2208000 2265600 2323200 2342400 2361600 2457600 \n", + .content = + "300000 345600 422400 499200 576000 652800 729600 806400 902400 979200 1056000 1132800 1190400 1267200 1344000 1420800 1497600 1574400 1651200 1728000 1804800 1881600 1958400 2035200 2112000 2208000 2265600 2323200 2342400 2361600 2457600 \n", }, { .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_available_governors", @@ -1875,38 +1874,37 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/time_in_state", .size = 372, - .content = - "300000 661746\n" - "345600 1638\n" - "422400 1427\n" - "499200 1731\n" - "576000 1435\n" - "652800 1733\n" - "729600 752\n" - "806400 1022\n" - "902400 799\n" - "979200 538\n" - "1056000 706\n" - "1132800 1112\n" - "1190400 465\n" - "1267200 384\n" - "1344000 391\n" - "1420800 570\n" - "1497600 290\n" - "1574400 263\n" - "1651200 422\n" - "1728000 671\n" - "1804800 337\n" - "1881600 229\n" - "1958400 225\n" - "2035200 239\n" - "2112000 357\n" - "2208000 299\n" - "2265600 162\n" - "2323200 141\n" - "2342400 72\n" - "2361600 68\n" - "2457600 16817\n", + .content = "300000 661746\n" + "345600 1638\n" + "422400 1427\n" + "499200 1731\n" + "576000 1435\n" + "652800 1733\n" + "729600 752\n" + "806400 1022\n" + "902400 799\n" + "979200 538\n" + "1056000 706\n" + "1132800 1112\n" + "1190400 465\n" + "1267200 384\n" + "1344000 391\n" + "1420800 570\n" + "1497600 290\n" + "1574400 263\n" + "1651200 422\n" + "1728000 671\n" + "1804800 337\n" + "1881600 229\n" + "1958400 225\n" + "2035200 239\n" + "2112000 357\n" + "2208000 299\n" + "2265600 162\n" + "2323200 141\n" + "2342400 72\n" + "2361600 68\n" + "2457600 16817\n", }, { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/total_trans", @@ -2121,7 +2119,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_available_frequencies", .size = 239, - .content = "300000 345600 422400 499200 576000 652800 729600 806400 902400 979200 1056000 1132800 1190400 1267200 1344000 1420800 1497600 1574400 1651200 1728000 1804800 1881600 1958400 2035200 2112000 2208000 2265600 2323200 2342400 2361600 2457600 \n", + .content = + "300000 345600 422400 499200 576000 652800 729600 806400 902400 979200 1056000 1132800 1190400 1267200 1344000 1420800 1497600 1574400 1651200 1728000 1804800 1881600 1958400 2035200 2112000 2208000 2265600 2323200 2342400 2361600 2457600 \n", }, { .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_available_governors", @@ -2156,38 +2155,37 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/time_in_state", .size = 372, - .content = - "300000 662030\n" - "345600 1638\n" - "422400 1427\n" - "499200 1731\n" - "576000 1437\n" - "652800 1735\n" - "729600 752\n" - "806400 1022\n" - "902400 799\n" - "979200 538\n" - "1056000 706\n" - "1132800 1112\n" - "1190400 465\n" - "1267200 384\n" - "1344000 391\n" - "1420800 570\n" - "1497600 290\n" - "1574400 263\n" - "1651200 422\n" - "1728000 671\n" - "1804800 337\n" - "1881600 229\n" - "1958400 225\n" - "2035200 239\n" - "2112000 357\n" - "2208000 299\n" - "2265600 162\n" - "2323200 141\n" - "2342400 72\n" - "2361600 68\n" - "2457600 16817\n", + .content = "300000 662030\n" + "345600 1638\n" + "422400 1427\n" + "499200 1731\n" + "576000 1437\n" + "652800 1735\n" + "729600 752\n" + "806400 1022\n" + "902400 799\n" + "979200 538\n" + "1056000 706\n" + "1132800 1112\n" + "1190400 465\n" + "1267200 384\n" + "1344000 391\n" + "1420800 570\n" + "1497600 290\n" + "1574400 263\n" + "1651200 422\n" + "1728000 671\n" + "1804800 337\n" + "1881600 229\n" + "1958400 225\n" + "2035200 239\n" + "2112000 357\n" + "2208000 299\n" + "2265600 162\n" + "2323200 141\n" + "2342400 72\n" + "2361600 68\n" + "2457600 16817\n", }, { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/total_trans", @@ -2369,7 +2367,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 10, .content = "WriteBack\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -4185,6 +4183,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wifi.interface", .value = "wlan0", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/pixel-c.cc b/test/mock/pixel-c.cc index 93fce0d1..fbff963f 100644 --- a/test/mock/pixel-c.cc +++ b/test/mock/pixel-c.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(4, cpuinfo_get_processors_count()); @@ -208,8 +207,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Nvidia Tegra T210", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Nvidia Tegra T210", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -251,59 +252,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -428,8 +429,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -480,8 +483,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -532,8 +537,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/pixel-c.h b/test/mock/pixel-c.h index 7c062e15..8c77bb07 100644 --- a/test/mock/pixel-c.h +++ b/test/mock/pixel-c.h @@ -2,39 +2,38 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 656, - .content = - "processor\t: 0\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x1\n" - "CPU part\t: 0xd07\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 1\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x1\n" - "CPU part\t: 0xd07\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 2\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x1\n" - "CPU part\t: 0xd07\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 3\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x1\n" - "CPU part\t: 0xd07\n" - "CPU revision\t: 1\n" - "\n", + .content = "processor\t: 0\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0xd07\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 1\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0xd07\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 2\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0xd07\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 3\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0xd07\n" + "CPU revision\t: 1\n" + "\n", }, { .path = "/sys/devices/system/cpu/kernel_max", @@ -69,28 +68,27 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpufreq/all_time_in_state", .size = 536, - .content = - "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\t\n" - "51000\t\t18\t\t18\t\t18\t\t18\t\t\n" - "102000\t\t13\t\t13\t\t13\t\t13\t\t\n" - "204000\t\t309\t\t309\t\t309\t\t309\t\t\n" - "306000\t\t31\t\t31\t\t31\t\t31\t\t\n" - "408000\t\t169\t\t169\t\t169\t\t169\t\t\n" - "510000\t\t106\t\t106\t\t106\t\t106\t\t\n" - "612000\t\t60\t\t60\t\t60\t\t60\t\t\n" - "714000\t\t23\t\t23\t\t23\t\t23\t\t\n" - "816000\t\t15\t\t15\t\t15\t\t15\t\t\n" - "918000\t\t19\t\t19\t\t19\t\t19\t\t\n" - "1020000\t\t7\t\t7\t\t7\t\t7\t\t\n" - "1122000\t\t3\t\t3\t\t3\t\t3\t\t\n" - "1224000\t\t5\t\t5\t\t5\t\t5\t\t\n" - "1326000\t\t6\t\t6\t\t6\t\t6\t\t\n" - "1428000\t\t0\t\t0\t\t0\t\t0\t\t\n" - "1530000\t\t71\t\t71\t\t71\t\t71\t\t\n" - "1632000\t\t13\t\t13\t\t13\t\t13\t\t\n" - "1734000\t\t17\t\t17\t\t17\t\t17\t\t\n" - "1836000\t\t26\t\t26\t\t26\t\t26\t\t\n" - "1912500\t\t932\t\t932\t\t932\t\t932\t\t\n", + .content = "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\t\n" + "51000\t\t18\t\t18\t\t18\t\t18\t\t\n" + "102000\t\t13\t\t13\t\t13\t\t13\t\t\n" + "204000\t\t309\t\t309\t\t309\t\t309\t\t\n" + "306000\t\t31\t\t31\t\t31\t\t31\t\t\n" + "408000\t\t169\t\t169\t\t169\t\t169\t\t\n" + "510000\t\t106\t\t106\t\t106\t\t106\t\t\n" + "612000\t\t60\t\t60\t\t60\t\t60\t\t\n" + "714000\t\t23\t\t23\t\t23\t\t23\t\t\n" + "816000\t\t15\t\t15\t\t15\t\t15\t\t\n" + "918000\t\t19\t\t19\t\t19\t\t19\t\t\n" + "1020000\t\t7\t\t7\t\t7\t\t7\t\t\n" + "1122000\t\t3\t\t3\t\t3\t\t3\t\t\n" + "1224000\t\t5\t\t5\t\t5\t\t5\t\t\n" + "1326000\t\t6\t\t6\t\t6\t\t6\t\t\n" + "1428000\t\t0\t\t0\t\t0\t\t0\t\t\n" + "1530000\t\t71\t\t71\t\t71\t\t71\t\t\n" + "1632000\t\t13\t\t13\t\t13\t\t13\t\t\n" + "1734000\t\t17\t\t17\t\t17\t\t17\t\t\n" + "1836000\t\t26\t\t26\t\t26\t\t26\t\t\n" + "1912500\t\t932\t\t932\t\t932\t\t932\t\t\n", }, { .path = "/sys/devices/system/cpu/cpufreq/current_in_state", @@ -139,7 +137,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies", .size = 150, - .content = "51000 102000 204000 306000 408000 510000 612000 714000 816000 918000 1020000 1122000 1224000 1326000 1428000 1530000 1632000 1734000 1836000 1912500 \n", + .content = + "51000 102000 204000 306000 408000 510000 612000 714000 816000 918000 1020000 1122000 1224000 1326000 1428000 1530000 1632000 1734000 1836000 1912500 \n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors", @@ -169,27 +168,26 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 209, - .content = - "51000 18\n" - "102000 13\n" - "204000 309\n" - "306000 31\n" - "408000 169\n" - "510000 106\n" - "612000 60\n" - "714000 23\n" - "816000 15\n" - "918000 19\n" - "1020000 7\n" - "1122000 3\n" - "1224000 5\n" - "1326000 6\n" - "1428000 0\n" - "1530000 71\n" - "1632000 13\n" - "1734000 17\n" - "1836000 26\n" - "1912500 1020\n", + .content = "51000 18\n" + "102000 13\n" + "204000 309\n" + "306000 31\n" + "408000 169\n" + "510000 106\n" + "612000 60\n" + "714000 23\n" + "816000 15\n" + "918000 19\n" + "1020000 7\n" + "1122000 3\n" + "1224000 5\n" + "1326000 6\n" + "1428000 0\n" + "1530000 71\n" + "1632000 13\n" + "1734000 17\n" + "1836000 26\n" + "1912500 1020\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -399,7 +397,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_frequencies", .size = 150, - .content = "51000 102000 204000 306000 408000 510000 612000 714000 816000 918000 1020000 1122000 1224000 1326000 1428000 1530000 1632000 1734000 1836000 1912500 \n", + .content = + "51000 102000 204000 306000 408000 510000 612000 714000 816000 918000 1020000 1122000 1224000 1326000 1428000 1530000 1632000 1734000 1836000 1912500 \n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_governors", @@ -429,27 +428,26 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 209, - .content = - "51000 18\n" - "102000 13\n" - "204000 309\n" - "306000 31\n" - "408000 169\n" - "510000 106\n" - "612000 60\n" - "714000 23\n" - "816000 15\n" - "918000 19\n" - "1020000 7\n" - "1122000 3\n" - "1224000 5\n" - "1326000 6\n" - "1428000 0\n" - "1530000 71\n" - "1632000 13\n" - "1734000 17\n" - "1836000 26\n" - "1912500 1304\n", + .content = "51000 18\n" + "102000 13\n" + "204000 309\n" + "306000 31\n" + "408000 169\n" + "510000 106\n" + "612000 60\n" + "714000 23\n" + "816000 15\n" + "918000 19\n" + "1020000 7\n" + "1122000 3\n" + "1224000 5\n" + "1326000 6\n" + "1428000 0\n" + "1530000 71\n" + "1632000 13\n" + "1734000 17\n" + "1836000 26\n" + "1912500 1304\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -659,7 +657,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_frequencies", .size = 150, - .content = "51000 102000 204000 306000 408000 510000 612000 714000 816000 918000 1020000 1122000 1224000 1326000 1428000 1530000 1632000 1734000 1836000 1912500 \n", + .content = + "51000 102000 204000 306000 408000 510000 612000 714000 816000 918000 1020000 1122000 1224000 1326000 1428000 1530000 1632000 1734000 1836000 1912500 \n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_governors", @@ -689,27 +688,26 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 209, - .content = - "51000 18\n" - "102000 13\n" - "204000 309\n" - "306000 31\n" - "408000 169\n" - "510000 106\n" - "612000 60\n" - "714000 23\n" - "816000 15\n" - "918000 19\n" - "1020000 7\n" - "1122000 3\n" - "1224000 5\n" - "1326000 6\n" - "1428000 0\n" - "1530000 71\n" - "1632000 13\n" - "1734000 17\n" - "1836000 26\n" - "1912500 1609\n", + .content = "51000 18\n" + "102000 13\n" + "204000 309\n" + "306000 31\n" + "408000 169\n" + "510000 106\n" + "612000 60\n" + "714000 23\n" + "816000 15\n" + "918000 19\n" + "1020000 7\n" + "1122000 3\n" + "1224000 5\n" + "1326000 6\n" + "1428000 0\n" + "1530000 71\n" + "1632000 13\n" + "1734000 17\n" + "1836000 26\n" + "1912500 1609\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -919,7 +917,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_frequencies", .size = 150, - .content = "51000 102000 204000 306000 408000 510000 612000 714000 816000 918000 1020000 1122000 1224000 1326000 1428000 1530000 1632000 1734000 1836000 1912500 \n", + .content = + "51000 102000 204000 306000 408000 510000 612000 714000 816000 918000 1020000 1122000 1224000 1326000 1428000 1530000 1632000 1734000 1836000 1912500 \n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_governors", @@ -949,27 +948,26 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 210, - .content = - "51000 18\n" - "102000 13\n" - "204000 315\n" - "306000 31\n" - "408000 170\n" - "510000 106\n" - "612000 60\n" - "714000 23\n" - "816000 23\n" - "918000 19\n" - "1020000 11\n" - "1122000 3\n" - "1224000 5\n" - "1326000 6\n" - "1428000 0\n" - "1530000 76\n" - "1632000 13\n" - "1734000 17\n" - "1836000 26\n" - "1912500 1864\n", + .content = "51000 18\n" + "102000 13\n" + "204000 315\n" + "306000 31\n" + "408000 170\n" + "510000 106\n" + "612000 60\n" + "714000 23\n" + "816000 23\n" + "918000 19\n" + "1020000 11\n" + "1122000 3\n" + "1224000 5\n" + "1326000 6\n" + "1428000 0\n" + "1530000 76\n" + "1632000 13\n" + "1734000 17\n" + "1836000 26\n" + "1912500 1864\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -1151,7 +1149,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 10, .content = "WriteBack\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ @@ -2100,6 +2098,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wifi.interface", .value = "wlan0", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/pixel-xl.cc b/test/mock/pixel-xl.cc index 2c8e75dd..478932c9 100644 --- a/test/mock/pixel-xl.cc +++ b/test/mock/pixel-xl.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(4, cpuinfo_get_processors_count()); @@ -290,8 +289,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Qualcomm MSM8996PRO-AB", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Qualcomm MSM8996PRO-AB", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -333,59 +334,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -510,8 +511,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -562,8 +565,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -621,8 +626,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/pixel-xl.h b/test/mock/pixel-xl.h index ed006db0..eb23ccdf 100644 --- a/test/mock/pixel-xl.h +++ b/test/mock/pixel-xl.h @@ -2,54 +2,53 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 1025, - .content = - "Processor\t: AArch64 Processor rev 1 (aarch64)\n" - "processor\t: 0\n" - "min_vddcx\t: 400000\n" - "min_vddmx\t: 490000\n" - "BogoMIPS\t: 38.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x2\n" - "CPU part\t: 0x201\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 1\n" - "min_vddcx\t: 400000\n" - "min_vddmx\t: 490000\n" - "BogoMIPS\t: 38.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x2\n" - "CPU part\t: 0x201\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 2\n" - "min_vddcx\t: 400000\n" - "min_vddmx\t: 490000\n" - "BogoMIPS\t: 38.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x2\n" - "CPU part\t: 0x205\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 3\n" - "min_vddcx\t: 400000\n" - "min_vddmx\t: 490000\n" - "BogoMIPS\t: 38.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x2\n" - "CPU part\t: 0x205\n" - "CPU revision\t: 1\n" - "\n" - "CPU param\t: 267 434 434 633 958 308 436 436 636 1078 \n" - "Hardware\t: Qualcomm Technologies, Inc MSM8996pro\n", + .content = "Processor\t: AArch64 Processor rev 1 (aarch64)\n" + "processor\t: 0\n" + "min_vddcx\t: 400000\n" + "min_vddmx\t: 490000\n" + "BogoMIPS\t: 38.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x2\n" + "CPU part\t: 0x201\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 1\n" + "min_vddcx\t: 400000\n" + "min_vddmx\t: 490000\n" + "BogoMIPS\t: 38.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x2\n" + "CPU part\t: 0x201\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 2\n" + "min_vddcx\t: 400000\n" + "min_vddmx\t: 490000\n" + "BogoMIPS\t: 38.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x2\n" + "CPU part\t: 0x205\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 3\n" + "min_vddcx\t: 400000\n" + "min_vddmx\t: 490000\n" + "BogoMIPS\t: 38.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x2\n" + "CPU part\t: 0x205\n" + "CPU revision\t: 1\n" + "\n" + "CPU param\t: 267 434 434 633 958 308 436 436 636 1078 \n" + "Hardware\t: Qualcomm Technologies, Inc MSM8996pro\n", }, { .path = "/system/build.prop", @@ -291,7 +290,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies", .size = 135, - .content = "307200 384000 460800 537600 614400 691200 768000 844800 902400 979200 1056000 1132800 1209600 1286400 1363200 1440000 1516800 1593600 \n", + .content = + "307200 384000 460800 537600 614400 691200 768000 844800 902400 979200 1056000 1132800 1209600 1286400 1363200 1440000 1516800 1593600 \n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors", @@ -321,25 +321,24 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 199, - .content = - "307200 253\n" - "384000 179\n" - "460800 168\n" - "537600 144\n" - "614400 156\n" - "691200 123\n" - "768000 121\n" - "844800 60\n" - "902400 67\n" - "979200 111\n" - "1056000 60\n" - "1132800 196\n" - "1209600 59\n" - "1286400 68\n" - "1363200 70\n" - "1440000 65\n" - "1516800 45\n" - "1593600 1033\n", + .content = "307200 253\n" + "384000 179\n" + "460800 168\n" + "537600 144\n" + "614400 156\n" + "691200 123\n" + "768000 121\n" + "844800 60\n" + "902400 67\n" + "979200 111\n" + "1056000 60\n" + "1132800 196\n" + "1209600 59\n" + "1286400 68\n" + "1363200 70\n" + "1440000 65\n" + "1516800 45\n" + "1593600 1033\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -404,7 +403,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_frequencies", .size = 135, - .content = "307200 384000 460800 537600 614400 691200 768000 844800 902400 979200 1056000 1132800 1209600 1286400 1363200 1440000 1516800 1593600 \n", + .content = + "307200 384000 460800 537600 614400 691200 768000 844800 902400 979200 1056000 1132800 1209600 1286400 1363200 1440000 1516800 1593600 \n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_governors", @@ -434,25 +434,24 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 199, - .content = - "307200 363\n" - "384000 268\n" - "460800 255\n" - "537600 169\n" - "614400 192\n" - "691200 129\n" - "768000 126\n" - "844800 65\n" - "902400 67\n" - "979200 111\n" - "1056000 60\n" - "1132800 196\n" - "1209600 59\n" - "1286400 68\n" - "1363200 70\n" - "1440000 65\n" - "1516800 45\n" - "1593600 1033\n", + .content = "307200 363\n" + "384000 268\n" + "460800 255\n" + "537600 169\n" + "614400 192\n" + "691200 129\n" + "768000 126\n" + "844800 65\n" + "902400 67\n" + "979200 111\n" + "1056000 60\n" + "1132800 196\n" + "1209600 59\n" + "1286400 68\n" + "1363200 70\n" + "1440000 65\n" + "1516800 45\n" + "1593600 1033\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -517,7 +516,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_frequencies", .size = 191, - .content = "307200 384000 460800 537600 614400 691200 748800 825600 902400 979200 1056000 1132800 1209600 1286400 1363200 1440000 1516800 1593600 1670400 1747200 1824000 1900800 1977600 2054400 2150400 \n", + .content = + "307200 384000 460800 537600 614400 691200 748800 825600 902400 979200 1056000 1132800 1209600 1286400 1363200 1440000 1516800 1593600 1670400 1747200 1824000 1900800 1977600 2054400 2150400 \n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_governors", @@ -552,32 +552,31 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 273, - .content = - "307200 803\n" - "384000 39\n" - "460800 172\n" - "537600 209\n" - "614400 104\n" - "691200 154\n" - "748800 62\n" - "825600 66\n" - "902400 56\n" - "979200 68\n" - "1056000 59\n" - "1132800 168\n" - "1209600 77\n" - "1286400 54\n" - "1363200 55\n" - "1440000 50\n" - "1516800 64\n" - "1593600 48\n" - "1670400 41\n" - "1747200 57\n" - "1824000 46\n" - "1900800 36\n" - "1977600 21\n" - "2054400 55\n" - "2150400 1146\n", + .content = "307200 803\n" + "384000 39\n" + "460800 172\n" + "537600 209\n" + "614400 104\n" + "691200 154\n" + "748800 62\n" + "825600 66\n" + "902400 56\n" + "979200 68\n" + "1056000 59\n" + "1132800 168\n" + "1209600 77\n" + "1286400 54\n" + "1363200 55\n" + "1440000 50\n" + "1516800 64\n" + "1593600 48\n" + "1670400 41\n" + "1747200 57\n" + "1824000 46\n" + "1900800 36\n" + "1977600 21\n" + "2054400 55\n" + "2150400 1146\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -642,7 +641,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_frequencies", .size = 191, - .content = "307200 384000 460800 537600 614400 691200 748800 825600 902400 979200 1056000 1132800 1209600 1286400 1363200 1440000 1516800 1593600 1670400 1747200 1824000 1900800 1977600 2054400 2150400 \n", + .content = + "307200 384000 460800 537600 614400 691200 748800 825600 902400 979200 1056000 1132800 1209600 1286400 1363200 1440000 1516800 1593600 1670400 1747200 1824000 1900800 1977600 2054400 2150400 \n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_governors", @@ -677,32 +677,31 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 273, - .content = - "307200 806\n" - "384000 40\n" - "460800 174\n" - "537600 224\n" - "614400 110\n" - "691200 164\n" - "748800 78\n" - "825600 68\n" - "902400 61\n" - "979200 78\n" - "1056000 64\n" - "1132800 178\n" - "1209600 82\n" - "1286400 65\n" - "1363200 60\n" - "1440000 61\n" - "1516800 74\n" - "1593600 49\n" - "1670400 47\n" - "1747200 57\n" - "1824000 56\n" - "1900800 41\n" - "1977600 26\n" - "2054400 70\n" - "2150400 1290\n", + .content = "307200 806\n" + "384000 40\n" + "460800 174\n" + "537600 224\n" + "614400 110\n" + "691200 164\n" + "748800 78\n" + "825600 68\n" + "902400 61\n" + "979200 78\n" + "1056000 64\n" + "1132800 178\n" + "1209600 82\n" + "1286400 65\n" + "1363200 60\n" + "1440000 61\n" + "1516800 74\n" + "1593600 49\n" + "1670400 47\n" + "1747200 57\n" + "1824000 56\n" + "1900800 41\n" + "1977600 26\n" + "2054400 70\n" + "2150400 1290\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -739,7 +738,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "8\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ @@ -2116,6 +2115,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.driver.status", .value = "ok", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/pixel.cc b/test/mock/pixel.cc index 969e978d..4eaa849c 100644 --- a/test/mock/pixel.cc +++ b/test/mock/pixel.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(4, cpuinfo_get_processors_count()); @@ -290,8 +289,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Qualcomm MSM8996PRO-AB", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Qualcomm MSM8996PRO-AB", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -333,59 +334,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -510,8 +511,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -562,8 +565,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -621,8 +626,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/pixel.h b/test/mock/pixel.h index 19cf1c7d..d731cb8d 100644 --- a/test/mock/pixel.h +++ b/test/mock/pixel.h @@ -2,54 +2,53 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 1025, - .content = - "Processor\t: AArch64 Processor rev 1 (aarch64)\n" - "processor\t: 0\n" - "min_vddcx\t: 400000\n" - "min_vddmx\t: 490000\n" - "BogoMIPS\t: 38.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x2\n" - "CPU part\t: 0x201\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 1\n" - "min_vddcx\t: 400000\n" - "min_vddmx\t: 490000\n" - "BogoMIPS\t: 38.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x2\n" - "CPU part\t: 0x201\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 2\n" - "min_vddcx\t: 400000\n" - "min_vddmx\t: 490000\n" - "BogoMIPS\t: 38.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x2\n" - "CPU part\t: 0x205\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 3\n" - "min_vddcx\t: 400000\n" - "min_vddmx\t: 490000\n" - "BogoMIPS\t: 38.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x2\n" - "CPU part\t: 0x205\n" - "CPU revision\t: 1\n" - "\n" - "CPU param\t: 321 487 487 679 976 319 464 464 697 1167 \n" - "Hardware\t: Qualcomm Technologies, Inc MSM8996pro\n", + .content = "Processor\t: AArch64 Processor rev 1 (aarch64)\n" + "processor\t: 0\n" + "min_vddcx\t: 400000\n" + "min_vddmx\t: 490000\n" + "BogoMIPS\t: 38.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x2\n" + "CPU part\t: 0x201\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 1\n" + "min_vddcx\t: 400000\n" + "min_vddmx\t: 490000\n" + "BogoMIPS\t: 38.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x2\n" + "CPU part\t: 0x201\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 2\n" + "min_vddcx\t: 400000\n" + "min_vddmx\t: 490000\n" + "BogoMIPS\t: 38.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x2\n" + "CPU part\t: 0x205\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 3\n" + "min_vddcx\t: 400000\n" + "min_vddmx\t: 490000\n" + "BogoMIPS\t: 38.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x2\n" + "CPU part\t: 0x205\n" + "CPU revision\t: 1\n" + "\n" + "CPU param\t: 321 487 487 679 976 319 464 464 697 1167 \n" + "Hardware\t: Qualcomm Technologies, Inc MSM8996pro\n", }, { .path = "/system/build.prop", @@ -291,7 +290,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies", .size = 135, - .content = "307200 384000 460800 537600 614400 691200 768000 844800 902400 979200 1056000 1132800 1209600 1286400 1363200 1440000 1516800 1593600 \n", + .content = + "307200 384000 460800 537600 614400 691200 768000 844800 902400 979200 1056000 1132800 1209600 1286400 1363200 1440000 1516800 1593600 \n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors", @@ -321,25 +321,24 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 192, - .content = - "307200 235\n" - "384000 31\n" - "460800 92\n" - "537600 123\n" - "614400 94\n" - "691200 50\n" - "768000 55\n" - "844800 51\n" - "902400 49\n" - "979200 95\n" - "1056000 47\n" - "1132800 55\n" - "1209600 46\n" - "1286400 71\n" - "1363200 30\n" - "1440000 54\n" - "1516800 76\n" - "1593600 1346\n", + .content = "307200 235\n" + "384000 31\n" + "460800 92\n" + "537600 123\n" + "614400 94\n" + "691200 50\n" + "768000 55\n" + "844800 51\n" + "902400 49\n" + "979200 95\n" + "1056000 47\n" + "1132800 55\n" + "1209600 46\n" + "1286400 71\n" + "1363200 30\n" + "1440000 54\n" + "1516800 76\n" + "1593600 1346\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -404,7 +403,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_frequencies", .size = 135, - .content = "307200 384000 460800 537600 614400 691200 768000 844800 902400 979200 1056000 1132800 1209600 1286400 1363200 1440000 1516800 1593600 \n", + .content = + "307200 384000 460800 537600 614400 691200 768000 844800 902400 979200 1056000 1132800 1209600 1286400 1363200 1440000 1516800 1593600 \n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_governors", @@ -434,25 +434,24 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 192, - .content = - "307200 235\n" - "384000 31\n" - "460800 92\n" - "537600 123\n" - "614400 94\n" - "691200 50\n" - "768000 55\n" - "844800 51\n" - "902400 49\n" - "979200 95\n" - "1056000 47\n" - "1132800 55\n" - "1209600 46\n" - "1286400 71\n" - "1363200 30\n" - "1440000 54\n" - "1516800 76\n" - "1593600 1660\n", + .content = "307200 235\n" + "384000 31\n" + "460800 92\n" + "537600 123\n" + "614400 94\n" + "691200 50\n" + "768000 55\n" + "844800 51\n" + "902400 49\n" + "979200 95\n" + "1056000 47\n" + "1132800 55\n" + "1209600 46\n" + "1286400 71\n" + "1363200 30\n" + "1440000 54\n" + "1516800 76\n" + "1593600 1660\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -517,7 +516,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_frequencies", .size = 191, - .content = "307200 384000 460800 537600 614400 691200 748800 825600 902400 979200 1056000 1132800 1209600 1286400 1363200 1440000 1516800 1593600 1670400 1747200 1824000 1900800 1977600 2054400 2150400 \n", + .content = + "307200 384000 460800 537600 614400 691200 748800 825600 902400 979200 1056000 1132800 1209600 1286400 1363200 1440000 1516800 1593600 1670400 1747200 1824000 1900800 1977600 2054400 2150400 \n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_governors", @@ -552,32 +552,31 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 270, - .content = - "307200 28\n" - "384000 39\n" - "460800 106\n" - "537600 125\n" - "614400 110\n" - "691200 90\n" - "748800 66\n" - "825600 58\n" - "902400 28\n" - "979200 56\n" - "1056000 27\n" - "1132800 67\n" - "1209600 21\n" - "1286400 47\n" - "1363200 30\n" - "1440000 23\n" - "1516800 62\n" - "1593600 46\n" - "1670400 36\n" - "1747200 34\n" - "1824000 35\n" - "1900800 86\n" - "1977600 57\n" - "2054400 56\n" - "2150400 1883\n", + .content = "307200 28\n" + "384000 39\n" + "460800 106\n" + "537600 125\n" + "614400 110\n" + "691200 90\n" + "748800 66\n" + "825600 58\n" + "902400 28\n" + "979200 56\n" + "1056000 27\n" + "1132800 67\n" + "1209600 21\n" + "1286400 47\n" + "1363200 30\n" + "1440000 23\n" + "1516800 62\n" + "1593600 46\n" + "1670400 36\n" + "1747200 34\n" + "1824000 35\n" + "1900800 86\n" + "1977600 57\n" + "2054400 56\n" + "2150400 1883\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -642,7 +641,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_frequencies", .size = 191, - .content = "307200 384000 460800 537600 614400 691200 748800 825600 902400 979200 1056000 1132800 1209600 1286400 1363200 1440000 1516800 1593600 1670400 1747200 1824000 1900800 1977600 2054400 2150400 \n", + .content = + "307200 384000 460800 537600 614400 691200 748800 825600 902400 979200 1056000 1132800 1209600 1286400 1363200 1440000 1516800 1593600 1670400 1747200 1824000 1900800 1977600 2054400 2150400 \n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_governors", @@ -677,32 +677,31 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 271, - .content = - "307200 42\n" - "384000 64\n" - "460800 144\n" - "537600 135\n" - "614400 131\n" - "691200 101\n" - "748800 72\n" - "825600 64\n" - "902400 36\n" - "979200 86\n" - "1056000 37\n" - "1132800 72\n" - "1209600 26\n" - "1286400 57\n" - "1363200 30\n" - "1440000 24\n" - "1516800 68\n" - "1593600 46\n" - "1670400 41\n" - "1747200 34\n" - "1824000 35\n" - "1900800 86\n" - "1977600 63\n" - "2054400 71\n" - "2150400 1950\n", + .content = "307200 42\n" + "384000 64\n" + "460800 144\n" + "537600 135\n" + "614400 131\n" + "691200 101\n" + "748800 72\n" + "825600 64\n" + "902400 36\n" + "979200 86\n" + "1056000 37\n" + "1132800 72\n" + "1209600 26\n" + "1286400 57\n" + "1363200 30\n" + "1440000 24\n" + "1516800 68\n" + "1593600 46\n" + "1670400 41\n" + "1747200 34\n" + "1824000 35\n" + "1900800 86\n" + "1977600 63\n" + "2054400 71\n" + "2150400 1950\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -739,7 +738,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "8\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ @@ -2204,6 +2203,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.driver.status", .value = "ok", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/scaleway.cc b/test/mock/scaleway.cc index c794fcb0..b6dfa0d7 100644 --- a/test/mock/scaleway.cc +++ b/test/mock/scaleway.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(2, cpuinfo_processors_count); diff --git a/test/mock/scaleway.h b/test/mock/scaleway.h index 5472ec6f..575a268a 100644 --- a/test/mock/scaleway.h +++ b/test/mock/scaleway.h @@ -2,61 +2,60 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 1140, - .content = - "processor\t: 0\n" - "BogoMIPS\t: 200.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics\n" - "CPU implementer\t: 0x43\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x1\n" - "CPU part\t: 0x0a1\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 1\n" - "BogoMIPS\t: 200.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics\n" - "CPU implementer\t: 0x43\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x1\n" - "CPU part\t: 0x0a1\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 2\n" - "BogoMIPS\t: 200.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics\n" - "CPU implementer\t: 0x43\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x1\n" - "CPU part\t: 0x0a1\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 3\n" - "BogoMIPS\t: 200.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics\n" - "CPU implementer\t: 0x43\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x1\n" - "CPU part\t: 0x0a1\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 4\n" - "BogoMIPS\t: 200.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics\n" - "CPU implementer\t: 0x43\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x1\n" - "CPU part\t: 0x0a1\n" - "CPU revision\t: 1\n" - "\n" - "processor\t: 5\n" - "BogoMIPS\t: 200.00\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics\n" - "CPU implementer\t: 0x43\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x1\n" - "CPU part\t: 0x0a1\n" - "CPU revision\t: 1\n" - "\n", + .content = "processor\t: 0\n" + "BogoMIPS\t: 200.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics\n" + "CPU implementer\t: 0x43\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0x0a1\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 1\n" + "BogoMIPS\t: 200.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics\n" + "CPU implementer\t: 0x43\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0x0a1\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 2\n" + "BogoMIPS\t: 200.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics\n" + "CPU implementer\t: 0x43\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0x0a1\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 3\n" + "BogoMIPS\t: 200.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics\n" + "CPU implementer\t: 0x43\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0x0a1\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 4\n" + "BogoMIPS\t: 200.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics\n" + "CPU implementer\t: 0x43\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0x0a1\n" + "CPU revision\t: 1\n" + "\n" + "processor\t: 5\n" + "BogoMIPS\t: 200.00\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics\n" + "CPU implementer\t: 0x43\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0x0a1\n" + "CPU revision\t: 1\n" + "\n", }, { .path = "/sys/devices/system/cpu/kernel_max", @@ -193,5 +192,5 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "5\n", }, - { NULL }, + {NULL}, }; diff --git a/test/mock/xiaomi-mi-5c.cc b/test/mock/xiaomi-mi-5c.cc index 886508a6..5050cfb1 100644 --- a/test/mock/xiaomi-mi-5c.cc +++ b/test/mock/xiaomi-mi-5c.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(8, cpuinfo_get_processors_count()); @@ -294,8 +293,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Pinecone Surge S1", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Pinecone Surge S1", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -337,59 +338,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -514,8 +515,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -566,8 +569,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -618,8 +623,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/xiaomi-mi-5c.h b/test/mock/xiaomi-mi-5c.h index 2bc1db13..44bb8825 100644 --- a/test/mock/xiaomi-mi-5c.h +++ b/test/mock/xiaomi-mi-5c.h @@ -3,322 +3,319 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 1086, - .content = - "processor\t: 0\n" - "BogoMIPS\t: 52.16\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 1\n" - "BogoMIPS\t: 52.16\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 2\n" - "BogoMIPS\t: 52.16\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 3\n" - "BogoMIPS\t: 52.16\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 4\n" - "BogoMIPS\t: 52.16\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 5\n" - "BogoMIPS\t: 52.16\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n", + .content = "processor\t: 0\n" + "BogoMIPS\t: 52.16\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 1\n" + "BogoMIPS\t: 52.16\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 2\n" + "BogoMIPS\t: 52.16\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 3\n" + "BogoMIPS\t: 52.16\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 4\n" + "BogoMIPS\t: 52.16\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 5\n" + "BogoMIPS\t: 52.16\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n", }, #elif CPUINFO_ARCH_ARM { .path = "/proc/cpuinfo", .size = 1248, - .content = - "processor\t: 0\n" - "BogoMIPS\t: 52.16\n" - "Features\t: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt evtstrm\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 1\n" - "BogoMIPS\t: 52.16\n" - "Features\t: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt evtstrm\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 2\n" - "BogoMIPS\t: 52.16\n" - "Features\t: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt evtstrm\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 3\n" - "BogoMIPS\t: 52.16\n" - "Features\t: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt evtstrm\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 4\n" - "BogoMIPS\t: 52.16\n" - "Features\t: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt evtstrm\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 5\n" - "BogoMIPS\t: 52.16\n" - "Features\t: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt evtstrm\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n", + .content = "processor\t: 0\n" + "BogoMIPS\t: 52.16\n" + "Features\t: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt evtstrm\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 1\n" + "BogoMIPS\t: 52.16\n" + "Features\t: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt evtstrm\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 2\n" + "BogoMIPS\t: 52.16\n" + "Features\t: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt evtstrm\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 3\n" + "BogoMIPS\t: 52.16\n" + "Features\t: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt evtstrm\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 4\n" + "BogoMIPS\t: 52.16\n" + "Features\t: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt evtstrm\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 5\n" + "BogoMIPS\t: 52.16\n" + "Features\t: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt evtstrm\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n", }, #endif { .path = "/system/build.prop", .size = 5397, - .content = - "\n" - "# begin build properties\n" - "# autogenerated by buildinfo.sh\n" - "ro.build.id=N2G47J\n" - "ro.build.display.id=N2G47J\n" - "ro.build.version.incremental=V8.5.3.0.0.NCJCNED\n" - "ro.build.version.sdk=25\n" - "ro.build.version.preview_sdk=0\n" - "ro.build.version.codename=REL\n" - "ro.build.version.all_codenames=REL\n" - "ro.build.version.release=7.1.2\n" - "ro.build.version.security_patch=2017-05-01\n" - "ro.build.version.base_os=\n" - "ro.build.date=Thu Jun 15 10:24:29 CST 2017\n" - "ro.build.date.utc=1497493469\n" - "ro.build.type=user\n" - "ro.build.user=builder\n" - "ro.build.host=c3-miui-ota-bd09.bj\n" - "ro.build.tags=release-keys\n" - "ro.build.flavor=song-user\n" - "ro.product.model=MI 5C\n" - "ro.product.brand=Xiaomi\n" - "ro.product.name=meri\n" - "ro.product.device=song\n" - "ro.product.mod_device=meri_global\n" - "ro.product.board=\n" - "# ro.product.cpu.abi and ro.product.cpu.abi2 are obsolete,\n" - "# use ro.product.cpu.abilist instead.\n" - "ro.product.cpu.abi=arm64-v8a\n" - "ro.product.cpu.abilist=arm64-v8a,armeabi-v7a,armeabi\n" - "ro.product.cpu.abilist32=armeabi-v7a,armeabi\n" - "ro.product.cpu.abilist64=arm64-v8a\n" - "ro.product.locale=en-US\n" - "ro.wifi.channels=\n" - "ro.board.platform=song\n" - "# ro.build.product is obsolete; use ro.product.device\n" - "ro.build.product=song\n" - "# Do not try to parse description, fingerprint, or thumbprint\n" - "ro.build.description=song-user 7.1.2 N2G47J V8.5.3.0.0.NCJCNED release-keys\n" - "ro.build.fingerprint=Xiaomi/meri/meri:7.1.2/N2G47J/V8.5.3.0.0.NCJCNED:user/release-keys\n" - "ro.build.characteristics=nosdcard\n" - "# end build properties\n" - "#\n" - "# from device/pinecone/song/system.prop\n" - "#\n" - "# This overrides settings in the products/generic/system.prop file\n" - "#\n" - "# rild.libpath=/system/lib/libreference-ril.so\n" - "# rild.libargs=-d /dev/ttyS0\n" - "ro.sf.lcd_density=480\n" - "ro.opengles.version=196610\n" - "ro.telephony.default_network=9\n" - "ro.ril.modem.pb=0\n" - "\n" - "# disable strictmode\n" - "persist.sys.strictmode.disable=true\n" - "mali.hwc.flattener.interval=900\n" - "mali.hwc.flattener.enable=1\n" - "mali.hwc.rotation.size=69120\n" - "\n" - "# disable ap log\n" - "persist.sys.song.log=/data/local/log,I1,0,0,I2,0,0,I3,0,0,I4,0,0,I5,0,0,I6,0,0\n" - "\n" - "# dirac\n" - "ro.dirac.acs.controller=afm\n" - "ro.dirac.acs.storeSettings=1\n" - "ro.dirac.afm.mode=global\n" - "ro.dirac.config=66\n" - "#ro.dirac.max_active.headset=3\n" - "#ro.dirac.max_active.powersound=2\n" - "ro.dirac.poolsize=2\n" - "\n" - "# button jack mode & switch\n" - "persist.sys.button_jack_profile=volume\n" - "persist.sys.button_jack_switch=0\n" - "\n" - "#power optimize\n" - "persist.sys.power.optimize=1\n" - "\n" - "#hardware ui\n" - "debug.hwui.en_partial_updates=false\n" - "\n" - "# display features\n" - "ro.sys.display.support=59\n" - "\n" - "#hwui properties\n" - "ro.hwui.texture_cache_size=72\n" - "ro.hwui.layer_cache_size=48\n" - "ro.hwui.r_buffer_cache_size=8\n" - "ro.hwui.path_cache_size=32\n" - "ro.hwui.gradient_cache_size=1\n" - "ro.hwui.drop_shadow_cache_size=6\n" - "ro.hwui.texture_cache_flushrate=0.4\n" - "ro.hwui.text_small_cache_width=1024\n" - "ro.hwui.text_small_cache_height=1024\n" - "ro.hwui.text_large_cache_width=2048\n" - "ro.hwui.text_large_cache_height=1024\n" - "\n" - "#telephony process\n" - "log.tag.InCall=V\n" - "\n" - "#volume step\n" - "ro.config.vc_call_vol_steps=11\n" - "\n" - "# load 3 mode nvram by default\n" - "persist.sys.proj.nvram.mode=3\n" - "\n" - "# art threads\n" - "dalvik.vm.boot-dex2oat-threads=4\n" - "dalvik.vm.dex2oat-threads=4\n" - "dalvik.vm.image-dex2oat-threads=4\n" - "\n" - "#\n" - "# ADDITIONAL_BUILD_PROPERTIES\n" - "#\n" - "ro.miui.version.code_time=1492617600\n" - "ro.miui.ui.version.code=6\n" - "ro.miui.ui.version.name=V8\n" - "dalvik.vm.dex2oat-filter=\n" - "persist.radio.multisim.config=dsds\n" - "persist.logd.size.radio=2M\n" - "persist.logd.size.main=2M\n" - "persist.logd.size.system=2M\n" - "persist.dbg.allow_ims_off=1\n" - "ro.setupwizard.mode=OPTIONAL\n" - "ro.product.first_api_level=23\n" - "dalvik.vm.heapstartsize=8m\n" - "dalvik.vm.heapgrowthlimit=192m\n" - "dalvik.vm.heapsize=512m\n" - "dalvik.vm.heaptargetutilization=0.75\n" - "dalvik.vm.heapminfree=512k\n" - "dalvik.vm.heapmaxfree=8m\n" - "wifi.interface=wlan0\n" - "persist.sys.song.msms=221\n" - "persist.sys.song.standby.rat=7,3\n" - "persist.sys.song.dual2single=1\n" - "persist.sys.song.dynamic.rat=1\n" - "persist.sys.song.master.card=10\n" - "persist.sys.song.check.imei=1\n" - "persist.sys.initial.pdp.type=3\n" - "persist.ims.ut.enable=1\n" - "ffmpeg.force.decodersource=audio\n" - "persist.radio.elog.path=1\n" - "persist.sys.elog.auto.run=0\n" - "persist.sys.calls.on.ims=true\n" - "ro.carrier=unknown\n" - "ro.ril.hsxpa=1\n" - "ro.ril.gprsclass=10\n" - "ro.adb.qemud=1\n" - "persist.sys.mcd_config_file=/system/etc/mcd_default.conf\n" - "persist.sys.perf.debug=true\n" - "ro.ss.version=5.1.111-004\n" - "ro.ss.nohidden=true\n" - "persist.sys.dalvik.vm.lib.2=libart.so\n" - "dalvik.vm.isa.arm64.variant=generic\n" - "dalvik.vm.isa.arm64.features=default\n" - "dalvik.vm.isa.arm.variant=cortex-a15\n" - "dalvik.vm.isa.arm.features=default\n" - "net.bt.name=Android\n" - "dalvik.vm.stack-trace-file=/data/anr/traces.txt\n" - "ro.miui.has_real_blur=1\n" - "ro.miui.has_handy_mode_sf=1\n" - "fw.max_users=5\n" - "ro.product.mod_device=meri_global\n" - "ro.config.sms_received_sound=FadeIn.ogg\n" - "ro.config.sms_delivered_sound=MessageComplete.ogg\n" - "ro.com.android.mobiledata=false\n" - "ro.product.manufacturer=Xiaomi\n" - "ro.config.elder-ringtone=Angel.mp3\n" - "keyguard.no_require_sim=true\n" - "ro.com.android.dataroaming=false\n" - "persist.sys.mitalk.enable=true\n" - "ro.config.ringtone=Ring_Synth_04.ogg\n" - "ro.config.notification_sound=pixiedust.ogg\n" - "ro.config.alarm_alert=Alarm_Classic.ogg\n" - "ro.product.cuptsm=XIAOMI|ESE|02|01\n" - "qemu.hw.mainkeys=1\n" - "persist.dbg.volte_avail_ovr=1\n" - "persist.dbg.vt_avail_ovr=1\n" - "persist.sys.handy_mode_cct=160\n" - "ro.config.max_starting_bg=4\n" - "persist.added_boot_bgservices=4\n" - "ro.com.google.clientidbase=android-xiaomi\n" - "ro.expect.recovery_id=0x69417ef0f89bc80082ed241388a04ba1581a1182376d101747b4a3bb8171d7e8\n" - "\n" - "persist.sys.timezone=America/New_York\n" - "ro.product.locale.language=en\n" - "ro.product.locale.region=US\n" - "ro.miui.region=US\n" - "ro.miui.mcc=9310\n" - "ro.miui.mnc=9999\n" - "ro.miui.cust_variant=us\n" - "\n" - "ro.adb.secure=1\n" - "persist.adb.notify=0\n", + .content = "\n" + "# begin build properties\n" + "# autogenerated by buildinfo.sh\n" + "ro.build.id=N2G47J\n" + "ro.build.display.id=N2G47J\n" + "ro.build.version.incremental=V8.5.3.0.0.NCJCNED\n" + "ro.build.version.sdk=25\n" + "ro.build.version.preview_sdk=0\n" + "ro.build.version.codename=REL\n" + "ro.build.version.all_codenames=REL\n" + "ro.build.version.release=7.1.2\n" + "ro.build.version.security_patch=2017-05-01\n" + "ro.build.version.base_os=\n" + "ro.build.date=Thu Jun 15 10:24:29 CST 2017\n" + "ro.build.date.utc=1497493469\n" + "ro.build.type=user\n" + "ro.build.user=builder\n" + "ro.build.host=c3-miui-ota-bd09.bj\n" + "ro.build.tags=release-keys\n" + "ro.build.flavor=song-user\n" + "ro.product.model=MI 5C\n" + "ro.product.brand=Xiaomi\n" + "ro.product.name=meri\n" + "ro.product.device=song\n" + "ro.product.mod_device=meri_global\n" + "ro.product.board=\n" + "# ro.product.cpu.abi and ro.product.cpu.abi2 are obsolete,\n" + "# use ro.product.cpu.abilist instead.\n" + "ro.product.cpu.abi=arm64-v8a\n" + "ro.product.cpu.abilist=arm64-v8a,armeabi-v7a,armeabi\n" + "ro.product.cpu.abilist32=armeabi-v7a,armeabi\n" + "ro.product.cpu.abilist64=arm64-v8a\n" + "ro.product.locale=en-US\n" + "ro.wifi.channels=\n" + "ro.board.platform=song\n" + "# ro.build.product is obsolete; use ro.product.device\n" + "ro.build.product=song\n" + "# Do not try to parse description, fingerprint, or thumbprint\n" + "ro.build.description=song-user 7.1.2 N2G47J V8.5.3.0.0.NCJCNED release-keys\n" + "ro.build.fingerprint=Xiaomi/meri/meri:7.1.2/N2G47J/V8.5.3.0.0.NCJCNED:user/release-keys\n" + "ro.build.characteristics=nosdcard\n" + "# end build properties\n" + "#\n" + "# from device/pinecone/song/system.prop\n" + "#\n" + "# This overrides settings in the products/generic/system.prop file\n" + "#\n" + "# rild.libpath=/system/lib/libreference-ril.so\n" + "# rild.libargs=-d /dev/ttyS0\n" + "ro.sf.lcd_density=480\n" + "ro.opengles.version=196610\n" + "ro.telephony.default_network=9\n" + "ro.ril.modem.pb=0\n" + "\n" + "# disable strictmode\n" + "persist.sys.strictmode.disable=true\n" + "mali.hwc.flattener.interval=900\n" + "mali.hwc.flattener.enable=1\n" + "mali.hwc.rotation.size=69120\n" + "\n" + "# disable ap log\n" + "persist.sys.song.log=/data/local/log,I1,0,0,I2,0,0,I3,0,0,I4,0,0,I5,0,0,I6,0,0\n" + "\n" + "# dirac\n" + "ro.dirac.acs.controller=afm\n" + "ro.dirac.acs.storeSettings=1\n" + "ro.dirac.afm.mode=global\n" + "ro.dirac.config=66\n" + "#ro.dirac.max_active.headset=3\n" + "#ro.dirac.max_active.powersound=2\n" + "ro.dirac.poolsize=2\n" + "\n" + "# button jack mode & switch\n" + "persist.sys.button_jack_profile=volume\n" + "persist.sys.button_jack_switch=0\n" + "\n" + "#power optimize\n" + "persist.sys.power.optimize=1\n" + "\n" + "#hardware ui\n" + "debug.hwui.en_partial_updates=false\n" + "\n" + "# display features\n" + "ro.sys.display.support=59\n" + "\n" + "#hwui properties\n" + "ro.hwui.texture_cache_size=72\n" + "ro.hwui.layer_cache_size=48\n" + "ro.hwui.r_buffer_cache_size=8\n" + "ro.hwui.path_cache_size=32\n" + "ro.hwui.gradient_cache_size=1\n" + "ro.hwui.drop_shadow_cache_size=6\n" + "ro.hwui.texture_cache_flushrate=0.4\n" + "ro.hwui.text_small_cache_width=1024\n" + "ro.hwui.text_small_cache_height=1024\n" + "ro.hwui.text_large_cache_width=2048\n" + "ro.hwui.text_large_cache_height=1024\n" + "\n" + "#telephony process\n" + "log.tag.InCall=V\n" + "\n" + "#volume step\n" + "ro.config.vc_call_vol_steps=11\n" + "\n" + "# load 3 mode nvram by default\n" + "persist.sys.proj.nvram.mode=3\n" + "\n" + "# art threads\n" + "dalvik.vm.boot-dex2oat-threads=4\n" + "dalvik.vm.dex2oat-threads=4\n" + "dalvik.vm.image-dex2oat-threads=4\n" + "\n" + "#\n" + "# ADDITIONAL_BUILD_PROPERTIES\n" + "#\n" + "ro.miui.version.code_time=1492617600\n" + "ro.miui.ui.version.code=6\n" + "ro.miui.ui.version.name=V8\n" + "dalvik.vm.dex2oat-filter=\n" + "persist.radio.multisim.config=dsds\n" + "persist.logd.size.radio=2M\n" + "persist.logd.size.main=2M\n" + "persist.logd.size.system=2M\n" + "persist.dbg.allow_ims_off=1\n" + "ro.setupwizard.mode=OPTIONAL\n" + "ro.product.first_api_level=23\n" + "dalvik.vm.heapstartsize=8m\n" + "dalvik.vm.heapgrowthlimit=192m\n" + "dalvik.vm.heapsize=512m\n" + "dalvik.vm.heaptargetutilization=0.75\n" + "dalvik.vm.heapminfree=512k\n" + "dalvik.vm.heapmaxfree=8m\n" + "wifi.interface=wlan0\n" + "persist.sys.song.msms=221\n" + "persist.sys.song.standby.rat=7,3\n" + "persist.sys.song.dual2single=1\n" + "persist.sys.song.dynamic.rat=1\n" + "persist.sys.song.master.card=10\n" + "persist.sys.song.check.imei=1\n" + "persist.sys.initial.pdp.type=3\n" + "persist.ims.ut.enable=1\n" + "ffmpeg.force.decodersource=audio\n" + "persist.radio.elog.path=1\n" + "persist.sys.elog.auto.run=0\n" + "persist.sys.calls.on.ims=true\n" + "ro.carrier=unknown\n" + "ro.ril.hsxpa=1\n" + "ro.ril.gprsclass=10\n" + "ro.adb.qemud=1\n" + "persist.sys.mcd_config_file=/system/etc/mcd_default.conf\n" + "persist.sys.perf.debug=true\n" + "ro.ss.version=5.1.111-004\n" + "ro.ss.nohidden=true\n" + "persist.sys.dalvik.vm.lib.2=libart.so\n" + "dalvik.vm.isa.arm64.variant=generic\n" + "dalvik.vm.isa.arm64.features=default\n" + "dalvik.vm.isa.arm.variant=cortex-a15\n" + "dalvik.vm.isa.arm.features=default\n" + "net.bt.name=Android\n" + "dalvik.vm.stack-trace-file=/data/anr/traces.txt\n" + "ro.miui.has_real_blur=1\n" + "ro.miui.has_handy_mode_sf=1\n" + "fw.max_users=5\n" + "ro.product.mod_device=meri_global\n" + "ro.config.sms_received_sound=FadeIn.ogg\n" + "ro.config.sms_delivered_sound=MessageComplete.ogg\n" + "ro.com.android.mobiledata=false\n" + "ro.product.manufacturer=Xiaomi\n" + "ro.config.elder-ringtone=Angel.mp3\n" + "keyguard.no_require_sim=true\n" + "ro.com.android.dataroaming=false\n" + "persist.sys.mitalk.enable=true\n" + "ro.config.ringtone=Ring_Synth_04.ogg\n" + "ro.config.notification_sound=pixiedust.ogg\n" + "ro.config.alarm_alert=Alarm_Classic.ogg\n" + "ro.product.cuptsm=XIAOMI|ESE|02|01\n" + "qemu.hw.mainkeys=1\n" + "persist.dbg.volte_avail_ovr=1\n" + "persist.dbg.vt_avail_ovr=1\n" + "persist.sys.handy_mode_cct=160\n" + "ro.config.max_starting_bg=4\n" + "persist.added_boot_bgservices=4\n" + "ro.com.google.clientidbase=android-xiaomi\n" + "ro.expect.recovery_id=0x69417ef0f89bc80082ed241388a04ba1581a1182376d101747b4a3bb8171d7e8\n" + "\n" + "persist.sys.timezone=America/New_York\n" + "ro.product.locale.language=en\n" + "ro.product.locale.region=US\n" + "ro.miui.region=US\n" + "ro.miui.mcc=9310\n" + "ro.miui.mnc=9999\n" + "ro.miui.cust_variant=us\n" + "\n" + "ro.adb.secure=1\n" + "persist.adb.notify=0\n", }, { .path = "/sys/devices/system/cpu/kernel_max", @@ -353,24 +350,22 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpufreq/all_time_in_state", .size = 409, - .content = - "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\t\n" - "460800\t\t3124\t\t3124\t\t3124\t\t3124\t\tN/A\t\tN/A\t\t\n" - "624000\t\t165\t\t165\t\t165\t\t165\t\tN/A\t\tN/A\t\t\n" - "1248000\t\t6344\t\t6344\t\t6344\t\t6344\t\tN/A\t\tN/A\t\t\n" - "1404000\t\t86\t\t86\t\t86\t\t86\t\tN/A\t\tN/A\t\t\n" - "1843200\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t8105\t\t8105\t\t\n" - "1950000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\t0\t\t\n" - "2002000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\t0\t\t\n" - "2106000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t14\t\t14\t\t\n" - "2158000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t180\t\t180\t\t\n", + .content = "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\t\n" + "460800\t\t3124\t\t3124\t\t3124\t\t3124\t\tN/A\t\tN/A\t\t\n" + "624000\t\t165\t\t165\t\t165\t\t165\t\tN/A\t\tN/A\t\t\n" + "1248000\t\t6344\t\t6344\t\t6344\t\t6344\t\tN/A\t\tN/A\t\t\n" + "1404000\t\t86\t\t86\t\t86\t\t86\t\tN/A\t\tN/A\t\t\n" + "1843200\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t8105\t\t8105\t\t\n" + "1950000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\t0\t\t\n" + "2002000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t0\t\t0\t\t\n" + "2106000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t14\t\t14\t\t\n" + "2158000\t\tN/A\t\tN/A\t\tN/A\t\tN/A\t\t180\t\t180\t\t\n", }, { .path = "/sys/devices/system/cpu/cpufreq/current_in_state", .size = 116, - .content = - "CPU0:460800=46 624000=70 1248000=174 1404000=217 \n" - "CPU4:1843200=300 1950000=352 2002000=370 2106000=421 2158000=470 \n", + .content = "CPU0:460800=46 624000=70 1248000=174 1404000=217 \n" + "CPU4:1843200=300 1950000=352 2002000=370 2106000=421 2158000=470 \n", }, { .path = "/sys/devices/system/cpu/cpuidle/current_driver", @@ -440,11 +435,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 47, - .content = - "460800 3240\n" - "624000 165\n" - "1248000 6358\n" - "1404000 86\n", + .content = "460800 3240\n" + "624000 165\n" + "1248000 6358\n" + "1404000 86\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -539,11 +533,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 47, - .content = - "460800 3445\n" - "624000 194\n" - "1248000 6358\n" - "1404000 86\n", + .content = "460800 3445\n" + "624000 194\n" + "1248000 6358\n" + "1404000 86\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -638,11 +631,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 47, - .content = - "460800 3671\n" - "624000 194\n" - "1248000 6368\n" - "1404000 86\n", + .content = "460800 3671\n" + "624000 194\n" + "1248000 6368\n" + "1404000 86\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -737,11 +729,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 47, - .content = - "460800 3914\n" - "624000 194\n" - "1248000 6368\n" - "1404000 86\n", + .content = "460800 3914\n" + "624000 194\n" + "1248000 6368\n" + "1404000 86\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -841,12 +832,11 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/time_in_state", .size = 54, - .content = - "1843200 6013\n" - "1950000 0\n" - "2002000 0\n" - "2106000 1\n" - "2158000 54\n", + .content = "1843200 6013\n" + "1950000 0\n" + "2002000 0\n" + "2106000 1\n" + "2158000 54\n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/total_trans", @@ -946,12 +936,11 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/time_in_state", .size = 54, - .content = - "1843200 6264\n" - "1950000 0\n" - "2002000 0\n" - "2106000 1\n" - "2158000 54\n", + .content = "1843200 6264\n" + "1950000 0\n" + "2002000 0\n" + "2106000 1\n" + "2158000 54\n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/total_trans", @@ -988,7 +977,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "5\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -2424,6 +2413,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.driver.status", .value = "ok", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/xiaomi-redmi-2a.cc b/test/mock/xiaomi-redmi-2a.cc index 3e0d7a82..be56fe4d 100644 --- a/test/mock/xiaomi-redmi-2a.cc +++ b/test/mock/xiaomi-redmi-2a.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(5, cpuinfo_get_processors_count()); @@ -266,8 +265,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Leadcore LC1860", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Leadcore LC1860", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -458,8 +459,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -510,8 +513,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -569,8 +574,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/xiaomi-redmi-2a.h b/test/mock/xiaomi-redmi-2a.h index 1e8af3fc..7bd70d66 100644 --- a/test/mock/xiaomi-redmi-2a.h +++ b/test/mock/xiaomi-redmi-2a.h @@ -2,54 +2,53 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 1225, - .content = - "processor\t: 0\n" - "model name\t: ARMv7 Processor rev 5 (v7l)\n" - "Processor\t: ARMv7 Processor rev 5 (v7l)\n" - "BogoMIPS\t: 2609.15\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xc07\n" - "CPU revision\t: 5\n" - "\n" - "processor\t: 1\n" - "model name\t: ARMv7 Processor rev 5 (v7l)\n" - "Processor\t: ARMv7 Processor rev 5 (v7l)\n" - "BogoMIPS\t: 2609.15\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xc07\n" - "CPU revision\t: 5\n" - "\n" - "processor\t: 2\n" - "model name\t: ARMv7 Processor rev 5 (v7l)\n" - "Processor\t: ARMv7 Processor rev 5 (v7l)\n" - "BogoMIPS\t: 2609.15\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xc07\n" - "CPU revision\t: 5\n" - "\n" - "processor\t: 3\n" - "model name\t: ARMv7 Processor rev 5 (v7l)\n" - "Processor\t: ARMv7 Processor rev 5 (v7l)\n" - "BogoMIPS\t: 2609.15\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xc07\n" - "CPU revision\t: 5\n" - "\n" - "Hardware\t: Leadcore Innopower\n" - "Revision\t: 0000\n" - "Serial\t\t: 0000000000000000\n", + .content = "processor\t: 0\n" + "model name\t: ARMv7 Processor rev 5 (v7l)\n" + "Processor\t: ARMv7 Processor rev 5 (v7l)\n" + "BogoMIPS\t: 2609.15\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xc07\n" + "CPU revision\t: 5\n" + "\n" + "processor\t: 1\n" + "model name\t: ARMv7 Processor rev 5 (v7l)\n" + "Processor\t: ARMv7 Processor rev 5 (v7l)\n" + "BogoMIPS\t: 2609.15\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xc07\n" + "CPU revision\t: 5\n" + "\n" + "processor\t: 2\n" + "model name\t: ARMv7 Processor rev 5 (v7l)\n" + "Processor\t: ARMv7 Processor rev 5 (v7l)\n" + "BogoMIPS\t: 2609.15\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xc07\n" + "CPU revision\t: 5\n" + "\n" + "processor\t: 3\n" + "model name\t: ARMv7 Processor rev 5 (v7l)\n" + "Processor\t: ARMv7 Processor rev 5 (v7l)\n" + "BogoMIPS\t: 2609.15\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xc07\n" + "CPU revision\t: 5\n" + "\n" + "Hardware\t: Leadcore Innopower\n" + "Revision\t: 0000\n" + "Serial\t\t: 0000000000000000\n", }, { .path = "/system/build.prop", @@ -280,18 +279,17 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 114, - .content = - "1495000 450\n" - "1401563 20\n" - "1308125 12\n" - "1214688 0\n" - "1121250 9\n" - "1027813 2\n" - "934375 18\n" - "840938 33\n" - "747500 213\n" - "654063 14\n" - "624000 0\n", + .content = "1495000 450\n" + "1401563 20\n" + "1308125 12\n" + "1214688 0\n" + "1121250 9\n" + "1027813 2\n" + "934375 18\n" + "840938 33\n" + "747500 213\n" + "654063 14\n" + "624000 0\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -409,18 +407,17 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 116, - .content = - "1495000 595\n" - "1401563 24\n" - "1308125 12\n" - "1214688 4\n" - "1121250 17\n" - "1027813 10\n" - "934375 30\n" - "840938 49\n" - "747500 233\n" - "654063 14\n" - "624000 0\n", + .content = "1495000 595\n" + "1401563 24\n" + "1308125 12\n" + "1214688 4\n" + "1121250 17\n" + "1027813 10\n" + "934375 30\n" + "840938 49\n" + "747500 233\n" + "654063 14\n" + "624000 0\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -538,18 +535,17 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 116, - .content = - "1495000 763\n" - "1401563 24\n" - "1308125 28\n" - "1214688 4\n" - "1121250 29\n" - "1027813 10\n" - "934375 30\n" - "840938 49\n" - "747500 258\n" - "654063 18\n" - "624000 0\n", + .content = "1495000 763\n" + "1401563 24\n" + "1308125 28\n" + "1214688 4\n" + "1121250 29\n" + "1027813 10\n" + "934375 30\n" + "840938 49\n" + "747500 258\n" + "654063 18\n" + "624000 0\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -667,20 +663,19 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 116, - .content = - "1495000 956\n" - "1401563 24\n" - "1308125 40\n" - "1214688 4\n" - "1121250 49\n" - "1027813 10\n" - "934375 30\n" - "840938 49\n" - "747500 264\n" - "654063 18\n" - "624000 0\n", - }, - { NULL }, + .content = "1495000 956\n" + "1401563 24\n" + "1308125 40\n" + "1214688 4\n" + "1121250 49\n" + "1027813 10\n" + "934375 30\n" + "840938 49\n" + "747500 264\n" + "654063 18\n" + "624000 0\n", + }, + {NULL}, }; #ifdef __ANDROID__ @@ -1593,6 +1588,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wifi.interface", .value = "wlan0", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/xiaomi-redmi-note-3.cc b/test/mock/xiaomi-redmi-note-3.cc index a9847b5e..f61ebd5f 100644 --- a/test/mock/xiaomi-redmi-note-3.cc +++ b/test/mock/xiaomi-redmi-note-3.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(6, cpuinfo_get_processors_count()); @@ -334,8 +333,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Qualcomm MSM8956", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Qualcomm MSM8956", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -377,59 +378,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -576,8 +577,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -639,8 +642,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -698,8 +703,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/xiaomi-redmi-note-3.h b/test/mock/xiaomi-redmi-note-3.h index 7fe6eab2..239ca306 100644 --- a/test/mock/xiaomi-redmi-note-3.h +++ b/test/mock/xiaomi-redmi-note-3.h @@ -3,22 +3,21 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 327, - .content = - "Processor\t: AArch64 Processor rev 4 (aarch64)\n" - "processor\t: 0\n" - "processor\t: 1\n" - "processor\t: 2\n" - "processor\t: 3\n" - "processor\t: 4\n" - "processor\t: 5\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 \n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "Hardware\t: Qualcomm Technologies, Inc MSM8956\n", + .content = "Processor\t: AArch64 Processor rev 4 (aarch64)\n" + "processor\t: 0\n" + "processor\t: 1\n" + "processor\t: 2\n" + "processor\t: 3\n" + "processor\t: 4\n" + "processor\t: 5\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 \n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "Hardware\t: Qualcomm Technologies, Inc MSM8956\n", }, #elif CPUINFO_ARCH_ARM { @@ -432,12 +431,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/class/kgsl/kgsl-3d0/devfreq/available_frequencies", .size = 91, - .content = "133333333 200000000 266666667 300000000 366670000 432000000 480000000 550000000 600000000\r\n", + .content = + "133333333 200000000 266666667 300000000 366670000 432000000 480000000 550000000 600000000\r\n", }, { .path = "/sys/class/kgsl/kgsl-3d0/devfreq/available_governors", .size = 110, - .content = "spdm_bw_hyp bw_hwmon bw_vbif gpubw_mon msm-adreno-tz cpufreq userspace powersave performance simple_ondemand\r\n", + .content = + "spdm_bw_hyp bw_hwmon bw_vbif gpubw_mon msm-adreno-tz cpufreq userspace powersave performance simple_ondemand\r\n", }, { .path = "/sys/class/kgsl/kgsl-3d0/devfreq/cur_freq", @@ -472,15 +473,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/class/kgsl/kgsl-3d0/devfreq/trans_stat", .size = 423, - .content = - " From : To\r\n" - " :600000000480000000432000000300000000266666667 time(ms)\r\n" - " 600000000: 0 0 0 0 0 0\r\n" - " 480000000: 0 0 1 0 2 42840\r\n" - " 432000000: 0 0 0 1 2 1540\r\n" - " 300000000: 0 0 2 0 3 1090\r\n" - "*266666667: 0 3 0 4 0 380980\r\n" - "Total transition : 18\r\n", + .content = " From : To\r\n" + " :600000000480000000432000000300000000266666667 time(ms)\r\n" + " 600000000: 0 0 0 0 0 0\r\n" + " 480000000: 0 0 1 0 2 42840\r\n" + " 432000000: 0 0 0 1 2 1540\r\n" + " 300000000: 0 0 2 0 3 1090\r\n" + "*266666667: 0 3 0 4 0 380980\r\n" + "Total transition : 18\r\n", }, { .path = "/sys/class/kgsl/kgsl-3d0/ft_fast_hang_detect", @@ -610,23 +610,20 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/soc0/image_crm_version", .size = 5, - .content = - "REL\n" - "\n", + .content = "REL\n" + "\n", }, { .path = "/sys/devices/soc0/image_variant", .size = 12, - .content = - "kenzo-user\n" - "\n", + .content = "kenzo-user\n" + "\n", }, { .path = "/sys/devices/soc0/image_version", .size = 28, - .content = - "10:LMY47V:V8.0.7.0.LHOCNDG\n" - "\n", + .content = "10:LMY47V:V8.0.7.0.LHOCNDG\n" + "\n", }, { .path = "/sys/devices/soc0/machine", @@ -741,55 +738,54 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/core_ctl/global_state", .size = 527, - .content = - "CPU0\n" - "\tCPU: 0\n" - "\tOnline: 1\n" - "\tRejected: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 3\n" - "\tIs busy: 1\n" - "\tNr running: 0\n" - "\tAvail CPUs: 4\n" - "\tNeed CPUs: 4\n" - "CPU1\n" - "\tCPU: 1\n" - "\tOnline: 1\n" - "\tRejected: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 0\n" - "\tIs busy: 1\n" - "CPU2\n" - "\tCPU: 2\n" - "\tOnline: 1\n" - "\tRejected: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 10\n" - "\tIs busy: 1\n" - "CPU3\n" - "\tCPU: 3\n" - "\tOnline: 1\n" - "\tRejected: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 2\n" - "\tIs busy: 1\n" - "CPU4\n" - "\tCPU: 4\n" - "\tOnline: 1\n" - "\tRejected: 0\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "\tNr running: 0\n" - "\tAvail CPUs: 2\n" - "\tNeed CPUs: 0\n" - "CPU5\n" - "\tCPU: 5\n" - "\tOnline: 1\n" - "\tRejected: 0\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n", + .content = "CPU0\n" + "\tCPU: 0\n" + "\tOnline: 1\n" + "\tRejected: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 3\n" + "\tIs busy: 1\n" + "\tNr running: 0\n" + "\tAvail CPUs: 4\n" + "\tNeed CPUs: 4\n" + "CPU1\n" + "\tCPU: 1\n" + "\tOnline: 1\n" + "\tRejected: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 0\n" + "\tIs busy: 1\n" + "CPU2\n" + "\tCPU: 2\n" + "\tOnline: 1\n" + "\tRejected: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 10\n" + "\tIs busy: 1\n" + "CPU3\n" + "\tCPU: 3\n" + "\tOnline: 1\n" + "\tRejected: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 2\n" + "\tIs busy: 1\n" + "CPU4\n" + "\tCPU: 4\n" + "\tOnline: 1\n" + "\tRejected: 0\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "\tNr running: 0\n" + "\tAvail CPUs: 2\n" + "\tNeed CPUs: 0\n" + "CPU5\n" + "\tCPU: 5\n" + "\tOnline: 1\n" + "\tRejected: 0\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n", }, { .path = "/sys/devices/system/cpu/cpu0/core_ctl/is_big_cluster", @@ -814,11 +810,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/core_ctl/not_preferred", .size = 36, - .content = - "\tCPU:0 0\n" - "\tCPU:1 0\n" - "\tCPU:2 0\n" - "\tCPU:3 0\n", + .content = "\tCPU:0 0\n" + "\tCPU:1 0\n" + "\tCPU:2 0\n" + "\tCPU:3 0\n", }, { .path = "/sys/devices/system/cpu/cpu0/core_ctl/offline_delay_ms", @@ -888,15 +883,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 94, - .content = - "400000 0\n" - "691200 34849\n" - "806400 234\n" - "1017600 415\n" - "1190400 176\n" - "1305600 2200\n" - "1382400 91\n" - "1401600 4725\n", + .content = "400000 0\n" + "691200 34849\n" + "806400 234\n" + "1017600 415\n" + "1190400 176\n" + "1305600 2200\n" + "1382400 91\n" + "1401600 4725\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -991,15 +985,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 94, - .content = - "400000 0\n" - "691200 35077\n" - "806400 234\n" - "1017600 415\n" - "1190400 176\n" - "1305600 2200\n" - "1382400 91\n" - "1401600 4725\n", + .content = "400000 0\n" + "691200 35077\n" + "806400 234\n" + "1017600 415\n" + "1190400 176\n" + "1305600 2200\n" + "1382400 91\n" + "1401600 4725\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -1094,15 +1087,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 94, - .content = - "400000 0\n" - "691200 35312\n" - "806400 234\n" - "1017600 415\n" - "1190400 176\n" - "1305600 2200\n" - "1382400 91\n" - "1401600 4725\n", + .content = "400000 0\n" + "691200 35312\n" + "806400 234\n" + "1017600 415\n" + "1190400 176\n" + "1305600 2200\n" + "1382400 91\n" + "1401600 4725\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -1197,15 +1189,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 94, - .content = - "400000 0\n" - "691200 35557\n" - "806400 234\n" - "1017600 415\n" - "1190400 176\n" - "1305600 2200\n" - "1382400 91\n" - "1401600 4725\n", + .content = "400000 0\n" + "691200 35557\n" + "806400 234\n" + "1017600 415\n" + "1190400 176\n" + "1305600 2200\n" + "1382400 91\n" + "1401600 4725\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -1255,55 +1246,54 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/core_ctl/global_state", .size = 526, - .content = - "CPU0\n" - "\tCPU: 0\n" - "\tOnline: 1\n" - "\tRejected: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 1\n" - "\tIs busy: 1\n" - "\tNr running: 0\n" - "\tAvail CPUs: 4\n" - "\tNeed CPUs: 4\n" - "CPU1\n" - "\tCPU: 1\n" - "\tOnline: 1\n" - "\tRejected: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 0\n" - "\tIs busy: 1\n" - "CPU2\n" - "\tCPU: 2\n" - "\tOnline: 1\n" - "\tRejected: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 7\n" - "\tIs busy: 1\n" - "CPU3\n" - "\tCPU: 3\n" - "\tOnline: 1\n" - "\tRejected: 0\n" - "\tFirst CPU: 0\n" - "\tBusy%: 0\n" - "\tIs busy: 1\n" - "CPU4\n" - "\tCPU: 4\n" - "\tOnline: 1\n" - "\tRejected: 0\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n" - "\tNr running: 0\n" - "\tAvail CPUs: 2\n" - "\tNeed CPUs: 0\n" - "CPU5\n" - "\tCPU: 5\n" - "\tOnline: 1\n" - "\tRejected: 0\n" - "\tFirst CPU: 4\n" - "\tBusy%: 0\n" - "\tIs busy: 0\n", + .content = "CPU0\n" + "\tCPU: 0\n" + "\tOnline: 1\n" + "\tRejected: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 1\n" + "\tIs busy: 1\n" + "\tNr running: 0\n" + "\tAvail CPUs: 4\n" + "\tNeed CPUs: 4\n" + "CPU1\n" + "\tCPU: 1\n" + "\tOnline: 1\n" + "\tRejected: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 0\n" + "\tIs busy: 1\n" + "CPU2\n" + "\tCPU: 2\n" + "\tOnline: 1\n" + "\tRejected: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 7\n" + "\tIs busy: 1\n" + "CPU3\n" + "\tCPU: 3\n" + "\tOnline: 1\n" + "\tRejected: 0\n" + "\tFirst CPU: 0\n" + "\tBusy%: 0\n" + "\tIs busy: 1\n" + "CPU4\n" + "\tCPU: 4\n" + "\tOnline: 1\n" + "\tRejected: 0\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n" + "\tNr running: 0\n" + "\tAvail CPUs: 2\n" + "\tNeed CPUs: 0\n" + "CPU5\n" + "\tCPU: 5\n" + "\tOnline: 1\n" + "\tRejected: 0\n" + "\tFirst CPU: 4\n" + "\tBusy%: 0\n" + "\tIs busy: 0\n", }, { .path = "/sys/devices/system/cpu/cpu4/core_ctl/is_big_cluster", @@ -1328,9 +1318,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/core_ctl/not_preferred", .size = 18, - .content = - "\tCPU:4 0\n" - "\tCPU:5 0\n", + .content = "\tCPU:4 0\n" + "\tCPU:5 0\n", }, { .path = "/sys/devices/system/cpu/cpu4/core_ctl/offline_delay_ms", @@ -1375,7 +1364,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_available_frequencies", .size = 101, - .content = "400000 883200 940800 998400 1056000 1113600 1190400 1248000 1305600 1382400 1612800 1747200 1804800 \n", + .content = + "400000 883200 940800 998400 1056000 1113600 1190400 1248000 1305600 1382400 1612800 1747200 1804800 \n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_available_governors", @@ -1410,20 +1400,19 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/time_in_state", .size = 142, - .content = - "400000 0\n" - "883200 39978\n" - "940800 27\n" - "998400 15\n" - "1056000 11\n" - "1113600 77\n" - "1190400 10\n" - "1248000 16\n" - "1305600 0\n" - "1382400 530\n" - "1612800 68\n" - "1747200 0\n" - "1804800 2914\n", + .content = "400000 0\n" + "883200 39978\n" + "940800 27\n" + "998400 15\n" + "1056000 11\n" + "1113600 77\n" + "1190400 10\n" + "1248000 16\n" + "1305600 0\n" + "1382400 530\n" + "1612800 68\n" + "1747200 0\n" + "1804800 2914\n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/total_trans", @@ -1493,7 +1482,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_available_frequencies", .size = 101, - .content = "400000 883200 940800 998400 1056000 1113600 1190400 1248000 1305600 1382400 1612800 1747200 1804800 \n", + .content = + "400000 883200 940800 998400 1056000 1113600 1190400 1248000 1305600 1382400 1612800 1747200 1804800 \n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_available_governors", @@ -1528,20 +1518,19 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/time_in_state", .size = 142, - .content = - "400000 0\n" - "883200 40217\n" - "940800 27\n" - "998400 15\n" - "1056000 11\n" - "1113600 77\n" - "1190400 10\n" - "1248000 16\n" - "1305600 0\n" - "1382400 530\n" - "1612800 68\n" - "1747200 0\n" - "1804800 2914\n", + .content = "400000 0\n" + "883200 40217\n" + "940800 27\n" + "998400 15\n" + "1056000 11\n" + "1113600 77\n" + "1190400 10\n" + "1248000 16\n" + "1305600 0\n" + "1382400 530\n" + "1612800 68\n" + "1747200 0\n" + "1804800 2914\n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/total_trans", @@ -1578,7 +1567,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "5\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -3518,6 +3507,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.driver.status", .value = "ok", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/xiaomi-redmi-note-4.cc b/test/mock/xiaomi-redmi-note-4.cc index 7044735d..8039f8f6 100644 --- a/test/mock/xiaomi-redmi-note-4.cc +++ b/test/mock/xiaomi-redmi-note-4.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(8, cpuinfo_get_processors_count()); @@ -274,8 +273,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Qualcomm MSM8953", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Qualcomm MSM8953", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -317,59 +318,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -494,8 +495,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -546,8 +549,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -605,8 +610,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/xiaomi-redmi-note-4.h b/test/mock/xiaomi-redmi-note-4.h index 06e7b8ba..021518b9 100644 --- a/test/mock/xiaomi-redmi-note-4.h +++ b/test/mock/xiaomi-redmi-note-4.h @@ -3,81 +3,80 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 1540, - .content = - "Processor\t: AArch64 Processor rev 4 (aarch64)\n" - "processor\t: 0\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 1\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 2\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 3\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 4\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 5\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 6\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "processor\t: 7\n" - "BogoMIPS\t: 38.40\n" - "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: 8\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 4\n" - "\n" - "Hardware\t: Qualcomm Technologies, Inc MSM8953\n", + .content = "Processor\t: AArch64 Processor rev 4 (aarch64)\n" + "processor\t: 0\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 1\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 2\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 3\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 4\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 5\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 6\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "processor\t: 7\n" + "BogoMIPS\t: 38.40\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 4\n" + "\n" + "Hardware\t: Qualcomm Technologies, Inc MSM8953\n", }, #elif CPUINFO_ARCH_ARM { @@ -590,7 +589,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/class/kgsl/kgsl-3d0/devfreq/available_governors", .size = 165, - .content = "spdm_bw_hyp bw_hwmon venus-ddr-gov msm-vidc-vmem+ msm-vidc-vmem msm-vidc-ddr bw_vbif gpubw_mon msm-adreno-tz cpufreq userspace powersave performance simple_ondemand\n", + .content = + "spdm_bw_hyp bw_hwmon venus-ddr-gov msm-vidc-vmem+ msm-vidc-vmem msm-vidc-ddr bw_vbif gpubw_mon msm-adreno-tz cpufreq userspace powersave performance simple_ondemand\n", }, { .path = "/sys/class/kgsl/kgsl-3d0/devfreq/cur_freq", @@ -635,17 +635,16 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/class/kgsl/kgsl-3d0/devfreq/trans_stat", .size = 670, - .content = - " From : To\n" - " :650000000560000000510000000400000000320000000216000000133330000 time(ms)\n" - " 650000000: 0 0 0 0 0 0 0 0\n" - " 560000000: 0 0 1 0 0 0 0 210\n" - "*510000000: 0 1 0 2 0 0 0 97470\n" - " 400000000: 0 0 2 0 5 0 0 119280\n" - " 320000000: 0 0 1 4 0 54 0 96060\n" - " 216000000: 0 0 0 0 38 0 100 59980\n" - " 133330000: 0 0 0 1 15 84 0 78320\n" - "Total transition : 308\n", + .content = " From : To\n" + " :650000000560000000510000000400000000320000000216000000133330000 time(ms)\n" + " 650000000: 0 0 0 0 0 0 0 0\n" + " 560000000: 0 0 1 0 0 0 0 210\n" + "*510000000: 0 1 0 2 0 0 0 97470\n" + " 400000000: 0 0 2 0 5 0 0 119280\n" + " 320000000: 0 0 1 4 0 54 0 96060\n" + " 216000000: 0 0 0 0 38 0 100 59980\n" + " 133330000: 0 0 0 1 15 84 0 78320\n" + "Total transition : 308\n", }, { .path = "/sys/class/kgsl/kgsl-3d0/freq_table_mhz", @@ -820,71 +819,67 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/soc0/image_crm_version", .size = 5, - .content = - "REL\n" - "\n", + .content = "REL\n" + "\n", }, { .path = "/sys/devices/soc0/image_variant", .size = 11, - .content = - "mido-user\n" - "\n", + .content = "mido-user\n" + "\n", }, { .path = "/sys/devices/soc0/image_version", .size = 28, - .content = - "10:NRD90M:V8.5.4.0.NCFMIED\n" - "\n", + .content = "10:NRD90M:V8.5.4.0.NCFMIED\n" + "\n", }, { .path = "/sys/devices/soc0/images", .size = 562, - .content = - "0:\n" - "\tCRM:\t\t00:BOOT.BF.3.3-00199\n" - "\tVariant:\tJAASANAZA\n" - "\tVersion:\tmodem-ci\n" - "\n" - "1:\n" - "\tCRM:\t\t01:TZ.BF.4.0.5-00030\n" - "\tVariant:\t\n" - "\tVersion:\tCRM\n" - "\n" - "3:\n" - "\tCRM:\t\t03:RPM.BF.2.4-00054\n" - "\tVariant:\tAAAAANAAR\n" - "\tVersion:\tmodem-ci\n" - "\n" - "10:\n" - "\tCRM:\t\t10:NRD90M:V8.5.4.0.NCFMIED\n" - "\n" - "\tVariant:\tmido-user\n" - "\n" - "\tVersion:\tREL\n" - "\n" - "\n" - "11:\n" - "\tCRM:\t\t11:MPSS.TA.2.2.C1-109373\n" - "\tVariant:\t8953.gen.prodQ\n" - "\tVersion:\tmodem-ci\n" - "\n" - "12:\n" - "\tCRM:\t\t12:ADSP.8953.2.8.2-00046\n" - "\tVariant:\tAAAAAAAAQ\n" - "\tVersion:\tmodem-ci\n" - "\n" - "13:\n" - "\tCRM:\t\t13:CNSS.PR.4.0-107273\n" - "\tVariant:\tSCAQNAZM\n" - "\tVersion:\tCRM\n" - "\n" - "14:\n" - "\tCRM:\t\t14:VIDEO.VE.4.2-00031\n" - "\tVariant:\tPROD\n" - "\tVersion:\t:CRM\n" - "\n", + .content = "0:\n" + "\tCRM:\t\t00:BOOT.BF.3.3-00199\n" + "\tVariant:\tJAASANAZA\n" + "\tVersion:\tmodem-ci\n" + "\n" + "1:\n" + "\tCRM:\t\t01:TZ.BF.4.0.5-00030\n" + "\tVariant:\t\n" + "\tVersion:\tCRM\n" + "\n" + "3:\n" + "\tCRM:\t\t03:RPM.BF.2.4-00054\n" + "\tVariant:\tAAAAANAAR\n" + "\tVersion:\tmodem-ci\n" + "\n" + "10:\n" + "\tCRM:\t\t10:NRD90M:V8.5.4.0.NCFMIED\n" + "\n" + "\tVariant:\tmido-user\n" + "\n" + "\tVersion:\tREL\n" + "\n" + "\n" + "11:\n" + "\tCRM:\t\t11:MPSS.TA.2.2.C1-109373\n" + "\tVariant:\t8953.gen.prodQ\n" + "\tVersion:\tmodem-ci\n" + "\n" + "12:\n" + "\tCRM:\t\t12:ADSP.8953.2.8.2-00046\n" + "\tVariant:\tAAAAAAAAQ\n" + "\tVersion:\tmodem-ci\n" + "\n" + "13:\n" + "\tCRM:\t\t13:CNSS.PR.4.0-107273\n" + "\tVariant:\tSCAQNAZM\n" + "\tVersion:\tCRM\n" + "\n" + "14:\n" + "\tCRM:\t\t14:VIDEO.VE.4.2-00031\n" + "\tVariant:\tPROD\n" + "\tVersion:\t:CRM\n" + "\n", }, { .path = "/sys/devices/soc0/machine", @@ -989,11 +984,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpufreq/current_in_state", .size = 300, - .content = - "CPU4:652800=0 1036800=0 1401600=0 1689600=0 1843200=0 1958400=0 2016000=0 \n" - "CPU5:652800=0 1036800=0 1401600=0 1689600=0 1843200=0 1958400=0 2016000=0 \n" - "CPU6:652800=0 1036800=0 1401600=0 1689600=0 1843200=0 1958400=0 2016000=0 \n" - "CPU7:652800=0 1036800=0 1401600=0 1689600=0 1843200=0 1958400=0 2016000=0 \n", + .content = "CPU4:652800=0 1036800=0 1401600=0 1689600=0 1843200=0 1958400=0 2016000=0 \n" + "CPU5:652800=0 1036800=0 1401600=0 1689600=0 1843200=0 1958400=0 2016000=0 \n" + "CPU6:652800=0 1036800=0 1401600=0 1689600=0 1843200=0 1958400=0 2016000=0 \n" + "CPU7:652800=0 1036800=0 1401600=0 1689600=0 1843200=0 1958400=0 2016000=0 \n", }, { .path = "/sys/devices/system/cpu/cpuidle/current_driver", @@ -1068,14 +1062,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 86, - .content = - "652800 35835\n" - "1036800 525\n" - "1401600 1882\n" - "1689600 426\n" - "1843200 291\n" - "1958400 84\n" - "2016000 6157\n", + .content = "652800 35835\n" + "1036800 525\n" + "1401600 1882\n" + "1689600 426\n" + "1843200 291\n" + "1958400 84\n" + "2016000 6157\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -1175,14 +1168,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 86, - .content = - "652800 36081\n" - "1036800 525\n" - "1401600 1882\n" - "1689600 426\n" - "1843200 291\n" - "1958400 84\n" - "2016000 6157\n", + .content = "652800 36081\n" + "1036800 525\n" + "1401600 1882\n" + "1689600 426\n" + "1843200 291\n" + "1958400 84\n" + "2016000 6157\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -1282,14 +1274,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 86, - .content = - "652800 36327\n" - "1036800 525\n" - "1401600 1882\n" - "1689600 426\n" - "1843200 291\n" - "1958400 84\n" - "2016000 6157\n", + .content = "652800 36327\n" + "1036800 525\n" + "1401600 1882\n" + "1689600 426\n" + "1843200 291\n" + "1958400 84\n" + "2016000 6157\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -1389,14 +1380,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 86, - .content = - "652800 36575\n" - "1036800 525\n" - "1401600 1882\n" - "1689600 426\n" - "1843200 291\n" - "1958400 84\n" - "2016000 6157\n", + .content = "652800 36575\n" + "1036800 525\n" + "1401600 1882\n" + "1689600 426\n" + "1843200 291\n" + "1958400 84\n" + "2016000 6157\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -1496,14 +1486,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/time_in_state", .size = 86, - .content = - "652800 36826\n" - "1036800 525\n" - "1401600 1882\n" - "1689600 426\n" - "1843200 291\n" - "1958400 84\n" - "2016000 6157\n", + .content = "652800 36826\n" + "1036800 525\n" + "1401600 1882\n" + "1689600 426\n" + "1843200 291\n" + "1958400 84\n" + "2016000 6157\n", }, { .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/total_trans", @@ -1603,14 +1592,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/time_in_state", .size = 86, - .content = - "652800 37076\n" - "1036800 525\n" - "1401600 1882\n" - "1689600 426\n" - "1843200 291\n" - "1958400 84\n" - "2016000 6157\n", + .content = "652800 37076\n" + "1036800 525\n" + "1401600 1882\n" + "1689600 426\n" + "1843200 291\n" + "1958400 84\n" + "2016000 6157\n", }, { .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/total_trans", @@ -1710,14 +1698,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/time_in_state", .size = 86, - .content = - "652800 37327\n" - "1036800 525\n" - "1401600 1882\n" - "1689600 426\n" - "1843200 291\n" - "1958400 84\n" - "2016000 6157\n", + .content = "652800 37327\n" + "1036800 525\n" + "1401600 1882\n" + "1689600 426\n" + "1843200 291\n" + "1958400 84\n" + "2016000 6157\n", }, { .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/total_trans", @@ -1817,14 +1804,13 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/time_in_state", .size = 86, - .content = - "652800 37576\n" - "1036800 525\n" - "1401600 1882\n" - "1689600 426\n" - "1843200 291\n" - "1958400 84\n" - "2016000 6157\n", + .content = "652800 37576\n" + "1036800 525\n" + "1401600 1882\n" + "1689600 426\n" + "1843200 291\n" + "1958400 84\n" + "2016000 6157\n", }, { .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/total_trans", @@ -1861,7 +1847,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "7\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -3917,6 +3903,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.driver.status", .value = "ok", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/xperia-c4-dual.cc b/test/mock/xperia-c4-dual.cc index 20248767..298da902 100644 --- a/test/mock/xperia-c4-dual.cc +++ b/test/mock/xperia-c4-dual.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(8, cpuinfo_get_processors_count()); @@ -274,8 +273,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("MediaTek MT6752", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "MediaTek MT6752", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -317,59 +318,59 @@ TEST(PACKAGES, cluster_count) { } TEST(ISA, thumb) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); +#endif } TEST(ISA, thumb2) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_thumb2()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_thumb2()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); +#endif } TEST(ISA, armv5e) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v5e()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v5e()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); +#endif } TEST(ISA, armv6) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); +#endif } TEST(ISA, armv6k) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v6k()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v6k()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); +#endif } TEST(ISA, armv7) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); +#endif } TEST(ISA, armv7mp) { - #if CPUINFO_ARCH_ARM - ASSERT_TRUE(cpuinfo_has_arm_v7mp()); - #elif CPUINFO_ARCH_ARM64 - ASSERT_FALSE(cpuinfo_has_arm_v7mp()); - #endif +#if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); +#elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); +#endif } TEST(ISA, idiv) { @@ -453,43 +454,43 @@ TEST(ISA, fcma) { } TEST(ISA, aes) { - #if CPUINFO_ARCH_ARM64 - ASSERT_TRUE(cpuinfo_has_arm_aes()); - #elif CPUINFO_ARCH_ARM - ASSERT_FALSE(cpuinfo_has_arm_aes()); - #endif +#if CPUINFO_ARCH_ARM64 + ASSERT_TRUE(cpuinfo_has_arm_aes()); +#elif CPUINFO_ARCH_ARM + ASSERT_FALSE(cpuinfo_has_arm_aes()); +#endif } TEST(ISA, sha1) { - #if CPUINFO_ARCH_ARM64 - ASSERT_TRUE(cpuinfo_has_arm_sha1()); - #elif CPUINFO_ARCH_ARM - ASSERT_FALSE(cpuinfo_has_arm_sha1()); - #endif +#if CPUINFO_ARCH_ARM64 + ASSERT_TRUE(cpuinfo_has_arm_sha1()); +#elif CPUINFO_ARCH_ARM + ASSERT_FALSE(cpuinfo_has_arm_sha1()); +#endif } TEST(ISA, sha2) { - #if CPUINFO_ARCH_ARM64 - ASSERT_TRUE(cpuinfo_has_arm_sha2()); - #elif CPUINFO_ARCH_ARM - ASSERT_FALSE(cpuinfo_has_arm_sha2()); - #endif +#if CPUINFO_ARCH_ARM64 + ASSERT_TRUE(cpuinfo_has_arm_sha2()); +#elif CPUINFO_ARCH_ARM + ASSERT_FALSE(cpuinfo_has_arm_sha2()); +#endif } TEST(ISA, pmull) { - #if CPUINFO_ARCH_ARM64 - ASSERT_TRUE(cpuinfo_has_arm_pmull()); - #elif CPUINFO_ARCH_ARM - ASSERT_FALSE(cpuinfo_has_arm_pmull()); - #endif +#if CPUINFO_ARCH_ARM64 + ASSERT_TRUE(cpuinfo_has_arm_pmull()); +#elif CPUINFO_ARCH_ARM + ASSERT_FALSE(cpuinfo_has_arm_pmull()); +#endif } TEST(ISA, crc32) { - #if CPUINFO_ARCH_ARM64 - ASSERT_TRUE(cpuinfo_has_arm_crc32()); - #elif CPUINFO_ARCH_ARM - ASSERT_FALSE(cpuinfo_has_arm_crc32()); - #endif +#if CPUINFO_ARCH_ARM64 + ASSERT_TRUE(cpuinfo_has_arm_crc32()); +#elif CPUINFO_ARCH_ARM + ASSERT_FALSE(cpuinfo_has_arm_crc32()); +#endif } TEST(L1I, count) { @@ -514,8 +515,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -566,8 +569,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -618,8 +623,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/xperia-c4-dual.h b/test/mock/xperia-c4-dual.h index fe84a1fc..de410408 100644 --- a/test/mock/xperia-c4-dual.h +++ b/test/mock/xperia-c4-dual.h @@ -3,18 +3,17 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 243, - .content = - "Processor\t: AArch64 Processor rev 2 (aarch64)\n" - "processor\t: 0\n" - "BogoMIPS\t: 26.00\n" - "Features\t: fp asimd aes pmull sha1 sha2 crc32\n" - "CPU implementer\t: 0x41\n" - "CPU architecture: AArch64\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0xd03\n" - "CPU revision\t: 2\n" - "\n" - "Hardware\t: MT6752\n", + .content = "Processor\t: AArch64 Processor rev 2 (aarch64)\n" + "processor\t: 0\n" + "BogoMIPS\t: 26.00\n" + "Features\t: fp asimd aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: AArch64\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0xd03\n" + "CPU revision\t: 2\n" + "\n" + "Hardware\t: MT6752\n", }, #elif CPUINFO_ARCH_ARM { @@ -363,16 +362,15 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpufreq/all_time_in_state", .size = 172, - .content = - "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\t\n" - "468000\t\t2351\t\t\n" - "702000\t\t538\t\t\n" - "936000\t\t104\t\t\n" - "1170000\t\t9954\t\t\n" - "1287000\t\t47\t\t\n" - "1417000\t\t24\t\t\n" - "1560000\t\t48\t\t\n" - "1690000\t\t4478\t\t\n", + .content = "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\tcpu4\t\tcpu5\t\tcpu6\t\tcpu7\t\t\n" + "468000\t\t2351\t\t\n" + "702000\t\t538\t\t\n" + "936000\t\t104\t\t\n" + "1170000\t\t9954\t\t\n" + "1287000\t\t47\t\t\n" + "1417000\t\t24\t\t\n" + "1560000\t\t48\t\t\n" + "1690000\t\t4478\t\t\n", }, { .path = "/sys/devices/system/cpu/cputopo/big_cpumask", @@ -382,11 +380,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cputopo/glbinfo", .size = 70, - .content = - "big/little arch: no\n" - "big/little cpumask:0/ff\n" - "nr_cups: 8\n" - "nr_clusters: 2\n", + .content = "big/little arch: no\n" + "big/little cpumask:0/ff\n" + "nr_cups: 8\n" + "nr_clusters: 2\n", }, { .path = "/sys/devices/system/cpu/cputopo/is_big_little", @@ -466,15 +463,14 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 93, - .content = - "1690000 4496\n" - "1560000 48\n" - "1417000 24\n" - "1287000 47\n" - "1170000 9954\n" - "936000 104\n" - "702000 538\n" - "468000 2479\n", + .content = "1690000 4496\n" + "1560000 48\n" + "1417000 24\n" + "1287000 47\n" + "1170000 9954\n" + "936000 104\n" + "702000 538\n" + "468000 2479\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -526,7 +522,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "0\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -2350,6 +2346,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.wfd.security.image", .value = "1", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/xperia-sl.cc b/test/mock/xperia-sl.cc index 21b06189..d9b75e25 100644 --- a/test/mock/xperia-sl.cc +++ b/test/mock/xperia-sl.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(2, cpuinfo_get_processors_count()); @@ -208,8 +207,10 @@ TEST(PACKAGES, count) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Qualcomm MSM8660", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Qualcomm MSM8660", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -400,8 +401,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -452,8 +455,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -492,9 +497,7 @@ TEST(L2, non_null) { TEST(L2, size) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - switch (i) { - ASSERT_EQ(512 * 1024, cpuinfo_get_l2_cache(i)->size); - } + switch (i) { ASSERT_EQ(512 * 1024, cpuinfo_get_l2_cache(i)->size); } } } @@ -506,8 +509,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/xperia-sl.h b/test/mock/xperia-sl.h index efcbacc2..a244f7e2 100644 --- a/test/mock/xperia-sl.h +++ b/test/mock/xperia-sl.h @@ -2,21 +2,20 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/proc/cpuinfo", .size = 287, - .content = - "Processor\t: ARMv7 Processor rev 4 (v7l)\n" - "processor\t: 0\n" - "BogoMIPS\t: 13.52\n" - "\n" - "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls \n" - "CPU implementer\t: 0x51\n" - "CPU architecture: 7\n" - "CPU variant\t: 0x0\n" - "CPU part\t: 0x02d\n" - "CPU revision\t: 4\n" - "\n" - "Hardware\t: fuji\n" - "Revision\t: 0000\n" - "Serial\t\t: 0000000000000000\n", + .content = "Processor\t: ARMv7 Processor rev 4 (v7l)\n" + "processor\t: 0\n" + "BogoMIPS\t: 13.52\n" + "\n" + "Features\t: swp half thumb fastmult vfp edsp neon vfpv3 tls \n" + "CPU implementer\t: 0x51\n" + "CPU architecture: 7\n" + "CPU variant\t: 0x0\n" + "CPU part\t: 0x02d\n" + "CPU revision\t: 4\n" + "\n" + "Hardware\t: fuji\n" + "Revision\t: 0000\n" + "Serial\t\t: 0000000000000000\n", }, { .path = "/system/build.prop", @@ -301,7 +300,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies", .size = 196, - .content = "192000 384000 432000 486000 540000 594000 648000 702000 756000 810000 864000 918000 972000 1026000 1080000 1134000 1188000 1242000 1296000 1350000 1404000 1458000 1512000 1566000 1620000 1674000 \n", + .content = + "192000 384000 432000 486000 540000 594000 648000 702000 756000 810000 864000 918000 972000 1026000 1080000 1134000 1188000 1242000 1296000 1350000 1404000 1458000 1512000 1566000 1620000 1674000 \n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors", @@ -336,33 +336,32 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 277, - .content = - "192000 1826\n" - "384000 33027\n" - "432000 82\n" - "486000 65\n" - "540000 38\n" - "594000 34\n" - "648000 26\n" - "702000 37\n" - "756000 30\n" - "810000 0\n" - "864000 10\n" - "918000 5\n" - "972000 34\n" - "1026000 39\n" - "1080000 13\n" - "1134000 16\n" - "1188000 5\n" - "1242000 35\n" - "1296000 15\n" - "1350000 17\n" - "1404000 29\n" - "1458000 16\n" - "1512000 69\n" - "1566000 42\n" - "1620000 57\n" - "1674000 6928\n", + .content = "192000 1826\n" + "384000 33027\n" + "432000 82\n" + "486000 65\n" + "540000 38\n" + "594000 34\n" + "648000 26\n" + "702000 37\n" + "756000 30\n" + "810000 0\n" + "864000 10\n" + "918000 5\n" + "972000 34\n" + "1026000 39\n" + "1080000 13\n" + "1134000 16\n" + "1188000 5\n" + "1242000 35\n" + "1296000 15\n" + "1350000 17\n" + "1404000 29\n" + "1458000 16\n" + "1512000 69\n" + "1566000 42\n" + "1620000 57\n" + "1674000 6928\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -399,7 +398,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "0\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ struct cpuinfo_mock_property properties[] = { @@ -1419,6 +1418,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wifi.supplicant_scan_interval", .value = "15", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/zenfone-2.cc b/test/mock/zenfone-2.cc index 62c43a86..4682cd6b 100644 --- a/test/mock/zenfone-2.cc +++ b/test/mock/zenfone-2.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(4, cpuinfo_get_processors_count()); @@ -212,8 +211,10 @@ TEST(PACKAGES, non_null) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Intel Atom Z3580", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Intel Atom Z3580", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -536,8 +537,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -588,8 +591,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -640,8 +645,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/zenfone-2.h b/test/mock/zenfone-2.h index 9fcf3fa0..26444d94 100644 --- a/test/mock/zenfone-2.h +++ b/test/mock/zenfone-2.h @@ -174,1358 +174,1361 @@ struct cpuinfo_mock_cpuid cpuid_dump[] = { .edx = 0x00000000, }, }; -struct cpuinfo_mock_file filesystem[] = { - { - .path = "/proc/cpuinfo", - .size = 3682, - .content = - "processor\t: 0\n" - "vendor_id\t: GenuineIntel\n" - "cpu family\t: 6\n" - "model\t\t: 90\n" - "model name\t: Intel(R) Atom(TM) CPU Z3580 @ 1.33GHz\n" - "stepping\t: 0\n" - "microcode\t: 0x38\n" - "cpu MHz\t\t: 1333.000\n" - "cache size\t: 1024 KB\n" - "physical id\t: 0\n" - "siblings\t: 4\n" - "core id\t\t: 0\n" - "cpu cores\t: 4\n" - "apicid\t\t: 0\n" - "initial apicid\t: 0\n" - "fpu\t\t: yes\n" - "fpu_exception\t: yes\n" - "cpuid level\t: 11\n" - "wp\t\t: yes\n" - "flags\t\t: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 movbe popcnt tsc_deadline_timer aes rdrand lahf_lm 3dnowprefetch ida arat epb dtherm tpr_shadow vnmi flexpriority ept vpid tsc_adjust smep erms\n" - "bogomips\t: 2662.40\n" - "clflush size\t: 64\n" - "cache_alignment\t: 64\n" - "address sizes\t: 36 bits physical, 48 bits virtual\n" - "power management:\n" - "\n" - "processor\t: 1\n" - "vendor_id\t: GenuineIntel\n" - "cpu family\t: 6\n" - "model\t\t: 90\n" - "model name\t: Intel(R) Atom(TM) CPU Z3580 @ 1.33GHz\n" - "stepping\t: 0\n" - "microcode\t: 0x38\n" - "cpu MHz\t\t: 1333.000\n" - "cache size\t: 1024 KB\n" - "physical id\t: 0\n" - "siblings\t: 4\n" - "core id\t\t: 1\n" - "cpu cores\t: 4\n" - "apicid\t\t: 2\n" - "initial apicid\t: 2\n" - "fpu\t\t: yes\n" - "fpu_exception\t: yes\n" - "cpuid level\t: 11\n" - "wp\t\t: yes\n" - "flags\t\t: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 movbe popcnt tsc_deadline_timer aes rdrand lahf_lm 3dnowprefetch ida arat epb dtherm tpr_shadow vnmi flexpriority ept vpid tsc_adjust smep erms\n" - "bogomips\t: 2662.40\n" - "clflush size\t: 64\n" - "cache_alignment\t: 64\n" - "address sizes\t: 36 bits physical, 48 bits virtual\n" - "power management:\n" - "\n" - "processor\t: 2\n" - "vendor_id\t: GenuineIntel\n" - "cpu family\t: 6\n" - "model\t\t: 90\n" - "model name\t: Intel(R) Atom(TM) CPU Z3580 @ 1.33GHz\n" - "stepping\t: 0\n" - "microcode\t: 0x38\n" - "cpu MHz\t\t: 500.000\n" - "cache size\t: 1024 KB\n" - "physical id\t: 0\n" - "siblings\t: 4\n" - "core id\t\t: 2\n" - "cpu cores\t: 4\n" - "apicid\t\t: 4\n" - "initial apicid\t: 4\n" - "fpu\t\t: yes\n" - "fpu_exception\t: yes\n" - "cpuid level\t: 11\n" - "wp\t\t: yes\n" - "flags\t\t: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 movbe popcnt tsc_deadline_timer aes rdrand lahf_lm 3dnowprefetch ida arat epb dtherm tpr_shadow vnmi flexpriority ept vpid tsc_adjust smep erms\n" - "bogomips\t: 2662.40\n" - "clflush size\t: 64\n" - "cache_alignment\t: 64\n" - "address sizes\t: 36 bits physical, 48 bits virtual\n" - "power management:\n" - "\n" - "processor\t: 3\n" - "vendor_id\t: GenuineIntel\n" - "cpu family\t: 6\n" - "model\t\t: 90\n" - "model name\t: Intel(R) Atom(TM) CPU Z3580 @ 1.33GHz\n" - "stepping\t: 0\n" - "microcode\t: 0x38\n" - "cpu MHz\t\t: 500.000\n" - "cache size\t: 1024 KB\n" - "physical id\t: 0\n" - "siblings\t: 4\n" - "core id\t\t: 3\n" - "cpu cores\t: 4\n" - "apicid\t\t: 6\n" - "initial apicid\t: 6\n" - "fpu\t\t: yes\n" - "fpu_exception\t: yes\n" - "cpuid level\t: 11\n" - "wp\t\t: yes\n" - "flags\t\t: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 movbe popcnt tsc_deadline_timer aes rdrand lahf_lm 3dnowprefetch ida arat epb dtherm tpr_shadow vnmi flexpriority ept vpid tsc_adjust smep erms\n" - "bogomips\t: 2662.40\n" - "clflush size\t: 64\n" - "cache_alignment\t: 64\n" - "address sizes\t: 36 bits physical, 48 bits virtual\n" - "power management:\n" - "\n", - }, - { - .path = "/system/build.prop", - .size = 3983, - .content = - "\n" - "# begin build properties\n" - "# autogenerated by buildinfo.sh\n" - "ro.build.id=MMB29P\n" - "ro.build.display.id=MMB29P.WW-ASUS_Z00A-4.21.40.352_20170623_7598_user\n" - "ro.build.version.incremental=WW_Z00A-WW_4.21.40.352_20170623_7598_user_rel-user-20170623\n" - "ro.build.version.sdk=23\n" - "ro.build.version.preview_sdk=0\n" - "ro.build.version.codename=REL\n" - "ro.build.version.all_codenames=REL\n" - "ro.build.version.release=6.0.1\n" - "ro.build.version.houdini=6.1.1a\n" - "ro.build.version.security_patch=2017-05-01\n" - "ro.build.version.base_os=\n" - "ro.build.date=xE4xBAx94 6xE6x9Cx88 23 00:08:45 CST 2017\n" - "ro.build.date.utc=1498147725\n" - "ro.build.type=user\n" - "ro.build.user=jenkins\n" - "ro.build.host=fdc-01-jenkins\n" - "ro.build.tags=release-keys\n" - "ro.build.flavor=asusmofd_fhd-user\n" - "ro.product.model=ASUS_Z00A\n" - "ro.product.brand=asus\n" - "ro.product.name=WW_Z00A\n" - "ro.product.device=Z00A\n" - "ro.product.board=moorefield\n" - "# ro.product.cpu.abi and ro.product.cpu.abi2 are obsolete,\n" - "# use ro.product.cpu.abilist instead.\n" - "ro.product.cpu.abi=x86\n" - "ro.product.cpu.abilist=x86,armeabi-v7a,armeabi\n" - "ro.product.cpu.abilist32=x86,armeabi-v7a,armeabi\n" - "ro.product.cpu.abilist64=\n" - "ro.product.first_api_level=21\n" - "ro.product.manufacturer=asus\n" - "ro.product.locale=en-US\n" - "ro.build.asus.sku=WW\n" - "ro.build.asus.version=4.21.40.352\n" - "ro.wifi.channels=\n" - "ro.board.platform=moorefield\n" - "# ro.build.product is obsolete; use ro.product.device\n" - "ro.build.product=mofd_v1\n" - "# Do not try to parse description, fingerprint, or thumbprint\n" - "ro.build.description=asusmofd_fhd-user 6.0.1 MMB29P 4.21.40.352_20170623_7598_user release-keys\n" - "ro.build.fingerprint=asus/WW_Z00A/Z00A:6.0.1/MMB29P/4.21.40.352_20170623_7598_user:user/release-keys\n" - "ro.build.characteristics=nosdcard\n" - "ro.build.csc.version=WW_ZE551ML_4.21.40.352_20170623\n" - "ro.camera.sound.forced=0\n" - "# end build properties\n" - "\n" - "#\n" - "# ADDITIONAL_BUILD_PROPERTIES\n" - "#\n" - "ro.build.app.version=060020736_201603210001\n" - "ro.asus.ui=1.0\n" - "ro.ril.ecclist=112,911\n" - "ro.com.google.clientidbase=android-asus\n" - "ro.com.google.clientidbase.ms=android-asus\n" - "ro.com.google.clientidbase.am=android-asus\n" - "ro.com.google.clientidbase.gmm=android-asus\n" - "ro.com.google.clientidbase.yt=android-asus\n" - "ro.spid.gps.tty=ttyMFD2\n" - "ro.spid.gps.FrqPlan=FRQ_PLAN_26MHZ_2PPM\n" - "ro.spid.gps.RfType=GL_RF_47531_BRCM\n" - "hwc.video.extmode.enable=0\n" - "ro.nfc.conf=mofd-ffd2-a\n" - "ro.nfc.clk=pll\n" - "keyguard.no_require_sim=true\n" - "ro.com.android.dateformat=MM-dd-yyyy\n" - "ro.carrier=unknown\n" - "ro.telephony.default_network=9\n" - "ro.asus.network.types=2\n" - "persist.tel.hot_swap.support=true\n" - "ro.asus.phone.ipcall=0\n" - "ro.asus.phone.sipcall=1\n" - "drm.service.enabled=true\n" - "ro.blankphone_id=1\n" - "ro.dalvik.vm.isa.arm=x86\n" - "ro.enable.native.bridge.exec=1\n" - "dalvik.vm.heapstartsize=16m\n" - "dalvik.vm.heapgrowthlimit=256m\n" - "dalvik.vm.heapsize=512m\n" - "dalvik.vm.heaptargetutilization=0.75\n" - "dalvik.vm.heapminfree=512k\n" - "dalvik.vm.heapmaxfree=8m\n" - "ro.hwui.texture_cache_size=72\n" - "ro.hwui.layer_cache_size=48\n" - "ro.hwui.r_buffer_cache_size=8\n" - "ro.hwui.gradient_cache_size=1\n" - "ro.hwui.path_cache_size=32\n" - "ro.hwui.drop_shadow_cache_size=6\n" - "ro.hwui.texture_cache_flushrate=0.4\n" - "ro.hwui.text_small_cache_width=1024\n" - "ro.hwui.text_small_cache_height=1024\n" - "ro.hwui.text_large_cache_width=2048\n" - "ro.hwui.text_large_cache_height=1024\n" - "ro.camera.sound.forced=0\n" - "ro.config.ringtone=Festival.ogg\n" - "ro.config.notification_sound=NewMessage.ogg\n" - "ro.config.newmail_sound=NewMail.ogg\n" - "ro.config.sentmail_sound=SentMail.ogg\n" - "ro.config.calendaralert_sound=CalendarEvent.ogg\n" - "ro.config.alarm_alert=BusyBugs.ogg\n" - "ro.additionalbutton.operation=0\n" - "ro.setupwizard.mode=OPTIONAL\n" - "ro.com.google.gmsversion=6.0_r11\n" - "ro.ril.status.polling.enable=0\n" - "rild.libpath=/system/lib/librapid-ril-core.so\n" - "bt.hfp.WideBandSpeechEnabled=true\n" - "gps.version.driver=66.19.20.275658\n" - "wifi.version.driver=6.37.45.11\n" - "bt.version.driver=V10.00.02\n" - "persist.sys.dalvik.vm.lib.2=libart\n" - "dalvik.vm.isa.x86.variant=x86\n" - "dalvik.vm.isa.x86.features=default\n" - "net.bt.name=Android\n" - "dalvik.vm.stack-trace-file=/data/anr/traces.txt\n" - "ro.config.hwrlib=T9_x86\n" - "ro.config.xt9ime.max_subtype=7\n" - "ro.ime.lowmemory=false\n" - "ro.intel.corp.email=1\n" - "ro.expect.recovery_id=0x9c0e1ee4a82056edf9114ab36dc033fd65faac41000000000000000000000000\n" - "\n" - "\n", - }, - { - .path = "/sys/devices/system/cpu/kernel_max", - .size = 2, - .content = "3\n", - }, - { - .path = "/sys/devices/system/cpu/possible", - .size = 4, - .content = "0-3\n", - }, - { - .path = "/sys/devices/system/cpu/present", - .size = 4, - .content = "0-3\n", - }, - { - .path = "/sys/devices/system/cpu/online", - .size = 4, - .content = "0-3\n", - }, - { - .path = "/sys/devices/system/cpu/offline", - .size = 1, - .content = "\n", - }, - { - .path = "/sys/devices/system/cpu/modalias", - .size = 436, - .content = "x86cpu:vendor:0000:family:0006:model:005A:feature:,0000,0001,0002,0003,0004,0005,0006,0007,0008,0009,000B,000C,000D,000E,000F,0010,0011,0013,0015,0016,0017,0018,0019,001A,001B,001C,001D,001F,002B,0034,003B,003D,0068,006B,006C,006D,006F,0070,0072,0074,0076,0078,007C,0080,0081,0082,0083,0084,0085,0087,0088,0089,008D,008E,008F,0093,0094,0096,0097,0098,0099,009E,00C0,00C8,00E0,00E1,00E3,00E7,0100,0101,0102,0103,0104,0121,0127,0129,012D\n", - }, - { - .path = "/sys/devices/system/cpu/cpufreq/all_time_in_state", - .size = 769, - .content = - "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\t\n" - "500000\t\t4283894\t\t4283894\t\t4404405\t\t4404405\t\t\n" - "583000\t\t14933\t\t14933\t\t3589\t\t3589\t\t\n" - "666000\t\t3580\t\t3580\t\t1684\t\t1684\t\t\n" - "750000\t\t3550\t\t3550\t\t1120\t\t1120\t\t\n" - "833000\t\t1801\t\t1801\t\t912\t\t912\t\t\n" - "916000\t\t1745\t\t1745\t\t849\t\t849\t\t\n" - "1000000\t\t1321\t\t1321\t\t630\t\t630\t\t\n" - "1083000\t\t994\t\t994\t\t730\t\t730\t\t\n" - "1166000\t\t875\t\t875\t\t593\t\t593\t\t\n" - "1250000\t\t872\t\t872\t\t724\t\t724\t\t\n" - "1333000\t\t936\t\t936\t\t637\t\t637\t\t\n" - "1416000\t\t753\t\t753\t\t716\t\t716\t\t\n" - "1500000\t\t800\t\t800\t\t758\t\t758\t\t\n" - "1583000\t\t708\t\t708\t\t703\t\t703\t\t\n" - "1666000\t\t703\t\t703\t\t781\t\t781\t\t\n" - "1750000\t\t867\t\t867\t\t610\t\t610\t\t\n" - "1833000\t\t36252\t\t36252\t\t8354\t\t8354\t\t\n" - "1916000\t\t642\t\t642\t\t515\t\t515\t\t\n" - "2000000\t\t790\t\t790\t\t600\t\t600\t\t\n" - "2083000\t\t657\t\t657\t\t682\t\t682\t\t\n" - "2166000\t\t785\t\t785\t\t509\t\t509\t\t\n" - "2250000\t\t776\t\t776\t\t656\t\t656\t\t\n" - "2333000\t\t243140\t\t243140\t\t170617\t\t170617\t\t\n", - }, - { - .path = "/sys/devices/system/cpu/cpuidle/current_driver", - .size = 11, - .content = "intel_idle\n", - }, - { - .path = "/sys/devices/system/cpu/cpuidle/current_governor_ro", - .size = 5, - .content = "menu\n", - }, - { - .path = "/sys/devices/system/cpu/cpu0/cpufreq/affected_cpus", - .size = 4, - .content = "0 1\n", - }, - { - .path = "/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq", - .size = 8, - .content = "2333000\n", - }, - { - .path = "/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_min_freq", - .size = 7, - .content = "500000\n", - }, - { - .path = "/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_transition_latency", - .size = 7, - .content = "100000\n", - }, - { - .path = "/sys/devices/system/cpu/cpu0/cpufreq/related_cpus", - .size = 4, - .content = "0 1\n", - }, - { - .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies", - .size = 179, - .content = "2333000 2250000 2166000 2083000 2000000 1916000 1833000 1750000 1666000 1583000 1500000 1416000 1333000 1250000 1166000 1083000 1000000 916000 833000 750000 666000 583000 500000 \n", - }, - { - .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors", - .size = 44, - .content = "ondemand userspace interactive performance \n", - }, - { - .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq", - .size = 7, - .content = "500000\n", - }, - { - .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_driver", - .size = 12, - .content = "sfi-cpufreq\n", - }, - { - .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_governor", - .size = 12, - .content = "interactive\n", - }, - { - .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_min_freq", - .size = 7, - .content = "500000\n", - }, - { - .path = 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1083000: 28 0 0 0 0 0 6 0 0 0 0 0 0 7 26 0 21 14 11 ", - }, - { - .path = "/sys/devices/system/cpu/cpu0/topology/physical_package_id", - .size = 2, - .content = "0\n", - }, - { - .path = "/sys/devices/system/cpu/cpu0/topology/core_siblings_list", - .size = 4, - .content = "0-3\n", - }, - { - .path = "/sys/devices/system/cpu/cpu0/topology/core_siblings", - .size = 2, - .content = "f\n", - }, - { - .path = "/sys/devices/system/cpu/cpu0/topology/core_id", - .size = 2, - .content = "0\n", - }, - { - .path = "/sys/devices/system/cpu/cpu0/topology/thread_siblings_list", - .size = 2, - .content = "0\n", - }, - { - .path = "/sys/devices/system/cpu/cpu0/topology/thread_siblings", - .size = 2, - .content = "1\n", - }, - { - .path = "/sys/devices/system/cpu/cpu0/cache/index0/coherency_line_size", - .size = 3, - .content = "64\n", - }, - { - .path = "/sys/devices/system/cpu/cpu0/cache/index0/level", - .size = 2, - .content = "1\n", - }, - { - .path = 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"/sys/devices/system/cpu/cpu1/cache/index1/shared_cpu_list", - .size = 2, - .content = "1\n", - }, - { - .path = "/sys/devices/system/cpu/cpu1/cache/index1/shared_cpu_map", - .size = 2, - .content = "2\n", - }, - { - .path = "/sys/devices/system/cpu/cpu1/cache/index1/size", - .size = 4, - .content = "32K\n", - }, - { - .path = "/sys/devices/system/cpu/cpu1/cache/index1/type", - .size = 12, - .content = "Instruction\n", - }, - { - .path = "/sys/devices/system/cpu/cpu1/cache/index1/ways_of_associativity", - .size = 2, - .content = "8\n", - }, - { - .path = "/sys/devices/system/cpu/cpu1/cache/index2/coherency_line_size", - .size = 3, - .content = "64\n", - }, - { - .path = "/sys/devices/system/cpu/cpu1/cache/index2/level", - .size = 2, - .content = "2\n", - }, - { - .path = "/sys/devices/system/cpu/cpu1/cache/index2/number_of_sets", - .size = 5, - .content = "1024\n", - }, - { - .path = "/sys/devices/system/cpu/cpu1/cache/index2/shared_cpu_list", - .size = 4, - .content = "0-1\n", - }, - { - .path = "/sys/devices/system/cpu/cpu1/cache/index2/shared_cpu_map", - .size = 2, - .content = "3\n", - }, - { - .path = "/sys/devices/system/cpu/cpu1/cache/index2/size", - .size = 6, - .content = "1024K\n", - }, - { - .path = "/sys/devices/system/cpu/cpu1/cache/index2/type", - .size = 8, - .content = "Unified\n", - }, - { - .path = "/sys/devices/system/cpu/cpu1/cache/index2/ways_of_associativity", - .size = 3, - .content = "16\n", - }, - { - .path = "/sys/devices/system/cpu/cpu2/cpufreq/affected_cpus", - .size = 4, - .content = "2 3\n", - }, - { - .path = "/sys/devices/system/cpu/cpu2/cpufreq/cpuinfo_max_freq", - .size = 8, - .content = "2333000\n", - }, - { - .path = "/sys/devices/system/cpu/cpu2/cpufreq/cpuinfo_min_freq", - .size = 7, - .content = "500000\n", - }, - { - .path = "/sys/devices/system/cpu/cpu2/cpufreq/cpuinfo_transition_latency", - .size = 7, - .content = "100000\n", - }, - { - .path = "/sys/devices/system/cpu/cpu2/cpufreq/related_cpus", - .size = 4, - .content = "2 3\n", - }, - { - .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_frequencies", - .size = 179, - .content = "2333000 2250000 2166000 2083000 2000000 1916000 1833000 1750000 1666000 1583000 1500000 1416000 1333000 1250000 1166000 1083000 1000000 916000 833000 750000 666000 583000 500000 \n", - }, - { - .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_governors", - .size = 44, - .content = "ondemand userspace interactive performance \n", - }, - { - .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_cur_freq", - .size = 7, - .content = "500000\n", - }, - { - .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_driver", - .size = 12, - .content = "sfi-cpufreq\n", - }, - { - .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_governor", - .size = 12, - .content = "interactive\n", - }, - { - .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_min_freq", - .size = 7, - .content = "500000\n", - }, - { - .path = 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0 0 0 0 3 29 0 11 7 6 ", - }, - { - .path = "/sys/devices/system/cpu/cpu2/topology/physical_package_id", - .size = 2, - .content = "0\n", - }, - { - .path = "/sys/devices/system/cpu/cpu2/topology/core_siblings_list", - .size = 4, - .content = "0-3\n", - }, - { - .path = "/sys/devices/system/cpu/cpu2/topology/core_siblings", - .size = 2, - .content = "f\n", - }, - { - .path = "/sys/devices/system/cpu/cpu2/topology/core_id", - .size = 2, - .content = "2\n", - }, - { - .path = "/sys/devices/system/cpu/cpu2/topology/thread_siblings_list", - .size = 2, - .content = "2\n", - }, - { - .path = "/sys/devices/system/cpu/cpu2/topology/thread_siblings", - .size = 2, - .content = "4\n", - }, - { - .path = "/sys/devices/system/cpu/cpu2/cache/index0/coherency_line_size", - .size = 3, - .content = "64\n", - }, - { - .path = "/sys/devices/system/cpu/cpu2/cache/index0/level", - .size = 2, - .content = "1\n", - }, - { - .path = "/sys/devices/system/cpu/cpu2/cache/index0/number_of_sets", - .size = 3, - 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.content = "2\n", - }, - { - .path = "/sys/devices/system/cpu/cpu2/cache/index1/shared_cpu_map", - .size = 2, - .content = "4\n", - }, - { - .path = "/sys/devices/system/cpu/cpu2/cache/index1/size", - .size = 4, - .content = "32K\n", - }, - { - .path = "/sys/devices/system/cpu/cpu2/cache/index1/type", - .size = 12, - .content = "Instruction\n", - }, - { - .path = "/sys/devices/system/cpu/cpu2/cache/index1/ways_of_associativity", - .size = 2, - .content = "8\n", - }, - { - .path = "/sys/devices/system/cpu/cpu2/cache/index2/coherency_line_size", - .size = 3, - .content = "64\n", - }, - { - .path = "/sys/devices/system/cpu/cpu2/cache/index2/level", - .size = 2, - .content = "2\n", - }, - { - .path = "/sys/devices/system/cpu/cpu2/cache/index2/number_of_sets", - .size = 5, - .content = "1024\n", - }, - { - .path = "/sys/devices/system/cpu/cpu2/cache/index2/shared_cpu_list", - .size = 4, - .content = "2-3\n", - }, - { - .path = "/sys/devices/system/cpu/cpu2/cache/index2/shared_cpu_map", - .size = 2, - .content = "c\n", - }, - { - .path = "/sys/devices/system/cpu/cpu2/cache/index2/size", - .size = 6, - .content = "1024K\n", - }, - { - .path = "/sys/devices/system/cpu/cpu2/cache/index2/type", - .size = 8, - .content = "Unified\n", - }, - { - .path = "/sys/devices/system/cpu/cpu2/cache/index2/ways_of_associativity", - .size = 3, - .content = "16\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cpufreq/affected_cpus", - .size = 4, - .content = "2 3\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cpufreq/cpuinfo_max_freq", - .size = 8, - .content = "2333000\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cpufreq/cpuinfo_min_freq", - .size = 7, - .content = "500000\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cpufreq/cpuinfo_transition_latency", - .size = 7, - .content = "100000\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cpufreq/related_cpus", - .size = 4, - .content = "2 3\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_frequencies", - .size = 179, - .content = "2333000 2250000 2166000 2083000 2000000 1916000 1833000 1750000 1666000 1583000 1500000 1416000 1333000 1250000 1166000 1083000 1000000 916000 833000 750000 666000 583000 500000 \n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_governors", - .size = 44, - .content = "ondemand userspace interactive performance \n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_cur_freq", - .size = 7, - .content = "500000\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_driver", - .size = 12, - .content = "sfi-cpufreq\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_governor", - .size = 12, - .content = "interactive\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_min_freq", - .size = 7, - .content = "500000\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", - .size = 281, - .content = - "2333000 170617\n" - "2250000 656\n" - "2166000 509\n" - "2083000 682\n" - "2000000 600\n" - "1916000 515\n" - "1833000 8354\n" - "1750000 610\n" - "1666000 781\n" - "1583000 703\n" - "1500000 758\n" - "1416000 716\n" - "1333000 637\n" - "1250000 724\n" - "1166000 593\n" - "1083000 730\n" - "1000000 630\n" - "916000 849\n" - "833000 912\n" - "750000 1120\n" - "666000 1684\n" - "583000 3589\n" - "500000 4405273\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", - .size = 5, - .content = "7130\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/trans_table", - .size = 4095, - .content = - " From : To\n" - " : 2333000 2250000 2166000 2083000 2000000 1916000 1833000 1750000 1666000 1583000 1500000 1416000 1333000 1250000 1166000 1083000 1000000 916000 833000 750000 666000 583000 500000 \n" - " 2333000: 0 104 85 92 74 68 78 67 57 52 61 54 47 51 31 45 31 37 36 37 36 51 530 \n" - " 2250000: 114 0 6 7 3 6 2 2 4 2 0 0 5 0 1 1 0 1 1 1 0 0 5 \n" - " 2166000: 59 22 0 4 3 5 5 1 4 3 2 2 1 1 1 1 1 1 2 0 1 0 5 \n" - " 2083000: 62 21 18 0 5 4 6 4 4 3 3 1 1 3 2 2 1 4 0 1 1 1 4 \n" - " 2000000: 21 14 13 25 0 7 8 3 5 1 6 2 3 2 1 1 3 2 3 0 0 0 6 \n" - " 1916000: 33 0 2 20 20 0 6 2 3 4 2 3 2 3 2 1 2 0 0 1 2 0 15 \n" - " 1833000: 46 0 0 3 18 23 0 18 24 22 18 13 17 12 9 13 12 12 4 7 3 9 166 \n" - " 1750000: 35 0 0 0 3 9 37 0 6 4 2 4 4 4 4 3 1 1 1 3 0 1 15 \n" - " 1666000: 29 0 0 0 0 0 29 20 0 11 8 3 5 12 2 2 2 5 2 0 2 0 16 \n" - " 1583000: 31 0 0 0 0 0 5 19 18 0 7 9 5 3 6 5 3 5 4 1 2 0 15 \n" - " 1500000: 30 0 0 0 0 0 0 0 22 20 0 14 6 6 7 6 5 6 1 1 2 6 17 \n" - " 1416000: 42 0 0 0 0 0 3 0 0 16 23 0 5 14 2 5 1 6 7 2 3 1 19 \n" - " 1333000: 34 0 0 0 0 0 6 1 0 0 17 30 0 4 1 6 8 4 2 7 4 2 15 \n" - " 1250000: 27 0 0 0 0 0 4 0 0 0 0 14 27 0 11 7 6 5 4 4 5 4 20 \n" - " 1166000: 19 0 0 0 0 0 4 0 0 0 0 0 13 20 0 5 4 5 9 4 5 1 28 \n" - " 1083000: 20 0 0 0 0 0 4 0 0 0 0 0 0 3 29 0 11 7 6 ", - }, - { - .path = "/sys/devices/system/cpu/cpu3/topology/physical_package_id", - .size = 2, - .content = "0\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/topology/core_siblings_list", - .size = 4, - .content = "0-3\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/topology/core_siblings", - .size = 2, - .content = "f\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/topology/core_id", - .size = 2, - .content = "3\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/topology/thread_siblings_list", - .size = 2, - .content = "3\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/topology/thread_siblings", - .size = 2, - .content = "8\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cache/index0/coherency_line_size", - .size = 3, - .content = "64\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cache/index0/level", - .size = 2, - .content = "1\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cache/index0/number_of_sets", - .size = 3, - .content = "64\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cache/index0/shared_cpu_list", - .size = 2, - .content = "3\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cache/index0/shared_cpu_map", - .size = 2, - .content = "8\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cache/index0/size", - .size = 4, - .content = "24K\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cache/index0/type", - .size = 5, - .content = "Data\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cache/index0/ways_of_associativity", - .size = 2, - .content = "6\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cache/index1/coherency_line_size", - .size = 3, - .content = "64\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cache/index1/level", - .size = 2, - .content = "1\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cache/index1/number_of_sets", - .size = 3, - .content = "64\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cache/index1/shared_cpu_list", - .size = 2, - .content = "3\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cache/index1/shared_cpu_map", - .size = 2, - .content = "8\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cache/index1/size", - .size = 4, - .content = "32K\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cache/index1/type", - .size = 12, - .content = "Instruction\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cache/index1/ways_of_associativity", - .size = 2, - .content = "8\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cache/index2/coherency_line_size", - .size = 3, - .content = "64\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cache/index2/level", - .size = 2, - .content = "2\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cache/index2/number_of_sets", - .size = 5, - .content = "1024\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cache/index2/shared_cpu_list", - .size = 4, - .content = "2-3\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cache/index2/shared_cpu_map", - .size = 2, - .content = "c\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cache/index2/size", - .size = 6, - .content = "1024K\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cache/index2/type", - .size = 8, - .content = "Unified\n", - }, - { - .path = "/sys/devices/system/cpu/cpu3/cache/index2/ways_of_associativity", - .size = 3, - .content = "16\n", - }, - { NULL }, +struct cpuinfo_mock_file + filesystem + [] = + { + { + .path = "/proc/cpuinfo", + .size = 3682, + .content = + "processor\t: 0\n" + "vendor_id\t: GenuineIntel\n" + "cpu family\t: 6\n" + "model\t\t: 90\n" + "model name\t: Intel(R) Atom(TM) CPU Z3580 @ 1.33GHz\n" + "stepping\t: 0\n" + "microcode\t: 0x38\n" + "cpu MHz\t\t: 1333.000\n" + "cache size\t: 1024 KB\n" + "physical id\t: 0\n" + "siblings\t: 4\n" + "core id\t\t: 0\n" + "cpu cores\t: 4\n" + "apicid\t\t: 0\n" + "initial apicid\t: 0\n" + "fpu\t\t: yes\n" + "fpu_exception\t: yes\n" + "cpuid level\t: 11\n" + "wp\t\t: yes\n" + "flags\t\t: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 movbe popcnt tsc_deadline_timer aes rdrand lahf_lm 3dnowprefetch ida arat epb dtherm tpr_shadow vnmi flexpriority ept vpid tsc_adjust smep erms\n" + "bogomips\t: 2662.40\n" + "clflush size\t: 64\n" + "cache_alignment\t: 64\n" + "address sizes\t: 36 bits physical, 48 bits virtual\n" + "power management:\n" + "\n" + "processor\t: 1\n" + "vendor_id\t: GenuineIntel\n" + "cpu family\t: 6\n" + "model\t\t: 90\n" + "model name\t: Intel(R) Atom(TM) CPU Z3580 @ 1.33GHz\n" + "stepping\t: 0\n" + "microcode\t: 0x38\n" + "cpu MHz\t\t: 1333.000\n" + "cache size\t: 1024 KB\n" + "physical id\t: 0\n" + "siblings\t: 4\n" + "core id\t\t: 1\n" + "cpu cores\t: 4\n" + "apicid\t\t: 2\n" + "initial apicid\t: 2\n" + "fpu\t\t: yes\n" + "fpu_exception\t: yes\n" + "cpuid level\t: 11\n" + "wp\t\t: yes\n" + "flags\t\t: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 movbe popcnt tsc_deadline_timer aes rdrand lahf_lm 3dnowprefetch ida arat epb dtherm tpr_shadow vnmi flexpriority ept vpid tsc_adjust smep erms\n" + "bogomips\t: 2662.40\n" + "clflush size\t: 64\n" + "cache_alignment\t: 64\n" + "address sizes\t: 36 bits physical, 48 bits virtual\n" + "power management:\n" + "\n" + "processor\t: 2\n" + "vendor_id\t: GenuineIntel\n" + "cpu family\t: 6\n" + "model\t\t: 90\n" + "model name\t: Intel(R) Atom(TM) CPU Z3580 @ 1.33GHz\n" + "stepping\t: 0\n" + "microcode\t: 0x38\n" + "cpu MHz\t\t: 500.000\n" + "cache size\t: 1024 KB\n" + "physical id\t: 0\n" + "siblings\t: 4\n" + "core id\t\t: 2\n" + "cpu cores\t: 4\n" + "apicid\t\t: 4\n" + "initial apicid\t: 4\n" + "fpu\t\t: yes\n" + "fpu_exception\t: yes\n" + "cpuid level\t: 11\n" + "wp\t\t: yes\n" + "flags\t\t: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 movbe popcnt tsc_deadline_timer aes rdrand lahf_lm 3dnowprefetch ida arat epb dtherm tpr_shadow vnmi flexpriority ept vpid tsc_adjust smep erms\n" + "bogomips\t: 2662.40\n" + "clflush size\t: 64\n" + "cache_alignment\t: 64\n" + "address sizes\t: 36 bits physical, 48 bits virtual\n" + "power management:\n" + "\n" + "processor\t: 3\n" + "vendor_id\t: GenuineIntel\n" + "cpu family\t: 6\n" + "model\t\t: 90\n" + "model name\t: Intel(R) Atom(TM) CPU Z3580 @ 1.33GHz\n" + "stepping\t: 0\n" + "microcode\t: 0x38\n" + "cpu MHz\t\t: 500.000\n" + "cache size\t: 1024 KB\n" + "physical id\t: 0\n" + "siblings\t: 4\n" + "core id\t\t: 3\n" + "cpu cores\t: 4\n" + "apicid\t\t: 6\n" + "initial apicid\t: 6\n" + "fpu\t\t: yes\n" + "fpu_exception\t: yes\n" + "cpuid level\t: 11\n" + "wp\t\t: yes\n" + "flags\t\t: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 movbe popcnt tsc_deadline_timer aes rdrand lahf_lm 3dnowprefetch ida arat epb dtherm tpr_shadow vnmi flexpriority ept vpid tsc_adjust smep erms\n" + "bogomips\t: 2662.40\n" + "clflush size\t: 64\n" + "cache_alignment\t: 64\n" + "address sizes\t: 36 bits physical, 48 bits virtual\n" + "power management:\n" + "\n", + }, + { + .path = "/system/build.prop", + .size = 3983, + .content = + "\n" + "# begin build properties\n" + "# autogenerated by buildinfo.sh\n" + "ro.build.id=MMB29P\n" + "ro.build.display.id=MMB29P.WW-ASUS_Z00A-4.21.40.352_20170623_7598_user\n" + "ro.build.version.incremental=WW_Z00A-WW_4.21.40.352_20170623_7598_user_rel-user-20170623\n" + "ro.build.version.sdk=23\n" + "ro.build.version.preview_sdk=0\n" + "ro.build.version.codename=REL\n" + "ro.build.version.all_codenames=REL\n" + "ro.build.version.release=6.0.1\n" + "ro.build.version.houdini=6.1.1a\n" + "ro.build.version.security_patch=2017-05-01\n" + "ro.build.version.base_os=\n" + "ro.build.date=xE4xBAx94 6xE6x9Cx88 23 00:08:45 CST 2017\n" + "ro.build.date.utc=1498147725\n" + "ro.build.type=user\n" + "ro.build.user=jenkins\n" + "ro.build.host=fdc-01-jenkins\n" + "ro.build.tags=release-keys\n" + "ro.build.flavor=asusmofd_fhd-user\n" + "ro.product.model=ASUS_Z00A\n" + "ro.product.brand=asus\n" + "ro.product.name=WW_Z00A\n" + "ro.product.device=Z00A\n" + "ro.product.board=moorefield\n" + "# ro.product.cpu.abi and ro.product.cpu.abi2 are obsolete,\n" + "# use ro.product.cpu.abilist instead.\n" + "ro.product.cpu.abi=x86\n" + "ro.product.cpu.abilist=x86,armeabi-v7a,armeabi\n" + "ro.product.cpu.abilist32=x86,armeabi-v7a,armeabi\n" + "ro.product.cpu.abilist64=\n" + "ro.product.first_api_level=21\n" + "ro.product.manufacturer=asus\n" + "ro.product.locale=en-US\n" + "ro.build.asus.sku=WW\n" + "ro.build.asus.version=4.21.40.352\n" + "ro.wifi.channels=\n" + "ro.board.platform=moorefield\n" + "# ro.build.product is obsolete; use ro.product.device\n" + "ro.build.product=mofd_v1\n" + "# Do not try to parse description, fingerprint, or thumbprint\n" + "ro.build.description=asusmofd_fhd-user 6.0.1 MMB29P 4.21.40.352_20170623_7598_user release-keys\n" + "ro.build.fingerprint=asus/WW_Z00A/Z00A:6.0.1/MMB29P/4.21.40.352_20170623_7598_user:user/release-keys\n" + "ro.build.characteristics=nosdcard\n" + "ro.build.csc.version=WW_ZE551ML_4.21.40.352_20170623\n" + "ro.camera.sound.forced=0\n" + "# end build properties\n" + "\n" + "#\n" + "# ADDITIONAL_BUILD_PROPERTIES\n" + "#\n" + "ro.build.app.version=060020736_201603210001\n" + "ro.asus.ui=1.0\n" + "ro.ril.ecclist=112,911\n" + "ro.com.google.clientidbase=android-asus\n" + "ro.com.google.clientidbase.ms=android-asus\n" + "ro.com.google.clientidbase.am=android-asus\n" + "ro.com.google.clientidbase.gmm=android-asus\n" + "ro.com.google.clientidbase.yt=android-asus\n" + "ro.spid.gps.tty=ttyMFD2\n" + "ro.spid.gps.FrqPlan=FRQ_PLAN_26MHZ_2PPM\n" + "ro.spid.gps.RfType=GL_RF_47531_BRCM\n" + "hwc.video.extmode.enable=0\n" + "ro.nfc.conf=mofd-ffd2-a\n" + "ro.nfc.clk=pll\n" + "keyguard.no_require_sim=true\n" + "ro.com.android.dateformat=MM-dd-yyyy\n" + "ro.carrier=unknown\n" + "ro.telephony.default_network=9\n" + "ro.asus.network.types=2\n" + "persist.tel.hot_swap.support=true\n" + "ro.asus.phone.ipcall=0\n" + "ro.asus.phone.sipcall=1\n" + "drm.service.enabled=true\n" + "ro.blankphone_id=1\n" + "ro.dalvik.vm.isa.arm=x86\n" + "ro.enable.native.bridge.exec=1\n" + "dalvik.vm.heapstartsize=16m\n" + "dalvik.vm.heapgrowthlimit=256m\n" + "dalvik.vm.heapsize=512m\n" + "dalvik.vm.heaptargetutilization=0.75\n" + "dalvik.vm.heapminfree=512k\n" + "dalvik.vm.heapmaxfree=8m\n" + "ro.hwui.texture_cache_size=72\n" + "ro.hwui.layer_cache_size=48\n" + "ro.hwui.r_buffer_cache_size=8\n" + "ro.hwui.gradient_cache_size=1\n" + "ro.hwui.path_cache_size=32\n" + "ro.hwui.drop_shadow_cache_size=6\n" + "ro.hwui.texture_cache_flushrate=0.4\n" + "ro.hwui.text_small_cache_width=1024\n" + "ro.hwui.text_small_cache_height=1024\n" + "ro.hwui.text_large_cache_width=2048\n" + "ro.hwui.text_large_cache_height=1024\n" + "ro.camera.sound.forced=0\n" + "ro.config.ringtone=Festival.ogg\n" + "ro.config.notification_sound=NewMessage.ogg\n" + "ro.config.newmail_sound=NewMail.ogg\n" + "ro.config.sentmail_sound=SentMail.ogg\n" + "ro.config.calendaralert_sound=CalendarEvent.ogg\n" + "ro.config.alarm_alert=BusyBugs.ogg\n" + "ro.additionalbutton.operation=0\n" + "ro.setupwizard.mode=OPTIONAL\n" + "ro.com.google.gmsversion=6.0_r11\n" + "ro.ril.status.polling.enable=0\n" + "rild.libpath=/system/lib/librapid-ril-core.so\n" + "bt.hfp.WideBandSpeechEnabled=true\n" + "gps.version.driver=66.19.20.275658\n" + "wifi.version.driver=6.37.45.11\n" + "bt.version.driver=V10.00.02\n" + "persist.sys.dalvik.vm.lib.2=libart\n" + "dalvik.vm.isa.x86.variant=x86\n" + "dalvik.vm.isa.x86.features=default\n" + "net.bt.name=Android\n" + "dalvik.vm.stack-trace-file=/data/anr/traces.txt\n" + "ro.config.hwrlib=T9_x86\n" + "ro.config.xt9ime.max_subtype=7\n" + "ro.ime.lowmemory=false\n" + "ro.intel.corp.email=1\n" + "ro.expect.recovery_id=0x9c0e1ee4a82056edf9114ab36dc033fd65faac41000000000000000000000000\n" + "\n" + "\n", + }, + { + .path = "/sys/devices/system/cpu/kernel_max", + .size = 2, + .content = "3\n", + }, + { + .path = "/sys/devices/system/cpu/possible", + .size = 4, + .content = "0-3\n", + }, + { + .path = "/sys/devices/system/cpu/present", + .size = 4, + .content = "0-3\n", + }, + { + .path = "/sys/devices/system/cpu/online", + .size = 4, + .content = "0-3\n", + }, + { + .path = "/sys/devices/system/cpu/offline", + .size = 1, + .content = "\n", + }, + { + .path = "/sys/devices/system/cpu/modalias", + .size = 436, + .content = + "x86cpu:vendor:0000:family:0006:model:005A:feature:,0000,0001,0002,0003,0004,0005,0006,0007,0008,0009,000B,000C,000D,000E,000F,0010,0011,0013,0015,0016,0017,0018,0019,001A,001B,001C,001D,001F,002B,0034,003B,003D,0068,006B,006C,006D,006F,0070,0072,0074,0076,0078,007C,0080,0081,0082,0083,0084,0085,0087,0088,0089,008D,008E,008F,0093,0094,0096,0097,0098,0099,009E,00C0,00C8,00E0,00E1,00E3,00E7,0100,0101,0102,0103,0104,0121,0127,0129,012D\n", + }, + { + .path = "/sys/devices/system/cpu/cpufreq/all_time_in_state", + .size = 769, + .content = "freq\t\tcpu0\t\tcpu1\t\tcpu2\t\tcpu3\t\t\n" + "500000\t\t4283894\t\t4283894\t\t4404405\t\t4404405\t\t\n" + "583000\t\t14933\t\t14933\t\t3589\t\t3589\t\t\n" + "666000\t\t3580\t\t3580\t\t1684\t\t1684\t\t\n" + "750000\t\t3550\t\t3550\t\t1120\t\t1120\t\t\n" + "833000\t\t1801\t\t1801\t\t912\t\t912\t\t\n" + "916000\t\t1745\t\t1745\t\t849\t\t849\t\t\n" + "1000000\t\t1321\t\t1321\t\t630\t\t630\t\t\n" + "1083000\t\t994\t\t994\t\t730\t\t730\t\t\n" + "1166000\t\t875\t\t875\t\t593\t\t593\t\t\n" + "1250000\t\t872\t\t872\t\t724\t\t724\t\t\n" + "1333000\t\t936\t\t936\t\t637\t\t637\t\t\n" + "1416000\t\t753\t\t753\t\t716\t\t716\t\t\n" + "1500000\t\t800\t\t800\t\t758\t\t758\t\t\n" + "1583000\t\t708\t\t708\t\t703\t\t703\t\t\n" + "1666000\t\t703\t\t703\t\t781\t\t781\t\t\n" + "1750000\t\t867\t\t867\t\t610\t\t610\t\t\n" + "1833000\t\t36252\t\t36252\t\t8354\t\t8354\t\t\n" + "1916000\t\t642\t\t642\t\t515\t\t515\t\t\n" + "2000000\t\t790\t\t790\t\t600\t\t600\t\t\n" + "2083000\t\t657\t\t657\t\t682\t\t682\t\t\n" + "2166000\t\t785\t\t785\t\t509\t\t509\t\t\n" + "2250000\t\t776\t\t776\t\t656\t\t656\t\t\n" + "2333000\t\t243140\t\t243140\t\t170617\t\t170617\t\t\n", + }, + { + .path = "/sys/devices/system/cpu/cpuidle/current_driver", + .size = 11, + .content = "intel_idle\n", + }, + { + .path = "/sys/devices/system/cpu/cpuidle/current_governor_ro", + .size = 5, + .content = "menu\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/affected_cpus", + .size = 4, + .content = "0 1\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq", + .size = 8, + .content = "2333000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_min_freq", + .size = 7, + .content = "500000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_transition_latency", + .size = 7, + .content = "100000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/related_cpus", + .size = 4, + .content = "0 1\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies", + .size = 179, + .content = + "2333000 2250000 2166000 2083000 2000000 1916000 1833000 1750000 1666000 1583000 1500000 1416000 1333000 1250000 1166000 1083000 1000000 916000 833000 750000 666000 583000 500000 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors", + .size = 44, + .content = "ondemand userspace interactive performance \n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq", + .size = 7, + .content = "500000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_driver", + .size = 12, + .content = "sfi-cpufreq\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_governor", + .size = 12, + .content = "interactive\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_min_freq", + .size = 7, + .content = "500000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", + .size = 286, + .content = "2333000 243140\n" + "2250000 776\n" + "2166000 785\n" + "2083000 657\n" + "2000000 790\n" + "1916000 642\n" + "1833000 36252\n" + "1750000 867\n" + "1666000 703\n" + "1583000 708\n" + "1500000 800\n" + "1416000 753\n" + "1333000 936\n" + "1250000 872\n" + "1166000 875\n" + "1083000 994\n" + "1000000 1321\n" + "916000 1745\n" + "833000 1801\n" + "750000 3550\n" + "666000 3580\n" + "583000 14933\n" + "500000 4283973\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", + .size = 6, + .content = "18659\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/trans_table", + .size = 4095, + .content = + " From : To\n" + " : 2333000 2250000 2166000 2083000 2000000 1916000 1833000 1750000 1666000 1583000 1500000 1416000 1333000 1250000 1166000 1083000 1000000 916000 833000 750000 666000 583000 500000 \n" + " 2333000: 0 147 147 107 128 92 102 101 85 80 92 71 78 66 57 53 55 57 62 60 63 91 1654 \n" + " 2250000: 156 0 6 2 3 3 1 4 3 4 2 2 1 2 1 1 4 2 1 0 0 1 11 \n" + " 2166000: 117 26 0 7 13 1 2 6 3 3 2 1 2 2 1 0 1 2 1 0 0 0 8 \n" + " 2083000: 57 25 22 0 2 5 2 4 4 4 4 4 0 1 1 1 2 1 3 5 0 0 5 \n" + " 2000000: 66 12 18 20 0 6 4 2 7 2 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"/sys/devices/system/cpu/cpu2/cache/index1/ways_of_associativity", + .size = 2, + .content = "8\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/cache/index2/coherency_line_size", + .size = 3, + .content = "64\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/cache/index2/level", + .size = 2, + .content = "2\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/cache/index2/number_of_sets", + .size = 5, + .content = "1024\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/cache/index2/shared_cpu_list", + .size = 4, + .content = "2-3\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/cache/index2/shared_cpu_map", + .size = 2, + .content = "c\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/cache/index2/size", + .size = 6, + .content = "1024K\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/cache/index2/type", + .size = 8, + .content = "Unified\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/cache/index2/ways_of_associativity", + .size = 3, + .content = "16\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cpufreq/affected_cpus", + .size = 4, + .content = "2 3\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cpufreq/cpuinfo_max_freq", + .size = 8, + .content = "2333000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cpufreq/cpuinfo_min_freq", + .size = 7, + .content = "500000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cpufreq/cpuinfo_transition_latency", + .size = 7, + .content = "100000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cpufreq/related_cpus", + .size = 4, + .content = "2 3\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_frequencies", + .size = 179, + .content = + "2333000 2250000 2166000 2083000 2000000 1916000 1833000 1750000 1666000 1583000 1500000 1416000 1333000 1250000 1166000 1083000 1000000 916000 833000 750000 666000 583000 500000 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_governors", + .size = 44, + .content = "ondemand userspace interactive performance \n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_cur_freq", + .size = 7, + .content = "500000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_driver", + .size = 12, + .content = "sfi-cpufreq\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_governor", + .size = 12, + .content = "interactive\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_min_freq", + .size = 7, + .content = "500000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", + .size = 281, + .content = "2333000 170617\n" + "2250000 656\n" + "2166000 509\n" + "2083000 682\n" + "2000000 600\n" + "1916000 515\n" + "1833000 8354\n" + "1750000 610\n" + "1666000 781\n" + "1583000 703\n" + "1500000 758\n" + "1416000 716\n" + "1333000 637\n" + "1250000 724\n" + "1166000 593\n" + "1083000 730\n" + "1000000 630\n" + "916000 849\n" + "833000 912\n" + "750000 1120\n" + "666000 1684\n" + "583000 3589\n" + "500000 4405273\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", + .size = 5, + .content = "7130\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/trans_table", + .size = 4095, + .content = + " From : To\n" + " : 2333000 2250000 2166000 2083000 2000000 1916000 1833000 1750000 1666000 1583000 1500000 1416000 1333000 1250000 1166000 1083000 1000000 916000 833000 750000 666000 583000 500000 \n" + " 2333000: 0 104 85 92 74 68 78 67 57 52 61 54 47 51 31 45 31 37 36 37 36 51 530 \n" + " 2250000: 114 0 6 7 3 6 2 2 4 2 0 0 5 0 1 1 0 1 1 1 0 0 5 \n" + " 2166000: 59 22 0 4 3 5 5 1 4 3 2 2 1 1 1 1 1 1 2 0 1 0 5 \n" + " 2083000: 62 21 18 0 5 4 6 4 4 3 3 1 1 3 2 2 1 4 0 1 1 1 4 \n" + " 2000000: 21 14 13 25 0 7 8 3 5 1 6 2 3 2 1 1 3 2 3 0 0 0 6 \n" + " 1916000: 33 0 2 20 20 0 6 2 3 4 2 3 2 3 2 1 2 0 0 1 2 0 15 \n" + " 1833000: 46 0 0 3 18 23 0 18 24 22 18 13 17 12 9 13 12 12 4 7 3 9 166 \n" + " 1750000: 35 0 0 0 3 9 37 0 6 4 2 4 4 4 4 3 1 1 1 3 0 1 15 \n" + " 1666000: 29 0 0 0 0 0 29 20 0 11 8 3 5 12 2 2 2 5 2 0 2 0 16 \n" + " 1583000: 31 0 0 0 0 0 5 19 18 0 7 9 5 3 6 5 3 5 4 1 2 0 15 \n" + " 1500000: 30 0 0 0 0 0 0 0 22 20 0 14 6 6 7 6 5 6 1 1 2 6 17 \n" + " 1416000: 42 0 0 0 0 0 3 0 0 16 23 0 5 14 2 5 1 6 7 2 3 1 19 \n" + " 1333000: 34 0 0 0 0 0 6 1 0 0 17 30 0 4 1 6 8 4 2 7 4 2 15 \n" + " 1250000: 27 0 0 0 0 0 4 0 0 0 0 14 27 0 11 7 6 5 4 4 5 4 20 \n" + " 1166000: 19 0 0 0 0 0 4 0 0 0 0 0 13 20 0 5 4 5 9 4 5 1 28 \n" + " 1083000: 20 0 0 0 0 0 4 0 0 0 0 0 0 3 29 0 11 7 6 ", + }, + { + .path = "/sys/devices/system/cpu/cpu3/topology/physical_package_id", + .size = 2, + .content = "0\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/topology/core_siblings_list", + .size = 4, + .content = "0-3\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/topology/core_siblings", + .size = 2, + .content = "f\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/topology/core_id", + .size = 2, + .content = "3\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/topology/thread_siblings_list", + .size = 2, + .content = "3\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/topology/thread_siblings", + .size = 2, + .content = "8\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cache/index0/coherency_line_size", + .size = 3, + .content = "64\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cache/index0/level", + .size = 2, + .content = "1\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cache/index0/number_of_sets", + .size = 3, + .content = "64\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cache/index0/shared_cpu_list", + .size = 2, + .content = "3\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cache/index0/shared_cpu_map", + .size = 2, + .content = "8\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cache/index0/size", + .size = 4, + .content = "24K\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cache/index0/type", + .size = 5, + .content = "Data\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cache/index0/ways_of_associativity", + .size = 2, + .content = "6\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cache/index1/coherency_line_size", + .size = 3, + .content = "64\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cache/index1/level", + .size = 2, + .content = "1\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cache/index1/number_of_sets", + .size = 3, + .content = "64\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cache/index1/shared_cpu_list", + .size = 2, + .content = "3\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cache/index1/shared_cpu_map", + .size = 2, + .content = "8\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cache/index1/size", + .size = 4, + .content = "32K\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cache/index1/type", + .size = 12, + .content = "Instruction\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cache/index1/ways_of_associativity", + .size = 2, + .content = "8\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cache/index2/coherency_line_size", + .size = 3, + .content = "64\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cache/index2/level", + .size = 2, + .content = "2\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cache/index2/number_of_sets", + .size = 5, + .content = "1024\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cache/index2/shared_cpu_list", + .size = 4, + .content = "2-3\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cache/index2/shared_cpu_map", + .size = 2, + .content = "c\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cache/index2/size", + .size = 6, + .content = "1024K\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cache/index2/type", + .size = 8, + .content = "Unified\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cache/index2/ways_of_associativity", + .size = 3, + .content = "16\n", + }, + {NULL}, }; #ifdef __ANDROID__ @@ -3046,6 +3049,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.driver.status", .value = "ok", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/zenfone-2e.cc b/test/mock/zenfone-2e.cc index 057c069e..2d4bfd2c 100644 --- a/test/mock/zenfone-2e.cc +++ b/test/mock/zenfone-2e.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(4, cpuinfo_get_processors_count()); @@ -212,8 +211,10 @@ TEST(PACKAGES, non_null) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Intel Atom Z2560", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Intel Atom Z2560", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -536,8 +537,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -588,8 +591,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -640,8 +645,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/zenfone-2e.h b/test/mock/zenfone-2e.h index 5e0993b8..4dfefa68 100644 --- a/test/mock/zenfone-2e.h +++ b/test/mock/zenfone-2e.h @@ -478,7 +478,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/modalias", .size = 321, - .content = "x86cpu:vendor:0000:family:0006:model:0035:feature:,0000,0001,0002,0003,0004,0005,0006,0007,0008,0009,000B,000C,000D,000E,000F,0010,0013,0015,0016,0017,0018,0019,001A,001B,001C,001D,001F,0034,0066,0068,006B,006C,006D,0072,0078,007C,007E,0080,0082,0083,0084,0085,0087,0088,0089,008E,008F,0096,00C0,00E1,00E7,0100,0101,0102\n", + .content = + "x86cpu:vendor:0000:family:0006:model:0035:feature:,0000,0001,0002,0003,0004,0005,0006,0007,0008,0009,000B,000C,000D,000E,000F,0010,0013,0015,0016,0017,0018,0019,001A,001B,001C,001D,001F,0034,0066,0068,006B,006C,006D,0072,0078,007C,007E,0080,0082,0083,0084,0085,0087,0088,0089,008E,008F,0096,00C0,00E1,00E7,0100,0101,0102\n", }, { .path = "/sys/devices/system/cpu/cpuidle/current_driver", @@ -548,11 +549,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 49, - .content = - "1600000 6382\n" - "1333000 580\n" - "933000 362\n" - "800000 19032\n", + .content = "1600000 6382\n" + "1333000 580\n" + "933000 362\n" + "800000 19032\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -562,13 +562,12 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/trans_table", .size = 277, - .content = - " From : To\n" - " : 1600000 1333000 933000 800000 \n" - " 1600000: 0 46 18 130 \n" - " 1333000: 36 0 4 34 \n" - " 933000: 21 12 0 35 \n" - " 800000: 137 16 46 0 \n", + .content = " From : To\n" + " : 1600000 1333000 933000 800000 \n" + " 1600000: 0 46 18 130 \n" + " 1333000: 36 0 4 34 \n" + " 933000: 21 12 0 35 \n" + " 800000: 137 16 46 0 \n", }, { .path = "/sys/devices/system/cpu/cpu0/topology/physical_package_id", @@ -778,11 +777,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 49, - .content = - "1600000 6415\n" - "1333000 580\n" - "933000 362\n" - "800000 19247\n", + .content = "1600000 6415\n" + "1333000 580\n" + "933000 362\n" + "800000 19247\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -792,13 +790,12 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/trans_table", .size = 277, - .content = - " From : To\n" - " : 1600000 1333000 933000 800000 \n" - " 1600000: 0 46 18 132 \n" - " 1333000: 36 0 4 34 \n" - " 933000: 21 12 0 35 \n" - " 800000: 139 16 46 0 \n", + .content = " From : To\n" + " : 1600000 1333000 933000 800000 \n" + " 1600000: 0 46 18 132 \n" + " 1333000: 36 0 4 34 \n" + " 933000: 21 12 0 35 \n" + " 800000: 139 16 46 0 \n", }, { .path = "/sys/devices/system/cpu/cpu1/topology/physical_package_id", @@ -1013,11 +1010,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 49, - .content = - "1600000 6073\n" - "1333000 374\n" - "933000 465\n" - "800000 19948\n", + .content = "1600000 6073\n" + "1333000 374\n" + "933000 465\n" + "800000 19948\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -1027,13 +1023,12 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/trans_table", .size = 277, - .content = - " From : To\n" - " : 1600000 1333000 933000 800000 \n" - " 1600000: 0 41 15 129 \n" - " 1333000: 27 0 5 31 \n" - " 933000: 17 12 0 45 \n" - " 800000: 141 10 54 0 \n", + .content = " From : To\n" + " : 1600000 1333000 933000 800000 \n" + " 1600000: 0 41 15 129 \n" + " 1333000: 27 0 5 31 \n" + " 933000: 17 12 0 45 \n" + " 800000: 141 10 54 0 \n", }, { .path = "/sys/devices/system/cpu/cpu2/topology/physical_package_id", @@ -1248,11 +1243,10 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 49, - .content = - "1600000 6085\n" - "1333000 374\n" - "933000 465\n" - "800000 20190\n", + .content = "1600000 6085\n" + "1333000 374\n" + "933000 465\n" + "800000 20190\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -1262,13 +1256,12 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/trans_table", .size = 277, - .content = - " From : To\n" - " : 1600000 1333000 933000 800000 \n" - " 1600000: 0 41 15 130 \n" - " 1333000: 27 0 5 31 \n" - " 933000: 17 12 0 45 \n" - " 800000: 142 10 54 0 \n", + .content = " From : To\n" + " : 1600000 1333000 933000 800000 \n" + " 1600000: 0 41 15 130 \n" + " 1333000: 27 0 5 31 \n" + " 933000: 17 12 0 45 \n" + " 800000: 142 10 54 0 \n", }, { .path = "/sys/devices/system/cpu/cpu3/topology/physical_package_id", @@ -1420,7 +1413,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "8\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ @@ -2757,6 +2750,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wlan.driver.status", .value = "ok", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/mock/zenfone-c.cc b/test/mock/zenfone-c.cc index 79ff72e3..22fbbaa6 100644 --- a/test/mock/zenfone-c.cc +++ b/test/mock/zenfone-c.cc @@ -1,8 +1,7 @@ #include -#include #include - +#include TEST(PROCESSORS, count) { ASSERT_EQ(4, cpuinfo_get_processors_count()); @@ -212,8 +211,10 @@ TEST(PACKAGES, non_null) { TEST(PACKAGES, name) { for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - ASSERT_EQ("Intel Atom Z2520", - std::string(cpuinfo_get_package(i)->name, + ASSERT_EQ( + "Intel Atom Z2520", + std::string( + cpuinfo_get_package(i)->name, strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); } } @@ -536,8 +537,10 @@ TEST(L1I, associativity) { TEST(L1I, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, - cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * + cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); } } @@ -588,8 +591,10 @@ TEST(L1D, associativity) { TEST(L1D, sets) { for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, - cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * + cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); } } @@ -640,8 +645,10 @@ TEST(L2, associativity) { TEST(L2, sets) { for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { - ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, - cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + ASSERT_EQ( + cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * + cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); } } diff --git a/test/mock/zenfone-c.h b/test/mock/zenfone-c.h index b0cf3f0c..1ccd1836 100644 --- a/test/mock/zenfone-c.h +++ b/test/mock/zenfone-c.h @@ -416,7 +416,8 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/modalias", .size = 321, - .content = "x86cpu:vendor:0000:family:0006:model:0035:feature:,0000,0001,0002,0003,0004,0005,0006,0007,0008,0009,000B,000C,000D,000E,000F,0010,0013,0015,0016,0017,0018,0019,001A,001B,001C,001D,001F,0034,0066,0068,006B,006C,006D,0072,0078,007C,007E,0080,0082,0083,0084,0085,0087,0088,0089,008E,008F,0096,00C0,00E1,00E7,0100,0101,0102\n", + .content = + "x86cpu:vendor:0000:family:0006:model:0035:feature:,0000,0001,0002,0003,0004,0005,0006,0007,0008,0009,000B,000C,000D,000E,000F,0010,0013,0015,0016,0017,0018,0019,001A,001B,001C,001D,001F,0034,0066,0068,006B,006C,006D,0072,0078,007C,007E,0080,0082,0083,0084,0085,0087,0088,0089,008E,008F,0096,00C0,00E1,00E7,0100,0101,0102\n", }, { .path = "/sys/devices/system/cpu/cpuidle/current_driver", @@ -486,10 +487,9 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", .size = 36, - .content = - "1200000 4635\n" - "933000 258\n" - "800000 8780\n", + .content = "1200000 4635\n" + "933000 258\n" + "800000 8780\n", }, { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", @@ -499,12 +499,11 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/trans_table", .size = 185, - .content = - " From : To\n" - " : 1200000 933000 800000 \n" - " 1200000: 0 5 76 \n" - " 933000: 38 0 9 \n" - " 800000: 43 42 0 \n", + .content = " From : To\n" + " : 1200000 933000 800000 \n" + " 1200000: 0 5 76 \n" + " 933000: 38 0 9 \n" + " 800000: 43 42 0 \n", }, { .path = "/sys/devices/system/cpu/cpu0/topology/physical_package_id", @@ -719,10 +718,9 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", .size = 36, - .content = - "1200000 4873\n" - "933000 208\n" - "800000 8864\n", + .content = "1200000 4873\n" + "933000 208\n" + "800000 8864\n", }, { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", @@ -732,12 +730,11 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/trans_table", .size = 185, - .content = - " From : To\n" - " : 1200000 933000 800000 \n" - " 1200000: 0 12 79 \n" - " 933000: 35 0 9 \n" - " 800000: 56 32 0 \n", + .content = " From : To\n" + " : 1200000 933000 800000 \n" + " 1200000: 0 12 79 \n" + " 933000: 35 0 9 \n" + " 800000: 56 32 0 \n", }, { .path = "/sys/devices/system/cpu/cpu1/topology/physical_package_id", @@ -952,10 +949,9 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", .size = 36, - .content = - "1200000 5134\n" - "933000 340\n" - "800000 8738\n", + .content = "1200000 5134\n" + "933000 340\n" + "800000 8738\n", }, { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", @@ -965,12 +961,11 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/trans_table", .size = 185, - .content = - " From : To\n" - " : 1200000 933000 800000 \n" - " 1200000: 0 12 84 \n" - " 933000: 39 0 19 \n" - " 800000: 57 46 0 \n", + .content = " From : To\n" + " : 1200000 933000 800000 \n" + " 1200000: 0 12 84 \n" + " 933000: 39 0 19 \n" + " 800000: 57 46 0 \n", }, { .path = "/sys/devices/system/cpu/cpu2/topology/physical_package_id", @@ -1185,10 +1180,9 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", .size = 36, - .content = - "1200000 5255\n" - "933000 336\n" - "800000 8901\n", + .content = "1200000 5255\n" + "933000 336\n" + "800000 8901\n", }, { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", @@ -1198,12 +1192,11 @@ struct cpuinfo_mock_file filesystem[] = { { .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/trans_table", .size = 185, - .content = - " From : To\n" - " : 1200000 933000 800000 \n" - " 1200000: 0 16 77 \n" - " 933000: 42 0 17 \n" - " 800000: 51 43 0 \n", + .content = " From : To\n" + " : 1200000 933000 800000 \n" + " 1200000: 0 16 77 \n" + " 933000: 42 0 17 \n" + " 800000: 51 43 0 \n", }, { .path = "/sys/devices/system/cpu/cpu3/topology/physical_package_id", @@ -1355,7 +1348,7 @@ struct cpuinfo_mock_file filesystem[] = { .size = 2, .content = "8\n", }, - { NULL }, + {NULL}, }; #ifdef __ANDROID__ @@ -2568,6 +2561,6 @@ struct cpuinfo_mock_property properties[] = { .key = "wpa_supplicant.pid", .value = "694", }, - { NULL }, + {NULL}, }; #endif /* __ANDROID__ */ diff --git a/test/name/android-properties-interface.c b/test/name/android-properties-interface.c index 4913f77f..57dbb198 100644 --- a/test/name/android-properties-interface.c +++ b/test/name/android-properties-interface.c @@ -1,9 +1,8 @@ #include +#include #include #include -#include - void cpuinfo_arm_android_parse_chipset_properties( const char proc_cpuinfo_hardware[CPUINFO_HARDWARE_VALUE_MAX], @@ -14,8 +13,7 @@ void cpuinfo_arm_android_parse_chipset_properties( const char ro_chipname[CPUINFO_BUILD_PROP_VALUE_MAX], uint32_t cores, uint32_t max_cpu_freq_max, - char chipset_name[CPUINFO_ARM_CHIPSET_NAME_MAX]) -{ + char chipset_name[CPUINFO_ARM_CHIPSET_NAME_MAX]) { struct cpuinfo_android_properties properties; strncpy(properties.proc_cpuinfo_hardware, proc_cpuinfo_hardware, CPUINFO_HARDWARE_VALUE_MAX); strncpy(properties.ro_product_board, ro_product_board, CPUINFO_BUILD_PROP_VALUE_MAX); @@ -24,8 +22,7 @@ void cpuinfo_arm_android_parse_chipset_properties( strncpy(properties.ro_arch, ro_arch, CPUINFO_BUILD_PROP_VALUE_MAX); strncpy(properties.ro_chipname, ro_chipname, CPUINFO_BUILD_PROP_VALUE_MAX); - struct cpuinfo_arm_chipset chipset = - cpuinfo_arm_android_decode_chipset(&properties, cores, max_cpu_freq_max); + struct cpuinfo_arm_chipset chipset = cpuinfo_arm_android_decode_chipset(&properties, cores, max_cpu_freq_max); if (chipset.series == cpuinfo_arm_chipset_series_unknown) { chipset_name[0] = 0; } else { @@ -34,11 +31,13 @@ void cpuinfo_arm_android_parse_chipset_properties( } void cpuinfo_arm_android_parse_proc_cpuinfo_hardware( - const char hardware[CPUINFO_HARDWARE_VALUE_MAX], uint32_t cores, uint32_t max_cpu_freq_max, bool is_tegra, - char chipset_name[CPUINFO_ARM_CHIPSET_NAME_MAX]) -{ - struct cpuinfo_arm_chipset chipset = - cpuinfo_arm_linux_decode_chipset_from_proc_cpuinfo_hardware(hardware, cores, max_cpu_freq_max, is_tegra); + const char hardware[CPUINFO_HARDWARE_VALUE_MAX], + uint32_t cores, + uint32_t max_cpu_freq_max, + bool is_tegra, + char chipset_name[CPUINFO_ARM_CHIPSET_NAME_MAX]) { + struct cpuinfo_arm_chipset chipset = cpuinfo_arm_linux_decode_chipset_from_proc_cpuinfo_hardware( + hardware, cores, max_cpu_freq_max, is_tegra); if (chipset.series == cpuinfo_arm_chipset_series_unknown) { chipset_name[0] = 0; } else { @@ -48,9 +47,10 @@ void cpuinfo_arm_android_parse_proc_cpuinfo_hardware( } void cpuinfo_arm_android_parse_ro_product_board( - const char board[CPUINFO_BUILD_PROP_VALUE_MAX], uint32_t cores, uint32_t max_cpu_freq_max, - char chipset_name[CPUINFO_ARM_CHIPSET_NAME_MAX]) -{ + const char board[CPUINFO_BUILD_PROP_VALUE_MAX], + uint32_t cores, + uint32_t max_cpu_freq_max, + char chipset_name[CPUINFO_ARM_CHIPSET_NAME_MAX]) { struct cpuinfo_arm_chipset chipset = cpuinfo_arm_android_decode_chipset_from_ro_product_board(board, cores, max_cpu_freq_max); if (chipset.series == cpuinfo_arm_chipset_series_unknown) { @@ -62,9 +62,10 @@ void cpuinfo_arm_android_parse_ro_product_board( } void cpuinfo_arm_android_parse_ro_board_platform( - const char platform[CPUINFO_BUILD_PROP_VALUE_MAX], uint32_t cores, uint32_t max_cpu_freq_max, - char chipset_name[CPUINFO_ARM_CHIPSET_NAME_MAX]) -{ + const char platform[CPUINFO_BUILD_PROP_VALUE_MAX], + uint32_t cores, + uint32_t max_cpu_freq_max, + char chipset_name[CPUINFO_ARM_CHIPSET_NAME_MAX]) { struct cpuinfo_arm_chipset chipset = cpuinfo_arm_android_decode_chipset_from_ro_board_platform(platform, cores, max_cpu_freq_max); if (chipset.series == cpuinfo_arm_chipset_series_unknown) { @@ -76,9 +77,10 @@ void cpuinfo_arm_android_parse_ro_board_platform( } void cpuinfo_arm_android_parse_ro_mediatek_platform( - const char platform[CPUINFO_BUILD_PROP_VALUE_MAX], uint32_t cores, uint32_t max_cpu_freq_max, - char chipset_name[CPUINFO_ARM_CHIPSET_NAME_MAX]) -{ + const char platform[CPUINFO_BUILD_PROP_VALUE_MAX], + uint32_t cores, + uint32_t max_cpu_freq_max, + char chipset_name[CPUINFO_ARM_CHIPSET_NAME_MAX]) { struct cpuinfo_arm_chipset chipset = cpuinfo_arm_android_decode_chipset_from_ro_mediatek_platform(platform); if (chipset.series == cpuinfo_arm_chipset_series_unknown) { chipset_name[0] = 0; @@ -89,9 +91,10 @@ void cpuinfo_arm_android_parse_ro_mediatek_platform( } void cpuinfo_arm_android_parse_ro_arch( - const char arch[CPUINFO_BUILD_PROP_VALUE_MAX], uint32_t cores, uint32_t max_cpu_freq_max, - char chipset_name[CPUINFO_ARM_CHIPSET_NAME_MAX]) -{ + const char arch[CPUINFO_BUILD_PROP_VALUE_MAX], + uint32_t cores, + uint32_t max_cpu_freq_max, + char chipset_name[CPUINFO_ARM_CHIPSET_NAME_MAX]) { struct cpuinfo_arm_chipset chipset = cpuinfo_arm_android_decode_chipset_from_ro_arch(arch); if (chipset.series == cpuinfo_arm_chipset_series_unknown) { chipset_name[0] = 0; @@ -102,9 +105,10 @@ void cpuinfo_arm_android_parse_ro_arch( } void cpuinfo_arm_android_parse_ro_chipname( - const char chipname[CPUINFO_BUILD_PROP_VALUE_MAX], uint32_t cores, uint32_t max_cpu_freq_max, - char chipset_name[CPUINFO_ARM_CHIPSET_NAME_MAX]) -{ + const char chipname[CPUINFO_BUILD_PROP_VALUE_MAX], + uint32_t cores, + uint32_t max_cpu_freq_max, + char chipset_name[CPUINFO_ARM_CHIPSET_NAME_MAX]) { struct cpuinfo_arm_chipset chipset = cpuinfo_arm_android_decode_chipset_from_ro_chipname(chipname); if (chipset.series == cpuinfo_arm_chipset_series_unknown) { chipset_name[0] = 0; diff --git a/test/name/android-properties.cc b/test/name/android-properties.cc index 945e7075..b712cdc9 100644 --- a/test/name/android-properties.cc +++ b/test/name/android-properties.cc @@ -27,121 +27,103 @@ inline std::string parse_chipset( std::string mediatek_platform, std::string arch, std::string chipname, - uint32_t cores=1, - uint32_t max_cpu_freq_max=0) -{ + uint32_t cores = 1, + uint32_t max_cpu_freq_max = 0) { char chipset_name[CPUINFO_ARM_CHIPSET_NAME_MAX]; cpuinfo_arm_android_parse_chipset_properties( - hardware.c_str(), product_board.c_str(), board_platform.c_str(), mediatek_platform.c_str(), arch.c_str(), chipname.c_str(), - cores, max_cpu_freq_max, chipset_name); + hardware.c_str(), + product_board.c_str(), + board_platform.c_str(), + mediatek_platform.c_str(), + arch.c_str(), + chipname.c_str(), + cores, + max_cpu_freq_max, + chipset_name); return std::string(chipset_name, strnlen(chipset_name, CPUINFO_ARM_CHIPSET_NAME_MAX)); } TEST(ANDROID_PROPERTIES, disambiguate_chipset) { #if CPUINFO_ARCH_ARM - EXPECT_EQ("Amlogic S812", - parse_chipset("Amlogic Meson8", "n200C", "meson8", "", "", "")); - EXPECT_EQ("HiSilicon Kirin 925", - parse_chipset("Kirin925", "MT7-L09", "hi3630", "", "", "")); + EXPECT_EQ("Amlogic S812", parse_chipset("Amlogic Meson8", "n200C", "meson8", "", "", "")); + EXPECT_EQ("HiSilicon Kirin 925", parse_chipset("Kirin925", "MT7-L09", "hi3630", "", "", "")); #endif /* CPUINFO_ARCH_ARM */ - EXPECT_EQ("HiSilicon Kirin 955", - parse_chipset("Hisilicon Kirin 955", "EVA-L09", "hi3650", "", "", "")); + EXPECT_EQ("HiSilicon Kirin 955", parse_chipset("Hisilicon Kirin 955", "EVA-L09", "hi3650", "", "", "")); #if CPUINFO_ARCH_ARM - EXPECT_EQ("Marvell PXA986", - parse_chipset("PXA988", "PXA986", "mrvl", "", "", "")); - EXPECT_EQ("Marvell PXA986", - parse_chipset("PXA988", "PXA986", "mrvl", "", "", "PXA986")); + EXPECT_EQ("Marvell PXA986", parse_chipset("PXA988", "PXA986", "mrvl", "", "", "")); + EXPECT_EQ("Marvell PXA986", parse_chipset("PXA988", "PXA986", "mrvl", "", "", "PXA986")); #endif /* CPUINFO_ARCH_ARM */ - EXPECT_EQ("MediaTek MT6735P", - parse_chipset("MT6735P", "MT6735P", "mt6735m", "MT6735", "", "")); - EXPECT_EQ("MediaTek MT8382", - parse_chipset("MT8382", "MT8382", "", "MT6582", "", "")); - EXPECT_EQ("MediaTek MT6735P", - parse_chipset("MT6735P", "unknown", "mt6735m", "MT6735", "", "")); - EXPECT_EQ("MediaTek MT8382", - parse_chipset("MT8382", "LenovoTAB2A7-30HC", "", "MT6582", "", "")); - EXPECT_EQ("Qualcomm MSM8926", + EXPECT_EQ("MediaTek MT6735P", parse_chipset("MT6735P", "MT6735P", "mt6735m", "MT6735", "", "")); + EXPECT_EQ("MediaTek MT8382", parse_chipset("MT8382", "MT8382", "", "MT6582", "", "")); + EXPECT_EQ("MediaTek MT6735P", parse_chipset("MT6735P", "unknown", "mt6735m", "MT6735", "", "")); + EXPECT_EQ("MediaTek MT8382", parse_chipset("MT8382", "LenovoTAB2A7-30HC", "", "MT6582", "", "")); + EXPECT_EQ( + "Qualcomm MSM8926", parse_chipset("Qualcomm MSM 8226 (Flattened Device Tree)", "MSM8226", "msm8226", "", "", "MSM8926")); - EXPECT_EQ("Qualcomm MSM8926", - parse_chipset("Qualcomm MSM8926", "draconis", "msm8226", "", "", "")); - EXPECT_EQ("Qualcomm MSM8930AB", - parse_chipset("SAMSUNG SERRANO", "MSM8960", "msm8960", "", "", "MSM8930AB", 2)); - EXPECT_EQ("Qualcomm MSM8940", + EXPECT_EQ("Qualcomm MSM8926", parse_chipset("Qualcomm MSM8926", "draconis", "msm8226", "", "", "")); + EXPECT_EQ("Qualcomm MSM8930AB", parse_chipset("SAMSUNG SERRANO", "MSM8960", "msm8960", "", "", "MSM8930AB", 2)); + EXPECT_EQ( + "Qualcomm MSM8940", parse_chipset("Qualcomm Technologies, Inc MSM8940", "msm8937_32", "msm8937", "", "", "", 8)); - EXPECT_EQ("Spreadtrum SC6815AS", - parse_chipset("scx15", "SC6815AS", "scx15", "", "", "SC6815AS")); - EXPECT_EQ("Spreadtrum SC7727S", - parse_chipset("sc8830", "SC7727S", "sc8830", "", "", "SC7727S")); - EXPECT_EQ("Spreadtrum SC7731", - parse_chipset("sc7731", "SC7731", "sc8830", "", "", "")); - EXPECT_EQ("Spreadtrum SC7731C", - parse_chipset("sc7731c", "sp7731cea", "sc8830", "", "", "")); + EXPECT_EQ("Spreadtrum SC6815AS", parse_chipset("scx15", "SC6815AS", "scx15", "", "", "SC6815AS")); + EXPECT_EQ("Spreadtrum SC7727S", parse_chipset("sc8830", "SC7727S", "sc8830", "", "", "SC7727S")); + EXPECT_EQ("Spreadtrum SC7731", parse_chipset("sc7731", "SC7731", "sc8830", "", "", "")); + EXPECT_EQ("Spreadtrum SC7731C", parse_chipset("sc7731c", "sp7731cea", "sc8830", "", "", "")); } TEST(ANDROID_PROPERTIES, ambiguous_vendors) { - EXPECT_EQ("", - parse_chipset("MTK6580", "sp7731ceb", "sc8830", "", "", "")); - EXPECT_EQ("", - parse_chipset("", "universal5410", "msm8974", "", "", "")); - EXPECT_EQ("", - parse_chipset("MT6580", "universal8895", "mt6580", "MT6580", "", "")); + EXPECT_EQ("", parse_chipset("MTK6580", "sp7731ceb", "sc8830", "", "", "")); + EXPECT_EQ("", parse_chipset("", "universal5410", "msm8974", "", "", "")); + EXPECT_EQ("", parse_chipset("MT6580", "universal8895", "mt6580", "MT6580", "", "")); #if CPUINFO_ARCH_ARM - EXPECT_EQ("", - parse_chipset("", "smdk4x12", "msm8974", "", "", "", 2)); + EXPECT_EQ("", parse_chipset("", "smdk4x12", "msm8974", "", "", "", 2)); #endif /* CPUINFO_ARCH_ARM */ } TEST(ANDROID_PROPERTIES, unambiguous_chipset) { - EXPECT_EQ("Samsung Exynos 3470", + EXPECT_EQ( + "Samsung Exynos 3470", parse_chipset("UNIVERSAL_GARDA", "universal_garda", "exynos3", "", "exynos3470", "exynos3470")); - EXPECT_EQ("MediaTek MT6582", - parse_chipset("APPLE A8", "APPLE A8", "", "MT6582", "", "")); + EXPECT_EQ("MediaTek MT6582", parse_chipset("APPLE A8", "APPLE A8", "", "MT6582", "", "")); #if CPUINFO_ARCH_ARM - EXPECT_EQ("NovaThor U8500", - parse_chipset("SAMSUNG GOLDEN", "DB8520H", "montblanc", "", "", "")); + EXPECT_EQ("NovaThor U8500", parse_chipset("SAMSUNG GOLDEN", "DB8520H", "montblanc", "", "", "")); #endif /* CPUINFO_ARCH_ARM */ - EXPECT_EQ("MediaTek MT6580", - parse_chipset("Qualcomm", "unknown", "mt6580", "MT6580", "", "")); - EXPECT_EQ("HiSilicon Kirin 650", - parse_chipset("", "hi6250", "", "", "", "")); - EXPECT_EQ("Samsung Exynos 8890", - parse_chipset("", "universal8890", "exynos5", "", "exynos8890", "exynos8890")); - EXPECT_EQ("MediaTek MT6582", - parse_chipset("", "MT6582", "", "MT6582", "", "")); - EXPECT_EQ("Qualcomm MSM8994", - parse_chipset("", "msm8994", "msm8994", "", "", "")); - EXPECT_EQ("Qualcomm APQ8064", - parse_chipset("SAMSUNG JF", "MSM8960", "msm8960", "", "", "apq8064", 4)); - EXPECT_EQ("MediaTek MT6795", - parse_chipset("", "mt6795", "mt6795", "MT6795", "", "")); + EXPECT_EQ("MediaTek MT6580", parse_chipset("Qualcomm", "unknown", "mt6580", "MT6580", "", "")); + EXPECT_EQ("HiSilicon Kirin 650", parse_chipset("", "hi6250", "", "", "", "")); + EXPECT_EQ("Samsung Exynos 8890", parse_chipset("", "universal8890", "exynos5", "", "exynos8890", "exynos8890")); + EXPECT_EQ("MediaTek MT6582", parse_chipset("", "MT6582", "", "MT6582", "", "")); + EXPECT_EQ("Qualcomm MSM8994", parse_chipset("", "msm8994", "msm8994", "", "", "")); + EXPECT_EQ("Qualcomm APQ8064", parse_chipset("SAMSUNG JF", "MSM8960", "msm8960", "", "", "apq8064", 4)); + EXPECT_EQ("MediaTek MT6795", parse_chipset("", "mt6795", "mt6795", "MT6795", "", "")); #if CPUINFO_ARCH_ARM - EXPECT_EQ("Marvell PXA1908", - parse_chipset("PXA1908", "PXA19xx", "mrvl", "", "", "PXA19xx")); + EXPECT_EQ("Marvell PXA1908", parse_chipset("PXA1908", "PXA19xx", "mrvl", "", "", "PXA19xx")); #endif /* CPUINFO_ARCH_ARM */ - EXPECT_EQ("Spreadtrum SC7715A", - parse_chipset("scx15", "SM-G928G", "scx15", "", "", "SC7715A")); - EXPECT_EQ("MediaTek MT6592", - parse_chipset("MT6592", "lcsh92_cwet_htc_kk", "", "MT6592", "", "")); - EXPECT_EQ("HiSilicon Kirin 620", - parse_chipset("hi6210sft", "BalongV8R1SFT", "hi6210sft", "", "", "")); - EXPECT_EQ("Qualcomm APQ8064", - parse_chipset("PANTECH APQ8064 EF52L", "VEGA", "msm8960", "", "", "apq8064", 4)); - EXPECT_EQ("MediaTek MT6580M", - parse_chipset("MT6580M", "unknown", "mt6580", "MT6580", "", "")); + EXPECT_EQ("Spreadtrum SC7715A", parse_chipset("scx15", "SM-G928G", "scx15", "", "", "SC7715A")); + EXPECT_EQ("MediaTek MT6592", parse_chipset("MT6592", "lcsh92_cwet_htc_kk", "", "MT6592", "", "")); + EXPECT_EQ("HiSilicon Kirin 620", parse_chipset("hi6210sft", "BalongV8R1SFT", "hi6210sft", "", "", "")); + EXPECT_EQ("Qualcomm APQ8064", parse_chipset("PANTECH APQ8064 EF52L", "VEGA", "msm8960", "", "", "apq8064", 4)); + EXPECT_EQ("MediaTek MT6580M", parse_chipset("MT6580M", "unknown", "mt6580", "MT6580", "", "")); #if CPUINFO_ARCH_ARM - EXPECT_EQ("Samsung Exynos 4412", - parse_chipset("SMDK4x12", "smdk4x12", "exynos4", "", "", "smdk4x12", 4)); + EXPECT_EQ("Samsung Exynos 4412", parse_chipset("SMDK4x12", "smdk4x12", "exynos4", "", "", "smdk4x12", 4)); #endif /* CPUINFO_ARCH_ARM */ - EXPECT_EQ("Samsung Exynos 7420", + EXPECT_EQ( + "Samsung Exynos 7420", parse_chipset("SAMSUNG Exynos7420", "universal7420", "exynos5", "", "exynos7420", "exynos7420")); - EXPECT_EQ("MediaTek MT6582", - parse_chipset("MT6582", "MT6582", "", "MT6582", "", "")); - EXPECT_EQ("Qualcomm MSM8916", + EXPECT_EQ("MediaTek MT6582", parse_chipset("MT6582", "MT6582", "", "MT6582", "", "")); + EXPECT_EQ( + "Qualcomm MSM8916", parse_chipset("Qualcomm Technologies, Inc MSM8916", "msm8916", "msm8916", "", "", "", 4)); - EXPECT_EQ("Qualcomm MSM8916", + EXPECT_EQ( + "Qualcomm MSM8916", parse_chipset("Qualcomm Technologies, Inc MSM8916", "MSM8916", "msm8916", "", "", "MSM8916", 4)); - EXPECT_EQ("MediaTek MT6735", - parse_chipset("MT6735", "mt6735", "mt6735", "MT6735", "", "")); - EXPECT_EQ("MediaTek MT6737T", - parse_chipset("Samsung GrandPrimePlus LTE CIS rev04 board based on MT6737T", "MT6737T", "mt6737t", "MT6737T", "", "MT6737T")); + EXPECT_EQ("MediaTek MT6735", parse_chipset("MT6735", "mt6735", "mt6735", "MT6735", "", "")); + EXPECT_EQ( + "MediaTek MT6737T", + parse_chipset( + "Samsung GrandPrimePlus LTE CIS rev04 board based on MT6737T", + "MT6737T", + "mt6737t", + "MT6737T", + "", + "MT6737T")); } diff --git a/test/name/brand-string.cc b/test/name/brand-string.cc index ec05ae2a..5cc9ba53 100644 --- a/test/name/brand-string.cc +++ b/test/name/brand-string.cc @@ -1,13 +1,10 @@ #include -#include #include #include +#include - -extern "C" uint32_t cpuinfo_x86_normalize_brand_string( - const char* raw_name, char* normalized_name); - +extern "C" uint32_t cpuinfo_x86_normalize_brand_string(const char* raw_name, char* normalized_name); inline std::string normalize_brand_string(const char name[48]) { char normalized_name[48]; @@ -16,579 +13,399 @@ inline std::string normalize_brand_string(const char name[48]) { } TEST(BRAND_STRING, intel) { - EXPECT_EQ("", - normalize_brand_string("Genuine Intel(R) CPU @ 2.33GHz\0")); - EXPECT_EQ("", - normalize_brand_string(" Genuine Intel(R) CPU 3.00GHz\0")); - EXPECT_EQ("", - normalize_brand_string(" Genuine Intel(R) CPU @ 2.60GHz\0")); - EXPECT_EQ("", - normalize_brand_string("Genuine Intel(R) CPU 0000 @ 1.73GHz\0")); - EXPECT_EQ("", - normalize_brand_string(" Genuine Intel(R) CPU @ 728\0MHz\0")); - EXPECT_EQ("", - normalize_brand_string(" Genuine Intel(R) CPU 3.46GHz\0")); - EXPECT_EQ("", - normalize_brand_string(" Genuine Intel(R) CPU @ 1.66GHz\0")); - EXPECT_EQ("", - normalize_brand_string("Genuine Intel(R) CPU 0000 @ 2.40GHz\0")); - EXPECT_EQ("", - normalize_brand_string("Genuine Intel(R) processor 800MHz\0")); - EXPECT_EQ("", - normalize_brand_string(" Genuine Intel(R) CPU @ 2.40GHz\0")); - EXPECT_EQ("", - normalize_brand_string("Genuine Intel(R) CPU 0 @ 1.60GHz\0")); - EXPECT_EQ("", - normalize_brand_string("Genuine Intel(R) CPU @ 2.66GHz\0")); - EXPECT_EQ("", - normalize_brand_string("Genuine Intel(R) CPU 000 @ 2.13GHz\0")); - EXPECT_EQ("", - normalize_brand_string("Genuine Intel(R) CPU @ 0000 @ 2.67GHz\0")); - EXPECT_EQ("", - normalize_brand_string("Genuine Intel(R) CPU 000 @ 2>13GHz\0")); - EXPECT_EQ("", - normalize_brand_string("Genuine Intel(R) CPU @ 0000 @ 1.87GHz\0")); - EXPECT_EQ("", - normalize_brand_string("Genuine Intel(R) CPU @ 2.13GHz\0")); - EXPECT_EQ("", - normalize_brand_string("Genuine Intel(R) CPU 000 @ 3.20GHz\0")); - EXPECT_EQ("4000", - normalize_brand_string(" Genuine Intel(R) CPU 4000 @ 1.00GHz\0")); - EXPECT_EQ("5Y70", - normalize_brand_string("Intel(R) Processor 5Y70 CPU @ 1.10GHz\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Atom 230", - normalize_brand_string(" Intel(R) Atom(TM) CPU 230 @ 1.60GHz\0")); - EXPECT_EQ("Atom 330", - normalize_brand_string(" Intel(R) Atom(TM) CPU 330 @ 1.60GHz\0")); - EXPECT_EQ("Atom C2750", - normalize_brand_string(" Intel(R) Atom(TM) CPU C2750 @ 2.40GHz\0")); - EXPECT_EQ("Atom C2758", - normalize_brand_string(" Intel(R) Atom(TM) CPU C2758 @ 2.40GHz\0")); - EXPECT_EQ("Atom D2500", - normalize_brand_string(" Intel(R) Atom(TM) CPU D2500 @ 1.86GHz\0")); - EXPECT_EQ("Atom D2700", - normalize_brand_string(" Intel(R) Atom(TM) CPU D2700 @ 2.13GHz\0")); - EXPECT_EQ("Atom D525", - normalize_brand_string(" Intel(R) Atom(TM) CPU D525 @ 1.80GHz\0")); - EXPECT_EQ("Atom N455", - normalize_brand_string(" Intel(R) Atom(TM) CPU N455 @ 1.66GHz\0")); - EXPECT_EQ("Atom S1260", - normalize_brand_string(" Intel(R) Atom(TM) CPU S1260 @ 2.00GHz\0")); - EXPECT_EQ("Atom Z2460", - normalize_brand_string(" Intel(R) Atom(TM) CPU Z2460 @ 1.60GHz\0")); - EXPECT_EQ("Atom Z2760", - normalize_brand_string(" Intel(R) Atom(TM) CPU Z2760 @ 1.80GHz\0")); - EXPECT_EQ("Atom Z3740", - normalize_brand_string(" Intel(R) Atom(TM) CPU Z3740 @ 1.33GHz\0")); - EXPECT_EQ("Atom Z3745", - normalize_brand_string(" Intel(R) Atom(TM) CPU Z3745 @ 1.33GHz\0")); - EXPECT_EQ("Atom Z670", - normalize_brand_string(" Intel(R) Atom(TM) CPU Z670 @ 1.50GHz\0")); - EXPECT_EQ("Atom x7-Z8700", - normalize_brand_string(" Intel(R) Atom(TM) x7-Z8700 CPU @ 1.60GHz\0")); - EXPECT_EQ("Celeron 1.70GHz", - normalize_brand_string(" Intel(R) Celeron(R) CPU 1.70GHz\0")); - EXPECT_EQ("Celeron 2.00GHz", - normalize_brand_string(" Intel(R) Celeron(R) CPU 2.00GHz\0")); - EXPECT_EQ("Celeron 2.53GHz", - normalize_brand_string(" Intel(R) Celeron(R) CPU 2.53GHz\0")); - EXPECT_EQ("Celeron 215", - normalize_brand_string("Intel(R) Celeron(R) CPU 215 @ 1.33GHz\0")); - EXPECT_EQ("Celeron 420", - normalize_brand_string("Intel(R) Celeron(R) CPU 420 @ 1.60GHz\0")); - EXPECT_EQ("Celeron 600MHz", - normalize_brand_string("Intel(R) Celeron(R) processor 600MHz\0")); - EXPECT_EQ("Celeron D 3.06GHz", - normalize_brand_string(" Intel(R) Celeron(R) D CPU 3.06GHz\0")); - EXPECT_EQ("Celeron G1610", - normalize_brand_string(" Intel(R) Celeron(R) CPU G1610 @ 2.60GHz\0")); - EXPECT_EQ("Celeron J1900", - normalize_brand_string(" Intel(R) Celeron(R) CPU J1900 @ 1.99GHz\0")); - EXPECT_EQ("Celeron J3455", - normalize_brand_string("Intel(R) Celeron(R) CPU J3455 @ 1.50GHz\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Celeron M 1300MHz", - normalize_brand_string("Intel(R) Celeron(R) M processor 1300MHz\0")); - EXPECT_EQ("Celeron M 430", - normalize_brand_string("Intel(R) Celeron(R) M CPU 430 @ 1.73GHz\0")); - EXPECT_EQ("Celeron N3050", - normalize_brand_string(" Intel(R) Celeron(R) CPU N3050 @ 1.60GHz\0")); - EXPECT_EQ("Celeron N3150", - normalize_brand_string(" Intel(R) Celeron(R) CPU N3150 @ 1.60GHz\0")); - EXPECT_EQ("Core 2 6300", - normalize_brand_string("Intel(R) Core(TM)2 CPU 6300 @ 1.86GHz\0")); - EXPECT_EQ("Core 2 6700", - normalize_brand_string("Intel(R) Core(TM)2 CPU 6700 @ 2.66GHz\0")); - EXPECT_EQ("Core 2 Duo P8400", - normalize_brand_string("Intel(R) Core(TM)2 Duo CPU P8400 @ 2.26GHz\0")); - EXPECT_EQ("Core 2 Duo T8300", - normalize_brand_string("Intel(R) Core(TM)2 Duo CPU T8300 @ 2.40GHz\0")); - EXPECT_EQ("Core 2 Extreme X9650", - normalize_brand_string("Intel(R) Core(TM)2 Extreme CPU X9650 @ 3.00GHz\0")); - EXPECT_EQ("Core 2 Quad 2.66GHz", - normalize_brand_string("Intel(R) Core(TM)2 Quad CPU @ 2.66GHz\0")); - EXPECT_EQ("Core 2 Quad Q6600", - normalize_brand_string("Intel(R) Core(TM)2 Quad CPU Q6600 @ 2.40GHz\0")); - EXPECT_EQ("Core 2 Quad Q9300", - normalize_brand_string("Intel(R) Core(TM)2 Quad CPU Q9300 @ 2.50GHz\0")); - EXPECT_EQ("Core 2 T5600", - normalize_brand_string("Intel(R) Core(TM)2 CPU T5600 @ 1.83GHz\0")); - EXPECT_EQ("Core 820Q", - normalize_brand_string("Intel(R) Core(TM) CPU Q 820 @ 1.73GHz\0")); - EXPECT_EQ("Core i3 380M", - normalize_brand_string("Intel(R) Core(TM) i3 CPU M 380 @ 2.53GHz\0")); - EXPECT_EQ("Core i5 480M", - normalize_brand_string("Intel(R) Core(TM) i5 CPU M 480 @ 2.67GHz\0")); - EXPECT_EQ("Core i5 650", - normalize_brand_string("Intel(R) Core(TM) i5 CPU 650 @ 3.20GHz\0")); - EXPECT_EQ("Core i5 750", - normalize_brand_string("Intel(R) Core(TM) i5 CPU 750 @ 2.67GHz\0")); - EXPECT_EQ("Core i5-2400", - normalize_brand_string(" Intel(R) Core(TM) i5-2400 CPU @ 3.10GHz\0")); - EXPECT_EQ("Core i5-2450M", - normalize_brand_string(" Intel(R) Core(TM) i5-2450M CPU @ 2.50GHz\0")); - EXPECT_EQ("Core i5-5250U", - normalize_brand_string("Intel(R) Core(TM) i5-5250U CPU @ 1.60GHz\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Core i5-6400T", - normalize_brand_string("Intel(R) Core(TM) i5-6400T CPU @ 2.20GHz\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Core i5-7200U", - normalize_brand_string("Intel(R) Core(TM) i5-7200U CPU @ 2.50GHz\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Core i7 720Q", - normalize_brand_string("Intel(R) Core(TM) i7 CPU Q 720 @ 1.60GHz\0")); - EXPECT_EQ("Core i7 860", - normalize_brand_string("Intel(R) Core(TM) i7 CPU 860 @ 2.80GHz\0")); - EXPECT_EQ("Core i7 990X", - normalize_brand_string("Intel(R) Core(TM) i7 CPU X 990 @ 3.47GHz\0")); - EXPECT_EQ("Core i7-2600", - normalize_brand_string(" Intel(R) Core(TM) i7-2600 CPU @ 3.40GHz\0")); - EXPECT_EQ("Core i7-2600K", - normalize_brand_string(" Intel(R) Core(TM) i7-2600K CPU @ 3.40GHz\0")); - EXPECT_EQ("Core i7-3770K", - normalize_brand_string(" Intel(R) Core(TM) i7-3770K CPU @ 3.50GHz\0")); - EXPECT_EQ("Core i7-3960X", - normalize_brand_string(" Intel(R) Core(TM) i7-3960X CPU @ 3.30GHz\0")); - EXPECT_EQ("Core i7-4500U", - normalize_brand_string("Intel(R) Core(TM) i7-4500U CPU @ 1.80GHz\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Core i7-4770", - normalize_brand_string("Intel(R) Core(TM) i7-4770 CPU @ 3.40GHz\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Core i7-4770R", - normalize_brand_string("Intel(R) Core(TM) i7-4770R CPU @ 3.20GHz\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Core i7-4930K", - normalize_brand_string(" Intel(R) Core(TM) i7-4930K CPU @ 3.40GHz\0")); - EXPECT_EQ("Core i7-5775C", - normalize_brand_string("Intel(R) Core(TM) i7-5775C CPU @ 3.30GHz\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Core i7-5820K", - normalize_brand_string("Intel(R) Core(TM) i7-5820K CPU @ 3.30GHz\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Core i7-6500U", - normalize_brand_string("Intel(R) Core(TM) i7-6500U CPU @ 2.50GHz\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Core i7-6800K", - normalize_brand_string("Intel(R) Core(TM) i7-6800K CPU @ 3.40GHz\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Core i7-6850K", - normalize_brand_string("Intel(R) Core(TM) i7-6850K CPU @ 3.60GHz\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Core i7-6950X", - normalize_brand_string("Intel(R) Core(TM) i7-6950X CPU @ 3.00GHz\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Core i7-7700K", - normalize_brand_string("Intel(R) Core(TM) i7-7700K CPU @ 4.20GHz\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Core i7-7800X", - normalize_brand_string("Intel(R) Core(TM) i7-7800X CPU @ 3.50GHz\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Core i9-7900X", - normalize_brand_string("Intel(R) Core(TM) i9-7900X CPU @ 3.30GHz\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Core m3-6Y30", - normalize_brand_string("Intel(R) Core(TM) m3-6Y30 CPU @ 0.90GHz\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Pentium 4 1.60GHz", - normalize_brand_string(" Intel(R) Pentium(R) 4 CPU 1.60GHz\0")); - EXPECT_EQ("Pentium 4 2.40GHz", - normalize_brand_string(" Intel(R) Pentium(R) 4 CPU 2.40GHz\0")); - EXPECT_EQ("Pentium 4 2.80GHz", - normalize_brand_string(" Intel(R) Pentium(R) 4 CPU 2.80GHz\0")); - EXPECT_EQ("Pentium 4 3.00GHz", - normalize_brand_string(" Intel(R) Pentium(R) 4 CPU 3.00GHz\0")); - EXPECT_EQ("Pentium 4 3.20GHz", - normalize_brand_string(" Intel(R) Pentium(R) 4 CPU 3.20GHz\0")); - EXPECT_EQ("Pentium 4 3.46GHz", - normalize_brand_string(" Intel(R) Pentium(R) 4 CPU 3.46GHz\0")); - EXPECT_EQ("Pentium 4 3.73GHz", - normalize_brand_string(" Intel(R) Pentium(R) 4 CPU 3.73GHz\0")); - EXPECT_EQ("Pentium D 2.80GHz", - normalize_brand_string(" Intel(R) Pentium(R) D CPU 2.80GHz\0")); - EXPECT_EQ("Pentium Dual E2220", - normalize_brand_string("Intel(R) Pentium(R) Dual CPU E2220 @ 2.40GHz\0")); - EXPECT_EQ("Pentium G840", - normalize_brand_string(" Intel(R) Pentium(R) CPU G840 @ 2.80GHz\0")); - EXPECT_EQ("Pentium III 1266MHz", - normalize_brand_string("Intel(R) Pentium(R) III CPU family 1266MHz\0")); - EXPECT_EQ("Pentium M 1.60GHz", - normalize_brand_string(" Intel(R) Pentium(R) M processor 1.60GHz\0")); - EXPECT_EQ("Pentium M 2.00GHz", - normalize_brand_string("Intel(R) Pentium(R) M CPU 000 @ 2.00GHz\0")); - EXPECT_EQ("Pentium N4200", - normalize_brand_string("Intel(R) Pentium(R) CPU N4200 @ 1.10GHz\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Pentium T4200", - normalize_brand_string("Pentium(R) Dual-Core CPU T4200 @ 2.00GHz\0")); - EXPECT_EQ("Pentium T4500", - normalize_brand_string("Pentium(R) Dual-Core CPU T4500 @ 2.30GHz\0")); - EXPECT_EQ("Xeon 2.66GHz", - normalize_brand_string(" Intel(R) Xeon(TM) CPU 2.66GHz\0")); - EXPECT_EQ("Xeon 2.80GHz", - normalize_brand_string(" Intel(R) Xeon(TM) CPU 2.80GHz\0")); - EXPECT_EQ("Xeon 3.06GHz", - normalize_brand_string(" Intel(R) Xeon(TM) CPU 3.06GHz\0")); - EXPECT_EQ("Xeon 3.20GHz", - normalize_brand_string(" Intel(R) Xeon(TM) CPU 3.20GHz\0")); - EXPECT_EQ("Xeon 3.40GHz", - normalize_brand_string(" Intel(R) Xeon(TM) CPU 3.40GHz\0")); - EXPECT_EQ("Xeon D-1540", - normalize_brand_string("Intel(R) Xeon(R) CPU D-1540 @ 2.00GHz\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Xeon E3-1230 v2", - normalize_brand_string(" Intel(R) Xeon(R) CPU E3-1230 V2 @ 3.30GHz\0")); - EXPECT_EQ("Xeon E3-1245 v3", - normalize_brand_string("Intel(R) Xeon(R) CPU E3-1245 v3 @ 3.40GHz\0\0\0\0\0\0\0")); - EXPECT_EQ("Xeon E5-2660 v3", - normalize_brand_string("Intel(R) Xeon(R) CPU E5-2660 v3 @ 2.60GHz\0\0\0\0\0\0\0")); - EXPECT_EQ("Xeon E5-2696 v4", - normalize_brand_string("Intel(R) Xeon(R) CPU E5-2696 v4 @ 2.20GHz\0\0\0\0\0\0\0")); - EXPECT_EQ("Xeon E5-2697 v2", - normalize_brand_string(" Intel(R) Xeon(R) CPU E5-2697 v2 @ 2.70GHz\0")); - EXPECT_EQ("Xeon E5-2697 v4", - normalize_brand_string("Intel(R) Xeon(R) CPU E5-2697 v4 @ 2.30GHz\0\0\0\0\0\0\0")); - EXPECT_EQ("Xeon E5-2699 v3", - normalize_brand_string("Intel(R) Xeon(R) CPU E5-2699 v3 @ 2.30GHz\0\0\0\0\0\0\0")); - EXPECT_EQ("Xeon E5462", - normalize_brand_string("Intel(R) Xeon(R) CPU E5462 @ 2.80GHz\0")); - EXPECT_EQ("Xeon E7-4870", - normalize_brand_string(" Intel(R) Xeon(R) CPU E7- 4870 @ 2.40GHz\0")); - EXPECT_EQ("Xeon E7-8870", - normalize_brand_string(" Intel(R) Xeon(R) CPU E7- 8870 @ 2.40GHz\0")); - EXPECT_EQ("Xeon E7450", - normalize_brand_string("Intel(R) Xeon(R) CPU E7450 @ 2.40GHz\0")); - EXPECT_EQ("Xeon E7520", - normalize_brand_string("Intel(R) Xeon(R) CPU E7520 @ 1.87GHz\0")); - EXPECT_EQ("Xeon Gold 6130", - normalize_brand_string("Intel(R) Xeon(R) Gold 6130 CPU @ 2.10GHz\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Xeon Gold 6154", - normalize_brand_string("Intel(R) Xeon(R) Gold 6154 CPU @ 3.00GHz\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Xeon L5320", - normalize_brand_string("Intel(R) Xeon(R) CPU L5320 @ 1.86GHz\0")); - EXPECT_EQ("Xeon Phi 7210", - normalize_brand_string("Intel(R) Xeon Phi(TM) CPU 7210 @ 1.30GHz\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Xeon Platinum 8180", - normalize_brand_string("Intel(R) Xeon(R) Platinum 8180 CPU @ 2.50GHz\0\0\0\0")); - EXPECT_EQ("Xeon X3210", - normalize_brand_string("Intel(R) Xeon(R) CPU X3210 @ 2.13GHz\0")); - EXPECT_EQ("Xeon X3323", - normalize_brand_string("Intel(R) Xeon(R) CPU X3323 @ 2.50GHz\0")); - EXPECT_EQ("Xeon X5667", - normalize_brand_string("Intel(R) Xeon(R) CPU X5667 @ 3.07GHz\0")); - EXPECT_EQ("Xeon X6550", - normalize_brand_string("Intel(R) Xeon(R) CPU X6550 @ 2.00GHz\0")); + EXPECT_EQ("", normalize_brand_string("Genuine Intel(R) CPU @ 2.33GHz\0")); + EXPECT_EQ("", normalize_brand_string(" Genuine Intel(R) CPU 3.00GHz\0")); + EXPECT_EQ("", normalize_brand_string(" Genuine Intel(R) CPU @ 2.60GHz\0")); + EXPECT_EQ("", normalize_brand_string("Genuine Intel(R) CPU 0000 @ 1.73GHz\0")); + EXPECT_EQ("", normalize_brand_string(" Genuine Intel(R) CPU @ 728\0MHz\0")); + EXPECT_EQ("", normalize_brand_string(" Genuine Intel(R) CPU 3.46GHz\0")); + EXPECT_EQ("", normalize_brand_string(" Genuine Intel(R) CPU @ 1.66GHz\0")); + EXPECT_EQ("", normalize_brand_string("Genuine Intel(R) CPU 0000 @ 2.40GHz\0")); + EXPECT_EQ("", normalize_brand_string("Genuine Intel(R) processor 800MHz\0")); + EXPECT_EQ("", normalize_brand_string(" Genuine Intel(R) CPU @ 2.40GHz\0")); + EXPECT_EQ("", normalize_brand_string("Genuine Intel(R) CPU 0 @ 1.60GHz\0")); + EXPECT_EQ("", normalize_brand_string("Genuine Intel(R) CPU @ 2.66GHz\0")); + EXPECT_EQ("", normalize_brand_string("Genuine Intel(R) CPU 000 @ 2.13GHz\0")); + EXPECT_EQ("", normalize_brand_string("Genuine Intel(R) CPU @ 0000 @ 2.67GHz\0")); + EXPECT_EQ("", normalize_brand_string("Genuine Intel(R) CPU 000 @ 2>13GHz\0")); + EXPECT_EQ("", normalize_brand_string("Genuine Intel(R) CPU @ 0000 @ 1.87GHz\0")); + EXPECT_EQ("", normalize_brand_string("Genuine Intel(R) CPU @ 2.13GHz\0")); + EXPECT_EQ("", normalize_brand_string("Genuine Intel(R) CPU 000 @ 3.20GHz\0")); + EXPECT_EQ("4000", normalize_brand_string(" Genuine Intel(R) CPU 4000 @ 1.00GHz\0")); + EXPECT_EQ("5Y70", normalize_brand_string("Intel(R) Processor 5Y70 CPU @ 1.10GHz\0\0\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Atom 230", normalize_brand_string(" Intel(R) Atom(TM) CPU 230 @ 1.60GHz\0")); + EXPECT_EQ("Atom 330", normalize_brand_string(" Intel(R) Atom(TM) CPU 330 @ 1.60GHz\0")); + EXPECT_EQ("Atom C2750", normalize_brand_string(" Intel(R) Atom(TM) CPU C2750 @ 2.40GHz\0")); + EXPECT_EQ("Atom C2758", normalize_brand_string(" Intel(R) Atom(TM) CPU C2758 @ 2.40GHz\0")); + EXPECT_EQ("Atom D2500", normalize_brand_string(" Intel(R) Atom(TM) CPU D2500 @ 1.86GHz\0")); + EXPECT_EQ("Atom D2700", normalize_brand_string(" Intel(R) Atom(TM) CPU D2700 @ 2.13GHz\0")); + EXPECT_EQ("Atom D525", normalize_brand_string(" Intel(R) Atom(TM) CPU D525 @ 1.80GHz\0")); + EXPECT_EQ("Atom N455", normalize_brand_string(" Intel(R) Atom(TM) CPU N455 @ 1.66GHz\0")); + EXPECT_EQ("Atom S1260", normalize_brand_string(" Intel(R) Atom(TM) CPU S1260 @ 2.00GHz\0")); + EXPECT_EQ("Atom Z2460", normalize_brand_string(" Intel(R) Atom(TM) CPU Z2460 @ 1.60GHz\0")); + EXPECT_EQ("Atom Z2760", normalize_brand_string(" Intel(R) Atom(TM) CPU Z2760 @ 1.80GHz\0")); + EXPECT_EQ("Atom Z3740", normalize_brand_string(" Intel(R) Atom(TM) CPU Z3740 @ 1.33GHz\0")); + EXPECT_EQ("Atom Z3745", normalize_brand_string(" Intel(R) Atom(TM) CPU Z3745 @ 1.33GHz\0")); + EXPECT_EQ("Atom Z670", normalize_brand_string(" Intel(R) Atom(TM) CPU Z670 @ 1.50GHz\0")); + EXPECT_EQ("Atom x7-Z8700", normalize_brand_string(" Intel(R) Atom(TM) x7-Z8700 CPU @ 1.60GHz\0")); + EXPECT_EQ("Celeron 1.70GHz", normalize_brand_string(" Intel(R) Celeron(R) CPU 1.70GHz\0")); + EXPECT_EQ("Celeron 2.00GHz", normalize_brand_string(" Intel(R) Celeron(R) CPU 2.00GHz\0")); + EXPECT_EQ("Celeron 2.53GHz", normalize_brand_string(" Intel(R) Celeron(R) CPU 2.53GHz\0")); + EXPECT_EQ("Celeron 215", normalize_brand_string("Intel(R) Celeron(R) CPU 215 @ 1.33GHz\0")); + EXPECT_EQ("Celeron 420", normalize_brand_string("Intel(R) Celeron(R) CPU 420 @ 1.60GHz\0")); + EXPECT_EQ("Celeron 600MHz", normalize_brand_string("Intel(R) Celeron(R) processor 600MHz\0")); + EXPECT_EQ("Celeron D 3.06GHz", normalize_brand_string(" Intel(R) Celeron(R) D CPU 3.06GHz\0")); + EXPECT_EQ("Celeron G1610", normalize_brand_string(" Intel(R) Celeron(R) CPU G1610 @ 2.60GHz\0")); + EXPECT_EQ("Celeron J1900", normalize_brand_string(" Intel(R) Celeron(R) CPU J1900 @ 1.99GHz\0")); + EXPECT_EQ("Celeron J3455", normalize_brand_string("Intel(R) Celeron(R) CPU J3455 @ 1.50GHz\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Celeron M 1300MHz", normalize_brand_string("Intel(R) Celeron(R) M processor 1300MHz\0")); + EXPECT_EQ("Celeron M 430", normalize_brand_string("Intel(R) Celeron(R) M CPU 430 @ 1.73GHz\0")); + EXPECT_EQ("Celeron N3050", normalize_brand_string(" Intel(R) Celeron(R) CPU N3050 @ 1.60GHz\0")); + EXPECT_EQ("Celeron N3150", normalize_brand_string(" Intel(R) Celeron(R) CPU N3150 @ 1.60GHz\0")); + EXPECT_EQ("Core 2 6300", normalize_brand_string("Intel(R) Core(TM)2 CPU 6300 @ 1.86GHz\0")); + EXPECT_EQ("Core 2 6700", normalize_brand_string("Intel(R) Core(TM)2 CPU 6700 @ 2.66GHz\0")); + EXPECT_EQ("Core 2 Duo P8400", normalize_brand_string("Intel(R) Core(TM)2 Duo CPU P8400 @ 2.26GHz\0")); + EXPECT_EQ("Core 2 Duo T8300", normalize_brand_string("Intel(R) Core(TM)2 Duo CPU T8300 @ 2.40GHz\0")); + EXPECT_EQ("Core 2 Extreme X9650", normalize_brand_string("Intel(R) Core(TM)2 Extreme CPU X9650 @ 3.00GHz\0")); + EXPECT_EQ("Core 2 Quad 2.66GHz", normalize_brand_string("Intel(R) Core(TM)2 Quad CPU @ 2.66GHz\0")); + EXPECT_EQ("Core 2 Quad Q6600", normalize_brand_string("Intel(R) Core(TM)2 Quad CPU Q6600 @ 2.40GHz\0")); + EXPECT_EQ("Core 2 Quad Q9300", normalize_brand_string("Intel(R) Core(TM)2 Quad CPU Q9300 @ 2.50GHz\0")); + EXPECT_EQ("Core 2 T5600", normalize_brand_string("Intel(R) Core(TM)2 CPU T5600 @ 1.83GHz\0")); + EXPECT_EQ("Core 820Q", normalize_brand_string("Intel(R) Core(TM) CPU Q 820 @ 1.73GHz\0")); + EXPECT_EQ("Core i3 380M", normalize_brand_string("Intel(R) Core(TM) i3 CPU M 380 @ 2.53GHz\0")); + EXPECT_EQ("Core i5 480M", normalize_brand_string("Intel(R) Core(TM) i5 CPU M 480 @ 2.67GHz\0")); + EXPECT_EQ("Core i5 650", normalize_brand_string("Intel(R) Core(TM) i5 CPU 650 @ 3.20GHz\0")); + EXPECT_EQ("Core i5 750", normalize_brand_string("Intel(R) Core(TM) i5 CPU 750 @ 2.67GHz\0")); + EXPECT_EQ("Core i5-2400", normalize_brand_string(" Intel(R) Core(TM) i5-2400 CPU @ 3.10GHz\0")); + EXPECT_EQ("Core i5-2450M", normalize_brand_string(" Intel(R) Core(TM) i5-2450M CPU @ 2.50GHz\0")); + EXPECT_EQ("Core i5-5250U", normalize_brand_string("Intel(R) Core(TM) i5-5250U CPU @ 1.60GHz\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Core i5-6400T", normalize_brand_string("Intel(R) Core(TM) i5-6400T CPU @ 2.20GHz\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Core i5-7200U", normalize_brand_string("Intel(R) Core(TM) i5-7200U CPU @ 2.50GHz\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Core i7 720Q", normalize_brand_string("Intel(R) Core(TM) i7 CPU Q 720 @ 1.60GHz\0")); + EXPECT_EQ("Core i7 860", normalize_brand_string("Intel(R) Core(TM) i7 CPU 860 @ 2.80GHz\0")); + EXPECT_EQ("Core i7 990X", normalize_brand_string("Intel(R) Core(TM) i7 CPU X 990 @ 3.47GHz\0")); + EXPECT_EQ("Core i7-2600", normalize_brand_string(" Intel(R) Core(TM) i7-2600 CPU @ 3.40GHz\0")); + EXPECT_EQ("Core i7-2600K", normalize_brand_string(" Intel(R) Core(TM) i7-2600K CPU @ 3.40GHz\0")); + EXPECT_EQ("Core i7-3770K", normalize_brand_string(" Intel(R) Core(TM) i7-3770K CPU @ 3.50GHz\0")); + EXPECT_EQ("Core i7-3960X", normalize_brand_string(" Intel(R) Core(TM) i7-3960X CPU @ 3.30GHz\0")); + EXPECT_EQ("Core i7-4500U", normalize_brand_string("Intel(R) Core(TM) i7-4500U CPU @ 1.80GHz\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Core i7-4770", normalize_brand_string("Intel(R) Core(TM) i7-4770 CPU @ 3.40GHz\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Core i7-4770R", normalize_brand_string("Intel(R) Core(TM) i7-4770R CPU @ 3.20GHz\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Core i7-4930K", normalize_brand_string(" Intel(R) Core(TM) i7-4930K CPU @ 3.40GHz\0")); + EXPECT_EQ("Core i7-5775C", normalize_brand_string("Intel(R) Core(TM) i7-5775C CPU @ 3.30GHz\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Core i7-5820K", normalize_brand_string("Intel(R) Core(TM) i7-5820K CPU @ 3.30GHz\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Core i7-6500U", normalize_brand_string("Intel(R) Core(TM) i7-6500U CPU @ 2.50GHz\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Core i7-6800K", normalize_brand_string("Intel(R) Core(TM) i7-6800K CPU @ 3.40GHz\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Core i7-6850K", normalize_brand_string("Intel(R) Core(TM) i7-6850K CPU @ 3.60GHz\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Core i7-6950X", normalize_brand_string("Intel(R) Core(TM) i7-6950X CPU @ 3.00GHz\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Core i7-7700K", normalize_brand_string("Intel(R) Core(TM) i7-7700K CPU @ 4.20GHz\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Core i7-7800X", normalize_brand_string("Intel(R) Core(TM) i7-7800X CPU @ 3.50GHz\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Core i9-7900X", normalize_brand_string("Intel(R) Core(TM) i9-7900X CPU @ 3.30GHz\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Core m3-6Y30", normalize_brand_string("Intel(R) Core(TM) m3-6Y30 CPU @ 0.90GHz\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Pentium 4 1.60GHz", normalize_brand_string(" Intel(R) Pentium(R) 4 CPU 1.60GHz\0")); + EXPECT_EQ("Pentium 4 2.40GHz", normalize_brand_string(" Intel(R) Pentium(R) 4 CPU 2.40GHz\0")); + EXPECT_EQ("Pentium 4 2.80GHz", normalize_brand_string(" Intel(R) Pentium(R) 4 CPU 2.80GHz\0")); + EXPECT_EQ("Pentium 4 3.00GHz", normalize_brand_string(" Intel(R) Pentium(R) 4 CPU 3.00GHz\0")); + EXPECT_EQ("Pentium 4 3.20GHz", normalize_brand_string(" Intel(R) Pentium(R) 4 CPU 3.20GHz\0")); + EXPECT_EQ("Pentium 4 3.46GHz", normalize_brand_string(" Intel(R) Pentium(R) 4 CPU 3.46GHz\0")); + EXPECT_EQ("Pentium 4 3.73GHz", normalize_brand_string(" Intel(R) Pentium(R) 4 CPU 3.73GHz\0")); + EXPECT_EQ("Pentium D 2.80GHz", normalize_brand_string(" Intel(R) Pentium(R) D CPU 2.80GHz\0")); + EXPECT_EQ("Pentium Dual E2220", normalize_brand_string("Intel(R) Pentium(R) Dual CPU E2220 @ 2.40GHz\0")); + EXPECT_EQ("Pentium G840", normalize_brand_string(" Intel(R) Pentium(R) CPU G840 @ 2.80GHz\0")); + EXPECT_EQ("Pentium III 1266MHz", normalize_brand_string("Intel(R) Pentium(R) III CPU family 1266MHz\0")); + EXPECT_EQ("Pentium M 1.60GHz", normalize_brand_string(" Intel(R) Pentium(R) M processor 1.60GHz\0")); + EXPECT_EQ("Pentium M 2.00GHz", normalize_brand_string("Intel(R) Pentium(R) M CPU 000 @ 2.00GHz\0")); + EXPECT_EQ("Pentium N4200", normalize_brand_string("Intel(R) Pentium(R) CPU N4200 @ 1.10GHz\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Pentium T4200", normalize_brand_string("Pentium(R) Dual-Core CPU T4200 @ 2.00GHz\0")); + EXPECT_EQ("Pentium T4500", normalize_brand_string("Pentium(R) Dual-Core CPU T4500 @ 2.30GHz\0")); + EXPECT_EQ("Xeon 2.66GHz", normalize_brand_string(" Intel(R) Xeon(TM) CPU 2.66GHz\0")); + EXPECT_EQ("Xeon 2.80GHz", normalize_brand_string(" Intel(R) Xeon(TM) CPU 2.80GHz\0")); + EXPECT_EQ("Xeon 3.06GHz", normalize_brand_string(" Intel(R) Xeon(TM) CPU 3.06GHz\0")); + EXPECT_EQ("Xeon 3.20GHz", normalize_brand_string(" Intel(R) Xeon(TM) CPU 3.20GHz\0")); + EXPECT_EQ("Xeon 3.40GHz", normalize_brand_string(" Intel(R) Xeon(TM) CPU 3.40GHz\0")); + EXPECT_EQ("Xeon D-1540", normalize_brand_string("Intel(R) Xeon(R) CPU D-1540 @ 2.00GHz\0\0\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Xeon E3-1230 v2", normalize_brand_string(" Intel(R) Xeon(R) CPU E3-1230 V2 @ 3.30GHz\0")); + EXPECT_EQ("Xeon E3-1245 v3", normalize_brand_string("Intel(R) Xeon(R) CPU E3-1245 v3 @ 3.40GHz\0\0\0\0\0\0\0")); + EXPECT_EQ("Xeon E5-2660 v3", normalize_brand_string("Intel(R) Xeon(R) CPU E5-2660 v3 @ 2.60GHz\0\0\0\0\0\0\0")); + EXPECT_EQ("Xeon E5-2696 v4", normalize_brand_string("Intel(R) Xeon(R) CPU E5-2696 v4 @ 2.20GHz\0\0\0\0\0\0\0")); + EXPECT_EQ("Xeon E5-2697 v2", normalize_brand_string(" Intel(R) Xeon(R) CPU E5-2697 v2 @ 2.70GHz\0")); + EXPECT_EQ("Xeon E5-2697 v4", normalize_brand_string("Intel(R) Xeon(R) CPU E5-2697 v4 @ 2.30GHz\0\0\0\0\0\0\0")); + EXPECT_EQ("Xeon E5-2699 v3", normalize_brand_string("Intel(R) Xeon(R) CPU E5-2699 v3 @ 2.30GHz\0\0\0\0\0\0\0")); + EXPECT_EQ("Xeon E5462", normalize_brand_string("Intel(R) Xeon(R) CPU E5462 @ 2.80GHz\0")); + EXPECT_EQ("Xeon E7-4870", normalize_brand_string(" Intel(R) Xeon(R) CPU E7- 4870 @ 2.40GHz\0")); + EXPECT_EQ("Xeon E7-8870", normalize_brand_string(" Intel(R) Xeon(R) CPU E7- 8870 @ 2.40GHz\0")); + EXPECT_EQ("Xeon E7450", normalize_brand_string("Intel(R) Xeon(R) CPU E7450 @ 2.40GHz\0")); + EXPECT_EQ("Xeon E7520", normalize_brand_string("Intel(R) Xeon(R) CPU E7520 @ 1.87GHz\0")); + EXPECT_EQ("Xeon Gold 6130", normalize_brand_string("Intel(R) Xeon(R) Gold 6130 CPU @ 2.10GHz\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Xeon Gold 6154", normalize_brand_string("Intel(R) Xeon(R) Gold 6154 CPU @ 3.00GHz\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Xeon L5320", normalize_brand_string("Intel(R) Xeon(R) CPU L5320 @ 1.86GHz\0")); + EXPECT_EQ("Xeon Phi 7210", normalize_brand_string("Intel(R) Xeon Phi(TM) CPU 7210 @ 1.30GHz\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Xeon Platinum 8180", normalize_brand_string("Intel(R) Xeon(R) Platinum 8180 CPU @ 2.50GHz\0\0\0\0")); + EXPECT_EQ("Xeon X3210", normalize_brand_string("Intel(R) Xeon(R) CPU X3210 @ 2.13GHz\0")); + EXPECT_EQ("Xeon X3323", normalize_brand_string("Intel(R) Xeon(R) CPU X3323 @ 2.50GHz\0")); + EXPECT_EQ("Xeon X5667", normalize_brand_string("Intel(R) Xeon(R) CPU X5667 @ 3.07GHz\0")); + EXPECT_EQ("Xeon X6550", normalize_brand_string("Intel(R) Xeon(R) CPU X6550 @ 2.00GHz\0")); } TEST(BRAND_STRING, intel_android) { - EXPECT_EQ("Atom N2600", - normalize_brand_string("Intel(R) Atom(TM) CPU N2600 @ 1.60GHz\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Atom Sofia3GR", + EXPECT_EQ("Atom N2600", normalize_brand_string("Intel(R) Atom(TM) CPU N2600 @ 1.60GHz\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ( + "Atom Sofia3GR", normalize_brand_string("Intel(R) Atom(TM) CPU Sofia3GR\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Atom Z2420", - normalize_brand_string("Intel(R) Atom(TM) CPU Z2420 @ 1.20GHz\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Atom Z2460", - normalize_brand_string("Intel(R) Atom(TM) CPU Z2460 @ 1.60GHz\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Atom Z2480", - normalize_brand_string("Intel(R) Atom(TM) CPU Z2480 @ 2.00GHz\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Atom Z2520", - normalize_brand_string("Intel(R) Atom(TM) CPU Z2520 @ 1.20GHz\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Atom Z2560", - normalize_brand_string("Intel(R) Atom(TM) CPU Z2560 @ 1.60GHz\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Atom Z2580", - normalize_brand_string("Intel(R) Atom(TM) CPU Z2580 @ 2.00GHz\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Atom Z3460", - normalize_brand_string("Intel(R) Atom(TM) CPU Z3460 @ 1.06GHz\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Atom Z3480", - normalize_brand_string("Intel(R) Atom(TM) CPU Z3480 @ 1.33GHz\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Atom Z3530", - normalize_brand_string("Intel(R) Atom(TM) CPU Z3530 @ 1.33GHz\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Atom Z3530", - normalize_brand_string("Intel(R) Atom(TM) CPU Z3530 @ 1.33GHz\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Atom Z3530", - normalize_brand_string("Intel(R) Atom(TM) CPU Z3530 @ 1.33GHz\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Atom Z3560", - normalize_brand_string("Intel(R) Atom(TM) CPU Z3560 @ 1.00GHz\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Atom Z3560", - normalize_brand_string("Intel(R) Atom(TM) CPU Z3560 @ 1.83GHz\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Atom Z3560", - normalize_brand_string("Intel(R) Atom(TM) CPU Z3560 @ 1.83GHz\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Atom Z3580", - normalize_brand_string("Intel(R) Atom(TM) CPU Z3580 @ 1.33GHz\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Atom Z3580", - normalize_brand_string("Intel(R) Atom(TM) CPU Z3580 @ 2.33GHz\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Atom Z3590", - normalize_brand_string("Intel(R) Atom(TM) CPU Z3590 @ 1.33GHz\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Atom Z3735D", - normalize_brand_string("Intel(R) Atom(TM) CPU Z3735D @ 1.33GHz\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Atom Z3735E", - normalize_brand_string("Intel(R) Atom(TM) CPU Z3735E @ 1.33GHz\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Atom Z3735F", - normalize_brand_string("Intel(R) Atom(TM) CPU Z3735F @ 1.33GHz\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Atom Z3735G", - normalize_brand_string("Intel(R) Atom(TM) CPU Z3735G @ 1.33GHz\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Atom Z3736F", - normalize_brand_string("Intel(R) Atom(TM) CPU Z3736F @ 1.33GHz\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Atom Z3736G", - normalize_brand_string("Intel(R) Atom(TM) CPU Z3736G @ 1.33GHz\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Atom Z3745", - normalize_brand_string("Intel(R) Atom(TM) CPU Z3745 @ 1.33GHz\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Atom x5-Z8300", - normalize_brand_string("Intel(R) Atom(TM) x5-Z8300 CPU @ 1.44GHz\0\0\0\0\0\0\0")); - EXPECT_EQ("Atom x5-Z8350", - normalize_brand_string("Intel(R) Atom(TM) x5-Z8350 CPU @ 1.44GHz\0\0\0\0\0\0\0")); - EXPECT_EQ("Atom x5-Z8500", - normalize_brand_string("Intel(R) Atom(TM) x5-Z8500 CPU @ 1.44GHz\0\0\0\0\0\0\0")); - EXPECT_EQ("Atom x5-Z8550", - normalize_brand_string("Intel(R) Atom(TM) x5-Z8550 CPU @ 1.44GHz\0\0\0\0\0\0\0")); - EXPECT_EQ("Atom x7-Z8700", - normalize_brand_string("Intel(R) Atom(TM) x7-Z8700 CPU @ 1.60GHz\0\0\0\0\0\0\0")); - EXPECT_EQ("Atom x7-Z8750", - normalize_brand_string("Intel(R) Atom(TM) x7-Z8750 CPU @ 1.60GHz\0\0\0\0\0\0\0")); - EXPECT_EQ("Celeron 847", - normalize_brand_string("Intel(R) Celeron(R) CPU 847 @ 1.10GHz\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Celeron N3060", - normalize_brand_string("Intel(R) Celeron(R) CPU N3060 @ 1.60GHz\0\0\0\0\0\0\0")); - EXPECT_EQ("Celeron N3160", - normalize_brand_string("Intel(R) Celeron(R) CPU N3160 @ 1.60GHz\0\0\0\0\0\0\0")); - EXPECT_EQ("Core i3-2100", - normalize_brand_string("Intel(R) Core(TM) i3-2100 CPU @ 3.10GHz\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Core i3-2120", - normalize_brand_string("Intel(R) Core(TM) i3-2120 CPU @ 3.30GHz\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Core i3-3110M", - normalize_brand_string("Intel(R) Core(TM) i3-3110M CPU @ 2.40GHz\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Core i3-3217U", - normalize_brand_string("Intel(R) Core(TM) i3-3217U CPU @ 1.80GHz\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Core i3-3220", - normalize_brand_string("Intel(R) Core(TM) i3-3220 CPU @ 3.30GHz\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Core i3-4005U", - normalize_brand_string("Intel(R) Core(TM) i3-4005U CPU @ 1.70GHz\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Core i3-5005U", - normalize_brand_string("Intel(R) Core(TM) i3-5005U CPU @ 2.00GHz\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Core i5-2467M", - normalize_brand_string("Intel(R) Core(TM) i5-2467M CPU @ 1.60GHz\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Core i5-3210M", - normalize_brand_string("Intel(R) Core(TM) i5-3210M CPU @ 2.50GHz\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Core i5-3230M", - normalize_brand_string("Intel(R) Core(TM) i5-3230M CPU @ 2.60GHz\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Core i5-3470", - normalize_brand_string("Intel(R) Core(TM) i5-3470 CPU @ 3.20GHz\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Core i5-4210U", - normalize_brand_string("Intel(R) Core(TM) i5-4210U CPU @ 1.70GHz\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Core i5-4460", - normalize_brand_string("Intel(R) Core(TM) i5-4460 CPU @ 3.20GHz\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Core i5-5200U", - normalize_brand_string("Intel(R) Core(TM) i5-5200U CPU @ 2.20GHz\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Core i5-6200U", - normalize_brand_string("Intel(R) Core(TM) i5-6200U CPU @ 2.30GHz\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Core i5-6400", - normalize_brand_string("Intel(R) Core(TM) i5-6400 CPU @ 2.70GHz\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Core i7-4790", - normalize_brand_string("Intel(R) Core(TM) i7-4790 CPU @ 3.60GHz\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Atom Z2420", normalize_brand_string("Intel(R) Atom(TM) CPU Z2420 @ 1.20GHz\0\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Atom Z2460", normalize_brand_string("Intel(R) Atom(TM) CPU Z2460 @ 1.60GHz\0\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Atom Z2480", normalize_brand_string("Intel(R) Atom(TM) CPU Z2480 @ 2.00GHz\0\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Atom Z2520", normalize_brand_string("Intel(R) Atom(TM) CPU Z2520 @ 1.20GHz\0\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Atom Z2560", normalize_brand_string("Intel(R) Atom(TM) CPU Z2560 @ 1.60GHz\0\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Atom Z2580", normalize_brand_string("Intel(R) Atom(TM) CPU Z2580 @ 2.00GHz\0\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Atom Z3460", normalize_brand_string("Intel(R) Atom(TM) CPU Z3460 @ 1.06GHz\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Atom Z3480", normalize_brand_string("Intel(R) Atom(TM) CPU Z3480 @ 1.33GHz\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Atom Z3530", normalize_brand_string("Intel(R) Atom(TM) CPU Z3530 @ 1.33GHz\0\0\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Atom Z3530", normalize_brand_string("Intel(R) Atom(TM) CPU Z3530 @ 1.33GHz\0\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Atom Z3530", normalize_brand_string("Intel(R) Atom(TM) CPU Z3530 @ 1.33GHz\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Atom Z3560", normalize_brand_string("Intel(R) Atom(TM) CPU Z3560 @ 1.00GHz\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Atom Z3560", normalize_brand_string("Intel(R) Atom(TM) CPU Z3560 @ 1.83GHz\0\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Atom Z3560", normalize_brand_string("Intel(R) Atom(TM) CPU Z3560 @ 1.83GHz\0\0\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Atom Z3580", normalize_brand_string("Intel(R) Atom(TM) CPU Z3580 @ 1.33GHz\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Atom Z3580", normalize_brand_string("Intel(R) Atom(TM) CPU Z3580 @ 2.33GHz\0\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Atom Z3590", normalize_brand_string("Intel(R) Atom(TM) CPU Z3590 @ 1.33GHz\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Atom Z3735D", normalize_brand_string("Intel(R) Atom(TM) CPU Z3735D @ 1.33GHz\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Atom Z3735E", normalize_brand_string("Intel(R) Atom(TM) CPU Z3735E @ 1.33GHz\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Atom Z3735F", normalize_brand_string("Intel(R) Atom(TM) CPU Z3735F @ 1.33GHz\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Atom Z3735G", normalize_brand_string("Intel(R) Atom(TM) CPU Z3735G @ 1.33GHz\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Atom Z3736F", normalize_brand_string("Intel(R) Atom(TM) CPU Z3736F @ 1.33GHz\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Atom Z3736G", normalize_brand_string("Intel(R) Atom(TM) CPU Z3736G @ 1.33GHz\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Atom Z3745", normalize_brand_string("Intel(R) Atom(TM) CPU Z3745 @ 1.33GHz\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Atom x5-Z8300", normalize_brand_string("Intel(R) Atom(TM) x5-Z8300 CPU @ 1.44GHz\0\0\0\0\0\0\0")); + EXPECT_EQ("Atom x5-Z8350", normalize_brand_string("Intel(R) Atom(TM) x5-Z8350 CPU @ 1.44GHz\0\0\0\0\0\0\0")); + EXPECT_EQ("Atom x5-Z8500", normalize_brand_string("Intel(R) Atom(TM) x5-Z8500 CPU @ 1.44GHz\0\0\0\0\0\0\0")); + EXPECT_EQ("Atom x5-Z8550", normalize_brand_string("Intel(R) Atom(TM) x5-Z8550 CPU @ 1.44GHz\0\0\0\0\0\0\0")); + EXPECT_EQ("Atom x7-Z8700", normalize_brand_string("Intel(R) Atom(TM) x7-Z8700 CPU @ 1.60GHz\0\0\0\0\0\0\0")); + EXPECT_EQ("Atom x7-Z8750", normalize_brand_string("Intel(R) Atom(TM) x7-Z8750 CPU @ 1.60GHz\0\0\0\0\0\0\0")); + EXPECT_EQ("Celeron 847", normalize_brand_string("Intel(R) Celeron(R) CPU 847 @ 1.10GHz\0\0\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Celeron N3060", normalize_brand_string("Intel(R) Celeron(R) CPU N3060 @ 1.60GHz\0\0\0\0\0\0\0")); + EXPECT_EQ("Celeron N3160", normalize_brand_string("Intel(R) Celeron(R) CPU N3160 @ 1.60GHz\0\0\0\0\0\0\0")); + EXPECT_EQ("Core i3-2100", normalize_brand_string("Intel(R) Core(TM) i3-2100 CPU @ 3.10GHz\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Core i3-2120", normalize_brand_string("Intel(R) Core(TM) i3-2120 CPU @ 3.30GHz\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Core i3-3110M", normalize_brand_string("Intel(R) Core(TM) i3-3110M CPU @ 2.40GHz\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Core i3-3217U", normalize_brand_string("Intel(R) Core(TM) i3-3217U CPU @ 1.80GHz\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Core i3-3220", normalize_brand_string("Intel(R) Core(TM) i3-3220 CPU @ 3.30GHz\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Core i3-4005U", normalize_brand_string("Intel(R) Core(TM) i3-4005U CPU @ 1.70GHz\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Core i3-5005U", normalize_brand_string("Intel(R) Core(TM) i3-5005U CPU @ 2.00GHz\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Core i5-2467M", normalize_brand_string("Intel(R) Core(TM) i5-2467M CPU @ 1.60GHz\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Core i5-3210M", normalize_brand_string("Intel(R) Core(TM) i5-3210M CPU @ 2.50GHz\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Core i5-3230M", normalize_brand_string("Intel(R) Core(TM) i5-3230M CPU @ 2.60GHz\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Core i5-3470", normalize_brand_string("Intel(R) Core(TM) i5-3470 CPU @ 3.20GHz\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Core i5-4210U", normalize_brand_string("Intel(R) Core(TM) i5-4210U CPU @ 1.70GHz\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Core i5-4460", normalize_brand_string("Intel(R) Core(TM) i5-4460 CPU @ 3.20GHz\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Core i5-5200U", normalize_brand_string("Intel(R) Core(TM) i5-5200U CPU @ 2.20GHz\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Core i5-6200U", normalize_brand_string("Intel(R) Core(TM) i5-6200U CPU @ 2.30GHz\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Core i5-6400", normalize_brand_string("Intel(R) Core(TM) i5-6400 CPU @ 2.70GHz\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Core i7-4790", normalize_brand_string("Intel(R) Core(TM) i7-4790 CPU @ 3.60GHz\0\0\0\0\0\0\0\0\0")); } TEST(BRAND_STRING, amd) { - EXPECT_EQ("", - normalize_brand_string("AMD Processor model unknown\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("", + EXPECT_EQ("", normalize_brand_string("AMD Processor model unknown\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ( + "", normalize_brand_string("AMD Engineering Sample\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("A10-4600M", - normalize_brand_string("AMD A10-4600M APU with Radeon(tm) HD Graphics \0")); - EXPECT_EQ("A10-5800K", - normalize_brand_string("AMD A10-5800K APU with Radeon(tm) HD Graphics \0")); - EXPECT_EQ("A10-6800K", - normalize_brand_string("AMD A10-6800K APU with Radeon(tm) HD Graphics \0")); - EXPECT_EQ("A10-7850K", - normalize_brand_string("AMD A10-7850K APU with Radeon(TM) R7 Graphics \0")); - EXPECT_EQ("A12-9700P", - normalize_brand_string("AMD A12-9700P RADEON R7, 10 COMPUTE CORES 4C+6G\0")); - EXPECT_EQ("A12-9800", - normalize_brand_string("AMD A12-9800 RADEON R7, 12 COMPUTE CORES 4C+8G \0")); - EXPECT_EQ("A4-5000", - normalize_brand_string("AMD A4-5000 APU with Radeon(TM) HD Graphics \0")); - EXPECT_EQ("A6-6310", - normalize_brand_string("AMD A6-6310 APU with AMD Radeon R4 Graphics \0")); - EXPECT_EQ("A8-3850", - normalize_brand_string("AMD A8-3850 APU with Radeon(tm) HD Graphics\0\0\0\0\0")); - EXPECT_EQ("A8-6410", - normalize_brand_string("AMD A8-6410 APU with AMD Radeon R5 Graphics \0")); - EXPECT_EQ("A8-7670K", - normalize_brand_string("AMD A8-7670K Radeon R7, 10 Compute Cores 4C+6G \0")); - EXPECT_EQ("A9-9410", - normalize_brand_string("AMD A9-9410 RADEON R5, 5 COMPUTE CORES 2C+3G \0")); - EXPECT_EQ("Athlon", + EXPECT_EQ("A10-4600M", normalize_brand_string("AMD A10-4600M APU with Radeon(tm) HD Graphics \0")); + EXPECT_EQ("A10-5800K", normalize_brand_string("AMD A10-5800K APU with Radeon(tm) HD Graphics \0")); + EXPECT_EQ("A10-6800K", normalize_brand_string("AMD A10-6800K APU with Radeon(tm) HD Graphics \0")); + EXPECT_EQ("A10-7850K", normalize_brand_string("AMD A10-7850K APU with Radeon(TM) R7 Graphics \0")); + EXPECT_EQ("A12-9700P", normalize_brand_string("AMD A12-9700P RADEON R7, 10 COMPUTE CORES 4C+6G\0")); + EXPECT_EQ("A12-9800", normalize_brand_string("AMD A12-9800 RADEON R7, 12 COMPUTE CORES 4C+8G \0")); + EXPECT_EQ("A4-5000", normalize_brand_string("AMD A4-5000 APU with Radeon(TM) HD Graphics \0")); + EXPECT_EQ("A6-6310", normalize_brand_string("AMD A6-6310 APU with AMD Radeon R4 Graphics \0")); + EXPECT_EQ("A8-3850", normalize_brand_string("AMD A8-3850 APU with Radeon(tm) HD Graphics\0\0\0\0\0")); + EXPECT_EQ("A8-6410", normalize_brand_string("AMD A8-6410 APU with AMD Radeon R5 Graphics \0")); + EXPECT_EQ("A8-7670K", normalize_brand_string("AMD A8-7670K Radeon R7, 10 Compute Cores 4C+6G \0")); + EXPECT_EQ("A9-9410", normalize_brand_string("AMD A9-9410 RADEON R5, 5 COMPUTE CORES 2C+3G \0")); + EXPECT_EQ( + "Athlon", normalize_brand_string("AMD Athlon(tm) Processor\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Athlon 5350", - normalize_brand_string("AMD Athlon(tm) 5350 APU with Radeon(tm) R3 \0")); - EXPECT_EQ("Athlon 64 2800+", + EXPECT_EQ("Athlon 5350", normalize_brand_string("AMD Athlon(tm) 5350 APU with Radeon(tm) R3 \0")); + EXPECT_EQ( + "Athlon 64 2800+", normalize_brand_string("AMD Athlon(tm) 64 Processor 2800+\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Athlon 64 3200+", + EXPECT_EQ( + "Athlon 64 3200+", normalize_brand_string("AMD Athlon(tm) 64 Processor 3200+\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Athlon 64 X2 3800+", - normalize_brand_string("AMD Athlon(tm) 64 X2 Dual Core Processor 3800+\0\0")); - EXPECT_EQ("Athlon 64 X2 4000+", - normalize_brand_string("AMD Athlon(tm) 64 X2 Dual Core Processor 4000+\0\0")); - EXPECT_EQ("Athlon 64 X2 6000+", - normalize_brand_string("AMD Athlon(tm) 64 X2 Dual Core Processor 6000+\0\0")); - EXPECT_EQ("Athlon 64 X2 6400+", - normalize_brand_string("AMD Athlon(tm) 64 X2 Dual Core Processor 6400+\0\0")); - EXPECT_EQ("Athlon 7750", - normalize_brand_string("AMD Athlon(tm) 7750 Dual-Core Processor\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Athlon II X2 245", + EXPECT_EQ("Athlon 64 X2 3800+", normalize_brand_string("AMD Athlon(tm) 64 X2 Dual Core Processor 3800+\0\0")); + EXPECT_EQ("Athlon 64 X2 4000+", normalize_brand_string("AMD Athlon(tm) 64 X2 Dual Core Processor 4000+\0\0")); + EXPECT_EQ("Athlon 64 X2 6000+", normalize_brand_string("AMD Athlon(tm) 64 X2 Dual Core Processor 6000+\0\0")); + EXPECT_EQ("Athlon 64 X2 6400+", normalize_brand_string("AMD Athlon(tm) 64 X2 Dual Core Processor 6400+\0\0")); + EXPECT_EQ("Athlon 7750", normalize_brand_string("AMD Athlon(tm) 7750 Dual-Core Processor\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ( + "Athlon II X2 245", normalize_brand_string("AMD Athlon(tm) II X2 245 Processor\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Athlon II X4 620", + EXPECT_EQ( + "Athlon II X4 620", normalize_brand_string("AMD Athlon(tm) II X4 620 Processor\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Athlon XP", + EXPECT_EQ( + "Athlon XP", normalize_brand_string("Athlon XP (Palomin?00+\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Athlon XP 2200+", + EXPECT_EQ( + "Athlon XP 2200+", normalize_brand_string("AMD Athlon(tm) XP 2200+\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Athlon XP 3200+", + EXPECT_EQ( + "Athlon XP 3200+", normalize_brand_string("AMD Athlon(tm) XP 3200+\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("C-50", - normalize_brand_string("AMD C-50 Processor\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Duron", + EXPECT_EQ( + "C-50", + normalize_brand_string( + "AMD C-50 Processor\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ( + "Duron", normalize_brand_string("AMD Duron(tm) processor\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("E-350", - normalize_brand_string("AMD E-350 Processor\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("E-450", - normalize_brand_string("AMD E-450 APU with Radeon(tm) HD Graphics\0\0\0\0\0\0\0")); - EXPECT_EQ("E2-3000M", - normalize_brand_string("AMD E2-3000M APU with Radeon(tm) HD Graphics\0\0\0\0")); - EXPECT_EQ("FX-6100", - normalize_brand_string("AMD FX(tm)-6100 Six-Core Processor \0")); - EXPECT_EQ("FX-8150", - normalize_brand_string("AMD FX(tm)-8150 Eight-Core Processor \0")); - EXPECT_EQ("FX-8350", - normalize_brand_string("AMD FX(tm)-8350 Eight-Core Processor \0")); - EXPECT_EQ("FX-8800P", - normalize_brand_string("AMD FX-8800P Radeon R7, 12 Compute Cores 4C+8G \0")); - EXPECT_EQ("G-T56N", + EXPECT_EQ( + "E-350", + normalize_brand_string( + "AMD E-350 Processor\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("E-450", normalize_brand_string("AMD E-450 APU with Radeon(tm) HD Graphics\0\0\0\0\0\0\0")); + EXPECT_EQ("E2-3000M", normalize_brand_string("AMD E2-3000M APU with Radeon(tm) HD Graphics\0\0\0\0")); + EXPECT_EQ("FX-6100", normalize_brand_string("AMD FX(tm)-6100 Six-Core Processor \0")); + EXPECT_EQ("FX-8150", normalize_brand_string("AMD FX(tm)-8150 Eight-Core Processor \0")); + EXPECT_EQ("FX-8350", normalize_brand_string("AMD FX(tm)-8350 Eight-Core Processor \0")); + EXPECT_EQ("FX-8800P", normalize_brand_string("AMD FX-8800P Radeon R7, 12 Compute Cores 4C+8G \0")); + EXPECT_EQ( + "G-T56N", normalize_brand_string("AMD G-T56N Processor\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("GX-212JC", - normalize_brand_string("AMD GX-212JC SOC with Radeon(TM) R2E Graphics \0")); - EXPECT_EQ("Geode", - normalize_brand_string("Geode(TM) Integrated Processor by AMD PCS\0\0\0\0\0\0\0")); - EXPECT_EQ("K5", + EXPECT_EQ("GX-212JC", normalize_brand_string("AMD GX-212JC SOC with Radeon(TM) R2E Graphics \0")); + EXPECT_EQ("Geode", normalize_brand_string("Geode(TM) Integrated Processor by AMD PCS\0\0\0\0\0\0\0")); + EXPECT_EQ( + "K5", normalize_brand_string("AMD-K5(tm) Processor\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("K6", - normalize_brand_string("AMD-K6tm w/ multimedia extensions\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("K6 3D", + EXPECT_EQ("K6", normalize_brand_string("AMD-K6tm w/ multimedia extensions\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ( + "K6 3D", normalize_brand_string("AMD-K6(tm) 3D processor\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("K6 3D+", + EXPECT_EQ( + "K6 3D+", normalize_brand_string("AMD-K6(tm) 3D+ Processor\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("K6-III", + EXPECT_EQ( + "K6-III", normalize_brand_string("AMD-K6(tm)-III Processor\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("K7", + EXPECT_EQ( + "K7", normalize_brand_string("AMD-K7(tm) Processor\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Opteron 2210 HE", - normalize_brand_string("Dual-Core AMD Opteron(tm) Processor 2210 HE\0\0\0\0\0")); - EXPECT_EQ("Opteron 2344 HE", - normalize_brand_string("Quad-Core AMD Opteron(tm) Processor 2344 HE\0\0\0\0\0")); - EXPECT_EQ("Opteron 2347 HE", - normalize_brand_string("Quad-Core AMD Opteron(tm) Processor 2347 HE\0\0\0\0\0")); - EXPECT_EQ("Opteron 2378", - normalize_brand_string("Quad-Core AMD Opteron(tm) Processor 2378\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Opteron 240 HE", + EXPECT_EQ("Opteron 2210 HE", normalize_brand_string("Dual-Core AMD Opteron(tm) Processor 2210 HE\0\0\0\0\0")); + EXPECT_EQ("Opteron 2344 HE", normalize_brand_string("Quad-Core AMD Opteron(tm) Processor 2344 HE\0\0\0\0\0")); + EXPECT_EQ("Opteron 2347 HE", normalize_brand_string("Quad-Core AMD Opteron(tm) Processor 2347 HE\0\0\0\0\0")); + EXPECT_EQ("Opteron 2378", normalize_brand_string("Quad-Core AMD Opteron(tm) Processor 2378\0\0\0\0\0\0\0\0")); + EXPECT_EQ( + "Opteron 240 HE", normalize_brand_string("AMD Opteron(tm) Processor 240 HE\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Opteron 2431", - normalize_brand_string("Six-Core AMD Opteron(tm) Processor 2431\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Opteron 248", + EXPECT_EQ("Opteron 2431", normalize_brand_string("Six-Core AMD Opteron(tm) Processor 2431\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ( + "Opteron 248", normalize_brand_string("AMD Opteron(tm) Processor 248\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Opteron 4176 HE", + EXPECT_EQ( + "Opteron 4176 HE", normalize_brand_string("AMD Opteron(tm) Processor 4176 HE\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Opteron 6180 SE", + EXPECT_EQ( + "Opteron 6180 SE", normalize_brand_string("AMD Opteron(tm) Processor 6180 SE\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Opteron 6274", - normalize_brand_string("AMD Opteron(TM) Processor 6274 \0")); - EXPECT_EQ("Opteron 8220 SE", - normalize_brand_string("Dual-Core AMD Opteron(tm) Processor 8220 SE\0\0\0\0\0")); - EXPECT_EQ("Phenom 9500", - normalize_brand_string("AMD Phenom(tm) 9500 Quad-Core Processor\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Phenom II 42 TWKR Black Edition", + EXPECT_EQ("Opteron 6274", normalize_brand_string("AMD Opteron(TM) Processor 6274 \0")); + EXPECT_EQ("Opteron 8220 SE", normalize_brand_string("Dual-Core AMD Opteron(tm) Processor 8220 SE\0\0\0\0\0")); + EXPECT_EQ("Phenom 9500", normalize_brand_string("AMD Phenom(tm) 9500 Quad-Core Processor\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ( + "Phenom II 42 TWKR Black Edition", normalize_brand_string("AMD Phenom(tm) II 42 TWKR Black Edition\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Phenom II X2 550", + EXPECT_EQ( + "Phenom II X2 550", normalize_brand_string("AMD Phenom(tm) II X2 550 Processor\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Phenom II X4 940", + EXPECT_EQ( + "Phenom II X4 940", normalize_brand_string("AMD Phenom(tm) II X4 940 Processor\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Phenom II X4 955", + EXPECT_EQ( + "Phenom II X4 955", normalize_brand_string("AMD Phenom(tm) II X4 955 Processor\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Phenom II X4 965", + EXPECT_EQ( + "Phenom II X4 965", normalize_brand_string("AMD Phenom(tm) II X4 965 Processor\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Phenom II X6 1055T", + EXPECT_EQ( + "Phenom II X6 1055T", normalize_brand_string("AMD Phenom(tm) II X6 1055T Processor\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Ryzen 5 1500X", - normalize_brand_string("AMD Ryzen 5 1500X Quad-Core Processor \0")); - EXPECT_EQ("Ryzen 7 1700X", - normalize_brand_string("AMD Ryzen 7 1700X Eight-Core Processor \0")); - EXPECT_EQ("Ryzen 7 1800X", - normalize_brand_string("AMD Ryzen 7 1800X Eight-Core Processor \0")); - EXPECT_EQ("Ryzen Threadripper 1950X", + EXPECT_EQ("Ryzen 5 1500X", normalize_brand_string("AMD Ryzen 5 1500X Quad-Core Processor \0")); + EXPECT_EQ("Ryzen 7 1700X", normalize_brand_string("AMD Ryzen 7 1700X Eight-Core Processor \0")); + EXPECT_EQ("Ryzen 7 1800X", normalize_brand_string("AMD Ryzen 7 1800X Eight-Core Processor \0")); + EXPECT_EQ( + "Ryzen Threadripper 1950X", normalize_brand_string("AMD Ryzen Threadripper 1950X 16-Core Processor \0")); - EXPECT_EQ("Sempron 140", + EXPECT_EQ( + "Sempron 140", normalize_brand_string("AMD Sempron(tm) 140 Processor\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Sempron 2600+", + EXPECT_EQ( + "Sempron 2600+", normalize_brand_string("AMD Sempron(tm) Processor 2600+\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Sempron 2800+", + EXPECT_EQ( + "Sempron 2800+", normalize_brand_string("AMD Sempron(tm) Processor 2800+\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Sempron 3000+", + EXPECT_EQ( + "Sempron 3000+", normalize_brand_string("AMD Sempron(tm) Processor 3000+\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Turion RM-70", + EXPECT_EQ( + "Turion RM-70", normalize_brand_string("AMD Turion Dual-Core RM-70\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Turion X2 Ultra ZM-82", - normalize_brand_string("AMD Turion(tm) X2 Ultra Dual-Core Mobile ZM-82\0\0")); + EXPECT_EQ( + "Turion X2 Ultra ZM-82", normalize_brand_string("AMD Turion(tm) X2 Ultra Dual-Core Mobile ZM-82\0\0")); } TEST(BRAND_STRING, via) { - EXPECT_EQ("C3 Ezra", - normalize_brand_string("VIA C3 Ezra\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("C7-M 1200MHz", - normalize_brand_string(" VIA C7-M Processor 1200MHz\0")); - EXPECT_EQ("CNA 1800MHz", - normalize_brand_string(" VIA CNA processor 1800MHz ")); - EXPECT_EQ("CNA 2667MHz", - normalize_brand_string(" VIA CNA processor 2667MHz ")); - EXPECT_EQ("Eden X4 C4250", - normalize_brand_string(" VIA Eden X4 C4250@1.2+GHz\0")); - EXPECT_EQ("Esther 1500MHz", - normalize_brand_string(" VIA Esther processor 1500MHz\0")); - EXPECT_EQ("Ezra", - normalize_brand_string("VIA Ezra\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("L4700", - normalize_brand_string(" VIA QuadCore L4700 @ 1.2+ GHz\0")); - EXPECT_EQ("Nano 1800MHz", - normalize_brand_string(" VIA Nano processor @1800MHz\0")); - EXPECT_EQ("Nano L2200", - normalize_brand_string(" VIA Nano processor L2200@1600MHz\0")); - EXPECT_EQ("Nano L3050", - normalize_brand_string(" VIA Nano L3050@1800MHz\0")); - EXPECT_EQ("Nehemiah", - normalize_brand_string("VIA Nehemiah\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Samuel", - normalize_brand_string("VIA Samuel\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Samuel 2", - normalize_brand_string("VIA Samuel 2\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("Samuel M", - normalize_brand_string("VIA Samuel\0\0M\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ( + "C3 Ezra", + normalize_brand_string( + "VIA C3 Ezra\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("C7-M 1200MHz", normalize_brand_string(" VIA C7-M Processor 1200MHz\0")); + EXPECT_EQ("CNA 1800MHz", normalize_brand_string(" VIA CNA processor 1800MHz ")); + EXPECT_EQ("CNA 2667MHz", normalize_brand_string(" VIA CNA processor 2667MHz ")); + EXPECT_EQ("Eden X4 C4250", normalize_brand_string(" VIA Eden X4 C4250@1.2+GHz\0")); + EXPECT_EQ("Esther 1500MHz", normalize_brand_string(" VIA Esther processor 1500MHz\0")); + EXPECT_EQ( + "Ezra", + normalize_brand_string( + "VIA Ezra\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("L4700", normalize_brand_string(" VIA QuadCore L4700 @ 1.2+ GHz\0")); + EXPECT_EQ("Nano 1800MHz", normalize_brand_string(" VIA Nano processor @1800MHz\0")); + EXPECT_EQ("Nano L2200", normalize_brand_string(" VIA Nano processor L2200@1600MHz\0")); + EXPECT_EQ("Nano L3050", normalize_brand_string(" VIA Nano L3050@1800MHz\0")); + EXPECT_EQ( + "Nehemiah", + normalize_brand_string( + "VIA Nehemiah\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ( + "Samuel", + normalize_brand_string( + "VIA Samuel\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ( + "Samuel 2", + normalize_brand_string( + "VIA Samuel 2\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ( + "Samuel M", + normalize_brand_string( + "VIA Samuel\0\0M\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); } TEST(BRAND_STRING, transmeta) { - EXPECT_EQ("Crusoe TM5800", - normalize_brand_string("Transmeta(tm) Crusoe(tm) Processor TM5800\0\0\0\0\0\0\0")); - EXPECT_EQ("Efficeon TM8000", - normalize_brand_string("Transmeta Efficeon(tm) Processor TM8000\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("Crusoe TM5800", normalize_brand_string("Transmeta(tm) Crusoe(tm) Processor TM5800\0\0\0\0\0\0\0")); + EXPECT_EQ( + "Efficeon TM8000", normalize_brand_string("Transmeta Efficeon(tm) Processor TM8000\0\0\0\0\0\0\0\0\0")); } TEST(BRAND_STRING, other) { - EXPECT_EQ("", - normalize_brand_string("\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("", - normalize_brand_string("Quad-Core Processor (up to 1.4GHz) \0")); - EXPECT_EQ("Geode", - normalize_brand_string("Geode(TM) Integrated Processor by National Semi\0")); - EXPECT_EQ("MediaGX", + EXPECT_EQ( + "", + normalize_brand_string( + "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ("", normalize_brand_string("Quad-Core Processor (up to 1.4GHz) \0")); + EXPECT_EQ("Geode", normalize_brand_string("Geode(TM) Integrated Processor by National Semi\0")); + EXPECT_EQ( + "MediaGX", normalize_brand_string("Cyrix MediaGXtm MMXtm Enhanced\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); - EXPECT_EQ("WinChip 2-3D", - normalize_brand_string("IDT WinChip 2-3D\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); + EXPECT_EQ( + "WinChip 2-3D", + normalize_brand_string( + "IDT WinChip 2-3D\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0")); } diff --git a/test/name/proc-cpuinfo-hardware.cc b/test/name/proc-cpuinfo-hardware.cc index 5e6561b5..8a3418d8 100644 --- a/test/name/proc-cpuinfo-hardware.cc +++ b/test/name/proc-cpuinfo-hardware.cc @@ -17,778 +17,461 @@ extern "C" void cpuinfo_arm_android_parse_proc_cpuinfo_hardware( inline std::string parse_proc_cpuinfo_hardware( std::string hardware, - uint32_t cores=1, - uint32_t max_cpu_freq_max=0) -{ + uint32_t cores = 1, + uint32_t max_cpu_freq_max = 0) { char hardware_buffer[CPUINFO_HARDWARE_VALUE_MAX]; strncpy(hardware_buffer, hardware.c_str(), CPUINFO_HARDWARE_VALUE_MAX); char chipset_name[CPUINFO_ARM_CHIPSET_NAME_MAX]; - cpuinfo_arm_android_parse_proc_cpuinfo_hardware( - hardware_buffer, cores, max_cpu_freq_max, false, chipset_name); + cpuinfo_arm_android_parse_proc_cpuinfo_hardware(hardware_buffer, cores, max_cpu_freq_max, false, chipset_name); return std::string(chipset_name, strnlen(chipset_name, CPUINFO_ARM_CHIPSET_NAME_MAX)); } inline std::string parse_proc_cpuinfo_hardware_tegra( std::string hardware, - uint32_t cores=1, - uint32_t max_cpu_freq_max=0) -{ + uint32_t cores = 1, + uint32_t max_cpu_freq_max = 0) { char hardware_buffer[CPUINFO_HARDWARE_VALUE_MAX]; strncpy(hardware_buffer, hardware.c_str(), CPUINFO_HARDWARE_VALUE_MAX); char chipset_name[CPUINFO_ARM_CHIPSET_NAME_MAX]; - cpuinfo_arm_android_parse_proc_cpuinfo_hardware( - hardware_buffer, cores, max_cpu_freq_max, true, chipset_name); + cpuinfo_arm_android_parse_proc_cpuinfo_hardware(hardware_buffer, cores, max_cpu_freq_max, true, chipset_name); return std::string(chipset_name, strnlen(chipset_name, CPUINFO_ARM_CHIPSET_NAME_MAX)); } TEST(PROC_CPUINFO_HARDWARE, qualcomm_msm) { - EXPECT_EQ("Qualcomm MSM7225AB", - parse_proc_cpuinfo_hardware("LG MSM7225AB")); - EXPECT_EQ("Qualcomm MSM7225AB", - parse_proc_cpuinfo_hardware("LG MSM7225AB V1")); - EXPECT_EQ("Qualcomm MSM7625A", - parse_proc_cpuinfo_hardware("QCT MSM7625a FFA")); - EXPECT_EQ("Qualcomm MSM8208", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8208")); - EXPECT_EQ("Qualcomm MSM8209", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8209")); - EXPECT_EQ("Qualcomm MSM8210", - parse_proc_cpuinfo_hardware("Qualcomm MSM8210")); - EXPECT_EQ("Qualcomm MSM8212", - parse_proc_cpuinfo_hardware("Qualcomm MSM 8212 (Flattened Device Tree)")); - EXPECT_EQ("Qualcomm MSM8212", - parse_proc_cpuinfo_hardware("Qualcomm MSM8212")); - EXPECT_EQ("Qualcomm MSM8225", - parse_proc_cpuinfo_hardware("QCT MSM8225 SURF")); - EXPECT_EQ("Qualcomm MSM8226", - parse_proc_cpuinfo_hardware("Qualcomm MSM 8226 (Flattened Device Tree)")); - EXPECT_EQ("Qualcomm MSM8226", - parse_proc_cpuinfo_hardware("Qualcomm MSM8226")); - EXPECT_EQ("Qualcomm MSM8228", - parse_proc_cpuinfo_hardware("Qualcomm MSM8228")); - EXPECT_EQ("Qualcomm MSM8230", - parse_proc_cpuinfo_hardware("LGE MSM8230 L9II")); - EXPECT_EQ("Qualcomm MSM8239", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8239")); - EXPECT_EQ("Qualcomm MSM8609", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8609")); - EXPECT_EQ("Qualcomm MSM8610", - parse_proc_cpuinfo_hardware("Qualcomm MSM 8610 (Flattened Device Tree)", 2)); - EXPECT_EQ("Qualcomm MSM8610", - parse_proc_cpuinfo_hardware("Qualcomm MSM8610", 2)); + EXPECT_EQ("Qualcomm MSM7225AB", parse_proc_cpuinfo_hardware("LG MSM7225AB")); + EXPECT_EQ("Qualcomm MSM7225AB", parse_proc_cpuinfo_hardware("LG MSM7225AB V1")); + EXPECT_EQ("Qualcomm MSM7625A", parse_proc_cpuinfo_hardware("QCT MSM7625a FFA")); + EXPECT_EQ("Qualcomm MSM8208", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8208")); + EXPECT_EQ("Qualcomm MSM8209", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8209")); + EXPECT_EQ("Qualcomm MSM8210", parse_proc_cpuinfo_hardware("Qualcomm MSM8210")); + EXPECT_EQ("Qualcomm MSM8212", parse_proc_cpuinfo_hardware("Qualcomm MSM 8212 (Flattened Device Tree)")); + EXPECT_EQ("Qualcomm MSM8212", parse_proc_cpuinfo_hardware("Qualcomm MSM8212")); + EXPECT_EQ("Qualcomm MSM8225", parse_proc_cpuinfo_hardware("QCT MSM8225 SURF")); + EXPECT_EQ("Qualcomm MSM8226", parse_proc_cpuinfo_hardware("Qualcomm MSM 8226 (Flattened Device Tree)")); + EXPECT_EQ("Qualcomm MSM8226", parse_proc_cpuinfo_hardware("Qualcomm MSM8226")); + EXPECT_EQ("Qualcomm MSM8228", parse_proc_cpuinfo_hardware("Qualcomm MSM8228")); + EXPECT_EQ("Qualcomm MSM8230", parse_proc_cpuinfo_hardware("LGE MSM8230 L9II")); + EXPECT_EQ("Qualcomm MSM8239", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8239")); + EXPECT_EQ("Qualcomm MSM8609", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8609")); + EXPECT_EQ("Qualcomm MSM8610", parse_proc_cpuinfo_hardware("Qualcomm MSM 8610 (Flattened Device Tree)", 2)); + EXPECT_EQ("Qualcomm MSM8610", parse_proc_cpuinfo_hardware("Qualcomm MSM8610", 2)); #if CPUINFO_ARCH_ARM - EXPECT_EQ("Qualcomm MSM8612", - parse_proc_cpuinfo_hardware("Qualcomm MSM 8610 (Flattened Device Tree)", 4)); - EXPECT_EQ("Qualcomm MSM8612", - parse_proc_cpuinfo_hardware("Qualcomm MSM 8612 (Flattened Device Tree)")); + EXPECT_EQ("Qualcomm MSM8612", parse_proc_cpuinfo_hardware("Qualcomm MSM 8610 (Flattened Device Tree)", 4)); + EXPECT_EQ("Qualcomm MSM8612", parse_proc_cpuinfo_hardware("Qualcomm MSM 8612 (Flattened Device Tree)")); #endif /* CPUINFO_ARCH_ARM */ - EXPECT_EQ("Qualcomm MSM8625", - parse_proc_cpuinfo_hardware("LG MSM8625 V7")); - EXPECT_EQ("Qualcomm MSM8625", - parse_proc_cpuinfo_hardware("QCT MSM8625 FFA")); - EXPECT_EQ("Qualcomm MSM8625", - parse_proc_cpuinfo_hardware("QCT MSM8625 SURF")); - EXPECT_EQ("Qualcomm MSM8625Q", - parse_proc_cpuinfo_hardware("QRD MSM8625Q SKUD")); - EXPECT_EQ("Qualcomm MSM8626", - parse_proc_cpuinfo_hardware("Qualcomm MSM8626")); - EXPECT_EQ("Qualcomm MSM8627", - parse_proc_cpuinfo_hardware("QCT MSM8627 MTP")); - EXPECT_EQ("Qualcomm MSM8628", - parse_proc_cpuinfo_hardware("Qualcomm MSM8628")); - EXPECT_EQ("Qualcomm MSM8909", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8909")); - EXPECT_EQ("Qualcomm MSM8916", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8216")); - EXPECT_EQ("Qualcomm MSM8916", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8916", 4)); - EXPECT_EQ("Qualcomm MSM8916", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8916MSM8916", 4)); - EXPECT_EQ("Qualcomm MSM8917", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8917", 4)); - EXPECT_EQ("Qualcomm MSM8920", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8920")); - EXPECT_EQ("Qualcomm MSM8926", - parse_proc_cpuinfo_hardware("Qualcomm MSM 8926 (Flattened Device Tree)")); - EXPECT_EQ("Qualcomm MSM8926", - parse_proc_cpuinfo_hardware("Qualcomm MSM8926")); - EXPECT_EQ("Qualcomm MSM8928", - parse_proc_cpuinfo_hardware("Qualcomm MSM8928")); - EXPECT_EQ("Qualcomm MSM8928", - parse_proc_cpuinfo_hardware("Qualcomm msm 8928")); - EXPECT_EQ("Qualcomm MSM8929", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8929")); - EXPECT_EQ("Qualcomm MSM8930", - parse_proc_cpuinfo_hardware("LGE MSM8930 FX3")); - EXPECT_EQ("Qualcomm MSM8930", - parse_proc_cpuinfo_hardware("QCT MSM8930 CDP")); - EXPECT_EQ("Qualcomm MSM8930", - parse_proc_cpuinfo_hardware("QCT MSM8930 MTP")); - EXPECT_EQ("Qualcomm MSM8937", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8937", 8)); - EXPECT_EQ("Qualcomm MSM8939", - parse_proc_cpuinfo_hardware("Qualcomm MSM 8939 HUAWEI ALE_L04")); - EXPECT_EQ("Qualcomm MSM8939", - parse_proc_cpuinfo_hardware("Qualcomm MSM 8939 HUAWEI ATH-UL01")); - EXPECT_EQ("Qualcomm MSM8939", - parse_proc_cpuinfo_hardware("Qualcomm MSM 8939 HUAWEI KII-L05")); - EXPECT_EQ("Qualcomm MSM8939", - parse_proc_cpuinfo_hardware("Qualcomm MSM 8939 HUAWEI KIW-L21")); - EXPECT_EQ("Qualcomm MSM8939", - parse_proc_cpuinfo_hardware("Qualcomm MSM 8939 HUAWEI KIW-L22")); - EXPECT_EQ("Qualcomm MSM8939", - parse_proc_cpuinfo_hardware("Qualcomm MSM 8939 HUAWEI KIW-L23")); - EXPECT_EQ("Qualcomm MSM8939", - parse_proc_cpuinfo_hardware("Qualcomm MSM 8939 HUAWEI KIW-L24")); - EXPECT_EQ("Qualcomm MSM8939", - parse_proc_cpuinfo_hardware("Qualcomm MSM 8939 HUAWEI KIW-L33")); - EXPECT_EQ("Qualcomm MSM8939", - parse_proc_cpuinfo_hardware("Qualcomm MSM 8939 HUAWEI RIO-L01_VB")); - EXPECT_EQ("Qualcomm MSM8939", - parse_proc_cpuinfo_hardware("Qualcomm MSM 8939 HUAWEI RIO-L02")); - EXPECT_EQ("Qualcomm MSM8939", - parse_proc_cpuinfo_hardware("Qualcomm MSM 8939 HUAWEI RIO-L03")); - EXPECT_EQ("Qualcomm MSM8939", - parse_proc_cpuinfo_hardware("Qualcomm MSM 8939 HUAWEI TEXAS-A1")); - EXPECT_EQ("Qualcomm MSM8939", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8939")); - EXPECT_EQ("Qualcomm MSM8939", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8939_BC")); - EXPECT_EQ("Qualcomm MSM8940", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8940")); - EXPECT_EQ("Qualcomm MSM8952", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8952")); - EXPECT_EQ("Qualcomm MSM8952", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8952MSM8952")); - EXPECT_EQ("Qualcomm MSM8952", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc. MSM8952 QRD SKUM")); - EXPECT_EQ("Qualcomm MSM8953", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8953")); - EXPECT_EQ("Qualcomm MSM8953PRO", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8953Pro")); - EXPECT_EQ("Qualcomm MSM8956", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8956")); - EXPECT_EQ("Qualcomm MSM8960", - parse_proc_cpuinfo_hardware("LGE MSM8960 D1L KR", 2)); - EXPECT_EQ("Qualcomm MSM8960", - parse_proc_cpuinfo_hardware("LGE MSM8960 FX1", 2)); - EXPECT_EQ("Qualcomm MSM8960", - parse_proc_cpuinfo_hardware("LGE MSM8960 Lx", 2)); - EXPECT_EQ("Qualcomm MSM8960", - parse_proc_cpuinfo_hardware("LGE MSM8960 VU2", 2)); - EXPECT_EQ("Qualcomm MSM8960", - parse_proc_cpuinfo_hardware("QCT MSM8960 CDP", 2)); - EXPECT_EQ("Qualcomm MSM8960", - parse_proc_cpuinfo_hardware("Qualcomm MSM8960", 2)); - EXPECT_EQ("Qualcomm MSM8960DT", - parse_proc_cpuinfo_hardware("msm8960dt")); - EXPECT_EQ("Qualcomm MSM8974", - parse_proc_cpuinfo_hardware("Qualcomm MSM 8974 (Flattened Device Tree)")); - EXPECT_EQ("Qualcomm MSM8974", + EXPECT_EQ("Qualcomm MSM8625", parse_proc_cpuinfo_hardware("LG MSM8625 V7")); + EXPECT_EQ("Qualcomm MSM8625", parse_proc_cpuinfo_hardware("QCT MSM8625 FFA")); + EXPECT_EQ("Qualcomm MSM8625", parse_proc_cpuinfo_hardware("QCT MSM8625 SURF")); + EXPECT_EQ("Qualcomm MSM8625Q", parse_proc_cpuinfo_hardware("QRD MSM8625Q SKUD")); + EXPECT_EQ("Qualcomm MSM8626", parse_proc_cpuinfo_hardware("Qualcomm MSM8626")); + EXPECT_EQ("Qualcomm MSM8627", parse_proc_cpuinfo_hardware("QCT MSM8627 MTP")); + EXPECT_EQ("Qualcomm MSM8628", parse_proc_cpuinfo_hardware("Qualcomm MSM8628")); + EXPECT_EQ("Qualcomm MSM8909", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8909")); + EXPECT_EQ("Qualcomm MSM8916", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8216")); + EXPECT_EQ("Qualcomm MSM8916", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8916", 4)); + EXPECT_EQ("Qualcomm MSM8916", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8916MSM8916", 4)); + EXPECT_EQ("Qualcomm MSM8917", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8917", 4)); + EXPECT_EQ("Qualcomm MSM8920", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8920")); + EXPECT_EQ("Qualcomm MSM8926", parse_proc_cpuinfo_hardware("Qualcomm MSM 8926 (Flattened Device Tree)")); + EXPECT_EQ("Qualcomm MSM8926", parse_proc_cpuinfo_hardware("Qualcomm MSM8926")); + EXPECT_EQ("Qualcomm MSM8928", parse_proc_cpuinfo_hardware("Qualcomm MSM8928")); + EXPECT_EQ("Qualcomm MSM8928", parse_proc_cpuinfo_hardware("Qualcomm msm 8928")); + EXPECT_EQ("Qualcomm MSM8929", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8929")); + EXPECT_EQ("Qualcomm MSM8930", parse_proc_cpuinfo_hardware("LGE MSM8930 FX3")); + EXPECT_EQ("Qualcomm MSM8930", parse_proc_cpuinfo_hardware("QCT MSM8930 CDP")); + EXPECT_EQ("Qualcomm MSM8930", parse_proc_cpuinfo_hardware("QCT MSM8930 MTP")); + EXPECT_EQ("Qualcomm MSM8937", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8937", 8)); + EXPECT_EQ("Qualcomm MSM8939", parse_proc_cpuinfo_hardware("Qualcomm MSM 8939 HUAWEI ALE_L04")); + EXPECT_EQ("Qualcomm MSM8939", parse_proc_cpuinfo_hardware("Qualcomm MSM 8939 HUAWEI ATH-UL01")); + EXPECT_EQ("Qualcomm MSM8939", parse_proc_cpuinfo_hardware("Qualcomm MSM 8939 HUAWEI KII-L05")); + EXPECT_EQ("Qualcomm MSM8939", parse_proc_cpuinfo_hardware("Qualcomm MSM 8939 HUAWEI KIW-L21")); + EXPECT_EQ("Qualcomm MSM8939", parse_proc_cpuinfo_hardware("Qualcomm MSM 8939 HUAWEI KIW-L22")); + EXPECT_EQ("Qualcomm MSM8939", parse_proc_cpuinfo_hardware("Qualcomm MSM 8939 HUAWEI KIW-L23")); + EXPECT_EQ("Qualcomm MSM8939", parse_proc_cpuinfo_hardware("Qualcomm MSM 8939 HUAWEI KIW-L24")); + EXPECT_EQ("Qualcomm MSM8939", parse_proc_cpuinfo_hardware("Qualcomm MSM 8939 HUAWEI KIW-L33")); + EXPECT_EQ("Qualcomm MSM8939", parse_proc_cpuinfo_hardware("Qualcomm MSM 8939 HUAWEI RIO-L01_VB")); + EXPECT_EQ("Qualcomm MSM8939", parse_proc_cpuinfo_hardware("Qualcomm MSM 8939 HUAWEI RIO-L02")); + EXPECT_EQ("Qualcomm MSM8939", parse_proc_cpuinfo_hardware("Qualcomm MSM 8939 HUAWEI RIO-L03")); + EXPECT_EQ("Qualcomm MSM8939", parse_proc_cpuinfo_hardware("Qualcomm MSM 8939 HUAWEI TEXAS-A1")); + EXPECT_EQ("Qualcomm MSM8939", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8939")); + EXPECT_EQ("Qualcomm MSM8939", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8939_BC")); + EXPECT_EQ("Qualcomm MSM8940", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8940")); + EXPECT_EQ("Qualcomm MSM8952", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8952")); + EXPECT_EQ("Qualcomm MSM8952", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8952MSM8952")); + EXPECT_EQ("Qualcomm MSM8952", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc. MSM8952 QRD SKUM")); + EXPECT_EQ("Qualcomm MSM8953", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8953")); + EXPECT_EQ("Qualcomm MSM8953PRO", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8953Pro")); + EXPECT_EQ("Qualcomm MSM8956", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8956")); + EXPECT_EQ("Qualcomm MSM8960", parse_proc_cpuinfo_hardware("LGE MSM8960 D1L KR", 2)); + EXPECT_EQ("Qualcomm MSM8960", parse_proc_cpuinfo_hardware("LGE MSM8960 FX1", 2)); + EXPECT_EQ("Qualcomm MSM8960", parse_proc_cpuinfo_hardware("LGE MSM8960 Lx", 2)); + EXPECT_EQ("Qualcomm MSM8960", parse_proc_cpuinfo_hardware("LGE MSM8960 VU2", 2)); + EXPECT_EQ("Qualcomm MSM8960", parse_proc_cpuinfo_hardware("QCT MSM8960 CDP", 2)); + EXPECT_EQ("Qualcomm MSM8960", parse_proc_cpuinfo_hardware("Qualcomm MSM8960", 2)); + EXPECT_EQ("Qualcomm MSM8960DT", parse_proc_cpuinfo_hardware("msm8960dt")); + EXPECT_EQ("Qualcomm MSM8974", parse_proc_cpuinfo_hardware("Qualcomm MSM 8974 (Flattened Device Tree)")); + EXPECT_EQ( + "Qualcomm MSM8974", parse_proc_cpuinfo_hardware("Qualcomm MSM 8974 HAMMERHEAD (Flattened Device Tree)")); - EXPECT_EQ("Qualcomm MSM8974", - parse_proc_cpuinfo_hardware("Qualcomm MSM8974")); - EXPECT_EQ("Qualcomm MSM8974PRO-AA", - parse_proc_cpuinfo_hardware("Qualcomm MSM8974PRO-AA")); - EXPECT_EQ("Qualcomm MSM8974PRO-AB", - parse_proc_cpuinfo_hardware("Qualcomm MSM8974PRO-AB")); - EXPECT_EQ("Qualcomm MSM8974PRO-AC", - parse_proc_cpuinfo_hardware("Qualcomm MSM8974PRO-AC")); - EXPECT_EQ("Qualcomm MSM8976", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8976")); - EXPECT_EQ("Qualcomm MSM8976PRO", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8976SG")); - EXPECT_EQ("Qualcomm MSM8992", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8992")); - EXPECT_EQ("Qualcomm MSM8994", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8994")); - EXPECT_EQ("Qualcomm MSM8994V", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc. MSM8994v2.1 MTP")); - EXPECT_EQ("Qualcomm MSM8996", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8996", 4)); - EXPECT_EQ("Qualcomm MSM8996PRO-AB", + EXPECT_EQ("Qualcomm MSM8974", parse_proc_cpuinfo_hardware("Qualcomm MSM8974")); + EXPECT_EQ("Qualcomm MSM8974PRO-AA", parse_proc_cpuinfo_hardware("Qualcomm MSM8974PRO-AA")); + EXPECT_EQ("Qualcomm MSM8974PRO-AB", parse_proc_cpuinfo_hardware("Qualcomm MSM8974PRO-AB")); + EXPECT_EQ("Qualcomm MSM8974PRO-AC", parse_proc_cpuinfo_hardware("Qualcomm MSM8974PRO-AC")); + EXPECT_EQ("Qualcomm MSM8976", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8976")); + EXPECT_EQ("Qualcomm MSM8976PRO", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8976SG")); + EXPECT_EQ("Qualcomm MSM8992", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8992")); + EXPECT_EQ("Qualcomm MSM8994", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8994")); + EXPECT_EQ("Qualcomm MSM8994V", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc. MSM8994v2.1 MTP")); + EXPECT_EQ("Qualcomm MSM8996", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8996", 4)); + EXPECT_EQ( + "Qualcomm MSM8996PRO-AB", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8996pro", 4, 1593600 /* LITTLE core */)); - EXPECT_EQ("Qualcomm MSM8996PRO-AB", + EXPECT_EQ( + "Qualcomm MSM8996PRO-AB", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8996pro", 4, 2150400 /* big core */)); - EXPECT_EQ("Qualcomm MSM8996PRO-AC", + EXPECT_EQ( + "Qualcomm MSM8996PRO-AC", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8996pro", 4, 2188800 /* LITTLE core */)); - EXPECT_EQ("Qualcomm MSM8996PRO-AC", + EXPECT_EQ( + "Qualcomm MSM8996PRO-AC", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8996pro", 4, 2342400 /* big core */)); - EXPECT_EQ("Qualcomm MSM8998", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8998")); + EXPECT_EQ("Qualcomm MSM8998", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc MSM8998")); } TEST(PROC_CPUINFO_HARDWARE, qualcomm_apq) { - EXPECT_EQ("Qualcomm APQ8009", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc APQ8009")); - EXPECT_EQ("Qualcomm APQ8016", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc APQ8016")); - EXPECT_EQ("Qualcomm APQ8016", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc APQ8016APQ8016")); - EXPECT_EQ("Qualcomm APQ8017", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc APQ8017")); - EXPECT_EQ("Qualcomm APQ8026", - parse_proc_cpuinfo_hardware("Qualcomm APQ8026")); - EXPECT_EQ("Qualcomm APQ8028", - parse_proc_cpuinfo_hardware("Qualcomm APQ8028")); - EXPECT_EQ("Qualcomm APQ8039", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc APQ8039")); - EXPECT_EQ("Qualcomm APQ8053", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc APQ8053")); - EXPECT_EQ("Qualcomm APQ8064", - parse_proc_cpuinfo_hardware("PANTECH APQ8064 EF48S")); - EXPECT_EQ("Qualcomm APQ8064", - parse_proc_cpuinfo_hardware("PANTECH APQ8064 EF49K")); - EXPECT_EQ("Qualcomm APQ8064", - parse_proc_cpuinfo_hardware("PANTECH APQ8064 EF50L")); - EXPECT_EQ("Qualcomm APQ8064", - parse_proc_cpuinfo_hardware("PANTECH APQ8064 EF51K")); - EXPECT_EQ("Qualcomm APQ8064", - parse_proc_cpuinfo_hardware("PANTECH APQ8064 EF51L")); - EXPECT_EQ("Qualcomm APQ8064", - parse_proc_cpuinfo_hardware("PANTECH APQ8064 EF51S")); - EXPECT_EQ("Qualcomm APQ8064", - parse_proc_cpuinfo_hardware("PANTECH APQ8064 EF52K")); - EXPECT_EQ("Qualcomm APQ8064", - parse_proc_cpuinfo_hardware("PANTECH APQ8064 EF52L")); - EXPECT_EQ("Qualcomm APQ8064", - parse_proc_cpuinfo_hardware("PANTECH APQ8064 EF52S")); - EXPECT_EQ("Qualcomm APQ8064", - parse_proc_cpuinfo_hardware("QCT APQ8064 AWIFI")); - EXPECT_EQ("Qualcomm APQ8064", - parse_proc_cpuinfo_hardware("QCT APQ8064 DEB")); - EXPECT_EQ("Qualcomm APQ8064", - parse_proc_cpuinfo_hardware("QCT APQ8064 DUMA")); - EXPECT_EQ("Qualcomm APQ8064", - parse_proc_cpuinfo_hardware("QCT APQ8064 FLO")); - EXPECT_EQ("Qualcomm APQ8064", - parse_proc_cpuinfo_hardware("QCT APQ8064 LEOPARDCAT")); - EXPECT_EQ("Qualcomm APQ8064", - parse_proc_cpuinfo_hardware("QCT APQ8064 MAKO")); - EXPECT_EQ("Qualcomm APQ8064", - parse_proc_cpuinfo_hardware("QCT APQ8064 MTP")); - EXPECT_EQ("Qualcomm APQ8074PRO-AB", - parse_proc_cpuinfo_hardware("Qualcomm APQ8074PRO-AB")); - EXPECT_EQ("Qualcomm APQ8076", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc APQ8076")); - EXPECT_EQ("Qualcomm APQ8084", - parse_proc_cpuinfo_hardware("Qualcomm APQ 8084 (Flattened Device Tree)")); - EXPECT_EQ("Qualcomm APQ8084", - parse_proc_cpuinfo_hardware("Qualcomm APQ8084")); - EXPECT_EQ("Qualcomm APQ8094", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc APQ8094")); - EXPECT_EQ("Qualcomm APQ8096", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc APQ8096")); + EXPECT_EQ("Qualcomm APQ8009", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc APQ8009")); + EXPECT_EQ("Qualcomm APQ8016", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc APQ8016")); + EXPECT_EQ("Qualcomm APQ8016", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc APQ8016APQ8016")); + EXPECT_EQ("Qualcomm APQ8017", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc APQ8017")); + EXPECT_EQ("Qualcomm APQ8026", parse_proc_cpuinfo_hardware("Qualcomm APQ8026")); + EXPECT_EQ("Qualcomm APQ8028", parse_proc_cpuinfo_hardware("Qualcomm APQ8028")); + EXPECT_EQ("Qualcomm APQ8039", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc APQ8039")); + EXPECT_EQ("Qualcomm APQ8053", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc APQ8053")); + EXPECT_EQ("Qualcomm APQ8064", parse_proc_cpuinfo_hardware("PANTECH APQ8064 EF48S")); + EXPECT_EQ("Qualcomm APQ8064", parse_proc_cpuinfo_hardware("PANTECH APQ8064 EF49K")); + EXPECT_EQ("Qualcomm APQ8064", parse_proc_cpuinfo_hardware("PANTECH APQ8064 EF50L")); + EXPECT_EQ("Qualcomm APQ8064", parse_proc_cpuinfo_hardware("PANTECH APQ8064 EF51K")); + EXPECT_EQ("Qualcomm APQ8064", parse_proc_cpuinfo_hardware("PANTECH APQ8064 EF51L")); + EXPECT_EQ("Qualcomm APQ8064", parse_proc_cpuinfo_hardware("PANTECH APQ8064 EF51S")); + EXPECT_EQ("Qualcomm APQ8064", parse_proc_cpuinfo_hardware("PANTECH APQ8064 EF52K")); + EXPECT_EQ("Qualcomm APQ8064", parse_proc_cpuinfo_hardware("PANTECH APQ8064 EF52L")); + EXPECT_EQ("Qualcomm APQ8064", parse_proc_cpuinfo_hardware("PANTECH APQ8064 EF52S")); + EXPECT_EQ("Qualcomm APQ8064", parse_proc_cpuinfo_hardware("QCT APQ8064 AWIFI")); + EXPECT_EQ("Qualcomm APQ8064", parse_proc_cpuinfo_hardware("QCT APQ8064 DEB")); + EXPECT_EQ("Qualcomm APQ8064", parse_proc_cpuinfo_hardware("QCT APQ8064 DUMA")); + EXPECT_EQ("Qualcomm APQ8064", parse_proc_cpuinfo_hardware("QCT APQ8064 FLO")); + EXPECT_EQ("Qualcomm APQ8064", parse_proc_cpuinfo_hardware("QCT APQ8064 LEOPARDCAT")); + EXPECT_EQ("Qualcomm APQ8064", parse_proc_cpuinfo_hardware("QCT APQ8064 MAKO")); + EXPECT_EQ("Qualcomm APQ8064", parse_proc_cpuinfo_hardware("QCT APQ8064 MTP")); + EXPECT_EQ("Qualcomm APQ8074PRO-AB", parse_proc_cpuinfo_hardware("Qualcomm APQ8074PRO-AB")); + EXPECT_EQ("Qualcomm APQ8076", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc APQ8076")); + EXPECT_EQ("Qualcomm APQ8084", parse_proc_cpuinfo_hardware("Qualcomm APQ 8084 (Flattened Device Tree)")); + EXPECT_EQ("Qualcomm APQ8084", parse_proc_cpuinfo_hardware("Qualcomm APQ8084")); + EXPECT_EQ("Qualcomm APQ8094", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc APQ8094")); + EXPECT_EQ("Qualcomm APQ8096", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc APQ8096")); } TEST(PROC_CPUINFO_HARDWARE, qualcomm_sdm) { - EXPECT_EQ("Qualcomm Snapdragon 630", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc SDM630")); - EXPECT_EQ("Qualcomm Snapdragon 660", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc SDM660")); + EXPECT_EQ("Qualcomm Snapdragon 630", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc SDM630")); + EXPECT_EQ("Qualcomm Snapdragon 660", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc SDM660")); } TEST(PROC_CPUINFO_HARDWARE, qualcomm_sm) { - EXPECT_EQ("Qualcomm Snapdragon 8150", - parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc SM8150")); + EXPECT_EQ("Qualcomm Snapdragon 8150", parse_proc_cpuinfo_hardware("Qualcomm Technologies, Inc SM8150")); } TEST(PROC_CPUINFO_HARDWARE, mediatek_mt) { - EXPECT_EQ("MediaTek MT5507", - parse_proc_cpuinfo_hardware("MT5507")); - EXPECT_EQ("MediaTek MT5508", - parse_proc_cpuinfo_hardware("MT5508")); - EXPECT_EQ("MediaTek MT6517", - parse_proc_cpuinfo_hardware("MT6517")); - EXPECT_EQ("MediaTek MT6570", - parse_proc_cpuinfo_hardware("MT6570")); - EXPECT_EQ("MediaTek MT6571", - parse_proc_cpuinfo_hardware("MT6571")); - EXPECT_EQ("MediaTek MT6572", - parse_proc_cpuinfo_hardware("MT6572")); - EXPECT_EQ("MediaTek MT6575", - parse_proc_cpuinfo_hardware("MT6575")); - EXPECT_EQ("MediaTek MT6577", - parse_proc_cpuinfo_hardware("MT6577")); - EXPECT_EQ("MediaTek MT6580", - parse_proc_cpuinfo_hardware("MT6580")); - EXPECT_EQ("MediaTek MT6580M", - parse_proc_cpuinfo_hardware("MT6580M")); - EXPECT_EQ("MediaTek MT6581", - parse_proc_cpuinfo_hardware("MT6581")); - EXPECT_EQ("MediaTek MT6582", - parse_proc_cpuinfo_hardware("MT6582")); - EXPECT_EQ("MediaTek MT6582", - parse_proc_cpuinfo_hardware("Mediatek MT6582")); - EXPECT_EQ("MediaTek MT6588", - parse_proc_cpuinfo_hardware("MT6588")); - EXPECT_EQ("MediaTek MT6589", - parse_proc_cpuinfo_hardware("MT6589")); - EXPECT_EQ("MediaTek MT6591", - parse_proc_cpuinfo_hardware("MT6591")); - EXPECT_EQ("MediaTek MT6592", - parse_proc_cpuinfo_hardware("MT6592")); - EXPECT_EQ("MediaTek MT6592T", - parse_proc_cpuinfo_hardware("MT6592T")); - EXPECT_EQ("MediaTek MT6592T", - parse_proc_cpuinfo_hardware("MT6592trubo")); - EXPECT_EQ("MediaTek MT6592T", - parse_proc_cpuinfo_hardware("MT6592turbo")); - EXPECT_EQ("MediaTek MT6595", - parse_proc_cpuinfo_hardware("MT6595")); - EXPECT_EQ("MediaTek MT6732", - parse_proc_cpuinfo_hardware("MT6732")); - EXPECT_EQ("MediaTek MT6732", - parse_proc_cpuinfo_hardware("MT6752", 4)); - EXPECT_EQ("MediaTek MT6732M", - parse_proc_cpuinfo_hardware("MT6732M")); - EXPECT_EQ("MediaTek MT6735", - parse_proc_cpuinfo_hardware("MT6735")); - EXPECT_EQ("MediaTek MT6735M", - parse_proc_cpuinfo_hardware("MT6735M")); - EXPECT_EQ("MediaTek MT6735P", - parse_proc_cpuinfo_hardware("MT6735P")); - EXPECT_EQ("MediaTek MT6737", - parse_proc_cpuinfo_hardware("MT6737")); - EXPECT_EQ("MediaTek MT6737M", - parse_proc_cpuinfo_hardware("MT6737M")); - EXPECT_EQ("MediaTek MT6737T", - parse_proc_cpuinfo_hardware("MT6737T")); - EXPECT_EQ("MediaTek MT6737T", + EXPECT_EQ("MediaTek MT5507", parse_proc_cpuinfo_hardware("MT5507")); + EXPECT_EQ("MediaTek MT5508", parse_proc_cpuinfo_hardware("MT5508")); + EXPECT_EQ("MediaTek MT6517", parse_proc_cpuinfo_hardware("MT6517")); + EXPECT_EQ("MediaTek MT6570", parse_proc_cpuinfo_hardware("MT6570")); + EXPECT_EQ("MediaTek MT6571", parse_proc_cpuinfo_hardware("MT6571")); + EXPECT_EQ("MediaTek MT6572", parse_proc_cpuinfo_hardware("MT6572")); + EXPECT_EQ("MediaTek MT6575", parse_proc_cpuinfo_hardware("MT6575")); + EXPECT_EQ("MediaTek MT6577", parse_proc_cpuinfo_hardware("MT6577")); + EXPECT_EQ("MediaTek MT6580", parse_proc_cpuinfo_hardware("MT6580")); + EXPECT_EQ("MediaTek MT6580M", parse_proc_cpuinfo_hardware("MT6580M")); + EXPECT_EQ("MediaTek MT6581", parse_proc_cpuinfo_hardware("MT6581")); + EXPECT_EQ("MediaTek MT6582", parse_proc_cpuinfo_hardware("MT6582")); + EXPECT_EQ("MediaTek MT6582", parse_proc_cpuinfo_hardware("Mediatek MT6582")); + EXPECT_EQ("MediaTek MT6588", parse_proc_cpuinfo_hardware("MT6588")); + EXPECT_EQ("MediaTek MT6589", parse_proc_cpuinfo_hardware("MT6589")); + EXPECT_EQ("MediaTek MT6591", parse_proc_cpuinfo_hardware("MT6591")); + EXPECT_EQ("MediaTek MT6592", parse_proc_cpuinfo_hardware("MT6592")); + EXPECT_EQ("MediaTek MT6592T", parse_proc_cpuinfo_hardware("MT6592T")); + EXPECT_EQ("MediaTek MT6592T", parse_proc_cpuinfo_hardware("MT6592trubo")); + EXPECT_EQ("MediaTek MT6592T", parse_proc_cpuinfo_hardware("MT6592turbo")); + EXPECT_EQ("MediaTek MT6595", parse_proc_cpuinfo_hardware("MT6595")); + EXPECT_EQ("MediaTek MT6732", parse_proc_cpuinfo_hardware("MT6732")); + EXPECT_EQ("MediaTek MT6732", parse_proc_cpuinfo_hardware("MT6752", 4)); + EXPECT_EQ("MediaTek MT6732M", parse_proc_cpuinfo_hardware("MT6732M")); + EXPECT_EQ("MediaTek MT6735", parse_proc_cpuinfo_hardware("MT6735")); + EXPECT_EQ("MediaTek MT6735M", parse_proc_cpuinfo_hardware("MT6735M")); + EXPECT_EQ("MediaTek MT6735P", parse_proc_cpuinfo_hardware("MT6735P")); + EXPECT_EQ("MediaTek MT6737", parse_proc_cpuinfo_hardware("MT6737")); + EXPECT_EQ("MediaTek MT6737M", parse_proc_cpuinfo_hardware("MT6737M")); + EXPECT_EQ("MediaTek MT6737T", parse_proc_cpuinfo_hardware("MT6737T")); + EXPECT_EQ( + "MediaTek MT6737T", parse_proc_cpuinfo_hardware("Samsung GrandPrimePlus LTE CIS rev04 board based on MT6737T")); - EXPECT_EQ("MediaTek MT6737T", + EXPECT_EQ( + "MediaTek MT6737T", parse_proc_cpuinfo_hardware("Samsung GrandPrimePlus LTE LTN DTV rev04 board based on MT6737T")); - EXPECT_EQ("MediaTek MT6737T", + EXPECT_EQ( + "MediaTek MT6737T", parse_proc_cpuinfo_hardware("Samsung GrandPrimePlus LTE LTN OPEN rev04 board based on MT6737T")); - EXPECT_EQ("MediaTek MT6738", - parse_proc_cpuinfo_hardware("MT6738")); - EXPECT_EQ("MediaTek MT6750", - parse_proc_cpuinfo_hardware("MT6750")); - EXPECT_EQ("MediaTek MT6750T", - parse_proc_cpuinfo_hardware("MT6750T")); - EXPECT_EQ("MediaTek MT6752", - parse_proc_cpuinfo_hardware("MT6752", 8)); - EXPECT_EQ("MediaTek MT6752M", - parse_proc_cpuinfo_hardware("MT6752M", 8)); - EXPECT_EQ("MediaTek MT6753", - parse_proc_cpuinfo_hardware("MT6753")); - EXPECT_EQ("MediaTek MT6753T", - parse_proc_cpuinfo_hardware("MT6753T")); - EXPECT_EQ("MediaTek MT6755", - parse_proc_cpuinfo_hardware("MT6755")); - EXPECT_EQ("MediaTek MT6755BM", - parse_proc_cpuinfo_hardware("MT6755BM")); - EXPECT_EQ("MediaTek MT6755M", - parse_proc_cpuinfo_hardware("MT6755M")); - EXPECT_EQ("MediaTek MT6755V/B", - parse_proc_cpuinfo_hardware("MT6755V/B")); - EXPECT_EQ("MediaTek MT6755V/BM", - parse_proc_cpuinfo_hardware("MT6755V/BM")); - EXPECT_EQ("MediaTek MT6755V/C", - parse_proc_cpuinfo_hardware("MT6755V/C")); - EXPECT_EQ("MediaTek MT6755V/CM", - parse_proc_cpuinfo_hardware("MT6755V/CM")); - EXPECT_EQ("MediaTek MT6755V/W", - parse_proc_cpuinfo_hardware("MT6755V/W")); - EXPECT_EQ("MediaTek MT6755V/WM", - parse_proc_cpuinfo_hardware("MT6755V/WM")); - EXPECT_EQ("MediaTek MT6755V/WT", - parse_proc_cpuinfo_hardware("MT6755V/WT")); - EXPECT_EQ("MediaTek MT6757", - parse_proc_cpuinfo_hardware("MT6757")); - EXPECT_EQ("MediaTek MT6757", - parse_proc_cpuinfo_hardware("Samsung J7 Max LTE SWA rev02a board based on MT6757")); - EXPECT_EQ("MediaTek MT6757CD", - parse_proc_cpuinfo_hardware("MT6757CD")); - EXPECT_EQ("MediaTek MT6757CH", - parse_proc_cpuinfo_hardware("MT6757CH")); - EXPECT_EQ("MediaTek MT6795", - parse_proc_cpuinfo_hardware("MT6795")); - EXPECT_EQ("MediaTek MT6795M", - parse_proc_cpuinfo_hardware("MT6795M")); - EXPECT_EQ("MediaTek MT6795MM", - parse_proc_cpuinfo_hardware("MT6795MM")); - EXPECT_EQ("MediaTek MT6795T", - parse_proc_cpuinfo_hardware("MT6795T")); - EXPECT_EQ("MediaTek MT6797", - parse_proc_cpuinfo_hardware("MT6797")); - EXPECT_EQ("MediaTek MT6797M", - parse_proc_cpuinfo_hardware("MT6797M")); - EXPECT_EQ("MediaTek MT6797T", - parse_proc_cpuinfo_hardware("MT6797T")); - EXPECT_EQ("MediaTek MT6797X", - parse_proc_cpuinfo_hardware("MT6797X")); - EXPECT_EQ("MediaTek MT8111", - parse_proc_cpuinfo_hardware("MT8111")); - EXPECT_EQ("MediaTek MT8121", - parse_proc_cpuinfo_hardware("MT8121")); - EXPECT_EQ("MediaTek MT8125", - parse_proc_cpuinfo_hardware("MT8125")); - EXPECT_EQ("MediaTek MT8127", - parse_proc_cpuinfo_hardware("MT8127")); - EXPECT_EQ("MediaTek MT8135", - parse_proc_cpuinfo_hardware("MT8135")); - EXPECT_EQ("MediaTek MT8151", - parse_proc_cpuinfo_hardware("MT8151")); - EXPECT_EQ("MediaTek MT8161", - parse_proc_cpuinfo_hardware("MT8161")); - EXPECT_EQ("MediaTek MT8161A", - parse_proc_cpuinfo_hardware("MT8161A")); - EXPECT_EQ("MediaTek MT8161P", - parse_proc_cpuinfo_hardware("MT8161P")); - EXPECT_EQ("MediaTek MT8163", - parse_proc_cpuinfo_hardware("MT8163")); - EXPECT_EQ("MediaTek MT8165", - parse_proc_cpuinfo_hardware("MT8165")); - EXPECT_EQ("MediaTek MT8167A", - parse_proc_cpuinfo_hardware("MT8167A")); - EXPECT_EQ("MediaTek MT8167B", - parse_proc_cpuinfo_hardware("MT8167B")); - EXPECT_EQ("MediaTek MT8173", - parse_proc_cpuinfo_hardware("MT8173")); - EXPECT_EQ("MediaTek MT8176", - parse_proc_cpuinfo_hardware("MT8176")); - EXPECT_EQ("MediaTek MT8312", - parse_proc_cpuinfo_hardware("MT8312")); - EXPECT_EQ("MediaTek MT8312C", - parse_proc_cpuinfo_hardware("MT8312C")); - EXPECT_EQ("MediaTek MT8312D", - parse_proc_cpuinfo_hardware("MT8312D")); - EXPECT_EQ("MediaTek MT8317", - parse_proc_cpuinfo_hardware("MT8317")); - EXPECT_EQ("MediaTek MT8321", - parse_proc_cpuinfo_hardware("MT8321")); - EXPECT_EQ("MediaTek MT8321M", - parse_proc_cpuinfo_hardware("MT8321M")); - EXPECT_EQ("MediaTek MT8377", - parse_proc_cpuinfo_hardware("MT8377")); - EXPECT_EQ("MediaTek MT8382", - parse_proc_cpuinfo_hardware("MT8382")); - EXPECT_EQ("MediaTek MT8389", - parse_proc_cpuinfo_hardware("MT8389")); - EXPECT_EQ("MediaTek MT8389Q", - parse_proc_cpuinfo_hardware("MT8389Q")); - EXPECT_EQ("MediaTek MT8392", - parse_proc_cpuinfo_hardware("MT8392")); - EXPECT_EQ("MediaTek MT8685", - parse_proc_cpuinfo_hardware("MT8685")); - EXPECT_EQ("MediaTek MT8732", - parse_proc_cpuinfo_hardware("MT8732")); - EXPECT_EQ("MediaTek MT8732T", - parse_proc_cpuinfo_hardware("MT8732T")); - EXPECT_EQ("MediaTek MT8735", - parse_proc_cpuinfo_hardware("MT8735")); - EXPECT_EQ("MediaTek MT8735A", - parse_proc_cpuinfo_hardware("MT8735A")); - EXPECT_EQ("MediaTek MT8735B", - parse_proc_cpuinfo_hardware("MT8735B")); - EXPECT_EQ("MediaTek MT8735D", - parse_proc_cpuinfo_hardware("MT8735D")); - EXPECT_EQ("MediaTek MT8735M", - parse_proc_cpuinfo_hardware("MT8735M")); - EXPECT_EQ("MediaTek MT8735P", - parse_proc_cpuinfo_hardware("MT8735P")); - EXPECT_EQ("MediaTek MT8735T", - parse_proc_cpuinfo_hardware("MT8735T")); - EXPECT_EQ("MediaTek MT8752", - parse_proc_cpuinfo_hardware("MT8752")); - EXPECT_EQ("MediaTek MT8783", - parse_proc_cpuinfo_hardware("MT8783")); - EXPECT_EQ("MediaTek MT8783T", - parse_proc_cpuinfo_hardware("MT8783T")); + EXPECT_EQ("MediaTek MT6738", parse_proc_cpuinfo_hardware("MT6738")); + EXPECT_EQ("MediaTek MT6750", parse_proc_cpuinfo_hardware("MT6750")); + EXPECT_EQ("MediaTek MT6750T", parse_proc_cpuinfo_hardware("MT6750T")); + EXPECT_EQ("MediaTek MT6752", parse_proc_cpuinfo_hardware("MT6752", 8)); + EXPECT_EQ("MediaTek MT6752M", parse_proc_cpuinfo_hardware("MT6752M", 8)); + EXPECT_EQ("MediaTek MT6753", parse_proc_cpuinfo_hardware("MT6753")); + EXPECT_EQ("MediaTek MT6753T", parse_proc_cpuinfo_hardware("MT6753T")); + EXPECT_EQ("MediaTek MT6755", parse_proc_cpuinfo_hardware("MT6755")); + EXPECT_EQ("MediaTek MT6755BM", parse_proc_cpuinfo_hardware("MT6755BM")); + EXPECT_EQ("MediaTek MT6755M", parse_proc_cpuinfo_hardware("MT6755M")); + EXPECT_EQ("MediaTek MT6755V/B", parse_proc_cpuinfo_hardware("MT6755V/B")); + EXPECT_EQ("MediaTek MT6755V/BM", parse_proc_cpuinfo_hardware("MT6755V/BM")); + EXPECT_EQ("MediaTek MT6755V/C", parse_proc_cpuinfo_hardware("MT6755V/C")); + EXPECT_EQ("MediaTek MT6755V/CM", parse_proc_cpuinfo_hardware("MT6755V/CM")); + EXPECT_EQ("MediaTek MT6755V/W", parse_proc_cpuinfo_hardware("MT6755V/W")); + EXPECT_EQ("MediaTek MT6755V/WM", parse_proc_cpuinfo_hardware("MT6755V/WM")); + EXPECT_EQ("MediaTek MT6755V/WT", parse_proc_cpuinfo_hardware("MT6755V/WT")); + EXPECT_EQ("MediaTek MT6757", parse_proc_cpuinfo_hardware("MT6757")); + EXPECT_EQ( + "MediaTek MT6757", parse_proc_cpuinfo_hardware("Samsung J7 Max LTE SWA rev02a board based on MT6757")); + EXPECT_EQ("MediaTek MT6757CD", parse_proc_cpuinfo_hardware("MT6757CD")); + EXPECT_EQ("MediaTek MT6757CH", parse_proc_cpuinfo_hardware("MT6757CH")); + EXPECT_EQ("MediaTek MT6795", parse_proc_cpuinfo_hardware("MT6795")); + EXPECT_EQ("MediaTek MT6795M", parse_proc_cpuinfo_hardware("MT6795M")); + EXPECT_EQ("MediaTek MT6795MM", parse_proc_cpuinfo_hardware("MT6795MM")); + EXPECT_EQ("MediaTek MT6795T", parse_proc_cpuinfo_hardware("MT6795T")); + EXPECT_EQ("MediaTek MT6797", parse_proc_cpuinfo_hardware("MT6797")); + EXPECT_EQ("MediaTek MT6797M", parse_proc_cpuinfo_hardware("MT6797M")); + EXPECT_EQ("MediaTek MT6797T", parse_proc_cpuinfo_hardware("MT6797T")); + EXPECT_EQ("MediaTek MT6797X", parse_proc_cpuinfo_hardware("MT6797X")); + EXPECT_EQ("MediaTek MT8111", parse_proc_cpuinfo_hardware("MT8111")); + EXPECT_EQ("MediaTek MT8121", parse_proc_cpuinfo_hardware("MT8121")); + EXPECT_EQ("MediaTek MT8125", parse_proc_cpuinfo_hardware("MT8125")); + EXPECT_EQ("MediaTek MT8127", parse_proc_cpuinfo_hardware("MT8127")); + EXPECT_EQ("MediaTek MT8135", parse_proc_cpuinfo_hardware("MT8135")); + EXPECT_EQ("MediaTek MT8151", parse_proc_cpuinfo_hardware("MT8151")); + EXPECT_EQ("MediaTek MT8161", parse_proc_cpuinfo_hardware("MT8161")); + EXPECT_EQ("MediaTek MT8161A", parse_proc_cpuinfo_hardware("MT8161A")); + EXPECT_EQ("MediaTek MT8161P", parse_proc_cpuinfo_hardware("MT8161P")); + EXPECT_EQ("MediaTek MT8163", parse_proc_cpuinfo_hardware("MT8163")); + EXPECT_EQ("MediaTek MT8165", parse_proc_cpuinfo_hardware("MT8165")); + EXPECT_EQ("MediaTek MT8167A", parse_proc_cpuinfo_hardware("MT8167A")); + EXPECT_EQ("MediaTek MT8167B", parse_proc_cpuinfo_hardware("MT8167B")); + EXPECT_EQ("MediaTek MT8173", parse_proc_cpuinfo_hardware("MT8173")); + EXPECT_EQ("MediaTek MT8176", parse_proc_cpuinfo_hardware("MT8176")); + EXPECT_EQ("MediaTek MT8312", parse_proc_cpuinfo_hardware("MT8312")); + EXPECT_EQ("MediaTek MT8312C", parse_proc_cpuinfo_hardware("MT8312C")); + EXPECT_EQ("MediaTek MT8312D", parse_proc_cpuinfo_hardware("MT8312D")); + EXPECT_EQ("MediaTek MT8317", parse_proc_cpuinfo_hardware("MT8317")); + EXPECT_EQ("MediaTek MT8321", parse_proc_cpuinfo_hardware("MT8321")); + EXPECT_EQ("MediaTek MT8321M", parse_proc_cpuinfo_hardware("MT8321M")); + EXPECT_EQ("MediaTek MT8377", parse_proc_cpuinfo_hardware("MT8377")); + EXPECT_EQ("MediaTek MT8382", parse_proc_cpuinfo_hardware("MT8382")); + EXPECT_EQ("MediaTek MT8389", parse_proc_cpuinfo_hardware("MT8389")); + EXPECT_EQ("MediaTek MT8389Q", parse_proc_cpuinfo_hardware("MT8389Q")); + EXPECT_EQ("MediaTek MT8392", parse_proc_cpuinfo_hardware("MT8392")); + EXPECT_EQ("MediaTek MT8685", parse_proc_cpuinfo_hardware("MT8685")); + EXPECT_EQ("MediaTek MT8732", parse_proc_cpuinfo_hardware("MT8732")); + EXPECT_EQ("MediaTek MT8732T", parse_proc_cpuinfo_hardware("MT8732T")); + EXPECT_EQ("MediaTek MT8735", parse_proc_cpuinfo_hardware("MT8735")); + EXPECT_EQ("MediaTek MT8735A", parse_proc_cpuinfo_hardware("MT8735A")); + EXPECT_EQ("MediaTek MT8735B", parse_proc_cpuinfo_hardware("MT8735B")); + EXPECT_EQ("MediaTek MT8735D", parse_proc_cpuinfo_hardware("MT8735D")); + EXPECT_EQ("MediaTek MT8735M", parse_proc_cpuinfo_hardware("MT8735M")); + EXPECT_EQ("MediaTek MT8735P", parse_proc_cpuinfo_hardware("MT8735P")); + EXPECT_EQ("MediaTek MT8735T", parse_proc_cpuinfo_hardware("MT8735T")); + EXPECT_EQ("MediaTek MT8752", parse_proc_cpuinfo_hardware("MT8752")); + EXPECT_EQ("MediaTek MT8783", parse_proc_cpuinfo_hardware("MT8783")); + EXPECT_EQ("MediaTek MT8783T", parse_proc_cpuinfo_hardware("MT8783T")); } TEST(PROC_CPUINFO_HARDWARE, samsung_exynos) { - EXPECT_EQ("Samsung Exynos 4415", - parse_proc_cpuinfo_hardware("Samsung EXYNOS4415")); - EXPECT_EQ("Samsung Exynos 5420", - parse_proc_cpuinfo_hardware("Samsung EXYNOS5420", 4)); - EXPECT_EQ("Samsung Exynos 5430", - parse_proc_cpuinfo_hardware("Samsung EXYNOS5430")); - EXPECT_EQ("Samsung Exynos 5433", - parse_proc_cpuinfo_hardware("Samsung EXYNOS5433")); - EXPECT_EQ("Samsung Exynos 7420", - parse_proc_cpuinfo_hardware("SAMSUNG Exynos7420")); - EXPECT_EQ("Samsung Exynos 7578", - parse_proc_cpuinfo_hardware("SAMSUNG Exynos7580", 4)); - EXPECT_EQ("Samsung Exynos 7580", - parse_proc_cpuinfo_hardware("SAMSUNG Exynos7580", 8)); + EXPECT_EQ("Samsung Exynos 4415", parse_proc_cpuinfo_hardware("Samsung EXYNOS4415")); + EXPECT_EQ("Samsung Exynos 5420", parse_proc_cpuinfo_hardware("Samsung EXYNOS5420", 4)); + EXPECT_EQ("Samsung Exynos 5430", parse_proc_cpuinfo_hardware("Samsung EXYNOS5430")); + EXPECT_EQ("Samsung Exynos 5433", parse_proc_cpuinfo_hardware("Samsung EXYNOS5433")); + EXPECT_EQ("Samsung Exynos 7420", parse_proc_cpuinfo_hardware("SAMSUNG Exynos7420")); + EXPECT_EQ("Samsung Exynos 7578", parse_proc_cpuinfo_hardware("SAMSUNG Exynos7580", 4)); + EXPECT_EQ("Samsung Exynos 7580", parse_proc_cpuinfo_hardware("SAMSUNG Exynos7580", 8)); } TEST(PROC_CPUINFO_HARDWARE, samsung_universal) { - EXPECT_EQ("Samsung Exynos 3470", - parse_proc_cpuinfo_hardware("UNIVERSAL3470")); - EXPECT_EQ("Samsung Exynos 3475", - parse_proc_cpuinfo_hardware("UNIVERSAL3475")); - EXPECT_EQ("Samsung Exynos 5260", - parse_proc_cpuinfo_hardware("UNIVERSAL5260")); - EXPECT_EQ("Samsung Exynos 5410", - parse_proc_cpuinfo_hardware("UNIVERSAL5410")); - EXPECT_EQ("Samsung Exynos 5420", - parse_proc_cpuinfo_hardware("UNIVERSAL5420", 4)); - EXPECT_EQ("Samsung Exynos 5422", - parse_proc_cpuinfo_hardware("universal5422")); - EXPECT_EQ("Samsung Exynos 5430", - parse_proc_cpuinfo_hardware("UNIVERSAL5430")); + EXPECT_EQ("Samsung Exynos 3470", parse_proc_cpuinfo_hardware("UNIVERSAL3470")); + EXPECT_EQ("Samsung Exynos 3475", parse_proc_cpuinfo_hardware("UNIVERSAL3475")); + EXPECT_EQ("Samsung Exynos 5260", parse_proc_cpuinfo_hardware("UNIVERSAL5260")); + EXPECT_EQ("Samsung Exynos 5410", parse_proc_cpuinfo_hardware("UNIVERSAL5410")); + EXPECT_EQ("Samsung Exynos 5420", parse_proc_cpuinfo_hardware("UNIVERSAL5420", 4)); + EXPECT_EQ("Samsung Exynos 5422", parse_proc_cpuinfo_hardware("universal5422")); + EXPECT_EQ("Samsung Exynos 5430", parse_proc_cpuinfo_hardware("UNIVERSAL5430")); } #if CPUINFO_ARCH_ARM - TEST(PROC_CPUINFO_HARDWARE, samsung_smdk) { - EXPECT_EQ("Samsung Exynos 4210", - parse_proc_cpuinfo_hardware("SMDK4210")); - EXPECT_EQ("Samsung Exynos 4212", - parse_proc_cpuinfo_hardware("SMDK4x12", 2)); - EXPECT_EQ("Samsung Exynos 4412", - parse_proc_cpuinfo_hardware("SMDK4x12", 4)); - } +TEST(PROC_CPUINFO_HARDWARE, samsung_smdk) { + EXPECT_EQ("Samsung Exynos 4210", parse_proc_cpuinfo_hardware("SMDK4210")); + EXPECT_EQ("Samsung Exynos 4212", parse_proc_cpuinfo_hardware("SMDK4x12", 2)); + EXPECT_EQ("Samsung Exynos 4412", parse_proc_cpuinfo_hardware("SMDK4x12", 4)); +} - TEST(PROC_CPUINFO_HARDWARE, samsung_special) { - EXPECT_EQ("Samsung Exynos 5250", - parse_proc_cpuinfo_hardware("Manta")); - } +TEST(PROC_CPUINFO_HARDWARE, samsung_special) { + EXPECT_EQ("Samsung Exynos 5250", parse_proc_cpuinfo_hardware("Manta")); +} #endif /* CPUINFO_ARCH_ARM */ TEST(PROC_CPUINFO_HARDWARE, hisilicon_kirin) { #if CPUINFO_ARCH_ARM - EXPECT_EQ("HiSilicon Kirin 920", - parse_proc_cpuinfo_hardware("Hisilicon Kirin 920")); - EXPECT_EQ("HiSilicon Kirin 920", - parse_proc_cpuinfo_hardware("Kirin920")); - EXPECT_EQ("HiSilicon Kirin 925", - parse_proc_cpuinfo_hardware("Hisilicon Kirin 925")); - EXPECT_EQ("HiSilicon Kirin 925", - parse_proc_cpuinfo_hardware("Kirin925")); + EXPECT_EQ("HiSilicon Kirin 920", parse_proc_cpuinfo_hardware("Hisilicon Kirin 920")); + EXPECT_EQ("HiSilicon Kirin 920", parse_proc_cpuinfo_hardware("Kirin920")); + EXPECT_EQ("HiSilicon Kirin 925", parse_proc_cpuinfo_hardware("Hisilicon Kirin 925")); + EXPECT_EQ("HiSilicon Kirin 925", parse_proc_cpuinfo_hardware("Kirin925")); #endif /* CPUINFO_ARCH_ARM */ - EXPECT_EQ("HiSilicon Kirin 930", - parse_proc_cpuinfo_hardware("Hisilicon Kirin 930")); - EXPECT_EQ("HiSilicon Kirin 935", - parse_proc_cpuinfo_hardware("Hisilicon Kirin 935")); - EXPECT_EQ("HiSilicon Kirin 950", - parse_proc_cpuinfo_hardware("Hisilicon Kirin 950")); - EXPECT_EQ("HiSilicon Kirin 955", - parse_proc_cpuinfo_hardware("Hisilicon Kirin 955")); + EXPECT_EQ("HiSilicon Kirin 930", parse_proc_cpuinfo_hardware("Hisilicon Kirin 930")); + EXPECT_EQ("HiSilicon Kirin 935", parse_proc_cpuinfo_hardware("Hisilicon Kirin 935")); + EXPECT_EQ("HiSilicon Kirin 950", parse_proc_cpuinfo_hardware("Hisilicon Kirin 950")); + EXPECT_EQ("HiSilicon Kirin 955", parse_proc_cpuinfo_hardware("Hisilicon Kirin 955")); } TEST(PROC_CPUINFO_HARDWARE, hisilicon_special) { - EXPECT_EQ("HiSilicon Hi3751", - parse_proc_cpuinfo_hardware("hi3751")); + EXPECT_EQ("HiSilicon Hi3751", parse_proc_cpuinfo_hardware("hi3751")); #if CPUINFO_ARCH_ARM - EXPECT_EQ("HiSilicon K3V2", - parse_proc_cpuinfo_hardware("k3v2oem1")); + EXPECT_EQ("HiSilicon K3V2", parse_proc_cpuinfo_hardware("k3v2oem1")); #endif /* CPUINFO_ARCH_ARM */ - EXPECT_EQ("HiSilicon Kirin 620", - parse_proc_cpuinfo_hardware("hi6210sft")); - EXPECT_EQ("HiSilicon Kirin 650", - parse_proc_cpuinfo_hardware("hi6250")); + EXPECT_EQ("HiSilicon Kirin 620", parse_proc_cpuinfo_hardware("hi6210sft")); + EXPECT_EQ("HiSilicon Kirin 650", parse_proc_cpuinfo_hardware("hi6250")); #if CPUINFO_ARCH_ARM - EXPECT_EQ("HiSilicon Kirin 910T", - parse_proc_cpuinfo_hardware("hi6620oem")); + EXPECT_EQ("HiSilicon Kirin 910T", parse_proc_cpuinfo_hardware("hi6620oem")); #endif /* CPUINFO_ARCH_ARM */ } #if CPUINFO_ARCH_ARM - TEST(PROC_CPUINFO_HARDWARE, actions) { - EXPECT_EQ("Actions ATM7029", - parse_proc_cpuinfo_hardware("gs702a")); - EXPECT_EQ("Actions ATM7029B", - parse_proc_cpuinfo_hardware("gs702c")); - EXPECT_EQ("Actions ATM7059A", - parse_proc_cpuinfo_hardware("gs705a")); - } +TEST(PROC_CPUINFO_HARDWARE, actions) { + EXPECT_EQ("Actions ATM7029", parse_proc_cpuinfo_hardware("gs702a")); + EXPECT_EQ("Actions ATM7029B", parse_proc_cpuinfo_hardware("gs702c")); + EXPECT_EQ("Actions ATM7059A", parse_proc_cpuinfo_hardware("gs705a")); +} #endif /* CPUINFO_ARCH_ARM */ TEST(PROC_CPUINFO_HARDWARE, allwinner_sunxi) { #if CPUINFO_ARCH_ARM - EXPECT_EQ("Allwinner A10", - parse_proc_cpuinfo_hardware("sun4i", 1)); - EXPECT_EQ("Allwinner A13", - parse_proc_cpuinfo_hardware("sun5i", 1)); - EXPECT_EQ("Allwinner A20", - parse_proc_cpuinfo_hardware("sun7i", 2)); - EXPECT_EQ("Allwinner A23", - parse_proc_cpuinfo_hardware("sun8i", 2)); - EXPECT_EQ("Allwinner A31", - parse_proc_cpuinfo_hardware("sun6i", 4)); - EXPECT_EQ("Allwinner A33", - parse_proc_cpuinfo_hardware("sun8i", 4)); + EXPECT_EQ("Allwinner A10", parse_proc_cpuinfo_hardware("sun4i", 1)); + EXPECT_EQ("Allwinner A13", parse_proc_cpuinfo_hardware("sun5i", 1)); + EXPECT_EQ("Allwinner A20", parse_proc_cpuinfo_hardware("sun7i", 2)); + EXPECT_EQ("Allwinner A23", parse_proc_cpuinfo_hardware("sun8i", 2)); + EXPECT_EQ("Allwinner A31", parse_proc_cpuinfo_hardware("sun6i", 4)); + EXPECT_EQ("Allwinner A33", parse_proc_cpuinfo_hardware("sun8i", 4)); #endif /* CPUINFO_ARCH_ARM */ - EXPECT_EQ("Allwinner A64", - parse_proc_cpuinfo_hardware("sun50iw1", 4)); - EXPECT_EQ("Allwinner A64", - parse_proc_cpuinfo_hardware("sun50iw1p1", 4)); - EXPECT_EQ("Allwinner A64", - parse_proc_cpuinfo_hardware("sun50iw2", 4)); + EXPECT_EQ("Allwinner A64", parse_proc_cpuinfo_hardware("sun50iw1", 4)); + EXPECT_EQ("Allwinner A64", parse_proc_cpuinfo_hardware("sun50iw1p1", 4)); + EXPECT_EQ("Allwinner A64", parse_proc_cpuinfo_hardware("sun50iw2", 4)); #if CPUINFO_ARCH_ARM - EXPECT_EQ("Allwinner A80", - parse_proc_cpuinfo_hardware("sun9i", 8)); - EXPECT_EQ("Allwinner A83T", - parse_proc_cpuinfo_hardware("sun8i", 8)); + EXPECT_EQ("Allwinner A80", parse_proc_cpuinfo_hardware("sun9i", 8)); + EXPECT_EQ("Allwinner A83T", parse_proc_cpuinfo_hardware("sun8i", 8)); #endif /* CPUINFO_ARCH_ARM */ } #if CPUINFO_ARCH_ARM - TEST(PROC_CPUINFO_HARDWARE, amlogic) { - EXPECT_EQ("Amlogic S805", - parse_proc_cpuinfo_hardware("Amlogic Meson8B")); - EXPECT_EQ("Amlogic S812", - parse_proc_cpuinfo_hardware("Amlogic Meson8")); - } +TEST(PROC_CPUINFO_HARDWARE, amlogic) { + EXPECT_EQ("Amlogic S805", parse_proc_cpuinfo_hardware("Amlogic Meson8B")); + EXPECT_EQ("Amlogic S812", parse_proc_cpuinfo_hardware("Amlogic Meson8")); +} - TEST(PROC_CPUINFO_HARDWARE, lg) { - EXPECT_EQ("LG Nuclun 7111", - parse_proc_cpuinfo_hardware("Odin")); - } +TEST(PROC_CPUINFO_HARDWARE, lg) { + EXPECT_EQ("LG Nuclun 7111", parse_proc_cpuinfo_hardware("Odin")); +} - TEST(PROC_CPUINFO_HARDWARE, marvell_pxa) { - EXPECT_EQ("Marvell PXA1088", - parse_proc_cpuinfo_hardware("PXA1088")); - EXPECT_EQ("Marvell PXA1088", - parse_proc_cpuinfo_hardware("PXA1L88")); - EXPECT_EQ("Marvell PXA1908", - parse_proc_cpuinfo_hardware("PXA1908")); - EXPECT_EQ("Marvell PXA1928", - parse_proc_cpuinfo_hardware("PXA1928")); - EXPECT_EQ("Marvell PXA988", - parse_proc_cpuinfo_hardware("PXA988")); - } +TEST(PROC_CPUINFO_HARDWARE, marvell_pxa) { + EXPECT_EQ("Marvell PXA1088", parse_proc_cpuinfo_hardware("PXA1088")); + EXPECT_EQ("Marvell PXA1088", parse_proc_cpuinfo_hardware("PXA1L88")); + EXPECT_EQ("Marvell PXA1908", parse_proc_cpuinfo_hardware("PXA1908")); + EXPECT_EQ("Marvell PXA1928", parse_proc_cpuinfo_hardware("PXA1928")); + EXPECT_EQ("Marvell PXA988", parse_proc_cpuinfo_hardware("PXA988")); +} - TEST(PROC_CPUINFO_HARDWARE, mstar) { - EXPECT_EQ("MStar 6A338", - parse_proc_cpuinfo_hardware("Madison")); - } +TEST(PROC_CPUINFO_HARDWARE, mstar) { + EXPECT_EQ("MStar 6A338", parse_proc_cpuinfo_hardware("Madison")); +} - TEST(PROC_CPUINFO_HARDWARE, nvidia) { - EXPECT_EQ("Nvidia Tegra AP20H", - parse_proc_cpuinfo_hardware_tegra("picasso")); - EXPECT_EQ("Nvidia Tegra AP20H", - parse_proc_cpuinfo_hardware_tegra("picasso_e")); - EXPECT_EQ("Nvidia Tegra AP20H", - parse_proc_cpuinfo_hardware_tegra("stingray")); - EXPECT_EQ("Nvidia Tegra AP33", - parse_proc_cpuinfo_hardware_tegra("endeavoru")); - EXPECT_EQ("Nvidia Tegra AP33", - parse_proc_cpuinfo_hardware_tegra("x3")); - EXPECT_EQ("Nvidia Tegra SL460N", - parse_proc_cpuinfo_hardware_tegra("Ceres")); - EXPECT_EQ("Nvidia Tegra T114", - parse_proc_cpuinfo_hardware_tegra("macallan")); - EXPECT_EQ("Nvidia Tegra T114", - parse_proc_cpuinfo_hardware_tegra("mozart")); - EXPECT_EQ("Nvidia Tegra T114", - parse_proc_cpuinfo_hardware_tegra("tostab12BA")); - EXPECT_EQ("Nvidia Tegra T124", - parse_proc_cpuinfo_hardware_tegra("mocha")); - EXPECT_EQ("Nvidia Tegra T124", - parse_proc_cpuinfo_hardware_tegra("tn8")); - EXPECT_EQ("Nvidia Tegra T20", - parse_proc_cpuinfo_hardware_tegra("nbx03")); - EXPECT_EQ("Nvidia Tegra T20", - parse_proc_cpuinfo_hardware_tegra("p3")); - EXPECT_EQ("Nvidia Tegra T20", - parse_proc_cpuinfo_hardware_tegra("ventana")); - EXPECT_EQ("Nvidia Tegra T30", - parse_proc_cpuinfo_hardware_tegra("cardhu")); - EXPECT_EQ("Nvidia Tegra T30", - parse_proc_cpuinfo_hardware_tegra("chagall")); - EXPECT_EQ("Nvidia Tegra T30", - parse_proc_cpuinfo_hardware_tegra("picasso_m")); - EXPECT_EQ("Nvidia Tegra T30", - parse_proc_cpuinfo_hardware_tegra("picasso_mf")); - EXPECT_EQ("Nvidia Tegra T30L", - parse_proc_cpuinfo_hardware_tegra("BIRCH")); - EXPECT_EQ("Nvidia Tegra T30L", - parse_proc_cpuinfo_hardware_tegra("NS_14T004")); - EXPECT_EQ("Nvidia Tegra T30L", - parse_proc_cpuinfo_hardware_tegra("avalon")); - EXPECT_EQ("Nvidia Tegra T30L", - parse_proc_cpuinfo_hardware_tegra("picasso_e2")); - EXPECT_EQ("Nvidia Tegra T30L", - parse_proc_cpuinfo_hardware_tegra("tostab12BL")); - EXPECT_EQ("Nvidia Tegra T30L", - parse_proc_cpuinfo_hardware_tegra("txs03")); - EXPECT_EQ("Nvidia Tegra T33", - parse_proc_cpuinfo_hardware_tegra("bobsleigh")); - EXPECT_EQ("Nvidia Tegra T33", - parse_proc_cpuinfo_hardware_tegra("enrc2b")); - EXPECT_EQ("Nvidia Tegra T33", - parse_proc_cpuinfo_hardware_tegra("evitareul")); - EXPECT_EQ("Nvidia Tegra T33", - parse_proc_cpuinfo_hardware_tegra("tegra_fjdev103")); - } +TEST(PROC_CPUINFO_HARDWARE, nvidia) { + EXPECT_EQ("Nvidia Tegra AP20H", parse_proc_cpuinfo_hardware_tegra("picasso")); + EXPECT_EQ("Nvidia Tegra AP20H", parse_proc_cpuinfo_hardware_tegra("picasso_e")); + EXPECT_EQ("Nvidia Tegra AP20H", parse_proc_cpuinfo_hardware_tegra("stingray")); + EXPECT_EQ("Nvidia Tegra AP33", parse_proc_cpuinfo_hardware_tegra("endeavoru")); + EXPECT_EQ("Nvidia Tegra AP33", parse_proc_cpuinfo_hardware_tegra("x3")); + EXPECT_EQ("Nvidia Tegra SL460N", parse_proc_cpuinfo_hardware_tegra("Ceres")); + EXPECT_EQ("Nvidia Tegra T114", parse_proc_cpuinfo_hardware_tegra("macallan")); + EXPECT_EQ("Nvidia Tegra T114", parse_proc_cpuinfo_hardware_tegra("mozart")); + EXPECT_EQ("Nvidia Tegra T114", parse_proc_cpuinfo_hardware_tegra("tostab12BA")); + EXPECT_EQ("Nvidia Tegra T124", parse_proc_cpuinfo_hardware_tegra("mocha")); + EXPECT_EQ("Nvidia Tegra T124", parse_proc_cpuinfo_hardware_tegra("tn8")); + EXPECT_EQ("Nvidia Tegra T20", parse_proc_cpuinfo_hardware_tegra("nbx03")); + EXPECT_EQ("Nvidia Tegra T20", parse_proc_cpuinfo_hardware_tegra("p3")); + EXPECT_EQ("Nvidia Tegra T20", parse_proc_cpuinfo_hardware_tegra("ventana")); + EXPECT_EQ("Nvidia Tegra T30", parse_proc_cpuinfo_hardware_tegra("cardhu")); + EXPECT_EQ("Nvidia Tegra T30", parse_proc_cpuinfo_hardware_tegra("chagall")); + EXPECT_EQ("Nvidia Tegra T30", parse_proc_cpuinfo_hardware_tegra("picasso_m")); + EXPECT_EQ("Nvidia Tegra T30", parse_proc_cpuinfo_hardware_tegra("picasso_mf")); + EXPECT_EQ("Nvidia Tegra T30L", parse_proc_cpuinfo_hardware_tegra("BIRCH")); + EXPECT_EQ("Nvidia Tegra T30L", parse_proc_cpuinfo_hardware_tegra("NS_14T004")); + EXPECT_EQ("Nvidia Tegra T30L", parse_proc_cpuinfo_hardware_tegra("avalon")); + EXPECT_EQ("Nvidia Tegra T30L", parse_proc_cpuinfo_hardware_tegra("picasso_e2")); + EXPECT_EQ("Nvidia Tegra T30L", parse_proc_cpuinfo_hardware_tegra("tostab12BL")); + EXPECT_EQ("Nvidia Tegra T30L", parse_proc_cpuinfo_hardware_tegra("txs03")); + EXPECT_EQ("Nvidia Tegra T33", parse_proc_cpuinfo_hardware_tegra("bobsleigh")); + EXPECT_EQ("Nvidia Tegra T33", parse_proc_cpuinfo_hardware_tegra("enrc2b")); + EXPECT_EQ("Nvidia Tegra T33", parse_proc_cpuinfo_hardware_tegra("evitareul")); + EXPECT_EQ("Nvidia Tegra T33", parse_proc_cpuinfo_hardware_tegra("tegra_fjdev103")); +} #endif /* CPUINFO_ARCH_ARM */ TEST(PROC_CPUINFO_HARDWARE, rockchip_rk) { - EXPECT_EQ("Rockchip RK3126", - parse_proc_cpuinfo_hardware("Rockchip RK3126")); - EXPECT_EQ("Rockchip RK3128", - parse_proc_cpuinfo_hardware("Rockchip RK3128")); - EXPECT_EQ("Rockchip RK3188", - parse_proc_cpuinfo_hardware("Rockchip RK3188")); - EXPECT_EQ("Rockchip RK3228H", - parse_proc_cpuinfo_hardware("rockchip,rk3228h")); - EXPECT_EQ("Rockchip RK3229", - parse_proc_cpuinfo_hardware("Rockchip RK3229")); - EXPECT_EQ("Rockchip RK3328", - parse_proc_cpuinfo_hardware("rockchip,rk3328")); - EXPECT_EQ("Rockchip RK3368", - parse_proc_cpuinfo_hardware("rockchip,rk3368")); + EXPECT_EQ("Rockchip RK3126", parse_proc_cpuinfo_hardware("Rockchip RK3126")); + EXPECT_EQ("Rockchip RK3128", parse_proc_cpuinfo_hardware("Rockchip RK3128")); + EXPECT_EQ("Rockchip RK3188", parse_proc_cpuinfo_hardware("Rockchip RK3188")); + EXPECT_EQ("Rockchip RK3228H", parse_proc_cpuinfo_hardware("rockchip,rk3228h")); + EXPECT_EQ("Rockchip RK3229", parse_proc_cpuinfo_hardware("Rockchip RK3229")); + EXPECT_EQ("Rockchip RK3328", parse_proc_cpuinfo_hardware("rockchip,rk3328")); + EXPECT_EQ("Rockchip RK3368", parse_proc_cpuinfo_hardware("rockchip,rk3368")); } TEST(PROC_CPUINFO_HARDWARE, spreadtrum_sc) { - EXPECT_EQ("Spreadtrum SC5735", - parse_proc_cpuinfo_hardware("sc5735")); - EXPECT_EQ("Spreadtrum SC6820I", - parse_proc_cpuinfo_hardware("sc6820i")); - EXPECT_EQ("Spreadtrum SC7715", - parse_proc_cpuinfo_hardware("scx15")); - EXPECT_EQ("Spreadtrum SC7730", - parse_proc_cpuinfo_hardware("sc7730")); - EXPECT_EQ("Spreadtrum SC7731", - parse_proc_cpuinfo_hardware("sc7731")); - EXPECT_EQ("Spreadtrum SC7731C", - parse_proc_cpuinfo_hardware("sc7731c")); - EXPECT_EQ("Spreadtrum SC7731G", - parse_proc_cpuinfo_hardware("sc7731g")); - EXPECT_EQ("Spreadtrum SC8825", - parse_proc_cpuinfo_hardware("sc8825")); - EXPECT_EQ("Spreadtrum SC8830", - parse_proc_cpuinfo_hardware("sc8830")); - EXPECT_EQ("Spreadtrum SC9830", - parse_proc_cpuinfo_hardware("sc9830")); - EXPECT_EQ("Spreadtrum SC9832", - parse_proc_cpuinfo_hardware("sc9832")); - EXPECT_EQ("Spreadtrum SC9832A", - parse_proc_cpuinfo_hardware("sc9832a")); + EXPECT_EQ("Spreadtrum SC5735", parse_proc_cpuinfo_hardware("sc5735")); + EXPECT_EQ("Spreadtrum SC6820I", parse_proc_cpuinfo_hardware("sc6820i")); + EXPECT_EQ("Spreadtrum SC7715", parse_proc_cpuinfo_hardware("scx15")); + EXPECT_EQ("Spreadtrum SC7730", parse_proc_cpuinfo_hardware("sc7730")); + EXPECT_EQ("Spreadtrum SC7731", parse_proc_cpuinfo_hardware("sc7731")); + EXPECT_EQ("Spreadtrum SC7731C", parse_proc_cpuinfo_hardware("sc7731c")); + EXPECT_EQ("Spreadtrum SC7731G", parse_proc_cpuinfo_hardware("sc7731g")); + EXPECT_EQ("Spreadtrum SC8825", parse_proc_cpuinfo_hardware("sc8825")); + EXPECT_EQ("Spreadtrum SC8830", parse_proc_cpuinfo_hardware("sc8830")); + EXPECT_EQ("Spreadtrum SC9830", parse_proc_cpuinfo_hardware("sc9830")); + EXPECT_EQ("Spreadtrum SC9832", parse_proc_cpuinfo_hardware("sc9832")); + EXPECT_EQ("Spreadtrum SC9832A", parse_proc_cpuinfo_hardware("sc9832a")); } TEST(PROC_CPUINFO_HARDWARE, telechips) { - EXPECT_EQ("Telechips TCC892X", - parse_proc_cpuinfo_hardware("tcc892x")); - EXPECT_EQ("Telechips TCC893X", - parse_proc_cpuinfo_hardware("tcc893x")); + EXPECT_EQ("Telechips TCC892X", parse_proc_cpuinfo_hardware("tcc892x")); + EXPECT_EQ("Telechips TCC893X", parse_proc_cpuinfo_hardware("tcc893x")); } #if CPUINFO_ARCH_ARM - TEST(PROC_CPUINFO_HARDWARE, texas_instruments_omap) { - EXPECT_EQ("Texas Instruments OMAP4430", - parse_proc_cpuinfo_hardware("OMAP4430")); - EXPECT_EQ("Texas Instruments OMAP4460", - parse_proc_cpuinfo_hardware("OMAP4460")); - } +TEST(PROC_CPUINFO_HARDWARE, texas_instruments_omap) { + EXPECT_EQ("Texas Instruments OMAP4430", parse_proc_cpuinfo_hardware("OMAP4430")); + EXPECT_EQ("Texas Instruments OMAP4460", parse_proc_cpuinfo_hardware("OMAP4460")); +} - TEST(PROC_CPUINFO_HARDWARE, texas_instruments_special) { - EXPECT_EQ("Texas Instruments OMAP4430", - parse_proc_cpuinfo_hardware("mapphone_CDMA")); - EXPECT_EQ("Texas Instruments OMAP4460", - parse_proc_cpuinfo_hardware("Tuna")); - } +TEST(PROC_CPUINFO_HARDWARE, texas_instruments_special) { + EXPECT_EQ("Texas Instruments OMAP4430", parse_proc_cpuinfo_hardware("mapphone_CDMA")); + EXPECT_EQ("Texas Instruments OMAP4460", parse_proc_cpuinfo_hardware("Tuna")); +} - TEST(PROC_CPUINFO_HARDWARE, wondermedia) { - EXPECT_EQ("WonderMedia WM8850", - parse_proc_cpuinfo_hardware("WMT", 1, 1200000)); - EXPECT_EQ("WonderMedia WM8880", - parse_proc_cpuinfo_hardware("WMT", 2, 1500000)); - EXPECT_EQ("WonderMedia WM8950", - parse_proc_cpuinfo_hardware("WMT", 1, 1008000)); - } +TEST(PROC_CPUINFO_HARDWARE, wondermedia) { + EXPECT_EQ("WonderMedia WM8850", parse_proc_cpuinfo_hardware("WMT", 1, 1200000)); + EXPECT_EQ("WonderMedia WM8880", parse_proc_cpuinfo_hardware("WMT", 2, 1500000)); + EXPECT_EQ("WonderMedia WM8950", parse_proc_cpuinfo_hardware("WMT", 1, 1008000)); +} #endif diff --git a/test/name/ro-arch.cc b/test/name/ro-arch.cc index af5746c2..f0f3e071 100644 --- a/test/name/ro-arch.cc +++ b/test/name/ro-arch.cc @@ -14,54 +14,32 @@ extern "C" void cpuinfo_arm_android_parse_ro_arch( uint32_t max_cpu_freq_max, char chipset_name[CPUINFO_ARM_CHIPSET_NAME_MAX]); -inline std::string parse_ro_arch( - std::string arch, uint32_t cores=1, uint32_t max_cpu_freq_max=0) -{ +inline std::string parse_ro_arch(std::string arch, uint32_t cores = 1, uint32_t max_cpu_freq_max = 0) { char arch_buffer[CPUINFO_BUILD_PROP_VALUE_MAX]; strncpy(arch_buffer, arch.c_str(), CPUINFO_BUILD_PROP_VALUE_MAX); char chipset_name[CPUINFO_ARM_CHIPSET_NAME_MAX]; - cpuinfo_arm_android_parse_ro_arch( - arch_buffer, cores, max_cpu_freq_max, chipset_name); + cpuinfo_arm_android_parse_ro_arch(arch_buffer, cores, max_cpu_freq_max, chipset_name); return std::string(chipset_name, strnlen(chipset_name, CPUINFO_ARM_CHIPSET_NAME_MAX)); } TEST(RO_ARCH, samsung_exynos) { - EXPECT_EQ("Samsung Exynos 3470", - parse_ro_arch("exynos3470")); - EXPECT_EQ("Samsung Exynos 3475", - parse_ro_arch("exynos3475")); - EXPECT_EQ("Samsung Exynos 4415", - parse_ro_arch("exynos4415")); - EXPECT_EQ("Samsung Exynos 5260", - parse_ro_arch("exynos5260")); - EXPECT_EQ("Samsung Exynos 5410", - parse_ro_arch("exynos5410")); - EXPECT_EQ("Samsung Exynos 5420", - parse_ro_arch("exynos5420", 4)); - EXPECT_EQ("Samsung Exynos 5422", - parse_ro_arch("exynos5422")); - EXPECT_EQ("Samsung Exynos 5430", - parse_ro_arch("exynos5430")); - EXPECT_EQ("Samsung Exynos 5433", - parse_ro_arch("exynos5433")); - EXPECT_EQ("Samsung Exynos 7420", - parse_ro_arch("exynos7420")); - EXPECT_EQ("Samsung Exynos 7570", - parse_ro_arch("exynos7570")); - EXPECT_EQ("Samsung Exynos 7580", - parse_ro_arch("exynos7580", 8)); - EXPECT_EQ("Samsung Exynos 7870", - parse_ro_arch("exynos7870")); - EXPECT_EQ("Samsung Exynos 7872", - parse_ro_arch("exynos7872")); - EXPECT_EQ("Samsung Exynos 7880", - parse_ro_arch("exynos7880")); - EXPECT_EQ("Samsung Exynos 7885", - parse_ro_arch("exynos7885")); - EXPECT_EQ("Samsung Exynos 8890", - parse_ro_arch("exynos8890")); - EXPECT_EQ("Samsung Exynos 8895", - parse_ro_arch("exynos8895")); - EXPECT_EQ("Samsung Exynos 9810", - parse_ro_arch("exynos9810")); + EXPECT_EQ("Samsung Exynos 3470", parse_ro_arch("exynos3470")); + EXPECT_EQ("Samsung Exynos 3475", parse_ro_arch("exynos3475")); + EXPECT_EQ("Samsung Exynos 4415", parse_ro_arch("exynos4415")); + EXPECT_EQ("Samsung Exynos 5260", parse_ro_arch("exynos5260")); + EXPECT_EQ("Samsung Exynos 5410", parse_ro_arch("exynos5410")); + EXPECT_EQ("Samsung Exynos 5420", parse_ro_arch("exynos5420", 4)); + EXPECT_EQ("Samsung Exynos 5422", parse_ro_arch("exynos5422")); + EXPECT_EQ("Samsung Exynos 5430", parse_ro_arch("exynos5430")); + EXPECT_EQ("Samsung Exynos 5433", parse_ro_arch("exynos5433")); + EXPECT_EQ("Samsung Exynos 7420", parse_ro_arch("exynos7420")); + EXPECT_EQ("Samsung Exynos 7570", parse_ro_arch("exynos7570")); + EXPECT_EQ("Samsung Exynos 7580", parse_ro_arch("exynos7580", 8)); + EXPECT_EQ("Samsung Exynos 7870", parse_ro_arch("exynos7870")); + EXPECT_EQ("Samsung Exynos 7872", parse_ro_arch("exynos7872")); + EXPECT_EQ("Samsung Exynos 7880", parse_ro_arch("exynos7880")); + EXPECT_EQ("Samsung Exynos 7885", parse_ro_arch("exynos7885")); + EXPECT_EQ("Samsung Exynos 8890", parse_ro_arch("exynos8890")); + EXPECT_EQ("Samsung Exynos 8895", parse_ro_arch("exynos8895")); + EXPECT_EQ("Samsung Exynos 9810", parse_ro_arch("exynos9810")); } diff --git a/test/name/ro-board-platform.cc b/test/name/ro-board-platform.cc index 51d73c3a..f9b5b28e 100644 --- a/test/name/ro-board-platform.cc +++ b/test/name/ro-board-platform.cc @@ -14,299 +14,182 @@ extern "C" void cpuinfo_arm_android_parse_ro_board_platform( uint32_t max_cpu_freq_max, char chipset_name[CPUINFO_ARM_CHIPSET_NAME_MAX]); -inline std::string parse_ro_board_platform( - std::string platform, uint32_t cores=1, uint32_t max_cpu_freq_max=0) -{ +inline std::string parse_ro_board_platform(std::string platform, uint32_t cores = 1, uint32_t max_cpu_freq_max = 0) { char platform_buffer[CPUINFO_BUILD_PROP_VALUE_MAX]; strncpy(platform_buffer, platform.c_str(), CPUINFO_BUILD_PROP_VALUE_MAX); char chipset_name[CPUINFO_ARM_CHIPSET_NAME_MAX]; - cpuinfo_arm_android_parse_ro_board_platform( - platform_buffer, cores, max_cpu_freq_max, chipset_name); + cpuinfo_arm_android_parse_ro_board_platform(platform_buffer, cores, max_cpu_freq_max, chipset_name); return std::string(chipset_name, strnlen(chipset_name, CPUINFO_ARM_CHIPSET_NAME_MAX)); } TEST(RO_BOARD_PLATFORM, qualcomm_msm) { - EXPECT_EQ("Qualcomm APQ8064", - parse_ro_board_platform("msm8960", 4)); - EXPECT_EQ("Qualcomm MSM7627A", - parse_ro_board_platform("msm7627a")); - EXPECT_EQ("Qualcomm MSM8084", - parse_ro_board_platform("msm8084")); - EXPECT_EQ("Qualcomm MSM8226", - parse_ro_board_platform("msm8226")); + EXPECT_EQ("Qualcomm APQ8064", parse_ro_board_platform("msm8960", 4)); + EXPECT_EQ("Qualcomm MSM7627A", parse_ro_board_platform("msm7627a")); + EXPECT_EQ("Qualcomm MSM8084", parse_ro_board_platform("msm8084")); + EXPECT_EQ("Qualcomm MSM8226", parse_ro_board_platform("msm8226")); #if CPUINFO_ARCH_ARM - EXPECT_EQ("Qualcomm MSM8610", - parse_ro_board_platform("msm8610", 2)); - EXPECT_EQ("Qualcomm MSM8612", - parse_ro_board_platform("msm8610", 4)); + EXPECT_EQ("Qualcomm MSM8610", parse_ro_board_platform("msm8610", 2)); + EXPECT_EQ("Qualcomm MSM8612", parse_ro_board_platform("msm8610", 4)); #endif /* CPUINFO_ARCH_ARM */ - EXPECT_EQ("Qualcomm MSM8612", - parse_ro_board_platform("MSM8612")); - EXPECT_EQ("Qualcomm MSM8660", - parse_ro_board_platform("msm8660")); - EXPECT_EQ("Qualcomm MSM8909", - parse_ro_board_platform("msm8909")); - EXPECT_EQ("Qualcomm MSM8916", - parse_ro_board_platform("msm8916", 4)); - EXPECT_EQ("Qualcomm MSM8917", - parse_ro_board_platform("msm8937", 4)); - EXPECT_EQ("Qualcomm MSM8937", - parse_ro_board_platform("msm8937", 8)); - EXPECT_EQ("Qualcomm MSM8939", - parse_ro_board_platform("msm8916", 8)); - EXPECT_EQ("Qualcomm MSM8952", - parse_ro_board_platform("msm8952")); - EXPECT_EQ("Qualcomm MSM8953", - parse_ro_board_platform("msm8953")); - EXPECT_EQ("Qualcomm MSM8960", - parse_ro_board_platform("msm8960", 2)); - EXPECT_EQ("Qualcomm MSM8974", - parse_ro_board_platform("msm8974")); - EXPECT_EQ("Qualcomm MSM8992", - parse_ro_board_platform("msm8992")); - EXPECT_EQ("Qualcomm MSM8994", - parse_ro_board_platform("msm8994")); - EXPECT_EQ("Qualcomm MSM8996", - parse_ro_board_platform("msm8996", 4)); - EXPECT_EQ("Qualcomm MSM8998", - parse_ro_board_platform("msm8998")); + EXPECT_EQ("Qualcomm MSM8612", parse_ro_board_platform("MSM8612")); + EXPECT_EQ("Qualcomm MSM8660", parse_ro_board_platform("msm8660")); + EXPECT_EQ("Qualcomm MSM8909", parse_ro_board_platform("msm8909")); + EXPECT_EQ("Qualcomm MSM8916", parse_ro_board_platform("msm8916", 4)); + EXPECT_EQ("Qualcomm MSM8917", parse_ro_board_platform("msm8937", 4)); + EXPECT_EQ("Qualcomm MSM8937", parse_ro_board_platform("msm8937", 8)); + EXPECT_EQ("Qualcomm MSM8939", parse_ro_board_platform("msm8916", 8)); + EXPECT_EQ("Qualcomm MSM8952", parse_ro_board_platform("msm8952")); + EXPECT_EQ("Qualcomm MSM8953", parse_ro_board_platform("msm8953")); + EXPECT_EQ("Qualcomm MSM8960", parse_ro_board_platform("msm8960", 2)); + EXPECT_EQ("Qualcomm MSM8974", parse_ro_board_platform("msm8974")); + EXPECT_EQ("Qualcomm MSM8992", parse_ro_board_platform("msm8992")); + EXPECT_EQ("Qualcomm MSM8994", parse_ro_board_platform("msm8994")); + EXPECT_EQ("Qualcomm MSM8996", parse_ro_board_platform("msm8996", 4)); + EXPECT_EQ("Qualcomm MSM8998", parse_ro_board_platform("msm8998")); } TEST(RO_BOARD_PLATFORM, qualcomm_apq) { - EXPECT_EQ("Qualcomm APQ8084", - parse_ro_board_platform("apq8084")); + EXPECT_EQ("Qualcomm APQ8084", parse_ro_board_platform("apq8084")); } TEST(RO_BOARD_PLATFORM, mediatek_mt) { - EXPECT_EQ("MediaTek MT5861", - parse_ro_board_platform("mt5861")); - EXPECT_EQ("MediaTek MT5882", - parse_ro_board_platform("mt5882")); - EXPECT_EQ("MediaTek MT6570", - parse_ro_board_platform("mt6570")); - EXPECT_EQ("MediaTek MT6572", - parse_ro_board_platform("mt6572")); - EXPECT_EQ("MediaTek MT6572A", - parse_ro_board_platform("MT6572A")); - EXPECT_EQ("MediaTek MT6575", - parse_ro_board_platform("mt6575")); - EXPECT_EQ("MediaTek MT6577", - parse_ro_board_platform("MT6577")); - EXPECT_EQ("MediaTek MT6577", - parse_ro_board_platform("mt6577")); - EXPECT_EQ("MediaTek MT6580", - parse_ro_board_platform("mt6580")); - EXPECT_EQ("MediaTek MT6582", - parse_ro_board_platform("MTK6582")); - EXPECT_EQ("MediaTek MT6582", - parse_ro_board_platform("mt6582")); - EXPECT_EQ("MediaTek MT6582M", - parse_ro_board_platform("MTK6582M")); - EXPECT_EQ("MediaTek MT6589", - parse_ro_board_platform("MT6589")); - EXPECT_EQ("MediaTek MT6589", - parse_ro_board_platform("MTK6589")); - EXPECT_EQ("MediaTek MT6592", - parse_ro_board_platform("mt6592")); - EXPECT_EQ("MediaTek MT6592T", - parse_ro_board_platform("MTK6592T")); - EXPECT_EQ("MediaTek MT6595", - parse_ro_board_platform("mt6595")); - EXPECT_EQ("MediaTek MT6732", - parse_ro_board_platform("mt6752", 4)); - EXPECT_EQ("MediaTek MT6735", - parse_ro_board_platform("mt6735")); - EXPECT_EQ("MediaTek MT6735M", - parse_ro_board_platform("mt6735m")); - EXPECT_EQ("MediaTek MT6737", - parse_ro_board_platform("mt6737")); - EXPECT_EQ("MediaTek MT6737M", - parse_ro_board_platform("mt6737m")); - EXPECT_EQ("MediaTek MT6737T", - parse_ro_board_platform("mt6737t")); - EXPECT_EQ("MediaTek MT6750", - parse_ro_board_platform("mt6750")); - EXPECT_EQ("MediaTek MT6752", - parse_ro_board_platform("mt6752", 8)); - EXPECT_EQ("MediaTek MT6753", - parse_ro_board_platform("mt6753")); - EXPECT_EQ("MediaTek MT6755", - parse_ro_board_platform("mt6755")); - EXPECT_EQ("MediaTek MT6757", - parse_ro_board_platform("mt6757")); - EXPECT_EQ("MediaTek MT6795", - parse_ro_board_platform("mt6795")); - EXPECT_EQ("MediaTek MT6797", - parse_ro_board_platform("mt6797")); - EXPECT_EQ("MediaTek MT8111", - parse_ro_board_platform("MT8111")); - EXPECT_EQ("MediaTek MT8127", - parse_ro_board_platform("MT8127")); - EXPECT_EQ("MediaTek MT8127", - parse_ro_board_platform("mt8127")); - EXPECT_EQ("MediaTek MT8135", - parse_ro_board_platform("mt8135")); - EXPECT_EQ("MediaTek MT8151", - parse_ro_board_platform("mt8151")); - EXPECT_EQ("MediaTek MT8163", - parse_ro_board_platform("mt8163")); - EXPECT_EQ("MediaTek MT8167", - parse_ro_board_platform("mt8167")); - EXPECT_EQ("MediaTek MT8173", - parse_ro_board_platform("mt8173")); - EXPECT_EQ("MediaTek MT8312", - parse_ro_board_platform("MT8312")); - EXPECT_EQ("MediaTek MT8382", - parse_ro_board_platform("MT8382")); - EXPECT_EQ("MediaTek MT8382V", - parse_ro_board_platform("MT8382V")); - EXPECT_EQ("MediaTek MT8392", - parse_ro_board_platform("MT8392")); + EXPECT_EQ("MediaTek MT5861", parse_ro_board_platform("mt5861")); + EXPECT_EQ("MediaTek MT5882", parse_ro_board_platform("mt5882")); + EXPECT_EQ("MediaTek MT6570", parse_ro_board_platform("mt6570")); + EXPECT_EQ("MediaTek MT6572", parse_ro_board_platform("mt6572")); + EXPECT_EQ("MediaTek MT6572A", parse_ro_board_platform("MT6572A")); + EXPECT_EQ("MediaTek MT6575", parse_ro_board_platform("mt6575")); + EXPECT_EQ("MediaTek MT6577", parse_ro_board_platform("MT6577")); + EXPECT_EQ("MediaTek MT6577", parse_ro_board_platform("mt6577")); + EXPECT_EQ("MediaTek MT6580", parse_ro_board_platform("mt6580")); + EXPECT_EQ("MediaTek MT6582", parse_ro_board_platform("MTK6582")); + EXPECT_EQ("MediaTek MT6582", parse_ro_board_platform("mt6582")); + EXPECT_EQ("MediaTek MT6582M", parse_ro_board_platform("MTK6582M")); + EXPECT_EQ("MediaTek MT6589", parse_ro_board_platform("MT6589")); + EXPECT_EQ("MediaTek MT6589", parse_ro_board_platform("MTK6589")); + EXPECT_EQ("MediaTek MT6592", parse_ro_board_platform("mt6592")); + EXPECT_EQ("MediaTek MT6592T", parse_ro_board_platform("MTK6592T")); + EXPECT_EQ("MediaTek MT6595", parse_ro_board_platform("mt6595")); + EXPECT_EQ("MediaTek MT6732", parse_ro_board_platform("mt6752", 4)); + EXPECT_EQ("MediaTek MT6735", parse_ro_board_platform("mt6735")); + EXPECT_EQ("MediaTek MT6735M", parse_ro_board_platform("mt6735m")); + EXPECT_EQ("MediaTek MT6737", parse_ro_board_platform("mt6737")); + EXPECT_EQ("MediaTek MT6737M", parse_ro_board_platform("mt6737m")); + EXPECT_EQ("MediaTek MT6737T", parse_ro_board_platform("mt6737t")); + EXPECT_EQ("MediaTek MT6750", parse_ro_board_platform("mt6750")); + EXPECT_EQ("MediaTek MT6752", parse_ro_board_platform("mt6752", 8)); + EXPECT_EQ("MediaTek MT6753", parse_ro_board_platform("mt6753")); + EXPECT_EQ("MediaTek MT6755", parse_ro_board_platform("mt6755")); + EXPECT_EQ("MediaTek MT6757", parse_ro_board_platform("mt6757")); + EXPECT_EQ("MediaTek MT6795", parse_ro_board_platform("mt6795")); + EXPECT_EQ("MediaTek MT6797", parse_ro_board_platform("mt6797")); + EXPECT_EQ("MediaTek MT8111", parse_ro_board_platform("MT8111")); + EXPECT_EQ("MediaTek MT8127", parse_ro_board_platform("MT8127")); + EXPECT_EQ("MediaTek MT8127", parse_ro_board_platform("mt8127")); + EXPECT_EQ("MediaTek MT8135", parse_ro_board_platform("mt8135")); + EXPECT_EQ("MediaTek MT8151", parse_ro_board_platform("mt8151")); + EXPECT_EQ("MediaTek MT8163", parse_ro_board_platform("mt8163")); + EXPECT_EQ("MediaTek MT8167", parse_ro_board_platform("mt8167")); + EXPECT_EQ("MediaTek MT8173", parse_ro_board_platform("mt8173")); + EXPECT_EQ("MediaTek MT8312", parse_ro_board_platform("MT8312")); + EXPECT_EQ("MediaTek MT8382", parse_ro_board_platform("MT8382")); + EXPECT_EQ("MediaTek MT8382V", parse_ro_board_platform("MT8382V")); + EXPECT_EQ("MediaTek MT8392", parse_ro_board_platform("MT8392")); } TEST(RO_BOARD_PLATFORM, samsung) { - EXPECT_EQ("Samsung Exynos 4412", - parse_ro_board_platform("exynos4412")); + EXPECT_EQ("Samsung Exynos 4412", parse_ro_board_platform("exynos4412")); } TEST(RO_BOARD_PLATFORM, hisilicon) { #if CPUINFO_ARCH_ARM - EXPECT_EQ("HiSilicon K3V2", - parse_ro_board_platform("k3v200")); - EXPECT_EQ("HiSilicon K3V2", - parse_ro_board_platform("k3v2oem1")); + EXPECT_EQ("HiSilicon K3V2", parse_ro_board_platform("k3v200")); + EXPECT_EQ("HiSilicon K3V2", parse_ro_board_platform("k3v2oem1")); #endif - EXPECT_EQ("HiSilicon Kirin 620", - parse_ro_board_platform("hi6210sft")); - EXPECT_EQ("HiSilicon Kirin 650", - parse_ro_board_platform("hi6250")); + EXPECT_EQ("HiSilicon Kirin 620", parse_ro_board_platform("hi6210sft")); + EXPECT_EQ("HiSilicon Kirin 650", parse_ro_board_platform("hi6250")); #if CPUINFO_ARCH_ARM - EXPECT_EQ("HiSilicon Kirin 910T", - parse_ro_board_platform("hi6620oem")); - EXPECT_EQ("HiSilicon Kirin 920", - parse_ro_board_platform("hi3630")); + EXPECT_EQ("HiSilicon Kirin 910T", parse_ro_board_platform("hi6620oem")); + EXPECT_EQ("HiSilicon Kirin 920", parse_ro_board_platform("hi3630")); #endif - EXPECT_EQ("HiSilicon Kirin 930", - parse_ro_board_platform("hi3635")); - EXPECT_EQ("HiSilicon Kirin 950", - parse_ro_board_platform("hi3650")); - EXPECT_EQ("HiSilicon Kirin 960", - parse_ro_board_platform("hi3660")); - EXPECT_EQ("HiSilicon Kirin 970", - parse_ro_board_platform("kirin970")); + EXPECT_EQ("HiSilicon Kirin 930", parse_ro_board_platform("hi3635")); + EXPECT_EQ("HiSilicon Kirin 950", parse_ro_board_platform("hi3650")); + EXPECT_EQ("HiSilicon Kirin 960", parse_ro_board_platform("hi3660")); + EXPECT_EQ("HiSilicon Kirin 970", parse_ro_board_platform("kirin970")); } TEST(RO_BOARD_PLATFORM, amlogic) { #if CPUINFO_ARCH_ARM - EXPECT_EQ("Amlogic AML8726-M", - parse_ro_board_platform("meson3")); - EXPECT_EQ("Amlogic AML8726-MX", - parse_ro_board_platform("meson6")); - EXPECT_EQ("Amlogic S805", - parse_ro_board_platform("meson8")); + EXPECT_EQ("Amlogic AML8726-M", parse_ro_board_platform("meson3")); + EXPECT_EQ("Amlogic AML8726-MX", parse_ro_board_platform("meson6")); + EXPECT_EQ("Amlogic S805", parse_ro_board_platform("meson8")); #endif /* CPUINFO_ARCH_ARM */ - EXPECT_EQ("Amlogic S905", - parse_ro_board_platform("gxbaby")); - EXPECT_EQ("Amlogic S905X", - parse_ro_board_platform("gxl")); - EXPECT_EQ("Amlogic S912", - parse_ro_board_platform("gxm")); + EXPECT_EQ("Amlogic S905", parse_ro_board_platform("gxbaby")); + EXPECT_EQ("Amlogic S905X", parse_ro_board_platform("gxl")); + EXPECT_EQ("Amlogic S912", parse_ro_board_platform("gxm")); } #if CPUINFO_ARCH_ARM - TEST(RO_BOARD_PLATFORM, broadcom) { - EXPECT_EQ("Broadcom BCM21654", - parse_ro_board_platform("rhea", 1, 849999)); - EXPECT_EQ("Broadcom BCM21654G", - parse_ro_board_platform("rhea", 1, 999999)); - EXPECT_EQ("Broadcom BCM21663", - parse_ro_board_platform("hawaii", 1, 999999)); - EXPECT_EQ("Broadcom BCM21664", - parse_ro_board_platform("hawaii", 2, 999999)); - EXPECT_EQ("Broadcom BCM21664T", - parse_ro_board_platform("hawaii", 2, 1200000)); - EXPECT_EQ("Broadcom BCM23550", - parse_ro_board_platform("java", 4, 1200000)); - EXPECT_EQ("Broadcom BCM28155", - parse_ro_board_platform("capri", 2, 1200000)); - EXPECT_EQ("Broadcom BCM28155", - parse_ro_board_platform("capri", 2, 1399999)); - } +TEST(RO_BOARD_PLATFORM, broadcom) { + EXPECT_EQ("Broadcom BCM21654", parse_ro_board_platform("rhea", 1, 849999)); + EXPECT_EQ("Broadcom BCM21654G", parse_ro_board_platform("rhea", 1, 999999)); + EXPECT_EQ("Broadcom BCM21663", parse_ro_board_platform("hawaii", 1, 999999)); + EXPECT_EQ("Broadcom BCM21664", parse_ro_board_platform("hawaii", 2, 999999)); + EXPECT_EQ("Broadcom BCM21664T", parse_ro_board_platform("hawaii", 2, 1200000)); + EXPECT_EQ("Broadcom BCM23550", parse_ro_board_platform("java", 4, 1200000)); + EXPECT_EQ("Broadcom BCM28155", parse_ro_board_platform("capri", 2, 1200000)); + EXPECT_EQ("Broadcom BCM28155", parse_ro_board_platform("capri", 2, 1399999)); +} - TEST(RO_BOARD_PLATFORM, leadcore) { - EXPECT_EQ("Leadcore LC1860", - parse_ro_board_platform("lc1860")); - } +TEST(RO_BOARD_PLATFORM, leadcore) { + EXPECT_EQ("Leadcore LC1860", parse_ro_board_platform("lc1860")); +} - TEST(RO_BOARD_PLATFORM, novathor) { - EXPECT_EQ("NovaThor U8500", - parse_ro_board_platform("montblanc")); - } +TEST(RO_BOARD_PLATFORM, novathor) { + EXPECT_EQ("NovaThor U8500", parse_ro_board_platform("montblanc")); +} #endif /* CPUINFO_ARCH_ARM */ TEST(RO_BOARD_PLATFORM, nvidia) { #if CPUINFO_ARCH_ARM - EXPECT_EQ("Nvidia Tegra T114", - parse_ro_board_platform("tegra4")); + EXPECT_EQ("Nvidia Tegra T114", parse_ro_board_platform("tegra4")); #endif /* CPUINFO_ARCH_ARM */ - EXPECT_EQ("Nvidia Tegra T132", - parse_ro_board_platform("tegra132")); - EXPECT_EQ("Nvidia Tegra T210", - parse_ro_board_platform("tegra210_dragon")); + EXPECT_EQ("Nvidia Tegra T132", parse_ro_board_platform("tegra132")); + EXPECT_EQ("Nvidia Tegra T210", parse_ro_board_platform("tegra210_dragon")); } TEST(RO_BOARD_PLATFORM, pinecone) { - EXPECT_EQ("Pinecone Surge S1", - parse_ro_board_platform("song")); + EXPECT_EQ("Pinecone Surge S1", parse_ro_board_platform("song")); } TEST(RO_BOARD_PLATFORM, rockchip_rk) { - EXPECT_EQ("Rockchip RK2928", - parse_ro_board_platform("rk2928")); - EXPECT_EQ("Rockchip RK3026", - parse_ro_board_platform("rk3026")); - EXPECT_EQ("Rockchip RK3066", - parse_ro_board_platform("rk3066")); - EXPECT_EQ("Rockchip RK3188", - parse_ro_board_platform("rk3188")); - EXPECT_EQ("Rockchip RK3228", - parse_ro_board_platform("rk3228")); + EXPECT_EQ("Rockchip RK2928", parse_ro_board_platform("rk2928")); + EXPECT_EQ("Rockchip RK3026", parse_ro_board_platform("rk3026")); + EXPECT_EQ("Rockchip RK3066", parse_ro_board_platform("rk3066")); + EXPECT_EQ("Rockchip RK3188", parse_ro_board_platform("rk3188")); + EXPECT_EQ("Rockchip RK3228", parse_ro_board_platform("rk3228")); #if CPUINFO_ARCH_ARM - EXPECT_EQ("Rockchip RK3229", - parse_ro_board_platform("rk322x")); + EXPECT_EQ("Rockchip RK3229", parse_ro_board_platform("rk322x")); #endif /* CPUINFO_ARCH_ARM */ - EXPECT_EQ("Rockchip RK3288", - parse_ro_board_platform("rk3288", 4)); - EXPECT_EQ("Rockchip RK3399", - parse_ro_board_platform("rk3288", 6)); - EXPECT_EQ("Rockchip RK3328", - parse_ro_board_platform("rk3328")); - EXPECT_EQ("Rockchip RK3368", - parse_ro_board_platform("rk3368")); - EXPECT_EQ("Rockchip RK3399", - parse_ro_board_platform("rk3399")); + EXPECT_EQ("Rockchip RK3288", parse_ro_board_platform("rk3288", 4)); + EXPECT_EQ("Rockchip RK3399", parse_ro_board_platform("rk3288", 6)); + EXPECT_EQ("Rockchip RK3328", parse_ro_board_platform("rk3328")); + EXPECT_EQ("Rockchip RK3368", parse_ro_board_platform("rk3368")); + EXPECT_EQ("Rockchip RK3399", parse_ro_board_platform("rk3399")); } TEST(RO_BOARD_PLATFORM, spreadtrum_sc) { - EXPECT_EQ("Spreadtrum SC6820I", - parse_ro_board_platform("sc6820i")); - EXPECT_EQ("Spreadtrum SC7731", - parse_ro_board_platform("SC7731")); - EXPECT_EQ("Spreadtrum SC7731", - parse_ro_board_platform("sc7731")); - EXPECT_EQ("Spreadtrum SC7731G", - parse_ro_board_platform("sc7731g")); - EXPECT_EQ("Spreadtrum SC8810", - parse_ro_board_platform("sc8810")); - EXPECT_EQ("Spreadtrum SC8825", - parse_ro_board_platform("sc8825")); - EXPECT_EQ("Spreadtrum SC8830", - parse_ro_board_platform("sc8830")); + EXPECT_EQ("Spreadtrum SC6820I", parse_ro_board_platform("sc6820i")); + EXPECT_EQ("Spreadtrum SC7731", parse_ro_board_platform("SC7731")); + EXPECT_EQ("Spreadtrum SC7731", parse_ro_board_platform("sc7731")); + EXPECT_EQ("Spreadtrum SC7731G", parse_ro_board_platform("sc7731g")); + EXPECT_EQ("Spreadtrum SC8810", parse_ro_board_platform("sc8810")); + EXPECT_EQ("Spreadtrum SC8825", parse_ro_board_platform("sc8825")); + EXPECT_EQ("Spreadtrum SC8830", parse_ro_board_platform("sc8830")); } #if CPUINFO_ARCH_ARM - TEST(RO_BOARD_PLATFORM, texas_instruments_omap) { - EXPECT_EQ("Texas Instruments OMAP4430", - parse_ro_board_platform("omap4", 2, 1008000)); - } +TEST(RO_BOARD_PLATFORM, texas_instruments_omap) { + EXPECT_EQ("Texas Instruments OMAP4430", parse_ro_board_platform("omap4", 2, 1008000)); +} #endif /* CPUINFO_ARCH_ARM */ diff --git a/test/name/ro-chipname.cc b/test/name/ro-chipname.cc index d1230eeb..3a4a121a 100644 --- a/test/name/ro-chipname.cc +++ b/test/name/ro-chipname.cc @@ -14,180 +14,105 @@ extern "C" void cpuinfo_arm_android_parse_ro_chipname( uint32_t max_cpu_freq_max, char chipset_name[CPUINFO_ARM_CHIPSET_NAME_MAX]); -inline std::string parse_ro_chipname( - std::string chipname, uint32_t cores=1, uint32_t max_cpu_freq_max=0) -{ +inline std::string parse_ro_chipname(std::string chipname, uint32_t cores = 1, uint32_t max_cpu_freq_max = 0) { char chipname_buffer[CPUINFO_BUILD_PROP_VALUE_MAX]; strncpy(chipname_buffer, chipname.c_str(), CPUINFO_BUILD_PROP_VALUE_MAX); char chipset_name[CPUINFO_ARM_CHIPSET_NAME_MAX]; - cpuinfo_arm_android_parse_ro_chipname( - chipname_buffer, cores, max_cpu_freq_max, chipset_name); + cpuinfo_arm_android_parse_ro_chipname(chipname_buffer, cores, max_cpu_freq_max, chipset_name); return std::string(chipset_name, strnlen(chipset_name, CPUINFO_ARM_CHIPSET_NAME_MAX)); } TEST(RO_CHIPNAME, qualcomm_msm) { - EXPECT_EQ("Qualcomm MSM7630", - parse_ro_chipname("MSM7630_SURF")); - EXPECT_EQ("Qualcomm MSM8210", - parse_ro_chipname("MSM8210")); - EXPECT_EQ("Qualcomm MSM8226", - parse_ro_chipname("MSM8226")); - EXPECT_EQ("Qualcomm MSM8228", - parse_ro_chipname("MSM8228")); - EXPECT_EQ("Qualcomm MSM8230AB", - parse_ro_chipname("MSM8230AB")); - EXPECT_EQ("Qualcomm MSM8230VV", - parse_ro_chipname("MSM8230VV")); - EXPECT_EQ("Qualcomm MSM8239", - parse_ro_chipname("MSM8239")); - EXPECT_EQ("Qualcomm MSM8260A", - parse_ro_chipname("MSM8260A")); - EXPECT_EQ("Qualcomm MSM8274", - parse_ro_chipname("MSM8274")); - EXPECT_EQ("Qualcomm MSM8610", - parse_ro_chipname("MSM8610", 2)); - EXPECT_EQ("Qualcomm MSM8626", - parse_ro_chipname("MSM8626")); - EXPECT_EQ("Qualcomm MSM8660", - parse_ro_chipname("MSM8660_SURF")); - EXPECT_EQ("Qualcomm MSM8674", - parse_ro_chipname("MSM8674")); - EXPECT_EQ("Qualcomm MSM8674PRO", - parse_ro_chipname("MSM8674PRO")); - EXPECT_EQ("Qualcomm MSM8916", - parse_ro_chipname("MSM8216")); - EXPECT_EQ("Qualcomm MSM8916", - parse_ro_chipname("MSM8916", 4)); - EXPECT_EQ("Qualcomm MSM8916", - parse_ro_chipname("msm8916", 4)); - EXPECT_EQ("Qualcomm MSM8917", - parse_ro_chipname("MSM8937", 4)); - EXPECT_EQ("Qualcomm MSM8926", - parse_ro_chipname("MSM8926")); - EXPECT_EQ("Qualcomm MSM8928", - parse_ro_chipname("MSM8928")); - EXPECT_EQ("Qualcomm MSM8929", - parse_ro_chipname("MSM8929")); - EXPECT_EQ("Qualcomm MSM8930", - parse_ro_chipname("MSM8930")); - EXPECT_EQ("Qualcomm MSM8930AB", - parse_ro_chipname("MSM8930AB")); - EXPECT_EQ("Qualcomm MSM8930VV", - parse_ro_chipname("MSM8930VV")); - EXPECT_EQ("Qualcomm MSM8939", - parse_ro_chipname("MSM8939")); - EXPECT_EQ("Qualcomm MSM8952", - parse_ro_chipname("MSM8952")); - EXPECT_EQ("Qualcomm MSM8953", - parse_ro_chipname("MSM8953")); - EXPECT_EQ("Qualcomm MSM8960", - parse_ro_chipname("MSM8960", 2)); - EXPECT_EQ("Qualcomm MSM8974", - parse_ro_chipname("MSM8974")); - EXPECT_EQ("Qualcomm MSM8974PRO", - parse_ro_chipname("MSM8974PRO")); - EXPECT_EQ("Qualcomm MSM8976", - parse_ro_chipname("MSM8976")); - EXPECT_EQ("Qualcomm MSM8996", - parse_ro_chipname("MSM8996", 4)); - EXPECT_EQ("Qualcomm MSM8998", - parse_ro_chipname("MSM8998")); + EXPECT_EQ("Qualcomm MSM7630", parse_ro_chipname("MSM7630_SURF")); + EXPECT_EQ("Qualcomm MSM8210", parse_ro_chipname("MSM8210")); + EXPECT_EQ("Qualcomm MSM8226", parse_ro_chipname("MSM8226")); + EXPECT_EQ("Qualcomm MSM8228", parse_ro_chipname("MSM8228")); + EXPECT_EQ("Qualcomm MSM8230AB", parse_ro_chipname("MSM8230AB")); + EXPECT_EQ("Qualcomm MSM8230VV", parse_ro_chipname("MSM8230VV")); + EXPECT_EQ("Qualcomm MSM8239", parse_ro_chipname("MSM8239")); + EXPECT_EQ("Qualcomm MSM8260A", parse_ro_chipname("MSM8260A")); + EXPECT_EQ("Qualcomm MSM8274", parse_ro_chipname("MSM8274")); + EXPECT_EQ("Qualcomm MSM8610", parse_ro_chipname("MSM8610", 2)); + EXPECT_EQ("Qualcomm MSM8626", parse_ro_chipname("MSM8626")); + EXPECT_EQ("Qualcomm MSM8660", parse_ro_chipname("MSM8660_SURF")); + EXPECT_EQ("Qualcomm MSM8674", parse_ro_chipname("MSM8674")); + EXPECT_EQ("Qualcomm MSM8674PRO", parse_ro_chipname("MSM8674PRO")); + EXPECT_EQ("Qualcomm MSM8916", parse_ro_chipname("MSM8216")); + EXPECT_EQ("Qualcomm MSM8916", parse_ro_chipname("MSM8916", 4)); + EXPECT_EQ("Qualcomm MSM8916", parse_ro_chipname("msm8916", 4)); + EXPECT_EQ("Qualcomm MSM8917", parse_ro_chipname("MSM8937", 4)); + EXPECT_EQ("Qualcomm MSM8926", parse_ro_chipname("MSM8926")); + EXPECT_EQ("Qualcomm MSM8928", parse_ro_chipname("MSM8928")); + EXPECT_EQ("Qualcomm MSM8929", parse_ro_chipname("MSM8929")); + EXPECT_EQ("Qualcomm MSM8930", parse_ro_chipname("MSM8930")); + EXPECT_EQ("Qualcomm MSM8930AB", parse_ro_chipname("MSM8930AB")); + EXPECT_EQ("Qualcomm MSM8930VV", parse_ro_chipname("MSM8930VV")); + EXPECT_EQ("Qualcomm MSM8939", parse_ro_chipname("MSM8939")); + EXPECT_EQ("Qualcomm MSM8952", parse_ro_chipname("MSM8952")); + EXPECT_EQ("Qualcomm MSM8953", parse_ro_chipname("MSM8953")); + EXPECT_EQ("Qualcomm MSM8960", parse_ro_chipname("MSM8960", 2)); + EXPECT_EQ("Qualcomm MSM8974", parse_ro_chipname("MSM8974")); + EXPECT_EQ("Qualcomm MSM8974PRO", parse_ro_chipname("MSM8974PRO")); + EXPECT_EQ("Qualcomm MSM8976", parse_ro_chipname("MSM8976")); + EXPECT_EQ("Qualcomm MSM8996", parse_ro_chipname("MSM8996", 4)); + EXPECT_EQ("Qualcomm MSM8998", parse_ro_chipname("MSM8998")); } TEST(RO_CHIPNAME, qualcomm_apq) { - EXPECT_EQ("Qualcomm APQ8016", - parse_ro_chipname("APQ8016")); - EXPECT_EQ("Qualcomm APQ8026", - parse_ro_chipname("APQ8026")); - EXPECT_EQ("Qualcomm APQ8064", - parse_ro_chipname("apq8064")); - EXPECT_EQ("Qualcomm APQ8074", - parse_ro_chipname("APQ8074")); - EXPECT_EQ("Qualcomm APQ8076", - parse_ro_chipname("APQ8076")); - EXPECT_EQ("Qualcomm APQ8084", - parse_ro_chipname("APQ8084")); + EXPECT_EQ("Qualcomm APQ8016", parse_ro_chipname("APQ8016")); + EXPECT_EQ("Qualcomm APQ8026", parse_ro_chipname("APQ8026")); + EXPECT_EQ("Qualcomm APQ8064", parse_ro_chipname("apq8064")); + EXPECT_EQ("Qualcomm APQ8074", parse_ro_chipname("APQ8074")); + EXPECT_EQ("Qualcomm APQ8076", parse_ro_chipname("APQ8076")); + EXPECT_EQ("Qualcomm APQ8084", parse_ro_chipname("APQ8084")); } TEST(RO_CHIPNAME, mediatek_mt) { - EXPECT_EQ("MediaTek MT6737T", - parse_ro_chipname("MT6737T")); - EXPECT_EQ("MediaTek MT6757", - parse_ro_chipname("MT6757")); + EXPECT_EQ("MediaTek MT6737T", parse_ro_chipname("MT6737T")); + EXPECT_EQ("MediaTek MT6757", parse_ro_chipname("MT6757")); } TEST(RO_CHIPNAME, samsung_exynos) { - EXPECT_EQ("Samsung Exynos 3470", - parse_ro_chipname("exynos3470")); - EXPECT_EQ("Samsung Exynos 3475", - parse_ro_chipname("exynos3475")); - EXPECT_EQ("Samsung Exynos 4415", - parse_ro_chipname("exynos4415")); - EXPECT_EQ("Samsung Exynos 5260", - parse_ro_chipname("exynos5260")); - EXPECT_EQ("Samsung Exynos 5410", - parse_ro_chipname("exynos5410")); - EXPECT_EQ("Samsung Exynos 5420", - parse_ro_chipname("exynos5420", 4)); - EXPECT_EQ("Samsung Exynos 5422", - parse_ro_chipname("exynos5422")); - EXPECT_EQ("Samsung Exynos 5430", - parse_ro_chipname("exynos5430")); - EXPECT_EQ("Samsung Exynos 5433", - parse_ro_chipname("exynos5433")); - EXPECT_EQ("Samsung Exynos 7420", - parse_ro_chipname("exynos7420")); - EXPECT_EQ("Samsung Exynos 7570", - parse_ro_chipname("exynos7570")); - EXPECT_EQ("Samsung Exynos 7578", - parse_ro_chipname("exynos7580", 4)); - EXPECT_EQ("Samsung Exynos 7580", - parse_ro_chipname("exynos7580", 8)); - EXPECT_EQ("Samsung Exynos 7870", - parse_ro_chipname("exynos7870")); - EXPECT_EQ("Samsung Exynos 7880", - parse_ro_chipname("exynos7880")); - EXPECT_EQ("Samsung Exynos 8890", - parse_ro_chipname("exynos8890")); - EXPECT_EQ("Samsung Exynos 8895", - parse_ro_chipname("exynos8895")); + EXPECT_EQ("Samsung Exynos 3470", parse_ro_chipname("exynos3470")); + EXPECT_EQ("Samsung Exynos 3475", parse_ro_chipname("exynos3475")); + EXPECT_EQ("Samsung Exynos 4415", parse_ro_chipname("exynos4415")); + EXPECT_EQ("Samsung Exynos 5260", parse_ro_chipname("exynos5260")); + EXPECT_EQ("Samsung Exynos 5410", parse_ro_chipname("exynos5410")); + EXPECT_EQ("Samsung Exynos 5420", parse_ro_chipname("exynos5420", 4)); + EXPECT_EQ("Samsung Exynos 5422", parse_ro_chipname("exynos5422")); + EXPECT_EQ("Samsung Exynos 5430", parse_ro_chipname("exynos5430")); + EXPECT_EQ("Samsung Exynos 5433", parse_ro_chipname("exynos5433")); + EXPECT_EQ("Samsung Exynos 7420", parse_ro_chipname("exynos7420")); + EXPECT_EQ("Samsung Exynos 7570", parse_ro_chipname("exynos7570")); + EXPECT_EQ("Samsung Exynos 7578", parse_ro_chipname("exynos7580", 4)); + EXPECT_EQ("Samsung Exynos 7580", parse_ro_chipname("exynos7580", 8)); + EXPECT_EQ("Samsung Exynos 7870", parse_ro_chipname("exynos7870")); + EXPECT_EQ("Samsung Exynos 7880", parse_ro_chipname("exynos7880")); + EXPECT_EQ("Samsung Exynos 8890", parse_ro_chipname("exynos8890")); + EXPECT_EQ("Samsung Exynos 8895", parse_ro_chipname("exynos8895")); } #if CPUINFO_ARCH_ARM - TEST(RO_CHIPNAME, marvell_pxa) { - EXPECT_EQ("Marvell PXA1088", - parse_ro_chipname("PXA1088")); - EXPECT_EQ("Marvell PXA986", - parse_ro_chipname("PXA986")); - } +TEST(RO_CHIPNAME, marvell_pxa) { + EXPECT_EQ("Marvell PXA1088", parse_ro_chipname("PXA1088")); + EXPECT_EQ("Marvell PXA986", parse_ro_chipname("PXA986")); +} - TEST(RO_CHIPNAME, renesas) { - EXPECT_EQ("Renesas MP5232", - parse_ro_chipname("mp523x")); - } +TEST(RO_CHIPNAME, renesas) { + EXPECT_EQ("Renesas MP5232", parse_ro_chipname("mp523x")); +} #endif /* CPUINFO_ARCH_ARM */ TEST(RO_CHIPNAME, spreadtrum) { - EXPECT_EQ("Spreadtrum SC6815AS", - parse_ro_chipname("SC6815AS")); - EXPECT_EQ("Spreadtrum SC7715A", - parse_ro_chipname("SC7715A")); - EXPECT_EQ("Spreadtrum SC7715T", - parse_ro_chipname("SC7715T")); - EXPECT_EQ("Spreadtrum SC7727S", - parse_ro_chipname("SC7727S")); - EXPECT_EQ("Spreadtrum SC7727S", - parse_ro_chipname("sc7727s")); - EXPECT_EQ("Spreadtrum SC7727SE", - parse_ro_chipname("SC7727SE")); - EXPECT_EQ("Spreadtrum SC7730S", - parse_ro_chipname("sc7730s")); - EXPECT_EQ("Spreadtrum SC7730SE", - parse_ro_chipname("SC7730SE")); - EXPECT_EQ("Spreadtrum SC7730SW", - parse_ro_chipname("SC7730SW")); - EXPECT_EQ("Spreadtrum SC7735S", - parse_ro_chipname("sc7735s")); - EXPECT_EQ("Spreadtrum SC9830I", - parse_ro_chipname("SC9830I")); + EXPECT_EQ("Spreadtrum SC6815AS", parse_ro_chipname("SC6815AS")); + EXPECT_EQ("Spreadtrum SC7715A", parse_ro_chipname("SC7715A")); + EXPECT_EQ("Spreadtrum SC7715T", parse_ro_chipname("SC7715T")); + EXPECT_EQ("Spreadtrum SC7727S", parse_ro_chipname("SC7727S")); + EXPECT_EQ("Spreadtrum SC7727S", parse_ro_chipname("sc7727s")); + EXPECT_EQ("Spreadtrum SC7727SE", parse_ro_chipname("SC7727SE")); + EXPECT_EQ("Spreadtrum SC7730S", parse_ro_chipname("sc7730s")); + EXPECT_EQ("Spreadtrum SC7730SE", parse_ro_chipname("SC7730SE")); + EXPECT_EQ("Spreadtrum SC7730SW", parse_ro_chipname("SC7730SW")); + EXPECT_EQ("Spreadtrum SC7735S", parse_ro_chipname("sc7735s")); + EXPECT_EQ("Spreadtrum SC9830I", parse_ro_chipname("SC9830I")); } diff --git a/test/name/ro-mediatek-platform.cc b/test/name/ro-mediatek-platform.cc index a89a1a6c..b3c985b0 100644 --- a/test/name/ro-mediatek-platform.cc +++ b/test/name/ro-mediatek-platform.cc @@ -14,14 +14,11 @@ extern "C" void cpuinfo_arm_android_parse_ro_mediatek_platform( uint32_t max_cpu_freq_max, char chipset_name[CPUINFO_ARM_CHIPSET_NAME_MAX]); -inline std::string parse_ro_mediatek_platform( - std::string platform, uint32_t cores=1, uint32_t max_cpu_freq_max=0) -{ +inline std::string parse_ro_mediatek_platform(std::string platform, uint32_t cores = 1, uint32_t max_cpu_freq_max = 0) { char platform_buffer[CPUINFO_BUILD_PROP_VALUE_MAX]; strncpy(platform_buffer, platform.c_str(), CPUINFO_BUILD_PROP_VALUE_MAX); char chipset_name[CPUINFO_ARM_CHIPSET_NAME_MAX]; - cpuinfo_arm_android_parse_ro_mediatek_platform( - platform_buffer, cores, max_cpu_freq_max, chipset_name); + cpuinfo_arm_android_parse_ro_mediatek_platform(platform_buffer, cores, max_cpu_freq_max, chipset_name); return std::string(chipset_name, strnlen(chipset_name, CPUINFO_ARM_CHIPSET_NAME_MAX)); } @@ -42,88 +39,46 @@ TEST(RO_MEDIATEK_PLATFORM, apple) { } TEST(RO_MEDIATEK_PLATFORM, mediatek_mt) { - EXPECT_EQ("MediaTek MT5861", - parse_ro_mediatek_platform("mt5861")); - EXPECT_EQ("MediaTek MT5882", - parse_ro_mediatek_platform("mt5882")); - EXPECT_EQ("MediaTek MT6570", - parse_ro_mediatek_platform("mt6570")); - EXPECT_EQ("MediaTek MT6572", - parse_ro_mediatek_platform("mt6572")); - EXPECT_EQ("MediaTek MT6572A", - parse_ro_mediatek_platform("MT6572A")); - EXPECT_EQ("MediaTek MT6575", - parse_ro_mediatek_platform("mt6575")); - EXPECT_EQ("MediaTek MT6577", - parse_ro_mediatek_platform("MT6577")); - EXPECT_EQ("MediaTek MT6577", - parse_ro_mediatek_platform("mt6577")); - EXPECT_EQ("MediaTek MT6580", - parse_ro_mediatek_platform("mt6580")); - EXPECT_EQ("MediaTek MT6582", - parse_ro_mediatek_platform("MTK6582")); - EXPECT_EQ("MediaTek MT6582", - parse_ro_mediatek_platform("mt6582")); - EXPECT_EQ("MediaTek MT6582M", - parse_ro_mediatek_platform("MTK6582M")); - EXPECT_EQ("MediaTek MT6589", - parse_ro_mediatek_platform("MT6589")); - EXPECT_EQ("MediaTek MT6589", - parse_ro_mediatek_platform("MTK6589")); - EXPECT_EQ("MediaTek MT6592", - parse_ro_mediatek_platform("mt6592")); - EXPECT_EQ("MediaTek MT6592T", - parse_ro_mediatek_platform("MTK6592T")); - EXPECT_EQ("MediaTek MT6595", - parse_ro_mediatek_platform("mt6595")); - EXPECT_EQ("MediaTek MT6732", - parse_ro_mediatek_platform("mt6752", 4)); - EXPECT_EQ("MediaTek MT6735", - parse_ro_mediatek_platform("mt6735")); - EXPECT_EQ("MediaTek MT6735M", - parse_ro_mediatek_platform("mt6735m")); - EXPECT_EQ("MediaTek MT6737", - parse_ro_mediatek_platform("mt6737")); - EXPECT_EQ("MediaTek MT6737M", - parse_ro_mediatek_platform("mt6737m")); - EXPECT_EQ("MediaTek MT6737T", - parse_ro_mediatek_platform("mt6737t")); - EXPECT_EQ("MediaTek MT6750", - parse_ro_mediatek_platform("mt6750")); - EXPECT_EQ("MediaTek MT6752", - parse_ro_mediatek_platform("mt6752", 8)); - EXPECT_EQ("MediaTek MT6753", - parse_ro_mediatek_platform("mt6753")); - EXPECT_EQ("MediaTek MT6755", - parse_ro_mediatek_platform("mt6755")); - EXPECT_EQ("MediaTek MT6757", - parse_ro_mediatek_platform("mt6757")); - EXPECT_EQ("MediaTek MT6795", - parse_ro_mediatek_platform("mt6795")); - EXPECT_EQ("MediaTek MT6797", - parse_ro_mediatek_platform("mt6797")); - EXPECT_EQ("MediaTek MT8111", - parse_ro_mediatek_platform("MT8111")); - EXPECT_EQ("MediaTek MT8127", - parse_ro_mediatek_platform("MT8127")); - EXPECT_EQ("MediaTek MT8127", - parse_ro_mediatek_platform("mt8127")); - EXPECT_EQ("MediaTek MT8135", - parse_ro_mediatek_platform("mt8135")); - EXPECT_EQ("MediaTek MT8151", - parse_ro_mediatek_platform("mt8151")); - EXPECT_EQ("MediaTek MT8163", - parse_ro_mediatek_platform("mt8163")); - EXPECT_EQ("MediaTek MT8167", - parse_ro_mediatek_platform("mt8167")); - EXPECT_EQ("MediaTek MT8173", - parse_ro_mediatek_platform("mt8173")); - EXPECT_EQ("MediaTek MT8312", - parse_ro_mediatek_platform("MT8312")); - EXPECT_EQ("MediaTek MT8382", - parse_ro_mediatek_platform("MT8382")); - EXPECT_EQ("MediaTek MT8382V", - parse_ro_mediatek_platform("MT8382V")); - EXPECT_EQ("MediaTek MT8392", - parse_ro_mediatek_platform("MT8392")); + EXPECT_EQ("MediaTek MT5861", parse_ro_mediatek_platform("mt5861")); + EXPECT_EQ("MediaTek MT5882", parse_ro_mediatek_platform("mt5882")); + EXPECT_EQ("MediaTek MT6570", parse_ro_mediatek_platform("mt6570")); + EXPECT_EQ("MediaTek MT6572", parse_ro_mediatek_platform("mt6572")); + EXPECT_EQ("MediaTek MT6572A", parse_ro_mediatek_platform("MT6572A")); + EXPECT_EQ("MediaTek MT6575", parse_ro_mediatek_platform("mt6575")); + EXPECT_EQ("MediaTek MT6577", parse_ro_mediatek_platform("MT6577")); + EXPECT_EQ("MediaTek MT6577", parse_ro_mediatek_platform("mt6577")); + EXPECT_EQ("MediaTek MT6580", parse_ro_mediatek_platform("mt6580")); + EXPECT_EQ("MediaTek MT6582", parse_ro_mediatek_platform("MTK6582")); + EXPECT_EQ("MediaTek MT6582", parse_ro_mediatek_platform("mt6582")); + EXPECT_EQ("MediaTek MT6582M", parse_ro_mediatek_platform("MTK6582M")); + EXPECT_EQ("MediaTek MT6589", parse_ro_mediatek_platform("MT6589")); + EXPECT_EQ("MediaTek MT6589", parse_ro_mediatek_platform("MTK6589")); + EXPECT_EQ("MediaTek MT6592", parse_ro_mediatek_platform("mt6592")); + EXPECT_EQ("MediaTek MT6592T", parse_ro_mediatek_platform("MTK6592T")); + EXPECT_EQ("MediaTek MT6595", parse_ro_mediatek_platform("mt6595")); + EXPECT_EQ("MediaTek MT6732", parse_ro_mediatek_platform("mt6752", 4)); + EXPECT_EQ("MediaTek MT6735", parse_ro_mediatek_platform("mt6735")); + EXPECT_EQ("MediaTek MT6735M", parse_ro_mediatek_platform("mt6735m")); + EXPECT_EQ("MediaTek MT6737", parse_ro_mediatek_platform("mt6737")); + EXPECT_EQ("MediaTek MT6737M", parse_ro_mediatek_platform("mt6737m")); + EXPECT_EQ("MediaTek MT6737T", parse_ro_mediatek_platform("mt6737t")); + EXPECT_EQ("MediaTek MT6750", parse_ro_mediatek_platform("mt6750")); + EXPECT_EQ("MediaTek MT6752", parse_ro_mediatek_platform("mt6752", 8)); + EXPECT_EQ("MediaTek MT6753", parse_ro_mediatek_platform("mt6753")); + EXPECT_EQ("MediaTek MT6755", parse_ro_mediatek_platform("mt6755")); + EXPECT_EQ("MediaTek MT6757", parse_ro_mediatek_platform("mt6757")); + EXPECT_EQ("MediaTek MT6795", parse_ro_mediatek_platform("mt6795")); + EXPECT_EQ("MediaTek MT6797", parse_ro_mediatek_platform("mt6797")); + EXPECT_EQ("MediaTek MT8111", parse_ro_mediatek_platform("MT8111")); + EXPECT_EQ("MediaTek MT8127", parse_ro_mediatek_platform("MT8127")); + EXPECT_EQ("MediaTek MT8127", parse_ro_mediatek_platform("mt8127")); + EXPECT_EQ("MediaTek MT8135", parse_ro_mediatek_platform("mt8135")); + EXPECT_EQ("MediaTek MT8151", parse_ro_mediatek_platform("mt8151")); + EXPECT_EQ("MediaTek MT8163", parse_ro_mediatek_platform("mt8163")); + EXPECT_EQ("MediaTek MT8167", parse_ro_mediatek_platform("mt8167")); + EXPECT_EQ("MediaTek MT8173", parse_ro_mediatek_platform("mt8173")); + EXPECT_EQ("MediaTek MT8312", parse_ro_mediatek_platform("MT8312")); + EXPECT_EQ("MediaTek MT8382", parse_ro_mediatek_platform("MT8382")); + EXPECT_EQ("MediaTek MT8382V", parse_ro_mediatek_platform("MT8382V")); + EXPECT_EQ("MediaTek MT8392", parse_ro_mediatek_platform("MT8392")); } diff --git a/test/name/ro-product-board.cc b/test/name/ro-product-board.cc index 48a2d72b..5a4cc7b2 100644 --- a/test/name/ro-product-board.cc +++ b/test/name/ro-product-board.cc @@ -14,467 +14,266 @@ extern "C" void cpuinfo_arm_android_parse_ro_product_board( uint32_t max_cpu_freq_max, char chipset_name[CPUINFO_ARM_CHIPSET_NAME_MAX]); -inline std::string parse_ro_product_board( - std::string board, uint32_t cores=1, uint32_t max_cpu_freq_max=0) -{ +inline std::string parse_ro_product_board(std::string board, uint32_t cores = 1, uint32_t max_cpu_freq_max = 0) { char board_buffer[CPUINFO_BUILD_PROP_VALUE_MAX]; strncpy(board_buffer, board.c_str(), CPUINFO_BUILD_PROP_VALUE_MAX); char chipset_name[CPUINFO_ARM_CHIPSET_NAME_MAX]; - cpuinfo_arm_android_parse_ro_product_board( - board_buffer, cores, max_cpu_freq_max, chipset_name); + cpuinfo_arm_android_parse_ro_product_board(board_buffer, cores, max_cpu_freq_max, chipset_name); return std::string(chipset_name, strnlen(chipset_name, CPUINFO_ARM_CHIPSET_NAME_MAX)); } TEST(RO_PRODUCT_BOARD, qualcomm_msm) { - EXPECT_EQ("Qualcomm APQ8064", - parse_ro_product_board("MSM8960", 4)); - EXPECT_EQ("Qualcomm MSM7630", - parse_ro_product_board("MSM7630_SURF")); - EXPECT_EQ("Qualcomm MSM8209", - parse_ro_product_board("MSM8209")); - EXPECT_EQ("Qualcomm MSM8210", - parse_ro_product_board("MSM8210")); - EXPECT_EQ("Qualcomm MSM8212", - parse_ro_product_board("MSM8212")); - EXPECT_EQ("Qualcomm MSM8225", - parse_ro_product_board("MSM8225")); - EXPECT_EQ("Qualcomm MSM8226", - parse_ro_product_board("MSM8226")); - EXPECT_EQ("Qualcomm MSM8227", - parse_ro_product_board("MSM8227")); - EXPECT_EQ("Qualcomm MSM8228", - parse_ro_product_board("MSM8228")); - EXPECT_EQ("Qualcomm MSM8230", - parse_ro_product_board("MSM8230")); - EXPECT_EQ("Qualcomm MSM8260A", - parse_ro_product_board("MSM8260A")); - EXPECT_EQ("Qualcomm MSM8274", - parse_ro_product_board("MSM8274")); + EXPECT_EQ("Qualcomm APQ8064", parse_ro_product_board("MSM8960", 4)); + EXPECT_EQ("Qualcomm MSM7630", parse_ro_product_board("MSM7630_SURF")); + EXPECT_EQ("Qualcomm MSM8209", parse_ro_product_board("MSM8209")); + EXPECT_EQ("Qualcomm MSM8210", parse_ro_product_board("MSM8210")); + EXPECT_EQ("Qualcomm MSM8212", parse_ro_product_board("MSM8212")); + EXPECT_EQ("Qualcomm MSM8225", parse_ro_product_board("MSM8225")); + EXPECT_EQ("Qualcomm MSM8226", parse_ro_product_board("MSM8226")); + EXPECT_EQ("Qualcomm MSM8227", parse_ro_product_board("MSM8227")); + EXPECT_EQ("Qualcomm MSM8228", parse_ro_product_board("MSM8228")); + EXPECT_EQ("Qualcomm MSM8230", parse_ro_product_board("MSM8230")); + EXPECT_EQ("Qualcomm MSM8260A", parse_ro_product_board("MSM8260A")); + EXPECT_EQ("Qualcomm MSM8274", parse_ro_product_board("MSM8274")); #if CPUINFO_ARCH_ARM - EXPECT_EQ("Qualcomm MSM8610", - parse_ro_product_board("MSM8610", 2)); - EXPECT_EQ("Qualcomm MSM8612", - parse_ro_product_board("MSM8610", 4)); + EXPECT_EQ("Qualcomm MSM8610", parse_ro_product_board("MSM8610", 2)); + EXPECT_EQ("Qualcomm MSM8612", parse_ro_product_board("MSM8610", 4)); #endif /* CPUINFO_ARCH_ARM */ - EXPECT_EQ("Qualcomm MSM8612", - parse_ro_product_board("MSM8612")); - EXPECT_EQ("Qualcomm MSM8625", - parse_ro_product_board("MSM8625")); - EXPECT_EQ("Qualcomm MSM8626", - parse_ro_product_board("MSM8626")); - EXPECT_EQ("Qualcomm MSM8660", - parse_ro_product_board("MSM8660_SURF")); - EXPECT_EQ("Qualcomm MSM8674", - parse_ro_product_board("MSM8674")); - EXPECT_EQ("Qualcomm MSM8909", - parse_ro_product_board("MSM8909")); - EXPECT_EQ("Qualcomm MSM8909", - parse_ro_product_board("msm8909")); - EXPECT_EQ("Qualcomm MSM8916", - parse_ro_product_board("MSM8216")); - EXPECT_EQ("Qualcomm MSM8916", - parse_ro_product_board("MSM8916", 4)); - EXPECT_EQ("Qualcomm MSM8916", - parse_ro_product_board("msm8916", 4)); - EXPECT_EQ("Qualcomm MSM8917", - parse_ro_product_board("MSM8917")); - EXPECT_EQ("Qualcomm MSM8917", - parse_ro_product_board("msm8937", 4)); - EXPECT_EQ("Qualcomm MSM8917", - parse_ro_product_board("msm8937_32", 4)); - EXPECT_EQ("Qualcomm MSM8926", - parse_ro_product_board("MSM8926")); - EXPECT_EQ("Qualcomm MSM8928", - parse_ro_product_board("MSM8928")); - EXPECT_EQ("Qualcomm MSM8929", - parse_ro_product_board("MSM8929")); - EXPECT_EQ("Qualcomm MSM8929", - parse_ro_product_board("msm8929")); - EXPECT_EQ("Qualcomm MSM8937", - parse_ro_product_board("MSM8937", 8)); - EXPECT_EQ("Qualcomm MSM8937", - parse_ro_product_board("msm8937", 8)); - EXPECT_EQ("Qualcomm MSM8937", - parse_ro_product_board("msm8937_32", 8)); - EXPECT_EQ("Qualcomm MSM8939", - parse_ro_product_board("MSM8916", 8)); - EXPECT_EQ("Qualcomm MSM8939", - parse_ro_product_board("MSM8939")); - EXPECT_EQ("Qualcomm MSM8939", - parse_ro_product_board("msm8916", 8)); - EXPECT_EQ("Qualcomm MSM8939", - parse_ro_product_board("msm8939")); - EXPECT_EQ("Qualcomm MSM8939", - parse_ro_product_board("msm8939_64")); - EXPECT_EQ("Qualcomm MSM8940", - parse_ro_product_board("MSM8940")); - EXPECT_EQ("Qualcomm MSM8952", - parse_ro_product_board("MSM8952")); - EXPECT_EQ("Qualcomm MSM8952", - parse_ro_product_board("msm8952")); - EXPECT_EQ("Qualcomm MSM8953", - parse_ro_product_board("msm8953")); - EXPECT_EQ("Qualcomm MSM8960", - parse_ro_product_board("MSM8960", 2)); - EXPECT_EQ("Qualcomm MSM8974", - parse_ro_product_board("MSM8974")); - EXPECT_EQ("Qualcomm MSM8974", - parse_ro_product_board("msm8974")); - EXPECT_EQ("Qualcomm MSM8976", - parse_ro_product_board("MSM8976")); - EXPECT_EQ("Qualcomm MSM8992", - parse_ro_product_board("MSM8992")); - EXPECT_EQ("Qualcomm MSM8992", - parse_ro_product_board("msm8992")); - EXPECT_EQ("Qualcomm MSM8994", - parse_ro_product_board("MSM8994")); - EXPECT_EQ("Qualcomm MSM8994", - parse_ro_product_board("msm8994")); - EXPECT_EQ("Qualcomm MSM8996", - parse_ro_product_board("msm8996", 4)); - EXPECT_EQ("Qualcomm MSM8998", - parse_ro_product_board("msm8998")); + EXPECT_EQ("Qualcomm MSM8612", parse_ro_product_board("MSM8612")); + EXPECT_EQ("Qualcomm MSM8625", parse_ro_product_board("MSM8625")); + EXPECT_EQ("Qualcomm MSM8626", parse_ro_product_board("MSM8626")); + EXPECT_EQ("Qualcomm MSM8660", parse_ro_product_board("MSM8660_SURF")); + EXPECT_EQ("Qualcomm MSM8674", parse_ro_product_board("MSM8674")); + EXPECT_EQ("Qualcomm MSM8909", parse_ro_product_board("MSM8909")); + EXPECT_EQ("Qualcomm MSM8909", parse_ro_product_board("msm8909")); + EXPECT_EQ("Qualcomm MSM8916", parse_ro_product_board("MSM8216")); + EXPECT_EQ("Qualcomm MSM8916", parse_ro_product_board("MSM8916", 4)); + EXPECT_EQ("Qualcomm MSM8916", parse_ro_product_board("msm8916", 4)); + EXPECT_EQ("Qualcomm MSM8917", parse_ro_product_board("MSM8917")); + EXPECT_EQ("Qualcomm MSM8917", parse_ro_product_board("msm8937", 4)); + EXPECT_EQ("Qualcomm MSM8917", parse_ro_product_board("msm8937_32", 4)); + EXPECT_EQ("Qualcomm MSM8926", parse_ro_product_board("MSM8926")); + EXPECT_EQ("Qualcomm MSM8928", parse_ro_product_board("MSM8928")); + EXPECT_EQ("Qualcomm MSM8929", parse_ro_product_board("MSM8929")); + EXPECT_EQ("Qualcomm MSM8929", parse_ro_product_board("msm8929")); + EXPECT_EQ("Qualcomm MSM8937", parse_ro_product_board("MSM8937", 8)); + EXPECT_EQ("Qualcomm MSM8937", parse_ro_product_board("msm8937", 8)); + EXPECT_EQ("Qualcomm MSM8937", parse_ro_product_board("msm8937_32", 8)); + EXPECT_EQ("Qualcomm MSM8939", parse_ro_product_board("MSM8916", 8)); + EXPECT_EQ("Qualcomm MSM8939", parse_ro_product_board("MSM8939")); + EXPECT_EQ("Qualcomm MSM8939", parse_ro_product_board("msm8916", 8)); + EXPECT_EQ("Qualcomm MSM8939", parse_ro_product_board("msm8939")); + EXPECT_EQ("Qualcomm MSM8939", parse_ro_product_board("msm8939_64")); + EXPECT_EQ("Qualcomm MSM8940", parse_ro_product_board("MSM8940")); + EXPECT_EQ("Qualcomm MSM8952", parse_ro_product_board("MSM8952")); + EXPECT_EQ("Qualcomm MSM8952", parse_ro_product_board("msm8952")); + EXPECT_EQ("Qualcomm MSM8953", parse_ro_product_board("msm8953")); + EXPECT_EQ("Qualcomm MSM8960", parse_ro_product_board("MSM8960", 2)); + EXPECT_EQ("Qualcomm MSM8974", parse_ro_product_board("MSM8974")); + EXPECT_EQ("Qualcomm MSM8974", parse_ro_product_board("msm8974")); + EXPECT_EQ("Qualcomm MSM8976", parse_ro_product_board("MSM8976")); + EXPECT_EQ("Qualcomm MSM8992", parse_ro_product_board("MSM8992")); + EXPECT_EQ("Qualcomm MSM8992", parse_ro_product_board("msm8992")); + EXPECT_EQ("Qualcomm MSM8994", parse_ro_product_board("MSM8994")); + EXPECT_EQ("Qualcomm MSM8994", parse_ro_product_board("msm8994")); + EXPECT_EQ("Qualcomm MSM8996", parse_ro_product_board("msm8996", 4)); + EXPECT_EQ("Qualcomm MSM8998", parse_ro_product_board("msm8998")); } TEST(RO_PRODUCT_BOARD, qualcomm_apq) { - EXPECT_EQ("Qualcomm APQ8064", - parse_ro_product_board("APQ8064")); - EXPECT_EQ("Qualcomm APQ8064A", - parse_ro_product_board("APQ8064A")); - EXPECT_EQ("Qualcomm APQ8064PRO", - parse_ro_product_board("APQ8064Pro")); - EXPECT_EQ("Qualcomm APQ8084", - parse_ro_product_board("APQ8084")); + EXPECT_EQ("Qualcomm APQ8064", parse_ro_product_board("APQ8064")); + EXPECT_EQ("Qualcomm APQ8064A", parse_ro_product_board("APQ8064A")); + EXPECT_EQ("Qualcomm APQ8064PRO", parse_ro_product_board("APQ8064Pro")); + EXPECT_EQ("Qualcomm APQ8084", parse_ro_product_board("APQ8084")); } TEST(RO_PRODUCT_BOARD, qualcomm_special) { - EXPECT_EQ("Qualcomm MSM8996PRO-AB", - parse_ro_product_board("marlin")); - EXPECT_EQ("Qualcomm MSM8996PRO-AB", - parse_ro_product_board("sailfish")); + EXPECT_EQ("Qualcomm MSM8996PRO-AB", parse_ro_product_board("marlin")); + EXPECT_EQ("Qualcomm MSM8996PRO-AB", parse_ro_product_board("sailfish")); } TEST(RO_PRODUCT_BOARD, mediatek_mt) { - EXPECT_EQ("MediaTek MT5861", - parse_ro_product_board("mt5861")); - EXPECT_EQ("MediaTek MT5882", - parse_ro_product_board("mt5882")); - EXPECT_EQ("MediaTek MT6572", - parse_ro_product_board("mt6572")); - EXPECT_EQ("MediaTek MT6572M", - parse_ro_product_board("MT6572M")); - EXPECT_EQ("MediaTek MT6575", - parse_ro_product_board("MTK6575")); - EXPECT_EQ("MediaTek MT6575", - parse_ro_product_board("mt6575")); - EXPECT_EQ("MediaTek MT6577", - parse_ro_product_board("MTK6577")); - EXPECT_EQ("MediaTek MT6577", - parse_ro_product_board("mt6577")); - EXPECT_EQ("MediaTek MT6580", - parse_ro_product_board("MT6580")); - EXPECT_EQ("MediaTek MT6580", - parse_ro_product_board("mt6580")); - EXPECT_EQ("MediaTek MT6580A", - parse_ro_product_board("MT6580A")); - EXPECT_EQ("MediaTek MT6580M", - parse_ro_product_board("MT6580M")); - EXPECT_EQ("MediaTek MT6582", - parse_ro_product_board("MT6582")); - EXPECT_EQ("MediaTek MT6582", - parse_ro_product_board("mt6582")); - EXPECT_EQ("MediaTek MT6582M", - parse_ro_product_board("MTK6582M")); - EXPECT_EQ("MediaTek MT6582V", - parse_ro_product_board("MT6582V")); - EXPECT_EQ("MediaTek MT6582W", - parse_ro_product_board("MT6582W")); - EXPECT_EQ("MediaTek MT6589", - parse_ro_product_board("MT6589")); - EXPECT_EQ("MediaTek MT6589T", - parse_ro_product_board("MT6589T")); - EXPECT_EQ("MediaTek MT6592", - parse_ro_product_board("MT6592")); - EXPECT_EQ("MediaTek MT6592", - parse_ro_product_board("mt6592")); - EXPECT_EQ("MediaTek MT6592M", - parse_ro_product_board("MT6592M")); - EXPECT_EQ("MediaTek MT6595", - parse_ro_product_board("MT6595")); - EXPECT_EQ("MediaTek MT6732", - parse_ro_product_board("MT6732")); - EXPECT_EQ("MediaTek MT6735", - parse_ro_product_board("MT6735")); - EXPECT_EQ("MediaTek MT6735", - parse_ro_product_board("mt6735")); - EXPECT_EQ("MediaTek MT6735M", - parse_ro_product_board("MT6735M")); - EXPECT_EQ("MediaTek MT6735M", - parse_ro_product_board("mt6735m")); - EXPECT_EQ("MediaTek MT6735P", - parse_ro_product_board("MT6735P")); - EXPECT_EQ("MediaTek MT6735V", - parse_ro_product_board("MT6735V")); - EXPECT_EQ("MediaTek MT6737", - parse_ro_product_board("MT6737")); - EXPECT_EQ("MediaTek MT6737M", - parse_ro_product_board("mt6737m")); - EXPECT_EQ("MediaTek MT6737T", - parse_ro_product_board("MT6737T")); - EXPECT_EQ("MediaTek MT6750", - parse_ro_product_board("MT6750")); - EXPECT_EQ("MediaTek MT6750", - parse_ro_product_board("mt6750")); - EXPECT_EQ("MediaTek MT6752", - parse_ro_product_board("MT6752", 8)); - EXPECT_EQ("MediaTek MT6753", - parse_ro_product_board("MT6753")); - EXPECT_EQ("MediaTek MT6753", - parse_ro_product_board("mt6753")); - EXPECT_EQ("MediaTek MT6755", - parse_ro_product_board("mt6755")); - EXPECT_EQ("MediaTek MT6755M", - parse_ro_product_board("MT6755M")); - EXPECT_EQ("MediaTek MT6757", - parse_ro_product_board("MT6757")); - EXPECT_EQ("MediaTek MT6795", - parse_ro_product_board("mt6795")); - EXPECT_EQ("MediaTek MT6797", - parse_ro_product_board("MT6797")); - EXPECT_EQ("MediaTek MT8127", - parse_ro_product_board("mt8127")); - EXPECT_EQ("MediaTek MT8151", - parse_ro_product_board("mt8151")); - EXPECT_EQ("MediaTek MT8163", - parse_ro_product_board("mt8163")); - EXPECT_EQ("MediaTek MT8312", - parse_ro_product_board("MT8312")); - EXPECT_EQ("MediaTek MT8321", - parse_ro_product_board("MT8321")); - EXPECT_EQ("MediaTek MT8382", - parse_ro_product_board("MT8382")); - EXPECT_EQ("MediaTek MT8382V", - parse_ro_product_board("MT8382V")); - EXPECT_EQ("MediaTek MT8389", - parse_ro_product_board("MT8389")); - EXPECT_EQ("MediaTek MT8735M", - parse_ro_product_board("MT8735m")); - EXPECT_EQ("MediaTek MT8735P", - parse_ro_product_board("MT8735P")); - EXPECT_EQ("MediaTek MT8783", - parse_ro_product_board("MT8783")); + EXPECT_EQ("MediaTek MT5861", parse_ro_product_board("mt5861")); + EXPECT_EQ("MediaTek MT5882", parse_ro_product_board("mt5882")); + EXPECT_EQ("MediaTek MT6572", parse_ro_product_board("mt6572")); + EXPECT_EQ("MediaTek MT6572M", parse_ro_product_board("MT6572M")); + EXPECT_EQ("MediaTek MT6575", parse_ro_product_board("MTK6575")); + EXPECT_EQ("MediaTek MT6575", parse_ro_product_board("mt6575")); + EXPECT_EQ("MediaTek MT6577", parse_ro_product_board("MTK6577")); + EXPECT_EQ("MediaTek MT6577", parse_ro_product_board("mt6577")); + EXPECT_EQ("MediaTek MT6580", parse_ro_product_board("MT6580")); + EXPECT_EQ("MediaTek MT6580", parse_ro_product_board("mt6580")); + EXPECT_EQ("MediaTek MT6580A", parse_ro_product_board("MT6580A")); + EXPECT_EQ("MediaTek MT6580M", parse_ro_product_board("MT6580M")); + EXPECT_EQ("MediaTek MT6582", parse_ro_product_board("MT6582")); + EXPECT_EQ("MediaTek MT6582", parse_ro_product_board("mt6582")); + EXPECT_EQ("MediaTek MT6582M", parse_ro_product_board("MTK6582M")); + EXPECT_EQ("MediaTek MT6582V", parse_ro_product_board("MT6582V")); + EXPECT_EQ("MediaTek MT6582W", parse_ro_product_board("MT6582W")); + EXPECT_EQ("MediaTek MT6589", parse_ro_product_board("MT6589")); + EXPECT_EQ("MediaTek MT6589T", parse_ro_product_board("MT6589T")); + EXPECT_EQ("MediaTek MT6592", parse_ro_product_board("MT6592")); + EXPECT_EQ("MediaTek MT6592", parse_ro_product_board("mt6592")); + EXPECT_EQ("MediaTek MT6592M", parse_ro_product_board("MT6592M")); + EXPECT_EQ("MediaTek MT6595", parse_ro_product_board("MT6595")); + EXPECT_EQ("MediaTek MT6732", parse_ro_product_board("MT6732")); + EXPECT_EQ("MediaTek MT6735", parse_ro_product_board("MT6735")); + EXPECT_EQ("MediaTek MT6735", parse_ro_product_board("mt6735")); + EXPECT_EQ("MediaTek MT6735M", parse_ro_product_board("MT6735M")); + EXPECT_EQ("MediaTek MT6735M", parse_ro_product_board("mt6735m")); + EXPECT_EQ("MediaTek MT6735P", parse_ro_product_board("MT6735P")); + EXPECT_EQ("MediaTek MT6735V", parse_ro_product_board("MT6735V")); + EXPECT_EQ("MediaTek MT6737", parse_ro_product_board("MT6737")); + EXPECT_EQ("MediaTek MT6737M", parse_ro_product_board("mt6737m")); + EXPECT_EQ("MediaTek MT6737T", parse_ro_product_board("MT6737T")); + EXPECT_EQ("MediaTek MT6750", parse_ro_product_board("MT6750")); + EXPECT_EQ("MediaTek MT6750", parse_ro_product_board("mt6750")); + EXPECT_EQ("MediaTek MT6752", parse_ro_product_board("MT6752", 8)); + EXPECT_EQ("MediaTek MT6753", parse_ro_product_board("MT6753")); + EXPECT_EQ("MediaTek MT6753", parse_ro_product_board("mt6753")); + EXPECT_EQ("MediaTek MT6755", parse_ro_product_board("mt6755")); + EXPECT_EQ("MediaTek MT6755M", parse_ro_product_board("MT6755M")); + EXPECT_EQ("MediaTek MT6757", parse_ro_product_board("MT6757")); + EXPECT_EQ("MediaTek MT6795", parse_ro_product_board("mt6795")); + EXPECT_EQ("MediaTek MT6797", parse_ro_product_board("MT6797")); + EXPECT_EQ("MediaTek MT8127", parse_ro_product_board("mt8127")); + EXPECT_EQ("MediaTek MT8151", parse_ro_product_board("mt8151")); + EXPECT_EQ("MediaTek MT8163", parse_ro_product_board("mt8163")); + EXPECT_EQ("MediaTek MT8312", parse_ro_product_board("MT8312")); + EXPECT_EQ("MediaTek MT8321", parse_ro_product_board("MT8321")); + EXPECT_EQ("MediaTek MT8382", parse_ro_product_board("MT8382")); + EXPECT_EQ("MediaTek MT8382V", parse_ro_product_board("MT8382V")); + EXPECT_EQ("MediaTek MT8389", parse_ro_product_board("MT8389")); + EXPECT_EQ("MediaTek MT8735M", parse_ro_product_board("MT8735m")); + EXPECT_EQ("MediaTek MT8735P", parse_ro_product_board("MT8735P")); + EXPECT_EQ("MediaTek MT8783", parse_ro_product_board("MT8783")); } TEST(RO_PRODUCT_BOARD, samsung_universal) { - EXPECT_EQ("Samsung Exynos 3470", - parse_ro_product_board("universal3470")); - EXPECT_EQ("Samsung Exynos 3475", - parse_ro_product_board("universal3475")); - EXPECT_EQ("Samsung Exynos 4415", - parse_ro_product_board("universal4415")); - EXPECT_EQ("Samsung Exynos 5260", - parse_ro_product_board("universal5260")); - EXPECT_EQ("Samsung Exynos 5410", - parse_ro_product_board("universal5410")); - EXPECT_EQ("Samsung Exynos 5420", - parse_ro_product_board("universal5420", 4)); - EXPECT_EQ("Samsung Exynos 5422", - parse_ro_product_board("universal5422")); - EXPECT_EQ("Samsung Exynos 5430", - parse_ro_product_board("universal5430")); - EXPECT_EQ("Samsung Exynos 5433", - parse_ro_product_board("universal5433")); - EXPECT_EQ("Samsung Exynos 7420", - parse_ro_product_board("universal7420")); - EXPECT_EQ("Samsung Exynos 7570", - parse_ro_product_board("universal7570")); - EXPECT_EQ("Samsung Exynos 7578", - parse_ro_product_board("universal7580", 4)); - EXPECT_EQ("Samsung Exynos 7580", - parse_ro_product_board("universal7580", 8)); - EXPECT_EQ("Samsung Exynos 7870", - parse_ro_product_board("universal7870")); - EXPECT_EQ("Samsung Exynos 7880", - parse_ro_product_board("universal7880")); - EXPECT_EQ("Samsung Exynos 8890", - parse_ro_product_board("universal8890")); - EXPECT_EQ("Samsung Exynos 8895", - parse_ro_product_board("universal8895")); + EXPECT_EQ("Samsung Exynos 3470", parse_ro_product_board("universal3470")); + EXPECT_EQ("Samsung Exynos 3475", parse_ro_product_board("universal3475")); + EXPECT_EQ("Samsung Exynos 4415", parse_ro_product_board("universal4415")); + EXPECT_EQ("Samsung Exynos 5260", parse_ro_product_board("universal5260")); + EXPECT_EQ("Samsung Exynos 5410", parse_ro_product_board("universal5410")); + EXPECT_EQ("Samsung Exynos 5420", parse_ro_product_board("universal5420", 4)); + EXPECT_EQ("Samsung Exynos 5422", parse_ro_product_board("universal5422")); + EXPECT_EQ("Samsung Exynos 5430", parse_ro_product_board("universal5430")); + EXPECT_EQ("Samsung Exynos 5433", parse_ro_product_board("universal5433")); + EXPECT_EQ("Samsung Exynos 7420", parse_ro_product_board("universal7420")); + EXPECT_EQ("Samsung Exynos 7570", parse_ro_product_board("universal7570")); + EXPECT_EQ("Samsung Exynos 7578", parse_ro_product_board("universal7580", 4)); + EXPECT_EQ("Samsung Exynos 7580", parse_ro_product_board("universal7580", 8)); + EXPECT_EQ("Samsung Exynos 7870", parse_ro_product_board("universal7870")); + EXPECT_EQ("Samsung Exynos 7880", parse_ro_product_board("universal7880")); + EXPECT_EQ("Samsung Exynos 8890", parse_ro_product_board("universal8890")); + EXPECT_EQ("Samsung Exynos 8895", parse_ro_product_board("universal8895")); } #if CPUINFO_ARCH_ARM - TEST(RO_PRODUCT_BOARD, samsung_smdk) { - EXPECT_EQ("Samsung Exynos 4212", - parse_ro_product_board("smdk4x12", 2)); - EXPECT_EQ("Samsung Exynos 4412", - parse_ro_product_board("smdk4x12", 4)); - } +TEST(RO_PRODUCT_BOARD, samsung_smdk) { + EXPECT_EQ("Samsung Exynos 4212", parse_ro_product_board("smdk4x12", 2)); + EXPECT_EQ("Samsung Exynos 4412", parse_ro_product_board("smdk4x12", 4)); +} #endif TEST(RO_PRODUCT_BOARD, hisilicon_huawei) { - EXPECT_EQ("HiSilicon Kirin 659", - parse_ro_product_board("BAC")); - EXPECT_EQ("HiSilicon Kirin 950", - parse_ro_product_board("FRD")); - EXPECT_EQ("HiSilicon Kirin 950", - parse_ro_product_board("FRD-L09")); - EXPECT_EQ("HiSilicon Kirin 950", - parse_ro_product_board("NXT")); - EXPECT_EQ("HiSilicon Kirin 950", - parse_ro_product_board("NXT-AL10")); - EXPECT_EQ("HiSilicon Kirin 950", - parse_ro_product_board("NXT-L09")); - EXPECT_EQ("HiSilicon Kirin 950", - parse_ro_product_board("NXT-L29")); - EXPECT_EQ("HiSilicon Kirin 955", - parse_ro_product_board("EVA")); - EXPECT_EQ("HiSilicon Kirin 955", - parse_ro_product_board("EVA-AL10")); - EXPECT_EQ("HiSilicon Kirin 955", - parse_ro_product_board("EVA-L09")); - EXPECT_EQ("HiSilicon Kirin 955", - parse_ro_product_board("EVA-L19")); - EXPECT_EQ("HiSilicon Kirin 955", - parse_ro_product_board("VIE-L09")); - EXPECT_EQ("HiSilicon Kirin 955", - parse_ro_product_board("VIE-L29")); - EXPECT_EQ("HiSilicon Kirin 960", - parse_ro_product_board("DUK")); - EXPECT_EQ("HiSilicon Kirin 960", - parse_ro_product_board("LON")); - EXPECT_EQ("HiSilicon Kirin 960", - parse_ro_product_board("MHA")); - EXPECT_EQ("HiSilicon Kirin 960", - parse_ro_product_board("STF")); - EXPECT_EQ("HiSilicon Kirin 960", - parse_ro_product_board("VKY")); - EXPECT_EQ("HiSilicon Kirin 960", - parse_ro_product_board("VTR")); + EXPECT_EQ("HiSilicon Kirin 659", parse_ro_product_board("BAC")); + EXPECT_EQ("HiSilicon Kirin 950", parse_ro_product_board("FRD")); + EXPECT_EQ("HiSilicon Kirin 950", parse_ro_product_board("FRD-L09")); + EXPECT_EQ("HiSilicon Kirin 950", parse_ro_product_board("NXT")); + EXPECT_EQ("HiSilicon Kirin 950", parse_ro_product_board("NXT-AL10")); + EXPECT_EQ("HiSilicon Kirin 950", parse_ro_product_board("NXT-L09")); + EXPECT_EQ("HiSilicon Kirin 950", parse_ro_product_board("NXT-L29")); + EXPECT_EQ("HiSilicon Kirin 955", parse_ro_product_board("EVA")); + EXPECT_EQ("HiSilicon Kirin 955", parse_ro_product_board("EVA-AL10")); + EXPECT_EQ("HiSilicon Kirin 955", parse_ro_product_board("EVA-L09")); + EXPECT_EQ("HiSilicon Kirin 955", parse_ro_product_board("EVA-L19")); + EXPECT_EQ("HiSilicon Kirin 955", parse_ro_product_board("VIE-L09")); + EXPECT_EQ("HiSilicon Kirin 955", parse_ro_product_board("VIE-L29")); + EXPECT_EQ("HiSilicon Kirin 960", parse_ro_product_board("DUK")); + EXPECT_EQ("HiSilicon Kirin 960", parse_ro_product_board("LON")); + EXPECT_EQ("HiSilicon Kirin 960", parse_ro_product_board("MHA")); + EXPECT_EQ("HiSilicon Kirin 960", parse_ro_product_board("STF")); + EXPECT_EQ("HiSilicon Kirin 960", parse_ro_product_board("VKY")); + EXPECT_EQ("HiSilicon Kirin 960", parse_ro_product_board("VTR")); } TEST(RO_PRODUCT_BOARD, hisilicon_special) { - EXPECT_EQ("HiSilicon Kirin 620", - parse_ro_product_board("hi6210sft")); - EXPECT_EQ("HiSilicon Kirin 650", - parse_ro_product_board("hi6250")); + EXPECT_EQ("HiSilicon Kirin 620", parse_ro_product_board("hi6210sft")); + EXPECT_EQ("HiSilicon Kirin 650", parse_ro_product_board("hi6250")); #if CPUINFO_ARCH_ARM - EXPECT_EQ("HiSilicon Kirin 920", - parse_ro_product_board("hi3630")); + EXPECT_EQ("HiSilicon Kirin 920", parse_ro_product_board("hi3630")); #endif /* CPUINFO_ARCH_ARM */ - EXPECT_EQ("HiSilicon Kirin 930", - parse_ro_product_board("hi3635")); - EXPECT_EQ("HiSilicon Kirin 950", - parse_ro_product_board("hi3650")); - EXPECT_EQ("HiSilicon Kirin 960", - parse_ro_product_board("hi3660")); - EXPECT_EQ("HiSilicon Kirin 950", - parse_ro_product_board("BEETHOVEN")); + EXPECT_EQ("HiSilicon Kirin 930", parse_ro_product_board("hi3635")); + EXPECT_EQ("HiSilicon Kirin 950", parse_ro_product_board("hi3650")); + EXPECT_EQ("HiSilicon Kirin 960", parse_ro_product_board("hi3660")); + EXPECT_EQ("HiSilicon Kirin 950", parse_ro_product_board("BEETHOVEN")); } #if CPUINFO_ARCH_ARM - TEST(RO_PRODUCT_BOARD, broadcom) { - EXPECT_EQ("Broadcom BCM28155", - parse_ro_product_board("capri", 2, 1200000)); - EXPECT_EQ("Broadcom BCM28155", - parse_ro_product_board("capri", 2, 1300000)); - EXPECT_EQ("Broadcom BCM28155", - parse_ro_product_board("capri", 2, 1399999)); - EXPECT_EQ("Broadcom BCM28155", - parse_ro_product_board("capri", 2, 1399999)); - EXPECT_EQ("Broadcom BCM23550", - parse_ro_product_board("java", 4, 1200000)); - EXPECT_EQ("Broadcom BCM23550", - parse_ro_product_board("java", 4, 1300000)); - EXPECT_EQ("Broadcom BCM21654", - parse_ro_product_board("rhea", 1, 849999)); - EXPECT_EQ("Broadcom BCM21654G", - parse_ro_product_board("rhea", 1, 999999)); - EXPECT_EQ("Broadcom BCM21663", - parse_ro_product_board("hawaii", 1, 999999)); - EXPECT_EQ("Broadcom BCM21664", - parse_ro_product_board("hawaii", 2, 999999)); - EXPECT_EQ("Broadcom BCM21664T", - parse_ro_product_board("hawaii", 2, 1200000)); - } +TEST(RO_PRODUCT_BOARD, broadcom) { + EXPECT_EQ("Broadcom BCM28155", parse_ro_product_board("capri", 2, 1200000)); + EXPECT_EQ("Broadcom BCM28155", parse_ro_product_board("capri", 2, 1300000)); + EXPECT_EQ("Broadcom BCM28155", parse_ro_product_board("capri", 2, 1399999)); + EXPECT_EQ("Broadcom BCM28155", parse_ro_product_board("capri", 2, 1399999)); + EXPECT_EQ("Broadcom BCM23550", parse_ro_product_board("java", 4, 1200000)); + EXPECT_EQ("Broadcom BCM23550", parse_ro_product_board("java", 4, 1300000)); + EXPECT_EQ("Broadcom BCM21654", parse_ro_product_board("rhea", 1, 849999)); + EXPECT_EQ("Broadcom BCM21654G", parse_ro_product_board("rhea", 1, 999999)); + EXPECT_EQ("Broadcom BCM21663", parse_ro_product_board("hawaii", 1, 999999)); + EXPECT_EQ("Broadcom BCM21664", parse_ro_product_board("hawaii", 2, 999999)); + EXPECT_EQ("Broadcom BCM21664T", parse_ro_product_board("hawaii", 2, 1200000)); +} - TEST(RO_PRODUCT_BOARD, leadcore_lc) { - EXPECT_EQ("Leadcore LC1810", - parse_ro_product_board("lc1810")); - } +TEST(RO_PRODUCT_BOARD, leadcore_lc) { + EXPECT_EQ("Leadcore LC1810", parse_ro_product_board("lc1810")); +} - TEST(RO_PRODUCT_BOARD, marvell_pxa) { - EXPECT_EQ("Marvell PXA1088", - parse_ro_product_board("PXA1088")); - EXPECT_EQ("Marvell PXA986", - parse_ro_product_board("PXA986")); - EXPECT_EQ("Marvell PXA988", - parse_ro_product_board("PXA988")); - } +TEST(RO_PRODUCT_BOARD, marvell_pxa) { + EXPECT_EQ("Marvell PXA1088", parse_ro_product_board("PXA1088")); + EXPECT_EQ("Marvell PXA986", parse_ro_product_board("PXA986")); + EXPECT_EQ("Marvell PXA988", parse_ro_product_board("PXA988")); +} - TEST(RO_PRODUCT_BOARD, nvidia) { - EXPECT_EQ("Nvidia Tegra SL460N", - parse_ro_product_board("g2mv")); - EXPECT_EQ("Nvidia Tegra T132", - parse_ro_product_board("flounder")); - EXPECT_EQ("Nvidia Tegra T210", - parse_ro_product_board("dragon")); - EXPECT_EQ("Nvidia Tegra T30L", - parse_ro_product_board("grouper")); - } +TEST(RO_PRODUCT_BOARD, nvidia) { + EXPECT_EQ("Nvidia Tegra SL460N", parse_ro_product_board("g2mv")); + EXPECT_EQ("Nvidia Tegra T132", parse_ro_product_board("flounder")); + EXPECT_EQ("Nvidia Tegra T210", parse_ro_product_board("dragon")); + EXPECT_EQ("Nvidia Tegra T30L", parse_ro_product_board("grouper")); +} - TEST(RO_PRODUCT_BOARD, renesas) { - EXPECT_EQ("Renesas MP5232", - parse_ro_product_board("mp523x")); - } +TEST(RO_PRODUCT_BOARD, renesas) { + EXPECT_EQ("Renesas MP5232", parse_ro_product_board("mp523x")); +} - TEST(RO_PRODUCT_BOARD, rockchip) { - EXPECT_EQ("Rockchip RK3066", - parse_ro_product_board("T7H")); - EXPECT_EQ("Rockchip RK3168", - parse_ro_product_board("hws7701u")); - EXPECT_EQ("Rockchip RK3188", - parse_ro_product_board("K00F")); - } +TEST(RO_PRODUCT_BOARD, rockchip) { + EXPECT_EQ("Rockchip RK3066", parse_ro_product_board("T7H")); + EXPECT_EQ("Rockchip RK3168", parse_ro_product_board("hws7701u")); + EXPECT_EQ("Rockchip RK3188", parse_ro_product_board("K00F")); +} #endif TEST(RO_PRODUCT_BOARD, spreadtrum) { - EXPECT_EQ("Spreadtrum SC6815AS", - parse_ro_product_board("SC6815AS")); - EXPECT_EQ("Spreadtrum SC7715", - parse_ro_product_board("SC7715")); - EXPECT_EQ("Spreadtrum SC7715A", - parse_ro_product_board("SC7715A")); - EXPECT_EQ("Spreadtrum SC7715T", - parse_ro_product_board("SC7715T")); - EXPECT_EQ("Spreadtrum SC7727S", - parse_ro_product_board("SC7727S")); - EXPECT_EQ("Spreadtrum SC7727S", - parse_ro_product_board("sc7727s")); - EXPECT_EQ("Spreadtrum SC7727SE", - parse_ro_product_board("SC7727SE")); - EXPECT_EQ("Spreadtrum SC7730S", - parse_ro_product_board("sc7730s")); - EXPECT_EQ("Spreadtrum SC7730SE", - parse_ro_product_board("SC7730SE")); - EXPECT_EQ("Spreadtrum SC7730SW", - parse_ro_product_board("SC7730SW")); - EXPECT_EQ("Spreadtrum SC7731", - parse_ro_product_board("SC7731")); - EXPECT_EQ("Spreadtrum SC7731C", - parse_ro_product_board("SC7731C")); - EXPECT_EQ("Spreadtrum SC7731G", - parse_ro_product_board("SC7731G")); - EXPECT_EQ("Spreadtrum SC7735S", - parse_ro_product_board("sc7735s")); - EXPECT_EQ("Spreadtrum SC9830A", - parse_ro_product_board("SC9830A")); - EXPECT_EQ("Spreadtrum SC9830I", - parse_ro_product_board("SC9830I")); + EXPECT_EQ("Spreadtrum SC6815AS", parse_ro_product_board("SC6815AS")); + EXPECT_EQ("Spreadtrum SC7715", parse_ro_product_board("SC7715")); + EXPECT_EQ("Spreadtrum SC7715A", parse_ro_product_board("SC7715A")); + EXPECT_EQ("Spreadtrum SC7715T", parse_ro_product_board("SC7715T")); + EXPECT_EQ("Spreadtrum SC7727S", parse_ro_product_board("SC7727S")); + EXPECT_EQ("Spreadtrum SC7727S", parse_ro_product_board("sc7727s")); + EXPECT_EQ("Spreadtrum SC7727SE", parse_ro_product_board("SC7727SE")); + EXPECT_EQ("Spreadtrum SC7730S", parse_ro_product_board("sc7730s")); + EXPECT_EQ("Spreadtrum SC7730SE", parse_ro_product_board("SC7730SE")); + EXPECT_EQ("Spreadtrum SC7730SW", parse_ro_product_board("SC7730SW")); + EXPECT_EQ("Spreadtrum SC7731", parse_ro_product_board("SC7731")); + EXPECT_EQ("Spreadtrum SC7731C", parse_ro_product_board("SC7731C")); + EXPECT_EQ("Spreadtrum SC7731G", parse_ro_product_board("SC7731G")); + EXPECT_EQ("Spreadtrum SC7735S", parse_ro_product_board("sc7735s")); + EXPECT_EQ("Spreadtrum SC9830A", parse_ro_product_board("SC9830A")); + EXPECT_EQ("Spreadtrum SC9830I", parse_ro_product_board("SC9830I")); } #if CPUINFO_ARCH_ARM - TEST(RO_PRODUCT_BOARD, texas_instruments) { - EXPECT_EQ("Texas Instruments OMAP4460", - parse_ro_product_board("tuna")); - } +TEST(RO_PRODUCT_BOARD, texas_instruments) { + EXPECT_EQ("Texas Instruments OMAP4460", parse_ro_product_board("tuna")); +} #endif /* CPUINFO_ARCH_ARM */ diff --git a/test/size.c b/test/size.c index 58dbabd2..513eac40 100644 --- a/test/size.c +++ b/test/size.c @@ -1,6 +1,5 @@ #include - int main(int argc, char** argv) { cpuinfo_initialize(); return 0; diff --git a/tools/auxv-dump.c b/tools/auxv-dump.c index a15e5c10..a7773dce 100644 --- a/tools/auxv-dump.c +++ b/tools/auxv-dump.c @@ -1,13 +1,12 @@ -#include #include +#include -#include -#include #include +#include +#include #include - typedef unsigned long (*getauxval_function_t)(unsigned long); int main(int argc, char** argv) { @@ -17,16 +16,16 @@ int main(int argc, char** argv) { exit(EXIT_FAILURE); } - getauxval_function_t getauxval = (getauxval_function_t) dlsym(libc, "getauxval"); + getauxval_function_t getauxval = (getauxval_function_t)dlsym(libc, "getauxval"); if (getauxval == NULL) { fprintf(stderr, "Error: failed to locate getauxval in libc.so: %s", dlerror()); exit(EXIT_FAILURE); } printf("AT_HWCAP = 0x%08lX\n", getauxval(AT_HWCAP)); - #if CPUINFO_ARCH_ARM - printf("AT_HWCAP2 = 0x%08lX\n", getauxval(AT_HWCAP2)); - #endif +#if CPUINFO_ARCH_ARM + printf("AT_HWCAP2 = 0x%08lX\n", getauxval(AT_HWCAP2)); +#endif return 0; } diff --git a/tools/cache-info.c b/tools/cache-info.c index 05f69eeb..a6a7120a 100644 --- a/tools/cache-info.c +++ b/tools/cache-info.c @@ -1,16 +1,12 @@ +#include #include #include -#include #include - -void report_cache( - uint32_t count, const struct cpuinfo_cache* cache, - uint32_t level, const char* nonunified_type) -{ +void report_cache(uint32_t count, const struct cpuinfo_cache* cache, uint32_t level, const char* nonunified_type) { const char* type = (cache->flags & CPUINFO_CACHE_UNIFIED) ? "unified" : nonunified_type; - printf("L%"PRIu32" %s cache: ", level, type); + printf("L%" PRIu32 " %s cache: ", level, type); uint32_t size = cache->size; const char* units = "bytes"; @@ -22,23 +18,26 @@ void report_cache( units = "KB"; } if (count != 1) { - printf("%"PRIu32" x ", count); + printf("%" PRIu32 " x ", count); } if (level == 1) { - printf("%"PRIu32" %s, ", size, units); + printf("%" PRIu32 " %s, ", size, units); } else { - printf("%"PRIu32" %s (%s), ", size, units, (cache->flags & CPUINFO_CACHE_INCLUSIVE) ? "inclusive" : "exclusive"); + printf("%" PRIu32 " %s (%s), ", + size, + units, + (cache->flags & CPUINFO_CACHE_INCLUSIVE) ? "inclusive" : "exclusive"); } if (cache->associativity * cache->line_size == cache->size) { printf("fully associative"); } else { - printf("%"PRIu32"-way set associative", cache->associativity); + printf("%" PRIu32 "-way set associative", cache->associativity); } if (cache->sets != 0) { - printf(" (%"PRIu32" sets", cache->sets); + printf(" (%" PRIu32 " sets", cache->sets); if (cache->partitions != 1) { - printf(", %"PRIu32" partitions", cache->partitions); + printf(", %" PRIu32 " partitions", cache->partitions); } if (cache->flags & CPUINFO_CACHE_COMPLEX_INDEXING) { printf(", complex indexing), "); @@ -47,9 +46,9 @@ void report_cache( } } - printf("%"PRIu32" byte lines", cache->line_size); + printf("%" PRIu32 " byte lines", cache->line_size); if (cache->processor_count != 0) { - printf(", shared by %"PRIu32" processors\n", cache->processor_count); + printf(", shared by %" PRIu32 " processors\n", cache->processor_count); } else { printf("\n"); } @@ -60,7 +59,7 @@ int main(int argc, char** argv) { fprintf(stderr, "failed to initialize CPU information\n"); exit(EXIT_FAILURE); } - printf("Max cache size (upper bound): %"PRIu32" bytes\n", cpuinfo_get_max_cache_size()); + printf("Max cache size (upper bound): %" PRIu32 " bytes\n", cpuinfo_get_max_cache_size()); if (cpuinfo_get_l1i_caches_count() != 0 && (cpuinfo_get_l1i_cache(0)->flags & CPUINFO_CACHE_UNIFIED) == 0) { report_cache(cpuinfo_get_l1i_caches_count(), cpuinfo_get_l1i_cache(0), 1, "instruction"); diff --git a/tools/cpu-info.c b/tools/cpu-info.c index 5b82dd0a..a4ace204 100644 --- a/tools/cpu-info.c +++ b/tools/cpu-info.c @@ -1,11 +1,10 @@ -#include +#include #include +#include #include -#include #include - static const char* vendor_to_string(enum cpuinfo_vendor vendor) { switch (vendor) { case cpuinfo_vendor_unknown: @@ -293,65 +292,67 @@ int main(int argc, char** argv) { fprintf(stderr, "failed to initialize CPU information\n"); exit(EXIT_FAILURE); } - #ifdef __ANDROID__ - printf("SoC name: %s\n", cpuinfo_get_package(0)->name); - #else - printf("Packages:\n"); - for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { - printf("\t%"PRIu32": %s\n", i, cpuinfo_get_package(i)->name); - } - #endif +#ifdef __ANDROID__ + printf("SoC name: %s\n", cpuinfo_get_package(0)->name); +#else + printf("Packages:\n"); + for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { + printf("\t%" PRIu32 ": %s\n", i, cpuinfo_get_package(i)->name); + } +#endif printf("Microarchitectures:\n"); for (uint32_t i = 0; i < cpuinfo_get_uarchs_count(); i++) { const struct cpuinfo_uarch_info* uarch_info = cpuinfo_get_uarch(i); const char* uarch_string = uarch_to_string(uarch_info->uarch); if (uarch_string == NULL) { - printf("\t%"PRIu32"x Unknown (0x%08"PRIx32"\n", - uarch_info->core_count, (uint32_t) uarch_info->uarch); + printf("\t%" PRIu32 "x Unknown (0x%08" PRIx32 "\n", + uarch_info->core_count, + (uint32_t)uarch_info->uarch); } else { - printf("\t%"PRIu32"x %s\n", uarch_info->core_count, uarch_string); + printf("\t%" PRIu32 "x %s\n", uarch_info->core_count, uarch_string); } } printf("Cores:\n"); for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { const struct cpuinfo_core* core = cpuinfo_get_core(i); if (core->processor_count == 1) { - printf("\t%"PRIu32": 1 processor (%"PRIu32")", i, core->processor_start); + printf("\t%" PRIu32 ": 1 processor (%" PRIu32 ")", i, core->processor_start); } else { - printf("\t%"PRIu32": %"PRIu32" processors (%"PRIu32"-%"PRIu32")", - i, core->processor_count, core->processor_start, core->processor_start + core->processor_count - 1); + printf("\t%" PRIu32 ": %" PRIu32 " processors (%" PRIu32 "-%" PRIu32 ")", + i, + core->processor_count, + core->processor_start, + core->processor_start + core->processor_count - 1); } const char* vendor_string = vendor_to_string(core->vendor); const char* uarch_string = uarch_to_string(core->uarch); if (vendor_string == NULL) { - printf(", vendor 0x%08"PRIx32" uarch 0x%08"PRIx32"\n", - (uint32_t) core->vendor, (uint32_t) core->uarch); - } - else if (uarch_string == NULL) { - printf(", %s uarch 0x%08"PRIx32"\n", - vendor_string, (uint32_t) core->uarch); - } - else { + printf(", vendor 0x%08" PRIx32 " uarch 0x%08" PRIx32 "\n", + (uint32_t)core->vendor, + (uint32_t)core->uarch); + } else if (uarch_string == NULL) { + printf(", %s uarch 0x%08" PRIx32 "\n", vendor_string, (uint32_t)core->uarch); + } else { printf(", %s %s\n", vendor_string, uarch_string); } } printf("Logical processors"); - #if defined(__linux__) - printf(" (System ID)"); - #endif +#if defined(__linux__) + printf(" (System ID)"); +#endif printf(":\n"); for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { const struct cpuinfo_processor* processor = cpuinfo_get_processor(i); - printf("\t%"PRIu32"", i); + printf("\t%" PRIu32 "", i); - #if defined(__linux__) - printf(" (%"PRId32")", processor->linux_id); - #endif +#if defined(__linux__) + printf(" (%" PRId32 ")", processor->linux_id); +#endif - #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 - printf(": APIC ID 0x%08"PRIx32"\n", processor->apic_id); - #else - printf("\n"); - #endif +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + printf(": APIC ID 0x%08" PRIx32 "\n", processor->apic_id); +#else + printf("\n"); +#endif } } diff --git a/tools/cpuid-dump.c b/tools/cpuid-dump.c index 58eb1b78..87c403d5 100644 --- a/tools/cpuid-dump.c +++ b/tools/cpuid-dump.c @@ -1,18 +1,27 @@ -#include -#include #include +#include +#include #include #include static void print_cpuid(struct cpuid_regs regs, uint32_t eax) { - printf("CPUID %08"PRIX32": %08"PRIX32"-%08"PRIX32"-%08"PRIX32"-%08"PRIX32"\n", - eax, regs.eax, regs.ebx, regs.ecx, regs.edx); + printf("CPUID %08" PRIX32 ": %08" PRIX32 "-%08" PRIX32 "-%08" PRIX32 "-%08" PRIX32 "\n", + eax, + regs.eax, + regs.ebx, + regs.ecx, + regs.edx); } static void print_cpuidex(struct cpuid_regs regs, uint32_t eax, uint32_t ecx) { - printf("CPUID %08"PRIX32": %08"PRIX32"-%08"PRIX32"-%08"PRIX32"-%08"PRIX32" [SL %02"PRIX32"]\n", - eax, regs.eax, regs.ebx, regs.ecx, regs.edx, ecx); + printf("CPUID %08" PRIX32 ": %08" PRIX32 "-%08" PRIX32 "-%08" PRIX32 "-%08" PRIX32 " [SL %02" PRIX32 "]\n", + eax, + regs.eax, + regs.ebx, + regs.ecx, + regs.edx, + ecx); } static void print_cpuid_vendor(struct cpuid_regs regs, uint32_t eax) { @@ -21,8 +30,13 @@ static void print_cpuid_vendor(struct cpuid_regs regs, uint32_t eax) { memcpy(&vendor_id[0], ®s.ebx, sizeof(regs.ebx)); memcpy(&vendor_id[4], ®s.edx, sizeof(regs.edx)); memcpy(&vendor_id[8], ®s.ecx, sizeof(regs.ecx)); - printf("CPUID %08"PRIX32": %08"PRIX32"-%08"PRIX32"-%08"PRIX32"-%08"PRIX32" [%.12s]\n", - eax, regs.eax, regs.ebx, regs.ecx, regs.edx, vendor_id); + printf("CPUID %08" PRIX32 ": %08" PRIX32 "-%08" PRIX32 "-%08" PRIX32 "-%08" PRIX32 " [%.12s]\n", + eax, + regs.eax, + regs.ebx, + regs.ecx, + regs.edx, + vendor_id); } else { print_cpuid(regs, eax); } @@ -34,8 +48,13 @@ static void print_cpuid_brand_string(struct cpuid_regs regs, uint32_t eax) { memcpy(&brand_string[4], ®s.ebx, sizeof(regs.ebx)); memcpy(&brand_string[8], ®s.ecx, sizeof(regs.ecx)); memcpy(&brand_string[12], ®s.edx, sizeof(regs.edx)); - printf("CPUID %08"PRIX32": %08"PRIX32"-%08"PRIX32"-%08"PRIX32"-%08"PRIX32" [%.16s]\n", - eax, regs.eax, regs.ebx, regs.ecx, regs.edx, brand_string); + printf("CPUID %08" PRIX32 ": %08" PRIX32 "-%08" PRIX32 "-%08" PRIX32 "-%08" PRIX32 " [%.16s]\n", + eax, + regs.eax, + regs.ebx, + regs.ecx, + regs.edx, + brand_string); } int main(int argc, char** argv) { @@ -48,7 +67,7 @@ int main(int argc, char** argv) { print_cpuid_vendor(cpuid(eax), eax); break; case UINT32_C(0x00000004): - for (uint32_t ecx = 0; ; ecx++) { + for (uint32_t ecx = 0;; ecx++) { const struct cpuid_regs regs = cpuidex(eax, ecx); if ((regs.eax & UINT32_C(0x1F)) == 0) { break; @@ -67,7 +86,7 @@ int main(int argc, char** argv) { } break; case UINT32_C(0x0000000B): - for (uint32_t ecx = 0; ; ecx++) { + for (uint32_t ecx = 0;; ecx++) { const struct cpuid_regs regs = cpuidex(eax, ecx); if ((regs.ecx & UINT32_C(0x0000FF00)) == 0) { break; @@ -77,7 +96,7 @@ int main(int argc, char** argv) { break; case UINT32_C(0x00000012): if (has_sgx) { - for (uint32_t ecx = 0; ; ecx++) { + for (uint32_t ecx = 0;; ecx++) { const struct cpuid_regs regs = cpuidex(eax, ecx); if (ecx >= 2 && (regs.eax & UINT32_C(0x0000000F)) == 0) { break; diff --git a/tools/cpuinfo-dump.c b/tools/cpuinfo-dump.c index 5b5228aa..1673c53a 100644 --- a/tools/cpuinfo-dump.c +++ b/tools/cpuinfo-dump.c @@ -2,10 +2,9 @@ #include #include -#include -#include #include - +#include +#include #define BUFFER_SIZE 4096 char buffer[BUFFER_SIZE]; @@ -26,14 +25,17 @@ int main(int argc, char** argv) { do { bytes_read = read(file, buffer, BUFFER_SIZE); if (bytes_read < 0) { - fprintf(stderr, "Error: failed to read file %s at position %zu: %s\n", - CPUINFO_PATH, position, strerror(errno)); + fprintf(stderr, + "Error: failed to read file %s at position %zu: %s\n", + CPUINFO_PATH, + position, + strerror(errno)); exit(EXIT_FAILURE); } - position += (size_t) bytes_read; + position += (size_t)bytes_read; if (bytes_read > 0) { - fwrite(buffer, 1, (size_t) bytes_read, stdout); + fwrite(buffer, 1, (size_t)bytes_read, stdout); } } while (bytes_read != 0); diff --git a/tools/gpu-dump.c b/tools/gpu-dump.c index 6d173741..e7144b64 100644 --- a/tools/gpu-dump.c +++ b/tools/gpu-dump.c @@ -1,14 +1,12 @@ +#include +#include #include #include -#include -#include #include #include - -#define COUNT_OF(x) (sizeof(x) / sizeof(0[x])) - +#define COUNT_OF(x) (sizeof(x) / sizeof(0 [x])) struct egl_enum_item { EGLint id; @@ -64,7 +62,7 @@ struct egl_enum_item egl_enum_color_buffer[] = { }; #ifndef EGL_OPENGL_ES3_BIT - #define EGL_OPENGL_ES3_BIT 0x40 +#define EGL_OPENGL_ES3_BIT 0x40 #endif struct egl_enum_item egl_enum_conformant[] = { @@ -253,19 +251,19 @@ struct egl_config_attribute egl_config_attributes[] = { { .id = EGL_SURFACE_TYPE, .name = "EGL_SURFACE_TYPE", - .cardinality = -(int32_t) COUNT_OF(egl_enum_surface_type), + .cardinality = -(int32_t)COUNT_OF(egl_enum_surface_type), .values = egl_enum_surface_type, }, { .id = EGL_RENDERABLE_TYPE, .name = "EGL_RENDERABLE_TYPE", - .cardinality = -(int32_t) COUNT_OF(egl_enum_renderable_type), + .cardinality = -(int32_t)COUNT_OF(egl_enum_renderable_type), .values = egl_enum_renderable_type, }, { .id = EGL_CONFORMANT, .name = "EGL_CONFORMANT", - .cardinality = -(int32_t) COUNT_OF(egl_enum_conformant), + .cardinality = -(int32_t)COUNT_OF(egl_enum_conformant), .values = egl_enum_conformant, }, { @@ -306,7 +304,7 @@ void report_gles_attributes(void) { fprintf(stderr, "failed to initialize EGL display connection\n"); goto cleanup; } - printf("initialized display connection with EGL %d.%d\n", (int) egl_major, (int) egl_minor); + printf("initialized display connection with EGL %d.%d\n", (int)egl_major, (int)egl_minor); EGLint configs_count = 0; egl_status = eglGetConfigs(display, NULL, 0, &configs_count); @@ -315,10 +313,12 @@ void report_gles_attributes(void) { goto cleanup; } - configs = (EGLConfig*) malloc(configs_count * sizeof(EGLConfig)); + configs = (EGLConfig*)malloc(configs_count * sizeof(EGLConfig)); if (configs == NULL) { - fprintf(stderr, "failed to allocate %zu bytes for %d frame buffer configurations\n", - configs_count * sizeof(EGLConfig), configs_count); + fprintf(stderr, + "failed to allocate %zu bytes for %d frame buffer configurations\n", + configs_count * sizeof(EGLConfig), + configs_count); goto cleanup; } @@ -330,18 +330,20 @@ void report_gles_attributes(void) { printf("EGL framebuffer configurations:\n"); for (EGLint i = 0; i < configs_count; i++) { - printf("\tConfiguration #%d:\n", (int) i); + printf("\tConfiguration #%d:\n", (int)i); for (size_t n = 0; n < COUNT_OF(egl_config_attributes); n++) { EGLint value = 0; egl_status = eglGetConfigAttrib(display, configs[i], egl_config_attributes[n].id, &value); if (egl_config_attributes[n].cardinality == 0) { - printf("\t\t%s: %d\n", egl_config_attributes[n].name, (int) value); + printf("\t\t%s: %d\n", egl_config_attributes[n].name, (int)value); } else if (egl_config_attributes[n].cardinality > 0) { /* Enumeration */ bool known_value = false; - for (size_t k = 0; k < (size_t) egl_config_attributes[n].cardinality; k++) { + for (size_t k = 0; k < (size_t)egl_config_attributes[n].cardinality; k++) { if (egl_config_attributes[n].values[k].id == value) { - printf("\t\t%s: %s\n", egl_config_attributes[n].name, egl_config_attributes[n].values[k].name); + printf("\t\t%s: %s\n", + egl_config_attributes[n].name, + egl_config_attributes[n].values[k].name); known_value = true; break; } @@ -355,18 +357,19 @@ void report_gles_attributes(void) { if (value == 0) { printf("none\n"); } else { - for (size_t k = 0; k < (size_t) -egl_config_attributes[n].cardinality; k++) { + for (size_t k = 0; k < (size_t)-egl_config_attributes[n].cardinality; k++) { if (egl_config_attributes[n].values[k].id & value) { value &= ~egl_config_attributes[n].values[k].id; if (value != 0) { - printf("%s | ", egl_config_attributes[n].values[k].name); + printf("%s | ", + egl_config_attributes[n].values[k].name); } else { printf("%s\n", egl_config_attributes[n].values[k].name); } } } if (value != 0) { - printf("0x%08X\n", (int) value); + printf("0x%08X\n", (int)value); } } } @@ -374,10 +377,14 @@ void report_gles_attributes(void) { } EGLint const config_attributes[] = { - EGL_BIND_TO_TEXTURE_RGBA, EGL_TRUE, - EGL_RENDERABLE_TYPE, EGL_OPENGL_ES2_BIT, - EGL_CONFORMANT, EGL_OPENGL_ES2_BIT, - EGL_SURFACE_TYPE, EGL_PBUFFER_BIT, + EGL_BIND_TO_TEXTURE_RGBA, + EGL_TRUE, + EGL_RENDERABLE_TYPE, + EGL_OPENGL_ES2_BIT, + EGL_CONFORMANT, + EGL_OPENGL_ES2_BIT, + EGL_SURFACE_TYPE, + EGL_PBUFFER_BIT, EGL_NONE, }; EGLConfig config = NULL; @@ -389,10 +396,14 @@ void report_gles_attributes(void) { } EGLint const surface_attributes[] = { - EGL_HEIGHT, 1, - EGL_WIDTH, 1, - EGL_TEXTURE_FORMAT, EGL_TEXTURE_RGBA, - EGL_TEXTURE_TARGET, EGL_TEXTURE_2D, + EGL_HEIGHT, + 1, + EGL_WIDTH, + 1, + EGL_TEXTURE_FORMAT, + EGL_TEXTURE_RGBA, + EGL_TEXTURE_TARGET, + EGL_TEXTURE_2D, EGL_NONE, }; surface = eglCreatePbufferSurface(display, config, surface_attributes); @@ -402,7 +413,8 @@ void report_gles_attributes(void) { } EGLint const context_attributes[] = { - EGL_CONTEXT_CLIENT_VERSION, 2, + EGL_CONTEXT_CLIENT_VERSION, + 2, EGL_NONE, }; context = eglCreateContext(display, config, EGL_NO_CONTEXT, context_attributes); diff --git a/tools/isa-info.c b/tools/isa-info.c index ff69791d..892be0be 100644 --- a/tools/isa-info.c +++ b/tools/isa-info.c @@ -13,180 +13,173 @@ int main(int argc, char** argv) { printf("Scalar instructions:\n"); #if CPUINFO_ARCH_X86 - printf("\tx87 FPU: %s\n", cpuinfo_has_x86_fpu() ? "yes" : "no"); - printf("\tCMOV: %s\n", cpuinfo_has_x86_cmov() ? "yes" : "no"); + printf("\tx87 FPU: %s\n", cpuinfo_has_x86_fpu() ? "yes" : "no"); + printf("\tCMOV: %s\n", cpuinfo_has_x86_cmov() ? "yes" : "no"); #endif - printf("\tLAHF/SAHF: %s\n", cpuinfo_has_x86_lahf_sahf() ? "yes" : "no"); - printf("\tLZCNT: %s\n", cpuinfo_has_x86_lzcnt() ? "yes" : "no"); - printf("\tPOPCNT: %s\n", cpuinfo_has_x86_popcnt() ? "yes" : "no"); - printf("\tTBM: %s\n", cpuinfo_has_x86_tbm() ? "yes" : "no"); - printf("\tBMI: %s\n", cpuinfo_has_x86_bmi() ? "yes" : "no"); - printf("\tBMI2: %s\n", cpuinfo_has_x86_bmi2() ? "yes" : "no"); - printf("\tADCX/ADOX: %s\n", cpuinfo_has_x86_adx() ? "yes" : "no"); - + printf("\tLAHF/SAHF: %s\n", cpuinfo_has_x86_lahf_sahf() ? "yes" : "no"); + printf("\tLZCNT: %s\n", cpuinfo_has_x86_lzcnt() ? "yes" : "no"); + printf("\tPOPCNT: %s\n", cpuinfo_has_x86_popcnt() ? "yes" : "no"); + printf("\tTBM: %s\n", cpuinfo_has_x86_tbm() ? "yes" : "no"); + printf("\tBMI: %s\n", cpuinfo_has_x86_bmi() ? "yes" : "no"); + printf("\tBMI2: %s\n", cpuinfo_has_x86_bmi2() ? "yes" : "no"); + printf("\tADCX/ADOX: %s\n", cpuinfo_has_x86_adx() ? "yes" : "no"); printf("Memory instructions:\n"); - printf("\tMOVBE: %s\n", cpuinfo_has_x86_movbe() ? "yes" : "no"); - printf("\tPREFETCH: %s\n", cpuinfo_has_x86_prefetch() ? "yes" : "no"); - printf("\tPREFETCHW: %s\n", cpuinfo_has_x86_prefetchw() ? "yes" : "no"); - printf("\tPREFETCHWT1: %s\n", cpuinfo_has_x86_prefetchwt1() ? "yes" : "no"); - printf("\tCLZERO: %s\n", cpuinfo_has_x86_clzero() ? "yes" : "no"); - + printf("\tMOVBE: %s\n", cpuinfo_has_x86_movbe() ? "yes" : "no"); + printf("\tPREFETCH: %s\n", cpuinfo_has_x86_prefetch() ? "yes" : "no"); + printf("\tPREFETCHW: %s\n", cpuinfo_has_x86_prefetchw() ? "yes" : "no"); + printf("\tPREFETCHWT1: %s\n", cpuinfo_has_x86_prefetchwt1() ? "yes" : "no"); + printf("\tCLZERO: %s\n", cpuinfo_has_x86_clzero() ? "yes" : "no"); printf("SIMD extensions:\n"); - printf("\tMMX: %s\n", cpuinfo_has_x86_mmx() ? "yes" : "no"); - printf("\tMMX+: %s\n", cpuinfo_has_x86_mmx_plus() ? "yes" : "no"); - printf("\t3dnow!: %s\n", cpuinfo_has_x86_3dnow() ? "yes" : "no"); - printf("\t3dnow!+: %s\n", cpuinfo_has_x86_3dnow_plus() ? "yes" : "no"); - printf("\t3dnow! Geode: %s\n", cpuinfo_has_x86_3dnow_geode() ? "yes" : "no"); - printf("\tDAZ: %s\n", cpuinfo_has_x86_daz() ? "yes" : "no"); - printf("\tSSE: %s\n", cpuinfo_has_x86_sse() ? "yes" : "no"); - printf("\tSSE2: %s\n", cpuinfo_has_x86_sse2() ? "yes" : "no"); - printf("\tSSE3: %s\n", cpuinfo_has_x86_sse3() ? "yes" : "no"); - printf("\tSSSE3: %s\n", cpuinfo_has_x86_ssse3() ? "yes" : "no"); - printf("\tSSE4.1: %s\n", cpuinfo_has_x86_sse4_1() ? "yes" : "no"); - printf("\tSSE4.2: %s\n", cpuinfo_has_x86_sse4_2() ? "yes" : "no"); - printf("\tSSE4a: %s\n", cpuinfo_has_x86_sse4a() ? "yes" : "no"); - printf("\tMisaligned SSE: %s\n", cpuinfo_has_x86_misaligned_sse() ? "yes" : "no"); - printf("\tAVX: %s\n", cpuinfo_has_x86_avx() ? "yes" : "no"); - printf("\tFMA3: %s\n", cpuinfo_has_x86_fma3() ? "yes" : "no"); - printf("\tFMA4: %s\n", cpuinfo_has_x86_fma4() ? "yes" : "no"); - printf("\tXOP: %s\n", cpuinfo_has_x86_xop() ? "yes" : "no"); - printf("\tF16C: %s\n", cpuinfo_has_x86_f16c() ? "yes" : "no"); - printf("\tAVX2: %s\n", cpuinfo_has_x86_avx2() ? "yes" : "no"); - printf("\tAVX512F: %s\n", cpuinfo_has_x86_avx512f() ? "yes" : "no"); - printf("\tAVX512PF: %s\n", cpuinfo_has_x86_avx512pf() ? "yes" : "no"); - printf("\tAVX512ER: %s\n", cpuinfo_has_x86_avx512er() ? "yes" : "no"); - printf("\tAVX512CD: %s\n", cpuinfo_has_x86_avx512cd() ? "yes" : "no"); - printf("\tAVX512DQ: %s\n", cpuinfo_has_x86_avx512dq() ? "yes" : "no"); - printf("\tAVX512BW: %s\n", cpuinfo_has_x86_avx512bw() ? "yes" : "no"); - printf("\tAVX512VL: %s\n", cpuinfo_has_x86_avx512vl() ? "yes" : "no"); - printf("\tAVX512IFMA: %s\n", cpuinfo_has_x86_avx512ifma() ? "yes" : "no"); - printf("\tAVX512VBMI: %s\n", cpuinfo_has_x86_avx512vbmi() ? "yes" : "no"); - printf("\tAVX512VBMI2: %s\n", cpuinfo_has_x86_avx512vbmi2() ? "yes" : "no"); - printf("\tAVX512BITALG: %s\n", cpuinfo_has_x86_avx512bitalg() ? "yes" : "no"); - printf("\tAVX512VPOPCNTDQ: %s\n", cpuinfo_has_x86_avx512vpopcntdq() ? "yes" : "no"); - printf("\tAVX512VNNI: %s\n", cpuinfo_has_x86_avx512vnni() ? "yes" : "no"); - printf("\tAVX512BF16: %s\n", cpuinfo_has_x86_avx512bf16() ? "yes" : "no"); - printf("\tAVX512FP16: %s\n", cpuinfo_has_x86_avx512fp16() ? "yes" : "no"); - printf("\tAVX512VP2INTERSECT: %s\n", cpuinfo_has_x86_avx512vp2intersect() ? "yes" : "no"); - printf("\tAVX512_4VNNIW: %s\n", cpuinfo_has_x86_avx512_4vnniw() ? "yes" : "no"); - printf("\tAVX512_4FMAPS: %s\n", cpuinfo_has_x86_avx512_4fmaps() ? "yes" : "no"); - printf("\tAVXVNNI: %s\n", cpuinfo_has_x86_avxvnni() ? "yes" : "no"); - + printf("\tMMX: %s\n", cpuinfo_has_x86_mmx() ? "yes" : "no"); + printf("\tMMX+: %s\n", cpuinfo_has_x86_mmx_plus() ? "yes" : "no"); + printf("\t3dnow!: %s\n", cpuinfo_has_x86_3dnow() ? "yes" : "no"); + printf("\t3dnow!+: %s\n", cpuinfo_has_x86_3dnow_plus() ? "yes" : "no"); + printf("\t3dnow! Geode: %s\n", cpuinfo_has_x86_3dnow_geode() ? "yes" : "no"); + printf("\tDAZ: %s\n", cpuinfo_has_x86_daz() ? "yes" : "no"); + printf("\tSSE: %s\n", cpuinfo_has_x86_sse() ? "yes" : "no"); + printf("\tSSE2: %s\n", cpuinfo_has_x86_sse2() ? "yes" : "no"); + printf("\tSSE3: %s\n", cpuinfo_has_x86_sse3() ? "yes" : "no"); + printf("\tSSSE3: %s\n", cpuinfo_has_x86_ssse3() ? "yes" : "no"); + printf("\tSSE4.1: %s\n", cpuinfo_has_x86_sse4_1() ? "yes" : "no"); + printf("\tSSE4.2: %s\n", cpuinfo_has_x86_sse4_2() ? "yes" : "no"); + printf("\tSSE4a: %s\n", cpuinfo_has_x86_sse4a() ? "yes" : "no"); + printf("\tMisaligned SSE: %s\n", cpuinfo_has_x86_misaligned_sse() ? "yes" : "no"); + printf("\tAVX: %s\n", cpuinfo_has_x86_avx() ? "yes" : "no"); + printf("\tFMA3: %s\n", cpuinfo_has_x86_fma3() ? "yes" : "no"); + printf("\tFMA4: %s\n", cpuinfo_has_x86_fma4() ? "yes" : "no"); + printf("\tXOP: %s\n", cpuinfo_has_x86_xop() ? "yes" : "no"); + printf("\tF16C: %s\n", cpuinfo_has_x86_f16c() ? "yes" : "no"); + printf("\tAVX2: %s\n", cpuinfo_has_x86_avx2() ? "yes" : "no"); + printf("\tAVX512F: %s\n", cpuinfo_has_x86_avx512f() ? "yes" : "no"); + printf("\tAVX512PF: %s\n", cpuinfo_has_x86_avx512pf() ? "yes" : "no"); + printf("\tAVX512ER: %s\n", cpuinfo_has_x86_avx512er() ? "yes" : "no"); + printf("\tAVX512CD: %s\n", cpuinfo_has_x86_avx512cd() ? "yes" : "no"); + printf("\tAVX512DQ: %s\n", cpuinfo_has_x86_avx512dq() ? "yes" : "no"); + printf("\tAVX512BW: %s\n", cpuinfo_has_x86_avx512bw() ? "yes" : "no"); + printf("\tAVX512VL: %s\n", cpuinfo_has_x86_avx512vl() ? "yes" : "no"); + printf("\tAVX512IFMA: %s\n", cpuinfo_has_x86_avx512ifma() ? "yes" : "no"); + printf("\tAVX512VBMI: %s\n", cpuinfo_has_x86_avx512vbmi() ? "yes" : "no"); + printf("\tAVX512VBMI2: %s\n", cpuinfo_has_x86_avx512vbmi2() ? "yes" : "no"); + printf("\tAVX512BITALG: %s\n", cpuinfo_has_x86_avx512bitalg() ? "yes" : "no"); + printf("\tAVX512VPOPCNTDQ: %s\n", cpuinfo_has_x86_avx512vpopcntdq() ? "yes" : "no"); + printf("\tAVX512VNNI: %s\n", cpuinfo_has_x86_avx512vnni() ? "yes" : "no"); + printf("\tAVX512BF16: %s\n", cpuinfo_has_x86_avx512bf16() ? "yes" : "no"); + printf("\tAVX512FP16: %s\n", cpuinfo_has_x86_avx512fp16() ? "yes" : "no"); + printf("\tAVX512VP2INTERSECT: %s\n", cpuinfo_has_x86_avx512vp2intersect() ? "yes" : "no"); + printf("\tAVX512_4VNNIW: %s\n", cpuinfo_has_x86_avx512_4vnniw() ? "yes" : "no"); + printf("\tAVX512_4FMAPS: %s\n", cpuinfo_has_x86_avx512_4fmaps() ? "yes" : "no"); + printf("\tAVXVNNI: %s\n", cpuinfo_has_x86_avxvnni() ? "yes" : "no"); printf("Multi-threading extensions:\n"); - printf("\tMONITOR/MWAIT: %s\n", cpuinfo_has_x86_mwait() ? "yes" : "no"); - printf("\tMONITORX/MWAITX: %s\n", cpuinfo_has_x86_mwaitx() ? "yes" : "no"); + printf("\tMONITOR/MWAIT: %s\n", cpuinfo_has_x86_mwait() ? "yes" : "no"); + printf("\tMONITORX/MWAITX: %s\n", cpuinfo_has_x86_mwaitx() ? "yes" : "no"); #if CPUINFO_ARCH_X86 - printf("\tCMPXCHG8B: %s\n", cpuinfo_has_x86_cmpxchg8b() ? "yes" : "no"); + printf("\tCMPXCHG8B: %s\n", cpuinfo_has_x86_cmpxchg8b() ? "yes" : "no"); #endif - printf("\tCMPXCHG16B: %s\n", cpuinfo_has_x86_cmpxchg16b() ? "yes" : "no"); - printf("\tHLE: %s\n", cpuinfo_has_x86_hle() ? "yes" : "no"); - printf("\tRTM: %s\n", cpuinfo_has_x86_rtm() ? "yes" : "no"); - printf("\tXTEST: %s\n", cpuinfo_has_x86_xtest() ? "yes" : "no"); - printf("\tRDPID: %s\n", cpuinfo_has_x86_rdpid() ? "yes" : "no"); - + printf("\tCMPXCHG16B: %s\n", cpuinfo_has_x86_cmpxchg16b() ? "yes" : "no"); + printf("\tHLE: %s\n", cpuinfo_has_x86_hle() ? "yes" : "no"); + printf("\tRTM: %s\n", cpuinfo_has_x86_rtm() ? "yes" : "no"); + printf("\tXTEST: %s\n", cpuinfo_has_x86_xtest() ? "yes" : "no"); + printf("\tRDPID: %s\n", cpuinfo_has_x86_rdpid() ? "yes" : "no"); printf("Cryptography extensions:\n"); - printf("\tAES: %s\n", cpuinfo_has_x86_aes() ? "yes" : "no"); - printf("\tVAES: %s\n", cpuinfo_has_x86_vaes() ? "yes" : "no"); - printf("\tPCLMULQDQ: %s\n", cpuinfo_has_x86_pclmulqdq() ? "yes" : "no"); - printf("\tVPCLMULQDQ: %s\n", cpuinfo_has_x86_vpclmulqdq() ? "yes" : "no"); - printf("\tGFNI: %s\n", cpuinfo_has_x86_gfni() ? "yes" : "no"); - printf("\tRDRAND: %s\n", cpuinfo_has_x86_rdrand() ? "yes" : "no"); - printf("\tRDSEED: %s\n", cpuinfo_has_x86_rdseed() ? "yes" : "no"); - printf("\tSHA: %s\n", cpuinfo_has_x86_sha() ? "yes" : "no"); - + printf("\tAES: %s\n", cpuinfo_has_x86_aes() ? "yes" : "no"); + printf("\tVAES: %s\n", cpuinfo_has_x86_vaes() ? "yes" : "no"); + printf("\tPCLMULQDQ: %s\n", cpuinfo_has_x86_pclmulqdq() ? "yes" : "no"); + printf("\tVPCLMULQDQ: %s\n", cpuinfo_has_x86_vpclmulqdq() ? "yes" : "no"); + printf("\tGFNI: %s\n", cpuinfo_has_x86_gfni() ? "yes" : "no"); + printf("\tRDRAND: %s\n", cpuinfo_has_x86_rdrand() ? "yes" : "no"); + printf("\tRDSEED: %s\n", cpuinfo_has_x86_rdseed() ? "yes" : "no"); + printf("\tSHA: %s\n", cpuinfo_has_x86_sha() ? "yes" : "no"); printf("Profiling instructions:\n"); #if CPUINFO_ARCH_X86 - printf("\tRDTSC: %s\n", cpuinfo_has_x86_rdtsc() ? "yes" : "no"); + printf("\tRDTSC: %s\n", cpuinfo_has_x86_rdtsc() ? "yes" : "no"); #endif - printf("\tRDTSCP: %s\n", cpuinfo_has_x86_rdtscp() ? "yes" : "no"); - printf("\tMPX: %s\n", cpuinfo_has_x86_mpx() ? "yes" : "no"); - + printf("\tRDTSCP: %s\n", cpuinfo_has_x86_rdtscp() ? "yes" : "no"); + printf("\tMPX: %s\n", cpuinfo_has_x86_mpx() ? "yes" : "no"); printf("System instructions:\n"); - printf("\tCLWB: %s\n", cpuinfo_has_x86_clwb() ? "yes" : "no"); - printf("\tFXSAVE/FXSTOR: %s\n", cpuinfo_has_x86_fxsave() ? "yes" : "no"); - printf("\tXSAVE/XSTOR: %s\n", cpuinfo_has_x86_xsave() ? "yes" : "no"); + printf("\tCLWB: %s\n", cpuinfo_has_x86_clwb() ? "yes" : "no"); + printf("\tFXSAVE/FXSTOR: %s\n", cpuinfo_has_x86_fxsave() ? "yes" : "no"); + printf("\tXSAVE/XSTOR: %s\n", cpuinfo_has_x86_xsave() ? "yes" : "no"); #endif /* CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 */ #if CPUINFO_ARCH_ARM printf("Instruction sets:\n"); - printf("\tThumb: %s\n", cpuinfo_has_arm_thumb() ? "yes" : "no"); - printf("\tThumb 2: %s\n", cpuinfo_has_arm_thumb2() ? "yes" : "no"); - printf("\tARMv5E: %s\n", cpuinfo_has_arm_v5e() ? "yes" : "no"); - printf("\tARMv6: %s\n", cpuinfo_has_arm_v6() ? "yes" : "no"); - printf("\tARMv6-K: %s\n", cpuinfo_has_arm_v6k() ? "yes" : "no"); - printf("\tARMv7: %s\n", cpuinfo_has_arm_v7() ? "yes" : "no"); - printf("\tARMv7 MP: %s\n", cpuinfo_has_arm_v7mp() ? "yes" : "no"); - printf("\tARMv8: %s\n", cpuinfo_has_arm_v8() ? "yes" : "no"); - printf("\tIDIV: %s\n", cpuinfo_has_arm_idiv() ? "yes" : "no"); + printf("\tThumb: %s\n", cpuinfo_has_arm_thumb() ? "yes" : "no"); + printf("\tThumb 2: %s\n", cpuinfo_has_arm_thumb2() ? "yes" : "no"); + printf("\tARMv5E: %s\n", cpuinfo_has_arm_v5e() ? "yes" : "no"); + printf("\tARMv6: %s\n", cpuinfo_has_arm_v6() ? "yes" : "no"); + printf("\tARMv6-K: %s\n", cpuinfo_has_arm_v6k() ? "yes" : "no"); + printf("\tARMv7: %s\n", cpuinfo_has_arm_v7() ? "yes" : "no"); + printf("\tARMv7 MP: %s\n", cpuinfo_has_arm_v7mp() ? "yes" : "no"); + printf("\tARMv8: %s\n", cpuinfo_has_arm_v8() ? "yes" : "no"); + printf("\tIDIV: %s\n", cpuinfo_has_arm_idiv() ? "yes" : "no"); printf("Floating-Point support:\n"); - printf("\tVFPv2: %s\n", cpuinfo_has_arm_vfpv2() ? "yes" : "no"); - printf("\tVFPv3: %s\n", cpuinfo_has_arm_vfpv3() ? "yes" : "no"); - printf("\tVFPv3+D32: %s\n", cpuinfo_has_arm_vfpv3_d32() ? "yes" : "no"); - printf("\tVFPv3+FP16: %s\n", cpuinfo_has_arm_vfpv3_fp16() ? "yes" : "no"); - printf("\tVFPv3+FP16+D32: %s\n", cpuinfo_has_arm_vfpv3_fp16_d32() ? "yes" : "no"); - printf("\tVFPv4: %s\n", cpuinfo_has_arm_vfpv4() ? "yes" : "no"); - printf("\tVFPv4+D32: %s\n", cpuinfo_has_arm_vfpv4_d32() ? "yes" : "no"); - printf("\tVJCVT: %s\n", cpuinfo_has_arm_jscvt() ? "yes" : "no"); + printf("\tVFPv2: %s\n", cpuinfo_has_arm_vfpv2() ? "yes" : "no"); + printf("\tVFPv3: %s\n", cpuinfo_has_arm_vfpv3() ? "yes" : "no"); + printf("\tVFPv3+D32: %s\n", cpuinfo_has_arm_vfpv3_d32() ? "yes" : "no"); + printf("\tVFPv3+FP16: %s\n", cpuinfo_has_arm_vfpv3_fp16() ? "yes" : "no"); + printf("\tVFPv3+FP16+D32: %s\n", cpuinfo_has_arm_vfpv3_fp16_d32() ? "yes" : "no"); + printf("\tVFPv4: %s\n", cpuinfo_has_arm_vfpv4() ? "yes" : "no"); + printf("\tVFPv4+D32: %s\n", cpuinfo_has_arm_vfpv4_d32() ? "yes" : "no"); + printf("\tVJCVT: %s\n", cpuinfo_has_arm_jscvt() ? "yes" : "no"); printf("SIMD extensions:\n"); - printf("\tWMMX: %s\n", cpuinfo_has_arm_wmmx() ? "yes" : "no"); - printf("\tWMMX 2: %s\n", cpuinfo_has_arm_wmmx2() ? "yes" : "no"); - printf("\tNEON: %s\n", cpuinfo_has_arm_neon() ? "yes" : "no"); - printf("\tNEON-FP16: %s\n", cpuinfo_has_arm_neon_fp16() ? "yes" : "no"); - printf("\tNEON-FMA: %s\n", cpuinfo_has_arm_neon_fma() ? "yes" : "no"); - printf("\tNEON VQRDMLAH/VQRDMLSH: %s\n", cpuinfo_has_arm_neon_rdm() ? "yes" : "no"); - printf("\tNEON FP16 arithmetics: %s\n", cpuinfo_has_arm_neon_fp16_arith() ? "yes" : "no"); - printf("\tNEON complex: %s\n", cpuinfo_has_arm_fcma() ? "yes" : "no"); - printf("\tNEON VSDOT/VUDOT: %s\n", cpuinfo_has_arm_neon_dot() ? "yes" : "no"); - printf("\tNEON VFMLAL/VFMLSL: %s\n", cpuinfo_has_arm_fhm() ? "yes" : "no"); + printf("\tWMMX: %s\n", cpuinfo_has_arm_wmmx() ? "yes" : "no"); + printf("\tWMMX 2: %s\n", cpuinfo_has_arm_wmmx2() ? "yes" : "no"); + printf("\tNEON: %s\n", cpuinfo_has_arm_neon() ? "yes" : "no"); + printf("\tNEON-FP16: %s\n", cpuinfo_has_arm_neon_fp16() ? "yes" : "no"); + printf("\tNEON-FMA: %s\n", cpuinfo_has_arm_neon_fma() ? "yes" : "no"); + printf("\tNEON VQRDMLAH/VQRDMLSH: %s\n", cpuinfo_has_arm_neon_rdm() ? "yes" : "no"); + printf("\tNEON FP16 arithmetics: %s\n", cpuinfo_has_arm_neon_fp16_arith() ? "yes" : "no"); + printf("\tNEON complex: %s\n", cpuinfo_has_arm_fcma() ? "yes" : "no"); + printf("\tNEON VSDOT/VUDOT: %s\n", cpuinfo_has_arm_neon_dot() ? "yes" : "no"); + printf("\tNEON VFMLAL/VFMLSL: %s\n", cpuinfo_has_arm_fhm() ? "yes" : "no"); printf("Cryptography extensions:\n"); - printf("\tAES: %s\n", cpuinfo_has_arm_aes() ? "yes" : "no"); - printf("\tSHA1: %s\n", cpuinfo_has_arm_sha1() ? "yes" : "no"); - printf("\tSHA2: %s\n", cpuinfo_has_arm_sha2() ? "yes" : "no"); - printf("\tPMULL: %s\n", cpuinfo_has_arm_pmull() ? "yes" : "no"); - printf("\tCRC32: %s\n", cpuinfo_has_arm_crc32() ? "yes" : "no"); + printf("\tAES: %s\n", cpuinfo_has_arm_aes() ? "yes" : "no"); + printf("\tSHA1: %s\n", cpuinfo_has_arm_sha1() ? "yes" : "no"); + printf("\tSHA2: %s\n", cpuinfo_has_arm_sha2() ? "yes" : "no"); + printf("\tPMULL: %s\n", cpuinfo_has_arm_pmull() ? "yes" : "no"); + printf("\tCRC32: %s\n", cpuinfo_has_arm_crc32() ? "yes" : "no"); #endif /* CPUINFO_ARCH_ARM */ #if CPUINFO_ARCH_ARM64 printf("Instruction sets:\n"); - printf("\tARM v8.1 atomics: %s\n", cpuinfo_has_arm_atomics() ? "yes" : "no"); - printf("\tARM v8.1 SQRDMLxH: %s\n", cpuinfo_has_arm_neon_rdm() ? "yes" : "no"); - printf("\tARM v8.2 FP16 arithmetics: %s\n", cpuinfo_has_arm_fp16_arith() ? "yes" : "no"); - printf("\tARM v8.2 FHM: %s\n", cpuinfo_has_arm_fhm() ? "yes" : "no"); - printf("\tARM v8.2 BF16: %s\n", cpuinfo_has_arm_bf16() ? "yes" : "no"); - printf("\tARM v8.2 Int8 dot product: %s\n", cpuinfo_has_arm_neon_dot() ? "yes" : "no"); - printf("\tARM v8.2 Int8 matrix multiplication: %s\n", cpuinfo_has_arm_i8mm() ? "yes" : "no"); - printf("\tARM v8.3 JS conversion: %s\n", cpuinfo_has_arm_jscvt() ? "yes" : "no"); - printf("\tARM v8.3 complex: %s\n", cpuinfo_has_arm_fcma() ? "yes" : "no"); + printf("\tARM v8.1 atomics: %s\n", cpuinfo_has_arm_atomics() ? "yes" : "no"); + printf("\tARM v8.1 SQRDMLxH: %s\n", cpuinfo_has_arm_neon_rdm() ? "yes" : "no"); + printf("\tARM v8.2 FP16 arithmetics: %s\n", cpuinfo_has_arm_fp16_arith() ? "yes" : "no"); + printf("\tARM v8.2 FHM: %s\n", cpuinfo_has_arm_fhm() ? "yes" : "no"); + printf("\tARM v8.2 BF16: %s\n", cpuinfo_has_arm_bf16() ? "yes" : "no"); + printf("\tARM v8.2 Int8 dot product: %s\n", cpuinfo_has_arm_neon_dot() ? "yes" : "no"); + printf("\tARM v8.2 Int8 matrix multiplication: %s\n", cpuinfo_has_arm_i8mm() ? "yes" : "no"); + printf("\tARM v8.3 JS conversion: %s\n", cpuinfo_has_arm_jscvt() ? "yes" : "no"); + printf("\tARM v8.3 complex: %s\n", cpuinfo_has_arm_fcma() ? "yes" : "no"); printf("SIMD extensions:\n"); - printf("\tARM SVE: %s\n", cpuinfo_has_arm_sve() ? "yes" : "no"); - printf("\tARM SVE 2: %s\n", cpuinfo_has_arm_sve2() ? "yes" : "no"); + printf("\tARM SVE: %s\n", cpuinfo_has_arm_sve() ? "yes" : "no"); + printf("\tARM SVE 2: %s\n", cpuinfo_has_arm_sve2() ? "yes" : "no"); printf("Cryptography extensions:\n"); - printf("\tAES: %s\n", cpuinfo_has_arm_aes() ? "yes" : "no"); - printf("\tSHA1: %s\n", cpuinfo_has_arm_sha1() ? "yes" : "no"); - printf("\tSHA2: %s\n", cpuinfo_has_arm_sha2() ? "yes" : "no"); - printf("\tPMULL: %s\n", cpuinfo_has_arm_pmull() ? "yes" : "no"); - printf("\tCRC32: %s\n", cpuinfo_has_arm_crc32() ? "yes" : "no"); + printf("\tAES: %s\n", cpuinfo_has_arm_aes() ? "yes" : "no"); + printf("\tSHA1: %s\n", cpuinfo_has_arm_sha1() ? "yes" : "no"); + printf("\tSHA2: %s\n", cpuinfo_has_arm_sha2() ? "yes" : "no"); + printf("\tPMULL: %s\n", cpuinfo_has_arm_pmull() ? "yes" : "no"); + printf("\tCRC32: %s\n", cpuinfo_has_arm_crc32() ? "yes" : "no"); #endif #if CPUINFO_ARCH_RISCV32 || CPUINFO_ARCH_RISCV64 printf("Instruction sets:\n"); - printf("\tBase Integer: %s\n", cpuinfo_has_riscv_i() ? "yes" : "no"); - printf("\tInteger Multiply/Divide: %s\n", cpuinfo_has_riscv_m() ? "yes" : "no"); - printf("\tAtomics: %s\n", cpuinfo_has_riscv_a() ? "yes" : "no"); - printf("\tSingle-Precision Floating-Point: %s\n", cpuinfo_has_riscv_f() ? "yes" : "no"); - printf("\tDouble-Precision Floating-Point: %s\n", cpuinfo_has_riscv_d() ? "yes" : "no"); - printf("\tCompressed: %s\n", cpuinfo_has_riscv_c() ? "yes" : "no"); - printf("\tVector: %s\n", cpuinfo_has_riscv_v() ? "yes" : "no"); + printf("\tBase Integer: %s\n", cpuinfo_has_riscv_i() ? "yes" : "no"); + printf("\tInteger Multiply/Divide: %s\n", cpuinfo_has_riscv_m() ? "yes" : "no"); + printf("\tAtomics: %s\n", cpuinfo_has_riscv_a() ? "yes" : "no"); + printf("\tSingle-Precision Floating-Point: %s\n", cpuinfo_has_riscv_f() ? "yes" : "no"); + printf("\tDouble-Precision Floating-Point: %s\n", cpuinfo_has_riscv_d() ? "yes" : "no"); + printf("\tCompressed: %s\n", cpuinfo_has_riscv_c() ? "yes" : "no"); + printf("\tVector: %s\n", cpuinfo_has_riscv_v() ? "yes" : "no"); #endif - } From 050273682e78409dd76bdfea2a24e17f63f94977 Mon Sep 17 00:00:00 2001 From: Prashanth Swaminathan <40780424+prashanthswami@users.noreply.github.com> Date: Mon, 8 Jan 2024 13:05:58 -0800 Subject: [PATCH 50/60] Adjust log levels of /proc/cpuinfo parsing (#209) There are a few steps in our parsing logic where we skip lines that don't match the expectations of the /proc/cpuinfo node. Reduce the log level of these lines to 'debug', as these are not generally errors and are noisy on systems that have unique cpuinfo key-value pairs. When parsing logic encounters a higher-than-expected processor number, increase the level to warning, to indicate that an error may have occurred in the parsing step. This does not fully address #19 but resolves the underlying noise reported. --- src/arm/linux/cpuinfo.c | 8 ++++---- src/x86/linux/cpuinfo.c | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/arm/linux/cpuinfo.c b/src/arm/linux/cpuinfo.c index 3f477e77..2afd6cba 100644 --- a/src/arm/linux/cpuinfo.c +++ b/src/arm/linux/cpuinfo.c @@ -742,7 +742,7 @@ static bool parse_line( } /* Skip line if no ':' separator was found. */ if (separator == line_end) { - cpuinfo_log_info( + cpuinfo_log_debug( "Line %.*s in /proc/cpuinfo is ignored: key/value separator ':' not found", (int)(line_end - line_start), line_start); @@ -758,7 +758,7 @@ static bool parse_line( } /* Skip line if key contains nothing but spaces. */ if (key_end == line_start) { - cpuinfo_log_info( + cpuinfo_log_debug( "Line %.*s in /proc/cpuinfo is ignored: key contains only spaces", (int)(line_end - line_start), line_start); @@ -774,7 +774,7 @@ static bool parse_line( } /* Value part contains nothing but spaces. Skip line. */ if (value_start == line_end) { - cpuinfo_log_info( + cpuinfo_log_debug( "Line %.*s in /proc/cpuinfo is ignored: value contains only spaces", (int)(line_end - line_start), line_start); @@ -918,7 +918,7 @@ static bool parse_line( } else if (new_processor_index > processor_index + 1) { /* Strange, but common: skipped * processor $(processor_index + 1) */ - cpuinfo_log_info( + cpuinfo_log_warning( "unexpectedly high processor number %" PRIu32 " following processor %" PRIu32 " in /proc/cpuinfo", new_processor_index, diff --git a/src/x86/linux/cpuinfo.c b/src/x86/linux/cpuinfo.c index ff90884e..7df72aba 100644 --- a/src/x86/linux/cpuinfo.c +++ b/src/x86/linux/cpuinfo.c @@ -99,7 +99,7 @@ static bool parse_line( } /* Skip line if no ':' separator was found. */ if (separator == line_end) { - cpuinfo_log_info( + cpuinfo_log_debug( "Line %.*s in /proc/cpuinfo is ignored: key/value separator ':' not found", (int)(line_end - line_start), line_start); @@ -115,7 +115,7 @@ static bool parse_line( } /* Skip line if key contains nothing but spaces. */ if (key_end == line_start) { - cpuinfo_log_info( + cpuinfo_log_debug( "Line %.*s in /proc/cpuinfo is ignored: key contains only spaces", (int)(line_end - line_start), line_start); @@ -131,7 +131,7 @@ static bool parse_line( } /* Value part contains nothing but spaces. Skip line. */ if (value_start == line_end) { - cpuinfo_log_info( + cpuinfo_log_debug( "Line %.*s in /proc/cpuinfo is ignored: value contains only spaces", (int)(line_end - line_start), line_start); @@ -177,7 +177,7 @@ static bool parse_line( } else if (new_processor_index > processor_index + 1) { /* Strange, but common: skipped * processor $(processor_index + 1) */ - cpuinfo_log_info( + cpuinfo_log_warning( "unexpectedly high processor number %" PRIu32 " following processor %" PRIu32 " in /proc/cpuinfo", new_processor_index, From 76cc10d627add77922dc24521b332a055a4d6d77 Mon Sep 17 00:00:00 2001 From: Prashanth Swaminathan <40780424+prashanthswami@users.noreply.github.com> Date: Mon, 8 Jan 2024 16:59:57 -0800 Subject: [PATCH 51/60] Run Bazel build in Github Actions (#213) As some clients rely on the Bazel build, add a workflow to verify at least one Bazel target (linux-x86). Also, perform some minor cleanup to comments and target branches in our workflow files. --- .bazelversion | 1 - .github/workflows/build.yml | 1 - .github/workflows/build_bazel.yml | 21 +++++++++++++++++++++ scripts/local-bazel-build.sh | 18 ++++++++++++++++++ scripts/local-build.sh | 4 +++- 5 files changed, 42 insertions(+), 3 deletions(-) delete mode 100644 .bazelversion create mode 100644 .github/workflows/build_bazel.yml create mode 100755 scripts/local-bazel-build.sh diff --git a/.bazelversion b/.bazelversion deleted file mode 100644 index 0062ac97..00000000 --- a/.bazelversion +++ /dev/null @@ -1 +0,0 @@ -5.0.0 diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 06bce128..1407dc22 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -3,7 +3,6 @@ on: pull_request: push: branches: - - master - main permissions: diff --git a/.github/workflows/build_bazel.yml b/.github/workflows/build_bazel.yml new file mode 100644 index 00000000..84594726 --- /dev/null +++ b/.github/workflows/build_bazel.yml @@ -0,0 +1,21 @@ +name: Build using Bazel +on: + pull_request: + push: + branches: + - main + +permissions: + contents: read + +concurrency: + group: ${{ github.workflow }}-${{ github.head_ref || github.ref }} + cancel-in-progress: true +jobs: + bazel-linux-local: + runs-on: ubuntu-latest + timeout-minutes: 40 + steps: + - uses: actions/checkout@v2 + - name: Build + run: scripts/local-bazel-build.sh diff --git a/scripts/local-bazel-build.sh b/scripts/local-bazel-build.sh new file mode 100755 index 00000000..c2aeb322 --- /dev/null +++ b/scripts/local-bazel-build.sh @@ -0,0 +1,18 @@ +#!/usr/bin/env bash +# Copyright 2024 Google LLC + +set -e + +BAZEL_ARGS=() + +# Bazel-level configuration +# +# If editing these flags, make sure `local-build.sh` flags are updated. +BAZEL_ARGS+=("-c=\"opt\"") +BAZEL_ARGS+=("-copt=\"fpic\"") + +# User-specified Bazel arguments go last to allow overridding defaults +BAZEL_ARGS+=($@) + +# Build all targets +bazel build :all diff --git a/scripts/local-build.sh b/scripts/local-build.sh index 426a13bb..2be99e7b 100755 --- a/scripts/local-build.sh +++ b/scripts/local-build.sh @@ -13,6 +13,8 @@ mkdir -p build/local CMAKE_ARGS=() # CMake-level configuration +# +# If editing these flags, make sure `local-build-bazel.sh` flags are updated. CMAKE_ARGS+=("-DCMAKE_BUILD_TYPE=Release") CMAKE_ARGS+=("-DCMAKE_POSITION_INDEPENDENT_CODE=ON") @@ -22,7 +24,7 @@ then CMAKE_ARGS+=("-GNinja") fi -# Use-specified CMake arguments go last to allow overridding defaults +# User-specified CMake arguments go last to allow overridding defaults CMAKE_ARGS+=($@) cd build/local && cmake ../.. \ From 9321265af2078e98b91774a53bdccaea0f6665f8 Mon Sep 17 00:00:00 2001 From: Mark Ryan Date: Mon, 22 Jan 2024 18:43:46 +0100 Subject: [PATCH 52/60] Fix RISC-V Linux build again (#215) PR https://github.com/pytorch/cpuinfo/pull/204 broke the RISC-V build by including for a second time a header file that currently only exists in the RISC-V Android NDK. The header is not yet available in mainstream Linux distributions. The header in question, , is already included when building for Android at the top of riscv-hw.c so the second include is unnecessary and can be safely removed. --- src/riscv/linux/riscv-hw.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/riscv/linux/riscv-hw.c b/src/riscv/linux/riscv-hw.c index 243ca870..d737acad 100644 --- a/src/riscv/linux/riscv-hw.c +++ b/src/riscv/linux/riscv-hw.c @@ -14,7 +14,6 @@ #endif #include -#include #include #include From 434970b5d072d2f1e5e5fb44009884f278514588 Mon Sep 17 00:00:00 2001 From: Prashanth Swaminathan <40780424+prashanthswami@users.noreply.github.com> Date: Tue, 23 Jan 2024 06:53:09 -0800 Subject: [PATCH 53/60] Upgrade to warning when name is truncated (#216) Signal to users that the name field may not produce the expected string if the chipset name and revision exceeds the maximum size of the buffer. In practice, this is unlikely as the buffer size is reasonably high for a chipset name/revision. --- src/arm/linux/cpuinfo.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/arm/linux/cpuinfo.c b/src/arm/linux/cpuinfo.c index 2afd6cba..081d9aab 100644 --- a/src/arm/linux/cpuinfo.c +++ b/src/arm/linux/cpuinfo.c @@ -873,7 +873,7 @@ static bool parse_line( } else if (memcmp(line_start, "Hardware", key_length) == 0) { size_t value_length = value_end - value_start; if (value_length > CPUINFO_HARDWARE_VALUE_MAX) { - cpuinfo_log_info( + cpuinfo_log_warning( "length of Hardware value \"%.*s\" in /proc/cpuinfo exceeds limit (%d): truncating to the limit", (int)value_length, value_start, @@ -888,7 +888,7 @@ static bool parse_line( } else if (memcmp(line_start, "Revision", key_length) == 0) { size_t value_length = value_end - value_start; if (value_length > CPUINFO_REVISION_VALUE_MAX) { - cpuinfo_log_info( + cpuinfo_log_warning( "length of Revision value \"%.*s\" in /proc/cpuinfo exceeds limit (%d): truncating to the limit", (int)value_length, value_start, From 9484a6c590f831a30c1eec1311568b1a967a89dc Mon Sep 17 00:00:00 2001 From: Mark Ryan Date: Tue, 23 Jan 2024 15:59:49 +0100 Subject: [PATCH 54/60] ci: Add an Ubuntu:22.04 builder for RISC-V (#219) cpuinfo is built for riscv64 using a riscv64 container. binfmt_misc allows the riscv64 binaries in the container to be executed with QEMU. This is slower than cross compiling but as there's not that much code the build times are acceptable. It takes just under 6 minutes for the full riscv64 github action to run. We also have the option of running some of the built RISC-V binaries, e.g., unit tests, in the CI. It should be easy to expand the matrix to add CI for other architectures not natively supported by github actions. --- .github/workflows/build.yml | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 1407dc22..311f926b 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -93,3 +93,26 @@ jobs: working-directory: ${{ github.workspace }} env: ANDROID_NDK: ${{ steps.setup-ndk.outputs.ndk-path }} + cmake-linux-qemu: + runs-on: ubuntu-22.04 + timeout-minutes: 40 + strategy: + matrix: + build_props: + - [ + "cmake-linux-riscv64", + "riscv64/ubuntu:22.04" + ] + + name: ${{ matrix.build_props[0] }} + steps: + - uses: actions/checkout@v2 + - name: Setup QEMU + uses: docker/setup-qemu-action@v3.0.0 + - name: Build cpuinfo in ${{ matrix.build_props[1] }} + run: | + docker run -i -v $(pwd):/cpuinfo ${{ matrix.build_props[1] }} /bin/bash -c " + apt update && + apt install -y cmake git gcc g++ && + cd /cpuinfo && + scripts/local-build.sh" From 3990771460470b37ef5affd98c206d5af9f89b80 Mon Sep 17 00:00:00 2001 From: Frank Barchard Date: Fri, 23 Feb 2024 16:58:01 -0800 Subject: [PATCH 55/60] Add missing break to cpuinfo_x86_decode_cache_descriptor --- src/x86/cache/descriptor.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/x86/cache/descriptor.c b/src/x86/cache/descriptor.c index 8dc71ddc..93d855ae 100644 --- a/src/x86/cache/descriptor.c +++ b/src/x86/cache/descriptor.c @@ -240,6 +240,7 @@ void cpuinfo_x86_decode_cache_descriptor( .line_size = 64, .flags = CPUINFO_CACHE_INCLUSIVE, }; + break; case 0x21: /* * Intel ISA Reference: From fb08ae018ef8d8f71e3a2960c0982f90b688fe06 Mon Sep 17 00:00:00 2001 From: Vertexwahn Date: Fri, 15 Mar 2024 16:43:54 +0100 Subject: [PATCH 56/60] Bazel-support: Add MODUEL.bazel to support Bzlmod (#229) This PR adds a `MODULE.bazel` file. This is needed for [Bzlmod](https://bazel.build/external/mod-command) support of Bazel. In the long term this will replace the `WORKSPACE.bazel` file. In the meantime, both files are needed. --- MODULE.bazel | 1 + WORKSPACE.bazel | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) create mode 100644 MODULE.bazel diff --git a/MODULE.bazel b/MODULE.bazel new file mode 100644 index 00000000..961ad95a --- /dev/null +++ b/MODULE.bazel @@ -0,0 +1 @@ +module(name = "cpuinfo") diff --git a/WORKSPACE.bazel b/WORKSPACE.bazel index 24874c73..ea537780 100644 --- a/WORKSPACE.bazel +++ b/WORKSPACE.bazel @@ -1 +1 @@ -workspace(name = "org_pytorch_cpuinfo") \ No newline at end of file +workspace(name = "org_pytorch_cpuinfo") From 6543fec09b2f04ac4a666882998b534afc9c1349 Mon Sep 17 00:00:00 2001 From: Everton Constantino Date: Sat, 16 Mar 2024 21:45:01 -0300 Subject: [PATCH 57/60] Include support for Windows on Arm on BUILD.bazel along with proper Volterra detection (#220) This MR includes support for building with Bazel on cpu `arm64_windows`, I also tried this on my Volterra Windows Dev Kit and noticed that the core string seems different from what the current source code defines. I don't know if this is because my hardware is a bit different or not. I ran the tests with the following results ``` [==========] Running 132 tests from 28 test suites. [----------] Global test environment set-up. [----------] 1 test from PROCESSORS_COUNT [ RUN ] PROCESSORS_COUNT.non_zero [ OK ] PROCESSORS_COUNT.non_zero (0 ms) [----------] 1 test from PROCESSORS_COUNT (0 ms total) [----------] 1 test from PROCESSORS [ RUN ] PROCESSORS.non_null [ OK ] PROCESSORS.non_null (0 ms) [----------] 1 test from PROCESSORS (0 ms total) [----------] 13 tests from PROCESSOR [ RUN ] PROCESSOR.non_null [ OK ] PROCESSOR.non_null (0 ms) [ RUN ] PROCESSOR.valid_smt_id [ OK ] PROCESSOR.valid_smt_id (0 ms) [ RUN ] PROCESSOR.valid_core [ OK ] PROCESSOR.valid_core (0 ms) [ RUN ] PROCESSOR.consistent_core [ OK ] PROCESSOR.consistent_core (0 ms) [ RUN ] PROCESSOR.valid_cluster [ OK ] PROCESSOR.valid_cluster (0 ms) [ RUN ] PROCESSOR.consistent_cluster [ OK ] PROCESSOR.consistent_cluster (0 ms) [ RUN ] PROCESSOR.valid_package [ OK ] PROCESSOR.valid_package (0 ms) [ RUN ] PROCESSOR.consistent_package [ OK ] PROCESSOR.consistent_package (0 ms) [ RUN ] PROCESSOR.consistent_l1i [ OK ] PROCESSOR.consistent_l1i (0 ms) [ RUN ] PROCESSOR.consistent_l1d [ OK ] PROCESSOR.consistent_l1d (0 ms) [ RUN ] PROCESSOR.consistent_l2 [ OK ] PROCESSOR.consistent_l2 (0 ms) [ RUN ] PROCESSOR.consistent_l3 [ OK ] PROCESSOR.consistent_l3 (0 ms) [ RUN ] PROCESSOR.consistent_l4 [ OK ] PROCESSOR.consistent_l4 (0 ms) [----------] 13 tests from PROCESSOR (7 ms total) [----------] 1 test from CORES_COUNT [ RUN ] CORES_COUNT.within_bounds [ OK ] CORES_COUNT.within_bounds (0 ms) [----------] 1 test from CORES_COUNT (0 ms total) [----------] 1 test from CORES [ RUN ] CORES.non_null [ OK ] CORES.non_null (0 ms) [----------] 1 test from CORES (0 ms total) [----------] 10 tests from CORE [ RUN ] CORE.non_null [ OK ] CORE.non_null (0 ms) [ RUN ] CORE.non_zero_processors [ OK ] CORE.non_zero_processors (0 ms) [ RUN ] CORE.consistent_processors [ OK ] CORE.consistent_processors (0 ms) [ RUN ] CORE.valid_core_id [ OK ] CORE.valid_core_id (0 ms) [ RUN ] CORE.valid_cluster [ OK ] CORE.valid_cluster (0 ms) [ RUN ] CORE.consistent_cluster [ OK ] CORE.consistent_cluster (0 ms) [ RUN ] CORE.valid_package [ OK ] CORE.valid_package (0 ms) [ RUN ] CORE.consistent_package [ OK ] CORE.consistent_package (0 ms) [ RUN ] CORE.known_vendor [ OK ] CORE.known_vendor (0 ms) [ RUN ] CORE.known_uarch [ OK ] CORE.known_uarch (0 ms) [----------] 10 tests from CORE (5 ms total) [----------] 1 test from CLUSTERS_COUNT [ RUN ] CLUSTERS_COUNT.within_bounds [ OK ] CLUSTERS_COUNT.within_bounds (0 ms) [----------] 1 test from CLUSTERS_COUNT (0 ms total) [----------] 1 test from CLUSTERS [ RUN ] CLUSTERS.non_null [ OK ] CLUSTERS.non_null (0 ms) [----------] 1 test from CLUSTERS (0 ms total) [----------] 14 tests from CLUSTER [ RUN ] CLUSTER.non_null [ OK ] CLUSTER.non_null (0 ms) [ RUN ] CLUSTER.non_zero_processors [ OK ] CLUSTER.non_zero_processors (0 ms) [ RUN ] CLUSTER.valid_processors [ OK ] CLUSTER.valid_processors (0 ms) [ RUN ] CLUSTER.consistent_processors [ OK ] CLUSTER.consistent_processors (0 ms) [ RUN ] CLUSTER.non_zero_cores [ OK ] CLUSTER.non_zero_cores (0 ms) [ RUN ] CLUSTER.valid_cores [ OK ] CLUSTER.valid_cores (0 ms) [ RUN ] CLUSTER.consistent_cores [ OK ] CLUSTER.consistent_cores (0 ms) [ RUN ] CLUSTER.valid_cluster_id [ OK ] CLUSTER.valid_cluster_id (0 ms) [ RUN ] CLUSTER.valid_package [ OK ] CLUSTER.valid_package (0 ms) [ RUN ] CLUSTER.consistent_package [ OK ] CLUSTER.consistent_package (0 ms) [ RUN ] CLUSTER.consistent_vendor [ OK ] CLUSTER.consistent_vendor (0 ms) [ RUN ] CLUSTER.consistent_uarch [ OK ] CLUSTER.consistent_uarch (0 ms) [ RUN ] CLUSTER.consistent_midr [ OK ] CLUSTER.consistent_midr (0 ms) [ RUN ] CLUSTER.consistent_frequency [ OK ] CLUSTER.consistent_frequency (0 ms) [----------] 14 tests from CLUSTER (7 ms total) [----------] 1 test from PACKAGES_COUNT [ RUN ] PACKAGES_COUNT.within_bounds [ OK ] PACKAGES_COUNT.within_bounds (0 ms) [----------] 1 test from PACKAGES_COUNT (0 ms total) [----------] 1 test from PACKAGES [ RUN ] PACKAGES.non_null [ OK ] PACKAGES.non_null (0 ms) [----------] 1 test from PACKAGES (0 ms total) [----------] 10 tests from PACKAGE [ RUN ] PACKAGE.non_null [ OK ] PACKAGE.non_null (0 ms) [ RUN ] PACKAGE.non_zero_processors [ OK ] PACKAGE.non_zero_processors (0 ms) [ RUN ] PACKAGE.valid_processors [ OK ] PACKAGE.valid_processors (0 ms) [ RUN ] PACKAGE.consistent_processors [ OK ] PACKAGE.consistent_processors (0 ms) [ RUN ] PACKAGE.non_zero_cores [ OK ] PACKAGE.non_zero_cores (0 ms) [ RUN ] PACKAGE.valid_cores [ OK ] PACKAGE.valid_cores (0 ms) [ RUN ] PACKAGE.consistent_cores [ OK ] PACKAGE.consistent_cores (0 ms) [ RUN ] PACKAGE.non_zero_clusters [ OK ] PACKAGE.non_zero_clusters (0 ms) [ RUN ] PACKAGE.valid_clusters [ OK ] PACKAGE.valid_clusters (0 ms) [ RUN ] PACKAGE.consistent_cluster [ OK ] PACKAGE.consistent_cluster (0 ms) [----------] 10 tests from PACKAGE (5 ms total) [----------] 1 test from UARCHS_COUNT [ RUN ] UARCHS_COUNT.within_bounds [ OK ] UARCHS_COUNT.within_bounds (0 ms) [----------] 1 test from UARCHS_COUNT (0 ms total) [----------] 1 test from UARCHS [ RUN ] UARCHS.non_null [ OK ] UARCHS.non_null (0 ms) [----------] 1 test from UARCHS (0 ms total) [----------] 5 tests from UARCH [ RUN ] UARCH.non_null [ OK ] UARCH.non_null (0 ms) [ RUN ] UARCH.non_zero_processors [ OK ] UARCH.non_zero_processors (0 ms) [ RUN ] UARCH.valid_processors [ OK ] UARCH.valid_processors (0 ms) [ RUN ] UARCH.non_zero_cores [ OK ] UARCH.non_zero_cores (0 ms) [ RUN ] UARCH.valid_cores [ OK ] UARCH.valid_cores (0 ms) [----------] 5 tests from UARCH (2 ms total) [----------] 1 test from L1I_CACHES_COUNT [ RUN ] L1I_CACHES_COUNT.within_bounds [ OK ] L1I_CACHES_COUNT.within_bounds (0 ms) [----------] 1 test from L1I_CACHES_COUNT (0 ms total) [----------] 1 test from L1I_CACHES [ RUN ] L1I_CACHES.non_null [ OK ] L1I_CACHES.non_null (0 ms) [----------] 1 test from L1I_CACHES (0 ms total) [----------] 13 tests from L1I_CACHE [ RUN ] L1I_CACHE.non_null [ OK ] L1I_CACHE.non_null (0 ms) [ RUN ] L1I_CACHE.non_zero_size [ OK ] L1I_CACHE.non_zero_size (0 ms) [ RUN ] L1I_CACHE.valid_size [ OK ] L1I_CACHE.valid_size (0 ms) [ RUN ] L1I_CACHE.non_zero_associativity [ OK ] L1I_CACHE.non_zero_associativity (0 ms) [ RUN ] L1I_CACHE.non_zero_partitions [ OK ] L1I_CACHE.non_zero_partitions (0 ms) [ RUN ] L1I_CACHE.non_zero_line_size [ OK ] L1I_CACHE.non_zero_line_size (0 ms) [ RUN ] L1I_CACHE.power_of_2_line_size [ OK ] L1I_CACHE.power_of_2_line_size (0 ms) [ RUN ] L1I_CACHE.reasonable_line_size [ OK ] L1I_CACHE.reasonable_line_size (0 ms) [ RUN ] L1I_CACHE.valid_flags [ OK ] L1I_CACHE.valid_flags (0 ms) [ RUN ] L1I_CACHE.non_inclusive [ OK ] L1I_CACHE.non_inclusive (0 ms) [ RUN ] L1I_CACHE.non_zero_processors [ OK ] L1I_CACHE.non_zero_processors (0 ms) [ RUN ] L1I_CACHE.valid_processors [ OK ] L1I_CACHE.valid_processors (0 ms) [ RUN ] L1I_CACHE.consistent_processors [ OK ] L1I_CACHE.consistent_processors (0 ms) [----------] 13 tests from L1I_CACHE (7 ms total) [----------] 1 test from L1D_CACHES_COUNT [ RUN ] L1D_CACHES_COUNT.within_bounds [ OK ] L1D_CACHES_COUNT.within_bounds (0 ms) [----------] 1 test from L1D_CACHES_COUNT (0 ms total) [----------] 1 test from L1D_CACHES [ RUN ] L1D_CACHES.non_null [ OK ] L1D_CACHES.non_null (0 ms) [----------] 1 test from L1D_CACHES (0 ms total) [----------] 13 tests from L1D_CACHE [ RUN ] L1D_CACHE.non_null [ OK ] L1D_CACHE.non_null (0 ms) [ RUN ] L1D_CACHE.non_zero_size [ OK ] L1D_CACHE.non_zero_size (0 ms) [ RUN ] L1D_CACHE.valid_size [ OK ] L1D_CACHE.valid_size (0 ms) [ RUN ] L1D_CACHE.non_zero_associativity [ OK ] L1D_CACHE.non_zero_associativity (0 ms) [ RUN ] L1D_CACHE.non_zero_partitions [ OK ] L1D_CACHE.non_zero_partitions (0 ms) [ RUN ] L1D_CACHE.non_zero_line_size [ OK ] L1D_CACHE.non_zero_line_size (0 ms) [ RUN ] L1D_CACHE.power_of_2_line_size [ OK ] L1D_CACHE.power_of_2_line_size (0 ms) [ RUN ] L1D_CACHE.reasonable_line_size [ OK ] L1D_CACHE.reasonable_line_size (0 ms) [ RUN ] L1D_CACHE.valid_flags [ OK ] L1D_CACHE.valid_flags (0 ms) [ RUN ] L1D_CACHE.non_inclusive [ OK ] L1D_CACHE.non_inclusive (0 ms) [ RUN ] L1D_CACHE.non_zero_processors [ OK ] L1D_CACHE.non_zero_processors (0 ms) [ RUN ] L1D_CACHE.valid_processors [ OK ] L1D_CACHE.valid_processors (0 ms) [ RUN ] L1D_CACHE.consistent_processors [ OK ] L1D_CACHE.consistent_processors (0 ms) [----------] 13 tests from L1D_CACHE (7 ms total) [----------] 1 test from L2_CACHES_COUNT [ RUN ] L2_CACHES_COUNT.within_bounds [ OK ] L2_CACHES_COUNT.within_bounds (0 ms) [----------] 1 test from L2_CACHES_COUNT (0 ms total) [----------] 1 test from L2_CACHES [ RUN ] L2_CACHES.non_null [ OK ] L2_CACHES.non_null (0 ms) [----------] 1 test from L2_CACHES (0 ms total) [----------] 12 tests from L2_CACHE [ RUN ] L2_CACHE.non_null [ OK ] L2_CACHE.non_null (0 ms) [ RUN ] L2_CACHE.non_zero_size [ OK ] L2_CACHE.non_zero_size (0 ms) [ RUN ] L2_CACHE.valid_size [ OK ] L2_CACHE.valid_size (0 ms) [ RUN ] L2_CACHE.non_zero_associativity [ OK ] L2_CACHE.non_zero_associativity (0 ms) [ RUN ] L2_CACHE.non_zero_partitions [ OK ] L2_CACHE.non_zero_partitions (0 ms) [ RUN ] L2_CACHE.non_zero_line_size [ OK ] L2_CACHE.non_zero_line_size (0 ms) [ RUN ] L2_CACHE.power_of_2_line_size [ OK ] L2_CACHE.power_of_2_line_size (0 ms) [ RUN ] L2_CACHE.reasonable_line_size [ OK ] L2_CACHE.reasonable_line_size (0 ms) [ RUN ] L2_CACHE.valid_flags [ OK ] L2_CACHE.valid_flags (0 ms) [ RUN ] L2_CACHE.non_zero_processors [ OK ] L2_CACHE.non_zero_processors (0 ms) [ RUN ] L2_CACHE.valid_processors [ OK ] L2_CACHE.valid_processors (0 ms) [ RUN ] L2_CACHE.consistent_processors [ OK ] L2_CACHE.consistent_processors (0 ms) [----------] 12 tests from L2_CACHE (6 ms total) [----------] 1 test from L3_CACHES_COUNT [ RUN ] L3_CACHES_COUNT.within_bounds [ OK ] L3_CACHES_COUNT.within_bounds (0 ms) [----------] 1 test from L3_CACHES_COUNT (0 ms total) [----------] 12 tests from L3_CACHE [ RUN ] L3_CACHE.non_null [ OK ] L3_CACHE.non_null (0 ms) [ RUN ] L3_CACHE.non_zero_size [ OK ] L3_CACHE.non_zero_size (0 ms) [ RUN ] L3_CACHE.valid_size [ OK ] L3_CACHE.valid_size (0 ms) [ RUN ] L3_CACHE.non_zero_associativity [ OK ] L3_CACHE.non_zero_associativity (0 ms) [ RUN ] L3_CACHE.non_zero_partitions [ OK ] L3_CACHE.non_zero_partitions (0 ms) [ RUN ] L3_CACHE.non_zero_line_size [ OK ] L3_CACHE.non_zero_line_size (0 ms) [ RUN ] L3_CACHE.power_of_2_line_size [ OK ] L3_CACHE.power_of_2_line_size (0 ms) [ RUN ] L3_CACHE.reasonable_line_size [ OK ] L3_CACHE.reasonable_line_size (0 ms) [ RUN ] L3_CACHE.valid_flags [ OK ] L3_CACHE.valid_flags (0 ms) [ RUN ] L3_CACHE.non_zero_processors [ OK ] L3_CACHE.non_zero_processors (0 ms) [ RUN ] L3_CACHE.valid_processors [ OK ] L3_CACHE.valid_processors (0 ms) [ RUN ] L3_CACHE.consistent_processors [ OK ] L3_CACHE.consistent_processors (0 ms) [----------] 12 tests from L3_CACHE (6 ms total) [----------] 1 test from L4_CACHES_COUNT [ RUN ] L4_CACHES_COUNT.within_bounds [ OK ] L4_CACHES_COUNT.within_bounds (0 ms) [----------] 1 test from L4_CACHES_COUNT (0 ms total) [----------] 12 tests from L4_CACHE [ RUN ] L4_CACHE.non_null [ OK ] L4_CACHE.non_null (0 ms) [ RUN ] L4_CACHE.non_zero_size [ OK ] L4_CACHE.non_zero_size (0 ms) [ RUN ] L4_CACHE.valid_size [ OK ] L4_CACHE.valid_size (0 ms) [ RUN ] L4_CACHE.non_zero_associativity [ OK ] L4_CACHE.non_zero_associativity (0 ms) [ RUN ] L4_CACHE.non_zero_partitions [ OK ] L4_CACHE.non_zero_partitions (0 ms) [ RUN ] L4_CACHE.non_zero_line_size [ OK ] L4_CACHE.non_zero_line_size (0 ms) [ RUN ] L4_CACHE.power_of_2_line_size [ OK ] L4_CACHE.power_of_2_line_size (0 ms) [ RUN ] L4_CACHE.reasonable_line_size [ OK ] L4_CACHE.reasonable_line_size (0 ms) [ RUN ] L4_CACHE.valid_flags [ OK ] L4_CACHE.valid_flags (0 ms) [ RUN ] L4_CACHE.non_zero_processors [ OK ] L4_CACHE.non_zero_processors (0 ms) [ RUN ] L4_CACHE.valid_processors [ OK ] L4_CACHE.valid_processors (0 ms) [ RUN ] L4_CACHE.consistent_processors [ OK ] L4_CACHE.consistent_processors (0 ms) [----------] 12 tests from L4_CACHE (6 ms total) [----------] Global test environment tear-down [==========] 132 tests from 28 test suites ran. (93 ms total) [ PASSED ] 132 tests. ``` with `cpu-info.exe` returning ``` Packages: 0: Snapdragon (TM) 8cx Gen 3 Microarchitectures: 4x Cortex-A78 4x Cortex-X1 Cores: 0: 1 processor (0), ARM Cortex-A78 1: 1 processor (1), ARM Cortex-A78 2: 1 processor (2), ARM Cortex-A78 3: 1 processor (3), ARM Cortex-A78 4: 1 processor (4), ARM Cortex-X1 5: 1 processor (5), ARM Cortex-X1 6: 1 processor (6), ARM Cortex-X1 7: 1 processor (7), ARM Cortex-X1 Logical processors: 0 1 2 3 4 5 6 7 ``` and `isa-info.exe` returning ``` Instruction sets: ARM v8.1 atomics: yes ARM v8.1 SQRDMLxH: yes ARM v8.2 FP16 arithmetics: yes ARM v8.2 FHM: no ARM v8.2 BF16: no ARM v8.2 Int8 dot product: yes ARM v8.2 Int8 matrix multiplication: no ARM v8.3 JS conversion: no ARM v8.3 complex: no SIMD extensions: ARM SVE: no ARM SVE 2: no Cryptography extensions: AES: yes SHA1: yes SHA2: yes PMULL: yes CRC32: yes ``` --- BUILD.bazel | 12 ++++++++++++ src/arm/windows/init.c | 9 +++++++++ 2 files changed, 21 insertions(+) diff --git a/BUILD.bazel b/BUILD.bazel index dc9634e7..4e3ea999 100644 --- a/BUILD.bazel +++ b/BUILD.bazel @@ -99,6 +99,11 @@ WINDOWS_X86_SRCS = [ "src/x86/windows/init.c", ] +WINDOWS_ARM_SRCS = [ + "src/arm/windows/init-by-logical-sys-info.c", + "src/arm/windows/init.c", +] + MACH_X86_SRCS = [ "src/x86/mach/init.c", ] @@ -128,6 +133,7 @@ cc_library( ":macos_x86_64_legacy": COMMON_SRCS + X86_SRCS + MACH_SRCS + MACH_X86_SRCS, ":macos_arm64": COMMON_SRCS + MACH_SRCS + MACH_ARM_SRCS, ":windows_x86_64": COMMON_SRCS + X86_SRCS + WINDOWS_X86_SRCS, + ":windows_arm64": COMMON_SRCS + ARM_SRCS + WINDOWS_ARM_SRCS, ":android_armv7": COMMON_SRCS + ARM_SRCS + LINUX_SRCS + LINUX_ARM32_SRCS + ANDROID_ARM_SRCS, ":android_arm64": COMMON_SRCS + ARM_SRCS + LINUX_SRCS + LINUX_ARM64_SRCS + ANDROID_ARM_SRCS, ":android_x86": COMMON_SRCS + X86_SRCS + LINUX_SRCS + LINUX_X86_SRCS, @@ -149,6 +155,7 @@ cc_library( }), copts = select({ ":windows_x86_64": [], + ":windows_arm64": [], "//conditions:default": C99OPTS, }) + [ "-Iexternal/cpuinfo/include", @@ -281,6 +288,11 @@ config_setting( values = {"cpu": "x64_windows"}, ) +config_setting( + name = "windows_arm64", + values = {"cpu": "arm64_windows"}, +) + config_setting( name = "android_armv7", values = { diff --git a/src/arm/windows/init.c b/src/arm/windows/init.c index 79828e6e..e7b80b42 100644 --- a/src/arm/windows/init.c +++ b/src/arm/windows/init.c @@ -43,6 +43,15 @@ static struct woa_chip_info woa_chips[] = { 2420000000, }, {cpuinfo_vendor_arm, cpuinfo_uarch_cortex_a76, 3150000000}}}, + /* Snapdragon (TM) 8cx Gen 3 @ 3.0 GHz */ + {L"Snapdragon (TM) 8cx Gen 3", + woa_chip_name_microsoft_sq_3, + {{ + cpuinfo_vendor_arm, + cpuinfo_uarch_cortex_a78, + 2420000000, + }, + {cpuinfo_vendor_arm, cpuinfo_uarch_cortex_x1, 3000000000}}}, /* Microsoft Windows Dev Kit 2023 */ {L"Snapdragon Compute Platform", woa_chip_name_microsoft_sq_3, From f42f5eaf0bbeabd3a1153651cd2a5989faac4f58 Mon Sep 17 00:00:00 2001 From: Ma Mingfei Date: Thu, 28 Mar 2024 14:03:24 +0800 Subject: [PATCH 58/60] Add detection for Intel Advanced Matrix Extensions (AMX) instructions (#231) Tested using intel SDE: https://www.intel.com/content/www/us/en/download/684897/intel-software-development-emulator.html Test scripts: ``` bash scripts/local-build.sh ISAS=() OPTIONS=() PLATFORMS=() OPTIONS+=(-quark); PLATFORMS+=("Quark") OPTIONS+=(-p4); PLATFORMS+=("Pentium4") OPTIONS+=(-p4p); PLATFORMS+=("Pentium4 Prescott") OPTIONS+=(-mrm); PLATFORMS+=("Merom") OPTIONS+=(-pnr); PLATFORMS+=("Penryn") OPTIONS+=(-nhm); PLATFORMS+=("Nehalem") OPTIONS+=(-wsm); PLATFORMS+=("Westmere") OPTIONS+=(-snb); PLATFORMS+=("Sandy Bridge") OPTIONS+=(-ivb); PLATFORMS+=("Ivy Bridge") OPTIONS+=(-hsw); PLATFORMS+=("Haswell") OPTIONS+=(-bdw); PLATFORMS+=("Broadwell") OPTIONS+=(-slt); PLATFORMS+=("Saltwell") OPTIONS+=(-slm); PLATFORMS+=("Silvermont") OPTIONS+=(-glm); PLATFORMS+=("Goldmont") OPTIONS+=(-glp); PLATFORMS+=("Goldmont Plus") OPTIONS+=(-tnt); PLATFORMS+=("Tremont") OPTIONS+=(-snr); PLATFORMS+=("Snow Ridge") OPTIONS+=(-skl); PLATFORMS+=("Skylake") OPTIONS+=(-cnl); PLATFORMS+=("Cannon Lake") OPTIONS+=(-icl); PLATFORMS+=("Ice Lake") OPTIONS+=(-skx); PLATFORMS+=("Skylake server") OPTIONS+=(-clx); PLATFORMS+=("Cascade Lake") OPTIONS+=(-cpx); PLATFORMS+=("Cooper Lake") OPTIONS+=(-icx); PLATFORMS+=("Ice Lake server") OPTIONS+=(-knl); PLATFORMS+=("Knights landing") OPTIONS+=(-knm); PLATFORMS+=("Knights mill") OPTIONS+=(-tgl); PLATFORMS+=("Tiger Lake") OPTIONS+=(-adl); PLATFORMS+=("Alder Lake") OPTIONS+=(-mtl); PLATFORMS+=("Meteor Lake") OPTIONS+=(-rpl); PLATFORMS+=("Raptor Lake") OPTIONS+=(-spr); PLATFORMS+=("Sapphire Rapids") OPTIONS+=(-gnr); PLATFORMS+=("Granite Rapids") OPTIONS+=(-gnr256); PLATFORMS+=("Granite Rapids (AVX10.1 / 256VL)") OPTIONS+=(-srf); PLATFORMS+=("Sierra Forest") OPTIONS+=(-arl); PLATFORMS+=("Arrow Lake") OPTIONS+=(-lnl); PLATFORMS+=("Lunar Lake") OPTIONS+=(-future); PLATFORMS+=("Future chip") ISAS+=("AMXBF16") ISAS+=("AMXTILE") ISAS+=("AMXINT8") ISAS+=("AMXFP16") SDE_BIN="/home/mingfeim/packages/sde-external-9.33.0-2024-01-07-lin/sde" for I in "${!PLATFORMS[@]}"; do echo "${PLATFORMS["${I}"]}" for J in "${!ISAS[@]}"; do "${SDE_BIN}" "${OPTIONS[$I]}" -- ./build/local/isa-info | grep ${ISAS[$J]} done done ``` Results: ``` Quark SDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM or by the input cpuid definition file SDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM or by the input cpuid definition file SDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM or by the input cpuid definition file SDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM or by the input cpuid definition file Pentium4 SDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM4 or by the input cpuid definition file SDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM4 or by the input cpuid definition file SDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM4 or by the input cpuid definition file SDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM4 or by the input cpuid definition file Pentium4 Prescott AMXBF16: no AMXTILE: no AMXINT8: no AMXFP16: no Merom AMXBF16: no AMXTILE: no AMXINT8: no AMXFP16: no Penryn AMXBF16: no AMXTILE: no AMXINT8: no AMXFP16: no Nehalem AMXBF16: no AMXTILE: no AMXINT8: no AMXFP16: no Westmere AMXBF16: no AMXTILE: no AMXINT8: no AMXFP16: no Sandy Bridge AMXBF16: no AMXTILE: no AMXINT8: no AMXFP16: no Ivy Bridge AMXBF16: no AMXTILE: no AMXINT8: no AMXFP16: no Haswell AMXBF16: no AMXTILE: no AMXINT8: no AMXFP16: no Broadwell AMXBF16: no AMXTILE: no AMXINT8: no AMXFP16: no Saltwell AMXBF16: no AMXTILE: no AMXINT8: no AMXFP16: no Silvermont AMXBF16: no AMXTILE: no AMXINT8: no AMXFP16: no Goldmont AMXBF16: no AMXTILE: no AMXINT8: no AMXFP16: no Goldmont Plus AMXBF16: no AMXTILE: no AMXINT8: no AMXFP16: no Tremont AMXBF16: no AMXTILE: no AMXINT8: no AMXFP16: no Snow Ridge AMXBF16: no AMXTILE: no AMXINT8: no AMXFP16: no Skylake AMXBF16: no AMXTILE: no AMXINT8: no AMXFP16: no Cannon Lake AMXBF16: no AMXTILE: no AMXINT8: no AMXFP16: no Ice Lake AMXBF16: no AMXTILE: no AMXINT8: no AMXFP16: no Skylake server AMXBF16: no AMXTILE: no AMXINT8: no AMXFP16: no Cascade Lake AMXBF16: no AMXTILE: no AMXINT8: no AMXFP16: no Cooper Lake AMXBF16: no AMXTILE: no AMXINT8: no AMXFP16: no Ice Lake server AMXBF16: no AMXTILE: no AMXINT8: no AMXFP16: no Knights landing AMXBF16: no AMXTILE: no AMXINT8: no AMXFP16: no Knights mill AMXBF16: no AMXTILE: no AMXINT8: no AMXFP16: no Tiger Lake AMXBF16: no AMXTILE: no AMXINT8: no AMXFP16: no Alder Lake AMXBF16: no AMXTILE: no AMXINT8: no AMXFP16: no Meteor Lake AMXBF16: no AMXTILE: no AMXINT8: no AMXFP16: no Raptor Lake AMXBF16: no AMXTILE: no AMXINT8: no AMXFP16: no Sapphire Rapids AMXBF16: yes AMXTILE: yes AMXINT8: yes AMXFP16: no Granite Rapids AMXBF16: yes AMXTILE: yes AMXINT8: yes AMXFP16: yes Granite Rapids (AVX10.1 / 256VL) AMXBF16: yes AMXTILE: yes AMXINT8: yes AMXFP16: yes Sierra Forest AMXBF16: no AMXTILE: no AMXINT8: no AMXFP16: no Arrow Lake AMXBF16: no AMXTILE: no AMXINT8: no AMXFP16: no Lunar Lake AMXBF16: no AMXTILE: no AMXINT8: no AMXFP16: no Future chip AMXBF16: yes AMXTILE: yes AMXINT8: yes AMXFP16: yes ``` --- include/cpuinfo.h | 56 +++++++++++++++++++++++++++++++++++++++++++++++ src/x86/isa.c | 24 ++++++++++++++++++++ tools/isa-info.c | 4 ++++ 3 files changed, 84 insertions(+) diff --git a/include/cpuinfo.h b/include/cpuinfo.h index 275c83f9..14fc928a 100644 --- a/include/cpuinfo.h +++ b/include/cpuinfo.h @@ -812,6 +812,10 @@ struct cpuinfo_x86_isa { bool avx512vp2intersect; bool avx512_4vnniw; bool avx512_4fmaps; + bool amx_bf16; + bool amx_tile; + bool amx_int8; + bool amx_fp16; bool hle; bool rtm; bool xtest; @@ -1328,6 +1332,58 @@ static inline bool cpuinfo_has_x86_avx512_4fmaps(void) { #endif } +/* [NOTE] Intel Advanced Matrix Extensions (AMX) detection + * + * I. AMX is a new extensions to the x86 ISA to work on matrices, consists of + * 1) 2-dimentional registers (tiles), hold sub-matrices from larger matrices in memory + * 2) Accelerator called Tile Matrix Multiply (TMUL), contains instructions operating on tiles + * + * II. Platforms that supports AMX: + * +-----------------+-----+----------+----------+----------+----------+ + * | Platforms | Gen | amx-bf16 | amx-tile | amx-int8 | amx-fp16 | + * +-----------------+-----+----------+----------+----------+----------+ + * | Sapphire Rapids | 4th | YES | YES | YES | NO | + * +-----------------+-----+----------+----------+----------+----------+ + * | Emerald Rapids | 5th | YES | YES | YES | NO | + * +-----------------+-----+----------+----------+----------+----------+ + * | Granite Rapids | 6th | YES | YES | YES | YES | + * +-----------------+-----+----------+----------+----------+----------+ + * + * Reference: https://www.intel.com/content/www/us/en/products/docs + * /accelerator-engines/advanced-matrix-extensions/overview.html + */ +static inline bool cpuinfo_has_x86_amx_bf16(void) { +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.amx_bf16; +#else + return false; +#endif +} + +static inline bool cpuinfo_has_x86_amx_tile(void) { +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.amx_tile; +#else + return false; +#endif +} + +static inline bool cpuinfo_has_x86_amx_int8(void) { +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.amx_int8; +#else + return false; +#endif +} + +static inline bool cpuinfo_has_x86_amx_fp16(void) { +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.amx_fp16; +#else + return false; +#endif +} + static inline bool cpuinfo_has_x86_hle(void) { #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 return cpuinfo_isa.hle; diff --git a/src/x86/isa.c b/src/x86/isa.c index a28f10f4..97e6d563 100644 --- a/src/x86/isa.c +++ b/src/x86/isa.c @@ -537,6 +537,30 @@ struct cpuinfo_x86_isa cpuinfo_x86_detect_isa( */ isa.avx512bf16 = avx512_regs && !!(structured_feature_info1.eax & UINT32_C(0x00000020)); + /* + * AMX_BF16 instructions: + * - Intel: edx[bit 22] in structured feature info (ecx = 0). + */ + isa.amx_bf16 = avx512_regs && !!(structured_feature_info0.edx & UINT32_C(0x00400000)); + + /* + * AMX_TILE instructions: + * - Intel: edx[bit 24] in structured feature info (ecx = 0). + */ + isa.amx_tile = avx512_regs && !!(structured_feature_info0.edx & UINT32_C(0x01000000)); + + /* + * AMX_INT8 instructions: + * - Intel: edx[bit 25] in structured feature info (ecx = 0). + */ + isa.amx_int8 = avx512_regs && !!(structured_feature_info0.edx & UINT32_C(0x02000000)); + + /* + * AMX_FP16 instructions: + * - Intel: eax[bit 21] in structured feature info (ecx = 1). + */ + isa.amx_fp16 = avx512_regs && !!(structured_feature_info1.eax & UINT32_C(0x00200000)); + /* * HLE instructions: * - Intel: ebx[bit 4] in structured feature info (ecx = 0). diff --git a/tools/isa-info.c b/tools/isa-info.c index 892be0be..af3f8d27 100644 --- a/tools/isa-info.c +++ b/tools/isa-info.c @@ -70,6 +70,10 @@ int main(int argc, char** argv) { printf("\tAVX512VP2INTERSECT: %s\n", cpuinfo_has_x86_avx512vp2intersect() ? "yes" : "no"); printf("\tAVX512_4VNNIW: %s\n", cpuinfo_has_x86_avx512_4vnniw() ? "yes" : "no"); printf("\tAVX512_4FMAPS: %s\n", cpuinfo_has_x86_avx512_4fmaps() ? "yes" : "no"); + printf("\tAMX_BF16: %s\n", cpuinfo_has_x86_amx_bf16() ? "yes" : "no"); + printf("\tAMX_TILE: %s\n", cpuinfo_has_x86_amx_tile() ? "yes" : "no"); + printf("\tAMX_INT8: %s\n", cpuinfo_has_x86_amx_int8() ? "yes" : "no"); + printf("\tAMX_FP16: %s\n", cpuinfo_has_x86_amx_fp16() ? "yes" : "no"); printf("\tAVXVNNI: %s\n", cpuinfo_has_x86_avxvnni() ? "yes" : "no"); printf("Multi-threading extensions:\n"); From 5de5c70fedc26e4477d14fdaad0e4eb5f354400b Mon Sep 17 00:00:00 2001 From: Ozan Aydin <148207261+ozanMSFT@users.noreply.github.com> Date: Wed, 17 Apr 2024 16:16:56 +0200 Subject: [PATCH 59/60] Fixing Ampere Altra Processor detection (#237) **Summary:** Resolves #236 Also related to [PR 220](https://github.com/pytorch/cpuinfo/pull/220) change. ``` "Unknown chip model name 'Ampere(R) Altra(R) Processor'. Please add new Windows on Arm SoC/chip support to arm/windows/init.c!" ``` --- **Previous error details:** The error's reason was: `woa_chip_name` (`windows-arm-init.h`) enum had only 4 elements (stored in `woa_chip_name_last`) ```c enum woa_chip_name { woa_chip_name_microsoft_sq_1 = 0, woa_chip_name_microsoft_sq_2 = 1, woa_chip_name_microsoft_sq_3 = 2, woa_chip_name_ampere_altra = 3, woa_chip_name_unknown = 4, woa_chip_name_last = woa_chip_name_unknown }; ``` However, `woa_chips[]` (`init.c`) has a duplicated value for `woa_chip_name_microsoft_sq_3` due to different strings for same target after the [PR 220](https://github.com/pytorch/cpuinfo/pull/220) > Strings are `Snapdragon (TM) 8cx Gen 3` and `Snapdragon Compute Platform` And this was causing following `for loop` (`init.c`) is not checking for all elements in `woa_chips[]`. ```c for (uint32_t i = 0; i < (uint32_t)woa_chip_name_last; i++) { size_t compare_length = wcsnlen(woa_chips[i].chip_name_string, CPUINFO_PACKAGE_NAME_MAX); int compare_result = wcsncmp(text_buffer, woa_chips[i].chip_name_string, compare_length); if (compare_result == 0) { chip_info = woa_chips + i; break; } } ``` --- **Fix Details:** We added `woa_chip_name_microsoft_sq_3_devkit` to maintain **one to one** relationship between `woa_chip_name` (`windows-arm-init.h`) and `woa_chips[]` (`init.c`). Also, we especially specified indexes with `enums` to prevent future duplications and increase readability of the code and relationship. --- src/arm/windows/init.c | 85 ++++++++++++++++-------------- src/arm/windows/windows-arm-init.h | 5 +- 2 files changed, 48 insertions(+), 42 deletions(-) diff --git a/src/arm/windows/init.c b/src/arm/windows/init.c index e7b80b42..de2f6ccd 100644 --- a/src/arm/windows/init.c +++ b/src/arm/windows/init.c @@ -20,51 +20,56 @@ static struct woa_chip_info woa_chip_unknown = { {{cpuinfo_vendor_unknown, cpuinfo_uarch_unknown, 0}}}; /* Please add new SoC/chip info here! */ -static struct woa_chip_info woa_chips[] = { +static struct woa_chip_info woa_chips[woa_chip_name_last] = { /* Microsoft SQ1 Kryo 495 4 + 4 cores (3 GHz + 1.80 GHz) */ - {L"Microsoft SQ1", - woa_chip_name_microsoft_sq_1, - {{ - cpuinfo_vendor_arm, - cpuinfo_uarch_cortex_a55, - 1800000000, - }, - { - cpuinfo_vendor_arm, - cpuinfo_uarch_cortex_a76, - 3000000000, - }}}, + [woa_chip_name_microsoft_sq_1] = + {L"Microsoft SQ1", + woa_chip_name_microsoft_sq_1, + {{ + cpuinfo_vendor_arm, + cpuinfo_uarch_cortex_a55, + 1800000000, + }, + { + cpuinfo_vendor_arm, + cpuinfo_uarch_cortex_a76, + 3000000000, + }}}, /* Microsoft SQ2 Kryo 495 4 + 4 cores (3.15 GHz + 2.42 GHz) */ - {L"Microsoft SQ2", - woa_chip_name_microsoft_sq_2, - {{ - cpuinfo_vendor_arm, - cpuinfo_uarch_cortex_a55, - 2420000000, - }, - {cpuinfo_vendor_arm, cpuinfo_uarch_cortex_a76, 3150000000}}}, + [woa_chip_name_microsoft_sq_2] = + {L"Microsoft SQ2", + woa_chip_name_microsoft_sq_2, + {{ + cpuinfo_vendor_arm, + cpuinfo_uarch_cortex_a55, + 2420000000, + }, + {cpuinfo_vendor_arm, cpuinfo_uarch_cortex_a76, 3150000000}}}, /* Snapdragon (TM) 8cx Gen 3 @ 3.0 GHz */ - {L"Snapdragon (TM) 8cx Gen 3", - woa_chip_name_microsoft_sq_3, - {{ - cpuinfo_vendor_arm, - cpuinfo_uarch_cortex_a78, - 2420000000, - }, - {cpuinfo_vendor_arm, cpuinfo_uarch_cortex_x1, 3000000000}}}, + [woa_chip_name_microsoft_sq_3] = + {L"Snapdragon (TM) 8cx Gen 3", + woa_chip_name_microsoft_sq_3, + {{ + cpuinfo_vendor_arm, + cpuinfo_uarch_cortex_a78, + 2420000000, + }, + {cpuinfo_vendor_arm, cpuinfo_uarch_cortex_x1, 3000000000}}}, /* Microsoft Windows Dev Kit 2023 */ - {L"Snapdragon Compute Platform", - woa_chip_name_microsoft_sq_3, - {{ - cpuinfo_vendor_arm, - cpuinfo_uarch_cortex_a78, - 2420000000, - }, - {cpuinfo_vendor_arm, cpuinfo_uarch_cortex_x1, 3000000000}}}, + [woa_chip_name_microsoft_sq_3_devkit] = + {L"Snapdragon Compute Platform", + woa_chip_name_microsoft_sq_3_devkit, + {{ + cpuinfo_vendor_arm, + cpuinfo_uarch_cortex_a78, + 2420000000, + }, + {cpuinfo_vendor_arm, cpuinfo_uarch_cortex_x1, 3000000000}}}, /* Ampere Altra */ - {L"Ampere(R) Altra(R) Processor", - woa_chip_name_ampere_altra, - {{cpuinfo_vendor_arm, cpuinfo_uarch_neoverse_n1, 3000000000}}}}; + [woa_chip_name_ampere_altra] = { + L"Ampere(R) Altra(R) Processor", + woa_chip_name_ampere_altra, + {{cpuinfo_vendor_arm, cpuinfo_uarch_neoverse_n1, 3000000000}}}}; BOOL CALLBACK cpuinfo_arm_windows_init(PINIT_ONCE init_once, PVOID parameter, PVOID* context) { struct woa_chip_info* chip_info = NULL; diff --git a/src/arm/windows/windows-arm-init.h b/src/arm/windows/windows-arm-init.h index 36fa061a..dc6e184c 100644 --- a/src/arm/windows/windows-arm-init.h +++ b/src/arm/windows/windows-arm-init.h @@ -8,8 +8,9 @@ enum woa_chip_name { woa_chip_name_microsoft_sq_1 = 0, woa_chip_name_microsoft_sq_2 = 1, woa_chip_name_microsoft_sq_3 = 2, - woa_chip_name_ampere_altra = 3, - woa_chip_name_unknown = 4, + woa_chip_name_microsoft_sq_3_devkit = 3, + woa_chip_name_ampere_altra = 4, + woa_chip_name_unknown = 5, woa_chip_name_last = woa_chip_name_unknown }; From 3c8b1533ac03dd6531ab6e7b9245d488f13a82a5 Mon Sep 17 00:00:00 2001 From: Ma Mingfei Date: Wed, 17 Apr 2024 23:29:37 +0800 Subject: [PATCH 60/60] add detection for intel new isa: avx_ne_convert, avx_vnni_int8, avx_vnni_int16 (#232) Test Plan: ``` bash scripts/local-build.sh ISAS=() OPTIONS=() PLATFORMS=() OPTIONS+=(-quark); PLATFORMS+=("Quark") OPTIONS+=(-p4); PLATFORMS+=("Pentium4") OPTIONS+=(-p4p); PLATFORMS+=("Pentium4 Prescott") OPTIONS+=(-mrm); PLATFORMS+=("Merom") OPTIONS+=(-pnr); PLATFORMS+=("Penryn") OPTIONS+=(-nhm); PLATFORMS+=("Nehalem") OPTIONS+=(-wsm); PLATFORMS+=("Westmere") OPTIONS+=(-snb); PLATFORMS+=("Sandy Bridge") OPTIONS+=(-ivb); PLATFORMS+=("Ivy Bridge") OPTIONS+=(-hsw); PLATFORMS+=("Haswell") OPTIONS+=(-bdw); PLATFORMS+=("Broadwell") OPTIONS+=(-slt); PLATFORMS+=("Saltwell") OPTIONS+=(-slm); PLATFORMS+=("Silvermont") OPTIONS+=(-glm); PLATFORMS+=("Goldmont") OPTIONS+=(-glp); PLATFORMS+=("Goldmont Plus") OPTIONS+=(-tnt); PLATFORMS+=("Tremont") OPTIONS+=(-snr); PLATFORMS+=("Snow Ridge") OPTIONS+=(-skl); PLATFORMS+=("Skylake") OPTIONS+=(-cnl); PLATFORMS+=("Cannon Lake") OPTIONS+=(-icl); PLATFORMS+=("Ice Lake") OPTIONS+=(-skx); PLATFORMS+=("Skylake server") OPTIONS+=(-clx); PLATFORMS+=("Cascade Lake") OPTIONS+=(-cpx); PLATFORMS+=("Cooper Lake") OPTIONS+=(-icx); PLATFORMS+=("Ice Lake server") OPTIONS+=(-knl); PLATFORMS+=("Knights landing") OPTIONS+=(-knm); PLATFORMS+=("Knights mill") OPTIONS+=(-tgl); PLATFORMS+=("Tiger Lake") OPTIONS+=(-adl); PLATFORMS+=("Alder Lake") OPTIONS+=(-mtl); PLATFORMS+=("Meteor Lake") OPTIONS+=(-rpl); PLATFORMS+=("Raptor Lake") OPTIONS+=(-spr); PLATFORMS+=("Sapphire Rapids") OPTIONS+=(-gnr); PLATFORMS+=("Granite Rapids") OPTIONS+=(-gnr256); PLATFORMS+=("Granite Rapids (AVX10.1 / 256VL)") OPTIONS+=(-srf); PLATFORMS+=("Sierra Forest") OPTIONS+=(-arl); PLATFORMS+=("Arrow Lake") OPTIONS+=(-lnl); PLATFORMS+=("Lunar Lake") OPTIONS+=(-future); PLATFORMS+=("Future chip") ISAS+=("AVX_VNNI_INT8") ISAS+=("AVX_VNNI_INT16") ISAS+=("AVX_NE_CONVERT") SDE_BIN="/home/mingfeim/packages/sde-external-9.33.0-2024-01-07-lin/sde" for I in "${!PLATFORMS[@]}"; do echo "${PLATFORMS["${I}"]}" for J in "${!ISAS[@]}"; do "${SDE_BIN}" "${OPTIONS[$I]}" -- ./build/local/isa-info | grep ${ISAS[$J]} done done ``` Results: ``` Quark SDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM or by the input cpuid definition file SDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM or by the input cpuid definition file SDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM or by the input cpuid definition file Pentium4 SDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM4 or by the input cpuid definition file SDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM4 or by the input cpuid definition file SDE-ERROR: 64 bits applications are not supported by input chip: PENTIUM4 or by the input cpuid definition file Pentium4 Prescott AVX_VNNI_INT8: no AVX_VNNI_INT16: no AVX_NE_CONVERT: no Merom AVX_VNNI_INT8: no AVX_VNNI_INT16: no AVX_NE_CONVERT: no Penryn AVX_VNNI_INT8: no AVX_VNNI_INT16: no AVX_NE_CONVERT: no Nehalem AVX_VNNI_INT8: no AVX_VNNI_INT16: no AVX_NE_CONVERT: no Westmere AVX_VNNI_INT8: no AVX_VNNI_INT16: no AVX_NE_CONVERT: no Sandy Bridge AVX_VNNI_INT8: no AVX_VNNI_INT16: no AVX_NE_CONVERT: no Ivy Bridge AVX_VNNI_INT8: no AVX_VNNI_INT16: no AVX_NE_CONVERT: no Haswell AVX_VNNI_INT8: no AVX_VNNI_INT16: no AVX_NE_CONVERT: no Broadwell AVX_VNNI_INT8: no AVX_VNNI_INT16: no AVX_NE_CONVERT: no Saltwell AVX_VNNI_INT8: no AVX_VNNI_INT16: no AVX_NE_CONVERT: no Silvermont AVX_VNNI_INT8: no AVX_VNNI_INT16: no AVX_NE_CONVERT: no Goldmont AVX_VNNI_INT8: no AVX_VNNI_INT16: no AVX_NE_CONVERT: no Goldmont Plus AVX_VNNI_INT8: no AVX_VNNI_INT16: no AVX_NE_CONVERT: no Tremont AVX_VNNI_INT8: no AVX_VNNI_INT16: no AVX_NE_CONVERT: no Snow Ridge AVX_VNNI_INT8: no AVX_VNNI_INT16: no AVX_NE_CONVERT: no Skylake AVX_VNNI_INT8: no AVX_VNNI_INT16: no AVX_NE_CONVERT: no Cannon Lake AVX_VNNI_INT8: no AVX_VNNI_INT16: no AVX_NE_CONVERT: no Ice Lake AVX_VNNI_INT8: no AVX_VNNI_INT16: no AVX_NE_CONVERT: no Skylake server AVX_VNNI_INT8: no AVX_VNNI_INT16: no AVX_NE_CONVERT: no Cascade Lake AVX_VNNI_INT8: no AVX_VNNI_INT16: no AVX_NE_CONVERT: no Cooper Lake AVX_VNNI_INT8: no AVX_VNNI_INT16: no AVX_NE_CONVERT: no Ice Lake server AVX_VNNI_INT8: no AVX_VNNI_INT16: no AVX_NE_CONVERT: no Knights landing AVX_VNNI_INT8: no AVX_VNNI_INT16: no AVX_NE_CONVERT: no Knights mill AVX_VNNI_INT8: no AVX_VNNI_INT16: no AVX_NE_CONVERT: no Tiger Lake AVX_VNNI_INT8: no AVX_VNNI_INT16: no AVX_NE_CONVERT: no Alder Lake AVX_VNNI_INT8: no AVX_VNNI_INT16: no AVX_NE_CONVERT: no Meteor Lake AVX_VNNI_INT8: no AVX_VNNI_INT16: no AVX_NE_CONVERT: no Raptor Lake AVX_VNNI_INT8: no AVX_VNNI_INT16: no AVX_NE_CONVERT: no Sapphire Rapids AVX_VNNI_INT8: no AVX_VNNI_INT16: no AVX_NE_CONVERT: no Granite Rapids AVX_VNNI_INT8: no AVX_VNNI_INT16: no AVX_NE_CONVERT: no Granite Rapids (AVX10.1 / 256VL) AVX_VNNI_INT8: no AVX_VNNI_INT16: no AVX_NE_CONVERT: no Sierra Forest AVX_VNNI_INT8: yes AVX_VNNI_INT16: no AVX_NE_CONVERT: yes Arrow Lake AVX_VNNI_INT8: yes AVX_VNNI_INT16: yes AVX_NE_CONVERT: yes Lunar Lake AVX_VNNI_INT8: yes AVX_VNNI_INT16: yes AVX_NE_CONVERT: yes Future chip AVX_VNNI_INT8: yes AVX_VNNI_INT16: yes AVX_NE_CONVERT: yes ``` --- include/cpuinfo.h | 43 +++++++++++++++++++++++++++++++++++++++++++ src/x86/isa.c | 18 ++++++++++++++++++ tools/isa-info.c | 3 +++ 3 files changed, 64 insertions(+) diff --git a/include/cpuinfo.h b/include/cpuinfo.h index 14fc928a..2d74b62f 100644 --- a/include/cpuinfo.h +++ b/include/cpuinfo.h @@ -816,6 +816,9 @@ struct cpuinfo_x86_isa { bool amx_tile; bool amx_int8; bool amx_fp16; + bool avx_vnni_int8; + bool avx_vnni_int16; + bool avx_ne_convert; bool hle; bool rtm; bool xtest; @@ -1384,6 +1387,46 @@ static inline bool cpuinfo_has_x86_amx_fp16(void) { #endif } +/* + * Intel AVX Vector Neural Network Instructions (VNNI) INT8 + * Supported Platfroms: Sierra Forest, Arrow Lake, Lunar Lake + */ +static inline bool cpuinfo_has_x86_avx_vnni_int8(void) { +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx_vnni_int8; +#else + return false; +#endif +} + +/* + * Intel AVX Vector Neural Network Instructions (VNNI) INT16 + * Supported Platfroms: Arrow Lake, Lunar Lake + */ +static inline bool cpuinfo_has_x86_avx_vnni_int16(void) { +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx_vnni_int16; +#else + return false; +#endif +} + +/* + * A new set of instructions, which can convert low precision floating point + * like BF16/FP16 to high precision floating point FP32, as well as convert FP32 + * elements to BF16. This instruction allows the platform to have improved AI + * capabilities and better compatibility. + * + * Supported Platforms: Sierra Forest, Arrow Lake, Lunar Lake + */ +static inline bool cpuinfo_has_x86_avx_ne_convert(void) { +#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 + return cpuinfo_isa.avx_ne_convert; +#else + return false; +#endif +} + static inline bool cpuinfo_has_x86_hle(void) { #if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64 return cpuinfo_isa.hle; diff --git a/src/x86/isa.c b/src/x86/isa.c index 97e6d563..bfd5e776 100644 --- a/src/x86/isa.c +++ b/src/x86/isa.c @@ -561,6 +561,24 @@ struct cpuinfo_x86_isa cpuinfo_x86_detect_isa( */ isa.amx_fp16 = avx512_regs && !!(structured_feature_info1.eax & UINT32_C(0x00200000)); + /* + * AVX_VNNI_INT8 instructions: + * - Intel: edx[bit 4] in structured feature info (ecx = 1). + */ + isa.avx_vnni_int8 = avx_regs && !!(structured_feature_info1.edx & UINT32_C(0x00000010)); + + /* + * AVX_VNNI_INT16 instructions: + * - Intel: edx[bit 10] in structured feature info (ecx = 1). + */ + isa.avx_vnni_int16 = avx_regs && !!(structured_feature_info1.edx & UINT32_C(0x00000400)); + + /* + * AVX_NE_CONVERT instructions: + * - Intel: edx[bit 5] in structured feature info (ecx = 1). + */ + isa.avx_ne_convert = avx_regs && !!(structured_feature_info1.edx & UINT32_C(0x00000020)); + /* * HLE instructions: * - Intel: ebx[bit 4] in structured feature info (ecx = 0). diff --git a/tools/isa-info.c b/tools/isa-info.c index af3f8d27..27294615 100644 --- a/tools/isa-info.c +++ b/tools/isa-info.c @@ -75,6 +75,9 @@ int main(int argc, char** argv) { printf("\tAMX_INT8: %s\n", cpuinfo_has_x86_amx_int8() ? "yes" : "no"); printf("\tAMX_FP16: %s\n", cpuinfo_has_x86_amx_fp16() ? "yes" : "no"); printf("\tAVXVNNI: %s\n", cpuinfo_has_x86_avxvnni() ? "yes" : "no"); + printf("\tAVX_VNNI_INT8: %s\n", cpuinfo_has_x86_avx_vnni_int8() ? "yes" : "no"); + printf("\tAVX_VNNI_INT16: %s\n", cpuinfo_has_x86_avx_vnni_int16() ? "yes" : "no"); + printf("\tAVX_NE_CONVERT: %s\n", cpuinfo_has_x86_avx_ne_convert() ? "yes" : "no"); printf("Multi-threading extensions:\n"); printf("\tMONITOR/MWAIT: %s\n", cpuinfo_has_x86_mwait() ? "yes" : "no");