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stages.py
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#----------------------------------------------------------------
#
# 4190.308 Computer Architecture (Fall 2019)
#
# Project #4: A 3-Stage Pipelined RISC-V Simulator
#
# November 19, 2019
#
# Jin-Soo Kim ([email protected])
# Systems Software & Architecture Laboratory
# Dept. of Computer Science and Engineering
# Seoul National University
#
#----------------------------------------------------------------
import sys
from consts import *
from isa import *
from components import *
from program import *
from pipe import *
#--------------------------------------------------------------------------
# Control signal table
#--------------------------------------------------------------------------
csignals = {
LW : [ Y, BR_N , OP1_RS1, OP2_IMI, OEN_1, OEN_0, ALU_ADD , WB_MEM, REN_1, MEN_1, M_XRD, MT_W, ],
SW : [ Y, BR_N , OP1_RS1, OP2_IMS, OEN_1, OEN_1, ALU_ADD , WB_X , REN_0, MEN_1, M_XWR, MT_W, ],
AUIPC : [ Y, BR_N , OP1_PC, OP2_IMU, OEN_0, OEN_0, ALU_ADD , WB_ALU, REN_1, MEN_0, M_X , MT_X, ],
LUI : [ Y, BR_N , OP1_X, OP2_IMU, OEN_0, OEN_0, ALU_COPY2, WB_ALU, REN_1, MEN_0, M_X , MT_X, ],
ADDI : [ Y, BR_N , OP1_RS1, OP2_IMI, OEN_1, OEN_0, ALU_ADD , WB_ALU, REN_1, MEN_0, M_X , MT_X, ],
SLLI : [ Y, BR_N , OP1_RS1, OP2_IMI, OEN_1, OEN_0, ALU_SLL , WB_ALU, REN_1, MEN_0, M_X , MT_X, ],
SLTI : [ Y, BR_N , OP1_RS1, OP2_IMI, OEN_1, OEN_0, ALU_SLT , WB_ALU, REN_1, MEN_0, M_X , MT_X, ],
SLTIU : [ Y, BR_N , OP1_RS1, OP2_IMI, OEN_1, OEN_0, ALU_SLTU , WB_ALU, REN_1, MEN_0, M_X , MT_X, ],
XORI : [ Y, BR_N , OP1_RS1, OP2_IMI, OEN_1, OEN_0, ALU_XOR , WB_ALU, REN_1, MEN_0, M_X , MT_X, ],
SRLI : [ Y, BR_N , OP1_RS1, OP2_IMI, OEN_1, OEN_0, ALU_SRL , WB_ALU, REN_1, MEN_0, M_X , MT_X, ],
SRAI : [ Y, BR_N , OP1_RS1, OP2_IMI, OEN_1, OEN_0, ALU_SRA , WB_ALU, REN_1, MEN_0, M_X , MT_X, ],
ORI : [ Y, BR_N , OP1_RS1, OP2_IMI, OEN_1, OEN_0, ALU_OR , WB_ALU, REN_1, MEN_0, M_X , MT_X, ],
ANDI : [ Y, BR_N , OP1_RS1, OP2_IMI, OEN_1, OEN_0, ALU_AND , WB_ALU, REN_1, MEN_0, M_X , MT_X, ],
ADD : [ Y, BR_N , OP1_RS1, OP2_RS2, OEN_1, OEN_1, ALU_ADD , WB_ALU, REN_1, MEN_0, M_X , MT_X, ],
SUB : [ Y, BR_N , OP1_RS1, OP2_RS2, OEN_1, OEN_1, ALU_SUB , WB_ALU, REN_1, MEN_0, M_X , MT_X, ],
SLL : [ Y, BR_N , OP1_RS1, OP2_RS2, OEN_1, OEN_1, ALU_SLL , WB_ALU, REN_1, MEN_0, M_X , MT_X, ],
SLT : [ Y, BR_N , OP1_RS1, OP2_RS2, OEN_1, OEN_1, ALU_SLT , WB_ALU, REN_1, MEN_0, M_X , MT_X, ],
SLTU : [ Y, BR_N , OP1_RS1, OP2_RS2, OEN_1, OEN_1, ALU_SLTU , WB_ALU, REN_1, MEN_0, M_X , MT_X, ],
XOR : [ Y, BR_N , OP1_RS1, OP2_RS2, OEN_1, OEN_1, ALU_XOR , WB_ALU, REN_1, MEN_0, M_X , MT_X, ],
SRL : [ Y, BR_N , OP1_RS1, OP2_RS2, OEN_1, OEN_1, ALU_SRL , WB_ALU, REN_1, MEN_0, M_X , MT_X, ],
SRA : [ Y, BR_N , OP1_RS1, OP2_RS2, OEN_1, OEN_1, ALU_SRA , WB_ALU, REN_1, MEN_0, M_X , MT_X, ],
OR : [ Y, BR_N , OP1_RS1, OP2_RS2, OEN_1, OEN_1, ALU_OR , WB_ALU, REN_1, MEN_0, M_X , MT_X, ],
AND : [ Y, BR_N , OP1_RS1, OP2_RS2, OEN_1, OEN_1, ALU_AND , WB_ALU, REN_1, MEN_0, M_X , MT_X, ],
JALR : [ Y, BR_JR , OP1_RS1, OP2_IMI, OEN_1, OEN_0, ALU_ADD , WB_PC4, REN_1, MEN_0, M_X , MT_X, ],
JAL : [ Y, BR_J , OP1_RS1, OP2_IMJ, OEN_0, OEN_0, ALU_X , WB_PC4, REN_1, MEN_0, M_X , MT_X, ],
BEQ : [ Y, BR_EQ , OP1_RS1, OP2_IMB, OEN_1, OEN_1, ALU_SEQ , WB_X , REN_0, MEN_0, M_X , MT_X, ],
BNE : [ Y, BR_NE , OP1_RS1, OP2_IMB, OEN_1, OEN_1, ALU_SEQ , WB_X , REN_0, MEN_0, M_X , MT_X, ],
BLT : [ Y, BR_LT , OP1_RS1, OP2_IMB, OEN_1, OEN_1, ALU_SLT , WB_X , REN_0, MEN_0, M_X , MT_X, ],
BGE : [ Y, BR_GE , OP1_RS1, OP2_IMB, OEN_1, OEN_1, ALU_SLT , WB_X , REN_0, MEN_0, M_X , MT_X, ],
BLTU : [ Y, BR_LTU, OP1_RS1, OP2_IMB, OEN_1, OEN_1, ALU_SLTU , WB_X , REN_0, MEN_0, M_X , MT_X, ],
BGEU : [ Y, BR_GEU, OP1_RS1, OP2_IMB, OEN_1, OEN_1, ALU_SLTU , WB_X , REN_0, MEN_0, M_X , MT_X, ],
ECALL : [ Y, BR_N , OP1_X , OP2_X , OEN_0, OEN_0, ALU_X , WB_X , REN_0, MEN_0, M_X , MT_X, ],
}
#--------------------------------------------------------------------------
# Control: Control logic (executed in ID stage)
#--------------------------------------------------------------------------
class Control(object):
def __init__(self):
super().__init__()
# Internal signals:----------------------------
#
# self.pc_sel # Pipe.CTL.pc_sel
# self.alu_fun # Pipe.CTL.alu_fun
# self.rf_wen # Pipe.CTL.rf_wen
# self.imem_en # Pipe.CTL.imem_en
# self.imem_rw # Pipe.CTL.imem_rw
#
#----------------------------------------------
# These signals are used before gen() is called
self.imem_en = True
self.imem_rw = M_XRD
def gen(self, inst):
from stages import FD, EX, MW
self.MW_bubble = False
# DO NOT TOUCH------------------------------------------------
opcode = RISCV.opcode(inst)
if opcode == ECALL:
Pipe.FD.exception |= EXC_ECALL
elif opcode == ILLEGAL:
Pipe.FD.exception |= EXC_ILLEGAL_INST
inst = BUBBLE
opcode = RISCV.opcode(inst)
cs = csignals[opcode]
self.br_type = cs[CS_BR_TYPE]
self.op1_sel = cs[CS_OP1_SEL]
self.op2_sel = cs[CS_OP2_SEL]
self.alu_fun = cs[CS_ALU_FUN]
self.wb_sel = cs[CS_WB_SEL]
self.rf_wen = cs[CS_RF_WEN]
rs1_oen = cs[CS_RS1_OEN]
rs2_oen = cs[CS_RS2_OEN]
self.dmem_en = cs[CS_MEM_EN]
self.dmem_rw = cs[CS_MEM_FCN]
#-------------------------------------------------------------
# Control signal to select the next PC
self.pc_sel = PC_4
# DO NOT TOUCH -----------------------------------------------
# Any instruction with an exception becomes BUBBLE as it enters the MW stage. (except ECALL)
# All the following instructions after exception become BUBBLE too.
self.MW_bubble = (Pipe.EX.exception and (Pipe.EX.exception != EXC_ECALL)) or (Pipe.MW.exception)
if inst == BUBBLE:
return False
else:
return True
#-------------------------------------------------------------
#--------------------------------------------------------------------------
# FD: Instruction fetch and decode stage
#--------------------------------------------------------------------------
class FD(Pipe):
# Pipeline registers ------------------------------
reg_pc = WORD(0) # FD.reg_pc
#--------------------------------------------------
def __init__(self):
super().__init__()
# Internal signals:----------------------------
#
# self.pc # Pipe.FD.pc
# self.inst # Pipe.FD.inst
# self.exception # Pipe.FD.exception
# self.pc_next # Pipe.FD.pc_next
# self.pcplus4 # Pipe.FD.pcplus4
#
# self.rs1 # Pipe.FD.rs1
# self.rs2 # Pipe.FD.rs2
# self.rd # Pipe.FD.rd
# self.op1_data # Pipe.FD.op1_data
# self.op2_data # Pipe.FD.op2_data
# self.rs2_data # Pipe.FD.rs2_data
#
#----------------------------------------------
def compute(self):
# DO NOT TOUCH -----------------------------------------------
# Read out pipeline register values
self.pc = FD.reg_pc
# Fetch an instruction from instruction memory (imem)
self.inst, status = Pipe.cpu.imem.access(Pipe.CTL.imem_en, self.pc, 0, Pipe.CTL.imem_rw)
# Handle exception during imem access
if not status:
self.exception = EXC_IMEM_ERROR
self.inst = BUBBLE
else:
self.exception = EXC_NONE
#-------------------------------------------------------------
# Compute PC + 4 using an adder
self.pcplus4 = Pipe.cpu.adder_pcplus4.op(self.pc, 4)
self.rs1 = RISCV.rs1(self.inst)
self.rs2 = RISCV.rs2(self.inst)
self.rd = RISCV.rd(self.inst)
imm_i = RISCV.imm_i(self.inst)
imm_s = RISCV.imm_s(self.inst)
imm_b = RISCV.imm_b(self.inst)
imm_u = RISCV.imm_u(self.inst)
imm_j = RISCV.imm_j(self.inst)
self.op1_data = Pipe.cpu.rf.read(self.rs1)
rf_rs2_data = Pipe.cpu.rf.read(self.rs2)
# Generate control signals
if not Pipe.CTL.gen(self.inst):
self.inst = BUBBLE
# Determine ALU operand 2: R[rs2] or immediate values
self.op2_data = rf_rs2_data if Pipe.CTL.op2_sel == OP2_RS2 else \
imm_i if Pipe.CTL.op2_sel == OP2_IMI else \
imm_s if Pipe.CTL.op2_sel == OP2_IMS else \
imm_b if Pipe.CTL.op2_sel == OP2_IMB else \
imm_u if Pipe.CTL.op2_sel == OP2_IMU else \
imm_j if Pipe.CTL.op2_sel == OP2_IMJ else \
WORD(0)
# Select next PC
self.pc_next = self.pcplus4 if Pipe.CTL.pc_sel == PC_4 else \
WORD(0)
def update(self):
FD.reg_pc = self.pc_next
EX.reg_pc = self.pc
EX.reg_inst = self.inst
EX.reg_exception = self.exception
EX.reg_rd = self.rd
EX.reg_op1_data = self.op1_data
EX.reg_op2_data = self.op2_data
EX.reg_c_rf_wen = Pipe.CTL.rf_wen
EX.reg_c_alu_fun = Pipe.CTL.alu_fun
# DO NOT TOUCH -----------------------------------------------
Pipe.log(S_FD, self.pc, self.inst, self.log())
#-------------------------------------------------------------
# DO NOT TOUCH ---------------------------------------------------
def log(self):
if self.inst in [ BUBBLE, ILLEGAL ]:
return('# -')
else:
return("# inst=0x%08x, pc_next=0x%08x, rd=%d rs1=%d rs2=%d op1=0x%08x op2=0x%08x"
% (self.inst, self.pc_next, self.rd, self.rs1, self.rs2, self.op1_data, self.op2_data))
#-----------------------------------------------------------------
#--------------------------------------------------------------------------
# EX: Execution stage
#--------------------------------------------------------------------------
class EX(Pipe):
# Pipeline registers ------------------------------
reg_pc = WORD(0) # EX.reg_pc
reg_inst = WORD(BUBBLE) # EX.reg_inst
reg_exception = WORD(EXC_NONE) # EX.exception
reg_rd = WORD(0) # EX.reg_rd
reg_c_rf_wen = False # EX.reg_c_rf_wen
reg_c_wb_sel = WORD(WB_X) # EX.reg_c_wb_sel
reg_c_alu_fun = WORD(ALU_X) # EX.reg_c_alu_fun
reg_op1_data = WORD(0) # EX.reg_op1_data
reg_op2_data = WORD(0) # EX.reg_op2_data
#--------------------------------------------------
def __init__(self):
super().__init__()
# Internal signals:----------------------------
#
# self.pc # Pipe.EX.pc
# self.inst # Pipe.EX.inst
# self.exception # Pipe.EX.exception
# self.rd # Pipe.EX.rd
# self.c_rf_wen # Pipe.EX.c_rf_wen
# self.c_alu_fun # Pipe.EX.c_alu_fun
# self.op1_data # Pipe.EX.op1_data
# self.op2_data # Pipe.EX.op2_data
#
# self.alu_out # Pipe.EX.alu_out
#
#----------------------------------------------
def compute(self):
# Read out pipeline register values
self.pc = EX.reg_pc
self.inst = EX.reg_inst
self.exception = EX.reg_exception
self.rd = EX.reg_rd
self.c_rf_wen = EX.reg_c_rf_wen
self.c_alu_fun = EX.reg_c_alu_fun
self.op1_data = EX.reg_op1_data
self.op2_data = EX.reg_op2_data
# The second input to ALU should be put into self.alu2_data for correct log msg.
self.alu2_data = self.op2_data
# Perform ALU operation
self.alu_out = Pipe.cpu.alu.op(self.c_alu_fun, self.op1_data, self.alu2_data)
def update(self):
MW.reg_pc = self.pc
MW.reg_exception = self.exception
if Pipe.CTL.MW_bubble:
MW.reg_inst = WORD(BUBBLE)
MW.reg_c_rf_wen = False
else:
MW.reg_inst = self.inst
MW.reg_rd = self.rd
MW.reg_c_rf_wen = self.c_rf_wen
MW.reg_alu_out = self.alu_out
# DO NOT TOUCH -----------------------------------------------
Pipe.log(S_EX, self.pc, self.inst, self.log())
#-------------------------------------------------------------
# DO NOT TOUCH ---------------------------------------------------
def log(self):
ALU_OPS = {
ALU_X : f'# -',
ALU_ADD : f'# {self.alu_out:#010x} <- {self.op1_data:#010x} + {self.alu2_data:#010x}',
ALU_SUB : f'# {self.alu_out:#010x} <- {self.op1_data:#010x} - {self.alu2_data:#010x}',
ALU_AND : f'# {self.alu_out:#010x} <- {self.op1_data:#010x} & {self.alu2_data:#010x}',
ALU_OR : f'# {self.alu_out:#010x} <- {self.op1_data:#010x} | {self.alu2_data:#010x}',
ALU_XOR : f'# {self.alu_out:#010x} <- {self.op1_data:#010x} ^ {self.alu2_data:#010x}',
ALU_SLT : f'# {self.alu_out:#010x} <- {self.op1_data:#010x} < {self.alu2_data:#010x} (signed)',
ALU_SLTU : f'# {self.alu_out:#010x} <- {self.op1_data:#010x} < {self.alu2_data:#010x} (unsigned)',
ALU_SLL : f'# {self.alu_out:#010x} <- {self.op1_data:#010x} << {self.alu2_data & 0x1f}',
ALU_SRL : f'# {self.alu_out:#010x} <- {self.op1_data:#010x} >> {self.alu2_data & 0x1f} (logical)',
ALU_SRA : f'# {self.alu_out:#010x} <- {self.op1_data:#010x} >> {self.alu2_data & 0x1f} (arithmetic)',
ALU_COPY1 : f'# {self.alu_out:#010x} <- {self.op1_data:#010x} (pass 1)',
ALU_COPY2 : f'# {self.alu_out:#010x} <- {self.alu2_data:#010x} (pass 2)',
ALU_SEQ : f'# {self.alu_out:#010x} <- {self.op1_data:#010x} == {self.alu2_data:#010x}',
}
return('# -' if self.inst == BUBBLE else ALU_OPS[self.c_alu_fun]);
#-----------------------------------------------------------------
#--------------------------------------------------------------------------
# MW: Memory access and write back stage
#--------------------------------------------------------------------------
class MW(Pipe):
# Pipeline registers ------------------------------
reg_pc = WORD(0) # MW.reg_pc
reg_inst = WORD(BUBBLE) # MW.reg_inst
reg_exception = WORD(EXC_NONE) # MW.reg_exception
reg_rd = WORD(0) # MW.reg_rd
reg_c_rf_wen = False # MW.reg_c_rf_wen
reg_alu_out = WORD(0) # MW.reg_alu_out
#--------------------------------------------------
def __init__(self):
super().__init__()
# Internal signals:----------------------------
#
# self.pc # Pipe.MW.pc
# self.inst # Pipe.MW.inst
# self.exception # Pipe.MW.exception
# self.rd # Pipe.MW.rd
# self.c_rf_wen # Pipe.MW.c_rf_wen
# self.alu_out # Pipe.MW.alu_out
#
#----------------------------------------------
def compute(self):
# Read out pipeline register values
self.pc = MW.reg_pc
self.inst = MW.reg_inst
self.exception = MW.reg_exception
self.rd = MW.reg_rd
self.c_rf_wen = MW.reg_c_rf_wen
self.alu_out = MW.reg_alu_out
# Nothing to do for now
def update(self):
if self.c_rf_wen:
Pipe.cpu.rf.write(self.rd, self.alu_out)
# DO NOT TOUCH -----------------------------------------------
Pipe.log(S_MW, self.pc, self.inst, self.log())
if (self.exception):
return False
else:
return True
# ------------------------------------------------------------
# DO NOT TOUCH ---------------------------------------------------
def log(self):
if self.inst == BUBBLE or (not self.c_rf_wen):
return('# -')
else:
return('# R[%d] <- 0x%08x' % (self.rd, self.alu_out))
#-----------------------------------------------------------------