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bdm-bit-S08.mu4
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| This file is part of muforth: https://muforth.dev/
|
| Copyright 2002-2025 David Frech. (Read the LICENSE for details.)
loading S08 BDM support (bit routines for S08)
__meta
( Force 24M bit routines if we're compiling for a USB device.)
.reg EPCTL0 .if
-d 24m
.then
( Support for Freescale's Background Debug Mode - or BDM.)
| These are bit send and receive commands for an S08 processor running at
| 18.432M - bus clock of 9.216M - and talking to S08 targets running at
| 4M and 8M.
|
| These routines are a bit different from their cousins for the 908 for
| several reasons:
|
| * the clock speeds are different - the S08 is running twice as fast as
| its 908 counterpart;
|
| * the instruction timings are different - not only how many cycles an
| instruction takes, but the positioning and read and write cycles is
| quite different between the 908 and S08;
|
| * I don't have the same 5v-to-3v translation issues, so driving the BKGD
| pin on another S08 _from_ an S08 - both at 3v - is easy.
aka PTAD PortA
aka PTADD DirA
aka PTBD PortB
aka PTBDD DirB
| We are using PortA0 (TPMCH0) to drive BKGD, and PortB0 to drive the
| target's RESET pin.
|
| To transmit, we set DirA0 high for the duration of the _byte_, and simply
| toggle the data value on PA0.
|
| To receive, we set PA0 low for the duration of the byte, and toggle the
| DirA0 to either drive a start bit, or listen for the target's response.
| The "standard" pinout of Freescale's BDM connector is shown below:
|
| 1
| +----+
| BKGD |X O| Gnd
| NC |O O| /RESET
| NC |O O| Vdd
| +----+
label BdmDriveLow
PortA 0 bclr
DirA 0 bset
rts ;c
( Called when BDM loop starts up; return to canonical state.)
label BdmHiZ
TPMC0SC ) clr ( take pin from timer
PortA 0 bset ( before tri-stating, briefly drive high)
DirA 0 bset
DirA 0 bclr ( tri-state A0)
rts ;c
label ResetDriveLow
PortB 0 bclr
DirB 0 bset
rts ;c
( Called when BDM loop starts up; return to canonical state.)
label ResetHiZ
PortB 0 bset ( before tri-stating, briefly drive high)
DirB 0 bset
DirB 0 bclr ( tri-state B0)
rts ;c
| The magic numbers for bit-banging BDM are as follows:
|
| * Start bit should be 4 target cycles long.
|
| * Received bits should be sampled on the 10th target cycle, counting from
| the falling edge of the start bit.
|
| * Transmitted bits should be held for 13 target cycles, counting from
| the falling edge of the start bit.
| IMPORTANT NOTE: We use the instruction 0 ,x tst as a one-byte, 3 cycle
| delay. This only works if HX points to RAM or into defined flash space!
| If it points to undefined memory, an illegal address (ILAD) exception
| will occur. If it points into I/O register space, it could erroneously
| clear flag bits - by reading data registers, eg. So be careful!
|
| The way we've defined the by-byte transmit and receive routines, HX
| always points into RAM space.
.ifdef 4.9152m
| I'm defining these bit routines so I can run an S08QG part from a xtal
| and get more accurate clock trim values for other parts - by measuring
| BDM sync pulses. This is precisely what I do with the 908.
|
| I found that running S08 parts from the internal clock - while accurate
| enough to do reliable serial communication - somehow got flaky results
| when trimming other parts, esp the JS parts. I tried trimming three QE32
| parts from an internally-clocked S08, and all three were off by one,
| compared to the trim I got when I ran the BDM code on a 908 clocked by a
| xtal. The JS parts were much worse: I was off so much that one of them
| barely worked over serial, and when I tried to flash it (via chat) the
| address being flashed jumped around. The high bit of H kept getting set,
| jumping the memory being flashed forward by 128 bytes. Better trims fixed
| the problem. But, oddly, the JS trims, instead of being off by one, were
| off by sixteen or more!
|
| The QG parts have a known erratum with their ICS. Running them with BDIV =
| 1 - which is what I'm doing! - is known to cause erratic behaviour.
| Whether clocked from the internal reference or from an external xtal,
| running them with BDIV = 2 is the only way to get solid clocking. But
| since I'm limited to using a 5M xtal - resulting in a 20M FLL clock -
| with BDIV = 2 I'll be running at 5M bus clock. Since I'll be using a
| 4.9152M xtal, that will be my bus clock too.
|
| This is about half the speed the I'm currently running the QG S08's, so I
| had to rewrite the BDM bit routines, and that's what we have here.
| ------------------------------------------------------------------------
| Host 4.9152M, Target 4M
| ------------------------------------------------------------------------
(
4M target 4.9152M host
========= ==========
4 4.9
10 12.3
13 16
)
label SetTx1_4M
MakeJmp bsr | pushes address of following code onto stack!
( Send one bit via BDM, from A0)
( 5~ start bit; hold for 16~)
PortA 0 bclr ( rfwpp - drive start bit)
nop nop ( p.p - delay 2 cycles)
PortA ) sta ( wpp - drive data bit)
.a psh .a pul nop ( sp.ufp.p - delay 6 cycles)
PortA 0 bset ( rfwpp - drive stop bit)
rts ;c
label SetRx1_4M
MakeJmp bsr | pushes address of following routine on stack!
( Recv one bit via BDM, into A0)
( 5~ start bit; sample at 12~)
DirA 0 bset ( rfwpp - drive start bit)
DirA 0 bclr ( rfwpp - tri-state BKGD)
0 ,x tst nop ( rfp.p - delay 4 cycles)
PortA ) lda ( rpp - sample bit)
rts ;c
| ------------------------------------------------------------------------
| Host 4.9152M, Target 8M
| ------------------------------------------------------------------------
(
8M target 4.9152M host
========= ==========
4 2.4
10 6
13 8
)
label SetTx1_8M
MakeJmp bsr | pushes address of following code onto stack!
( Send one bit via BDM, from A0)
( 3~ start bit; hold for 8~)
PortA 0 bclr ( rfwpp - drive start bit)
PortA ) sta ( wpp - drive data bit)
PortA 0 bset ( rfwpp - drive stop bit)
rts ;c
label SetRx1_8M
MakeJmp bsr | pushes address of following code onto stack!
( Recv one bit via BDM, into A0)
( 3~ start bit; sample at 6~)
.a clr
| DirA ) lda "0fe # and ( get ready to clear low bit)
DirA 0 bset ( rfwpp - drive start bit)
DirA ) sta ( wpp - tri-state BKGD)
PortA ) lda ( rpp - sample bit)
rts ;c
.else .ifdef 8m
| ------------------------------------------------------------------------
| Host 8M, Target 4M
| ------------------------------------------------------------------------
(
4M target 8M host
========= =======
4 8
10 20
13 26
)
label SetTx1_4M
MakeJmp bsr | pushes address of following code onto stack!
( Send one bit via BDM, from A0)
( 8~ start bit; hold for 26~)
PortA 0 bclr ( rfwpp - drive start bit)
0 ,x tst ( rfp )
nop nop ( p.p )
PortA ) sta ( wpp - drive data bit)
0 ,x tst ( rfp )
0 ,x tst ( rfp )
0 ,x tst ( rfp )
0 ,x tst ( rfp )
nop ( p )
PortA 0 bset ( rfwpp - drive stop bit)
rts ;c
label SetRx1_4M
MakeJmp bsr | pushes address of following code onto stack!
( Recv one bit via BDM, into A0)
( 8~ start bit; sample at 20~)
DirA 0 bset ( rfwpp - drive start bit)
0 ,x tst ( rfp )
DirA 0 bclr ( rfwpp - tri-state BKGD)
0 ,x tst ( rfw )
0 ,x tst ( rfw )
0 ,x tst ( rfw )
PortA ) lda ( rpp - sample bit)
rts ;c
| ------------------------------------------------------------------------
| Host 8M, Target 8M
| ------------------------------------------------------------------------
(
8M target 8M host
========= =======
4 4
10 10
13 13
)
label SetTx1_8M
MakeJmp bsr | pushes address of following code onto stack!
( Send one bit via BDM, from A0)
( 4~ start bit; hold for 13~)
PortA 0 bclr ( rfwpp )
nop ( p )
PortA ) sta ( wpp )
0 ,x tst ( rfw )
nop ( p )
PortA 0 bset ( rfwpp )
rts ;c
label SetRx1_8M
MakeJmp bsr | pushes address of following routine on stack!
( Recv one bit via BDM, into A0)
( 4~ start bit; sample at 10~)
.a clr
DirA 0 bset ( rfwpp )
nop ( p )
DirA ) sta ( wpp )
0 ,x tst ( rfp )
PortA ) lda ( rpp )
rts ;c
.else .ifdef 9.8304m
| I'm defining these bit routines so I can run an S08QG part from a xtal
| and get more accurate clock trim values for other parts - by measuring
| BDM sync pulses. This is precisely what I do with the 908.
|
| I found that running S08 parts from the internal clock - while accurate
| enough to do reliable serial communication - somehow got flaky results
| when trimming other parts, esp the JS parts. I tried trimming three QE32
| parts from an internally-clocked S08, and all three were off by one,
| compared to the trim I got when I ran the BDM code on a 908 clocked by a
| xtal. The JS parts were much worse: I was off so much that one of them
| barely worked over serial, and when I tried to flash it (via chat) the
| address being flashed jumped around. The high bit of H kept getting set,
| jumping the memory being flashed forward by 128 bytes. Better trims fixed
| the problem. But, oddly, the JS trims, instead of being off by one, were
| off by sixteen or more!
|
| The QG parts have a known erratum with their ICS. Running them with BDIV =
| 1 - which is what I'm doing! - is known to cause erratic behaviour. OTOH,
| I can't seem to reliably connect to one of my JS16 chips at this speed,
| so I'm going to try running with a 4.9152M xtal, but running with BDIV =
| 1; this will yield a 9.8304M bus clock.
| ------------------------------------------------------------------------
| Host 9.8304, Target 4M
| ------------------------------------------------------------------------
(
4M target 9.8304M host
========= ==========
4 9.8
10 24.6
13 31.9
)
label SetTx1_4M
MakeJmp bsr | pushes address of following code onto stack!
( Send one bit via BDM, from A0)
( 10~ start bit; hold for 32~)
PortA 0 bclr ( rfwpp - drive start bit)
0 ,x tst ( rfp )
0 ,x tst ( rfp )
nop ( p )
PortA ) sta ( wpp - drive data bit)
0 ,x tst ( rfp )
0 ,x tst ( rfp )
0 ,x tst ( rfp )
0 ,x tst ( rfp )
0 ,x tst ( rfp )
nop nop ( pp )
PortA 0 bset ( rfwpp - drive stop bit)
rts ;c
label SetRx1_4M
MakeJmp bsr | pushes address of following code onto stack!
( Recv one bit via BDM, into A0)
( 10~ start bit; sample at 25~)
DirA 0 bset ( rfwpp - drive start bit)
0 ,x tst nop nop ( rfp.p.p )
DirA 0 bclr ( rfwpp - tri-state BKGD)
0 ,x tst ( rfw )
0 ,x tst ( rfw )
0 ,x tst ( rfw )
0 ,x tst ( rfw )
PortA ) lda ( rpp - sample bit)
rts ;c
| ------------------------------------------------------------------------
| Host 9.8304, Target 8M
| ------------------------------------------------------------------------
(
8M target 9.8304M host
========= ==========
4 4.9
10 12.3
13 16
)
label SetTx1_8M
MakeJmp bsr | pushes address of following code onto stack!
( Send one bit via BDM, from A0)
( 5~ start bit; hold for 16~)
PortA 0 bclr ( rfwpp - drive start bit)
nop nop ( p.p - delay 2 cycles)
PortA ) sta ( wpp - drive data bit)
.a psh .a pul nop ( sp.ufp.p - delay 6 cycles)
PortA 0 bset ( rfwpp - drive stop bit)
rts ;c
label SetRx1_8M
MakeJmp bsr | pushes address of following routine on stack!
( Recv one bit via BDM, into A0)
( 5~ start bit; sample at 12~)
DirA 0 bset ( rfwpp - drive start bit)
DirA 0 bclr ( rfwpp - tri-state BKGD)
0 ,x tst nop ( rfp.p - delay 4 cycles)
PortA ) lda ( rpp - sample bit)
rts ;c
.else .ifdef 24m
| ------------------------------------------------------------------------
| Host 24M, Target 4M
| ------------------------------------------------------------------------
(
4M target 24M host
========= ========
4 24
10 60
13 78
)
label SetTx1_4M
MakeJmp bsr | pushes address of following code onto stack!
( Send one bit via BDM, from A0)
( 24~ start bit; hold for 79~)
PortA 0 bclr ( rfwpp - drive start bit)
.a psh 3 # lda ( sp.pp )
begin .a decz? until ( fppp * 3)
.a pul ( ufp )
nop nop ( pp )
PortA ) sta ( wpp - drive data bit)
12 # lda ( pp )
begin .a decz? until ( fppp * 12)
PortA 0 bset ( rfwpp - drive stop bit)
rts ;c
label SetRx1_4M
MakeJmp bsr | pushes address of following code onto stack!
( Recv one bit via BDM, into A0)
( 24~ start bit; sample at 61~)
DirA 0 bset ( rfwpp - drive start bit)
4 # lda ( pp )
begin .a decz? until ( fppp * 4)
nop ( p )
DirA 0 bclr ( rfwpp - tri-state BKGD)
8 # lda ( pp )
begin .a decz? until ( fppp * 8)
PortA ) lda ( rpp - sample bit)
rts ;c
| ------------------------------------------------------------------------
| Host 24M, Target 8M
| ------------------------------------------------------------------------
(
8M target 24M host
========= ========
4 12
10 30
13 39
)
label SetTx1_8M
MakeJmp bsr | pushes address of following code onto stack!
( Send one bit via BDM, from A0)
( 12~ start bit; hold for 39~)
PortA 0 bclr ( rfwpp - drive start bit)
0 ,x tst ( rfp )
0 ,x tst ( rfp )
0 ,x tst ( rfp )
PortA ) sta ( wpp - drive data bit)
5 # lda ( pp )
begin .a decz? until ( fppp * 5)
PortA 0 bset ( rfwpp - drive stop bit)
rts ;c
label SetRx1_8M
MakeJmp bsr | pushes address of following code onto stack!
( Recv one bit via BDM, into A0)
( 12~ start bit; sample at 30~)
DirA 0 bset ( rfwpp - drive start bit)
0 ,x tst ( rfp )
0 ,x tst ( rfp )
nop ( p )
DirA 0 bclr ( rfwpp - tri-state BKGD)
3 # lda ( pp )
begin .a decz? until ( fppp * 3)
nop ( p )
PortA ) lda ( rpp - sample bit)
rts ;c
| ------------------------------------------------------------------------
| Host 24M, Target 16M
| ------------------------------------------------------------------------
(
16M target 24M host
========= ========
4 6
10 15
13 19.5
)
label SetTx1_16M
MakeJmp bsr | pushes address of following code onto stack!
( Send one bit via BDM, from A0)
( 6~ start bit; hold for 20~)
PortA 0 bclr ( rfwpp - drive start bit)
0 ,x tst ( rfp )
PortA ) sta ( wpp - drive data bit)
0 ,x tst ( rfp )
0 ,x tst ( rfp )
0 ,x tst ( rfp )
PortA 0 bset ( rfwpp - drive stop bit)
rts ;c
label SetRx1_16M
MakeJmp bsr | pushes address of following code onto stack!
( Recv one bit via BDM, into A0)
( 6~ start bit; sample at 15~)
DirA 0 bset ( rfwpp - drive start bit)
nop ( p )
DirA 0 bclr ( rfwpp - tri-state BKGD)
0 ,x tst ( rfp )
0 ,x tst ( rfp )
PortA ) lda ( rpp - sample bit)
rts ;c
.else ( 9.216M host)
| ------------------------------------------------------------------------
| Host 9.216M, Target 4M
| ------------------------------------------------------------------------
(
4M target 9.216 host
========= ==========
4 9.2
10 23
13 30
)
label SetTx1_4M
MakeJmp bsr | pushes address of following code onto stack!
( Send one bit via BDM, from A0)
( 9~ start bit; hold for 30~)
PortA 0 bclr ( rfwpp - drive start bit)
0 ,x tst ( rfp - delay 6 cycles)
0 ,x tst ( rfp )
PortA ) sta ( wpp - drive data bit)
0 ,x tst ( rfp - delay 16 cycles)
0 ,x tst ( rfp )
0 ,x tst ( rfp )
0 ,x tst ( rfp )
0 ,x tst ( rfp )
nop ( p )
PortA 0 bset ( rfwpp - drive stop bit)
rts ;c
label SetRx1_4M
MakeJmp bsr | pushes address of following code onto stack!
( Recv one bit via BDM, into A0)
( 9~ start bit; sample at 23~)
DirA 0 bset ( rfwpp - drive start bit)
0 ,x tst nop ( rfp.p - delay 4 cycles)
DirA 0 bclr ( rfwpp - tri-state BKGD)
0 ,x tst ( rfw - delay 11 cycles)
0 ,x tst ( rfw )
.a psh .a pul ( sp.ufp - delay 5 cycles)
PortA ) lda ( rpp - sample bit)
rts ;c
| ------------------------------------------------------------------------
| Host 9.216M, Target 8M
| ------------------------------------------------------------------------
(
8M target 9.216 host
========= ==========
4 4.6
10 11.5
13 15
)
label SetTx1_8M
MakeJmp bsr | pushes address of following code onto stack!
( Send one bit via BDM, from A0)
( 5~ start bit; hold for 15~)
PortA 0 bclr ( rfwpp - drive start bit)
nop nop ( p.p - delay 2 cycles)
PortA ) sta ( wpp - drive data bit)
.a psh .a pul ( sp.ufp - delay 5 cycles)
PortA 0 bset ( rfwpp - drive stop bit)
rts ;c
label SetRx1_8M
MakeJmp bsr | pushes address of following code onto stack!
( Recv one bit via BDM, into A0)
( 5~ start bit; sample at 12~)
DirA 0 bset ( rfwpp - drive start bit)
DirA 0 bclr ( rfwpp - tri-state BKGD)
0 ,x tst nop ( rfp.p - delay 4 cycles)
PortA ) lda ( rpp - sample bit)
rts ;c
.ifdef bdm-16m-target
| ------------------------------------------------------------------------
| Host 9.216M, Target 16M
| ------------------------------------------------------------------------
(
16M target 9.216 host
========= ==========
4 2.3
10 5.7
13 7.4
)
label SetTx1_16M
MakeJmp bsr | pushes address of following code onto stack!
( Send one bit via BDM, from A0)
( 3~ start bit; hold for 8~)
PortA 0 bclr ( rfwpp - drive start bit)
PortA ) sta ( wpp - drive data bit)
PortA 0 bset ( rfwpp - drive stop bit)
rts ;c
label SetRx1_16M
MakeJmp bsr | pushes address of following code onto stack!
( Recv one bit via BDM, into A0)
( 3~ start bit; sample at 6~)
.a clr
| DirA ) lda "0fe # and ( get ready to clear low bit)
DirA 0 bset ( rfwpp - drive start bit)
DirA ) sta ( wpp - tri-state BKGD)
PortA ) lda ( rpp - sample bit)
rts ;c
.then ( 16M target)
.then .then .then .then ( 4.9152M host)
| ------------------------------------------------------------------------
| Byte-wise transmit and receive
| ------------------------------------------------------------------------
( Send one byte via BDM.)
( NOT the usual X stack discipline with two slots free!)
label BdmTx ( tx byte at 0,x)
( loop 8; generate bits MSB first)
8 # lda .a psh
PortA 0 bset ( idle A0 high)
DirA 0 bset ( drive A0 for the duration of the byte)
begin
0 ,x rol .a rol ( bit into A0)
BdmTx1 ) jsr
0 ,s decz? until
DirA 0 bclr ( done xmitting; tri-state A0)
.a pul
1 # aix rts ;c
( Recv one byte via BDM.)
( NOT the usual X stack discipline with two slots free!)
( BdmRx1 leaves received bit in C.)
label BdmRx ( recvd byte to 0,x)
( loop 8; recv bits MSB first; bit is 01)
8 # lda .a psh 0 ,x clr
PortA 0 bclr ( start bit is zero)
DirA 0 bclr ( make sure A0 tri-stated)
begin
BdmRx1 ) jsr .a ror ( A0 -> C) 0 ,x rol
0 ,s decz? until
.a pul
1 # aix rts ;c
label SyncWait | clobbers A
.a clr
begin
TPMC0SC 7 bclr? while ( edge not triggered)
.a psh .x psh mul .x pul .a pul ( 15~)
.a decz? until then rts ;c
label SyncPulse
TPMC0SC ) clr | take pin from timer
08 # TPMSC ) mov | start timer; clock from bus clock
BdmHiZ ) jsr | start in a known state
BdmDriveLow ) jsr
SyncWait bsr | drive BKGD low for a long time
BdmHiZ ) jsr | drive high briefly before tristating
08 # TPMC0SC ) mov | capture falling edge on BKGD in CH0 (PA0)
| now target waits 16 BDM cycles, then drives BKGD low for 128
SyncWait bsr
TPMC0SC 7 bset? if ( falling edge triggered)
( on S08 can read capture registers in either order)
TPMC0VL ) lda 1 ,x sta
TPMC0VH ) lda 0 ,x sta
04 # TPMC0SC ) mov | capture rising edge on BKGD in CH0 (PA0)
SyncWait bsr
TPMC0SC 7 bset? if ( rising edge triggered)
| If both falling and rising triggered, calculate difference;
| otherwise return 0.
TPMC0VL ) lda 1 ,x sub 1 ,x sta
TPMC0VH ) lda 0 ,x sbc 0 ,x sta
TPMC0SC ) clr | take pin from timer
rts
then
then
( return 0)
1 ,x clr 0 ,x clr
TPMC0SC ) clr | take pin from timer
rts ;c