Imperas DV Wrap does not detect mtvec clear when executed as first instruction after reset

[silabs-kjetil]

The cv32e40x contains a configurable mtvec reset value (mtvec_addr). This issue was seen when configuring the core with a mtvec_addr of 0x20000000 and clearing mtvec as the first instruction. In order to reproduce this we can create a firmware that contains this instruction as the first instruction executed after reset.

csrw  mtvec, x0;

When running this in simulation with USE_ISS=1 then we observe an ISS mismatch being detected. It seems like the imperas dv wrapper does not detect that the core has changed the mtvec value.

Info (IDV) Instruction executed prior to mismatch '0x20000080(rvtest_entry_point+0): 30501073 csrw    mtvec,x0'
Error (IDV) CSR register value mismatch (HartId:0, PC:0x20000080 rvtest_entry_point+0):
Error (IDV) Mismatch 0> CSR 305 (mtvec)
Error (IDV)   . dut:0x20000001 BASE:0x20000000 MODE:1(Vectored) (not updated)
Error (IDV)   . ref:0x00000000 BASE:0x0 MODE:0(Direct)

If we add a nop before the csr clear then we do not see the issue anymore.

nop;
csrw  mtvec, x0;

[silabs-kjetil]

It looks like there is something missing in the sensitivity list for updating the CSR state here https://github.com/openhwgroup/cv32e40x-dv/blob/main/tb/uvmt/uvmt_cv32e40x_imperas_dv_wrap.sv#L39. If I for instance add the wmask and rmask to the sensitivity list then I do not see the issue anymore.

It looks like the block does not detect the change in value because the csr_mtvec_w signal does not change value when the mtvec csr is cleared.