From 54176118fe04c873d8c05d1a0e7789bc42e2a66c Mon Sep 17 00:00:00 2001 From: Ravi Sahita Date: Tue, 26 Mar 2024 11:38:46 -0700 Subject: [PATCH] Apply suggestions from PR review Signed-off-by: Ravi Sahita --- chapter8.adoc | 5 +++++ example.bib | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/chapter8.adoc b/chapter8.adoc index f18b863..b42b3d7 100644 --- a/chapter8.adoc +++ b/chapter8.adoc @@ -9,6 +9,11 @@ software running on a separate target RISC-V platform, via a trace control/data transport that provides external access to the trace encoder controls cite:[ETrc]. This extension only affects debug or trace orchestrated by an external actor. Self-hosted debug (and trace) are managed by the RDSM. +This sub-specification refers to the Debug specification cite:[ExtDbg], +Trace specification cite:[ETrc], and the External debug security extension +cite:[ExtDbgSec] for the description and behavior of controls outside +the scope of this specification, but which interact with controls +specified in this specification when supervisor domains are used. === `Smsdedbg`: External Debug allowed control for Supervisor Domain diff --git a/example.bib b/example.bib index 0ed2eaa..d2a731d 100644 --- a/example.bib +++ b/example.bib @@ -29,6 +29,11 @@ @electronic{ETrc url = {https://github.com/riscv-non-isa/riscv-trace-spec/releases/download/v2.0.2/riscv-trace-spec-asciidoc.pdf} } +@electronic{ExtDbgSec, + title = {RISC-V External Debug Security, v0.0, March 26, 2024}, + url = {https://github.com/riscv-non-isa/riscv-external-debug-security/blob/main/external-debug-security.pdf} +} + @electronic{CBQRI, title = {RISC-V Capacity and Bandwidth Controller QoS Register Interface}, url = {https://github.com/riscv-non-isa/riscv-cbqri}