Wishbone bus interface?

[drom]

@mithro : Most open cores use the wishbone interface. Do you have an bus definition for that?

[mithro]

I have not created a DUH bus definition for wishbone. I was sure I commented on an issue related to DUH about wishbone....

[mithro]

Well apparently it was https://github.com/sifive/duh/issues/38 but now I get an error This issue has been moved to a repository you don't have access to.

[mithro]

Is this the latest spec? https://cdn.opencores.org/downloads/wbspec_b4.pdf

[mithro]

More info seems to be at https://opencores.org/howto/wishbone

[drom]

yes. that was my fault. I have to demolish previous repo. Will work on this issue soon.

[drom]

@olofk what is correct VLNV string for Wishbone interface?

[drom]

fixed here: https://github.com/sifive/duh-bus/blob/master/specs/opencores.org/wishbone/B4/1.0.0/B4_rtl.json5

[olofk]

Missed this thread. Wishbone is handled by FOSSi Foundation nowadays so the correct vendor would be fossi-foundation.org The latest official version is B3.1 which we released recently. I would recommend going with that (unless you absolutely need the delayed ack from B4) since B4 never was a sanctioned release

[drom]

Sure. Could you point me to the B3.1 spec PDF? I see RC1 here: https://github.com/fossi-foundation/wishbone/releases
What VLNV would you recommend? fossi-foundation.org/wishbone/B3/3.1.0 ?

[olofk]

My bad. I thought it was already released. It's a minor release though, so let's just stick with B3 instead. This is the official spec URL https://wishbone-interconnect.org/assets/wishbone-b3.pdf
As for the VLNV I would go for fossi-foundation.org:wishbone:wishbone:B.3.

[drom]

Here is a new version:
https://github.com/sifive/duh-bus/blob/master/specs/fossi-foundation.org/wishbone/wishbone/B.3/wishbone_rtl.json5

Here are some diagrams: https://observablehq.com/@drom/bus-definition-diagram

I have to create a logical wire name that connects physical ports to support the cross-over nature of the Wishbone.

How do you like it so far?