diff --git a/src/crc.rs b/src/crc.rs index 1943205..ff1a9f9 100644 --- a/src/crc.rs +++ b/src/crc.rs @@ -21,7 +21,6 @@ use crate::rcc::{Enable, Rcc, Reset}; use crate::stm32::CRC; use core::hash::Hasher; -use core::ptr; /// Extension trait to constrain the CRC peripheral. pub trait CrcExt { @@ -174,11 +173,8 @@ impl Crc { pub fn feed(&mut self, data: &[u8]) { let crc = unsafe { &(*CRC::ptr()) }; for byte in data { - unsafe { - // Workaround with svd2rust, it does not generate the byte interface to the DR - // register - ptr::write_volatile(&crc.dr as *const _ as *mut u8, *byte); - } + let ptr = &crc.dr as *const _; + unsafe { core::ptr::write_volatile(ptr as *mut u8, *byte) }; } } diff --git a/src/gpio.rs b/src/gpio.rs index c77dc65..c2755a4 100644 --- a/src/gpio.rs +++ b/src/gpio.rs @@ -445,9 +445,9 @@ macro_rules! gpio { let _ = &(*$GPIOX::ptr()).pupdr.modify(|r, w| { w.bits(r.bits() & !(0b11 << offset)) }); - &(*$GPIOX::ptr()).moder.modify(|r, w| { + let _ = &(*$GPIOX::ptr()).moder.modify(|r, w| { w.bits(r.bits() & !(0b11 << offset)) - }) + }); }; let offset = ($i % 4) * 8; let mask = $Pxn << offset; @@ -475,9 +475,9 @@ macro_rules! gpio { pub fn set_speed(self, speed: Speed) -> Self { let offset = 2 * $i; unsafe { - &(*$GPIOX::ptr()).ospeedr.modify(|r, w| { + let _ = &(*$GPIOX::ptr()).ospeedr.modify(|r, w| { w.bits((r.bits() & !(0b11 << offset)) | ((speed as u32) << offset)) - }) + }); }; self } diff --git a/src/spi.rs b/src/spi.rs index bab5130..69290c7 100644 --- a/src/spi.rs +++ b/src/spi.rs @@ -264,8 +264,8 @@ macro_rules! spi { } else if sr.crcerr().bit_is_set() { nb::Error::Other(Error::Crc) } else if sr.txe().bit_is_set() { - // NOTE(write_volatile) see note above - unsafe { ptr::write_volatile(&self.spi.dr as *const _ as *mut u8, byte) } + let ptr = &self.spi.dr as *const _; + unsafe { core::ptr::write_volatile(ptr as *mut u8, byte) }; return Ok(()); } else { nb::Error::WouldBlock