From 05a07e2a33c2973f9d1598b1ee6d816888ad1964 Mon Sep 17 00:00:00 2001 From: Mes Date: Sat, 14 Dec 2024 05:12:24 +0800 Subject: [PATCH] set the default option from ACLINT to CLINT - Added a flag `ENABLE_ACLINT` in the Makefile, allowing users to choose whether to enable ACLINT. By default, ACLINT is disabled (inspired by QEMU). If enabled, ACLINT will be used instead of CLINT. - Introduced `OBJS_IR_CTRL` in the Makefile, including `plic.o` in it, and conditionally compiling either `aclint.o` or `clint.o` based on the state of the `ENABLE_ACLINT` flag. - Changed the default script for generating the device-tree configuration to the CLINT version, and adjusted the script selection based on whether ACLINT is enabled. - Remove the macro `SEMU_FEATURE_ACLINT` in feature.h --- Makefile | 19 +++++-- feature.h | 5 -- .../{gen-clint-dts.py => gen-aclint-dts.py} | 49 +++++++++++++++---- scripts/gen-hart-dts.py | 49 ++++--------------- 4 files changed, 65 insertions(+), 57 deletions(-) rename scripts/{gen-clint-dts.py => gen-aclint-dts.py} (51%) diff --git a/Makefile b/Makefile index 24980d4c..1c36d206 100644 --- a/Makefile +++ b/Makefile @@ -43,6 +43,16 @@ ifeq ($(call has, VIRTIONET), 1) OBJS_EXTRA += netdev.o endif +# Interrupt Controller +OBJS_IR_CTRL := plic.o +ENABLE_ACLINT ?= 0 +$(call set-feature, ACLINT) +ifeq ($(call has, ACLINT), 1) + OBJS_IR_CTRL += aclint.o +else + OBJS_IR_CTRL += clint.o +endif + BIN = semu all: $(BIN) minimal.dtb @@ -50,11 +60,10 @@ OBJS := \ riscv.o \ ram.o \ utils.o \ - plic.o \ uart.o \ main.o \ - aclint.o \ - $(OBJS_EXTRA) + $(OBJS_IR_CTRL) \ + $(OBJS_EXTRA) deps := $(OBJS:%.o=.%.o.d) @@ -80,7 +89,11 @@ S := $E $E SMP ?= 1 .PHONY: riscv-harts.dtsi riscv-harts.dtsi: +ifeq ($(call has, ACLINT), 1) + $(Q)python3 scripts/gen-aclint-dts.py $@ $(SMP) $(CLOCK_FREQ) +else $(Q)python3 scripts/gen-hart-dts.py $@ $(SMP) $(CLOCK_FREQ) +endif minimal.dtb: minimal.dts riscv-harts.dtsi $(VECHO) " DTC\t$@\n" diff --git a/feature.h b/feature.h index 810fb3c7..1dee984a 100644 --- a/feature.h +++ b/feature.h @@ -12,10 +12,5 @@ #define SEMU_FEATURE_VIRTIONET 1 #endif -/* ACLINT */ -#ifndef SEMU_FEATURE_ACLINT -#define SEMU_FEATURE_ACLINT 1 -#endif - /* Feature test macro */ #define SEMU_HAS(x) SEMU_FEATURE_##x diff --git a/scripts/gen-clint-dts.py b/scripts/gen-aclint-dts.py similarity index 51% rename from scripts/gen-clint-dts.py rename to scripts/gen-aclint-dts.py index 22df971d..03cebbc1 100644 --- a/scripts/gen-clint-dts.py +++ b/scripts/gen-aclint-dts.py @@ -27,14 +27,26 @@ def plic_irq_format(nums): for i in range(nums): s += f"<&cpu{i}_intc 9>, " return s[:-2] - -def clint_irq_format(nums): + +def sswi_irq_format(nums): + s = "" + for i in range(nums): + s += f"<&cpu{i}_intc 1>, " # 1 is the SSWI interrupt number (Supervisor Software Interrupt) + return s[:-2] + +def mswi_irq_format(nums): + s = "" + for i in range(nums): + s += f"<&cpu{i}_intc 3>, " # 3 is the MSWI interrupt number (Machine Software Interrupt) + return s[:-2] + +def mtimer_irq_format(nums): s = "" for i in range(nums): - s += f"<&cpu{i}_intc 3 &cpu{i}_intc 7>, " + s += f"<&cpu{i}_intc 7>, " # 7 is the MTIMER interrupt number (Machine Timer Interrupt) return s[:-2] -def dtsi_template (cpu_list: str, plic_list, clint_list, clock_freq): +def dtsi_template (cpu_list: str, plic_list, sswi_list, mtimer_list, mswi_list, clock_freq): return f"""/{{ cpus {{ #address-cells = <1>; @@ -54,11 +66,28 @@ def dtsi_template (cpu_list: str, plic_list, clint_list, clock_freq): riscv,ndev = <31>; }}; - clint0: clint@4300000 {{ - compatible = "riscv,clint0"; - interrupts-extended = - {clint_list}; - reg = <0x4300000 0x10000>; + sswi0: sswi@4500000 {{ + #interrupt-cells = <0>; + #address-cells = <0>; + interrupt-controller; + interrupts-extended = {sswi_list}; + reg = <0x4500000 0x4000>; + compatible = "riscv,aclint-sswi"; + }}; + + mswi0: mswi@4400000 {{ + #interrupt-cells = <0>; + #address-cells = <0>; + interrupt-controller; + interrupts-extended = {mswi_list}; + reg = <0x4400000 0x4000>; + compatible = "riscv,aclint-mswi"; + }}; + + mtimer0: mtimer@4300000 {{ + interrupts-extended = {mtimer_list}; + reg = <0x4300000 0x8000>; + compatible = "riscv,aclint-mtimer"; }}; }}; }}; @@ -69,4 +98,4 @@ def dtsi_template (cpu_list: str, plic_list, clint_list, clock_freq): clock_freq = int(sys.argv[3]) with open(dtsi, "w") as dts: - dts.write(dtsi_template(cpu_format(harts), plic_irq_format(harts), clint_irq_format(harts), clock_freq)) + dts.write(dtsi_template(cpu_format(harts), plic_irq_format(harts), sswi_irq_format(harts), mswi_irq_format(harts), mtimer_irq_format(harts), clock_freq)) diff --git a/scripts/gen-hart-dts.py b/scripts/gen-hart-dts.py index 178ec4bf..22df971d 100644 --- a/scripts/gen-hart-dts.py +++ b/scripts/gen-hart-dts.py @@ -27,26 +27,14 @@ def plic_irq_format(nums): for i in range(nums): s += f"<&cpu{i}_intc 9>, " return s[:-2] - -def sswi_irq_format(nums): - s = "" - for i in range(nums): - s += f"<&cpu{i}_intc 1>, " # 1 is the SSWI interrupt number (Supervisor Software Interrupt) - return s[:-2] - -def mswi_irq_format(nums): - s = "" - for i in range(nums): - s += f"<&cpu{i}_intc 3>, " # 3 is the MSWI interrupt number (Machine Software Interrupt) - return s[:-2] - -def mtimer_irq_format(nums): + +def clint_irq_format(nums): s = "" for i in range(nums): - s += f"<&cpu{i}_intc 7>, " # 7 is the MTIMER interrupt number (Machine Timer Interrupt) + s += f"<&cpu{i}_intc 3 &cpu{i}_intc 7>, " return s[:-2] -def dtsi_template (cpu_list: str, plic_list, sswi_list, mtimer_list, mswi_list, clock_freq): +def dtsi_template (cpu_list: str, plic_list, clint_list, clock_freq): return f"""/{{ cpus {{ #address-cells = <1>; @@ -66,28 +54,11 @@ def dtsi_template (cpu_list: str, plic_list, sswi_list, mtimer_list, mswi_list, riscv,ndev = <31>; }}; - sswi0: sswi@4500000 {{ - #interrupt-cells = <0>; - #address-cells = <0>; - interrupt-controller; - interrupts-extended = {sswi_list}; - reg = <0x4500000 0x4000>; - compatible = "riscv,aclint-sswi"; - }}; - - mswi0: mswi@4400000 {{ - #interrupt-cells = <0>; - #address-cells = <0>; - interrupt-controller; - interrupts-extended = {mswi_list}; - reg = <0x4400000 0x4000>; - compatible = "riscv,aclint-mswi"; - }}; - - mtimer0: mtimer@4300000 {{ - interrupts-extended = {mtimer_list}; - reg = <0x4300000 0x8000>; - compatible = "riscv,aclint-mtimer"; + clint0: clint@4300000 {{ + compatible = "riscv,clint0"; + interrupts-extended = + {clint_list}; + reg = <0x4300000 0x10000>; }}; }}; }}; @@ -98,4 +69,4 @@ def dtsi_template (cpu_list: str, plic_list, sswi_list, mtimer_list, mswi_list, clock_freq = int(sys.argv[3]) with open(dtsi, "w") as dts: - dts.write(dtsi_template(cpu_format(harts), plic_irq_format(harts), sswi_irq_format(harts), mswi_irq_format(harts), mtimer_irq_format(harts), clock_freq)) \ No newline at end of file + dts.write(dtsi_template(cpu_format(harts), plic_irq_format(harts), clint_irq_format(harts), clock_freq))