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Xilinx - UG086 - Memory Interface Solutions User Guide
Chapter 7 describes the MIG DDR SDRAM implementation for Spartan-3E. This is probably the best place to get started.
The source code of a MIG-generated DDR SDRAM controller for the Pano Logic Spartan-3E can be found here.
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Xilinx - XAPP802 - Memory Interface Application Notes Overview
An overview of all Xilinx memory interface application notes.
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Xilinx - Synthesizable 400 Mb/s DDR SDRAM Controller
Contains detailed DCM implementation details for a Virtex-2 FPGA, which should be pretty similar to Spartan-3E.
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Xilinx - System Interface Timing Parameters
Talks about analysis of source synchronous interfaces such as DDR.
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Xilinx - DDR SDRAM Controller Using Virtex-5 FPGA Devices - Read Data Capture Timing Calibration
How to transfer data from DQ capture flops to internal clock domain.
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Xilinx - UG608 - Spartan-3 Libraries Guide for Schematic Design
Describes the low level cells that can be used in an Spartan-3 design. For example, a RAM64X1S cell or a MULT18X18S cell.
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Xilinx - XAPP485 - 1:7 Deserialization in Spartan-3E/3A FPGAs at Speeds Up to 666 Mbps
Not directly related to DDR, but it shows how you can design an LVDS interface with a DCM phase shifter to get the right data.
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Micron TN0454 - High Speed DRAM Controller Design
Convers tons of aspects about how to design DRAM controllers.
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Fastest and slowest tAC and tDQSCK timing diagrams for Micron chip: see page 84 of datasheet.
When running at fastest speed, in both cases, the risign edge of DQS falls between the same CK rising edges (at the DRAM side!), but it's close.
There needs to be logic to compensate for this. (This logic has nothing to do with adding a 90 degree delay to DQS to capture the data at the receive side.)
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SpinalHDL Example SDRAM Controller
Doesn't do DDR. Only SDR.
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FreeCores Spartan 3E DDR Controller
Uses DDR IOs and DCM to create phase clocks, but doesn't use DQS on input: that just gets ignored. Probably still good enough for slower speeds?
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The Love/Hate Relationship with DDR SDRAM Controllers
Interesting the history of DLL, DQS etc. in SDRAMs: why DQS is aligned the way it is for reads and writes etc.
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Implementing an all-digital PHY and delay-locked loop for high-speed DDR2/3 memory interfaces
Talks about master/slave DLL configuration.
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Lattice LPDDR SDRAM Controller
This data sheet of an LPDDR controller talks about read retraining due to lack of DLL inside the SDRAM. Every so many auto-refresh cycles, it does a bunch of reads and writes to a reserved location in DRAM location to retrain the settings.
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Lattice DDR Interface Design Implementation White Paper
Talks about how to implement a DDR interface with DLLs etc.
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High-Bandwidth Memory Interface Design
Excellent course presentation about various aspects of DRAM design.
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Synchronous DRAM Architectures, Organizations, and Alternative Technologies
Overview of different DRAM architectures. Definitely dated (2002) but talks about DLLs etc.
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Hynix DDR3 SDRAM Device Operation
Really interesting documentation with lot of detail about DDR3 operation. See page 25 of info about DLL-off operation, which is essentially the same as LPDDR operation.