New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Annotate Fixedpoint binary points in Verilog #94

Open

shunshou opened this issue Apr 26, 2017 · 0 comments

Member

shunshou commented Apr 26, 2017

(Is there some way to annotate binary points in Verilog and have your simulator of choice automatically pick it up?)

grebe mentioned this issue

Add width and binary point to fixed point names chipsalliance/firrtl#555

Closed

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment