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base repository: TUD-OS/M3
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head repository: utcs-scea/M3
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  • 4 commits
  • 15 files changed
  • 1 contributor

Commits on Oct 6, 2020

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    1d5e16c View commit details
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Commits on Oct 7, 2020

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Commits on Dec 1, 2020

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3 changes: 2 additions & 1 deletion .gitmodules
Original file line number Diff line number Diff line change
@@ -3,4 +3,5 @@
url = os.inf.tu-dresden.de:/home/nils/tomahawk.git
[submodule "hw/gem5"]
path = hw/gem5
url = https://github.com/TUD-OS/gem5-dtu.git
branch = master
url = https://github.com/utcs-scea/gem5-dtu.git
2 changes: 2 additions & 0 deletions src/apps/fstrace/linux/fsapi_posix.h
Original file line number Diff line number Diff line change
@@ -26,6 +26,8 @@
#include "exceptions.h"
#include "fsapi.h"

constexpr long SYS_getdents = SYS_getdents64;

class FSAPI_POSIX : public FSAPI {
enum { MaxOpenFds = 512 };

2 changes: 2 additions & 0 deletions src/include/base/CPU.h
Original file line number Diff line number Diff line change
@@ -48,4 +48,6 @@ class CPU {
# include <base/arch/x86_64/CPU.h>
#elif defined(__arm__)
# include <base/arch/arm/CPU.h>
#elif defined(__aarch64__)
# include <base/arch/aarch64/CPU.h>
#endif
2 changes: 2 additions & 0 deletions src/include/base/Exceptions.h
Original file line number Diff line number Diff line change
@@ -23,6 +23,8 @@
# include <base/arch/x86_64/ExceptionState.h>
#elif defined(__arm__)
# include <base/arch/arm/ExceptionState.h>
#elif defined(__aarch64__)
# include <base/arch/aarch64/ExceptionState.h>
#else
# error "Unsupported ISA"
#endif
78 changes: 78 additions & 0 deletions src/include/base/arch/aarch64/CPU.h
Original file line number Diff line number Diff line change
@@ -0,0 +1,78 @@
/*
* Copyright (C) 2016-2018, Nils Asmussen <nils@os.inf.tu-dresden.de>
* Economic rights: Technische Universitaet Dresden (Germany)
*
* This file is part of M3 (Microkernel-based SysteM for Heterogeneous Manycores).
*
* M3 is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* M3 is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License version 2 for more details.
*/

#pragma once

#include <base/Common.h>
#include <base/CPU.h>

namespace m3 {

inline uint64_t CPU::read8b(uintptr_t addr) {
uint64_t res;
asm volatile (
"ldr %0, [%1]"
: "=r"(res)
: "r"(addr)
);
return res;
}

inline void CPU::write8b(uintptr_t addr, uint64_t val) {
asm volatile (
"str %0, [%1]"
: : "r"(val), "r"(addr)
);
}

inline word_t CPU::get_sp() {
word_t val;
asm volatile (
"mov %0, x31;"
: "=r" (val)
);
return val;
}

inline void CPU::jumpto(uintptr_t addr) {
asm volatile (
"blx %0"
:
: "r"(addr)
);
UNREACHED;
}

inline void CPU::compute(cycles_t cycles) {
asm volatile (
"1: subs %0, %0, #1;"
"bgt 1b;"
// let the compiler know that we change the value of cycles
// as it seems, inputs are not expected to change
: "=r"(cycles) : "0"(cycles)
);
}

inline void CPU::memory_barrier() {
asm volatile (
"dmb"
:
:
: "memory"
);
}

}
2 changes: 2 additions & 0 deletions src/include/thread/Thread.h
Original file line number Diff line number Diff line change
@@ -24,6 +24,8 @@
# include <thread/isa/x86_64/Thread.h>
#elif defined(__arm__)
# include <thread/isa/arm/Thread.h>
#elif defined(__aarch64__)
# include <thread/isa/aarch64/Thread.h>
#else
# error "Unsupported ISA"
#endif
40 changes: 40 additions & 0 deletions src/include/thread/isa/aarch64/Thread.h
Original file line number Diff line number Diff line change
@@ -0,0 +1,40 @@
#pragma once

#ifdef __cplusplus
#include <base/Types.h>

namespace m3 {

typedef void (*_thread_func)(void*);

struct Regs {
word_t x0;
word_t x19;
word_t x20;
word_t x21;
word_t x22;
word_t x23;
word_t x24;
word_t x25;
word_t x26;
word_t x27;
word_t x28;
word_t fp; //x29
word_t lr; //x30
word_t sp; //x31
word_t DAIF;
word_t NZCV;
};

enum {
T_STACK_WORDS = 512
//T_STACK_WORDS = 1024
};

void thread_init(_thread_func func, void *arg, Regs *regs, word_t *stack);
extern "C" bool thread_save(Regs *regs);
extern "C" bool thread_resume(Regs *regs);

}

#endif
41 changes: 41 additions & 0 deletions src/libs/base/arch/aarch64/Backtrace.cc
Original file line number Diff line number Diff line change
@@ -0,0 +1,41 @@
/*
* Copyright (C) 2016, Nils Asmussen <nils@os.inf.tu-dresden.de>
* Economic rights: Technische Universitaet Dresden (Germany)
*
* This file is part of M3 (Microkernel-based SysteM for Heterogeneous Manycores).
*
* M3 is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* M3 is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License version 2 for more details.
*/

#include <base/util/Math.h>
#include <base/Backtrace.h>
#include <base/Config.h>
#include <base/CPU.h>

namespace m3 {

size_t Backtrace::collect(uintptr_t *addr, size_t max) {
uintptr_t fp;
asm volatile ("mov %0, x29;" : "=r" (fp));

uintptr_t base = Math::round_dn<uintptr_t>(fp, STACK_SIZE);
uintptr_t end = Math::round_up<uintptr_t>(fp, STACK_SIZE);
uintptr_t start = end - STACK_SIZE;

size_t i = 0;
for(; fp >= start && fp < end && i < max; ++i) {
fp = base + (fp & (STACK_SIZE - 1));
addr[i] = reinterpret_cast<uintptr_t*>(fp)[0] - 4;
fp = reinterpret_cast<uintptr_t*>(fp)[-1];
}
return i;
}

}
2 changes: 1 addition & 1 deletion src/libs/base/arch/host/Time.cc
Original file line number Diff line number Diff line change
@@ -29,7 +29,7 @@ cycles_t Time::stop(unsigned) {
uint32_t u, l;
asm volatile ("rdtsc" : "=a" (l), "=d" (u) : : "memory");
return static_cast<cycles_t>(u) << 32 | l;
#elif defined(__arm__)
#elif defined(__arm__) or defined(__aarch64__)
struct timeval tv;
gettimeofday(&tv,nullptr);
return static_cast<cycles_t>(tv.tv_sec) * 1000000 + static_cast<cycles_t>(tv.tv_usec);
67 changes: 67 additions & 0 deletions src/libs/rustbase/src/arch/aarch64/cpu.rs
Original file line number Diff line number Diff line change
@@ -0,0 +1,67 @@
use time;

pub fn read8b(addr: usize) -> u64 {
let res: u64;
unsafe {
asm!(
"ldr $0, [$1]"
: "=r"(res)
: "r"(addr)
: : "volatile"
);
}
res
}

pub fn write8b(addr: usize, val: u64) {
unsafe {
asm!(
"str $0, [$1]"
: : "r"(val), "r"(addr)
: : "volatile"
);
}
}

pub fn get_sp() -> usize {
let res: usize;
unsafe {
asm!(
"mov $0, x31;"
: "=r"(res)
);
}
res
}

pub fn get_bp() -> usize {
let val: usize;
unsafe {
asm!(
"mov $0, x29;"
: "=r"(val)
);
}
val
}

pub fn jmp_to(addr: usize) {
unsafe {
asm!(
"mov pc, $0;"
: : "r"(addr)
: : "volatile"
);
}
}

pub fn gem5_debug(msg: usize) -> time::Time {
let mut res = msg as time::Time;
unsafe {
asm!(
".long 0xEE630110"
: "+{r0}"(res)
);
}
res
}
1 change: 1 addition & 0 deletions src/libs/rustbase/src/arch/aarch64/mod.rs
Original file line number Diff line number Diff line change
@@ -0,0 +1 @@
pub mod cpu;
13 changes: 13 additions & 0 deletions src/libs/rustbase/src/arch/host/time.rs
Original file line number Diff line number Diff line change
@@ -16,6 +16,7 @@

use time;

#[cfg(target_arch = "x86_64")]
fn rdtsc() -> time::Time {
let u: u32;
let l: u32;
@@ -28,6 +29,18 @@ fn rdtsc() -> time::Time {
(u as time::Time) << 32 | (l as time::Time)
}

//We hope that the OS has enabled cntvct_e10
#[cfg(target_arch = "aarch64")]
fn rdtsc() -> time::Time
{
let t: time::Time;
unsafe
{
asm!("mrs $0, cntvct_e10" : "=r"(t));
}
return t;
}

pub fn start(_msg: usize) -> time::Time {
rdtsc()
}
34 changes: 34 additions & 0 deletions src/libs/rustthread/src/lib.rs
Original file line number Diff line number Diff line change
@@ -51,6 +51,29 @@ pub struct Regs {
rdi: u64,
}

#[cfg(target_arch = "aarch64")]
#[derive(Default)]
#[repr(C, packed)]
pub struct Regs
{
x0: u64,
x19: u64,
x20: u64,
x21: u64,
x22: u64,
x23: u64,
x24: u64,
x25: u64,
x26: u64,
x27: u64,
x28: u64,
fp: u64, //x29
lr: u64, //x30
sp: u64, //x31
DAIF: u64,
NZCV: u64,
}

#[cfg(target_arch = "arm")]
#[derive(Default)]
#[repr(C, packed)]
@@ -80,6 +103,17 @@ fn thread_init(thread: &mut Thread, func_addr: usize, arg: usize) {
thread.regs.rflags = 0x200; // enable interrupts
}

#[cfg(target_arch = "aarch64")]
fn thread_init(thread: &mut Thread, func_addr: usize, arg: usize) {
thread.regs.x0 = arg as u64; // arg
let top_idx = thread.stack.len() - 2;
thread.regs. sp = &thread.stack[top_idx] as *const usize as u64; // sp
thread.regs. fp = 0; // fp
thread.regs. lr = func_addr as u64; // lr
thread.regs.DAIF = 0x0; // Enable interrupts
thread.regs.NZCV = 0x0; // Clear all flags
}

#[cfg(target_arch = "arm")]
fn thread_init(thread: &mut Thread, func_addr: usize, arg: usize) {
thread.regs.r0 = arg as u32; // arg
30 changes: 30 additions & 0 deletions src/libs/thread/isa/aarch64/Thread.cc
Original file line number Diff line number Diff line change
@@ -0,0 +1,30 @@
/*
* Copyright (C) 2016, Nils Asmussen <nils@os.inf.tu-dresden.de>
* Economic rights: Technische Universitaet Dresden (Germany)
*
* This file is part of M3 (Microkernel-based SysteM for Heterogeneous Manycores).
*
* M3 is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* M3 is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License version 2 for more details.
*/

#include <thread/Thread.h>

namespace m3 {

void thread_init(Thread::thread_func func, void *arg, Regs *regs, word_t *stack) {
regs-> x0 = reinterpret_cast<word_t>(arg); // arg
regs-> sp = reinterpret_cast<word_t>(stack + T_STACK_WORDS - 2); // sp
regs-> fp = 0; // fp
regs-> lr = reinterpret_cast<word_t>(func); // lr
regs->DAIF = 0; // interrupts enabled
regs->NZCV = 0;
}

}
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