From 68e413f7178564a44065a67e2944d8615c5a33f4 Mon Sep 17 00:00:00 2001
From: Wenting Zhang <zephray@outlook.com>
Date: Sun, 14 Apr 2019 11:34:59 -0400
Subject: [PATCH] target-panog1: adjust vga timing; add cartridge ram

---
 target/panog1/fpga/pano_top.v   | 33 ++++++++++++++++++++++++++++-----
 target/panog1/fpga/vga_timing.v |  7 ++++---
 2 files changed, 32 insertions(+), 8 deletions(-)

diff --git a/target/panog1/fpga/pano_top.v b/target/panog1/fpga/pano_top.v
index 8540d2e..590caff 100644
--- a/target/panog1/fpga/pano_top.v
+++ b/target/panog1/fpga/pano_top.v
@@ -266,6 +266,9 @@ module pano_top(
     // ----------------------------------------------------------------------
     // MBC5
     wire [22:0] vb_rom_a;
+    wire [16:0] vb_ram_a;
+    wire vb_ram_cs_n;
+    wire [7:0] vb_crom_dout;
     mbc5 mbc5(
         .vb_clk(clk_4),
         .vb_a(vb_a[15:12]),
@@ -274,11 +277,31 @@ module pano_top(
         .vb_rd(vb_rd),
         .vb_rst(vb_rst),
         .rom_a(vb_rom_a[22:14]),
-        .ram_a(),
+        .ram_a(vb_ram_a[16:13]),
         .rom_cs_n(),
-        .ram_cs_n()
+        .ram_cs_n(vb_ram_cs_n)
     );
     assign vb_rom_a[13:0] = vb_a[13:0];
+    assign vb_ram_a[12:0] = vb_a[12:0];
+    
+    // ----------------------------------------------------------------------
+    // Cartridge RAM
+    // Work RAM
+    wire [7:0] vb_cram_dout;
+    wire vb_cram_wr = !vb_ram_cs_n & vb_wr;
+
+    singleport_ram #(
+        .WORDS(32768),
+        .ABITS(15)
+    ) br_cram (
+        .clka(clk_4),
+        .wea(vb_cram_wr),
+        .addra(vb_ram_a[14:0]),
+        .dina(vb_dout),
+        .douta(vb_cram_dout)
+    );
+    
+    assign vb_din = (vb_ram_cs_n) ? (vb_crom_dout) : (vb_cram_dout);
     
     // ----------------------------------------------------------------------
     // Audio
@@ -448,9 +471,9 @@ module pano_top(
         .ddr_valid(ddr_valid),
         .ddr_ready(ddr_ready),
         .vb_a(vb_rom_a),
-        .vb_din(vb_din),
-        .vb_dout(vb_dout),
-        .vb_rd(vb_rd),
+        .vb_din(vb_crom_dout),
+        .vb_dout(8'h00),
+        .vb_rd(vb_phi),
         .vb_wr(1'b0)
     );
     
diff --git a/target/panog1/fpga/vga_timing.v b/target/panog1/fpga/vga_timing.v
index 976bb3d..89eb63c 100644
--- a/target/panog1/fpga/vga_timing.v
+++ b/target/panog1/fpga/vga_timing.v
@@ -36,7 +36,8 @@ module vga_timing(
     );
 
     //Horizontal
-    parameter H_FRONT   = 26; //Front porch
+    // Sync is adjusted to compensate lower clock frequency
+    parameter H_FRONT   = 18; //Front porch
     parameter H_SYNC    = 96; //Sync
     parameter H_BACK    = 38; //Back porch
     /*parameter H_FRONT   = 16; //Front porch
@@ -139,11 +140,11 @@ module vga_timing(
 
     assign x = (h_count >= H_BLANK) ? (h_count - H_BLANK) : 11'h0;
     assign y = (v_count >= V_BLANK) ? (v_count - V_BLANK) : 11'h0;
-    wire gb_x_valid = (x > 11'd80)&&(x <= 11'd560);
+    wire gb_x_valid = (x > 11'd78)&&(x <= 11'd558);
     wire gb_y_valid = (y >= 11'd24)&&(y < 11'd456);
     assign gb_en = (gb_x_valid)&&(gb_y_valid);
     assign gb_grid = (gb_x_grid)||(gb_y_grid);
-    assign gb_x = (gb_en) ? (gb_x_count - 8'd80) : (8'h0);
+    assign gb_x = (gb_en) ? (gb_x_count - 8'd77) : (8'h0);
     //assign gb_y = (gb_en) ? (gb_y_count - 8'd24) : (8'h0);
     assign gb_y = (gb_y_valid) ? (gb_y_count - 8'd23) : (8'h0); // Y should be always available during the period
     //assign address = y * H_ACT + x;