Skip to content
This repository has been archived by the owner on Jun 25, 2018. It is now read-only.

rtl8366_smi: Exclude cpu port from pvid initialization. #1

Open
wants to merge 50 commits into
base: staging
Choose a base branch
from

Conversation

Quallenauge
Copy link

@Quallenauge Quallenauge commented Mar 9, 2017

It causes errors when probing the device, such as:
[ 2.568059] rtl8367b rtl8367b: using bus lantiq,xrx200-mdio
[ 2.572494] rtl8367b rtl8367b: RTL8367RB chip found
[ 4.041784] rtl8367b rtl8367b: VLAN initialization failed, err=1
[ 4.047809] rtl8367b: probe of rtl8367b failed with error 1

Maybe I missed that one on my last test.

13hakta and others added 30 commits February 19, 2017 12:50
Fix indentation and remove superfluous linebreaks.

Signed-off-by: Vitaly Chekryzhev <[email protected]>
Extend rtl8366_smi with chip_ver field for storing chip ID.
Useful for drivers supporting multiple chip versions.
Replace method calls with macro.
Receive chip number and mode only if detection error occured.

Signed-off-by: Vitaly Chekryzhev <[email protected]>
On chip present 2 ports, set CPU port id depending on which external port is configured.

Signed-off-by: Vitaly Chekryzhev <[email protected]>
Driver supports 2 chip versions: RTL8367RB, RTL8367R-VB. Each of them has 2 external ports.
RTL8367RB has ports indexed as 13hakta#1,lede-project#2 (PHY lede-project#6, lede-project#7).
RTL8367R-VB has ports indexed as #0,13hakta#1 (PHY lede-project#5,lede-project#6).
Map ports so that extif0 complies to external port 0 or 1 depending on chip ID.

Signed-off-by: Vitaly Chekryzhev <[email protected]>
Previously rlvid was wrongly converted and for different chip (0x1000, 0x1010)
it was equal 1 what caused loading improper values to RTL8367RB switch.
Load initvals depending on raw chip ID.

Signed-off-by: Vitaly Chekryzhev <[email protected]>
On RTL8367R-VB/RB chips present 2 external ports of maximum 3.
Port lede-project#7 works in RGMII mode only and present only on RTL8367RB.
Ports are numbered sequentially and so port lede-project#5 must be avoided as
only ports 0-4,6,7 are present on board.

Signed-off-by: Vitaly Chekryzhev <[email protected]>
Macro selects by mask all hardware ports for batch operations.

Signed-off-by: Vitaly Chekryzhev <[email protected]>
Add methods managing port abilities such as enabled, speed, green mode.

Signed-off-by: Vitaly Chekryzhev <[email protected]>
Add register and masks for external port lede-project#2
Add RGMII mode support for external port lede-project#2
Rewrite method according API, fix bit with bypass line rate.

Signed-off-by: Vitaly Chekryzhev <[email protected]>
Force enable PHY and external ports at switch setup.
Remove unused definitions and move register init to initval array.
Updated only short array as due to detection bug long array never used.

Signed-off-by: Vitaly Chekryzhev <[email protected]>
Replace long init array for RTL8367R-VB to short array for RTL8367RB.
Previously init always loaded short array for two chip models but
still there is difference among them.

Signed-off-by: Vitaly Chekryzhev <[email protected]>
Update names according to chip names.

Signed-off-by: Vitaly Chekryzhev <[email protected]>
Previously method marked port as not permitted, perform actual port on/off.

Signed-off-by: Vitaly Chekryzhev <[email protected]>
Add register and mask definitions for LED operations
Add LED control methods: group enable, switch serial/parallel mode, set group mode,
get/set blink rate.
Add swconfig methods: get/set group mode, get/set blink rate.
Add LED initialisation

Signed-off-by: Vitaly Chekryzhev <[email protected]>
Add swconfig methods to allow automatically manage port power with Realtek’s
Green Ethernet power saving modes, and Energy Efficient Ethernet (EEE)
mode (defined in IEEE 802.3az), to minimize system power consumption.

Signed-off-by: Vitaly Chekryzhev <[email protected]>
Fix indentation, add missing linebreaks and remove superfluous
linebreaks.

Signed-off-by: Vitaly Chekryzhev <[email protected]>
…acro

Convert method to macro slightly improves performance.

Signed-off-by: Vitaly Chekryzhev <[email protected]>
Switches support two management modes: GPIO driven/MDIO, while MDIO support was missing.
Workaround methods to add direct MDIO support.
Extend 'rtl8366_smi' struct with mdio_enabled flag.
Flag is set if 'mdio' property was found in devicetree, otherwise
switch is controlled via GPIO.

Signed-off-by: Vitaly Chekryzhev <[email protected]>
Remove unneeded cpu port property, update external interface init
according to mapped ports for RTL8267RB:
ext port 13hakta#1 = extif0
ext port lede-project#2 = extif1

Signed-off-by: Vitaly Chekryzhev <[email protected]>
According to external interface mapping extif1 on RTL8367RB becomes
extif0.

Signed-off-by: Vitaly Chekryzhev <[email protected]>
Signed-off-by: Vitaly Chekryzhev <[email protected]>
It causes errors when probing the device.
Fix indentation and remove superfluous linebreaks.

Signed-off-by: Vitaly Chekryzhev <[email protected]>
Extend rtl8366_smi with chip_ver field for storing chip ID.
Useful for drivers supporting multiple chip versions.
Replace method calls with macro.
Receive chip number and mode only if detection error occured.

Signed-off-by: Vitaly Chekryzhev <[email protected]>
On chip present 2 ports, set CPU port id depending on which external port is configured.

Signed-off-by: Vitaly Chekryzhev <[email protected]>
Driver supports 2 chip versions: RTL8367RB, RTL8367R-VB. Each of them has 2 external ports.
RTL8367RB has ports indexed as 13hakta#1,lede-project#2 (PHY lede-project#6, lede-project#7).
RTL8367R-VB has ports indexed as #0,13hakta#1 (PHY lede-project#5,lede-project#6).
Map ports so that extif0 complies to external port 0 or 1 depending on chip ID.

Signed-off-by: Vitaly Chekryzhev <[email protected]>
Previously rlvid was wrongly converted and for different chip (0x1000, 0x1010)
it was equal 1 what caused loading improper values to RTL8367RB switch.
Load initvals depending on raw chip ID.

Signed-off-by: Vitaly Chekryzhev <[email protected]>
13hakta added 4 commits March 22, 2017 20:19
Switches support two management modes: GPIO driven/MDIO, while MDIO support was missing.
Workaround methods to add direct MDIO support.
Extend 'rtl8366_smi' struct with mdio_enabled flag.
Flag is set if 'mdio' property was found in devicetree, otherwise
switch is controlled via GPIO.

Signed-off-by: Vitaly Chekryzhev <[email protected]>
Remove unneeded cpu port property, update external interface init
according to mapped ports for RTL8267RB:
ext port 13hakta#1 = extif0
ext port lede-project#2 = extif1

Signed-off-by: Vitaly Chekryzhev <[email protected]>
According to external interface mapping extif1 on RTL8367RB becomes
extif0.

Signed-off-by: Vitaly Chekryzhev <[email protected]>
Signed-off-by: Vitaly Chekryzhev <[email protected]>
@Quallenauge
Copy link
Author

Without the cpu check patch and adding a printk at the position:
printk("rtl8366_set_pvid: port=%d port+1=%d\n",port,port+1);
err = rtl8366_set_pvid(smi, port, (port + 1));
...
I get the following output:
DTS setting: lantiq,exif0:
[ 3.675970] rtl8366_set_pvid: port=0 port+1=1
[ 3.714521] rtl8366_set_pvid: port=1 port+1=2
[ 3.753551] rtl8366_set_pvid: port=2 port+1=3
[ 3.793103] rtl8366_set_pvid: port=3 port+1=4
[ 3.833179] rtl8366_set_pvid: port=4 port+1=5
[ 3.873752] rtl8366_set_pvid: port=5 port+1=6
[ 3.914568] rtl8366_set_pvid: port=6 port+1=7
[ 3.937875] rtl8367b rtl8367b: VLAN initialization failed, err=1
[ 3.942499] rtl8367b: probe of rtl8367b failed with error 1

DTS setting: lantiq,exif1:
[ 3.676044] rtl8366_set_pvid: port=0 port+1=1
[ 3.714592] rtl8366_set_pvid: port=1 port+1=2
[ 3.753629] rtl8366_set_pvid: port=2 port+1=3
[ 3.793190] rtl8366_set_pvid: port=3 port+1=4
[ 3.833264] rtl8366_set_pvid: port=4 port+1=5
[ 3.873839] rtl8366_set_pvid: port=5 port+1=6
[ 3.914654] rtl8366_set_pvid: port=6 port+1=7
[ 3.956276] rtl8366_set_pvid: port=7 port+1=8
[ 3.980067] rtl8367b rtl8367b: VLAN initialization failed, err=1
[ 3.984690] rtl8367b: probe of rtl8367b failed with error 1

DTS setting: lantiq,exif2:
[ 3.675544] rtl8366_set_pvid: port=0 port+1=1
[ 3.714074] rtl8366_set_pvid: port=1 port+1=2
[ 3.753107] rtl8366_set_pvid: port=2 port+1=3
[ 3.792656] rtl8366_set_pvid: port=3 port+1=4
[ 3.832708] rtl8366_set_pvid: port=4 port+1=5
[ 3.873283] rtl8366_set_pvid: port=5 port+1=6
[ 3.896047] rtl8367b rtl8367b: VLAN initialization failed, err=1
[ 3.900672] rtl8367b: probe of rtl8367b failed with error 1

Do I missing something?

@13hakta
Copy link
Owner

13hakta commented Mar 24, 2017

You've found an issue just at the point where I stopped. The point is that driver covers few devices which have different port combinations. R-VB has ext0,ext1 (port 5,6 or ext 0,1), RB has ext1,ext2 (port 7,8 or ext 1,2). That means that on PVID init must be avoided NON-present port. That's where you catch err=1.
While CPU port is not a port must be avoided, there must be another way. I suppose that it could be some kind of port mask or hardware disabling.

13hakta added a commit that referenced this pull request Apr 16, 2017
Driver supports 2 chip versions: RTL8367RB, RTL8367R-VB. Each of them has 2 external ports.
RTL8367RB has ports indexed as #1,lede-project#2 (PHY lede-project#6, lede-project#7).
RTL8367R-VB has ports indexed as #0,#1 (PHY lede-project#5,lede-project#6).
Map ports so that extif0 complies to external port 0 or 1 depending on chip ID.

Signed-off-by: Vitaly Chekryzhev <[email protected]>
13hakta added a commit that referenced this pull request Apr 16, 2017
Remove unneeded cpu port property, update external interface init
according to mapped ports for RTL8267RB:
ext port #1 = extif0
ext port lede-project#2 = extif1

Signed-off-by: Vitaly Chekryzhev <[email protected]>
13hakta added a commit that referenced this pull request May 16, 2017
Driver supports 2 chip versions: RTL8367RB, RTL8367R-VB. Each of them has 2 external ports.
RTL8367RB has ports indexed as #1,lede-project#2 (PHY lede-project#6, lede-project#7).
RTL8367R-VB has ports indexed as #0,#1 (PHY lede-project#5,lede-project#6).
Map ports so that extif0 complies to external port 0 or 1 depending on chip ID.

Signed-off-by: Vitaly Chekryzhev <[email protected]>
13hakta added a commit that referenced this pull request May 16, 2017
Remove unneeded cpu port property, update external interface init
according to mapped ports for RTL8267RB:
ext port #1 = extif0
ext port lede-project#2 = extif1

Signed-off-by: Vitaly Chekryzhev <[email protected]>
13hakta added a commit that referenced this pull request Jun 17, 2018
Driver supports 2 chip versions: RTL8367RB, RTL8367R-VB. Each of them has 2 external ports.
RTL8367RB has ports indexed as #1,lede-project#2 (PHY lede-project#6, lede-project#7).
RTL8367R-VB has ports indexed as #0,#1 (PHY lede-project#5,lede-project#6).
Map ports so that extif0 complies to external port 0 or 1 depending on chip ID.

Signed-off-by: Vitaly Chekryzhev <[email protected]>
13hakta added a commit that referenced this pull request Jun 17, 2018
Remove unneeded cpu port property, update external interface init
according to mapped ports for RTL8267RB:
ext port #1 = extif0
ext port lede-project#2 = extif1

Signed-off-by: Vitaly Chekryzhev <[email protected]>
13hakta added a commit that referenced this pull request Jun 17, 2018
Driver supports 2 chip versions: RTL8367RB, RTL8367R-VB. Each of them has 2 external ports.
RTL8367RB has ports indexed as #1,lede-project#2 (PHY lede-project#6, lede-project#7).
RTL8367R-VB has ports indexed as #0,#1 (PHY lede-project#5,lede-project#6).
Map ports so that extif0 complies to external port 0 or 1 depending on chip ID.

Signed-off-by: Vitaly Chekryzhev <[email protected]>
13hakta added a commit that referenced this pull request Jun 17, 2018
Remove unneeded cpu port property, update external interface init
according to mapped ports for RTL8267RB:
ext port #1 = extif0
ext port lede-project#2 = extif1

Signed-off-by: Vitaly Chekryzhev <[email protected]>
13hakta added a commit that referenced this pull request Jun 17, 2018
Driver supports 2 chip versions: RTL8367RB, RTL8367R-VB. Each of them has 2 external ports.
RTL8367RB has ports indexed as #1,lede-project#2 (PHY lede-project#6, lede-project#7).
RTL8367R-VB has ports indexed as #0,#1 (PHY lede-project#5,lede-project#6).
Map ports so that extif0 complies to external port 0 or 1 depending on chip ID.

Signed-off-by: Vitaly Chekryzhev <[email protected]>
13hakta added a commit that referenced this pull request Jun 17, 2018
Remove unneeded cpu port property, update external interface init
according to mapped ports for RTL8267RB:
ext port #1 = extif0
ext port lede-project#2 = extif1

Signed-off-by: Vitaly Chekryzhev <[email protected]>
13hakta added a commit that referenced this pull request Jun 18, 2018
Remove unneeded cpu port property, update external interface init
according to mapped ports for RTL8267RB:
ext port #1 = extif0
ext port lede-project#2 = extif1

Signed-off-by: Vitaly Chekryzhev <[email protected]>
13hakta added a commit that referenced this pull request Jun 18, 2018
Driver supports 2 chip versions: RTL8367RB, RTL8367R-VB. Each of them has 2 external ports.
RTL8367RB has ports indexed as #1,lede-project#2 (PHY lede-project#6, lede-project#7).
RTL8367R-VB has ports indexed as #0,#1 (PHY lede-project#5,lede-project#6).
Map ports so that extif0 complies to external port 0 or 1 depending on chip ID.

Signed-off-by: Vitaly Chekryzhev <[email protected]>
13hakta added a commit that referenced this pull request Jun 18, 2018
Remove unneeded cpu port property, update external interface init
according to mapped ports for RTL8267RB:
ext port #1 = extif0
ext port lede-project#2 = extif1

Signed-off-by: Vitaly Chekryzhev <[email protected]>
13hakta added a commit that referenced this pull request Jun 18, 2018
Driver supports 2 chip versions: RTL8367RB, RTL8367R-VB. Each of them has 2 external ports.
RTL8367RB has ports indexed as #1,lede-project#2 (PHY lede-project#6, lede-project#7).
RTL8367R-VB has ports indexed as #0,#1 (PHY lede-project#5,lede-project#6).
Map ports so that extif0 complies to external port 0 or 1 depending on chip ID.

Signed-off-by: Vitaly Chekryzhev <[email protected]>
13hakta added a commit that referenced this pull request Jun 18, 2018
Remove unneeded cpu port property, update external interface init
according to mapped ports for RTL8267RB:
ext port #1 = extif0
ext port lede-project#2 = extif1

Signed-off-by: Vitaly Chekryzhev <[email protected]>
13hakta added a commit that referenced this pull request Jun 19, 2018
Update external interface init according to mapped ports for RTL8367RB:
ext port #1 = extif0
ext port lede-project#2 = extif1

Signed-off-by: Vitaly Chekryzhev <[email protected]>
13hakta added a commit that referenced this pull request Jun 19, 2018
Driver supports 2 chip versions: RTL8367RB, RTL8367R-VB. Each of them has 2 external ports.
RTL8367RB has ports indexed as #1,lede-project#2 (PHY lede-project#6, lede-project#7).
RTL8367R-VB has ports indexed as #0,#1 (PHY lede-project#5,lede-project#6).
Map ports so that extif0 complies to external port 0 or 1 depending on chip ID.

Signed-off-by: Vitaly Chekryzhev <[email protected]>
13hakta added a commit that referenced this pull request Jun 19, 2018
Driver supports 2 chip versions: RTL8367RB, RTL8367R-VB. Each of them has 2 external ports.
RTL8367RB has ports indexed as #1,lede-project#2 (PHY lede-project#6, lede-project#7).
RTL8367R-VB has ports indexed as #0,#1 (PHY lede-project#5,lede-project#6).
Map ports so that extif0 complies to external port 0 or 1 depending on chip ID.

Signed-off-by: Vitaly Chekryzhev <[email protected]>
13hakta added a commit that referenced this pull request Jun 25, 2018
Update external interface init according to mapped ports for RTL8367RB:
ext port #1 = extif0
ext port lede-project#2 = extif1

Signed-off-by: Vitaly Chekryzhev <[email protected]>
13hakta added a commit that referenced this pull request Jun 25, 2018
Driver supports 2 chip versions: RTL8367RB, RTL8367R-VB. Each of them has 2 external ports.
RTL8367RB has ports indexed as #1,lede-project#2 (PHY lede-project#6, lede-project#7).
RTL8367R-VB has ports indexed as #0,#1 (PHY lede-project#5,lede-project#6).
Map ports so that extif0 complies to external port 0 or 1 depending on chip ID.

Signed-off-by: Vitaly Chekryzhev <[email protected]>
Sign up for free to subscribe to this conversation on GitHub. Already have an account? Sign in.
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

2 participants