This repository contains the Verilog implementation of a single-cycle processor. The goal is to bridge the gap between academic understanding and practical execution, following the RISC philosophy.
This processor supports R, I, and J type instructions as outlined in the MIPS architecture. The design has been inspired by the concepts discussed in the book "Digital Design and Computer Architecture" by David Money Harris & Sarah L. Harris (Pages 368-380).
- Quartus Prime Lite Edition
The processor components have been organized into different modules, each specified in its own Verilog file. To make it more user-friendly, the following steps can be followed to generate the Symbol files for each component:
1. Open the Verilog source file for a specific component in Quartus Prime.
2. For each component, go to File -> Create/Update -> Create Symbol Files (.bsf).
Creating Symbol Files
For better usability, it's recommended to generate Symbol files (.bsf) for each component in your Verilog source. Symbol files provide a graphical representation of the module, making it easier to understand the design hierarchy.
Follow these steps to create Symbol files for each component:
1. Open Quartus Prime and navigate to the project.
2. For each Verilog source file, open the file in Quartus Prime.
3. Once the file is open, go to File -> Create/Update -> Create Symbol Files (.bsf).
Feel free to explore the Verilog source code, testbenches, and documentation for more detailed insights.
This project is licensed under the Apache License 2.0 - see the LICENSE file for details.