Add Upduino board support

FemtoRV/BOARDS/upduino.mk

@@ -0,0 +1,30 @@
+YOSYS_UPDUINO_OPT=-DICE_BREAKER -q -p "synth_ice40 -abc9 -device u -dsp -top $(PROJECTNAME) -json $(PROJECTNAME).json"
+NEXTPNR_UPDUINO_OPT=--force --json $(PROJECTNAME).json --pcf BOARDS/upduino.pcf --asc $(PROJECTNAME).asc \
+                     --freq 12 --up5k --package sg48 --opt-timing
+
+#######################################################################################################################
+
+UPDUINO: UPDUINO.firmware_config UPDUINO.synth UPDUINO.prog
+
+UPDUINO.synth: 
+	yosys $(YOSYS_UPDUINO_OPT) $(VERILOGS)
+	nextpnr-ice40 $(NEXTPNR_UPDUINO_OPT)
+	icetime -p BOARDS/upduino.pcf -P sg48 -r $(PROJECTNAME).timings -d up5k -t $(PROJECTNAME).asc 
+	icepack -s $(PROJECTNAME).asc $(PROJECTNAME).bin
+
+UPDUINO.show: 
+	yosys $(YOSYS_UPDUINO_OPT) $(VERILOGS)
+	nextpnr-ice40 $(NEXTPNR_UPDUINO_OPT) --gui
+
+UPDUINO.prog:
+	iceprog $(PROJECTNAME).bin
+
+UPDUINO.firmware_config:
+	BOARD=upduino TOOLS/make_config.sh -DICE_BREAKER
+	(cd FIRMWARE; make libs)
+
+UPDUINO.lint:
+	verilator -DICE_BREAKER -DBENCH --lint-only --top-module $(PROJECTNAME) \
+         -IRTL -IRTL/PROCESSOR -IRTL/DEVICES -IRTL/PLL $(VERILOGS)
+
+#######################################################################################################################

FemtoRV/BOARDS/upduino.pcf

@@ -0,0 +1,115 @@
+# Taken from https://github.com/tinyvision-ai-inc/UPduino-v3.0/blob/master/RTL/common/upduino.pcf
+# Pinout Layout: https://upduino.readthedocs.io/en/latest/features/specs.html
+# To be used as a reference
+
+# The LED pins are on dedicated pins and cannot be modified!
+# Note that they are negative logic (write a 0 to turn on).
+# These are also brought out to the left side of the board. 
+# Cut the board trace on jumper R28 to disable the onboard 3 color LED.
+#set_io -nowarn led_green 39
+#set_io -nowarn led_red	41
+#set_io -nowarn led_blue	40
+
+# FTDI chip interface
+#set_io -nowarn serial_txd 14 # FPGA transmit to USB
+#set_io -nowarn serial_rxd 15 # FPGA receive from USB
+#set_io -nowarn spi_cs 16 # Connected to SPI flash, drive high unless using SPI flash!
+
+# If using the FTDI MPSSE engine, the following signals apply
+#set_io -nowarn spi_sck 15  # Shared with the flash
+#set_io -nowarn spi_ssn 16  # Connected to SPI flash, drive high unless using SPI flash!
+#set_io -nowarn spi_mosi 17 # Shared with the flash
+#set_io -nowarn spi_miso 14 # Shared with the flash
+
+# Normal GPIO pins, left side
+#set_io -nowarn gpio_23 23
+#set_io -nowarn gpio_25 25
+#set_io -nowarn gpio_26 26
+#set_io -nowarn gpio_27 27
+#set_io -nowarn gpio_32 32
+#set_io -nowarn gpio_35 35
+#set_io -nowarn gpio_31 31
+#set_io -nowarn gpio_37 37
+#set_io -nowarn gpio_34 34
+#set_io -nowarn gpio_43 43
+#set_io -nowarn gpio_36 36
+#set_io -nowarn gpio_42 42
+#set_io -nowarn gpio_38 38
+#set_io -nowarn gpio_28 28
+
+# Normal GPIO pins, right side
+
+# Following pins are added on the v3.0 of the board.
+# SPI pins are brought out to the right side of the board
+
+# Note: On board 12MHz clock can be brought to IOB_25B_G3 (pin 20) which is a global
+# clock input. Short across R16 (labelled OSC on the board) to enable 12MHz clock to
+# pin 20.
+#set_io -nowarn gpio_20 20
+#set_io -nowarn gpio_10 10
+
+# Following are also found on v2.x of the UPduino
+#set_io -nowarn gpio_12 12
+#set_io -nowarn gpio_21 21
+#set_io -nowarn gpio_13 13
+#set_io -nowarn gpio_19 19
+#set_io -nowarn gpio_18 18
+#set_io -nowarn gpio_11 11
+#set_io -nowarn gpio_9 9
+#set_io -nowarn gpio_6 6
+#set_io -nowarn gpio_44 44
+#set_io -nowarn gpio_4 4
+#set_io -nowarn gpio_3 3
+#set_io -nowarn gpio_48 48
+#set_io -nowarn gpio_45 45
+#set_io -nowarn gpio_47 47
+#set_io -nowarn gpio_46 46
+#set_io -nowarn gpio_2 2
+
+
+# FemtoRV Config Starts Here
+# 20 is the 12Mhz input but 35 I guess is the internal PLL?
+#set_io pclk 20
+set_io pclk 		35	# ??
+
+# USB (I think)
+set_io TXD 			14
+set_io RXD 			15
+
+set_io RESET 		38	# ??
+
+# Left Side of Upduino
+set_io D1 			39	# Green LED Physical Pin 5
+set_io D2 			41	# Red LED Physical Pin 6
+set_io D3 			40	# Blue LED Physical Pin 7
+set_io D4 			23	# Physical Pin 11
+set_io D5 			25	# Physical Pin 12
+
+# LED Matrix
+set_io ledmtx_DIN	26	# Physical Pin 13
+set_io ledmtx_CS	27	# Physical Pin 14 
+set_io ledmtx_CLK	32	# Physical Pin 15  
+
+# OLED Display
+set_io oled_DIN		31	# Physical Pin 17
+set_io oled_CLK		37	# Physical Pin 18
+set_io oled_CS		34	# Physical Pin 19
+set_io oled_DC		43	# Physical Pin 20
+set_io oled_RST		36	# Physical Pin 21
+
+# Right Side of Upduino
+set_io spi_io0		2	# Physical Pin 25
+set_io spi_io1		46	# Physical Pin 26
+set_io spi_io2		47	# Physical Pin 27
+set_io spi_io3		45	# Physical Pin 28
+
+set_io spi_clk		44	# Physical Pin 32
+set_io spi_cs_n		6	# Physical Pin 33
+set_io spi_miso		9	# Physical Pin 34, Not sure which is which
+set_io spi_mosi		11	# Physical Pin 35, Not sure which is which
+
+
+
+
+
+

FemtoRV/Makefile

@@ -16,6 +16,7 @@ include BOARDS/ecp5_evn.mk
 #include BOARDS/arty35_symbiflow.mk
 include BOARDS/arty35_yosys_nextpnr.mk
 include BOARDS/cmod_a7_yosys_nextpnr.mk
+include BOARDS/upduino.mk
 
 
 .PHONY: all clean terminal testbench 

FemtoRV/RTL/CONFIGS/upduino_config.v

@@ -0,0 +1,47 @@
+// Default femtosoc configuration file for IceStick
+
+`define NRV_NEGATIVE_RESET
+/************************* Devices **********************************************************************************/
+
+//`define NRV_IO_LEDS      // Mapped IO, LEDs D1,D2,D3,D4 (D5 is used to display errors)
+`define NRV_IO_UART      // Mapped IO, virtual UART (USB)
+//`define NRV_IO_SSD1351   // Mapped IO, 128x128x64K OLed screen
+//`define NRV_IO_MAX7219   // Mapped IO, 8x8 led matrix
+`define NRV_MAPPED_SPI_FLASH // SPI flash mapped in address space. Can be used with MINIRV32 to run code from SPI flash.
+
+/************************* Processor configuration ******************************************************************/
+
+//`define NRV_FEMTORV32_QUARK_BICYCLE // RV32I 
+//`define NRV_FEMTORV32_ELECTRON      // RV32IM
+//`define NRV_FEMTORV32_INTERMISSUM   // RV32IM  + IRQ
+`define NRV_FEMTORV32_GRACILIS      // RV32IMC + IRQ
+//`define NRV_FEMTORV32_PETITBATEAU     // RV32IMFC + IRQ, does not fit on IceBreaker
+
+//`define NRV_FREQ 20                 // Frequency in MHz. Recomm: 15 MHz   Overclocking: 20-25 MHz
+//`define NRV_FREQ 15                 // Frequency in MHz. Recomm: 15 MHz   Overclocking: 20-25 MHz
+`define NRV_RESET_ADDR 32'h00820000 // Jump execution to SPI Flash (800000h, +128k(20000h) for FPGA bitstream)
+// tinyraytracer: 30 MHz RV32IM  electron 3:12
+//                20 MHz RV32IM  gracilis 3:44
+//                20 MHz RV32IMC gracilis 3:32
+//                25 MHz RV32IMC gracilis 2:49
+
+/************************* RAM (in bytes, needs to be a multiple of 4)***********************************************/
+
+// Using the 128 kbytes of single-ported RAM of the ice40-up5k
+// Note: cannot initialize it from .hex file, need to run from SPI Flash
+
+`define ICE40UP5K_SPRAM
+`define NRV_RAM 131072 
+
+// (other option, the 12 kbytes of BRAM, this one can be initialized from .hex file).
+//`define NRV_RAM 12288
+
+/************************* Advanced devices configuration *********************************************************/
+
+`define NRV_RUN_FROM_SPI_FLASH // Do not 'readmemh()' firmware from '.hex' file
+`define NRV_IO_HARDWARE_CONFIG // Comment-out to disable hardware config registers mapped in IO-Space
+                               // (only if you use your own firmware, libfemtorv32 depends on it)
+
+/******************************************************************************************************************/
+
+`define NRV_CONFIGURED