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Fix decode of CHERI instructions following upstream change to decode …
…hook. riscv/sail-riscv#205 changed the way decode hooks used to override existing RISC-V instructions work. This commit imports changes from upstream to adapt to the change. Relevant commit: CTSRD-CHERI/sail-cheri-riscv@d760e53
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,71 @@ | ||
| /*=======================================================================================*/ | ||
| /* CHERI RISCV Sail Model */ | ||
| /* */ | ||
| /* This CHERI Sail RISC-V architecture model here, comprising all files and */ | ||
| /* directories except for the snapshots of the Lem and Sail libraries in the */ | ||
| /* prover_snapshots directory (which include copies of their licenses), is subject */ | ||
| /* to the BSD two-clause licence below. */ | ||
| /* */ | ||
| /* Copyright (c) 2017-2021 */ | ||
| /* Alasdair Armstrong */ | ||
| /* Thomas Bauereiss */ | ||
| /* Brian Campbell */ | ||
| /* Jessica Clarke */ | ||
| /* Nathaniel Wesley Filardo (contributions prior to July 2020, thereafter Microsoft) */ | ||
| /* Alexandre Joannou */ | ||
| /* Microsoft */ | ||
| /* Prashanth Mundkur */ | ||
| /* Robert Norton-Wright (contributions prior to March 2020, thereafter Microsoft) */ | ||
| /* Alexander Richardson */ | ||
| /* Peter Rugg */ | ||
| /* Peter Sewell */ | ||
| /* */ | ||
| /* All rights reserved. */ | ||
| /* */ | ||
| /* This software was developed by SRI International and the University of */ | ||
| /* Cambridge Computer Laboratory (Department of Computer Science and */ | ||
| /* Technology) under DARPA/AFRL contract FA8650-18-C-7809 ("CIFV"), and */ | ||
| /* under DARPA contract HR0011-18-C-0016 ("ECATS") as part of the DARPA */ | ||
| /* SSITH research programme. */ | ||
| /* */ | ||
| /* This software was developed within the Rigorous Engineering of */ | ||
| /* Mainstream Systems (REMS) project, partly funded by EPSRC grant */ | ||
| /* EP/K008528/1, at the Universities of Cambridge and Edinburgh. */ | ||
| /* */ | ||
| /* This project has received funding from the European Research Council */ | ||
| /* (ERC) under the European Union’s Horizon 2020 research and innovation */ | ||
| /* programme (grant agreement 789108, ELVER). */ | ||
| /* */ | ||
| /* Redistribution and use in source and binary forms, with or without */ | ||
| /* modification, are permitted provided that the following conditions */ | ||
| /* are met: */ | ||
| /* 1. Redistributions of source code must retain the above copyright */ | ||
| /* notice, this list of conditions and the following disclaimer. */ | ||
| /* 2. Redistributions in binary form must reproduce the above copyright */ | ||
| /* notice, this list of conditions and the following disclaimer in */ | ||
| /* the documentation and/or other materials provided with the */ | ||
| /* distribution. */ | ||
| /* */ | ||
| /* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' */ | ||
| /* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED */ | ||
| /* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A */ | ||
| /* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR */ | ||
| /* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ | ||
| /* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ | ||
| /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF */ | ||
| /* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND */ | ||
| /* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, */ | ||
| /* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */ | ||
| /* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF */ | ||
| /* SUCH DAMAGE. */ | ||
| /*=======================================================================================*/ | ||
|
|
||
| /* | ||
| * We add a separate capability-mode encdec clause to handle encodings that overlap | ||
| * with baseline RISC-V encodings. | ||
| */ | ||
| val encdec_capmode : ast <-> bits(32) effect {rreg} | ||
| scattered mapping encdec_capmode | ||
|
|
||
| val encdec_compressed_capmode : ast <-> bits(16) effect {rreg} | ||
| scattered mapping encdec_compressed_capmode |
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