Move to CHERIoT-platform submodule and catch up with upstream changes

[nwf-msr]

When reviewing, you'll probably want to also look at the changes in the submodule relative to upstream, CHERIoT-Platform/sail-riscv@main...CHERIoT-Platform:sail-riscv:cheriot-submodule, and/or the upstream changes included herein, CHERIoT-Platform/sail-riscv@6d0cc0f...CHERIoT-Platform:sail-riscv:main .

At least locally, with sail mainline, this commit builds both the csim and rvfi targets.

[davidchisnall]

Looks good to me, one place where even more things can be deleted (yay for deleting things!).

[rmn30]

This looks good but I was expecting to see some changes to adjust to CHERIoT-Platform/sail-riscv@9547a30 . Upstream made these changes: CTSRD-CHERI/sail-cheri-riscv@dab72aa . I must be missing something.

[rmn30]

Indeed, I've tested and the simulator builds but doesn't use CHERI instructions correctly. Will investigate.

[rmn30]

Replacing cheri_decode_ext.sail with the following and removing riscv_decode_ext.sail in the Makefile is sufficient to get a working simulator but is not optimal as we still get incorrect disassembly for compressed instructions. I will think about a solution more similar to upstream.

val ext_decode_compressed : bits(16) -> ast
function ext_decode_compressed(bv) = {
  let ast = encdec_compressed(bv);
  match ast {
    C_JAL(imm) => CJAL(sign_extend(imm @ 0b0), ra),
    C_JALR(rs1) => CJALR(zero_extend(0b0), rs1, ra),
    C_J(imm) => CJAL(sign_extend(imm @ 0b0), zreg),
    C_JR(rs1) => CJALR(zero_extend(0b0), rs1, zreg),
    C_MV(rd, 0b1 @ rs2 : bits(4)) => CMove(rd, 0b0 @ rs2),
    C_ADDI4SPN(rdc, nzimm) => CIncAddrImmediate(creg2reg_idx(rdc), sp, zero_extend(nzimm @ 0b00)),
    C_ADDI16SP(imm) => CIncAddrImmediate(sp, sp, sign_extend(imm @ 0x0)),
    OTHER => OTHER
  }
}

val ext_decode : bits(32) -> ast
function ext_decode(bv) = {
  let ast = encdec(bv);
  match ast {
    UTYPE(imm, 0b0 @ cd : bits(4), RISCV_AUIPC) => AUIPCC(imm, 0b0 @ cd),
    RISCV_JAL(imm, cd) => CJAL(imm, cd),
    RISCV_JALR(imm, cs1, cd) => CJALR(imm, cs1, cd),
    OTHER => OTHER
  }
}

[rmn30]

I have just pushed a branch that extends this PR to fix decode. @nwf would you like to incorporate that commit into this PR?

[nwf-msr]

Thanks @rmn30; I'd completely missed that. With your change added, the CHERIoT RTOS test suite passes for both release and test builds.