Remove bounds checks on jumps / branch. Simplify and clarify MEPCC an…

[rmn30]

…d MTCC behaviour.

As per #23 we want to delay the bounds check on jumps / branches until instruction fetch in order to simplify hardware. Due to this potentially leading to unrepresentable MEPCC values we also clear the tag of MEPCC on instruction fetch bounds violations. Due to this this got a bit mixed up with #30 which clarifies and simplifies validation and legalization of MEPCC / MTCC.

[rmn30]

Some less immediately obvious changes:

• Due to MEPCC / MTCC validation we can remove the check for sealed or non-executable PCC on instruction fetch. We only need tag and bounds checks. Untagged can only happen on mret with untagged MEPC or exception with untagged MTCC.
• We don't support sealed-as-sentry MEPCC which was previously implemented in Sail but not mentioned in the ISA doc. I don't think there's a use for this and it gets complicated with mepc legalisation, interrupt disable / enable etc.
• We clear MEPCC tag on any instruction fetch bounds failure even if MEPCC would have be representable. This simplifies hardware and the ISA vs current behaviour of preserving tag whenever possible (requiring representability check).
• We're explicitly not supporting vectored interrupt mode. We decided it actually wasn't very useful. I could add it back if we decide we want it...

[kliuMsft]

Looks good to me.

[vmurali]

PTAL at #23 (comment) and #23 (comment). I think this PR is wrong.