UART.rdf

<?xml version="1.0" encoding="UTF-8"?>
<RadiantProject version="4.1" title="UART" device="iCE40UP5K-SG48I" performance_grade="High-Performance_1.2V" default_implementation="impl_1">
    <Options/>
    <Implementation title="impl_1" dir="impl_1" description="impl_1" synthesis="lse" default_strategy="Strategy1">
        <Options def_top="main"/>
        <Source name="../uart_recv.sv" type="Verilog" type_short="Verilog">
            <Options VerilogStandard="System Verilog"/>
        </Source>
        <Source name="../uart_send.sv" type="Verilog" type_short="Verilog">
            <Options VerilogStandard="System Verilog"/>
        </Source>
        <Source name="source/impl_1/main.sv" type="Verilog" type_short="Verilog">
            <Options VerilogStandard="System Verilog" top_module="main"/>
        </Source>
    </Implementation>
    <Strategy name="Strategy1" file="UART1.sty"/>
</RadiantProject>