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Fix incorrect PLL1 VCO selection
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Signed-off-by: Akhil Velagapudi <[email protected]>
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akhilles authored and David-OConnor committed Jan 9, 2025
1 parent 42e9386 commit a728825
Showing 1 changed file with 3 additions and 2 deletions.
5 changes: 3 additions & 2 deletions src/clocks/h.rs
Original file line number Diff line number Diff line change
Expand Up @@ -742,8 +742,9 @@ impl Clocks {
// 0: Wide VCO range: 192 to 836 MHz (default after reset)
// 1: Medium VCO range: 150 to 420 MHz
let pll1_vco = match self.pll_input_speed(self.pll_src, 1) {
0..=2_000_000 => 0,
_ => 1,
1_000_000..=2_000_000 => 1,
2_000_001..=16_000_000 => 0,
_ => panic!("PLL1 input source must be between 1Mhz and 16Mhz."),
};

// The user application can then configure the proper VCO: if the frequency of the reference
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