verilog实现TPU中的脉动阵列计算卷积的module
data为实验数据
source为源码
testbench 测试各个模块用的testbench
data-preprocessing 原本是要写将卷积操作用python预先imtocol操作的，但后来直接使用matlab生成数据进行测试了
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Dazhuzhu-github/systolic-array
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verilog实现TPU中的脉动阵列计算卷积的module
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